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Merge remote-tracking branch 'md/for-next'
[deliverable/linux.git] / drivers / gpu / drm / tilcdc / tilcdc_drv.c
CommitLineData
16ea975e
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/* LCDC DRM driver, based on da8xx-fb */
19
103cd8bc 20#include <linux/component.h>
416a07fb
DG		 21#include <linux/pinctrl/consumer.h>
22#include <linux/suspend.h>
edc43303
JS		 23#include <drm/drm_atomic.h>
24#include <drm/drm_atomic_helper.h>
103cd8bc 25
16ea975e
RC		 26#include "tilcdc_drv.h"
27#include "tilcdc_regs.h"
28#include "tilcdc_tfp410.h"
0d4bbaf9 29#include "tilcdc_panel.h"
103cd8bc 30#include "tilcdc_external.h"
16ea975e
RC		 31
32#include "drm_fb_helper.h"
33
34static LIST_HEAD(module_list);
35
bcc5a6f5
JS		 36static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
37
38static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
39 DRM_FORMAT_BGR888,
40 DRM_FORMAT_XBGR8888 };
41
42static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
43 DRM_FORMAT_RGB888,
44 DRM_FORMAT_XRGB8888 };
45
46static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
47 DRM_FORMAT_RGB888,
48 DRM_FORMAT_XRGB8888 };
49
16ea975e
RC		 50void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
51 const struct tilcdc_module_ops *funcs)
52{
53 mod->name = name;
54 mod->funcs = funcs;
55 INIT_LIST_HEAD(&mod->list);
56 list_add(&mod->list, &module_list);
57}
58
59void tilcdc_module_cleanup(struct tilcdc_module *mod)
60{
61 list_del(&mod->list);
62}
63
64static struct of_device_id tilcdc_of_match[];
65
66static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
1eb83451 67 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
16ea975e
RC		 68{
69 return drm_fb_cma_create(dev, file_priv, mode_cmd);
70}
71
72static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
73{
74 struct tilcdc_drm_private *priv = dev->dev_private;
c0844817 75 drm_fbdev_cma_hotplug_event(priv->fbdev);
16ea975e
RC		 76}
77
edc43303
JS		 78int tilcdc_atomic_check(struct drm_device *dev,
79 struct drm_atomic_state *state)
80{
81 int ret;
82
83 ret = drm_atomic_helper_check_modeset(dev, state);
84 if (ret)
85 return ret;
86
87 ret = drm_atomic_helper_check_planes(dev, state);
88 if (ret)
89 return ret;
90
91 /*
92 * tilcdc ->atomic_check can update ->mode_changed if pixel format
93 * changes, hence will we check modeset changes again.
94 */
95 ret = drm_atomic_helper_check_modeset(dev, state);
96 if (ret)
97 return ret;
98
99 return ret;
100}
101
102static int tilcdc_commit(struct drm_device *dev,
103 struct drm_atomic_state *state,
104 bool async)
105{
106 int ret;
107
108 ret = drm_atomic_helper_prepare_planes(dev, state);
109 if (ret)
110 return ret;
111
112 drm_atomic_helper_swap_state(state, true);
113
114 /*
115 * Everything below can be run asynchronously without the need to grab
116 * any modeset locks at all under one condition: It must be guaranteed
117 * that the asynchronous work has either been cancelled (if the driver
118 * supports it, which at least requires that the framebuffers get
119 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
120 * before the new state gets committed on the software side with
121 * drm_atomic_helper_swap_state().
122 *
123 * This scheme allows new atomic state updates to be prepared and
124 * checked in parallel to the asynchronous completion of the previous
125 * update. Which is important since compositors need to figure out the
126 * composition of the next frame right after having submitted the
127 * current layout.
128 */
129
47bfd6c0
JS		 130 /* Keep HW on while we commit the state. */
131 pm_runtime_get_sync(dev->dev);
132
edc43303
JS		 133 drm_atomic_helper_commit_modeset_disables(dev, state);
134
2b58e98d 135 drm_atomic_helper_commit_planes(dev, state, 0);
edc43303
JS		 136
137 drm_atomic_helper_commit_modeset_enables(dev, state);
138
47bfd6c0
JS		 139 /* Now HW should remain on if need becase the crtc is enabled */
140 pm_runtime_put_sync(dev->dev);
141
edc43303
JS		 142 drm_atomic_helper_wait_for_vblanks(dev, state);
143
144 drm_atomic_helper_cleanup_planes(dev, state);
145
146 drm_atomic_state_free(state);
147
148 return 0;
149}
150
16ea975e
RC		 151static const struct drm_mode_config_funcs mode_config_funcs = {
152 .fb_create = tilcdc_fb_create,
153 .output_poll_changed = tilcdc_fb_output_poll_changed,
edc43303
JS		 154 .atomic_check = tilcdc_atomic_check,
155 .atomic_commit = tilcdc_commit,
16ea975e
RC		 156};
157
158static int modeset_init(struct drm_device *dev)
159{
160 struct tilcdc_drm_private *priv = dev->dev_private;
161 struct tilcdc_module *mod;
162
163 drm_mode_config_init(dev);
164
165 priv->crtc = tilcdc_crtc_create(dev);
166
167 list_for_each_entry(mod, &module_list, list) {
168 DBG("loading module: %s", mod->name);
169 mod->funcs->modeset_init(mod, dev);
170 }
171
16ea975e
RC		 172 dev->mode_config.min_width = 0;
173 dev->mode_config.min_height = 0;
174 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
175 dev->mode_config.max_height = 2048;
176 dev->mode_config.funcs = &mode_config_funcs;
177
178 return 0;
179}
180
181#ifdef CONFIG_CPU_FREQ
182static int cpufreq_transition(struct notifier_block *nb,
183 unsigned long val, void *data)
184{
185 struct tilcdc_drm_private *priv = container_of(nb,
186 struct tilcdc_drm_private, freq_transition);
187 if (val == CPUFREQ_POSTCHANGE) {
188 if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
189 priv->lcd_fck_rate = clk_get_rate(priv->clk);
190 tilcdc_crtc_update_clk(priv->crtc);
191 }
192 }
193
194 return 0;
195}
196#endif
197
198/*
199 * DRM operations:
200 */
201
202static int tilcdc_unload(struct drm_device *dev)
203{
204 struct tilcdc_drm_private *priv = dev->dev_private;
16ea975e 205
47bfd6c0 206 tilcdc_crtc_disable(priv->crtc);
1aea1e79 207
103cd8bc
JS		 208 tilcdc_remove_external_encoders(dev);
209
3a490122 210 drm_fbdev_cma_fini(priv->fbdev);
16ea975e
RC		 211 drm_kms_helper_poll_fini(dev);
212 drm_mode_config_cleanup(dev);
213 drm_vblank_cleanup(dev);
214
16ea975e 215 drm_irq_uninstall(dev);
16ea975e
RC		 216
217#ifdef CONFIG_CPU_FREQ
218 cpufreq_unregister_notifier(&priv->freq_transition,
219 CPUFREQ_TRANSITION_NOTIFIER);
220#endif
221
222 if (priv->clk)
223 clk_put(priv->clk);
224
225 if (priv->mmio)
226 iounmap(priv->mmio);
227
228 flush_workqueue(priv->wq);
229 destroy_workqueue(priv->wq);
230
231 dev->dev_private = NULL;
232
233 pm_runtime_disable(dev->dev);
234
16ea975e
RC		 235 return 0;
236}
237
238static int tilcdc_load(struct drm_device *dev, unsigned long flags)
239{
240 struct platform_device *pdev = dev->platformdev;
241 struct device_node *node = pdev->dev.of_node;
242 struct tilcdc_drm_private *priv;
243 struct resource *res;
dc28aa07 244 u32 bpp = 0;
16ea975e
RC		 245 int ret;
246
d0ec32ca 247 priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
514d1a1f 248 if (!priv) {
16ea975e
RC		 249 dev_err(dev->dev, "failed to allocate private data\n");
250 return -ENOMEM;
251 }
252
253 dev->dev_private = priv;
254
103cd8bc
JS		 255 priv->is_componentized =
256 tilcdc_get_external_components(dev->dev, NULL) > 0;
257
16ea975e 258 priv->wq = alloc_ordered_workqueue("tilcdc", 0);
b478e336
EG		 259 if (!priv->wq) {
260 ret = -ENOMEM;
d0ec32ca 261 goto fail_unset_priv;
b478e336 262 }
16ea975e
RC		 263
264 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265 if (!res) {
266 dev_err(dev->dev, "failed to get memory resource\n");
267 ret = -EINVAL;
b478e336 268 goto fail_free_wq;
16ea975e
RC		 269 }
270
271 priv->mmio = ioremap_nocache(res->start, resource_size(res));
272 if (!priv->mmio) {
273 dev_err(dev->dev, "failed to ioremap\n");
274 ret = -ENOMEM;
b478e336 275 goto fail_free_wq;
16ea975e
RC		 276 }
277
278 priv->clk = clk_get(dev->dev, "fck");
279 if (IS_ERR(priv->clk)) {
280 dev_err(dev->dev, "failed to get functional clock\n");
281 ret = -ENODEV;
b478e336 282 goto fail_iounmap;
16ea975e
RC		 283 }
284
16ea975e
RC		 285#ifdef CONFIG_CPU_FREQ
286 priv->lcd_fck_rate = clk_get_rate(priv->clk);
287 priv->freq_transition.notifier_call = cpufreq_transition;
288 ret = cpufreq_register_notifier(&priv->freq_transition,
289 CPUFREQ_TRANSITION_NOTIFIER);
290 if (ret) {
291 dev_err(dev->dev, "failed to register cpufreq notifier\n");
3d19306a 292 goto fail_put_clk;
16ea975e
RC		 293 }
294#endif
295
296 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
4e564346
DE		 297 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
298
299 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
300
301 if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
302 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
303
304 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
305
306 if (of_property_read_u32(node, "ti,max-pixelclock",
307 &priv->max_pixelclock))
308 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
309
310 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
16ea975e
RC		 311
312 pm_runtime_enable(dev->dev);
313
314 /* Determine LCD IP Version */
315 pm_runtime_get_sync(dev->dev);
316 switch (tilcdc_read(dev, LCDC_PID_REG)) {
317 case 0x4c100102:
318 priv->rev = 1;
319 break;
320 case 0x4f200800:
321 case 0x4f201000:
322 priv->rev = 2;
323 break;
324 default:
325 dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
326 "defaulting to LCD revision 1\n",
327 tilcdc_read(dev, LCDC_PID_REG));
328 priv->rev = 1;
329 break;
330 }
331
332 pm_runtime_put_sync(dev->dev);
333
bcc5a6f5
JS		 334 if (priv->rev == 1) {
335 DBG("Revision 1 LCDC supports only RGB565 format");
336 priv->pixelformats = tilcdc_rev1_formats;
337 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
c5665385 338 bpp = 16;
bcc5a6f5
JS		 339 } else {
340 const char *str = "\0";
341
342 of_property_read_string(node, "blue-and-red-wiring", &str);
343 if (0 == strcmp(str, "crossed")) {
344 DBG("Configured for crossed blue and red wires");
345 priv->pixelformats = tilcdc_crossed_formats;
346 priv->num_pixelformats =
347 ARRAY_SIZE(tilcdc_crossed_formats);
c5665385 348 bpp = 32; /* Choose bpp with RGB support for fbdef */
bcc5a6f5
JS		 349 } else if (0 == strcmp(str, "straight")) {
350 DBG("Configured for straight blue and red wires");
351 priv->pixelformats = tilcdc_straight_formats;
352 priv->num_pixelformats =
353 ARRAY_SIZE(tilcdc_straight_formats);
c5665385 354 bpp = 16; /* Choose bpp with RGB support for fbdef */
bcc5a6f5
JS		 355 } else {
356 DBG("Blue and red wiring '%s' unknown, use legacy mode",
357 str);
358 priv->pixelformats = tilcdc_legacy_formats;
359 priv->num_pixelformats =
360 ARRAY_SIZE(tilcdc_legacy_formats);
c5665385 361 bpp = 16; /* This is just a guess */
bcc5a6f5
JS		 362 }
363 }
364
16ea975e
RC		 365 ret = modeset_init(dev);
366 if (ret < 0) {
367 dev_err(dev->dev, "failed to initialize mode setting\n");
b478e336 368 goto fail_cpufreq_unregister;
16ea975e
RC		 369 }
370
103cd8bc
JS		 371 platform_set_drvdata(pdev, dev);
372
373 if (priv->is_componentized) {
374 ret = component_bind_all(dev->dev, dev);
375 if (ret < 0)
376 goto fail_mode_config_cleanup;
377
c5665385 378 ret = tilcdc_add_external_encoders(dev);
103cd8bc
JS		 379 if (ret < 0)
380 goto fail_component_cleanup;
381 }
382
383 if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
384 dev_err(dev->dev, "no encoders/connectors found\n");
385 ret = -ENXIO;
386 goto fail_external_cleanup;
387 }
388
16ea975e
RC		 389 ret = drm_vblank_init(dev, 1);
390 if (ret < 0) {
391 dev_err(dev->dev, "failed to initialize vblank\n");
103cd8bc 392 goto fail_external_cleanup;
16ea975e
RC		 393 }
394
bb0f1b5c 395 ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
16ea975e
RC		 396 if (ret < 0) {
397 dev_err(dev->dev, "failed to install IRQ handler\n");
b478e336 398 goto fail_vblank_cleanup;
16ea975e
RC		 399 }
400
522a76f8
JS		 401 drm_mode_config_reset(dev);
402
dc28aa07 403 priv->fbdev = drm_fbdev_cma_init(dev, bpp,
16ea975e
RC		 404 dev->mode_config.num_crtc,
405 dev->mode_config.num_connector);
b478e336
EG		 406 if (IS_ERR(priv->fbdev)) {
407 ret = PTR_ERR(priv->fbdev);
408 goto fail_irq_uninstall;
409 }
16ea975e
RC		 410
411 drm_kms_helper_poll_init(dev);
412
413 return 0;
414
b478e336 415fail_irq_uninstall:
b478e336 416 drm_irq_uninstall(dev);
b478e336
EG		 417
418fail_vblank_cleanup:
419 drm_vblank_cleanup(dev);
420
421fail_mode_config_cleanup:
422 drm_mode_config_cleanup(dev);
423
103cd8bc
JS		 424fail_component_cleanup:
425 if (priv->is_componentized)
426 component_unbind_all(dev->dev, dev);
427
428fail_external_cleanup:
429 tilcdc_remove_external_encoders(dev);
430
b478e336
EG		 431fail_cpufreq_unregister:
432 pm_runtime_disable(dev->dev);
433#ifdef CONFIG_CPU_FREQ
434 cpufreq_unregister_notifier(&priv->freq_transition,
435 CPUFREQ_TRANSITION_NOTIFIER);
b478e336
EG		 436
437fail_put_clk:
7974dff4 438#endif
b478e336
EG		 439 clk_put(priv->clk);
440
441fail_iounmap:
442 iounmap(priv->mmio);
443
444fail_free_wq:
445 flush_workqueue(priv->wq);
446 destroy_workqueue(priv->wq);
447
d0ec32ca 448fail_unset_priv:
b478e336 449 dev->dev_private = NULL;
d0ec32ca 450
16ea975e
RC		 451 return ret;
452}
453
16ea975e
RC		 454static void tilcdc_lastclose(struct drm_device *dev)
455{
456 struct tilcdc_drm_private *priv = dev->dev_private;
457 drm_fbdev_cma_restore_mode(priv->fbdev);
458}
459
e9f0d76f 460static irqreturn_t tilcdc_irq(int irq, void *arg)
16ea975e
RC		 461{
462 struct drm_device *dev = arg;
463 struct tilcdc_drm_private *priv = dev->dev_private;
464 return tilcdc_crtc_irq(priv->crtc);
465}
466
88e72717 467static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
16ea975e 468{
16ea975e
RC		 469 return 0;
470}
471
88e72717 472static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
16ea975e 473{
2b2080d7 474 return;
16ea975e
RC		 475}
476
514d1a1f 477#if defined(CONFIG_DEBUG_FS)
16ea975e
RC		 478static const struct {
479 const char *name;
480 uint8_t rev;
481 uint8_t save;
482 uint32_t reg;
32501459 483} registers[] = {
16ea975e
RC		 484#define REG(rev, save, reg) { #reg, rev, save, reg }
485 /* exists in revision 1: */
486 REG(1, false, LCDC_PID_REG),
487 REG(1, true, LCDC_CTRL_REG),
488 REG(1, false, LCDC_STAT_REG),
489 REG(1, true, LCDC_RASTER_CTRL_REG),
490 REG(1, true, LCDC_RASTER_TIMING_0_REG),
491 REG(1, true, LCDC_RASTER_TIMING_1_REG),
492 REG(1, true, LCDC_RASTER_TIMING_2_REG),
493 REG(1, true, LCDC_DMA_CTRL_REG),
494 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
495 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
496 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
497 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
498 /* new in revision 2: */
499 REG(2, false, LCDC_RAW_STAT_REG),
500 REG(2, false, LCDC_MASKED_STAT_REG),
f3a99946 501 REG(2, true, LCDC_INT_ENABLE_SET_REG),
16ea975e
RC		 502 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
503 REG(2, false, LCDC_END_OF_INT_IND_REG),
504 REG(2, true, LCDC_CLK_ENABLE_REG),
16ea975e
RC		 505#undef REG
506};
29ddd6e1 507
16ea975e
RC		 508#endif
509
510#ifdef CONFIG_DEBUG_FS
511static int tilcdc_regs_show(struct seq_file *m, void *arg)
512{
513 struct drm_info_node *node = (struct drm_info_node *) m->private;
514 struct drm_device *dev = node->minor->dev;
515 struct tilcdc_drm_private *priv = dev->dev_private;
516 unsigned i;
517
518 pm_runtime_get_sync(dev->dev);
519
520 seq_printf(m, "revision: %d\n", priv->rev);
521
522 for (i = 0; i < ARRAY_SIZE(registers); i++)
523 if (priv->rev >= registers[i].rev)
524 seq_printf(m, "%s:\t %08x\n", registers[i].name,
525 tilcdc_read(dev, registers[i].reg));
526
527 pm_runtime_put_sync(dev->dev);
528
529 return 0;
530}
531
532static int tilcdc_mm_show(struct seq_file *m, void *arg)
533{
534 struct drm_info_node *node = (struct drm_info_node *) m->private;
535 struct drm_device *dev = node->minor->dev;
b04a5906 536 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
16ea975e
RC		 537}
538
539static struct drm_info_list tilcdc_debugfs_list[] = {
540 { "regs", tilcdc_regs_show, 0 },
541 { "mm", tilcdc_mm_show, 0 },
542 { "fb", drm_fb_cma_debugfs_show, 0 },
543};
544
545static int tilcdc_debugfs_init(struct drm_minor *minor)
546{
547 struct drm_device *dev = minor->dev;
548 struct tilcdc_module *mod;
549 int ret;
550
551 ret = drm_debugfs_create_files(tilcdc_debugfs_list,
552 ARRAY_SIZE(tilcdc_debugfs_list),
553 minor->debugfs_root, minor);
554
555 list_for_each_entry(mod, &module_list, list)
556 if (mod->funcs->debugfs_init)
557 mod->funcs->debugfs_init(mod, minor);
558
559 if (ret) {
560 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
561 return ret;
562 }
563
564 return ret;
565}
566
567static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
568{
569 struct tilcdc_module *mod;
570 drm_debugfs_remove_files(tilcdc_debugfs_list,
571 ARRAY_SIZE(tilcdc_debugfs_list), minor);
572
573 list_for_each_entry(mod, &module_list, list)
574 if (mod->funcs->debugfs_cleanup)
575 mod->funcs->debugfs_cleanup(mod, minor);
576}
577#endif
578
579static const struct file_operations fops = {
580 .owner = THIS_MODULE,
581 .open = drm_open,
582 .release = drm_release,
583 .unlocked_ioctl = drm_ioctl,
584#ifdef CONFIG_COMPAT
585 .compat_ioctl = drm_compat_ioctl,
586#endif
587 .poll = drm_poll,
588 .read = drm_read,
16ea975e
RC		 589 .llseek = no_llseek,
590 .mmap = drm_gem_cma_mmap,
591};
592
593static struct drm_driver tilcdc_driver = {
9c153905 594 .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
305198de 595 DRIVER_PRIME | DRIVER_ATOMIC),
16ea975e
RC		 596 .load = tilcdc_load,
597 .unload = tilcdc_unload,
16ea975e
RC		 598 .lastclose = tilcdc_lastclose,
599 .irq_handler = tilcdc_irq,
b44f8408 600 .get_vblank_counter = drm_vblank_no_hw_counter,
16ea975e
RC		 601 .enable_vblank = tilcdc_enable_vblank,
602 .disable_vblank = tilcdc_disable_vblank,
aa0438ce 603 .gem_free_object_unlocked = drm_gem_cma_free_object,
16ea975e
RC		 604 .gem_vm_ops = &drm_gem_cma_vm_ops,
605 .dumb_create = drm_gem_cma_dumb_create,
606 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
43387b37 607 .dumb_destroy = drm_gem_dumb_destroy,
9c153905
JS		 608
609 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
610 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
611 .gem_prime_import = drm_gem_prime_import,
612 .gem_prime_export = drm_gem_prime_export,
613 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
614 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
615 .gem_prime_vmap = drm_gem_cma_prime_vmap,
616 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
617 .gem_prime_mmap = drm_gem_cma_prime_mmap,
16ea975e
RC		 618#ifdef CONFIG_DEBUG_FS
619 .debugfs_init = tilcdc_debugfs_init,
620 .debugfs_cleanup = tilcdc_debugfs_cleanup,
621#endif
622 .fops = &fops,
623 .name = "tilcdc",
624 .desc = "TI LCD Controller DRM",
625 .date = "20121205",
626 .major = 1,
627 .minor = 0,
628};
629
630/*
631 * Power management:
632 */
633
634#ifdef CONFIG_PM_SLEEP
635static int tilcdc_pm_suspend(struct device *dev)
636{
637 struct drm_device *ddev = dev_get_drvdata(dev);
638 struct tilcdc_drm_private *priv = ddev->dev_private;
16ea975e 639
514d1a1f 640 priv->saved_state = drm_atomic_helper_suspend(ddev);
16ea975e 641
85fd27f8
DE		 642 /* Select sleep pin state */
643 pinctrl_pm_select_sleep_state(dev);
644
16ea975e
RC		 645 return 0;
646}
647
648static int tilcdc_pm_resume(struct device *dev)
649{
650 struct drm_device *ddev = dev_get_drvdata(dev);
651 struct tilcdc_drm_private *priv = ddev->dev_private;
514d1a1f 652 int ret = 0;
16ea975e 653
416a07fb
DG		 654 /* Select default pin state */
655 pinctrl_pm_select_default_state(dev);
656
514d1a1f
JS		 657 if (priv->saved_state)
658 ret = drm_atomic_helper_resume(ddev, priv->saved_state);
16ea975e 659
514d1a1f 660 return ret;
16ea975e
RC		 661}
662#endif
663
664static const struct dev_pm_ops tilcdc_pm_ops = {
665 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
666};
667
668/*
669 * Platform driver:
670 */
671
103cd8bc
JS		 672static int tilcdc_bind(struct device *dev)
673{
674 return drm_platform_init(&tilcdc_driver, to_platform_device(dev));
675}
676
677static void tilcdc_unbind(struct device *dev)
678{
20a98acb
JS		 679 struct drm_device *ddev = dev_get_drvdata(dev);
680
681 /* Check if a subcomponent has already triggered the unloading. */
682 if (!ddev->dev_private)
683 return;
684
103cd8bc
JS		 685 drm_put_dev(dev_get_drvdata(dev));
686}
687
688static const struct component_master_ops tilcdc_comp_ops = {
689 .bind = tilcdc_bind,
690 .unbind = tilcdc_unbind,
691};
692
16ea975e
RC		 693static int tilcdc_pdev_probe(struct platform_device *pdev)
694{
103cd8bc
JS		 695 struct component_match *match = NULL;
696 int ret;
697
16ea975e
RC		 698 /* bail out early if no DT data: */
699 if (!pdev->dev.of_node) {
700 dev_err(&pdev->dev, "device-tree data is missing\n");
701 return -ENXIO;
702 }
703
103cd8bc
JS		 704 ret = tilcdc_get_external_components(&pdev->dev, &match);
705 if (ret < 0)
706 return ret;
707 else if (ret == 0)
708 return drm_platform_init(&tilcdc_driver, pdev);
709 else
710 return component_master_add_with_match(&pdev->dev,
711 &tilcdc_comp_ops,
712 match);
16ea975e
RC		 713}
714
715static int tilcdc_pdev_remove(struct platform_device *pdev)
716{
20a98acb 717 int ret;
103cd8bc 718
20a98acb
JS		 719 ret = tilcdc_get_external_components(&pdev->dev, NULL);
720 if (ret < 0)
721 return ret;
722 else if (ret == 0)
103cd8bc 723 drm_put_dev(platform_get_drvdata(pdev));
20a98acb
JS		 724 else
725 component_master_del(&pdev->dev, &tilcdc_comp_ops);
16ea975e
RC		 726
727 return 0;
728}
729
730static struct of_device_id tilcdc_of_match[] = {
731 { .compatible = "ti,am33xx-tilcdc", },
732 { },
733};
734MODULE_DEVICE_TABLE(of, tilcdc_of_match);
735
736static struct platform_driver tilcdc_platform_driver = {
737 .probe = tilcdc_pdev_probe,
738 .remove = tilcdc_pdev_remove,
739 .driver = {
16ea975e
RC		 740 .name = "tilcdc",
741 .pm = &tilcdc_pm_ops,
742 .of_match_table = tilcdc_of_match,
743 },
744};
745
746static int __init tilcdc_drm_init(void)
747{
748 DBG("init");
749 tilcdc_tfp410_init();
0d4bbaf9 750 tilcdc_panel_init();
16ea975e
RC		 751 return platform_driver_register(&tilcdc_platform_driver);
752}
753
754static void __exit tilcdc_drm_fini(void)
755{
756 DBG("fini");
16ea975e 757 platform_driver_unregister(&tilcdc_platform_driver);
eb565a2b 758 tilcdc_panel_fini();
eb565a2b 759 tilcdc_tfp410_fini();
16ea975e
RC		 760}
761
2023d84d 762module_init(tilcdc_drm_init);
16ea975e
RC		 763module_exit(tilcdc_drm_fini);
764
765MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
766MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
767MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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