[deliverable/linux.git] / drivers / gpu / drm / vc4 / vc4_hdmi.c

/*
 * Copyright (C) 2015 Broadcom
 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/**
 * DOC: VC4 Falcon HDMI module
 *
 * The HDMI core has a state machine and a PHY.  Most of the unit
 * operates off of the HSM clock from CPRMAN.  It also internally uses
 * the PLLH_PIX clock for the PHY.
 */

#include "drm_atomic_helper.h"
#include "drm_crtc_helper.h"
#include "drm_edid.h"
#include "linux/clk.h"
#include "linux/component.h"
#include "linux/i2c.h"
#include "linux/of_gpio.h"
#include "linux/of_platform.h"
#include "vc4_drv.h"
#include "vc4_regs.h"

/* General HDMI hardware state. */
struct vc4_hdmi {
	struct platform_device *pdev;

	struct drm_encoder *encoder;
	struct drm_connector *connector;

	struct i2c_adapter *ddc;
	void __iomem *hdmicore_regs;
	void __iomem *hd_regs;
	int hpd_gpio;
	bool hpd_active_low;

	struct clk *pixel_clock;
	struct clk *hsm_clock;
};

#define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
#define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
#define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
#define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)

/* VC4 HDMI encoder KMS struct */
struct vc4_hdmi_encoder {
	struct vc4_encoder base;
	bool hdmi_monitor;
};

static inline struct vc4_hdmi_encoder *
to_vc4_hdmi_encoder(struct drm_encoder *encoder)
{
	return container_of(encoder, struct vc4_hdmi_encoder, base.base);
}

/* VC4 HDMI connector KMS struct */
struct vc4_hdmi_connector {
	struct drm_connector base;

	/* Since the connector is attached to just the one encoder,
	 * this is the reference to it so we can do the best_encoder()
	 * hook.
	 */
	struct drm_encoder *encoder;
};

static inline struct vc4_hdmi_connector *
to_vc4_hdmi_connector(struct drm_connector *connector)
{
	return container_of(connector, struct vc4_hdmi_connector, base);
}

#define HDMI_REG(reg) { reg, #reg }
static const struct {
	u32 reg;
	const char *name;
} hdmi_regs[] = {
	HDMI_REG(VC4_HDMI_CORE_REV),
	HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
	HDMI_REG(VC4_HDMI_HOTPLUG_INT),
	HDMI_REG(VC4_HDMI_HOTPLUG),
	HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
	HDMI_REG(VC4_HDMI_HORZA),
	HDMI_REG(VC4_HDMI_HORZB),
	HDMI_REG(VC4_HDMI_FIFO_CTL),
	HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
	HDMI_REG(VC4_HDMI_VERTA0),
	HDMI_REG(VC4_HDMI_VERTA1),
	HDMI_REG(VC4_HDMI_VERTB0),
	HDMI_REG(VC4_HDMI_VERTB1),
	HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
};

static const struct {
	u32 reg;
	const char *name;
} hd_regs[] = {
	HDMI_REG(VC4_HD_M_CTL),
	HDMI_REG(VC4_HD_MAI_CTL),
	HDMI_REG(VC4_HD_VID_CTL),
	HDMI_REG(VC4_HD_CSC_CTL),
	HDMI_REG(VC4_HD_FRAME_COUNT),
};

#ifdef CONFIG_DEBUG_FS
int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	int i;

	for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
		seq_printf(m, "%s (0x%04x): 0x%08x\n",
			   hdmi_regs[i].name, hdmi_regs[i].reg,
			   HDMI_READ(hdmi_regs[i].reg));
	}

	for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
		seq_printf(m, "%s (0x%04x): 0x%08x\n",
			   hd_regs[i].name, hd_regs[i].reg,
			   HD_READ(hd_regs[i].reg));
	}

	return 0;
}
#endif /* CONFIG_DEBUG_FS */

static void vc4_hdmi_dump_regs(struct drm_device *dev)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	int i;

	for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
		DRM_INFO("0x%04x (%s): 0x%08x\n",
			 hdmi_regs[i].reg, hdmi_regs[i].name,
			 HDMI_READ(hdmi_regs[i].reg));
	}
	for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
		DRM_INFO("0x%04x (%s): 0x%08x\n",
			 hd_regs[i].reg, hd_regs[i].name,
			 HD_READ(hd_regs[i].reg));
	}
}

static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
{
	struct drm_device *dev = connector->dev;
	struct vc4_dev *vc4 = to_vc4_dev(dev);

	if (vc4->hdmi->hpd_gpio) {
		if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
		    vc4->hdmi->hpd_active_low)
			return connector_status_connected;
		else
			return connector_status_disconnected;
	}

	if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
		return connector_status_connected;
	else
		return connector_status_disconnected;
}

static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
{
	drm_connector_unregister(connector);
	drm_connector_cleanup(connector);
}

static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
{
	struct vc4_hdmi_connector *vc4_connector =
		to_vc4_hdmi_connector(connector);
	struct drm_encoder *encoder = vc4_connector->encoder;
	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
	struct drm_device *dev = connector->dev;
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	int ret = 0;
	struct edid *edid;

	edid = drm_get_edid(connector, vc4->hdmi->ddc);
	if (!edid)
		return -ENODEV;

	vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
	drm_mode_connector_update_edid_property(connector, edid);
	ret = drm_add_edid_modes(connector, edid);

	return ret;
}

/*
 * drm_helper_probe_single_connector_modes() applies drm_mode_set_crtcinfo to
 * all modes with flag CRTC_INTERLACE_HALVE_V. We don't want this, as it
 * screws up vblank timestamping for interlaced modes, so fix it up.
 */
static int vc4_hdmi_connector_probe_modes(struct drm_connector *connector,
					  uint32_t maxX, uint32_t maxY)
{
	struct drm_display_mode *mode;
	int count;

	count = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
	if (count == 0)
		return 0;

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] probed adapted modes :\n",
		      connector->base.id, connector->name);
	list_for_each_entry(mode, &connector->modes, head) {
		drm_mode_set_crtcinfo(mode, 0);
		drm_mode_debug_printmodeline(mode);
	}

	return count;
}

static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
	.dpms = drm_atomic_helper_connector_dpms,
	.detect = vc4_hdmi_connector_detect,
	.fill_modes = vc4_hdmi_connector_probe_modes,
	.destroy = vc4_hdmi_connector_destroy,
	.reset = drm_atomic_helper_connector_reset,
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};

static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
	.get_modes = vc4_hdmi_connector_get_modes,
};

static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
						     struct drm_encoder *encoder)
{
	struct drm_connector *connector = NULL;
	struct vc4_hdmi_connector *hdmi_connector;
	int ret = 0;

	hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
				      GFP_KERNEL);
	if (!hdmi_connector) {
		ret = -ENOMEM;
		goto fail;
	}
	connector = &hdmi_connector->base;

	hdmi_connector->encoder = encoder;

	drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
			   DRM_MODE_CONNECTOR_HDMIA);
	drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);

	connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
			     DRM_CONNECTOR_POLL_DISCONNECT);

	connector->interlace_allowed = 1;
	connector->doublescan_allowed = 0;

	drm_mode_connector_attach_encoder(connector, encoder);

	return connector;

 fail:
	if (connector)
		vc4_hdmi_connector_destroy(connector);

	return ERR_PTR(ret);
}

static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
{
	drm_encoder_cleanup(encoder);
}

static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
	.destroy = vc4_hdmi_encoder_destroy,
};

static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder,
				      struct drm_display_mode *unadjusted_mode,
				      struct drm_display_mode *mode)
{
	struct drm_device *dev = encoder->dev;
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	bool debug_dump_regs = false;
	bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
	bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
	u32 vactive = (mode->vdisplay >>
		       ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0));
	u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
				   VC4_HDMI_VERTA_VSP) |
		     VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
				   VC4_HDMI_VERTA_VFP) |
		     VC4_SET_FIELD(vactive, VC4_HDMI_VERTA_VAL));
	u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
		     VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
				   VC4_HDMI_VERTB_VBP));

	if (debug_dump_regs) {
		DRM_INFO("HDMI regs before:\n");
		vc4_hdmi_dump_regs(dev);
	}

	HD_WRITE(VC4_HD_VID_CTL, 0);

	clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000);

	HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
		   HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
		   VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
		   VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);

	HDMI_WRITE(VC4_HDMI_HORZA,
		   (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
		   (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
		   VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP));

	HDMI_WRITE(VC4_HDMI_HORZB,
		   VC4_SET_FIELD(mode->htotal - mode->hsync_end,
				 VC4_HDMI_HORZB_HBP) |
		   VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
				 VC4_HDMI_HORZB_HSP) |
		   VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
				 VC4_HDMI_HORZB_HFP));

	HDMI_WRITE(VC4_HDMI_VERTA0, verta);
	HDMI_WRITE(VC4_HDMI_VERTA1, verta);

	HDMI_WRITE(VC4_HDMI_VERTB0, vertb);
	HDMI_WRITE(VC4_HDMI_VERTB1, vertb);

	HD_WRITE(VC4_HD_VID_CTL,
		 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
		 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));

	/* The RGB order applies even when CSC is disabled. */
	HD_WRITE(VC4_HD_CSC_CTL, VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
					       VC4_HD_CSC_CTL_ORDER));

	HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);

	if (debug_dump_regs) {
		DRM_INFO("HDMI regs after:\n");
		vc4_hdmi_dump_regs(dev);
	}
}

static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct vc4_dev *vc4 = to_vc4_dev(dev);

	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
	HD_WRITE(VC4_HD_VID_CTL,
		 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
}

static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
{
	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
	struct drm_device *dev = encoder->dev;
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	int ret;

	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);

	HD_WRITE(VC4_HD_VID_CTL,
		 HD_READ(VC4_HD_VID_CTL) |
		 VC4_HD_VID_CTL_ENABLE |
		 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
		 VC4_HD_VID_CTL_FRAME_COUNTER_RESET);

	if (vc4_encoder->hdmi_monitor) {
		HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
			   HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
			   VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);

		ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
			       VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1);
		WARN_ONCE(ret, "Timeout waiting for "
			  "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
	} else {
		HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
			   HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
			   ~(VC4_HDMI_RAM_PACKET_ENABLE));
		HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
			   HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
			   ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);

		ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
				 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1);
		WARN_ONCE(ret, "Timeout waiting for "
			  "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
	}

	if (vc4_encoder->hdmi_monitor) {
		u32 drift;

		WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
			  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
		HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
			   HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
			   VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);

		/* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set
		 * up the infoframe.
		 */

		drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
		drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;

		HDMI_WRITE(VC4_HDMI_FIFO_CTL,
			   drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
		HDMI_WRITE(VC4_HDMI_FIFO_CTL,
			   drift | VC4_HDMI_FIFO_CTL_RECENTER);
		udelay(1000);
		HDMI_WRITE(VC4_HDMI_FIFO_CTL,
			   drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
		HDMI_WRITE(VC4_HDMI_FIFO_CTL,
			   drift | VC4_HDMI_FIFO_CTL_RECENTER);

		ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
			       VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
		WARN_ONCE(ret, "Timeout waiting for "
			  "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
	}
}

static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
	.mode_set = vc4_hdmi_encoder_mode_set,
	.disable = vc4_hdmi_encoder_disable,
	.enable = vc4_hdmi_encoder_enable,
};

static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct drm_device *drm = dev_get_drvdata(master);
	struct vc4_dev *vc4 = drm->dev_private;
	struct vc4_hdmi *hdmi;
	struct vc4_hdmi_encoder *vc4_hdmi_encoder;
	struct device_node *ddc_node;
	u32 value;
	int ret;

	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
	if (!hdmi)
		return -ENOMEM;

	vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
					GFP_KERNEL);
	if (!vc4_hdmi_encoder)
		return -ENOMEM;
	vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
	hdmi->encoder = &vc4_hdmi_encoder->base.base;

	hdmi->pdev = pdev;
	hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
	if (IS_ERR(hdmi->hdmicore_regs))
		return PTR_ERR(hdmi->hdmicore_regs);

	hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
	if (IS_ERR(hdmi->hd_regs))
		return PTR_ERR(hdmi->hd_regs);

	hdmi->pixel_clock = devm_clk_get(dev, "pixel");
	if (IS_ERR(hdmi->pixel_clock)) {
		DRM_ERROR("Failed to get pixel clock\n");
		return PTR_ERR(hdmi->pixel_clock);
	}
	hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
	if (IS_ERR(hdmi->hsm_clock)) {
		DRM_ERROR("Failed to get HDMI state machine clock\n");
		return PTR_ERR(hdmi->hsm_clock);
	}

	ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
	if (!ddc_node) {
		DRM_ERROR("Failed to find ddc node in device tree\n");
		return -ENODEV;
	}

	hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
	of_node_put(ddc_node);
	if (!hdmi->ddc) {
		DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
		return -EPROBE_DEFER;
	}

	/* Enable the clocks at startup.  We can't quite recover from
	 * turning off the pixel clock during disable/enables yet, so
	 * it's always running.
	 */
	ret = clk_prepare_enable(hdmi->pixel_clock);
	if (ret) {
		DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
		goto err_put_i2c;
	}

	/* This is the rate that is set by the firmware.  The number
	 * needs to be a bit higher than the pixel clock rate
	 * (generally 148.5Mhz).
	 */
	ret = clk_set_rate(hdmi->hsm_clock, 163682864);
	if (ret) {
		DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
		goto err_unprepare_pix;
	}

	ret = clk_prepare_enable(hdmi->hsm_clock);
	if (ret) {
		DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
			  ret);
		goto err_unprepare_pix;
	}

	/* Only use the GPIO HPD pin if present in the DT, otherwise
	 * we'll use the HDMI core's register.
	 */
	if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
		enum of_gpio_flags hpd_gpio_flags;

		hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
							 "hpd-gpios", 0,
							 &hpd_gpio_flags);
		if (hdmi->hpd_gpio < 0) {
			ret = hdmi->hpd_gpio;
			goto err_unprepare_hsm;
		}

		hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
	}

	vc4->hdmi = hdmi;

	/* HDMI core must be enabled. */
	if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
		HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
		udelay(1);
		HD_WRITE(VC4_HD_M_CTL, 0);

		HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);

		HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
			   VC4_HDMI_SW_RESET_HDMI |
			   VC4_HDMI_SW_RESET_FORMAT_DETECT);

		HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);

		/* PHY should be in reset, like
		 * vc4_hdmi_encoder_disable() does.
		 */
		HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
	}

	drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
			 DRM_MODE_ENCODER_TMDS, NULL);
	drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);

	hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
	if (IS_ERR(hdmi->connector)) {
		ret = PTR_ERR(hdmi->connector);
		goto err_destroy_encoder;
	}

	return 0;

err_destroy_encoder:
	vc4_hdmi_encoder_destroy(hdmi->encoder);
err_unprepare_hsm:
	clk_disable_unprepare(hdmi->hsm_clock);
err_unprepare_pix:
	clk_disable_unprepare(hdmi->pixel_clock);
err_put_i2c:
	put_device(&hdmi->ddc->dev);

	return ret;
}

static void vc4_hdmi_unbind(struct device *dev, struct device *master,
			    void *data)
{
	struct drm_device *drm = dev_get_drvdata(master);
	struct vc4_dev *vc4 = drm->dev_private;
	struct vc4_hdmi *hdmi = vc4->hdmi;

	vc4_hdmi_connector_destroy(hdmi->connector);
	vc4_hdmi_encoder_destroy(hdmi->encoder);

	clk_disable_unprepare(hdmi->pixel_clock);
	clk_disable_unprepare(hdmi->hsm_clock);
	put_device(&hdmi->ddc->dev);

	vc4->hdmi = NULL;
}

static const struct component_ops vc4_hdmi_ops = {
	.bind   = vc4_hdmi_bind,
	.unbind = vc4_hdmi_unbind,
};

static int vc4_hdmi_dev_probe(struct platform_device *pdev)
{
	return component_add(&pdev->dev, &vc4_hdmi_ops);
}

static int vc4_hdmi_dev_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &vc4_hdmi_ops);
	return 0;
}

static const struct of_device_id vc4_hdmi_dt_match[] = {
	{ .compatible = "brcm,bcm2835-hdmi" },
	{}
};

struct platform_driver vc4_hdmi_driver = {
	.probe = vc4_hdmi_dev_probe,
	.remove = vc4_hdmi_dev_remove,
	.driver = {
		.name = "vc4_hdmi",
		.of_match_table = vc4_hdmi_dt_match,
	},
};
Commit	Line	Data
c8b75bca EA	1	/*
	2	* Copyright (C) 2015 Broadcom
	3	* Copyright (c) 2014 The Linux Foundation. All rights reserved.
	4	* Copyright (C) 2013 Red Hat
	5	* Author: Rob Clark <robdclark@gmail.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published by
	9	* the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	/**
	21	* DOC: VC4 Falcon HDMI module
	22	*
	23	* The HDMI core has a state machine and a PHY. Most of the unit
	24	* operates off of the HSM clock from CPRMAN. It also internally uses
	25	* the PLLH_PIX clock for the PHY.
	26	*/
	27
	28	#include "drm_atomic_helper.h"
	29	#include "drm_crtc_helper.h"
	30	#include "drm_edid.h"
	31	#include "linux/clk.h"
	32	#include "linux/component.h"
	33	#include "linux/i2c.h"
	34	#include "linux/of_gpio.h"
	35	#include "linux/of_platform.h"
	36	#include "vc4_drv.h"
	37	#include "vc4_regs.h"
	38
	39	/* General HDMI hardware state. */
	40	struct vc4_hdmi {
	41	struct platform_device *pdev;
	42
	43	struct drm_encoder *encoder;
	44	struct drm_connector *connector;
	45
	46	struct i2c_adapter *ddc;
	47	void __iomem *hdmicore_regs;
	48	void __iomem *hd_regs;
	49	int hpd_gpio;
0b06e0a7	50	bool hpd_active_low;
c8b75bca EA	51
	52	struct clk *pixel_clock;
	53	struct clk *hsm_clock;
	54	};
	55
	56	#define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
	57	#define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
	58	#define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
	59	#define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
	60
	61	/* VC4 HDMI encoder KMS struct */
	62	struct vc4_hdmi_encoder {
	63	struct vc4_encoder base;
	64	bool hdmi_monitor;
	65	};
	66
	67	static inline struct vc4_hdmi_encoder *
	68	to_vc4_hdmi_encoder(struct drm_encoder *encoder)
	69	{
	70	return container_of(encoder, struct vc4_hdmi_encoder, base.base);
	71	}
	72
	73	/* VC4 HDMI connector KMS struct */
	74	struct vc4_hdmi_connector {
	75	struct drm_connector base;
	76
	77	/* Since the connector is attached to just the one encoder,
	78	* this is the reference to it so we can do the best_encoder()
	79	* hook.
	80	*/
	81	struct drm_encoder *encoder;
	82	};
	83
	84	static inline struct vc4_hdmi_connector *
	85	to_vc4_hdmi_connector(struct drm_connector *connector)
	86	{
	87	return container_of(connector, struct vc4_hdmi_connector, base);
	88	}
	89
	90	#define HDMI_REG(reg) { reg, #reg }
	91	static const struct {
	92	u32 reg;
	93	const char *name;
	94	} hdmi_regs[] = {
	95	HDMI_REG(VC4_HDMI_CORE_REV),
	96	HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
	97	HDMI_REG(VC4_HDMI_HOTPLUG_INT),
	98	HDMI_REG(VC4_HDMI_HOTPLUG),
936f1a53	99	HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
c8b75bca EA	100	HDMI_REG(VC4_HDMI_HORZA),
	101	HDMI_REG(VC4_HDMI_HORZB),
	102	HDMI_REG(VC4_HDMI_FIFO_CTL),
	103	HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
	104	HDMI_REG(VC4_HDMI_VERTA0),
	105	HDMI_REG(VC4_HDMI_VERTA1),
	106	HDMI_REG(VC4_HDMI_VERTB0),
	107	HDMI_REG(VC4_HDMI_VERTB1),
	108	HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
	109	};
	110
	111	static const struct {
	112	u32 reg;
	113	const char *name;
	114	} hd_regs[] = {
	115	HDMI_REG(VC4_HD_M_CTL),
	116	HDMI_REG(VC4_HD_MAI_CTL),
	117	HDMI_REG(VC4_HD_VID_CTL),
	118	HDMI_REG(VC4_HD_CSC_CTL),
	119	HDMI_REG(VC4_HD_FRAME_COUNT),
	120	};
	121
	122	#ifdef CONFIG_DEBUG_FS
	123	int vc4_hdmi_debugfs_regs(struct seq_file m, void unused)
	124	{
	125	struct drm_info_node node = (struct drm_info_node )m->private;
	126	struct drm_device *dev = node->minor->dev;
	127	struct vc4_dev *vc4 = to_vc4_dev(dev);
	128	int i;
	129
	130	for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
	131	seq_printf(m, "%s (0x%04x): 0x%08x\n",
	132	hdmi_regs[i].name, hdmi_regs[i].reg,
	133	HDMI_READ(hdmi_regs[i].reg));
	134	}
	135
	136	for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
	137	seq_printf(m, "%s (0x%04x): 0x%08x\n",
	138	hd_regs[i].name, hd_regs[i].reg,
	139	HD_READ(hd_regs[i].reg));
	140	}
	141
	142	return 0;
	143	}
	144	#endif /* CONFIG_DEBUG_FS */
	145
	146	static void vc4_hdmi_dump_regs(struct drm_device *dev)
	147	{
	148	struct vc4_dev *vc4 = to_vc4_dev(dev);
	149	int i;
	150
	151	for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
	152	DRM_INFO("0x%04x (%s): 0x%08x\n",
	153	hdmi_regs[i].reg, hdmi_regs[i].name,
	154	HDMI_READ(hdmi_regs[i].reg));
	155	}
	156	for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
	157	DRM_INFO("0x%04x (%s): 0x%08x\n",
	158	hd_regs[i].reg, hd_regs[i].name,
	159	HD_READ(hd_regs[i].reg));
	160	}
	161	}
	162
	163	static enum drm_connector_status
164	vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
165	{
166	struct drm_device *dev = connector->dev;
167	struct vc4_dev *vc4 = to_vc4_dev(dev);
168
169	if (vc4->hdmi->hpd_gpio) {
0b06e0a7 EA	170	if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
0b06e0a7 EA	171	vc4->hdmi->hpd_active_low)
c8b75bca EA	172	return connector_status_connected;
	173	else
	174	return connector_status_disconnected;
	175	}
	176
	177	if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
	178	return connector_status_connected;
	179	else
	180	return connector_status_disconnected;
	181	}
	182
	183	static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
	184	{
	185	drm_connector_unregister(connector);
	186	drm_connector_cleanup(connector);
	187	}
	188
	189	static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
	190	{
	191	struct vc4_hdmi_connector *vc4_connector =
	192	to_vc4_hdmi_connector(connector);
	193	struct drm_encoder *encoder = vc4_connector->encoder;
	194	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
	195	struct drm_device *dev = connector->dev;
	196	struct vc4_dev *vc4 = to_vc4_dev(dev);
	197	int ret = 0;
	198	struct edid *edid;
	199
	200	edid = drm_get_edid(connector, vc4->hdmi->ddc);
	201	if (!edid)
	202	return -ENODEV;
	203
	204	vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
	205	drm_mode_connector_update_edid_property(connector, edid);
	206	ret = drm_add_edid_modes(connector, edid);
	207
	208	return ret;
	209	}
	210
acc1be1d MK	211	/*
	212	* drm_helper_probe_single_connector_modes() applies drm_mode_set_crtcinfo to
	213	* all modes with flag CRTC_INTERLACE_HALVE_V. We don't want this, as it
	214	* screws up vblank timestamping for interlaced modes, so fix it up.
	215	*/
	216	static int vc4_hdmi_connector_probe_modes(struct drm_connector *connector,
	217	uint32_t maxX, uint32_t maxY)
	218	{
	219	struct drm_display_mode *mode;
	220	int count;
	221
	222	count = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
	223	if (count == 0)
	224	return 0;
	225
	226	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] probed adapted modes :\n",
	227	connector->base.id, connector->name);
	228	list_for_each_entry(mode, &connector->modes, head) {
	229	drm_mode_set_crtcinfo(mode, 0);
	230	drm_mode_debug_printmodeline(mode);
	231	}
	232
	233	return count;
	234	}
	235
c8b75bca EA	236	static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
	237	.dpms = drm_atomic_helper_connector_dpms,
	238	.detect = vc4_hdmi_connector_detect,
acc1be1d	239	.fill_modes = vc4_hdmi_connector_probe_modes,
c8b75bca EA	240	.destroy = vc4_hdmi_connector_destroy,
	241	.reset = drm_atomic_helper_connector_reset,
	242	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
	243	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	244	};
	245
	246	static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
	247	.get_modes = vc4_hdmi_connector_get_modes,
c8b75bca EA	248	};
	249
	250	static struct drm_connector vc4_hdmi_connector_init(struct drm_device dev,
	251	struct drm_encoder *encoder)
	252	{
	253	struct drm_connector *connector = NULL;
	254	struct vc4_hdmi_connector *hdmi_connector;
	255	int ret = 0;
	256
	257	hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
	258	GFP_KERNEL);
	259	if (!hdmi_connector) {
	260	ret = -ENOMEM;
	261	goto fail;
	262	}
	263	connector = &hdmi_connector->base;
	264
	265	hdmi_connector->encoder = encoder;
	266
	267	drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
	268	DRM_MODE_CONNECTOR_HDMIA);
	269	drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
	270
	271	connector->polled = (DRM_CONNECTOR_POLL_CONNECT \|
	272	DRM_CONNECTOR_POLL_DISCONNECT);
	273
acc1be1d	274	connector->interlace_allowed = 1;
c8b75bca EA	275	connector->doublescan_allowed = 0;
	276
	277	drm_mode_connector_attach_encoder(connector, encoder);
	278
	279	return connector;
	280
	281	fail:
	282	if (connector)
	283	vc4_hdmi_connector_destroy(connector);
	284
	285	return ERR_PTR(ret);
	286	}
	287
	288	static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
	289	{
	290	drm_encoder_cleanup(encoder);
	291	}
	292
	293	static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
	294	.destroy = vc4_hdmi_encoder_destroy,
	295	};
	296
	297	static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder,
	298	struct drm_display_mode *unadjusted_mode,
	299	struct drm_display_mode *mode)
	300	{
	301	struct drm_device *dev = encoder->dev;
	302	struct vc4_dev *vc4 = to_vc4_dev(dev);
	303	bool debug_dump_regs = false;
	304	bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
	305	bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
	306	u32 vactive = (mode->vdisplay >>
	307	((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0));
	308	u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
	309	VC4_HDMI_VERTA_VSP) \|
	310	VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
	311	VC4_HDMI_VERTA_VFP) \|
	312	VC4_SET_FIELD(vactive, VC4_HDMI_VERTA_VAL));
	313	u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) \|
	314	VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
	315	VC4_HDMI_VERTB_VBP));
	316
	317	if (debug_dump_regs) {
	318	DRM_INFO("HDMI regs before:\n");
	319	vc4_hdmi_dump_regs(dev);
	320	}
	321
	322	HD_WRITE(VC4_HD_VID_CTL, 0);
	323
	324	clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000);
	325
	326	HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
	327	HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) \|
	328	VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT \|
	329	VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
	330
	331	HDMI_WRITE(VC4_HDMI_HORZA,
	332	(vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) \|
	333	(hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) \|
	334	VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP));
	335
	336	HDMI_WRITE(VC4_HDMI_HORZB,
	337	VC4_SET_FIELD(mode->htotal - mode->hsync_end,
	338	VC4_HDMI_HORZB_HBP) \|
339	VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
340	VC4_HDMI_HORZB_HSP) \|
341	VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
342	VC4_HDMI_HORZB_HFP));
343
344	HDMI_WRITE(VC4_HDMI_VERTA0, verta);
345	HDMI_WRITE(VC4_HDMI_VERTA1, verta);
346
347	HDMI_WRITE(VC4_HDMI_VERTB0, vertb);
348	HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
349
350	HD_WRITE(VC4_HD_VID_CTL,
351	(vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) \|
352	(hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
353
354	/* The RGB order applies even when CSC is disabled. */
355	HD_WRITE(VC4_HD_CSC_CTL, VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
356	VC4_HD_CSC_CTL_ORDER));
357
358	HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
359
360	if (debug_dump_regs) {
361	DRM_INFO("HDMI regs after:\n");
362	vc4_hdmi_dump_regs(dev);
363	}
364	}
365
366	static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
367	{
368	struct drm_device *dev = encoder->dev;
369	struct vc4_dev *vc4 = to_vc4_dev(dev);
370
371	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
372	HD_WRITE(VC4_HD_VID_CTL,
373	HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
374	}
375
376	static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
377	{
378	struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
379	struct drm_device *dev = encoder->dev;
380	struct vc4_dev *vc4 = to_vc4_dev(dev);
381	int ret;
382
383	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
384
385	HD_WRITE(VC4_HD_VID_CTL,
386	HD_READ(VC4_HD_VID_CTL) \|
387	VC4_HD_VID_CTL_ENABLE \|
388	VC4_HD_VID_CTL_UNDERFLOW_ENABLE \|
389	VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
390
391	if (vc4_encoder->hdmi_monitor) {
392	HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
393	HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) \|
394	VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
395
396	ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
397	VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1);
398	WARN_ONCE(ret, "Timeout waiting for "
399	"VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
400	} else {
401	HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
402	HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
403	~(VC4_HDMI_RAM_PACKET_ENABLE));
404	HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
405	HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
406	~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
407
408	ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
409	VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1);
410	WARN_ONCE(ret, "Timeout waiting for "
411	"!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
412	}
413
414	if (vc4_encoder->hdmi_monitor) {
415	u32 drift;
416
417	WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
418	VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
419	HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
420	HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) \|
421	VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
422
423	/* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set
424	* up the infoframe.
425	*/
426
427	drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
428	drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
429
430	HDMI_WRITE(VC4_HDMI_FIFO_CTL,
431	drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
432	HDMI_WRITE(VC4_HDMI_FIFO_CTL,
433	drift \| VC4_HDMI_FIFO_CTL_RECENTER);
434	udelay(1000);
435	HDMI_WRITE(VC4_HDMI_FIFO_CTL,
436	drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
437	HDMI_WRITE(VC4_HDMI_FIFO_CTL,
438	drift \| VC4_HDMI_FIFO_CTL_RECENTER);
439
440	ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
441	VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
442	WARN_ONCE(ret, "Timeout waiting for "
443	"VC4_HDMI_FIFO_CTL_RECENTER_DONE");
444	}
445	}
446
447	static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
448	.mode_set = vc4_hdmi_encoder_mode_set,
449	.disable = vc4_hdmi_encoder_disable,
450	.enable = vc4_hdmi_encoder_enable,
451	};
452
453	static int vc4_hdmi_bind(struct device dev, struct device master, void *data)
454	{
455	struct platform_device *pdev = to_platform_device(dev);
456	struct drm_device *drm = dev_get_drvdata(master);
457	struct vc4_dev *vc4 = drm->dev_private;
458	struct vc4_hdmi *hdmi;
459	struct vc4_hdmi_encoder *vc4_hdmi_encoder;
460	struct device_node *ddc_node;
461	u32 value;
462	int ret;
463
464	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
465	if (!hdmi)
466	return -ENOMEM;
467
468	vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
469	GFP_KERNEL);
470	if (!vc4_hdmi_encoder)
471	return -ENOMEM;
472	vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
473	hdmi->encoder = &vc4_hdmi_encoder->base.base;
474
475	hdmi->pdev = pdev;
476	hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
477	if (IS_ERR(hdmi->hdmicore_regs))
478	return PTR_ERR(hdmi->hdmicore_regs);
479
480	hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
481	if (IS_ERR(hdmi->hd_regs))
482	return PTR_ERR(hdmi->hd_regs);
483
c8b75bca EA	484	hdmi->pixel_clock = devm_clk_get(dev, "pixel");
	485	if (IS_ERR(hdmi->pixel_clock)) {
	486	DRM_ERROR("Failed to get pixel clock\n");
	487	return PTR_ERR(hdmi->pixel_clock);
	488	}
	489	hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
	490	if (IS_ERR(hdmi->hsm_clock)) {
	491	DRM_ERROR("Failed to get HDMI state machine clock\n");
	492	return PTR_ERR(hdmi->hsm_clock);
	493	}
	494
027a6976 PC	495	ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
	496	if (!ddc_node) {
	497	DRM_ERROR("Failed to find ddc node in device tree\n");
	498	return -ENODEV;
	499	}
	500
c8b75bca	501	hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
027a6976	502	of_node_put(ddc_node);
c8b75bca EA	503	if (!hdmi->ddc) {
	504	DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
	505	return -EPROBE_DEFER;
	506	}
	507
	508	/* Enable the clocks at startup. We can't quite recover from
	509	* turning off the pixel clock during disable/enables yet, so
	510	* it's always running.
	511	*/
	512	ret = clk_prepare_enable(hdmi->pixel_clock);
	513	if (ret) {
	514	DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
	515	goto err_put_i2c;
	516	}
	517
851479ad EA	518	/* This is the rate that is set by the firmware. The number
	519	* needs to be a bit higher than the pixel clock rate
	520	* (generally 148.5Mhz).
	521	*/
	522	ret = clk_set_rate(hdmi->hsm_clock, 163682864);
	523	if (ret) {
	524	DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
	525	goto err_unprepare_pix;
	526	}
	527
c8b75bca EA	528	ret = clk_prepare_enable(hdmi->hsm_clock);
	529	if (ret) {
	530	DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
	531	ret);
	532	goto err_unprepare_pix;
	533	}
	534
	535	/* Only use the GPIO HPD pin if present in the DT, otherwise
	536	* we'll use the HDMI core's register.
	537	*/
	538	if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
0b06e0a7 EA	539	enum of_gpio_flags hpd_gpio_flags;
	540
	541	hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
	542	"hpd-gpios", 0,
	543	&hpd_gpio_flags);
c8b75bca EA	544	if (hdmi->hpd_gpio < 0) {
	545	ret = hdmi->hpd_gpio;
	546	goto err_unprepare_hsm;
	547	}
0b06e0a7 EA	548
0b06e0a7 EA	549	hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
c8b75bca EA	550	}
	551
	552	vc4->hdmi = hdmi;
	553
	554	/* HDMI core must be enabled. */
851479ad EA	555	if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
	556	HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
	557	udelay(1);
	558	HD_WRITE(VC4_HD_M_CTL, 0);
	559
	560	HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
	561
	562	HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
	563	VC4_HDMI_SW_RESET_HDMI \|
	564	VC4_HDMI_SW_RESET_FORMAT_DETECT);
	565
	566	HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
	567
	568	/* PHY should be in reset, like
	569	* vc4_hdmi_encoder_disable() does.
	570	*/
	571	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
	572	}
c8b75bca EA	573
c8b75bca EA	574	drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
13a3d91f	575	DRM_MODE_ENCODER_TMDS, NULL);
c8b75bca EA	576	drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
	577
	578	hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
	579	if (IS_ERR(hdmi->connector)) {
	580	ret = PTR_ERR(hdmi->connector);
	581	goto err_destroy_encoder;
	582	}
	583
	584	return 0;
	585
	586	err_destroy_encoder:
	587	vc4_hdmi_encoder_destroy(hdmi->encoder);
	588	err_unprepare_hsm:
	589	clk_disable_unprepare(hdmi->hsm_clock);
	590	err_unprepare_pix:
	591	clk_disable_unprepare(hdmi->pixel_clock);
	592	err_put_i2c:
58839803	593	put_device(&hdmi->ddc->dev);
c8b75bca EA	594
	595	return ret;
	596	}
	597
	598	static void vc4_hdmi_unbind(struct device dev, struct device master,
	599	void *data)
	600	{
	601	struct drm_device *drm = dev_get_drvdata(master);
	602	struct vc4_dev *vc4 = drm->dev_private;
	603	struct vc4_hdmi *hdmi = vc4->hdmi;
	604
	605	vc4_hdmi_connector_destroy(hdmi->connector);
	606	vc4_hdmi_encoder_destroy(hdmi->encoder);
	607
	608	clk_disable_unprepare(hdmi->pixel_clock);
	609	clk_disable_unprepare(hdmi->hsm_clock);
	610	put_device(&hdmi->ddc->dev);
	611
	612	vc4->hdmi = NULL;
	613	}
	614
	615	static const struct component_ops vc4_hdmi_ops = {
	616	.bind = vc4_hdmi_bind,
	617	.unbind = vc4_hdmi_unbind,
	618	};
	619
	620	static int vc4_hdmi_dev_probe(struct platform_device *pdev)
	621	{
	622	return component_add(&pdev->dev, &vc4_hdmi_ops);
	623	}
	624
	625	static int vc4_hdmi_dev_remove(struct platform_device *pdev)
	626	{
	627	component_del(&pdev->dev, &vc4_hdmi_ops);
	628	return 0;
	629	}
	630
	631	static const struct of_device_id vc4_hdmi_dt_match[] = {
	632	{ .compatible = "brcm,bcm2835-hdmi" },
	633	{}
	634	};
	635
	636	struct platform_driver vc4_hdmi_driver = {
	637	.probe = vc4_hdmi_dev_probe,
	638	.remove = vc4_hdmi_dev_remove,
	639	.driver = {
	640	.name = "vc4_hdmi",
	641	.of_match_table = vc4_hdmi_dt_match,
	642	},
	643	};