[deliverable/linux.git] / drivers / gpu / drm / vc4 / vc4_irq.c

/*
 * Copyright © 2014 Broadcom
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

/** DOC: Interrupt management for the V3D engine.
 *
 * We have an interrupt status register (V3D_INTCTL) which reports
 * interrupts, and where writing 1 bits clears those interrupts.
 * There are also a pair of interrupt registers
 * (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or
 * disables that specific interrupt, and 0s written are ignored
 * (reading either one returns the set of enabled interrupts).
 *
 * When we take a binning flush done interrupt, we need to submit the
 * next frame for binning and move the finished frame to the render
 * thread.
 *
 * When we take a render frame interrupt, we need to wake the
 * processes waiting for some frame to be done, and get the next frame
 * submitted ASAP (so the hardware doesn't sit idle when there's work
 * to do).
 *
 * When we take the binner out of memory interrupt, we need to
 * allocate some new memory and pass it to the binner so that the
 * current job can make progress.
 */

#include "vc4_drv.h"
#include "vc4_regs.h"

#define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \
			 V3D_INT_FLDONE | \
			 V3D_INT_FRDONE)

DECLARE_WAIT_QUEUE_HEAD(render_wait);

static void
vc4_overflow_mem_work(struct work_struct *work)
{
	struct vc4_dev *vc4 =
		container_of(work, struct vc4_dev, overflow_mem_work);
	struct drm_device *dev = vc4->dev;
	struct vc4_bo *bo;

	bo = vc4_bo_create(dev, 256 * 1024, true);
	if (IS_ERR(bo)) {
		DRM_ERROR("Couldn't allocate binner overflow mem\n");
		return;
	}

	/* If there's a job executing currently, then our previous
	 * overflow allocation is getting used in that job and we need
	 * to queue it to be released when the job is done.  But if no
	 * job is executing at all, then we can free the old overflow
	 * object direcctly.
	 *
	 * No lock necessary for this pointer since we're the only
	 * ones that update the pointer, and our workqueue won't
	 * reenter.
	 */
	if (vc4->overflow_mem) {
		struct vc4_exec_info *current_exec;
		unsigned long irqflags;

		spin_lock_irqsave(&vc4->job_lock, irqflags);
		current_exec = vc4_first_bin_job(vc4);
		if (!current_exec)
			current_exec = vc4_last_render_job(vc4);
		if (current_exec) {
			vc4->overflow_mem->seqno = current_exec->seqno;
			list_add_tail(&vc4->overflow_mem->unref_head,
				      &current_exec->unref_list);
			vc4->overflow_mem = NULL;
		}
		spin_unlock_irqrestore(&vc4->job_lock, irqflags);
	}

	if (vc4->overflow_mem)
		drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base);
	vc4->overflow_mem = bo;

	V3D_WRITE(V3D_BPOA, bo->base.paddr);
	V3D_WRITE(V3D_BPOS, bo->base.base.size);
	V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
	V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
}

static void
vc4_irq_finish_bin_job(struct drm_device *dev)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	struct vc4_exec_info *exec = vc4_first_bin_job(vc4);

	if (!exec)
		return;

	vc4_move_job_to_render(dev, exec);
	vc4_submit_next_bin_job(dev);
}

static void
vc4_cancel_bin_job(struct drm_device *dev)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	struct vc4_exec_info *exec = vc4_first_bin_job(vc4);

	if (!exec)
		return;

	list_move_tail(&exec->head, &vc4->bin_job_list);
	vc4_submit_next_bin_job(dev);
}

static void
vc4_irq_finish_render_job(struct drm_device *dev)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	struct vc4_exec_info *exec = vc4_first_render_job(vc4);

	if (!exec)
		return;

	vc4->finished_seqno++;
	list_move_tail(&exec->head, &vc4->job_done_list);
	vc4_submit_next_render_job(dev);

	wake_up_all(&vc4->job_wait_queue);
	schedule_work(&vc4->job_done_work);
}

irqreturn_t
vc4_irq(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	uint32_t intctl;
	irqreturn_t status = IRQ_NONE;

	barrier();
	intctl = V3D_READ(V3D_INTCTL);

	/* Acknowledge the interrupts we're handling here. The binner
	 * last flush / render frame done interrupt will be cleared,
	 * while OUTOMEM will stay high until the underlying cause is
	 * cleared.
	 */
	V3D_WRITE(V3D_INTCTL, intctl);

	if (intctl & V3D_INT_OUTOMEM) {
		/* Disable OUTOMEM until the work is done. */
		V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM);
		schedule_work(&vc4->overflow_mem_work);
		status = IRQ_HANDLED;
	}

	if (intctl & V3D_INT_FLDONE) {
		spin_lock(&vc4->job_lock);
		vc4_irq_finish_bin_job(dev);
		spin_unlock(&vc4->job_lock);
		status = IRQ_HANDLED;
	}

	if (intctl & V3D_INT_FRDONE) {
		spin_lock(&vc4->job_lock);
		vc4_irq_finish_render_job(dev);
		spin_unlock(&vc4->job_lock);
		status = IRQ_HANDLED;
	}

	return status;
}

void
vc4_irq_preinstall(struct drm_device *dev)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);

	init_waitqueue_head(&vc4->job_wait_queue);
	INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work);

	/* Clear any pending interrupts someone might have left around
	 * for us.
	 */
	V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
}

int
vc4_irq_postinstall(struct drm_device *dev)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);

	/* Enable both the render done and out of memory interrupts. */
	V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);

	return 0;
}

void
vc4_irq_uninstall(struct drm_device *dev)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);

	/* Disable sending interrupts for our driver's IRQs. */
	V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS);

	/* Clear any pending interrupts we might have left. */
	V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);

	cancel_work_sync(&vc4->overflow_mem_work);
}

/** Reinitializes interrupt registers when a GPU reset is performed. */
void vc4_irq_reset(struct drm_device *dev)
{
	struct vc4_dev *vc4 = to_vc4_dev(dev);
	unsigned long irqflags;

	/* Acknowledge any stale IRQs. */
	V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);

	/*
	 * Turn all our interrupts on.  Binner out of memory is the
	 * only one we expect to trigger at this point, since we've
	 * just come from poweron and haven't supplied any overflow
	 * memory yet.
	 */
	V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);

	spin_lock_irqsave(&vc4->job_lock, irqflags);
	vc4_cancel_bin_job(dev);
	vc4_irq_finish_render_job(dev);
	spin_unlock_irqrestore(&vc4->job_lock, irqflags);
}
Commit	Line	Data
d5b1a78a EA	1	/*
	2	* Copyright © 2014 Broadcom
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*/
	23
	24	/** DOC: Interrupt management for the V3D engine.
	25	*
	26	* We have an interrupt status register (V3D_INTCTL) which reports
	27	* interrupts, and where writing 1 bits clears those interrupts.
	28	* There are also a pair of interrupt registers
	29	* (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or
	30	* disables that specific interrupt, and 0s written are ignored
	31	* (reading either one returns the set of enabled interrupts).
	32	*
ca26d28b VG	33	* When we take a binning flush done interrupt, we need to submit the
	34	* next frame for binning and move the finished frame to the render
	35	* thread.
	36	*
d5b1a78a EA	37	* When we take a render frame interrupt, we need to wake the
	38	* processes waiting for some frame to be done, and get the next frame
	39	* submitted ASAP (so the hardware doesn't sit idle when there's work
	40	* to do).
	41	*
	42	* When we take the binner out of memory interrupt, we need to
	43	* allocate some new memory and pass it to the binner so that the
	44	* current job can make progress.
	45	*/
	46
	47	#include "vc4_drv.h"
	48	#include "vc4_regs.h"
	49
	50	#define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM \| \
ca26d28b	51	V3D_INT_FLDONE \| \
d5b1a78a EA	52	V3D_INT_FRDONE)
	53
	54	DECLARE_WAIT_QUEUE_HEAD(render_wait);
	55
	56	static void
	57	vc4_overflow_mem_work(struct work_struct *work)
	58	{
	59	struct vc4_dev *vc4 =
	60	container_of(work, struct vc4_dev, overflow_mem_work);
	61	struct drm_device *dev = vc4->dev;
	62	struct vc4_bo *bo;
	63
	64	bo = vc4_bo_create(dev, 256 * 1024, true);
2c68f1fc	65	if (IS_ERR(bo)) {
d5b1a78a EA	66	DRM_ERROR("Couldn't allocate binner overflow mem\n");
	67	return;
	68	}
	69
	70	/* If there's a job executing currently, then our previous
	71	* overflow allocation is getting used in that job and we need
	72	* to queue it to be released when the job is done. But if no
	73	* job is executing at all, then we can free the old overflow
	74	* object direcctly.
	75	*
	76	* No lock necessary for this pointer since we're the only
	77	* ones that update the pointer, and our workqueue won't
	78	* reenter.
	79	*/
	80	if (vc4->overflow_mem) {
	81	struct vc4_exec_info *current_exec;
	82	unsigned long irqflags;
	83
	84	spin_lock_irqsave(&vc4->job_lock, irqflags);
ca26d28b	85	current_exec = vc4_first_bin_job(vc4);
9326e6f2 EA	86	if (!current_exec)
9326e6f2 EA	87	current_exec = vc4_last_render_job(vc4);
d5b1a78a	88	if (current_exec) {
9326e6f2	89	vc4->overflow_mem->seqno = current_exec->seqno;
d5b1a78a EA	90	list_add_tail(&vc4->overflow_mem->unref_head,
	91	&current_exec->unref_list);
	92	vc4->overflow_mem = NULL;
	93	}
	94	spin_unlock_irqrestore(&vc4->job_lock, irqflags);
	95	}
	96
	97	if (vc4->overflow_mem)
	98	drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base);
	99	vc4->overflow_mem = bo;
	100
	101	V3D_WRITE(V3D_BPOA, bo->base.paddr);
	102	V3D_WRITE(V3D_BPOS, bo->base.base.size);
	103	V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
	104	V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
	105	}
	106
	107	static void
ca26d28b VG	108	vc4_irq_finish_bin_job(struct drm_device *dev)
	109	{
	110	struct vc4_dev *vc4 = to_vc4_dev(dev);
	111	struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
	112
	113	if (!exec)
	114	return;
	115
	116	vc4_move_job_to_render(dev, exec);
	117	vc4_submit_next_bin_job(dev);
	118	}
	119
	120	static void
	121	vc4_cancel_bin_job(struct drm_device *dev)
	122	{
	123	struct vc4_dev *vc4 = to_vc4_dev(dev);
	124	struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
	125
	126	if (!exec)
	127	return;
	128
	129	list_move_tail(&exec->head, &vc4->bin_job_list);
	130	vc4_submit_next_bin_job(dev);
	131	}
	132
	133	static void
	134	vc4_irq_finish_render_job(struct drm_device *dev)
d5b1a78a EA	135	{
d5b1a78a EA	136	struct vc4_dev *vc4 = to_vc4_dev(dev);
ca26d28b	137	struct vc4_exec_info *exec = vc4_first_render_job(vc4);
d5b1a78a EA	138
	139	if (!exec)
	140	return;
	141
	142	vc4->finished_seqno++;
	143	list_move_tail(&exec->head, &vc4->job_done_list);
ca26d28b	144	vc4_submit_next_render_job(dev);
d5b1a78a EA	145
	146	wake_up_all(&vc4->job_wait_queue);
	147	schedule_work(&vc4->job_done_work);
	148	}
	149
	150	irqreturn_t
	151	vc4_irq(int irq, void *arg)
	152	{
	153	struct drm_device *dev = arg;
	154	struct vc4_dev *vc4 = to_vc4_dev(dev);
	155	uint32_t intctl;
	156	irqreturn_t status = IRQ_NONE;
	157
	158	barrier();
	159	intctl = V3D_READ(V3D_INTCTL);
	160
ca26d28b VG	161	/* Acknowledge the interrupts we're handling here. The binner
	162	* last flush / render frame done interrupt will be cleared,
	163	* while OUTOMEM will stay high until the underlying cause is
	164	* cleared.
d5b1a78a EA	165	*/
	166	V3D_WRITE(V3D_INTCTL, intctl);
	167
	168	if (intctl & V3D_INT_OUTOMEM) {
	169	/* Disable OUTOMEM until the work is done. */
	170	V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM);
	171	schedule_work(&vc4->overflow_mem_work);
	172	status = IRQ_HANDLED;
	173	}
	174
ca26d28b VG	175	if (intctl & V3D_INT_FLDONE) {
	176	spin_lock(&vc4->job_lock);
	177	vc4_irq_finish_bin_job(dev);
	178	spin_unlock(&vc4->job_lock);
	179	status = IRQ_HANDLED;
	180	}
	181
d5b1a78a EA	182	if (intctl & V3D_INT_FRDONE) {
d5b1a78a EA	183	spin_lock(&vc4->job_lock);
ca26d28b	184	vc4_irq_finish_render_job(dev);
d5b1a78a EA	185	spin_unlock(&vc4->job_lock);
	186	status = IRQ_HANDLED;
	187	}
	188
	189	return status;
	190	}
	191
	192	void
	193	vc4_irq_preinstall(struct drm_device *dev)
	194	{
	195	struct vc4_dev *vc4 = to_vc4_dev(dev);
	196
	197	init_waitqueue_head(&vc4->job_wait_queue);
	198	INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work);
	199
	200	/* Clear any pending interrupts someone might have left around
	201	* for us.
	202	*/
	203	V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
	204	}
	205
	206	int
	207	vc4_irq_postinstall(struct drm_device *dev)
	208	{
	209	struct vc4_dev *vc4 = to_vc4_dev(dev);
	210
	211	/* Enable both the render done and out of memory interrupts. */
	212	V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
	213
	214	return 0;
	215	}
	216
	217	void
	218	vc4_irq_uninstall(struct drm_device *dev)
	219	{
	220	struct vc4_dev *vc4 = to_vc4_dev(dev);
	221
	222	/* Disable sending interrupts for our driver's IRQs. */
	223	V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS);
	224
	225	/* Clear any pending interrupts we might have left. */
	226	V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
	227
	228	cancel_work_sync(&vc4->overflow_mem_work);
	229	}
	230
	231	/** Reinitializes interrupt registers when a GPU reset is performed. */
	232	void vc4_irq_reset(struct drm_device *dev)
	233	{
	234	struct vc4_dev *vc4 = to_vc4_dev(dev);
	235	unsigned long irqflags;
	236
	237	/* Acknowledge any stale IRQs. */
	238	V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
	239
	240	/*
	241	* Turn all our interrupts on. Binner out of memory is the
	242	* only one we expect to trigger at this point, since we've
	243	* just come from poweron and haven't supplied any overflow
	244	* memory yet.
	245	*/
	246	V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
	247
	248	spin_lock_irqsave(&vc4->job_lock, irqflags);
ca26d28b VG	249	vc4_cancel_bin_job(dev);
ca26d28b VG	250	vc4_irq_finish_render_job(dev);
d5b1a78a EA	251	spin_unlock_irqrestore(&vc4->job_lock, irqflags);
d5b1a78a EA	252	}