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hwmon: (it87) Convert to use new hwmon API
[deliverable/linux.git] / drivers / hwmon / it87.c
CommitLineData
1da177e4 1/*
5f2dc798
JD		 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
c145d5c6 13 * Supports: IT8603E Super I/O chip w/LPC interface
3ba9d977 14 * IT8620E Super I/O chip w/LPC interface
574e9bd8 15 * IT8623E Super I/O chip w/LPC interface
c145d5c6 16 * IT8705F Super I/O chip w/LPC interface
5f2dc798
JD		 17 * IT8712F Super I/O chip w/LPC interface
18 * IT8716F Super I/O chip w/LPC interface
19 * IT8718F Super I/O chip w/LPC interface
20 * IT8720F Super I/O chip w/LPC interface
44c1bcd4 21 * IT8721F Super I/O chip w/LPC interface
5f2dc798 22 * IT8726F Super I/O chip w/LPC interface
16b5dda2 23 * IT8728F Super I/O chip w/LPC interface
ead80803 24 * IT8732F Super I/O chip w/LPC interface
44c1bcd4 25 * IT8758E Super I/O chip w/LPC interface
b0636707
GR		 26 * IT8771E Super I/O chip w/LPC interface
27 * IT8772E Super I/O chip w/LPC interface
7bc32d29 28 * IT8781F Super I/O chip w/LPC interface
0531d98b
GR		 29 * IT8782F Super I/O chip w/LPC interface
30 * IT8783E/F Super I/O chip w/LPC interface
a0c1424a 31 * IT8786E Super I/O chip w/LPC interface
4ee07157 32 * IT8790E Super I/O chip w/LPC interface
5f2dc798
JD		 33 * Sis950 A clone of the IT8705F
34 *
35 * Copyright (C) 2001 Chris Gauthron
7c81c60f 36 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
5f2dc798
JD		 37 *
38 * This program is free software; you can redistribute it and/or modify
39 * it under the terms of the GNU General Public License as published by
40 * the Free Software Foundation; either version 2 of the License, or
41 * (at your option) any later version.
42 *
43 * This program is distributed in the hope that it will be useful,
44 * but WITHOUT ANY WARRANTY; without even the implied warranty of
45 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
46 * GNU General Public License for more details.
47 *
48 * You should have received a copy of the GNU General Public License
49 * along with this program; if not, write to the Free Software
50 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
51 */
1da177e4 52
a8ca1037
JP		 53#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54
1da177e4
LT		 55#include <linux/module.h>
56#include <linux/init.h>
57#include <linux/slab.h>
58#include <linux/jiffies.h>
b74f3fdd 59#include <linux/platform_device.h>
943b0830 60#include <linux/hwmon.h>
303760b4
JD		 61#include <linux/hwmon-sysfs.h>
62#include <linux/hwmon-vid.h>
943b0830 63#include <linux/err.h>
9a61bf63 64#include <linux/mutex.h>
87808be4 65#include <linux/sysfs.h>
98dd22c3
JD		 66#include <linux/string.h>
67#include <linux/dmi.h>
b9acb64a 68#include <linux/acpi.h>
6055fae8 69#include <linux/io.h>
1da177e4 70
b74f3fdd 71#define DRVNAME "it87"
1da177e4 72
ead80803
JM		 73enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
74 it8771, it8772, it8781, it8782, it8783, it8786, it8790, it8603,
75 it8620 };
1da177e4 76
67b671bc
JD		 77static unsigned short force_id;
78module_param(force_id, ushort, 0);
79MODULE_PARM_DESC(force_id, "Override the detected device ID");
80
e84bd953 81static struct platform_device *it87_pdev[2];
b74f3fdd 82
3c2e3512 83#define REG_2E 0x2e /* The register to read/write */
e84bd953 84#define REG_4E 0x4e /* Secondary register to read/write */
3c2e3512 85
1da177e4 86#define DEV 0x07 /* Register: Logical device select */
1da177e4 87#define PME 0x04 /* The device with the fan registers in it */
b4da93e4
JMS		 88
89/* The device with the IT8718F/IT8720F VID value in it */
90#define GPIO 0x07
91
1da177e4
LT		 92#define DEVID 0x20 /* Register: Device ID */
93#define DEVREV 0x22 /* Register: Device Revision */
94
3c2e3512 95static inline int superio_inb(int ioreg, int reg)
1da177e4 96{
3c2e3512
GR		 97 outb(reg, ioreg);
98 return inb(ioreg + 1);
1da177e4
LT		 99}
100
3c2e3512 101static inline void superio_outb(int ioreg, int reg, int val)
436cad2a 102{
3c2e3512
GR		 103 outb(reg, ioreg);
104 outb(val, ioreg + 1);
436cad2a
JD		 105}
106
3c2e3512 107static int superio_inw(int ioreg, int reg)
1da177e4
LT		 108{
109 int val;
3c2e3512
GR		 110 outb(reg++, ioreg);
111 val = inb(ioreg + 1) << 8;
112 outb(reg, ioreg);
113 val |= inb(ioreg + 1);
1da177e4
LT		 114 return val;
115}
116
3c2e3512 117static inline void superio_select(int ioreg, int ldn)
1da177e4 118{
3c2e3512
GR		 119 outb(DEV, ioreg);
120 outb(ldn, ioreg + 1);
1da177e4
LT		 121}
122
3c2e3512 123static inline int superio_enter(int ioreg)
1da177e4 124{
5b0380c9 125 /*
3c2e3512 126 * Try to reserve ioreg and ioreg + 1 for exclusive access.
5b0380c9 127 */
3c2e3512 128 if (!request_muxed_region(ioreg, 2, DRVNAME))
5b0380c9
NG		 129 return -EBUSY;
130
3c2e3512
GR		 131 outb(0x87, ioreg);
132 outb(0x01, ioreg);
133 outb(0x55, ioreg);
e84bd953 134 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
5b0380c9 135 return 0;
1da177e4
LT		 136}
137
3c2e3512 138static inline void superio_exit(int ioreg)
1da177e4 139{
3c2e3512
GR		 140 outb(0x02, ioreg);
141 outb(0x02, ioreg + 1);
142 release_region(ioreg, 2);
1da177e4
LT		 143}
144
87673dd7 145/* Logical device 4 registers */
1da177e4
LT		 146#define IT8712F_DEVID 0x8712
147#define IT8705F_DEVID 0x8705
17d648bf 148#define IT8716F_DEVID 0x8716
87673dd7 149#define IT8718F_DEVID 0x8718
b4da93e4 150#define IT8720F_DEVID 0x8720
44c1bcd4 151#define IT8721F_DEVID 0x8721
08a8f6e9 152#define IT8726F_DEVID 0x8726
16b5dda2 153#define IT8728F_DEVID 0x8728
ead80803 154#define IT8732F_DEVID 0x8732
b0636707
GR		 155#define IT8771E_DEVID 0x8771
156#define IT8772E_DEVID 0x8772
7bc32d29 157#define IT8781F_DEVID 0x8781
0531d98b
GR		 158#define IT8782F_DEVID 0x8782
159#define IT8783E_DEVID 0x8783
a0c1424a 160#define IT8786E_DEVID 0x8786
4ee07157 161#define IT8790E_DEVID 0x8790
7183ae8c 162#define IT8603E_DEVID 0x8603
3ba9d977 163#define IT8620E_DEVID 0x8620
574e9bd8 164#define IT8623E_DEVID 0x8623
1da177e4
LT		 165#define IT87_ACT_REG 0x30
166#define IT87_BASE_REG 0x60
167
87673dd7 168/* Logical device 7 registers (IT8712F and later) */
0531d98b 169#define IT87_SIO_GPIO1_REG 0x25
3ba9d977 170#define IT87_SIO_GPIO2_REG 0x26
895ff267 171#define IT87_SIO_GPIO3_REG 0x27
36c4d98a 172#define IT87_SIO_GPIO4_REG 0x28
591ec650 173#define IT87_SIO_GPIO5_REG 0x29
0531d98b 174#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
87673dd7 175#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
0531d98b 176#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
87673dd7 177#define IT87_SIO_VID_REG 0xfc /* VID value */
d9b327c3 178#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
87673dd7 179
1da177e4 180/* Update battery voltage after every reading if true */
90ab5ee9 181static bool update_vbat;
1da177e4
LT		 182
183/* Not all BIOSes properly configure the PWM registers */
90ab5ee9 184static bool fix_pwm_polarity;
1da177e4 185
1da177e4
LT		 186/* Many IT87 constants specified below */
187
188/* Length of ISA address segment */
189#define IT87_EXTENT 8
190
87b4b663
BH		 191/* Length of ISA address segment for Environmental Controller */
192#define IT87_EC_EXTENT 2
193
194/* Offset of EC registers from ISA base address */
195#define IT87_EC_OFFSET 5
196
197/* Where are the ISA address/data registers relative to the EC base address */
198#define IT87_ADDR_REG_OFFSET 0
199#define IT87_DATA_REG_OFFSET 1
1da177e4
LT		 200
201/*----- The IT87 registers -----*/
202
203#define IT87_REG_CONFIG 0x00
204
205#define IT87_REG_ALARM1 0x01
206#define IT87_REG_ALARM2 0x02
207#define IT87_REG_ALARM3 0x03
208
4a0d71cf
GR		 209/*
210 * The IT8718F and IT8720F have the VID value in a different register, in
211 * Super-I/O configuration space.
212 */
1da177e4 213#define IT87_REG_VID 0x0a
4a0d71cf
GR		 214/*
215 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
216 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
217 * mode.
218 */
1da177e4 219#define IT87_REG_FAN_DIV 0x0b
17d648bf 220#define IT87_REG_FAN_16BIT 0x0c
1da177e4
LT		 221
222/* Monitors: 9 voltage (0 to 7, battery), 3 temp (1 to 3), 3 fan (1 to 3) */
223
fa3f70d6
GR		 224static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
225static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
226static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
227static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
228static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
161d898a 229
1da177e4
LT		 230#define IT87_REG_FAN_MAIN_CTRL 0x13
231#define IT87_REG_FAN_CTL 0x14
36c4d98a
GR		 232static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
233static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
1da177e4
LT		 234
235#define IT87_REG_VIN(nr) (0x20 + (nr))
236#define IT87_REG_TEMP(nr) (0x29 + (nr))
237
73055405
GR		 238#define IT87_REG_AVCC3 0x2f
239
1da177e4
LT		 240#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
241#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
242#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
243#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
244
1da177e4
LT		 245#define IT87_REG_VIN_ENABLE 0x50
246#define IT87_REG_TEMP_ENABLE 0x51
4573acbc 247#define IT87_REG_TEMP_EXTRA 0x55
d9b327c3 248#define IT87_REG_BEEP_ENABLE 0x5c
1da177e4
LT		 249
250#define IT87_REG_CHIPID 0x58
251
4f3f51bc
JD		 252#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i))
253#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i))
254
483db43e
GR		 255struct it87_devices {
256 const char *name;
faf392fb 257 const char * const suffix;
483db43e 258 u16 features;
19529784
GR		 259 u8 peci_mask;
260 u8 old_peci_mask;
483db43e
GR		 261};
262
263#define FEAT_12MV_ADC (1 << 0)
264#define FEAT_NEWER_AUTOPWM (1 << 1)
265#define FEAT_OLD_AUTOPWM (1 << 2)
266#define FEAT_16BIT_FANS (1 << 3)
267#define FEAT_TEMP_OFFSET (1 << 4)
5d8d2f2b 268#define FEAT_TEMP_PECI (1 << 5)
19529784 269#define FEAT_TEMP_OLD_PECI (1 << 6)
9faf28ca
GR		 270#define FEAT_FAN16_CONFIG (1 << 7) /* Need to enable 16-bit fans */
271#define FEAT_FIVE_FANS (1 << 8) /* Supports five fans */
32dd7c40 272#define FEAT_VID (1 << 9) /* Set if chip supports VID */
7f5726c3 273#define FEAT_IN7_INTERNAL (1 << 10) /* Set if in7 is internal */
fa3f70d6 274#define FEAT_SIX_FANS (1 << 11) /* Supports six fans */
ead80803 275#define FEAT_10_9MV_ADC (1 << 12)
73055405 276#define FEAT_AVCC3 (1 << 13) /* Chip supports in9/AVCC3 */
36c4d98a 277#define FEAT_SIX_PWM (1 << 14) /* Chip supports 6 pwm chn */
60878bcf 278#define FEAT_PWM_FREQ2 (1 << 15) /* Separate pwm freq 2 */
483db43e
GR		 279
280static const struct it87_devices it87_devices[] = {
281 [it87] = {
282 .name = "it87",
faf392fb 283 .suffix = "F",
483db43e
GR		 284 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
285 },
286 [it8712] = {
287 .name = "it8712",
faf392fb 288 .suffix = "F",
32dd7c40
GR		 289 .features = FEAT_OLD_AUTOPWM | FEAT_VID,
290 /* may need to overwrite */
483db43e
GR		 291 },
292 [it8716] = {
293 .name = "it8716",
faf392fb 294 .suffix = "F",
32dd7c40 295 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf 296 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
483db43e
GR		 297 },
298 [it8718] = {
299 .name = "it8718",
faf392fb 300 .suffix = "F",
32dd7c40 301 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf
GR		 302 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
303 | FEAT_PWM_FREQ2,
19529784 304 .old_peci_mask = 0x4,
483db43e
GR		 305 },
306 [it8720] = {
307 .name = "it8720",
faf392fb 308 .suffix = "F",
32dd7c40 309 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf
GR		 310 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
311 | FEAT_PWM_FREQ2,
19529784 312 .old_peci_mask = 0x4,
483db43e
GR		 313 },
314 [it8721] = {
315 .name = "it8721",
faf392fb 316 .suffix = "F",
483db43e 317 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
9faf28ca 318 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
60878bcf
GR		 319 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
320 | FEAT_PWM_FREQ2,
5d8d2f2b 321 .peci_mask = 0x05,
19529784 322 .old_peci_mask = 0x02, /* Actually reports PCH */
483db43e
GR		 323 },
324 [it8728] = {
325 .name = "it8728",
faf392fb 326 .suffix = "F",
483db43e 327 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
7f5726c3 328 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
60878bcf 329 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
5d8d2f2b 330 .peci_mask = 0x07,
483db43e 331 },
ead80803
JM		 332 [it8732] = {
333 .name = "it8732",
334 .suffix = "F",
335 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
336 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
337 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
338 .peci_mask = 0x07,
339 .old_peci_mask = 0x02, /* Actually reports PCH */
340 },
b0636707
GR		 341 [it8771] = {
342 .name = "it8771",
faf392fb 343 .suffix = "E",
b0636707 344 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 345 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
346 | FEAT_PWM_FREQ2,
9faf28ca
GR		 347 /* PECI: guesswork */
348 /* 12mV ADC (OHM) */
349 /* 16 bit fans (OHM) */
350 /* three fans, always 16 bit (guesswork) */
b0636707
GR		 351 .peci_mask = 0x07,
352 },
353 [it8772] = {
354 .name = "it8772",
faf392fb 355 .suffix = "E",
b0636707 356 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 357 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
358 | FEAT_PWM_FREQ2,
9faf28ca
GR		 359 /* PECI (coreboot) */
360 /* 12mV ADC (HWSensors4, OHM) */
361 /* 16 bit fans (HWSensors4, OHM) */
362 /* three fans, always 16 bit (datasheet) */
b0636707
GR		 363 .peci_mask = 0x07,
364 },
7bc32d29
GR		 365 [it8781] = {
366 .name = "it8781",
faf392fb 367 .suffix = "F",
7bc32d29 368 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 369 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
7bc32d29
GR		 370 .old_peci_mask = 0x4,
371 },
483db43e
GR		 372 [it8782] = {
373 .name = "it8782",
faf392fb 374 .suffix = "F",
19529784 375 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 376 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
19529784 377 .old_peci_mask = 0x4,
483db43e
GR		 378 },
379 [it8783] = {
380 .name = "it8783",
faf392fb 381 .suffix = "E/F",
19529784 382 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 383 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
19529784 384 .old_peci_mask = 0x4,
483db43e 385 },
a0c1424a
TL		 386 [it8786] = {
387 .name = "it8786",
faf392fb 388 .suffix = "E",
a0c1424a 389 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 390 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
391 | FEAT_PWM_FREQ2,
a0c1424a
TL		 392 .peci_mask = 0x07,
393 },
4ee07157
GR		 394 [it8790] = {
395 .name = "it8790",
396 .suffix = "E",
397 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 398 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
399 | FEAT_PWM_FREQ2,
4ee07157
GR		 400 .peci_mask = 0x07,
401 },
c145d5c6
RM		 402 [it8603] = {
403 .name = "it8603",
faf392fb 404 .suffix = "E",
c145d5c6 405 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
73055405 406 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
60878bcf 407 | FEAT_AVCC3 | FEAT_PWM_FREQ2,
c145d5c6
RM		 408 .peci_mask = 0x07,
409 },
3ba9d977
GR		 410 [it8620] = {
411 .name = "it8620",
412 .suffix = "E",
413 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
fa3f70d6 414 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
60878bcf 415 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2,
3ba9d977
GR		 416 .peci_mask = 0x07,
417 },
483db43e
GR		 418};
419
420#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
421#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
ead80803 422#define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
483db43e
GR		 423#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
424#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
425#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
5d8d2f2b
GR		 426#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
427 ((data)->peci_mask & (1 << nr)))
19529784
GR		 428#define has_temp_old_peci(data, nr) \
429 (((data)->features & FEAT_TEMP_OLD_PECI) && \
430 ((data)->old_peci_mask & (1 << nr)))
9faf28ca 431#define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
fa3f70d6
GR		 432#define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
433 FEAT_SIX_FANS))
32dd7c40 434#define has_vid(data) ((data)->features & FEAT_VID)
7f5726c3 435#define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
fa3f70d6 436#define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
73055405 437#define has_avcc3(data) ((data)->features & FEAT_AVCC3)
36c4d98a 438#define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
60878bcf 439#define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
1da177e4 440
b74f3fdd 441struct it87_sio_data {
442 enum chips type;
443 /* Values read from Super-I/O config space */
0475169c 444 u8 revision;
b74f3fdd 445 u8 vid_value;
d9b327c3 446 u8 beep_pin;
738e5e05 447 u8 internal; /* Internal sensors can be labeled */
591ec650 448 /* Features skipped based on config or DMI */
9172b5d1 449 u16 skip_in;
895ff267 450 u8 skip_vid;
591ec650 451 u8 skip_fan;
98dd22c3 452 u8 skip_pwm;
4573acbc 453 u8 skip_temp;
b74f3fdd 454};
455
4a0d71cf
GR		 456/*
457 * For each registered chip, we need to keep some data in memory.
458 * The structure is dynamically allocated.
459 */
1da177e4 460struct it87_data {
8638d0af 461 const struct attribute_group *groups[7];
1da177e4 462 enum chips type;
483db43e 463 u16 features;
19529784
GR		 464 u8 peci_mask;
465 u8 old_peci_mask;
1da177e4 466
b74f3fdd 467 unsigned short addr;
468 const char *name;
9a61bf63 469 struct mutex update_lock;
1da177e4
LT		 470 char valid; /* !=0 if following fields are valid */
471 unsigned long last_updated; /* In jiffies */
472
44c1bcd4 473 u16 in_scaled; /* Internal voltage sensors are scaled */
d3766848 474 u16 in_internal; /* Bitfield, internal sensors (for labels) */
52929715 475 u16 has_in; /* Bitfield, voltage sensors enabled */
c145d5c6 476 u8 in[10][3]; /* [nr][0]=in, [1]=min, [2]=max */
9060f8bd 477 u8 has_fan; /* Bitfield, fans enabled */
fa3f70d6 478 u16 fan[6][2]; /* Register values, [nr][0]=fan, [1]=min */
4573acbc 479 u8 has_temp; /* Bitfield, temp sensors enabled */
161d898a 480 s8 temp[3][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
19529784
GR		 481 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
482 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
1da177e4 483 u8 fan_div[3]; /* Register encoding, shifted right */
d3766848 484 bool has_vid; /* True if VID supported */
1da177e4 485 u8 vid; /* Register encoding, combined */
a7be58a1 486 u8 vrm;
1da177e4 487 u32 alarms; /* Register encoding, combined */
52929715 488 bool has_beep; /* true if beep supported */
d9b327c3 489 u8 beeps; /* Register encoding */
1da177e4 490 u8 fan_main_ctrl; /* Register value */
f8d0c19a 491 u8 fan_ctl; /* Register value */
b99883dc 492
4a0d71cf
GR		 493 /*
494 * The following 3 arrays correspond to the same registers up to
6229cdb2
JD		 495 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
496 * 7, and we want to preserve settings on mode changes, so we have
497 * to track all values separately.
498 * Starting with the IT8721F, the manual PWM duty cycles are stored
499 * in separate registers (8-bit values), so the separate tracking
500 * is no longer needed, but it is still done to keep the driver
4a0d71cf
GR		 501 * simple.
502 */
5c391261 503 u8 has_pwm; /* Bitfield, pwm control enabled */
36c4d98a
GR		 504 u8 pwm_ctrl[6]; /* Register value */
505 u8 pwm_duty[6]; /* Manual PWM value set by user */
506 u8 pwm_temp_map[6]; /* PWM to temp. chan. mapping (bits 1-0) */
4f3f51bc
JD		 507
508 /* Automatic fan speed control registers */
509 u8 auto_pwm[3][4]; /* [nr][3] is hard-coded */
510 s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */
1da177e4 511};
0df6454d 512
0531d98b 513static int adc_lsb(const struct it87_data *data, int nr)
44c1bcd4 514{
ead80803
JM		 515 int lsb;
516
517 if (has_12mv_adc(data))
518 lsb = 120;
519 else if (has_10_9mv_adc(data))
520 lsb = 109;
521 else
522 lsb = 160;
0531d98b
GR		 523 if (data->in_scaled & (1 << nr))
524 lsb <<= 1;
525 return lsb;
526}
44c1bcd4 527
0531d98b
GR		 528static u8 in_to_reg(const struct it87_data *data, int nr, long val)
529{
ead80803 530 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
2a844c14 531 return clamp_val(val, 0, 255);
44c1bcd4
JD		 532}
533
534static int in_from_reg(const struct it87_data *data, int nr, int val)
535{
ead80803 536 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
44c1bcd4 537}
0df6454d
JD		 538
539static inline u8 FAN_TO_REG(long rpm, int div)
540{
541 if (rpm == 0)
542 return 255;
2a844c14
GR		 543 rpm = clamp_val(rpm, 1, 1000000);
544 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
0df6454d
JD		 545}
546
547static inline u16 FAN16_TO_REG(long rpm)
548{
549 if (rpm == 0)
550 return 0xffff;
2a844c14 551 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
0df6454d
JD		 552}
553
554#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
555 1350000 / ((val) * (div)))
556/* The divider is fixed to 2 in 16-bit mode */
557#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
558 1350000 / ((val) * 2))
559
2a844c14
GR		 560#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
561 ((val) + 500) / 1000), -128, 127))
0df6454d
JD		 562#define TEMP_FROM_REG(val) ((val) * 1000)
563
44c1bcd4
JD		 564static u8 pwm_to_reg(const struct it87_data *data, long val)
565{
16b5dda2 566 if (has_newer_autopwm(data))
44c1bcd4
JD		 567 return val;
568 else
569 return val >> 1;
570}
571
572static int pwm_from_reg(const struct it87_data *data, u8 reg)
573{
16b5dda2 574 if (has_newer_autopwm(data))
44c1bcd4
JD		 575 return reg;
576 else
577 return (reg & 0x7f) << 1;
578}
579
0df6454d
JD		 580
581static int DIV_TO_REG(int val)
582{
583 int answer = 0;
584 while (answer < 7 && (val >>= 1))
585 answer++;
586 return answer;
587}
588#define DIV_FROM_REG(val) (1 << (val))
589
f56c9c0a
GR		 590/*
591 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
592 * depending on the chip type, to calculate the actual PWM frequency.
593 *
594 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
595 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
596 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
597 * sometimes just one. It is unknown if this is a datasheet error or real,
598 * so this is ignored for now.
599 */
0df6454d 600static const unsigned int pwm_freq[8] = {
f56c9c0a
GR		 601 48000000,
602 24000000,
603 12000000,
604 8000000,
605 6000000,
606 3000000,
607 1500000,
608 750000,
0df6454d 609};
1da177e4 610
c1e7a4ca
GR		 611/*
612 * Must be called with data->update_lock held, except during initialization.
613 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
614 * would slow down the IT87 access and should not be necessary.
615 */
616static int it87_read_value(struct it87_data *data, u8 reg)
617{
618 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
619 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
620}
621
622/*
623 * Must be called with data->update_lock held, except during initialization.
624 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
625 * would slow down the IT87 access and should not be necessary.
626 */
627static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
628{
629 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
630 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
631}
632
633static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
634{
635 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
636 if (has_newer_autopwm(data)) {
637 data->pwm_temp_map[nr] = (data->pwm_ctrl[nr] & 0x03) +
638 nr < 3 ? 0 : 3;
639 data->pwm_duty[nr] = it87_read_value(data,
640 IT87_REG_PWM_DUTY[nr]);
641 } else {
642 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
643 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
644 else /* Manual mode */
645 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
646 }
1da177e4 647
c1e7a4ca
GR		 648 if (has_old_autopwm(data)) {
649 int i;
1da177e4 650
c1e7a4ca
GR		 651 for (i = 0; i < 5 ; i++)
652 data->auto_temp[nr][i] = it87_read_value(data,
653 IT87_REG_AUTO_TEMP(nr, i));
654 for (i = 0; i < 3 ; i++)
655 data->auto_pwm[nr][i] = it87_read_value(data,
656 IT87_REG_AUTO_PWM(nr, i));
657 }
658}
1da177e4 659
c1e7a4ca
GR		 660static struct it87_data *it87_update_device(struct device *dev)
661{
662 struct it87_data *data = dev_get_drvdata(dev);
663 int i;
664
665 mutex_lock(&data->update_lock);
666
667 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
668 || !data->valid) {
669 if (update_vbat) {
670 /*
671 * Cleared after each update, so reenable. Value
672 * returned by this read will be previous value
673 */
674 it87_write_value(data, IT87_REG_CONFIG,
675 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
676 }
677 for (i = 0; i <= 7; i++) {
678 data->in[i][0] =
679 it87_read_value(data, IT87_REG_VIN(i));
680 data->in[i][1] =
681 it87_read_value(data, IT87_REG_VIN_MIN(i));
682 data->in[i][2] =
683 it87_read_value(data, IT87_REG_VIN_MAX(i));
684 }
685 /* in8 (battery) has no limit registers */
686 data->in[8][0] = it87_read_value(data, IT87_REG_VIN(8));
687 if (has_avcc3(data))
688 data->in[9][0] = it87_read_value(data, IT87_REG_AVCC3);
689
690 for (i = 0; i < 6; i++) {
691 /* Skip disabled fans */
692 if (!(data->has_fan & (1 << i)))
693 continue;
694
695 data->fan[i][1] =
696 it87_read_value(data, IT87_REG_FAN_MIN[i]);
697 data->fan[i][0] = it87_read_value(data,
698 IT87_REG_FAN[i]);
699 /* Add high byte if in 16-bit mode */
700 if (has_16bit_fans(data)) {
701 data->fan[i][0] |= it87_read_value(data,
702 IT87_REG_FANX[i]) << 8;
703 data->fan[i][1] |= it87_read_value(data,
704 IT87_REG_FANX_MIN[i]) << 8;
705 }
706 }
707 for (i = 0; i < 3; i++) {
708 if (!(data->has_temp & (1 << i)))
709 continue;
710 data->temp[i][0] =
711 it87_read_value(data, IT87_REG_TEMP(i));
712 data->temp[i][1] =
713 it87_read_value(data, IT87_REG_TEMP_LOW(i));
714 data->temp[i][2] =
715 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
716 if (has_temp_offset(data))
717 data->temp[i][3] =
718 it87_read_value(data,
719 IT87_REG_TEMP_OFFSET[i]);
720 }
721
722 /* Newer chips don't have clock dividers */
723 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
724 i = it87_read_value(data, IT87_REG_FAN_DIV);
725 data->fan_div[0] = i & 0x07;
726 data->fan_div[1] = (i >> 3) & 0x07;
727 data->fan_div[2] = (i & 0x40) ? 3 : 1;
728 }
729
730 data->alarms =
731 it87_read_value(data, IT87_REG_ALARM1) |
732 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
733 (it87_read_value(data, IT87_REG_ALARM3) << 16);
734 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
735
736 data->fan_main_ctrl = it87_read_value(data,
737 IT87_REG_FAN_MAIN_CTRL);
738 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
739 for (i = 0; i < 6; i++)
740 it87_update_pwm_ctrl(data, i);
741
742 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
743 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
744 /*
745 * The IT8705F does not have VID capability.
746 * The IT8718F and later don't use IT87_REG_VID for the
747 * same purpose.
748 */
749 if (data->type == it8712 || data->type == it8716) {
750 data->vid = it87_read_value(data, IT87_REG_VID);
751 /*
752 * The older IT8712F revisions had only 5 VID pins,
753 * but we assume it is always safe to read 6 bits.
754 */
755 data->vid &= 0x3f;
756 }
757 data->last_updated = jiffies;
758 data->valid = 1;
759 }
760
761 mutex_unlock(&data->update_lock);
762
763 return data;
764}
fde09509 765
20ad93d4 766static ssize_t show_in(struct device *dev, struct device_attribute *attr,
929c6a56 767 char *buf)
1da177e4 768{
929c6a56
GR		 769 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
770 int nr = sattr->nr;
771 int index = sattr->index;
20ad93d4 772
1da177e4 773 struct it87_data *data = it87_update_device(dev);
929c6a56 774 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1da177e4
LT		 775}
776
929c6a56
GR		 777static ssize_t set_in(struct device *dev, struct device_attribute *attr,
778 const char *buf, size_t count)
1da177e4 779{
929c6a56
GR		 780 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
781 int nr = sattr->nr;
782 int index = sattr->index;
20ad93d4 783
b74f3fdd 784 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 785 unsigned long val;
786
179c4fdb 787 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 788 return -EINVAL;
1da177e4 789
9a61bf63 790 mutex_lock(&data->update_lock);
929c6a56
GR		 791 data->in[nr][index] = in_to_reg(data, nr, val);
792 it87_write_value(data,
793 index == 1 ? IT87_REG_VIN_MIN(nr)
794 : IT87_REG_VIN_MAX(nr),
795 data->in[nr][index]);
9a61bf63 796 mutex_unlock(&data->update_lock);
1da177e4
LT		 797 return count;
798}
20ad93d4 799
929c6a56
GR		 800static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
801static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
802 0, 1);
803static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
804 0, 2);
f5f64501 805
929c6a56
GR		 806static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
807static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
808 1, 1);
809static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
810 1, 2);
1da177e4 811
929c6a56
GR		 812static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
813static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
814 2, 1);
815static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
816 2, 2);
1da177e4 817
929c6a56
GR		 818static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
819static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
820 3, 1);
821static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
822 3, 2);
823
824static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
825static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
826 4, 1);
827static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
828 4, 2);
829
830static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
831static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
832 5, 1);
833static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
834 5, 2);
835
836static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
837static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
838 6, 1);
839static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
840 6, 2);
841
842static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
843static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
844 7, 1);
845static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
846 7, 2);
847
848static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
c145d5c6 849static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1da177e4
LT		 850
851/* 3 temperatures */
20ad93d4 852static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
60ca385a 853 char *buf)
1da177e4 854{
60ca385a
GR		 855 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
856 int nr = sattr->nr;
857 int index = sattr->index;
1da177e4 858 struct it87_data *data = it87_update_device(dev);
20ad93d4 859
60ca385a 860 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1da177e4 861}
20ad93d4 862
60ca385a
GR		 863static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
864 const char *buf, size_t count)
1da177e4 865{
60ca385a
GR		 866 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
867 int nr = sattr->nr;
868 int index = sattr->index;
b74f3fdd 869 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 870 long val;
161d898a 871 u8 reg, regval;
f5f64501 872
179c4fdb 873 if (kstrtol(buf, 10, &val) < 0)
f5f64501 874 return -EINVAL;
1da177e4 875
9a61bf63 876 mutex_lock(&data->update_lock);
161d898a
GR		 877
878 switch (index) {
879 default:
880 case 1:
881 reg = IT87_REG_TEMP_LOW(nr);
882 break;
883 case 2:
884 reg = IT87_REG_TEMP_HIGH(nr);
885 break;
886 case 3:
887 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
888 if (!(regval & 0x80)) {
889 regval |= 0x80;
890 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
891 }
892 data->valid = 0;
893 reg = IT87_REG_TEMP_OFFSET[nr];
894 break;
895 }
896
60ca385a 897 data->temp[nr][index] = TEMP_TO_REG(val);
161d898a 898 it87_write_value(data, reg, data->temp[nr][index]);
9a61bf63 899 mutex_unlock(&data->update_lock);
1da177e4
LT		 900 return count;
901}
1da177e4 902
60ca385a
GR		 903static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
904static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
905 0, 1);
906static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
907 0, 2);
161d898a
GR		 908static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
909 set_temp, 0, 3);
60ca385a
GR		 910static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
911static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
912 1, 1);
913static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
914 1, 2);
161d898a
GR		 915static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
916 set_temp, 1, 3);
60ca385a
GR		 917static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
918static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
919 2, 1);
920static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
921 2, 2);
161d898a
GR		 922static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
923 set_temp, 2, 3);
1da177e4 924
2cece01f
GR		 925static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
926 char *buf)
1da177e4 927{
20ad93d4
JD		 928 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
929 int nr = sensor_attr->index;
1da177e4 930 struct it87_data *data = it87_update_device(dev);
4a0d71cf 931 u8 reg = data->sensor; /* In case value is updated while used */
19529784 932 u8 extra = data->extra;
5f2dc798 933
19529784
GR		 934 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1))
935 || (has_temp_old_peci(data, nr) && (extra & 0x80)))
5d8d2f2b 936 return sprintf(buf, "6\n"); /* Intel PECI */
1da177e4
LT		 937 if (reg & (1 << nr))
938 return sprintf(buf, "3\n"); /* thermal diode */
939 if (reg & (8 << nr))
4ed10779 940 return sprintf(buf, "4\n"); /* thermistor */
1da177e4
LT		 941 return sprintf(buf, "0\n"); /* disabled */
942}
2cece01f
GR		 943
944static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
945 const char *buf, size_t count)
1da177e4 946{
20ad93d4
JD		 947 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
948 int nr = sensor_attr->index;
949
b74f3fdd 950 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 951 long val;
19529784 952 u8 reg, extra;
f5f64501 953
179c4fdb 954 if (kstrtol(buf, 10, &val) < 0)
f5f64501 955 return -EINVAL;
1da177e4 956
8acf07c5
JD		 957 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
958 reg &= ~(1 << nr);
959 reg &= ~(8 << nr);
5d8d2f2b
GR		 960 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
961 reg &= 0x3f;
19529784
GR		 962 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
963 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
964 extra &= 0x7f;
4ed10779 965 if (val == 2) { /* backwards compatibility */
1d9bcf6a
GR		 966 dev_warn(dev,
967 "Sensor type 2 is deprecated, please use 4 instead\n");
4ed10779
JD		 968 val = 4;
969 }
5d8d2f2b 970 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1da177e4 971 if (val == 3)
8acf07c5 972 reg |= 1 << nr;
4ed10779 973 else if (val == 4)
8acf07c5 974 reg |= 8 << nr;
5d8d2f2b
GR		 975 else if (has_temp_peci(data, nr) && val == 6)
976 reg |= (nr + 1) << 6;
19529784
GR		 977 else if (has_temp_old_peci(data, nr) && val == 6)
978 extra |= 0x80;
8acf07c5 979 else if (val != 0)
1da177e4 980 return -EINVAL;
8acf07c5
JD		 981
982 mutex_lock(&data->update_lock);
983 data->sensor = reg;
19529784 984 data->extra = extra;
b74f3fdd 985 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
19529784
GR		 986 if (has_temp_old_peci(data, nr))
987 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
2b3d1d87 988 data->valid = 0; /* Force cache refresh */
9a61bf63 989 mutex_unlock(&data->update_lock);
1da177e4
LT		 990 return count;
991}
1da177e4 992
2cece01f
GR		 993static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
994 set_temp_type, 0);
995static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
996 set_temp_type, 1);
997static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
998 set_temp_type, 2);
1da177e4
LT		 999
1000/* 3 Fans */
b99883dc
JD		 1001
1002static int pwm_mode(const struct it87_data *data, int nr)
1003{
1004 int ctrl = data->fan_main_ctrl & (1 << nr);
1005
c145d5c6 1006 if (ctrl == 0 && data->type != it8603) /* Full speed */
b99883dc
JD		 1007 return 0;
1008 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
1009 return 2;
1010 else /* Manual mode */
1011 return 1;
1012}
1013
20ad93d4 1014static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
e1169ba0 1015 char *buf)
1da177e4 1016{
e1169ba0
GR		 1017 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1018 int nr = sattr->nr;
1019 int index = sattr->index;
1020 int speed;
1da177e4 1021 struct it87_data *data = it87_update_device(dev);
20ad93d4 1022
e1169ba0
GR		 1023 speed = has_16bit_fans(data) ?
1024 FAN16_FROM_REG(data->fan[nr][index]) :
1025 FAN_FROM_REG(data->fan[nr][index],
1026 DIV_FROM_REG(data->fan_div[nr]));
1027 return sprintf(buf, "%d\n", speed);
1da177e4 1028}
e1169ba0 1029
20ad93d4
JD		 1030static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1031 char *buf)
1da177e4 1032{
20ad93d4
JD		 1033 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1034 int nr = sensor_attr->index;
1035
1da177e4
LT		 1036 struct it87_data *data = it87_update_device(dev);
1037 return sprintf(buf, "%d\n", DIV_FROM_REG(data->fan_div[nr]));
1038}
5f2dc798
JD		 1039static ssize_t show_pwm_enable(struct device *dev,
1040 struct device_attribute *attr, char *buf)
1da177e4 1041{
20ad93d4
JD		 1042 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1043 int nr = sensor_attr->index;
1044
1da177e4 1045 struct it87_data *data = it87_update_device(dev);
b99883dc 1046 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1da177e4 1047}
20ad93d4
JD		 1048static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1049 char *buf)
1da177e4 1050{
20ad93d4
JD		 1051 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1052 int nr = sensor_attr->index;
1053
1da177e4 1054 struct it87_data *data = it87_update_device(dev);
44c1bcd4
JD		 1055 return sprintf(buf, "%d\n",
1056 pwm_from_reg(data, data->pwm_duty[nr]));
1da177e4 1057}
f8d0c19a
JD		 1058static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1059 char *buf)
1060{
60878bcf 1061 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
f8d0c19a 1062 struct it87_data *data = it87_update_device(dev);
60878bcf 1063 int nr = sensor_attr->index;
f56c9c0a 1064 unsigned int freq;
60878bcf
GR		 1065 int index;
1066
1067 if (has_pwm_freq2(data) && nr == 1)
1068 index = (data->extra >> 4) & 0x07;
1069 else
1070 index = (data->fan_ctl >> 4) & 0x07;
f8d0c19a 1071
f56c9c0a
GR		 1072 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1073
1074 return sprintf(buf, "%u\n", freq);
f8d0c19a 1075}
e1169ba0
GR		 1076
1077static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1078 const char *buf, size_t count)
1da177e4 1079{
e1169ba0
GR		 1080 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1081 int nr = sattr->nr;
1082 int index = sattr->index;
20ad93d4 1083
b74f3fdd 1084 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1085 long val;
7f999aa7 1086 u8 reg;
1da177e4 1087
179c4fdb 1088 if (kstrtol(buf, 10, &val) < 0)
f5f64501
JD		 1089 return -EINVAL;
1090
9a61bf63 1091 mutex_lock(&data->update_lock);
e1169ba0
GR		 1092
1093 if (has_16bit_fans(data)) {
1094 data->fan[nr][index] = FAN16_TO_REG(val);
1095 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1096 data->fan[nr][index] & 0xff);
1097 it87_write_value(data, IT87_REG_FANX_MIN[nr],
1098 data->fan[nr][index] >> 8);
1099 } else {
1100 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1101 switch (nr) {
1102 case 0:
1103 data->fan_div[nr] = reg & 0x07;
1104 break;
1105 case 1:
1106 data->fan_div[nr] = (reg >> 3) & 0x07;
1107 break;
1108 case 2:
1109 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1110 break;
1111 }
1112 data->fan[nr][index] =
1113 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1114 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1115 data->fan[nr][index]);
07eab46d
JD		 1116 }
1117
9a61bf63 1118 mutex_unlock(&data->update_lock);
1da177e4
LT		 1119 return count;
1120}
e1169ba0 1121
20ad93d4
JD		 1122static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1123 const char *buf, size_t count)
1da177e4 1124{
20ad93d4
JD		 1125 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1126 int nr = sensor_attr->index;
1127
b74f3fdd 1128 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1129 unsigned long val;
8ab4ec3e 1130 int min;
1da177e4
LT		 1131 u8 old;
1132
179c4fdb 1133 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 1134 return -EINVAL;
1135
9a61bf63 1136 mutex_lock(&data->update_lock);
b74f3fdd 1137 old = it87_read_value(data, IT87_REG_FAN_DIV);
1da177e4 1138
8ab4ec3e 1139 /* Save fan min limit */
e1169ba0 1140 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1da177e4
LT		 1141
1142 switch (nr) {
1143 case 0:
1144 case 1:
1145 data->fan_div[nr] = DIV_TO_REG(val);
1146 break;
1147 case 2:
1148 if (val < 8)
1149 data->fan_div[nr] = 1;
1150 else
1151 data->fan_div[nr] = 3;
1152 }
1153 val = old & 0x80;
1154 val |= (data->fan_div[0] & 0x07);
1155 val |= (data->fan_div[1] & 0x07) << 3;
1156 if (data->fan_div[2] == 3)
1157 val |= 0x1 << 6;
b74f3fdd 1158 it87_write_value(data, IT87_REG_FAN_DIV, val);
1da177e4 1159
8ab4ec3e 1160 /* Restore fan min limit */
e1169ba0
GR		 1161 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1162 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
8ab4ec3e 1163
9a61bf63 1164 mutex_unlock(&data->update_lock);
1da177e4
LT		 1165 return count;
1166}
cccfc9c4
JD		 1167
1168/* Returns 0 if OK, -EINVAL otherwise */
1169static int check_trip_points(struct device *dev, int nr)
1170{
1171 const struct it87_data *data = dev_get_drvdata(dev);
1172 int i, err = 0;
1173
1174 if (has_old_autopwm(data)) {
1175 for (i = 0; i < 3; i++) {
1176 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1177 err = -EINVAL;
1178 }
1179 for (i = 0; i < 2; i++) {
1180 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1181 err = -EINVAL;
1182 }
1183 }
1184
1185 if (err) {
1d9bcf6a
GR		 1186 dev_err(dev,
1187 "Inconsistent trip points, not switching to automatic mode\n");
cccfc9c4
JD		 1188 dev_err(dev, "Adjust the trip points and try again\n");
1189 }
1190 return err;
1191}
1192
20ad93d4
JD		 1193static ssize_t set_pwm_enable(struct device *dev,
1194 struct device_attribute *attr, const char *buf, size_t count)
1da177e4 1195{
20ad93d4
JD		 1196 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1197 int nr = sensor_attr->index;
1198
b74f3fdd 1199 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1200 long val;
1da177e4 1201
179c4fdb 1202 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
b99883dc
JD		 1203 return -EINVAL;
1204
cccfc9c4
JD		 1205 /* Check trip points before switching to automatic mode */
1206 if (val == 2) {
1207 if (check_trip_points(dev, nr) < 0)
1208 return -EINVAL;
1209 }
1210
c145d5c6
RM		 1211 /* IT8603E does not have on/off mode */
1212 if (val == 0 && data->type == it8603)
1213 return -EINVAL;
1214
9a61bf63 1215 mutex_lock(&data->update_lock);
1da177e4
LT		 1216
1217 if (val == 0) {
1218 int tmp;
1219 /* make sure the fan is on when in on/off mode */
b74f3fdd 1220 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1221 it87_write_value(data, IT87_REG_FAN_CTL, tmp | (1 << nr));
1da177e4
LT		 1222 /* set on/off mode */
1223 data->fan_main_ctrl &= ~(1 << nr);
5f2dc798
JD		 1224 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1225 data->fan_main_ctrl);
b99883dc
JD		 1226 } else {
1227 if (val == 1) /* Manual mode */
16b5dda2 1228 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
6229cdb2
JD		 1229 data->pwm_temp_map[nr] :
1230 data->pwm_duty[nr];
b99883dc
JD		 1231 else /* Automatic mode */
1232 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
36c4d98a 1233 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
c145d5c6
RM		 1234
1235 if (data->type != it8603) {
1236 /* set SmartGuardian mode */
1237 data->fan_main_ctrl |= (1 << nr);
1238 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1239 data->fan_main_ctrl);
1240 }
1da177e4
LT		 1241 }
1242
9a61bf63 1243 mutex_unlock(&data->update_lock);
1da177e4
LT		 1244 return count;
1245}
20ad93d4
JD		 1246static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1247 const char *buf, size_t count)
1da177e4 1248{
20ad93d4
JD		 1249 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1250 int nr = sensor_attr->index;
1251
b74f3fdd 1252 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1253 long val;
1da177e4 1254
179c4fdb 1255 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1da177e4
LT		 1256 return -EINVAL;
1257
9a61bf63 1258 mutex_lock(&data->update_lock);
16b5dda2 1259 if (has_newer_autopwm(data)) {
4a0d71cf
GR		 1260 /*
1261 * If we are in automatic mode, the PWM duty cycle register
1262 * is read-only so we can't write the value.
1263 */
6229cdb2
JD		 1264 if (data->pwm_ctrl[nr] & 0x80) {
1265 mutex_unlock(&data->update_lock);
1266 return -EBUSY;
1267 }
1268 data->pwm_duty[nr] = pwm_to_reg(data, val);
36c4d98a 1269 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
6229cdb2
JD		 1270 data->pwm_duty[nr]);
1271 } else {
1272 data->pwm_duty[nr] = pwm_to_reg(data, val);
4a0d71cf
GR		 1273 /*
1274 * If we are in manual mode, write the duty cycle immediately;
1275 * otherwise, just store it for later use.
1276 */
6229cdb2
JD		 1277 if (!(data->pwm_ctrl[nr] & 0x80)) {
1278 data->pwm_ctrl[nr] = data->pwm_duty[nr];
36c4d98a 1279 it87_write_value(data, IT87_REG_PWM[nr],
6229cdb2
JD		 1280 data->pwm_ctrl[nr]);
1281 }
b99883dc 1282 }
9a61bf63 1283 mutex_unlock(&data->update_lock);
1da177e4
LT		 1284 return count;
1285}
f8d0c19a
JD		 1286static ssize_t set_pwm_freq(struct device *dev,
1287 struct device_attribute *attr, const char *buf, size_t count)
1288{
60878bcf 1289 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
b74f3fdd 1290 struct it87_data *data = dev_get_drvdata(dev);
60878bcf 1291 int nr = sensor_attr->index;
f5f64501 1292 unsigned long val;
f8d0c19a
JD		 1293 int i;
1294
179c4fdb 1295 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1296 return -EINVAL;
f56c9c0a
GR		 1297
1298 val = clamp_val(val, 0, 1000000);
1299 val *= has_newer_autopwm(data) ? 256 : 128;
f5f64501 1300
f8d0c19a
JD		 1301 /* Search for the nearest available frequency */
1302 for (i = 0; i < 7; i++) {
1303 if (val > (pwm_freq[i] + pwm_freq[i+1]) / 2)
1304 break;
1305 }
1306
1307 mutex_lock(&data->update_lock);
60878bcf
GR		 1308 if (nr == 0) {
1309 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1310 data->fan_ctl |= i << 4;
1311 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1312 } else {
1313 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1314 data->extra |= i << 4;
1315 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1316 }
f8d0c19a
JD		 1317 mutex_unlock(&data->update_lock);
1318
1319 return count;
1320}
94ac7ee6
JD		 1321static ssize_t show_pwm_temp_map(struct device *dev,
1322 struct device_attribute *attr, char *buf)
1323{
1324 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1325 int nr = sensor_attr->index;
1326
1327 struct it87_data *data = it87_update_device(dev);
1328 int map;
1329
1330 if (data->pwm_temp_map[nr] < 3)
1331 map = 1 << data->pwm_temp_map[nr];
1332 else
1333 map = 0; /* Should never happen */
1334 return sprintf(buf, "%d\n", map);
1335}
1336static ssize_t set_pwm_temp_map(struct device *dev,
1337 struct device_attribute *attr, const char *buf, size_t count)
1338{
1339 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1340 int nr = sensor_attr->index;
1341
1342 struct it87_data *data = dev_get_drvdata(dev);
1343 long val;
1344 u8 reg;
1345
179c4fdb 1346 if (kstrtol(buf, 10, &val) < 0)
94ac7ee6
JD		 1347 return -EINVAL;
1348
1349 switch (val) {
1350 case (1 << 0):
1351 reg = 0x00;
1352 break;
1353 case (1 << 1):
1354 reg = 0x01;
1355 break;
1356 case (1 << 2):
1357 reg = 0x02;
1358 break;
1359 default:
1360 return -EINVAL;
1361 }
1362
1363 mutex_lock(&data->update_lock);
1364 data->pwm_temp_map[nr] = reg;
4a0d71cf
GR		 1365 /*
1366 * If we are in automatic mode, write the temp mapping immediately;
1367 * otherwise, just store it for later use.
1368 */
94ac7ee6
JD		 1369 if (data->pwm_ctrl[nr] & 0x80) {
1370 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
36c4d98a 1371 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
94ac7ee6
JD		 1372 }
1373 mutex_unlock(&data->update_lock);
1374 return count;
1375}
1da177e4 1376
4f3f51bc
JD		 1377static ssize_t show_auto_pwm(struct device *dev,
1378 struct device_attribute *attr, char *buf)
1379{
1380 struct it87_data *data = it87_update_device(dev);
1381 struct sensor_device_attribute_2 *sensor_attr =
1382 to_sensor_dev_attr_2(attr);
1383 int nr = sensor_attr->nr;
1384 int point = sensor_attr->index;
1385
44c1bcd4
JD		 1386 return sprintf(buf, "%d\n",
1387 pwm_from_reg(data, data->auto_pwm[nr][point]));
4f3f51bc
JD		 1388}
1389
1390static ssize_t set_auto_pwm(struct device *dev,
1391 struct device_attribute *attr, const char *buf, size_t count)
1392{
1393 struct it87_data *data = dev_get_drvdata(dev);
1394 struct sensor_device_attribute_2 *sensor_attr =
1395 to_sensor_dev_attr_2(attr);
1396 int nr = sensor_attr->nr;
1397 int point = sensor_attr->index;
1398 long val;
1399
179c4fdb 1400 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
4f3f51bc
JD		 1401 return -EINVAL;
1402
1403 mutex_lock(&data->update_lock);
44c1bcd4 1404 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
4f3f51bc
JD		 1405 it87_write_value(data, IT87_REG_AUTO_PWM(nr, point),
1406 data->auto_pwm[nr][point]);
1407 mutex_unlock(&data->update_lock);
1408 return count;
1409}
1410
1411static ssize_t show_auto_temp(struct device *dev,
1412 struct device_attribute *attr, char *buf)
1413{
1414 struct it87_data *data = it87_update_device(dev);
1415 struct sensor_device_attribute_2 *sensor_attr =
1416 to_sensor_dev_attr_2(attr);
1417 int nr = sensor_attr->nr;
1418 int point = sensor_attr->index;
1419
1420 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->auto_temp[nr][point]));
1421}
1422
1423static ssize_t set_auto_temp(struct device *dev,
1424 struct device_attribute *attr, const char *buf, size_t count)
1425{
1426 struct it87_data *data = dev_get_drvdata(dev);
1427 struct sensor_device_attribute_2 *sensor_attr =
1428 to_sensor_dev_attr_2(attr);
1429 int nr = sensor_attr->nr;
1430 int point = sensor_attr->index;
1431 long val;
1432
179c4fdb 1433 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
4f3f51bc
JD		 1434 return -EINVAL;
1435
1436 mutex_lock(&data->update_lock);
1437 data->auto_temp[nr][point] = TEMP_TO_REG(val);
1438 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point),
1439 data->auto_temp[nr][point]);
1440 mutex_unlock(&data->update_lock);
1441 return count;
1442}
1443
e1169ba0
GR		 1444static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1445static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1446 0, 1);
1447static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1448 set_fan_div, 0);
1449
1450static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1451static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1452 1, 1);
1453static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1454 set_fan_div, 1);
1455
1456static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1457static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1458 2, 1);
1459static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1460 set_fan_div, 2);
1461
1462static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1463static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1464 3, 1);
1da177e4 1465
e1169ba0
GR		 1466static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1467static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1468 4, 1);
1da177e4 1469
fa3f70d6
GR		 1470static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1471static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1472 5, 1);
1473
c4458db3
GR		 1474static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1475 show_pwm_enable, set_pwm_enable, 0);
1476static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
60878bcf
GR		 1477static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1478 set_pwm_freq, 0);
5c391261 1479static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1480 show_pwm_temp_map, set_pwm_temp_map, 0);
1481static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1482 show_auto_pwm, set_auto_pwm, 0, 0);
1483static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1484 show_auto_pwm, set_auto_pwm, 0, 1);
1485static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1486 show_auto_pwm, set_auto_pwm, 0, 2);
1487static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1488 show_auto_pwm, NULL, 0, 3);
1489static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1490 show_auto_temp, set_auto_temp, 0, 1);
1491static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1492 show_auto_temp, set_auto_temp, 0, 0);
1493static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1494 show_auto_temp, set_auto_temp, 0, 2);
1495static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1496 show_auto_temp, set_auto_temp, 0, 3);
1497static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1498 show_auto_temp, set_auto_temp, 0, 4);
1499
1500static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1501 show_pwm_enable, set_pwm_enable, 1);
1502static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
60878bcf 1503static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
5c391261 1504static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1505 show_pwm_temp_map, set_pwm_temp_map, 1);
1506static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1507 show_auto_pwm, set_auto_pwm, 1, 0);
1508static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1509 show_auto_pwm, set_auto_pwm, 1, 1);
1510static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1511 show_auto_pwm, set_auto_pwm, 1, 2);
1512static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1513 show_auto_pwm, NULL, 1, 3);
1514static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1515 show_auto_temp, set_auto_temp, 1, 1);
1516static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1517 show_auto_temp, set_auto_temp, 1, 0);
1518static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1519 show_auto_temp, set_auto_temp, 1, 2);
1520static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1521 show_auto_temp, set_auto_temp, 1, 3);
1522static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1523 show_auto_temp, set_auto_temp, 1, 4);
1524
1525static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1526 show_pwm_enable, set_pwm_enable, 2);
1527static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
60878bcf 1528static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
5c391261 1529static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1530 show_pwm_temp_map, set_pwm_temp_map, 2);
1531static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1532 show_auto_pwm, set_auto_pwm, 2, 0);
1533static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1534 show_auto_pwm, set_auto_pwm, 2, 1);
1535static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1536 show_auto_pwm, set_auto_pwm, 2, 2);
1537static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1538 show_auto_pwm, NULL, 2, 3);
1539static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1540 show_auto_temp, set_auto_temp, 2, 1);
1541static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1542 show_auto_temp, set_auto_temp, 2, 0);
1543static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1544 show_auto_temp, set_auto_temp, 2, 2);
1545static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1546 show_auto_temp, set_auto_temp, 2, 3);
1547static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1548 show_auto_temp, set_auto_temp, 2, 4);
1da177e4 1549
36c4d98a
GR		 1550static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
1551 show_pwm_enable, set_pwm_enable, 3);
1552static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
60878bcf 1553static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
5c391261 1554static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
36c4d98a
GR		 1555 show_pwm_temp_map, set_pwm_temp_map, 3);
1556
1557static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
1558 show_pwm_enable, set_pwm_enable, 4);
1559static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
60878bcf 1560static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
5c391261 1561static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
36c4d98a
GR		 1562 show_pwm_temp_map, set_pwm_temp_map, 4);
1563
1564static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
1565 show_pwm_enable, set_pwm_enable, 5);
1566static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
60878bcf 1567static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
5c391261 1568static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
36c4d98a
GR		 1569 show_pwm_temp_map, set_pwm_temp_map, 5);
1570
1da177e4 1571/* Alarms */
5f2dc798
JD		 1572static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
1573 char *buf)
1da177e4
LT		 1574{
1575 struct it87_data *data = it87_update_device(dev);
68188ba7 1576 return sprintf(buf, "%u\n", data->alarms);
1da177e4 1577}
1d66c64c 1578static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1da177e4 1579
0124dd78
JD		 1580static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1581 char *buf)
1582{
1583 int bitnr = to_sensor_dev_attr(attr)->index;
1584 struct it87_data *data = it87_update_device(dev);
1585 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1586}
3d30f9e6
JD		 1587
1588static ssize_t clear_intrusion(struct device *dev, struct device_attribute
1589 *attr, const char *buf, size_t count)
1590{
1591 struct it87_data *data = dev_get_drvdata(dev);
1592 long val;
1593 int config;
1594
179c4fdb 1595 if (kstrtol(buf, 10, &val) < 0 || val != 0)
3d30f9e6
JD		 1596 return -EINVAL;
1597
1598 mutex_lock(&data->update_lock);
1599 config = it87_read_value(data, IT87_REG_CONFIG);
1600 if (config < 0) {
1601 count = config;
1602 } else {
1603 config |= 1 << 5;
1604 it87_write_value(data, IT87_REG_CONFIG, config);
1605 /* Invalidate cache to force re-read */
1606 data->valid = 0;
1607 }
1608 mutex_unlock(&data->update_lock);
1609
1610 return count;
1611}
1612
0124dd78
JD		 1613static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1614static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1615static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1616static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1617static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1618static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1619static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1620static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1621static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1622static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1623static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1624static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1625static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
fa3f70d6 1626static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
0124dd78
JD		 1627static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1628static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1629static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
3d30f9e6
JD		 1630static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1631 show_alarm, clear_intrusion, 4);
0124dd78 1632
d9b327c3
JD		 1633static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1634 char *buf)
1635{
1636 int bitnr = to_sensor_dev_attr(attr)->index;
1637 struct it87_data *data = it87_update_device(dev);
1638 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1639}
1640static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1641 const char *buf, size_t count)
1642{
1643 int bitnr = to_sensor_dev_attr(attr)->index;
1644 struct it87_data *data = dev_get_drvdata(dev);
1645 long val;
1646
179c4fdb 1647 if (kstrtol(buf, 10, &val) < 0
d9b327c3
JD		 1648 || (val != 0 && val != 1))
1649 return -EINVAL;
1650
1651 mutex_lock(&data->update_lock);
1652 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1653 if (val)
1654 data->beeps |= (1 << bitnr);
1655 else
1656 data->beeps &= ~(1 << bitnr);
1657 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1658 mutex_unlock(&data->update_lock);
1659 return count;
1660}
1661
1662static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1663 show_beep, set_beep, 1);
1664static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1665static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1666static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1667static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1668static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1669static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1670static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1671/* fanX_beep writability is set later */
1672static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1673static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1674static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1675static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1676static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
fa3f70d6 1677static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
d9b327c3
JD		 1678static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1679 show_beep, set_beep, 2);
1680static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1681static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1682
5f2dc798
JD		 1683static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
1684 char *buf)
1da177e4 1685{
90d6619a 1686 struct it87_data *data = dev_get_drvdata(dev);
a7be58a1 1687 return sprintf(buf, "%u\n", data->vrm);
1da177e4 1688}
5f2dc798
JD		 1689static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
1690 const char *buf, size_t count)
1da177e4 1691{
b74f3fdd 1692 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 1693 unsigned long val;
1694
179c4fdb 1695 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1696 return -EINVAL;
1da177e4 1697
1da177e4
LT		 1698 data->vrm = val;
1699
1700 return count;
1701}
1702static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4 1703
5f2dc798
JD		 1704static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
1705 char *buf)
1da177e4
LT		 1706{
1707 struct it87_data *data = it87_update_device(dev);
1708 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
1709}
1710static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
87808be4 1711
738e5e05
JD		 1712static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1713 char *buf)
1714{
3c4c4971 1715 static const char * const labels[] = {
738e5e05
JD		 1716 "+5V",
1717 "5VSB",
1718 "Vbat",
1719 };
3c4c4971 1720 static const char * const labels_it8721[] = {
44c1bcd4
JD		 1721 "+3.3V",
1722 "3VSB",
1723 "Vbat",
1724 };
1725 struct it87_data *data = dev_get_drvdata(dev);
738e5e05 1726 int nr = to_sensor_dev_attr(attr)->index;
ead80803 1727 const char *label;
738e5e05 1728
ead80803
JM		 1729 if (has_12mv_adc(data) || has_10_9mv_adc(data))
1730 label = labels_it8721[nr];
1731 else
1732 label = labels[nr];
1733
1734 return sprintf(buf, "%s\n", label);
738e5e05
JD		 1735}
1736static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1737static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1738static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
73055405 1739/* AVCC3 */
c145d5c6 1740static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0);
738e5e05 1741
52929715
GR		 1742static umode_t it87_in_is_visible(struct kobject *kobj,
1743 struct attribute *attr, int index)
9172b5d1 1744{
52929715
GR		 1745 struct device *dev = container_of(kobj, struct device, kobj);
1746 struct it87_data *data = dev_get_drvdata(dev);
1747 int i = index / 5; /* voltage index */
1748 int a = index % 5; /* attribute index */
1749
1750 if (index >= 40) { /* in8, in9 only have input attributes */
1751 i = index - 40 + 8;
1752 a = 0;
1753 }
1754
1755 if (!(data->has_in & (1 << i)))
1756 return 0;
1757
1758 if (a == 4 && !data->has_beep)
1759 return 0;
1760
1761 return attr->mode;
1762}
1763
1764static struct attribute *it87_attributes_in[] = {
87808be4 1765 &sensor_dev_attr_in0_input.dev_attr.attr,
87808be4 1766 &sensor_dev_attr_in0_min.dev_attr.attr,
87808be4 1767 &sensor_dev_attr_in0_max.dev_attr.attr,
0124dd78 1768 &sensor_dev_attr_in0_alarm.dev_attr.attr,
52929715
GR		 1769 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
1770
9172b5d1
GR		 1771 &sensor_dev_attr_in1_input.dev_attr.attr,
1772 &sensor_dev_attr_in1_min.dev_attr.attr,
1773 &sensor_dev_attr_in1_max.dev_attr.attr,
0124dd78 1774 &sensor_dev_attr_in1_alarm.dev_attr.attr,
52929715
GR		 1775 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
1776
9172b5d1
GR		 1777 &sensor_dev_attr_in2_input.dev_attr.attr,
1778 &sensor_dev_attr_in2_min.dev_attr.attr,
1779 &sensor_dev_attr_in2_max.dev_attr.attr,
0124dd78 1780 &sensor_dev_attr_in2_alarm.dev_attr.attr,
52929715
GR		 1781 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
1782
9172b5d1
GR		 1783 &sensor_dev_attr_in3_input.dev_attr.attr,
1784 &sensor_dev_attr_in3_min.dev_attr.attr,
1785 &sensor_dev_attr_in3_max.dev_attr.attr,
0124dd78 1786 &sensor_dev_attr_in3_alarm.dev_attr.attr,
52929715
GR		 1787 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
1788
9172b5d1
GR		 1789 &sensor_dev_attr_in4_input.dev_attr.attr,
1790 &sensor_dev_attr_in4_min.dev_attr.attr,
1791 &sensor_dev_attr_in4_max.dev_attr.attr,
0124dd78 1792 &sensor_dev_attr_in4_alarm.dev_attr.attr,
52929715
GR		 1793 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
1794
9172b5d1
GR		 1795 &sensor_dev_attr_in5_input.dev_attr.attr,
1796 &sensor_dev_attr_in5_min.dev_attr.attr,
1797 &sensor_dev_attr_in5_max.dev_attr.attr,
0124dd78 1798 &sensor_dev_attr_in5_alarm.dev_attr.attr,
52929715
GR		 1799 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
1800
9172b5d1
GR		 1801 &sensor_dev_attr_in6_input.dev_attr.attr,
1802 &sensor_dev_attr_in6_min.dev_attr.attr,
1803 &sensor_dev_attr_in6_max.dev_attr.attr,
0124dd78 1804 &sensor_dev_attr_in6_alarm.dev_attr.attr,
52929715
GR		 1805 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
1806
9172b5d1
GR		 1807 &sensor_dev_attr_in7_input.dev_attr.attr,
1808 &sensor_dev_attr_in7_min.dev_attr.attr,
1809 &sensor_dev_attr_in7_max.dev_attr.attr,
0124dd78 1810 &sensor_dev_attr_in7_alarm.dev_attr.attr,
52929715
GR		 1811 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
1812
1813 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
87808be4 1814
52929715
GR		 1815 &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
1816};
1817
1818static const struct attribute_group it87_group_in = {
1819 .attrs = it87_attributes_in,
1820 .is_visible = it87_in_is_visible,
9172b5d1
GR		 1821};
1822
87533770
GR		 1823static umode_t it87_temp_is_visible(struct kobject *kobj,
1824 struct attribute *attr, int index)
4573acbc 1825{
87533770
GR		 1826 struct device *dev = container_of(kobj, struct device, kobj);
1827 struct it87_data *data = dev_get_drvdata(dev);
1828 int i = index / 7; /* temperature index */
1829 int a = index % 7; /* attribute index */
1830
1831 if (!(data->has_temp & (1 << i)))
1832 return 0;
1833
1834 if (a == 5 && !has_temp_offset(data))
1835 return 0;
1836
1837 if (a == 6 && !data->has_beep)
1838 return 0;
1839
1840 return attr->mode;
1841}
1842
1843static struct attribute *it87_attributes_temp[] = {
87808be4 1844 &sensor_dev_attr_temp1_input.dev_attr.attr,
87808be4 1845 &sensor_dev_attr_temp1_max.dev_attr.attr,
87808be4 1846 &sensor_dev_attr_temp1_min.dev_attr.attr,
87808be4 1847 &sensor_dev_attr_temp1_type.dev_attr.attr,
0124dd78 1848 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
87533770
GR		 1849 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
1850 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
1851
4573acbc
GR		 1852 &sensor_dev_attr_temp2_input.dev_attr.attr,
1853 &sensor_dev_attr_temp2_max.dev_attr.attr,
1854 &sensor_dev_attr_temp2_min.dev_attr.attr,
1855 &sensor_dev_attr_temp2_type.dev_attr.attr,
0124dd78 1856 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
87533770
GR		 1857 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1858 &sensor_dev_attr_temp2_beep.dev_attr.attr,
1859
4573acbc
GR		 1860 &sensor_dev_attr_temp3_input.dev_attr.attr,
1861 &sensor_dev_attr_temp3_max.dev_attr.attr,
1862 &sensor_dev_attr_temp3_min.dev_attr.attr,
1863 &sensor_dev_attr_temp3_type.dev_attr.attr,
0124dd78 1864 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
87533770
GR		 1865 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1866 &sensor_dev_attr_temp3_beep.dev_attr.attr,
4573acbc 1867
87533770 1868 NULL
4573acbc 1869};
87808be4 1870
87533770
GR		 1871static const struct attribute_group it87_group_temp = {
1872 .attrs = it87_attributes_temp,
1873 .is_visible = it87_temp_is_visible,
161d898a
GR		 1874};
1875
d3766848
GR		 1876static umode_t it87_is_visible(struct kobject *kobj,
1877 struct attribute *attr, int index)
1878{
1879 struct device *dev = container_of(kobj, struct device, kobj);
1880 struct it87_data *data = dev_get_drvdata(dev);
1881
8638d0af 1882 if ((index == 2 || index == 3) && !data->has_vid)
d3766848
GR		 1883 return 0;
1884
8638d0af 1885 if (index > 3 && !(data->in_internal & (1 << (index - 4))))
d3766848
GR		 1886 return 0;
1887
1888 return attr->mode;
1889}
1890
4573acbc 1891static struct attribute *it87_attributes[] = {
87808be4 1892 &dev_attr_alarms.attr,
3d30f9e6 1893 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
8638d0af
GR		 1894 &dev_attr_vrm.attr, /* 2 */
1895 &dev_attr_cpu0_vid.attr, /* 3 */
1896 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
d3766848
GR		 1897 &sensor_dev_attr_in7_label.dev_attr.attr,
1898 &sensor_dev_attr_in8_label.dev_attr.attr,
1899 &sensor_dev_attr_in9_label.dev_attr.attr,
87808be4
JD		 1900 NULL
1901};
1902
1903static const struct attribute_group it87_group = {
1904 .attrs = it87_attributes,
d3766848 1905 .is_visible = it87_is_visible,
87808be4
JD		 1906};
1907
9a70ee81
GR		 1908static umode_t it87_fan_is_visible(struct kobject *kobj,
1909 struct attribute *attr, int index)
1910{
1911 struct device *dev = container_of(kobj, struct device, kobj);
1912 struct it87_data *data = dev_get_drvdata(dev);
1913 int i = index / 5; /* fan index */
1914 int a = index % 5; /* attribute index */
1915
1916 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
1917 i = (index - 15) / 4 + 3;
1918 a = (index - 15) % 4;
1919 }
1920
1921 if (!(data->has_fan & (1 << i)))
1922 return 0;
1923
1924 if (a == 3) { /* beep */
1925 if (!data->has_beep)
1926 return 0;
1927 /* first fan beep attribute is writable */
1928 if (i == __ffs(data->has_fan))
1929 return attr->mode | S_IWUSR;
1930 }
1931
1932 if (a == 4 && has_16bit_fans(data)) /* divisor */
1933 return 0;
1934
1935 return attr->mode;
1936}
1937
1938static struct attribute *it87_attributes_fan[] = {
e1169ba0
GR		 1939 &sensor_dev_attr_fan1_input.dev_attr.attr,
1940 &sensor_dev_attr_fan1_min.dev_attr.attr,
723a0aa0 1941 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
9a70ee81
GR		 1942 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
1943 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
1944
e1169ba0
GR		 1945 &sensor_dev_attr_fan2_input.dev_attr.attr,
1946 &sensor_dev_attr_fan2_min.dev_attr.attr,
723a0aa0 1947 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
9a70ee81
GR		 1948 &sensor_dev_attr_fan2_beep.dev_attr.attr,
1949 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
1950
e1169ba0
GR		 1951 &sensor_dev_attr_fan3_input.dev_attr.attr,
1952 &sensor_dev_attr_fan3_min.dev_attr.attr,
723a0aa0 1953 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
9a70ee81
GR		 1954 &sensor_dev_attr_fan3_beep.dev_attr.attr,
1955 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
1956
1957 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
e1169ba0 1958 &sensor_dev_attr_fan4_min.dev_attr.attr,
723a0aa0 1959 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
9a70ee81
GR		 1960 &sensor_dev_attr_fan4_beep.dev_attr.attr,
1961
1962 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
e1169ba0 1963 &sensor_dev_attr_fan5_min.dev_attr.attr,
723a0aa0 1964 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
9a70ee81
GR		 1965 &sensor_dev_attr_fan5_beep.dev_attr.attr,
1966
1967 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
fa3f70d6
GR		 1968 &sensor_dev_attr_fan6_min.dev_attr.attr,
1969 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
9a70ee81 1970 &sensor_dev_attr_fan6_beep.dev_attr.attr,
fa3f70d6 1971 NULL
723a0aa0 1972};
87808be4 1973
9a70ee81
GR		 1974static const struct attribute_group it87_group_fan = {
1975 .attrs = it87_attributes_fan,
1976 .is_visible = it87_fan_is_visible,
723a0aa0
JD		 1977};
1978
5c391261
GR		 1979static umode_t it87_pwm_is_visible(struct kobject *kobj,
1980 struct attribute *attr, int index)
1981{
1982 struct device *dev = container_of(kobj, struct device, kobj);
1983 struct it87_data *data = dev_get_drvdata(dev);
1984 int i = index / 4; /* pwm index */
1985 int a = index % 4; /* attribute index */
1986
1987 if (!(data->has_pwm & (1 << i)))
1988 return 0;
1989
1990 /* pwmX_auto_channels_temp is only writable for old auto pwm */
1991 if (a == 3 && has_old_autopwm(data))
1992 return attr->mode | S_IWUSR;
1993
1994 /* pwm2_freq is writable if there are two pwm frequency selects */
1995 if (has_pwm_freq2(data) && i == 1 && a == 2)
1996 return attr->mode | S_IWUSR;
1997
1998 return attr->mode;
1999}
2000
2001static struct attribute *it87_attributes_pwm[] = {
87808be4 2002 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
87808be4 2003 &sensor_dev_attr_pwm1.dev_attr.attr,
60878bcf 2004 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
94ac7ee6 2005 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
5c391261 2006
723a0aa0
JD		 2007 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2008 &sensor_dev_attr_pwm2.dev_attr.attr,
60878bcf 2009 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
94ac7ee6 2010 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
5c391261 2011
723a0aa0
JD		 2012 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2013 &sensor_dev_attr_pwm3.dev_attr.attr,
60878bcf 2014 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
94ac7ee6 2015 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
5c391261 2016
36c4d98a
GR		 2017 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2018 &sensor_dev_attr_pwm4.dev_attr.attr,
60878bcf 2019 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
36c4d98a 2020 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
5c391261 2021
36c4d98a
GR		 2022 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2023 &sensor_dev_attr_pwm5.dev_attr.attr,
60878bcf 2024 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
36c4d98a 2025 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
5c391261 2026
36c4d98a
GR		 2027 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2028 &sensor_dev_attr_pwm6.dev_attr.attr,
60878bcf 2029 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
36c4d98a 2030 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
5c391261 2031
36c4d98a 2032 NULL
5c391261 2033};
87808be4 2034
5c391261
GR		 2035static const struct attribute_group it87_group_pwm = {
2036 .attrs = it87_attributes_pwm,
2037 .is_visible = it87_pwm_is_visible,
2038};
2039
2040static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2041 struct attribute *attr, int index)
60878bcf
GR		 2042{
2043 struct device *dev = container_of(kobj, struct device, kobj);
2044 struct it87_data *data = dev_get_drvdata(dev);
5c391261 2045 int i = index / 9; /* pwm index */
60878bcf 2046
5c391261
GR		 2047 if (!(data->has_pwm & (1 << i)))
2048 return 0;
60878bcf
GR		 2049
2050 return attr->mode;
2051}
2052
5c391261 2053static struct attribute *it87_attributes_auto_pwm[] = {
4f3f51bc
JD		 2054 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2055 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2056 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2057 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2058 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2059 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2060 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2061 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2062 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
5c391261 2063
4f3f51bc
JD		 2064 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
2065 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2066 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2067 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2068 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2069 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2070 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2071 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2072 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
5c391261 2073
4f3f51bc
JD		 2074 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
2075 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2076 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2077 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2078 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2079 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2080 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2081 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2082 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
4f3f51bc 2083
5c391261
GR		 2084 NULL,
2085};
2086
2087static const struct attribute_group it87_group_auto_pwm = {
2088 .attrs = it87_attributes_auto_pwm,
2089 .is_visible = it87_auto_pwm_is_visible,
4f3f51bc
JD		 2090};
2091
2d8672c5 2092/* SuperIO detection - will change isa_address if a chip is found */
3c2e3512
GR		 2093static int __init it87_find(int sioaddr, unsigned short *address,
2094 struct it87_sio_data *sio_data)
1da177e4 2095{
5b0380c9 2096 int err;
b74f3fdd 2097 u16 chip_type;
98dd22c3 2098 const char *board_vendor, *board_name;
f83a9cb6 2099 const struct it87_devices *config;
1da177e4 2100
3c2e3512 2101 err = superio_enter(sioaddr);
5b0380c9
NG		 2102 if (err)
2103 return err;
2104
2105 err = -ENODEV;
3c2e3512 2106 chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID);
b74f3fdd 2107
2108 switch (chip_type) {
2109 case IT8705F_DEVID:
2110 sio_data->type = it87;
2111 break;
2112 case IT8712F_DEVID:
2113 sio_data->type = it8712;
2114 break;
2115 case IT8716F_DEVID:
2116 case IT8726F_DEVID:
2117 sio_data->type = it8716;
2118 break;
2119 case IT8718F_DEVID:
2120 sio_data->type = it8718;
2121 break;
b4da93e4
JMS		 2122 case IT8720F_DEVID:
2123 sio_data->type = it8720;
2124 break;
44c1bcd4
JD		 2125 case IT8721F_DEVID:
2126 sio_data->type = it8721;
2127 break;
16b5dda2
JD		 2128 case IT8728F_DEVID:
2129 sio_data->type = it8728;
2130 break;
ead80803
JM		 2131 case IT8732F_DEVID:
2132 sio_data->type = it8732;
2133 break;
b0636707
GR		 2134 case IT8771E_DEVID:
2135 sio_data->type = it8771;
2136 break;
2137 case IT8772E_DEVID:
2138 sio_data->type = it8772;
2139 break;
7bc32d29
GR		 2140 case IT8781F_DEVID:
2141 sio_data->type = it8781;
2142 break;
0531d98b
GR		 2143 case IT8782F_DEVID:
2144 sio_data->type = it8782;
2145 break;
2146 case IT8783E_DEVID:
2147 sio_data->type = it8783;
2148 break;
a0c1424a
TL		 2149 case IT8786E_DEVID:
2150 sio_data->type = it8786;
2151 break;
4ee07157
GR		 2152 case IT8790E_DEVID:
2153 sio_data->type = it8790;
2154 break;
7183ae8c 2155 case IT8603E_DEVID:
574e9bd8 2156 case IT8623E_DEVID:
c145d5c6
RM		 2157 sio_data->type = it8603;
2158 break;
3ba9d977
GR		 2159 case IT8620E_DEVID:
2160 sio_data->type = it8620;
2161 break;
b74f3fdd 2162 case 0xffff: /* No device at all */
2163 goto exit;
2164 default:
a8ca1037 2165 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
b74f3fdd 2166 goto exit;
2167 }
1da177e4 2168
3c2e3512
GR		 2169 superio_select(sioaddr, PME);
2170 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
a8ca1037 2171 pr_info("Device not activated, skipping\n");
1da177e4
LT		 2172 goto exit;
2173 }
2174
3c2e3512 2175 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
1da177e4 2176 if (*address == 0) {
a8ca1037 2177 pr_info("Base address not set, skipping\n");
1da177e4
LT		 2178 goto exit;
2179 }
2180
2181 err = 0;
3c2e3512 2182 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
faf392fb
GR		 2183 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2184 it87_devices[sio_data->type].suffix,
a0c1424a 2185 *address, sio_data->revision);
1da177e4 2186
f83a9cb6
GR		 2187 config = &it87_devices[sio_data->type];
2188
7f5726c3 2189 /* in7 (VSB or VCCH5V) is always internal on some chips */
f83a9cb6 2190 if (has_in7_internal(config))
7f5726c3
GR		 2191 sio_data->internal |= (1 << 1);
2192
738e5e05 2193 /* in8 (Vbat) is always internal */
7f5726c3
GR		 2194 sio_data->internal |= (1 << 2);
2195
73055405
GR		 2196 /* in9 (AVCC3), always internal if supported */
2197 if (has_avcc3(config))
2198 sio_data->internal |= (1 << 3); /* in9 is AVCC */
2199 else
c145d5c6 2200 sio_data->skip_in |= (1 << 9);
738e5e05 2201
36c4d98a
GR		 2202 if (!has_six_pwm(config))
2203 sio_data->skip_pwm |= (1 << 3) | (1 << 4) | (1 << 5);
2204
f83a9cb6 2205 if (!has_vid(config))
895ff267 2206 sio_data->skip_vid = 1;
d9b327c3 2207
32dd7c40
GR		 2208 /* Read GPIO config and VID value from LDN 7 (GPIO) */
2209 if (sio_data->type == it87) {
d9b327c3 2210 /* The IT8705F has a different LD number for GPIO */
3c2e3512
GR		 2211 superio_select(sioaddr, 5);
2212 sio_data->beep_pin = superio_inb(sioaddr,
2213 IT87_SIO_BEEP_PIN_REG) & 0x3f;
0531d98b 2214 } else if (sio_data->type == it8783) {
088ce2ac 2215 int reg25, reg27, reg2a, reg2c, regef;
0531d98b 2216
3c2e3512 2217 superio_select(sioaddr, GPIO);
0531d98b 2218
3c2e3512
GR		 2219 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2220 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2221 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2222 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2223 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
0531d98b 2224
0531d98b 2225 /* Check if fan3 is there or not */
088ce2ac 2226 if ((reg27 & (1 << 0)) || !(reg2c & (1 << 2)))
0531d98b
GR		 2227 sio_data->skip_fan |= (1 << 2);
2228 if ((reg25 & (1 << 4))
088ce2ac 2229 || (!(reg2a & (1 << 1)) && (regef & (1 << 0))))
0531d98b
GR		 2230 sio_data->skip_pwm |= (1 << 2);
2231
2232 /* Check if fan2 is there or not */
2233 if (reg27 & (1 << 7))
2234 sio_data->skip_fan |= (1 << 1);
2235 if (reg27 & (1 << 3))
2236 sio_data->skip_pwm |= (1 << 1);
2237
2238 /* VIN5 */
088ce2ac 2239 if ((reg27 & (1 << 0)) || (reg2c & (1 << 2)))
9172b5d1 2240 sio_data->skip_in |= (1 << 5); /* No VIN5 */
0531d98b
GR		 2241
2242 /* VIN6 */
9172b5d1
GR		 2243 if (reg27 & (1 << 1))
2244 sio_data->skip_in |= (1 << 6); /* No VIN6 */
0531d98b
GR		 2245
2246 /*
2247 * VIN7
2248 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2249 */
9172b5d1
GR		 2250 if (reg27 & (1 << 2)) {
2251 /*
2252 * The data sheet is a bit unclear regarding the
2253 * internal voltage divider for VCCH5V. It says
2254 * "This bit enables and switches VIN7 (pin 91) to the
2255 * internal voltage divider for VCCH5V".
2256 * This is different to other chips, where the internal
2257 * voltage divider would connect VIN7 to an internal
2258 * voltage source. Maybe that is the case here as well.
2259 *
2260 * Since we don't know for sure, re-route it if that is
2261 * not the case, and ask the user to report if the
2262 * resulting voltage is sane.
2263 */
088ce2ac
GR		 2264 if (!(reg2c & (1 << 1))) {
2265 reg2c |= (1 << 1);
3c2e3512
GR		 2266 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2267 reg2c);
9172b5d1
GR		 2268 pr_notice("Routing internal VCCH5V to in7.\n");
2269 }
2270 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2271 pr_notice("Please report if it displays a reasonable voltage.\n");
2272 }
0531d98b 2273
088ce2ac 2274 if (reg2c & (1 << 0))
0531d98b 2275 sio_data->internal |= (1 << 0);
088ce2ac 2276 if (reg2c & (1 << 1))
0531d98b
GR		 2277 sio_data->internal |= (1 << 1);
2278
3c2e3512
GR		 2279 sio_data->beep_pin = superio_inb(sioaddr,
2280 IT87_SIO_BEEP_PIN_REG) & 0x3f;
c145d5c6
RM		 2281 } else if (sio_data->type == it8603) {
2282 int reg27, reg29;
2283
3c2e3512 2284 superio_select(sioaddr, GPIO);
0531d98b 2285
3c2e3512 2286 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
c145d5c6
RM		 2287
2288 /* Check if fan3 is there or not */
2289 if (reg27 & (1 << 6))
2290 sio_data->skip_pwm |= (1 << 2);
2291 if (reg27 & (1 << 7))
2292 sio_data->skip_fan |= (1 << 2);
2293
2294 /* Check if fan2 is there or not */
3c2e3512 2295 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
c145d5c6
RM		 2296 if (reg29 & (1 << 1))
2297 sio_data->skip_pwm |= (1 << 1);
2298 if (reg29 & (1 << 2))
2299 sio_data->skip_fan |= (1 << 1);
2300
2301 sio_data->skip_in |= (1 << 5); /* No VIN5 */
2302 sio_data->skip_in |= (1 << 6); /* No VIN6 */
2303
3c2e3512
GR		 2304 sio_data->beep_pin = superio_inb(sioaddr,
2305 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3ba9d977
GR		 2306 } else if (sio_data->type == it8620) {
2307 int reg;
2308
3c2e3512 2309 superio_select(sioaddr, GPIO);
3ba9d977 2310
36c4d98a 2311 /* Check for pwm5 */
3c2e3512 2312 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
36c4d98a
GR		 2313 if (reg & (1 << 6))
2314 sio_data->skip_pwm |= (1 << 4);
2315
3ba9d977 2316 /* Check for fan4, fan5 */
3c2e3512 2317 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3ba9d977
GR		 2318 if (!(reg & (1 << 5)))
2319 sio_data->skip_fan |= (1 << 3);
2320 if (!(reg & (1 << 4)))
2321 sio_data->skip_fan |= (1 << 4);
2322
2323 /* Check for pwm3, fan3 */
3c2e3512 2324 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3ba9d977
GR		 2325 if (reg & (1 << 6))
2326 sio_data->skip_pwm |= (1 << 2);
2327 if (reg & (1 << 7))
2328 sio_data->skip_fan |= (1 << 2);
2329
36c4d98a 2330 /* Check for pwm4 */
3c2e3512 2331 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
36c4d98a
GR		 2332 if (!(reg & (1 << 2)))
2333 sio_data->skip_pwm |= (1 << 3);
2334
3ba9d977 2335 /* Check for pwm2, fan2 */
3c2e3512 2336 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3ba9d977
GR		 2337 if (reg & (1 << 1))
2338 sio_data->skip_pwm |= (1 << 1);
2339 if (reg & (1 << 2))
2340 sio_data->skip_fan |= (1 << 1);
36c4d98a
GR		 2341 /* Check for pwm6, fan6 */
2342 if (!(reg & (1 << 7))) {
2343 sio_data->skip_pwm |= (1 << 5);
2344 sio_data->skip_fan |= (1 << 5);
2345 }
3ba9d977 2346
3c2e3512
GR		 2347 sio_data->beep_pin = superio_inb(sioaddr,
2348 IT87_SIO_BEEP_PIN_REG) & 0x3f;
895ff267 2349 } else {
87673dd7 2350 int reg;
9172b5d1 2351 bool uart6;
87673dd7 2352
3c2e3512 2353 superio_select(sioaddr, GPIO);
44c1bcd4 2354
3c2e3512 2355 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
32dd7c40 2356 if (!sio_data->skip_vid) {
44c1bcd4
JD		 2357 /* We need at least 4 VID pins */
2358 if (reg & 0x0f) {
a8ca1037 2359 pr_info("VID is disabled (pins used for GPIO)\n");
44c1bcd4
JD		 2360 sio_data->skip_vid = 1;
2361 }
895ff267
JD		 2362 }
2363
591ec650
JD		 2364 /* Check if fan3 is there or not */
2365 if (reg & (1 << 6))
2366 sio_data->skip_pwm |= (1 << 2);
2367 if (reg & (1 << 7))
2368 sio_data->skip_fan |= (1 << 2);
2369
2370 /* Check if fan2 is there or not */
3c2e3512 2371 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
591ec650
JD		 2372 if (reg & (1 << 1))
2373 sio_data->skip_pwm |= (1 << 1);
2374 if (reg & (1 << 2))
2375 sio_data->skip_fan |= (1 << 1);
2376
895ff267
JD		 2377 if ((sio_data->type == it8718 || sio_data->type == it8720)
2378 && !(sio_data->skip_vid))
3c2e3512
GR		 2379 sio_data->vid_value = superio_inb(sioaddr,
2380 IT87_SIO_VID_REG);
87673dd7 2381
3c2e3512 2382 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
9172b5d1
GR		 2383
2384 uart6 = sio_data->type == it8782 && (reg & (1 << 2));
2385
436cad2a
JD		 2386 /*
2387 * The IT8720F has no VIN7 pin, so VCCH should always be
2388 * routed internally to VIN7 with an internal divider.
2389 * Curiously, there still is a configuration bit to control
2390 * this, which means it can be set incorrectly. And even
2391 * more curiously, many boards out there are improperly
2392 * configured, even though the IT8720F datasheet claims
2393 * that the internal routing of VCCH to VIN7 is the default
2394 * setting. So we force the internal routing in this case.
0531d98b
GR		 2395 *
2396 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
9172b5d1
GR		 2397 * If UART6 is enabled, re-route VIN7 to the internal divider
2398 * if that is not already the case.
436cad2a 2399 */
9172b5d1 2400 if ((sio_data->type == it8720 || uart6) && !(reg & (1 << 1))) {
436cad2a 2401 reg |= (1 << 1);
3c2e3512 2402 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
a8ca1037 2403 pr_notice("Routing internal VCCH to in7\n");
436cad2a 2404 }
87673dd7 2405 if (reg & (1 << 0))
738e5e05 2406 sio_data->internal |= (1 << 0);
7f5726c3 2407 if (reg & (1 << 1))
738e5e05 2408 sio_data->internal |= (1 << 1);
d9b327c3 2409
9172b5d1
GR		 2410 /*
2411 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2412 * While VIN7 can be routed to the internal voltage divider,
2413 * VIN5 and VIN6 are not available if UART6 is enabled.
4573acbc
GR		 2414 *
2415 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2416 * is the temperature source. Since we can not read the
2417 * temperature source here, skip_temp is preliminary.
9172b5d1 2418 */
4573acbc 2419 if (uart6) {
9172b5d1 2420 sio_data->skip_in |= (1 << 5) | (1 << 6);
4573acbc
GR		 2421 sio_data->skip_temp |= (1 << 2);
2422 }
9172b5d1 2423
3c2e3512
GR		 2424 sio_data->beep_pin = superio_inb(sioaddr,
2425 IT87_SIO_BEEP_PIN_REG) & 0x3f;
87673dd7 2426 }
d9b327c3 2427 if (sio_data->beep_pin)
a8ca1037 2428 pr_info("Beeping is supported\n");
87673dd7 2429
98dd22c3
JD		 2430 /* Disable specific features based on DMI strings */
2431 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
2432 board_name = dmi_get_system_info(DMI_BOARD_NAME);
2433 if (board_vendor && board_name) {
2434 if (strcmp(board_vendor, "nVIDIA") == 0
2435 && strcmp(board_name, "FN68PT") == 0) {
4a0d71cf
GR		 2436 /*
2437 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
2438 * connected to a fan, but to something else. One user
2439 * has reported instant system power-off when changing
2440 * the PWM2 duty cycle, so we disable it.
2441 * I use the board name string as the trigger in case
2442 * the same board is ever used in other systems.
2443 */
a8ca1037 2444 pr_info("Disabling pwm2 due to hardware constraints\n");
98dd22c3
JD		 2445 sio_data->skip_pwm = (1 << 1);
2446 }
2447 }
2448
1da177e4 2449exit:
3c2e3512 2450 superio_exit(sioaddr);
1da177e4
LT		 2451 return err;
2452}
2453
c1e7a4ca
GR		 2454/* Called when we have found a new IT87. */
2455static void it87_init_device(struct platform_device *pdev)
1da177e4 2456{
c1e7a4ca
GR		 2457 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
2458 struct it87_data *data = platform_get_drvdata(pdev);
2459 int tmp, i;
2460 u8 mask;
b74f3fdd 2461
c1e7a4ca
GR		 2462 /*
2463 * For each PWM channel:
2464 * - If it is in automatic mode, setting to manual mode should set
2465 * the fan to full speed by default.
2466 * - If it is in manual mode, we need a mapping to temperature
2467 * channels to use when later setting to automatic mode later.
2468 * Use a 1:1 mapping by default (we are clueless.)
2469 * In both cases, the value can (and should) be changed by the user
2470 * prior to switching to a different mode.
2471 * Note that this is no longer needed for the IT8721F and later, as
2472 * these have separate registers for the temperature mapping and the
2473 * manual duty cycle.
2474 */
2475 for (i = 0; i < 3; i++) {
2476 data->pwm_temp_map[i] = i;
2477 data->pwm_duty[i] = 0x7f; /* Full speed */
2478 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
8e9afcbb 2479 }
1da177e4 2480
483db43e 2481 /*
c1e7a4ca
GR		 2482 * Some chips seem to have default value 0xff for all limit
2483 * registers. For low voltage limits it makes no sense and triggers
2484 * alarms, so change to 0 instead. For high temperature limits, it
2485 * means -1 degree C, which surprisingly doesn't trigger an alarm,
2486 * but is still confusing, so change to 127 degrees C.
483db43e 2487 */
c1e7a4ca
GR		 2488 for (i = 0; i < 8; i++) {
2489 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
2490 if (tmp == 0xff)
2491 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
2492 }
2493 for (i = 0; i < 3; i++) {
2494 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
2495 if (tmp == 0xff)
2496 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
483db43e 2497 }
1da177e4 2498
c1e7a4ca
GR		 2499 /*
2500 * Temperature channels are not forcibly enabled, as they can be
2501 * set to two different sensor types and we can't guess which one
2502 * is correct for a given system. These channels can be enabled at
2503 * run-time through the temp{1-3}_type sysfs accessors if needed.
2504 */
1da177e4 2505
c1e7a4ca
GR		 2506 /* Check if voltage monitors are reset manually or by some reason */
2507 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
2508 if ((tmp & 0xff) == 0) {
2509 /* Enable all voltage monitors */
2510 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
2511 }
2512
2513 /* Check if tachometers are reset manually or by some reason */
2514 mask = 0x70 & ~(sio_data->skip_fan << 4);
2515 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
2516 if ((data->fan_main_ctrl & mask) == 0) {
2517 /* Enable all fan tachometers */
2518 data->fan_main_ctrl |= mask;
2519 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2520 data->fan_main_ctrl);
2521 }
2522 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
2523
2524 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2525
2526 /* Set tachometers to 16-bit mode if needed */
2527 if (has_fan16_config(data)) {
2528 if (~tmp & 0x07 & data->has_fan) {
2529 dev_dbg(&pdev->dev,
2530 "Setting fan1-3 to 16-bit mode\n");
2531 it87_write_value(data, IT87_REG_FAN_16BIT,
2532 tmp | 0x07);
2533 }
2534 }
2535
2536 /* Check for additional fans */
2537 if (has_five_fans(data)) {
2538 if (tmp & (1 << 4))
2539 data->has_fan |= (1 << 3); /* fan4 enabled */
2540 if (tmp & (1 << 5))
2541 data->has_fan |= (1 << 4); /* fan5 enabled */
2542 if (has_six_fans(data) && (tmp & (1 << 2)))
2543 data->has_fan |= (1 << 5); /* fan6 enabled */
2544 }
2545
2546 /* Fan input pins may be used for alternative functions */
2547 data->has_fan &= ~sio_data->skip_fan;
2548
2549 /* Check if pwm5, pwm6 are enabled */
2550 if (has_six_pwm(data)) {
2551 /* The following code may be IT8620E specific */
2552 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
2553 if ((tmp & 0xc0) == 0xc0)
2554 sio_data->skip_pwm |= (1 << 4);
2555 if (!(tmp & (1 << 3)))
2556 sio_data->skip_pwm |= (1 << 5);
2557 }
2558
2559 /* Start monitoring */
2560 it87_write_value(data, IT87_REG_CONFIG,
2561 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
2562 | (update_vbat ? 0x41 : 0x01));
2563}
2564
2565/* Return 1 if and only if the PWM interface is safe to use */
2566static int it87_check_pwm(struct device *dev)
2567{
2568 struct it87_data *data = dev_get_drvdata(dev);
2569 /*
2570 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
2571 * and polarity set to active low is sign that this is the case so we
2572 * disable pwm control to protect the user.
2573 */
2574 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
2575
2576 if ((tmp & 0x87) == 0) {
2577 if (fix_pwm_polarity) {
2578 /*
2579 * The user asks us to attempt a chip reconfiguration.
2580 * This means switching to active high polarity and
2581 * inverting all fan speed values.
2582 */
2583 int i;
2584 u8 pwm[3];
2585
2586 for (i = 0; i < 3; i++)
2587 pwm[i] = it87_read_value(data,
2588 IT87_REG_PWM[i]);
2589
2590 /*
2591 * If any fan is in automatic pwm mode, the polarity
2592 * might be correct, as suspicious as it seems, so we
2593 * better don't change anything (but still disable the
2594 * PWM interface).
2595 */
2596 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
2597 dev_info(dev,
2598 "Reconfiguring PWM to active high polarity\n");
2599 it87_write_value(data, IT87_REG_FAN_CTL,
2600 tmp | 0x87);
2601 for (i = 0; i < 3; i++)
2602 it87_write_value(data,
2603 IT87_REG_PWM[i],
2604 0x7f & ~pwm[i]);
2605 return 1;
2606 }
2607
2608 dev_info(dev,
2609 "PWM configuration is too broken to be fixed\n");
2610 }
2611
2612 dev_info(dev,
2613 "Detected broken BIOS defaults, disabling PWM interface\n");
2614 return 0;
2615 } else if (fix_pwm_polarity) {
2616 dev_info(dev,
2617 "PWM configuration looks sane, won't touch\n");
2618 }
2619
2620 return 1;
2621}
2622
2623static int it87_probe(struct platform_device *pdev)
2624{
2625 struct it87_data *data;
2626 struct resource *res;
2627 struct device *dev = &pdev->dev;
2628 struct it87_sio_data *sio_data = dev_get_platdata(dev);
c1e7a4ca 2629 int enable_pwm_interface;
8638d0af 2630 struct device *hwmon_dev;
c1e7a4ca
GR		 2631
2632 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2633 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
2634 DRVNAME)) {
2635 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2636 (unsigned long)res->start,
2637 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
2638 return -EBUSY;
2639 }
2640
2641 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
2642 if (!data)
2643 return -ENOMEM;
2644
2645 data->addr = res->start;
2646 data->type = sio_data->type;
2647 data->features = it87_devices[sio_data->type].features;
2648 data->peci_mask = it87_devices[sio_data->type].peci_mask;
2649 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
c1e7a4ca
GR		 2650 /*
2651 * IT8705F Datasheet 0.4.1, 3h == Version G.
2652 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2653 * These are the first revisions with 16-bit tachometer support.
2654 */
2655 switch (data->type) {
2656 case it87:
2657 if (sio_data->revision >= 0x03) {
2658 data->features &= ~FEAT_OLD_AUTOPWM;
2659 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
2660 }
2661 break;
2662 case it8712:
2663 if (sio_data->revision >= 0x08) {
2664 data->features &= ~FEAT_OLD_AUTOPWM;
2665 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
2666 FEAT_FIVE_FANS;
2667 }
2668 break;
2669 default:
2670 break;
2671 }
2672
2673 /* Now, we do the remaining detection. */
2674 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80)
2675 || it87_read_value(data, IT87_REG_CHIPID) != 0x90)
2676 return -ENODEV;
2677
2678 platform_set_drvdata(pdev, data);
1da177e4 2679
9a61bf63 2680 mutex_init(&data->update_lock);
1da177e4 2681
1da177e4 2682 /* Check PWM configuration */
b74f3fdd 2683 enable_pwm_interface = it87_check_pwm(dev);
1da177e4 2684
44c1bcd4 2685 /* Starting with IT8721F, we handle scaling of internal voltages */
16b5dda2 2686 if (has_12mv_adc(data)) {
44c1bcd4
JD		 2687 if (sio_data->internal & (1 << 0))
2688 data->in_scaled |= (1 << 3); /* in3 is AVCC */
2689 if (sio_data->internal & (1 << 1))
2690 data->in_scaled |= (1 << 7); /* in7 is VSB */
2691 if (sio_data->internal & (1 << 2))
2692 data->in_scaled |= (1 << 8); /* in8 is Vbat */
c145d5c6
RM		 2693 if (sio_data->internal & (1 << 3))
2694 data->in_scaled |= (1 << 9); /* in9 is AVCC */
7bc32d29
GR		 2695 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
2696 sio_data->type == it8783) {
0531d98b
GR		 2697 if (sio_data->internal & (1 << 0))
2698 data->in_scaled |= (1 << 3); /* in3 is VCC5V */
2699 if (sio_data->internal & (1 << 1))
2700 data->in_scaled |= (1 << 7); /* in7 is VCCH5V */
44c1bcd4
JD		 2701 }
2702
4573acbc
GR		 2703 data->has_temp = 0x07;
2704 if (sio_data->skip_temp & (1 << 2)) {
2705 if (sio_data->type == it8782
2706 && !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
2707 data->has_temp &= ~(1 << 2);
2708 }
2709
d3766848 2710 data->in_internal = sio_data->internal;
52929715
GR		 2711 data->has_in = 0x3ff & ~sio_data->skip_in;
2712
2713 data->has_beep = !!sio_data->beep_pin;
2714
1da177e4 2715 /* Initialize the IT87 chip */
b74f3fdd 2716 it87_init_device(pdev);
1da177e4 2717
d3766848
GR		 2718 if (!sio_data->skip_vid) {
2719 data->has_vid = true;
2720 data->vrm = vid_which_vrm();
2721 /* VID reading from Super-I/O config space if available */
2722 data->vid = sio_data->vid_value;
2723 }
2724
8638d0af
GR		 2725 /* Prepare for sysfs hooks */
2726 data->groups[0] = &it87_group;
2727 data->groups[1] = &it87_group_in;
2728 data->groups[2] = &it87_group_temp;
2729 data->groups[3] = &it87_group_fan;
17d648bf 2730
1da177e4 2731 if (enable_pwm_interface) {
5c391261
GR		 2732 data->has_pwm = (1 << ARRAY_SIZE(IT87_REG_PWM)) - 1;
2733 data->has_pwm &= ~sio_data->skip_pwm;
4f3f51bc 2734
8638d0af
GR		 2735 data->groups[4] = &it87_group_pwm;
2736 if (has_old_autopwm(data))
2737 data->groups[5] = &it87_group_auto_pwm;
1da177e4
LT		 2738 }
2739
8638d0af
GR		 2740 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
2741 it87_devices[sio_data->type].name,
2742 data, data->groups);
2743 return PTR_ERR_OR_ZERO(hwmon_dev);
1da177e4
LT		 2744}
2745
c1e7a4ca
GR		 2746static struct platform_driver it87_driver = {
2747 .driver = {
2748 .name = DRVNAME,
2749 },
2750 .probe = it87_probe,
c1e7a4ca 2751};
1da177e4 2752
e84bd953 2753static int __init it87_device_add(int index, unsigned short address,
b74f3fdd 2754 const struct it87_sio_data *sio_data)
2755{
8e50e3c3 2756 struct platform_device *pdev;
b74f3fdd 2757 struct resource res = {
87b4b663
BH		 2758 .start = address + IT87_EC_OFFSET,
2759 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
b74f3fdd 2760 .name = DRVNAME,
2761 .flags = IORESOURCE_IO,
2762 };
2763 int err;
2764
b9acb64a
JD		 2765 err = acpi_check_resource_conflict(&res);
2766 if (err)
5cae84a5 2767 return err;
b9acb64a 2768
b74f3fdd 2769 pdev = platform_device_alloc(DRVNAME, address);
5cae84a5
GR		 2770 if (!pdev)
2771 return -ENOMEM;
b74f3fdd 2772
2773 err = platform_device_add_resources(pdev, &res, 1);
2774 if (err) {
a8ca1037 2775 pr_err("Device resource addition failed (%d)\n", err);
b74f3fdd 2776 goto exit_device_put;
2777 }
2778
2779 err = platform_device_add_data(pdev, sio_data,
2780 sizeof(struct it87_sio_data));
2781 if (err) {
a8ca1037 2782 pr_err("Platform data allocation failed\n");
b74f3fdd 2783 goto exit_device_put;
2784 }
2785
2786 err = platform_device_add(pdev);
2787 if (err) {
a8ca1037 2788 pr_err("Device addition failed (%d)\n", err);
b74f3fdd 2789 goto exit_device_put;
2790 }
2791
e84bd953 2792 it87_pdev[index] = pdev;
b74f3fdd 2793 return 0;
2794
2795exit_device_put:
2796 platform_device_put(pdev);
b74f3fdd 2797 return err;
2798}
2799
1da177e4
LT		 2800static int __init sm_it87_init(void)
2801{
e84bd953 2802 int sioaddr[2] = { REG_2E, REG_4E };
b74f3fdd 2803 struct it87_sio_data sio_data;
e84bd953
GR		 2804 unsigned short isa_address;
2805 bool found = false;
2806 int i, err;
b74f3fdd 2807
b74f3fdd 2808 err = platform_driver_register(&it87_driver);
2809 if (err)
2810 return err;
fde09509 2811
e84bd953
GR		 2812 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
2813 memset(&sio_data, 0, sizeof(struct it87_sio_data));
2814 isa_address = 0;
2815 err = it87_find(sioaddr[i], &isa_address, &sio_data);
2816 if (err || isa_address == 0)
2817 continue;
2818
2819 err = it87_device_add(i, isa_address, &sio_data);
2820 if (err)
2821 goto exit_dev_unregister;
2822 found = true;
b74f3fdd 2823 }
2824
e84bd953
GR		 2825 if (!found) {
2826 err = -ENODEV;
2827 goto exit_unregister;
2828 }
b74f3fdd 2829 return 0;
e84bd953
GR		 2830
2831exit_dev_unregister:
2832 /* NULL check handled by platform_device_unregister */
2833 platform_device_unregister(it87_pdev[0]);
2834exit_unregister:
2835 platform_driver_unregister(&it87_driver);
2836 return err;
1da177e4
LT		 2837}
2838
2839static void __exit sm_it87_exit(void)
2840{
e84bd953
GR		 2841 /* NULL check handled by platform_device_unregister */
2842 platform_device_unregister(it87_pdev[1]);
2843 platform_device_unregister(it87_pdev[0]);
b74f3fdd 2844 platform_driver_unregister(&it87_driver);
1da177e4
LT		 2845}
2846
2847
7c81c60f 2848MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
44c1bcd4 2849MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
1da177e4
LT		 2850module_param(update_vbat, bool, 0);
2851MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
2852module_param(fix_pwm_polarity, bool, 0);
5f2dc798
JD		 2853MODULE_PARM_DESC(fix_pwm_polarity,
2854 "Force PWM polarity to active high (DANGEROUS)");
1da177e4
LT		 2855MODULE_LICENSE("GPL");
2856
2857module_init(sm_it87_init);
2858module_exit(sm_it87_exit);
Linux kernel - Deliverables
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