[deliverable/linux.git] / drivers / i2c / busses / i2c-ocores.c

/*
 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
 * (http://www.opencores.org/projects.cgi/web/i2c/overview).
 *
 * Peter Korsgaard <jacmet@sunsite.dk>
 *
 * Support for the GRLIB port of the controller by
 * Andreas Larsson <andreas@gaisler.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/i2c-ocores.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/log2.h>

struct ocores_i2c {
	void __iomem *base;
	u32 reg_shift;
	u32 reg_io_width;
	wait_queue_head_t wait;
	struct i2c_adapter adap;
	struct i2c_msg *msg;
	int pos;
	int nmsgs;
	int state; /* see STATE_ */
	struct clk *clk;
	int ip_clock_khz;
	int bus_clock_khz;
	void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
	u8 (*getreg)(struct ocores_i2c *i2c, int reg);
};

/* registers */
#define OCI2C_PRELOW		0
#define OCI2C_PREHIGH		1
#define OCI2C_CONTROL		2
#define OCI2C_DATA		3
#define OCI2C_CMD		4 /* write only */
#define OCI2C_STATUS		4 /* read only, same address as OCI2C_CMD */

#define OCI2C_CTRL_IEN		0x40
#define OCI2C_CTRL_EN		0x80

#define OCI2C_CMD_START		0x91
#define OCI2C_CMD_STOP		0x41
#define OCI2C_CMD_READ		0x21
#define OCI2C_CMD_WRITE		0x11
#define OCI2C_CMD_READ_ACK	0x21
#define OCI2C_CMD_READ_NACK	0x29
#define OCI2C_CMD_IACK		0x01

#define OCI2C_STAT_IF		0x01
#define OCI2C_STAT_TIP		0x02
#define OCI2C_STAT_ARBLOST	0x20
#define OCI2C_STAT_BUSY		0x40
#define OCI2C_STAT_NACK		0x80

#define STATE_DONE		0
#define STATE_START		1
#define STATE_WRITE		2
#define STATE_READ		3
#define STATE_ERROR		4

#define TYPE_OCORES		0
#define TYPE_GRLIB		1

static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite8(value, i2c->base + (reg << i2c->reg_shift));
}

static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite16(value, i2c->base + (reg << i2c->reg_shift));
}

static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite32(value, i2c->base + (reg << i2c->reg_shift));
}

static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
}

static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
{
	iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
{
	return ioread8(i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
{
	return ioread16(i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
{
	return ioread32(i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
{
	return ioread16be(i2c->base + (reg << i2c->reg_shift));
}

static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
{
	return ioread32be(i2c->base + (reg << i2c->reg_shift));
}

static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
{
	i2c->setreg(i2c, reg, value);
}

static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
{
	return i2c->getreg(i2c, reg);
}

static void ocores_process(struct ocores_i2c *i2c)
{
	struct i2c_msg *msg = i2c->msg;
	u8 stat = oc_getreg(i2c, OCI2C_STATUS);

	if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
		/* stop has been sent */
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
		wake_up(&i2c->wait);
		return;
	}

	/* error? */
	if (stat & OCI2C_STAT_ARBLOST) {
		i2c->state = STATE_ERROR;
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
		return;
	}

	if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
		i2c->state =
			(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;

		if (stat & OCI2C_STAT_NACK) {
			i2c->state = STATE_ERROR;
			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
			return;
		}
	} else
		msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);

	/* end of msg? */
	if (i2c->pos == msg->len) {
		i2c->nmsgs--;
		i2c->msg++;
		i2c->pos = 0;
		msg = i2c->msg;

		if (i2c->nmsgs) {	/* end? */
			/* send start? */
			if (!(msg->flags & I2C_M_NOSTART)) {
				u8 addr = i2c_8bit_addr_from_msg(msg);

				i2c->state = STATE_START;

				oc_setreg(i2c, OCI2C_DATA, addr);
				oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
				return;
			} else
				i2c->state = (msg->flags & I2C_M_RD)
					? STATE_READ : STATE_WRITE;
		} else {
			i2c->state = STATE_DONE;
			oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
			return;
		}
	}

	if (i2c->state == STATE_READ) {
		oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
			  OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
	} else {
		oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
		oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
	}
}

static irqreturn_t ocores_isr(int irq, void *dev_id)
{
	struct ocores_i2c *i2c = dev_id;

	ocores_process(i2c);

	return IRQ_HANDLED;
}

static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct ocores_i2c *i2c = i2c_get_adapdata(adap);

	i2c->msg = msgs;
	i2c->pos = 0;
	i2c->nmsgs = num;
	i2c->state = STATE_START;

	oc_setreg(i2c, OCI2C_DATA,
			(i2c->msg->addr << 1) |
			((i2c->msg->flags & I2C_M_RD) ? 1:0));

	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);

	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
			       (i2c->state == STATE_DONE), HZ))
		return (i2c->state == STATE_DONE) ? num : -EIO;
	else
		return -ETIMEDOUT;
}

static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
{
	int prescale;
	int diff;
	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);

	/* make sure the device is disabled */
	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
	prescale = clamp(prescale, 0, 0xffff);

	diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
	if (abs(diff) > i2c->bus_clock_khz / 10) {
		dev_err(dev,
			"Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
			i2c->ip_clock_khz, i2c->bus_clock_khz);
		return -EINVAL;
	}

	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);

	/* Init the device */
	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);

	return 0;
}


static u32 ocores_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm ocores_algorithm = {
	.master_xfer = ocores_xfer,
	.functionality = ocores_func,
};

static struct i2c_adapter ocores_adapter = {
	.owner = THIS_MODULE,
	.name = "i2c-ocores",
	.class = I2C_CLASS_DEPRECATED,
	.algo = &ocores_algorithm,
};

static const struct of_device_id ocores_i2c_match[] = {
	{
		.compatible = "opencores,i2c-ocores",
		.data = (void *)TYPE_OCORES,
	},
	{
		.compatible = "aeroflexgaisler,i2cmst",
		.data = (void *)TYPE_GRLIB,
	},
	{},
};
MODULE_DEVICE_TABLE(of, ocores_i2c_match);

#ifdef CONFIG_OF
/* Read and write functions for the GRLIB port of the controller. Registers are
 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
 * register. The subsequent registers has their offset decreased accordingly. */
static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
{
	u32 rd;
	int rreg = reg;
	if (reg != OCI2C_PRELOW)
		rreg--;
	rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
	if (reg == OCI2C_PREHIGH)
		return (u8)(rd >> 8);
	else
		return (u8)rd;
}

static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
{
	u32 curr, wr;
	int rreg = reg;
	if (reg != OCI2C_PRELOW)
		rreg--;
	if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
		curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
		if (reg == OCI2C_PRELOW)
			wr = (curr & 0xff00) | value;
		else
			wr = (((u32)value) << 8) | (curr & 0xff);
	} else {
		wr = value;
	}
	iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
}

static int ocores_i2c_of_probe(struct platform_device *pdev,
				struct ocores_i2c *i2c)
{
	struct device_node *np = pdev->dev.of_node;
	const struct of_device_id *match;
	u32 val;
	u32 clock_frequency;
	bool clock_frequency_present;

	if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
		/* no 'reg-shift', check for deprecated 'regstep' */
		if (!of_property_read_u32(np, "regstep", &val)) {
			if (!is_power_of_2(val)) {
				dev_err(&pdev->dev, "invalid regstep %d\n",
					val);
				return -EINVAL;
			}
			i2c->reg_shift = ilog2(val);
			dev_warn(&pdev->dev,
				"regstep property deprecated, use reg-shift\n");
		}
	}

	clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
							&clock_frequency);
	i2c->bus_clock_khz = 100;

	i2c->clk = devm_clk_get(&pdev->dev, NULL);

	if (!IS_ERR(i2c->clk)) {
		int ret = clk_prepare_enable(i2c->clk);

		if (ret) {
			dev_err(&pdev->dev,
				"clk_prepare_enable failed: %d\n", ret);
			return ret;
		}
		i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
		if (clock_frequency_present)
			i2c->bus_clock_khz = clock_frequency / 1000;
	}

	if (i2c->ip_clock_khz == 0) {
		if (of_property_read_u32(np, "opencores,ip-clock-frequency",
						&val)) {
			if (!clock_frequency_present) {
				dev_err(&pdev->dev,
					"Missing required parameter 'opencores,ip-clock-frequency'\n");
				clk_disable_unprepare(i2c->clk);
				return -ENODEV;
			}
			i2c->ip_clock_khz = clock_frequency / 1000;
			dev_warn(&pdev->dev,
				 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
		} else {
			i2c->ip_clock_khz = val / 1000;
			if (clock_frequency_present)
				i2c->bus_clock_khz = clock_frequency / 1000;
		}
	}

	of_property_read_u32(pdev->dev.of_node, "reg-io-width",
				&i2c->reg_io_width);

	match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
	if (match && (long)match->data == TYPE_GRLIB) {
		dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
		i2c->setreg = oc_setreg_grlib;
		i2c->getreg = oc_getreg_grlib;
	}

	return 0;
}
#else
#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
#endif

static int ocores_i2c_probe(struct platform_device *pdev)
{
	struct ocores_i2c *i2c;
	struct ocores_i2c_platform_data *pdata;
	struct resource *res;
	int irq;
	int ret;
	int i;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
	if (!i2c)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2c->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(i2c->base))
		return PTR_ERR(i2c->base);

	pdata = dev_get_platdata(&pdev->dev);
	if (pdata) {
		i2c->reg_shift = pdata->reg_shift;
		i2c->reg_io_width = pdata->reg_io_width;
		i2c->ip_clock_khz = pdata->clock_khz;
		i2c->bus_clock_khz = 100;
	} else {
		ret = ocores_i2c_of_probe(pdev, i2c);
		if (ret)
			return ret;
	}

	if (i2c->reg_io_width == 0)
		i2c->reg_io_width = 1; /* Set to default value */

	if (!i2c->setreg || !i2c->getreg) {
		bool be = pdata ? pdata->big_endian :
			of_device_is_big_endian(pdev->dev.of_node);

		switch (i2c->reg_io_width) {
		case 1:
			i2c->setreg = oc_setreg_8;
			i2c->getreg = oc_getreg_8;
			break;

		case 2:
			i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
			i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
			break;

		case 4:
			i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
			i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
			break;

		default:
			dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
				i2c->reg_io_width);
			ret = -EINVAL;
			goto err_clk;
		}
	}

	ret = ocores_init(&pdev->dev, i2c);
	if (ret)
		goto err_clk;

	init_waitqueue_head(&i2c->wait);
	ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
			       pdev->name, i2c);
	if (ret) {
		dev_err(&pdev->dev, "Cannot claim IRQ\n");
		goto err_clk;
	}

	/* hook up driver to tree */
	platform_set_drvdata(pdev, i2c);
	i2c->adap = ocores_adapter;
	i2c_set_adapdata(&i2c->adap, i2c);
	i2c->adap.dev.parent = &pdev->dev;
	i2c->adap.dev.of_node = pdev->dev.of_node;

	/* add i2c adapter to i2c tree */
	ret = i2c_add_adapter(&i2c->adap);
	if (ret)
		goto err_clk;

	/* add in known devices to the bus */
	if (pdata) {
		for (i = 0; i < pdata->num_devices; i++)
			i2c_new_device(&i2c->adap, pdata->devices + i);
	}

	return 0;

err_clk:
	clk_disable_unprepare(i2c->clk);
	return ret;
}

static int ocores_i2c_remove(struct platform_device *pdev)
{
	struct ocores_i2c *i2c = platform_get_drvdata(pdev);

	/* disable i2c logic */
	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
		  & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	/* remove adapter & data */
	i2c_del_adapter(&i2c->adap);

	if (!IS_ERR(i2c->clk))
		clk_disable_unprepare(i2c->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int ocores_i2c_suspend(struct device *dev)
{
	struct ocores_i2c *i2c = dev_get_drvdata(dev);
	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);

	/* make sure the device is disabled */
	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));

	if (!IS_ERR(i2c->clk))
		clk_disable_unprepare(i2c->clk);
	return 0;
}

static int ocores_i2c_resume(struct device *dev)
{
	struct ocores_i2c *i2c = dev_get_drvdata(dev);

	if (!IS_ERR(i2c->clk)) {
		unsigned long rate;
		int ret = clk_prepare_enable(i2c->clk);

		if (ret) {
			dev_err(dev,
				"clk_prepare_enable failed: %d\n", ret);
			return ret;
		}
		rate = clk_get_rate(i2c->clk) / 1000;
		if (rate)
			i2c->ip_clock_khz = rate;
	}
	return ocores_init(dev, i2c);
}

static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
#define OCORES_I2C_PM	(&ocores_i2c_pm)
#else
#define OCORES_I2C_PM	NULL
#endif

static struct platform_driver ocores_i2c_driver = {
	.probe   = ocores_i2c_probe,
	.remove  = ocores_i2c_remove,
	.driver  = {
		.name = "ocores-i2c",
		.of_match_table = ocores_i2c_match,
		.pm = OCORES_I2C_PM,
	},
};

module_platform_driver(ocores_i2c_driver);

MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
MODULE_DESCRIPTION("OpenCores I2C bus driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ocores-i2c");
Commit	Line	Data
18f98b1e PK	1	/*
	2	* i2c-ocores.c: I2C bus driver for OpenCores I2C controller
	3	* (http://www.opencores.org/projects.cgi/web/i2c/overview).
	4	*
	5	* Peter Korsgaard <jacmet@sunsite.dk>
	6	*
a000b8c1 AL	7	* Support for the GRLIB port of the controller by
	8	* Andreas Larsson <andreas@gaisler.com>
	9	*
18f98b1e PK	10	* This file is licensed under the terms of the GNU General Public License
	11	* version 2. This program is licensed "as is" without any warranty of any
	12	* kind, whether express or implied.
	13	*/
	14
e961a094	15	#include <linux/clk.h>
84dbf809	16	#include <linux/err.h>
18f98b1e PK	17	#include <linux/kernel.h>
18f98b1e PK	18	#include <linux/module.h>
18f98b1e PK	19	#include <linux/errno.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/i2c.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/wait.h>
	24	#include <linux/i2c-ocores.h>
5a0e3ad6	25	#include <linux/slab.h>
21782180	26	#include <linux/io.h>
8bb986a8	27	#include <linux/log2.h>
18f98b1e PK	28
	29	struct ocores_i2c {
	30	void __iomem *base;
8bb986a8	31	u32 reg_shift;
7326e38f	32	u32 reg_io_width;
18f98b1e PK	33	wait_queue_head_t wait;
	34	struct i2c_adapter adap;
	35	struct i2c_msg *msg;
	36	int pos;
	37	int nmsgs;
	38	int state; /* see STATE_ */
e961a094	39	struct clk *clk;
3a33a854 MF	40	int ip_clock_khz;
3a33a854 MF	41	int bus_clock_khz;
a000b8c1 AL	42	void (setreg)(struct ocores_i2c i2c, int reg, u8 value);
a000b8c1 AL	43	u8 (getreg)(struct ocores_i2c i2c, int reg);
18f98b1e PK	44	};
	45
	46	/* registers */
	47	#define OCI2C_PRELOW 0
	48	#define OCI2C_PREHIGH 1
	49	#define OCI2C_CONTROL 2
	50	#define OCI2C_DATA 3
1ded969f PK	51	#define OCI2C_CMD 4 /* write only */
1ded969f PK	52	#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
18f98b1e PK	53
	54	#define OCI2C_CTRL_IEN 0x40
	55	#define OCI2C_CTRL_EN 0x80
	56
	57	#define OCI2C_CMD_START 0x91
	58	#define OCI2C_CMD_STOP 0x41
	59	#define OCI2C_CMD_READ 0x21
	60	#define OCI2C_CMD_WRITE 0x11
	61	#define OCI2C_CMD_READ_ACK 0x21
	62	#define OCI2C_CMD_READ_NACK 0x29
	63	#define OCI2C_CMD_IACK 0x01
	64
	65	#define OCI2C_STAT_IF 0x01
	66	#define OCI2C_STAT_TIP 0x02
	67	#define OCI2C_STAT_ARBLOST 0x20
	68	#define OCI2C_STAT_BUSY 0x40
	69	#define OCI2C_STAT_NACK 0x80
	70
	71	#define STATE_DONE 0
	72	#define STATE_START 1
	73	#define STATE_WRITE 2
	74	#define STATE_READ 3
	75	#define STATE_ERROR 4
	76
a000b8c1 AL	77	#define TYPE_OCORES 0
	78	#define TYPE_GRLIB 1
	79
	80	static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
18f98b1e	81	{
a000b8c1 AL	82	iowrite8(value, i2c->base + (reg << i2c->reg_shift));
	83	}
	84
	85	static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
	86	{
	87	iowrite16(value, i2c->base + (reg << i2c->reg_shift));
	88	}
	89
	90	static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
	91	{
	92	iowrite32(value, i2c->base + (reg << i2c->reg_shift));
	93	}
	94
b2991676 MF	95	static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
	96	{
	97	iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
	98	}
	99
	100	static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
	101	{
	102	iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
	103	}
	104
a000b8c1 AL	105	static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
	106	{
	107	return ioread8(i2c->base + (reg << i2c->reg_shift));
	108	}
	109
	110	static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
	111	{
	112	return ioread16(i2c->base + (reg << i2c->reg_shift));
	113	}
	114
	115	static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
	116	{
	117	return ioread32(i2c->base + (reg << i2c->reg_shift));
	118	}
	119
b2991676 MF	120	static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
	121	{
	122	return ioread16be(i2c->base + (reg << i2c->reg_shift));
	123	}
	124
	125	static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
	126	{
	127	return ioread32be(i2c->base + (reg << i2c->reg_shift));
	128	}
	129
18f98b1e PK	130	static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
18f98b1e PK	131	{
a000b8c1	132	i2c->setreg(i2c, reg, value);
18f98b1e PK	133	}
	134
	135	static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
	136	{
a000b8c1	137	return i2c->getreg(i2c, reg);
18f98b1e PK	138	}
	139
	140	static void ocores_process(struct ocores_i2c *i2c)
	141	{
	142	struct i2c_msg *msg = i2c->msg;
	143	u8 stat = oc_getreg(i2c, OCI2C_STATUS);
	144
	145	if ((i2c->state == STATE_DONE) \|\| (i2c->state == STATE_ERROR)) {
	146	/* stop has been sent */
	147	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	148	wake_up(&i2c->wait);
	149	return;
	150	}
	151
	152	/* error? */
	153	if (stat & OCI2C_STAT_ARBLOST) {
	154	i2c->state = STATE_ERROR;
	155	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	156	return;
	157	}
	158
	159	if ((i2c->state == STATE_START) \|\| (i2c->state == STATE_WRITE)) {
	160	i2c->state =
	161	(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
	162
	163	if (stat & OCI2C_STAT_NACK) {
	164	i2c->state = STATE_ERROR;
	165	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	166	return;
	167	}
	168	} else
	169	msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
	170
	171	/* end of msg? */
	172	if (i2c->pos == msg->len) {
	173	i2c->nmsgs--;
	174	i2c->msg++;
	175	i2c->pos = 0;
	176	msg = i2c->msg;
	177
	178	if (i2c->nmsgs) { /* end? */
	179	/* send start? */
	180	if (!(msg->flags & I2C_M_NOSTART)) {
380a295c	181	u8 addr = i2c_8bit_addr_from_msg(msg);
18f98b1e PK	182
	183	i2c->state = STATE_START;
	184
	185	oc_setreg(i2c, OCI2C_DATA, addr);
	186	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
	187	return;
	188	} else
	189	i2c->state = (msg->flags & I2C_M_RD)
	190	? STATE_READ : STATE_WRITE;
	191	} else {
	192	i2c->state = STATE_DONE;
	193	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
	194	return;
	195	}
	196	}
	197
	198	if (i2c->state == STATE_READ) {
	199	oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
	200	OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
	201	} else {
	202	oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
	203	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
	204	}
	205	}
	206
7d12e780	207	static irqreturn_t ocores_isr(int irq, void *dev_id)
18f98b1e PK	208	{
	209	struct ocores_i2c *i2c = dev_id;
	210
	211	ocores_process(i2c);
	212
	213	return IRQ_HANDLED;
	214	}
	215
	216	static int ocores_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
	217	{
	218	struct ocores_i2c *i2c = i2c_get_adapdata(adap);
	219
	220	i2c->msg = msgs;
	221	i2c->pos = 0;
	222	i2c->nmsgs = num;
	223	i2c->state = STATE_START;
	224
	225	oc_setreg(i2c, OCI2C_DATA,
	226	(i2c->msg->addr << 1) \|
	227	((i2c->msg->flags & I2C_M_RD) ? 1:0));
	228
	229	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
	230
	231	if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) \|\|
	232	(i2c->state == STATE_DONE), HZ))
	233	return (i2c->state == STATE_DONE) ? num : -EIO;
	234	else
	235	return -ETIMEDOUT;
	236	}
	237
3a33a854	238	static int ocores_init(struct device dev, struct ocores_i2c i2c)
18f98b1e PK	239	{
18f98b1e PK	240	int prescale;
3a33a854	241	int diff;
18f98b1e PK	242	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
	243
	244	/* make sure the device is disabled */
	245	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	246
3a33a854 MF	247	prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
	248	prescale = clamp(prescale, 0, 0xffff);
	249
	250	diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
	251	if (abs(diff) > i2c->bus_clock_khz / 10) {
	252	dev_err(dev,
	253	"Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
	254	i2c->ip_clock_khz, i2c->bus_clock_khz);
	255	return -EINVAL;
	256	}
	257
18f98b1e PK	258	oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
	259	oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
	260
	261	/* Init the device */
	262	oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
	263	oc_setreg(i2c, OCI2C_CONTROL, ctrl \| OCI2C_CTRL_IEN \| OCI2C_CTRL_EN);
3a33a854 MF	264
3a33a854 MF	265	return 0;
18f98b1e PK	266	}
	267
	268
	269	static u32 ocores_func(struct i2c_adapter *adap)
	270	{
	271	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	272	}
	273
8f9082c5	274	static const struct i2c_algorithm ocores_algorithm = {
1ce97e07 WS	275	.master_xfer = ocores_xfer,
1ce97e07 WS	276	.functionality = ocores_func,
18f98b1e PK	277	};
	278
	279	static struct i2c_adapter ocores_adapter = {
1ce97e07 WS	280	.owner = THIS_MODULE,
	281	.name = "i2c-ocores",
	282	.class = I2C_CLASS_DEPRECATED,
	283	.algo = &ocores_algorithm,
18f98b1e PK	284	};
18f98b1e PK	285
eae45e5d	286	static const struct of_device_id ocores_i2c_match[] = {
a000b8c1 AL	287	{
	288	.compatible = "opencores,i2c-ocores",
	289	.data = (void *)TYPE_OCORES,
	290	},
	291	{
	292	.compatible = "aeroflexgaisler,i2cmst",
	293	.data = (void *)TYPE_GRLIB,
	294	},
	295	{},
	296	};
	297	MODULE_DEVICE_TABLE(of, ocores_i2c_match);
	298
049bb69d	299	#ifdef CONFIG_OF
c5d54744 AL	300	/* Read and write functions for the GRLIB port of the controller. Registers are
	301	* 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
	302	* register. The subsequent registers has their offset decreased accordingly. */
	303	static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
	304	{
	305	u32 rd;
	306	int rreg = reg;
	307	if (reg != OCI2C_PRELOW)
	308	rreg--;
	309	rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
	310	if (reg == OCI2C_PREHIGH)
	311	return (u8)(rd >> 8);
	312	else
	313	return (u8)rd;
	314	}
	315
	316	static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
	317	{
	318	u32 curr, wr;
	319	int rreg = reg;
	320	if (reg != OCI2C_PRELOW)
	321	rreg--;
	322	if (reg == OCI2C_PRELOW \|\| reg == OCI2C_PREHIGH) {
	323	curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
	324	if (reg == OCI2C_PRELOW)
	325	wr = (curr & 0xff00) \| value;
	326	else
	327	wr = (((u32)value) << 8) \| (curr & 0xff);
	328	} else {
	329	wr = value;
	330	}
	331	iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
	332	}
	333
9ae97a89 J	334	static int ocores_i2c_of_probe(struct platform_device *pdev,
9ae97a89 J	335	struct ocores_i2c *i2c)
049bb69d	336	{
8bb986a8	337	struct device_node *np = pdev->dev.of_node;
a000b8c1	338	const struct of_device_id *match;
8bb986a8	339	u32 val;
3a33a854 MF	340	u32 clock_frequency;
3a33a854 MF	341	bool clock_frequency_present;
8bb986a8 GR	342
	343	if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
	344	/* no 'reg-shift', check for deprecated 'regstep' */
	345	if (!of_property_read_u32(np, "regstep", &val)) {
	346	if (!is_power_of_2(val)) {
	347	dev_err(&pdev->dev, "invalid regstep %d\n",
	348	val);
	349	return -EINVAL;
	350	}
	351	i2c->reg_shift = ilog2(val);
	352	dev_warn(&pdev->dev,
	353	"regstep property deprecated, use reg-shift\n");
	354	}
049bb69d	355	}
049bb69d	356
3a33a854 MF	357	clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
	358	&clock_frequency);
	359	i2c->bus_clock_khz = 100;
	360
e961a094 MF	361	i2c->clk = devm_clk_get(&pdev->dev, NULL);
	362
	363	if (!IS_ERR(i2c->clk)) {
	364	int ret = clk_prepare_enable(i2c->clk);
	365
	366	if (ret) {
	367	dev_err(&pdev->dev,
	368	"clk_prepare_enable failed: %d\n", ret);
	369	return ret;
	370	}
	371	i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
	372	if (clock_frequency_present)
	373	i2c->bus_clock_khz = clock_frequency / 1000;
0d8fb599 WS	374	}
	375
	376	if (i2c->ip_clock_khz == 0) {
	377	if (of_property_read_u32(np, "opencores,ip-clock-frequency",
	378	&val)) {
	379	if (!clock_frequency_present) {
	380	dev_err(&pdev->dev,
	381	"Missing required parameter 'opencores,ip-clock-frequency'\n");
97ccd4af	382	clk_disable_unprepare(i2c->clk);
0d8fb599 WS	383	return -ENODEV;
	384	}
	385	i2c->ip_clock_khz = clock_frequency / 1000;
	386	dev_warn(&pdev->dev,
	387	"Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
	388	} else {
	389	i2c->ip_clock_khz = val / 1000;
	390	if (clock_frequency_present)
	391	i2c->bus_clock_khz = clock_frequency / 1000;
3a33a854	392	}
049bb69d	393	}
049bb69d	394
7326e38f GR	395	of_property_read_u32(pdev->dev.of_node, "reg-io-width",
7326e38f GR	396	&i2c->reg_io_width);
a000b8c1 AL	397
a000b8c1 AL	398	match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
6beaddf2	399	if (match && (long)match->data == TYPE_GRLIB) {
a000b8c1 AL	400	dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
	401	i2c->setreg = oc_setreg_grlib;
	402	i2c->getreg = oc_getreg_grlib;
	403	}
	404
049bb69d JB	405	return 0;
	406	}
	407	#else
	408	#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
	409	#endif
18f98b1e	410
0b255e92	411	static int ocores_i2c_probe(struct platform_device *pdev)
18f98b1e PK	412	{
	413	struct ocores_i2c *i2c;
	414	struct ocores_i2c_platform_data *pdata;
f5f35a92 AL	415	struct resource *res;
f5f35a92 AL	416	int irq;
18f98b1e	417	int ret;
dd14be4c	418	int i;
18f98b1e	419
f5f35a92 AL	420	irq = platform_get_irq(pdev, 0);
	421	if (irq < 0)
	422	return irq;
18f98b1e	423
47def5b8	424	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
18f98b1e PK	425	if (!i2c)
	426	return -ENOMEM;
	427
b7d12a86	428	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
84dbf809 TR	429	i2c->base = devm_ioremap_resource(&pdev->dev, res);
	430	if (IS_ERR(i2c->base))
	431	return PTR_ERR(i2c->base);
18f98b1e	432
6d4028c6	433	pdata = dev_get_platdata(&pdev->dev);
049bb69d	434	if (pdata) {
8bb986a8	435	i2c->reg_shift = pdata->reg_shift;
7326e38f	436	i2c->reg_io_width = pdata->reg_io_width;
3a33a854 MF	437	i2c->ip_clock_khz = pdata->clock_khz;
3a33a854 MF	438	i2c->bus_clock_khz = 100;
049bb69d JB	439	} else {
	440	ret = ocores_i2c_of_probe(pdev, i2c);
	441	if (ret)
	442	return ret;
	443	}
	444
7326e38f GR	445	if (i2c->reg_io_width == 0)
	446	i2c->reg_io_width = 1; /* Set to default value */
	447
a000b8c1	448	if (!i2c->setreg \|\| !i2c->getreg) {
b2991676 MF	449	bool be = pdata ? pdata->big_endian :
	450	of_device_is_big_endian(pdev->dev.of_node);
	451
a000b8c1 AL	452	switch (i2c->reg_io_width) {
	453	case 1:
	454	i2c->setreg = oc_setreg_8;
	455	i2c->getreg = oc_getreg_8;
	456	break;
	457
	458	case 2:
b2991676 MF	459	i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
b2991676 MF	460	i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
a000b8c1 AL	461	break;
	462
	463	case 4:
b2991676 MF	464	i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
b2991676 MF	465	i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
a000b8c1 AL	466	break;
	467
	468	default:
	469	dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
	470	i2c->reg_io_width);
97ccd4af AK	471	ret = -EINVAL;
97ccd4af AK	472	goto err_clk;
a000b8c1 AL	473	}
	474	}
	475
3a33a854 MF	476	ret = ocores_init(&pdev->dev, i2c);
3a33a854 MF	477	if (ret)
97ccd4af	478	goto err_clk;
18f98b1e PK	479
18f98b1e PK	480	init_waitqueue_head(&i2c->wait);
f5f35a92	481	ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
47def5b8	482	pdev->name, i2c);
18f98b1e PK	483	if (ret) {
18f98b1e PK	484	dev_err(&pdev->dev, "Cannot claim IRQ\n");
97ccd4af	485	goto err_clk;
18f98b1e PK	486	}
	487
	488	/* hook up driver to tree */
	489	platform_set_drvdata(pdev, i2c);
	490	i2c->adap = ocores_adapter;
	491	i2c_set_adapdata(&i2c->adap, i2c);
	492	i2c->adap.dev.parent = &pdev->dev;
049bb69d	493	i2c->adap.dev.of_node = pdev->dev.of_node;
18f98b1e PK	494
	495	/* add i2c adapter to i2c tree */
	496	ret = i2c_add_adapter(&i2c->adap);
ea734404	497	if (ret)
97ccd4af	498	goto err_clk;
18f98b1e	499
dd14be4c	500	/* add in known devices to the bus */
049bb69d JB	501	if (pdata) {
	502	for (i = 0; i < pdata->num_devices; i++)
	503	i2c_new_device(&i2c->adap, pdata->devices + i);
	504	}
dd14be4c	505
18f98b1e	506	return 0;
97ccd4af AK	507
	508	err_clk:
	509	clk_disable_unprepare(i2c->clk);
	510	return ret;
18f98b1e PK	511	}
18f98b1e PK	512
0b255e92	513	static int ocores_i2c_remove(struct platform_device *pdev)
18f98b1e PK	514	{
18f98b1e PK	515	struct ocores_i2c *i2c = platform_get_drvdata(pdev);
18f98b1e PK	516
	517	/* disable i2c logic */
	518	oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
	519	& ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	520
	521	/* remove adapter & data */
	522	i2c_del_adapter(&i2c->adap);
18f98b1e	523
e961a094 MF	524	if (!IS_ERR(i2c->clk))
	525	clk_disable_unprepare(i2c->clk);
	526
18f98b1e PK	527	return 0;
	528	}
	529
f076e916	530	#ifdef CONFIG_PM_SLEEP
84603c7c	531	static int ocores_i2c_suspend(struct device *dev)
2373c180	532	{
84603c7c	533	struct ocores_i2c *i2c = dev_get_drvdata(dev);
2373c180 ML	534	u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
	535
	536	/* make sure the device is disabled */
	537	oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN\|OCI2C_CTRL_IEN));
	538
e961a094 MF	539	if (!IS_ERR(i2c->clk))
e961a094 MF	540	clk_disable_unprepare(i2c->clk);
2373c180 ML	541	return 0;
	542	}
	543
84603c7c	544	static int ocores_i2c_resume(struct device *dev)
2373c180	545	{
84603c7c	546	struct ocores_i2c *i2c = dev_get_drvdata(dev);
2373c180	547
e961a094	548	if (!IS_ERR(i2c->clk)) {
0d8fb599	549	unsigned long rate;
e961a094 MF	550	int ret = clk_prepare_enable(i2c->clk);
	551
	552	if (ret) {
	553	dev_err(dev,
	554	"clk_prepare_enable failed: %d\n", ret);
	555	return ret;
	556	}
0d8fb599 WS	557	rate = clk_get_rate(i2c->clk) / 1000;
	558	if (rate)
	559	i2c->ip_clock_khz = rate;
e961a094	560	}
3a33a854	561	return ocores_init(dev, i2c);
2373c180	562	}
84603c7c RW	563
	564	static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
	565	#define OCORES_I2C_PM (&ocores_i2c_pm)
2373c180	566	#else
84603c7c	567	#define OCORES_I2C_PM NULL
2373c180 ML	568	#endif
2373c180 ML	569
18f98b1e	570	static struct platform_driver ocores_i2c_driver = {
2373c180	571	.probe = ocores_i2c_probe,
0b255e92	572	.remove = ocores_i2c_remove,
2373c180	573	.driver = {
18f98b1e	574	.name = "ocores-i2c",
c9e358df	575	.of_match_table = ocores_i2c_match,
84603c7c	576	.pm = OCORES_I2C_PM,
18f98b1e PK	577	},
	578	};
	579
a3664b51	580	module_platform_driver(ocores_i2c_driver);
18f98b1e PK	581
	582	MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
	583	MODULE_DESCRIPTION("OpenCores I2C bus driver");
	584	MODULE_LICENSE("GPL");
a3664b51	585	MODULE_ALIAS("platform:ocores-i2c");