[deliverable/linux.git] / drivers / i2c / busses / i2c-wmt.c

/*
 *  Wondermedia I2C Master Mode Driver
 *
 *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 *
 *  Derived from GPLv2+ licensed source:
 *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2, or
 *  (at your option) any later version. as published by the Free Software
 *  Foundation
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>

#define REG_CR		0x00
#define REG_TCR		0x02
#define REG_CSR		0x04
#define REG_ISR		0x06
#define REG_IMR		0x08
#define REG_CDR		0x0A
#define REG_TR		0x0C
#define REG_MCR		0x0E
#define REG_SLAVE_CR	0x10
#define REG_SLAVE_SR	0x12
#define REG_SLAVE_ISR	0x14
#define REG_SLAVE_IMR	0x16
#define REG_SLAVE_DR	0x18
#define REG_SLAVE_TR	0x1A

/* REG_CR Bit fields */
#define CR_TX_NEXT_ACK		0x0000
#define CR_ENABLE		0x0001
#define CR_TX_NEXT_NO_ACK	0x0002
#define CR_TX_END		0x0004
#define CR_CPU_RDY		0x0008
#define SLAV_MODE_SEL		0x8000

/* REG_TCR Bit fields */
#define TCR_STANDARD_MODE	0x0000
#define TCR_MASTER_WRITE	0x0000
#define TCR_HS_MODE		0x2000
#define TCR_MASTER_READ		0x4000
#define TCR_FAST_MODE		0x8000
#define TCR_SLAVE_ADDR_MASK	0x007F

/* REG_ISR Bit fields */
#define ISR_NACK_ADDR		0x0001
#define ISR_BYTE_END		0x0002
#define ISR_SCL_TIMEOUT		0x0004
#define ISR_WRITE_ALL		0x0007

/* REG_IMR Bit fields */
#define IMR_ENABLE_ALL		0x0007

/* REG_CSR Bit fields */
#define CSR_RCV_NOT_ACK		0x0001
#define CSR_RCV_ACK_MASK	0x0001
#define CSR_READY_MASK		0x0002

/* REG_TR */
#define SCL_TIMEOUT(x)		(((x) & 0xFF) << 8)
#define TR_STD			0x0064
#define TR_HS			0x0019

/* REG_MCR */
#define MCR_APB_96M		7
#define MCR_APB_166M		12

#define I2C_MODE_STANDARD	0
#define I2C_MODE_FAST		1

#define WMT_I2C_TIMEOUT		(msecs_to_jiffies(1000))

struct wmt_i2c_dev {
	struct i2c_adapter	adapter;
	struct completion	complete;
	struct device		*dev;
	void __iomem		*base;
	struct clk		*clk;
	int			mode;
	int			irq;
	u16			cmd_status;
};

static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
{
	unsigned long timeout;

	timeout = jiffies + WMT_I2C_TIMEOUT;
	while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
		if (time_after(jiffies, timeout)) {
			dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
			return -EBUSY;
		}
		msleep(20);
	}

	return 0;
}

static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
{
	int ret = 0;

	if (i2c_dev->cmd_status & ISR_NACK_ADDR)
		ret = -EIO;

	if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
		ret = -ETIMEDOUT;

	return ret;
}

static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
			 int last)
{
	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
	u16 val, tcr_val;
	int ret;
	unsigned long wait_result;
	int xfer_len = 0;

	if (!(pmsg->flags & I2C_M_NOSTART)) {
		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
		if (ret < 0)
			return ret;
	}

	if (pmsg->len == 0) {
		/*
		 * We still need to run through the while (..) once, so
		 * start at -1 and break out early from the loop
		 */
		xfer_len = -1;
		writew(0, i2c_dev->base + REG_CDR);
	} else {
		writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
	}

	if (!(pmsg->flags & I2C_M_NOSTART)) {
		val = readw(i2c_dev->base + REG_CR);
		val &= ~CR_TX_END;
		writew(val, i2c_dev->base + REG_CR);

		val = readw(i2c_dev->base + REG_CR);
		val |= CR_CPU_RDY;
		writew(val, i2c_dev->base + REG_CR);
	}

	reinit_completion(&i2c_dev->complete);

	if (i2c_dev->mode == I2C_MODE_STANDARD)
		tcr_val = TCR_STANDARD_MODE;
	else
		tcr_val = TCR_FAST_MODE;

	tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));

	writew(tcr_val, i2c_dev->base + REG_TCR);

	if (pmsg->flags & I2C_M_NOSTART) {
		val = readw(i2c_dev->base + REG_CR);
		val |= CR_CPU_RDY;
		writew(val, i2c_dev->base + REG_CR);
	}

	while (xfer_len < pmsg->len) {
		wait_result = wait_for_completion_timeout(&i2c_dev->complete,
							msecs_to_jiffies(500));

		if (wait_result == 0)
			return -ETIMEDOUT;

		ret = wmt_check_status(i2c_dev);
		if (ret)
			return ret;

		xfer_len++;

		val = readw(i2c_dev->base + REG_CSR);
		if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
			dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
			return -EIO;
		}

		if (pmsg->len == 0) {
			val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
			writew(val, i2c_dev->base + REG_CR);
			break;
		}

		if (xfer_len == pmsg->len) {
			if (last != 1)
				writew(CR_ENABLE, i2c_dev->base + REG_CR);
		} else {
			writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
								REG_CDR);
			writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
		}
	}

	return 0;
}

static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
			int last)
{
	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
	u16 val, tcr_val;
	int ret;
	unsigned long wait_result;
	u32 xfer_len = 0;

	if (!(pmsg->flags & I2C_M_NOSTART)) {
		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
		if (ret < 0)
			return ret;
	}

	val = readw(i2c_dev->base + REG_CR);
	val &= ~CR_TX_END;
	writew(val, i2c_dev->base + REG_CR);

	val = readw(i2c_dev->base + REG_CR);
	val &= ~CR_TX_NEXT_NO_ACK;
	writew(val, i2c_dev->base + REG_CR);

	if (!(pmsg->flags & I2C_M_NOSTART)) {
		val = readw(i2c_dev->base + REG_CR);
		val |= CR_CPU_RDY;
		writew(val, i2c_dev->base + REG_CR);
	}

	if (pmsg->len == 1) {
		val = readw(i2c_dev->base + REG_CR);
		val |= CR_TX_NEXT_NO_ACK;
		writew(val, i2c_dev->base + REG_CR);
	}

	reinit_completion(&i2c_dev->complete);

	if (i2c_dev->mode == I2C_MODE_STANDARD)
		tcr_val = TCR_STANDARD_MODE;
	else
		tcr_val = TCR_FAST_MODE;

	tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);

	writew(tcr_val, i2c_dev->base + REG_TCR);

	if (pmsg->flags & I2C_M_NOSTART) {
		val = readw(i2c_dev->base + REG_CR);
		val |= CR_CPU_RDY;
		writew(val, i2c_dev->base + REG_CR);
	}

	while (xfer_len < pmsg->len) {
		wait_result = wait_for_completion_timeout(&i2c_dev->complete,
							msecs_to_jiffies(500));

		if (!wait_result)
			return -ETIMEDOUT;

		ret = wmt_check_status(i2c_dev);
		if (ret)
			return ret;

		pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
		xfer_len++;

		if (xfer_len == pmsg->len - 1) {
			val = readw(i2c_dev->base + REG_CR);
			val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
			writew(val, i2c_dev->base + REG_CR);
		} else {
			val = readw(i2c_dev->base + REG_CR);
			val |= CR_CPU_RDY;
			writew(val, i2c_dev->base + REG_CR);
		}
	}

	return 0;
}

static int wmt_i2c_xfer(struct i2c_adapter *adap,
			struct i2c_msg msgs[],
			int num)
{
	struct i2c_msg *pmsg;
	int i, is_last;
	int ret = 0;

	for (i = 0; ret >= 0 && i < num; i++) {
		is_last = ((i + 1) == num);

		pmsg = &msgs[i];
		if (pmsg->flags & I2C_M_RD)
			ret = wmt_i2c_read(adap, pmsg, is_last);
		else
			ret = wmt_i2c_write(adap, pmsg, is_last);
	}

	return (ret < 0) ? ret : i;
}

static u32 wmt_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
}

static const struct i2c_algorithm wmt_i2c_algo = {
	.master_xfer	= wmt_i2c_xfer,
	.functionality	= wmt_i2c_func,
};

static irqreturn_t wmt_i2c_isr(int irq, void *data)
{
	struct wmt_i2c_dev *i2c_dev = data;

	/* save the status and write-clear it */
	i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
	writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);

	complete(&i2c_dev->complete);

	return IRQ_HANDLED;
}

static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
{
	int err;

	err = clk_prepare_enable(i2c_dev->clk);
	if (err) {
		dev_err(i2c_dev->dev, "failed to enable clock\n");
		return err;
	}

	err = clk_set_rate(i2c_dev->clk, 20000000);
	if (err) {
		dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
		clk_disable_unprepare(i2c_dev->clk);
		return err;
	}

	writew(0, i2c_dev->base + REG_CR);
	writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
	writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
	writew(CR_ENABLE, i2c_dev->base + REG_CR);
	readw(i2c_dev->base + REG_CSR);		/* read clear */
	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);

	if (i2c_dev->mode == I2C_MODE_STANDARD)
		writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
	else
		writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);

	return 0;
}

static int wmt_i2c_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct wmt_i2c_dev *i2c_dev;
	struct i2c_adapter *adap;
	struct resource *res;
	int err;
	u32 clk_rate;

	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
	if (!i2c_dev)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(i2c_dev->base))
		return PTR_ERR(i2c_dev->base);

	i2c_dev->irq = irq_of_parse_and_map(np, 0);
	if (!i2c_dev->irq) {
		dev_err(&pdev->dev, "irq missing or invalid\n");
		return -EINVAL;
	}

	i2c_dev->clk = of_clk_get(np, 0);
	if (IS_ERR(i2c_dev->clk)) {
		dev_err(&pdev->dev, "unable to request clock\n");
		return PTR_ERR(i2c_dev->clk);
	}

	i2c_dev->mode = I2C_MODE_STANDARD;
	err = of_property_read_u32(np, "clock-frequency", &clk_rate);
	if ((!err) && (clk_rate == 400000))
		i2c_dev->mode = I2C_MODE_FAST;

	i2c_dev->dev = &pdev->dev;

	err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
							"i2c", i2c_dev);
	if (err) {
		dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
		return err;
	}

	adap = &i2c_dev->adapter;
	i2c_set_adapdata(adap, i2c_dev);
	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
	adap->owner = THIS_MODULE;
	adap->algo = &wmt_i2c_algo;
	adap->dev.parent = &pdev->dev;
	adap->dev.of_node = pdev->dev.of_node;

	init_completion(&i2c_dev->complete);

	err = wmt_i2c_reset_hardware(i2c_dev);
	if (err) {
		dev_err(&pdev->dev, "error initializing hardware\n");
		return err;
	}

	err = i2c_add_adapter(adap);
	if (err)
		return err;

	platform_set_drvdata(pdev, i2c_dev);

	return 0;
}

static int wmt_i2c_remove(struct platform_device *pdev)
{
	struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);

	/* Disable interrupts, clock and delete adapter */
	writew(0, i2c_dev->base + REG_IMR);
	clk_disable_unprepare(i2c_dev->clk);
	i2c_del_adapter(&i2c_dev->adapter);

	return 0;
}

static const struct of_device_id wmt_i2c_dt_ids[] = {
	{ .compatible = "wm,wm8505-i2c" },
	{ /* Sentinel */ },
};

static struct platform_driver wmt_i2c_driver = {
	.probe		= wmt_i2c_probe,
	.remove		= wmt_i2c_remove,
	.driver		= {
		.name	= "wmt-i2c",
		.of_match_table = wmt_i2c_dt_ids,
	},
};

module_platform_driver(wmt_i2c_driver);

MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
Commit	Line	Data
560746eb TP	1	/*
	2	* Wondermedia I2C Master Mode Driver
	3	*
	4	* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
	5	*
	6	* Derived from GPLv2+ licensed source:
	7	* - Copyright (C) 2008 WonderMedia Technologies, Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2, or
	11	* (at your option) any later version. as published by the Free Software
	12	* Foundation
	13	*/
	14
	15	#include <linux/clk.h>
	16	#include <linux/delay.h>
	17	#include <linux/err.h>
	18	#include <linux/i2c.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/io.h>
	21	#include <linux/module.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
560746eb TP	24	#include <linux/of_irq.h>
	25	#include <linux/platform_device.h>
	26
	27	#define REG_CR 0x00
	28	#define REG_TCR 0x02
	29	#define REG_CSR 0x04
	30	#define REG_ISR 0x06
	31	#define REG_IMR 0x08
	32	#define REG_CDR 0x0A
	33	#define REG_TR 0x0C
	34	#define REG_MCR 0x0E
	35	#define REG_SLAVE_CR 0x10
	36	#define REG_SLAVE_SR 0x12
	37	#define REG_SLAVE_ISR 0x14
	38	#define REG_SLAVE_IMR 0x16
	39	#define REG_SLAVE_DR 0x18
	40	#define REG_SLAVE_TR 0x1A
	41
	42	/* REG_CR Bit fields */
	43	#define CR_TX_NEXT_ACK 0x0000
	44	#define CR_ENABLE 0x0001
	45	#define CR_TX_NEXT_NO_ACK 0x0002
	46	#define CR_TX_END 0x0004
	47	#define CR_CPU_RDY 0x0008
	48	#define SLAV_MODE_SEL 0x8000
	49
	50	/* REG_TCR Bit fields */
	51	#define TCR_STANDARD_MODE 0x0000
	52	#define TCR_MASTER_WRITE 0x0000
	53	#define TCR_HS_MODE 0x2000
	54	#define TCR_MASTER_READ 0x4000
	55	#define TCR_FAST_MODE 0x8000
	56	#define TCR_SLAVE_ADDR_MASK 0x007F
	57
	58	/* REG_ISR Bit fields */
	59	#define ISR_NACK_ADDR 0x0001
	60	#define ISR_BYTE_END 0x0002
	61	#define ISR_SCL_TIMEOUT 0x0004
	62	#define ISR_WRITE_ALL 0x0007
	63
	64	/* REG_IMR Bit fields */
	65	#define IMR_ENABLE_ALL 0x0007
	66
	67	/* REG_CSR Bit fields */
	68	#define CSR_RCV_NOT_ACK 0x0001
	69	#define CSR_RCV_ACK_MASK 0x0001
	70	#define CSR_READY_MASK 0x0002
	71
	72	/* REG_TR */
	73	#define SCL_TIMEOUT(x) (((x) & 0xFF) << 8)
	74	#define TR_STD 0x0064
	75	#define TR_HS 0x0019
	76
	77	/* REG_MCR */
	78	#define MCR_APB_96M 7
	79	#define MCR_APB_166M 12
	80
	81	#define I2C_MODE_STANDARD 0
	82	#define I2C_MODE_FAST 1
	83
	84	#define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000))
	85
	86	struct wmt_i2c_dev {
	87	struct i2c_adapter adapter;
88	struct completion complete;
89	struct device *dev;
90	void __iomem *base;
91	struct clk *clk;
92	int mode;
93	int irq;
94	u16 cmd_status;
95	};
96
97	static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
98	{
99	unsigned long timeout;
100
101	timeout = jiffies + WMT_I2C_TIMEOUT;
102	while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
103	if (time_after(jiffies, timeout)) {
104	dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
105	return -EBUSY;
106	}
107	msleep(20);
108	}
109
110	return 0;
111	}
112
113	static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
114	{
115	int ret = 0;
116
117	if (i2c_dev->cmd_status & ISR_NACK_ADDR)
118	ret = -EIO;
119
120	if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
121	ret = -ETIMEDOUT;
122
123	return ret;
124	}
125
126	static int wmt_i2c_write(struct i2c_adapter adap, struct i2c_msg pmsg,
127	int last)
128	{
129	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
130	u16 val, tcr_val;
73958562 NMG	131	int ret;
73958562 NMG	132	unsigned long wait_result;
560746eb TP	133	int xfer_len = 0;
	134
	135	if (!(pmsg->flags & I2C_M_NOSTART)) {
	136	ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
	137	if (ret < 0)
	138	return ret;
	139	}
	140
	141	if (pmsg->len == 0) {
	142	/*
	143	* We still need to run through the while (..) once, so
	144	* start at -1 and break out early from the loop
	145	*/
	146	xfer_len = -1;
	147	writew(0, i2c_dev->base + REG_CDR);
	148	} else {
	149	writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
	150	}
	151
	152	if (!(pmsg->flags & I2C_M_NOSTART)) {
	153	val = readw(i2c_dev->base + REG_CR);
	154	val &= ~CR_TX_END;
	155	writew(val, i2c_dev->base + REG_CR);
	156
	157	val = readw(i2c_dev->base + REG_CR);
	158	val \|= CR_CPU_RDY;
	159	writew(val, i2c_dev->base + REG_CR);
	160	}
	161
16735d02	162	reinit_completion(&i2c_dev->complete);
560746eb TP	163
	164	if (i2c_dev->mode == I2C_MODE_STANDARD)
	165	tcr_val = TCR_STANDARD_MODE;
	166	else
	167	tcr_val = TCR_FAST_MODE;
	168
	169	tcr_val \|= (TCR_MASTER_WRITE \| (pmsg->addr & TCR_SLAVE_ADDR_MASK));
	170
	171	writew(tcr_val, i2c_dev->base + REG_TCR);
	172
	173	if (pmsg->flags & I2C_M_NOSTART) {
	174	val = readw(i2c_dev->base + REG_CR);
	175	val \|= CR_CPU_RDY;
	176	writew(val, i2c_dev->base + REG_CR);
	177	}
	178
	179	while (xfer_len < pmsg->len) {
	180	wait_result = wait_for_completion_timeout(&i2c_dev->complete,
bd9dd73c	181	msecs_to_jiffies(500));
560746eb TP	182
	183	if (wait_result == 0)
	184	return -ETIMEDOUT;
	185
	186	ret = wmt_check_status(i2c_dev);
	187	if (ret)
	188	return ret;
	189
	190	xfer_len++;
	191
	192	val = readw(i2c_dev->base + REG_CSR);
	193	if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
	194	dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
	195	return -EIO;
	196	}
	197
	198	if (pmsg->len == 0) {
	199	val = CR_TX_END \| CR_CPU_RDY \| CR_ENABLE;
	200	writew(val, i2c_dev->base + REG_CR);
	201	break;
	202	}
	203
	204	if (xfer_len == pmsg->len) {
	205	if (last != 1)
	206	writew(CR_ENABLE, i2c_dev->base + REG_CR);
	207	} else {
	208	writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
	209	REG_CDR);
	210	writew(CR_CPU_RDY \| CR_ENABLE, i2c_dev->base + REG_CR);
	211	}
	212	}
	213
	214	return 0;
	215	}
	216
	217	static int wmt_i2c_read(struct i2c_adapter adap, struct i2c_msg pmsg,
	218	int last)
	219	{
	220	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
	221	u16 val, tcr_val;
73958562 NMG	222	int ret;
73958562 NMG	223	unsigned long wait_result;
560746eb TP	224	u32 xfer_len = 0;
	225
	226	if (!(pmsg->flags & I2C_M_NOSTART)) {
	227	ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
	228	if (ret < 0)
	229	return ret;
	230	}
	231
	232	val = readw(i2c_dev->base + REG_CR);
	233	val &= ~CR_TX_END;
	234	writew(val, i2c_dev->base + REG_CR);
	235
	236	val = readw(i2c_dev->base + REG_CR);
	237	val &= ~CR_TX_NEXT_NO_ACK;
	238	writew(val, i2c_dev->base + REG_CR);
	239
	240	if (!(pmsg->flags & I2C_M_NOSTART)) {
	241	val = readw(i2c_dev->base + REG_CR);
	242	val \|= CR_CPU_RDY;
	243	writew(val, i2c_dev->base + REG_CR);
	244	}
	245
	246	if (pmsg->len == 1) {
	247	val = readw(i2c_dev->base + REG_CR);
	248	val \|= CR_TX_NEXT_NO_ACK;
	249	writew(val, i2c_dev->base + REG_CR);
	250	}
	251
16735d02	252	reinit_completion(&i2c_dev->complete);
560746eb TP	253
	254	if (i2c_dev->mode == I2C_MODE_STANDARD)
	255	tcr_val = TCR_STANDARD_MODE;
	256	else
	257	tcr_val = TCR_FAST_MODE;
	258
	259	tcr_val \|= TCR_MASTER_READ \| (pmsg->addr & TCR_SLAVE_ADDR_MASK);
	260
	261	writew(tcr_val, i2c_dev->base + REG_TCR);
	262
	263	if (pmsg->flags & I2C_M_NOSTART) {
	264	val = readw(i2c_dev->base + REG_CR);
	265	val \|= CR_CPU_RDY;
	266	writew(val, i2c_dev->base + REG_CR);
	267	}
	268
	269	while (xfer_len < pmsg->len) {
	270	wait_result = wait_for_completion_timeout(&i2c_dev->complete,
bd9dd73c	271	msecs_to_jiffies(500));
560746eb TP	272
	273	if (!wait_result)
	274	return -ETIMEDOUT;
	275
	276	ret = wmt_check_status(i2c_dev);
	277	if (ret)
	278	return ret;
	279
	280	pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
	281	xfer_len++;
	282
	283	if (xfer_len == pmsg->len - 1) {
	284	val = readw(i2c_dev->base + REG_CR);
	285	val \|= (CR_TX_NEXT_NO_ACK \| CR_CPU_RDY);
	286	writew(val, i2c_dev->base + REG_CR);
	287	} else {
	288	val = readw(i2c_dev->base + REG_CR);
	289	val \|= CR_CPU_RDY;
	290	writew(val, i2c_dev->base + REG_CR);
	291	}
	292	}
	293
	294	return 0;
	295	}
	296
	297	static int wmt_i2c_xfer(struct i2c_adapter *adap,
	298	struct i2c_msg msgs[],
	299	int num)
	300	{
	301	struct i2c_msg *pmsg;
	302	int i, is_last;
	303	int ret = 0;
	304
	305	for (i = 0; ret >= 0 && i < num; i++) {
	306	is_last = ((i + 1) == num);
	307
	308	pmsg = &msgs[i];
	309	if (pmsg->flags & I2C_M_RD)
	310	ret = wmt_i2c_read(adap, pmsg, is_last);
	311	else
	312	ret = wmt_i2c_write(adap, pmsg, is_last);
	313	}
	314
	315	return (ret < 0) ? ret : i;
	316	}
	317
	318	static u32 wmt_i2c_func(struct i2c_adapter *adap)
	319	{
	320	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL \| I2C_FUNC_NOSTART;
	321	}
	322
	323	static const struct i2c_algorithm wmt_i2c_algo = {
	324	.master_xfer = wmt_i2c_xfer,
	325	.functionality = wmt_i2c_func,
	326	};
	327
	328	static irqreturn_t wmt_i2c_isr(int irq, void *data)
	329	{
	330	struct wmt_i2c_dev *i2c_dev = data;
	331
	332	/* save the status and write-clear it */
	333	i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
	334	writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
	335
336	complete(&i2c_dev->complete);
337
338	return IRQ_HANDLED;
339	}
340
341	static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
342	{
343	int err;
344
345	err = clk_prepare_enable(i2c_dev->clk);
346	if (err) {
347	dev_err(i2c_dev->dev, "failed to enable clock\n");
348	return err;
349	}
350
351	err = clk_set_rate(i2c_dev->clk, 20000000);
352	if (err) {
353	dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
2dc9688a	354	clk_disable_unprepare(i2c_dev->clk);
560746eb TP	355	return err;
	356	}
	357
	358	writew(0, i2c_dev->base + REG_CR);
	359	writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
	360	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
	361	writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
	362	writew(CR_ENABLE, i2c_dev->base + REG_CR);
	363	readw(i2c_dev->base + REG_CSR); /* read clear */
	364	writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
	365
	366	if (i2c_dev->mode == I2C_MODE_STANDARD)
	367	writew(SCL_TIMEOUT(128) \| TR_STD, i2c_dev->base + REG_TR);
	368	else
	369	writew(SCL_TIMEOUT(128) \| TR_HS, i2c_dev->base + REG_TR);
	370
	371	return 0;
	372	}
	373
	374	static int wmt_i2c_probe(struct platform_device *pdev)
	375	{
	376	struct device_node *np = pdev->dev.of_node;
	377	struct wmt_i2c_dev *i2c_dev;
	378	struct i2c_adapter *adap;
	379	struct resource *res;
	380	int err;
	381	u32 clk_rate;
	382
	383	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
46797a2a	384	if (!i2c_dev)
560746eb	385	return -ENOMEM;
560746eb TP	386
	387	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	388	i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
	389	if (IS_ERR(i2c_dev->base))
	390	return PTR_ERR(i2c_dev->base);
	391
	392	i2c_dev->irq = irq_of_parse_and_map(np, 0);
	393	if (!i2c_dev->irq) {
	394	dev_err(&pdev->dev, "irq missing or invalid\n");
	395	return -EINVAL;
	396	}
	397
	398	i2c_dev->clk = of_clk_get(np, 0);
	399	if (IS_ERR(i2c_dev->clk)) {
	400	dev_err(&pdev->dev, "unable to request clock\n");
	401	return PTR_ERR(i2c_dev->clk);
	402	}
	403
	404	i2c_dev->mode = I2C_MODE_STANDARD;
	405	err = of_property_read_u32(np, "clock-frequency", &clk_rate);
	406	if ((!err) && (clk_rate == 400000))
	407	i2c_dev->mode = I2C_MODE_FAST;
	408
	409	i2c_dev->dev = &pdev->dev;
	410
	411	err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
	412	"i2c", i2c_dev);
	413	if (err) {
	414	dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
	415	return err;
	416	}
	417
	418	adap = &i2c_dev->adapter;
	419	i2c_set_adapdata(adap, i2c_dev);
	420	strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
	421	adap->owner = THIS_MODULE;
	422	adap->algo = &wmt_i2c_algo;
	423	adap->dev.parent = &pdev->dev;
	424	adap->dev.of_node = pdev->dev.of_node;
	425
	426	init_completion(&i2c_dev->complete);
	427
	428	err = wmt_i2c_reset_hardware(i2c_dev);
	429	if (err) {
	430	dev_err(&pdev->dev, "error initializing hardware\n");
	431	return err;
	432	}
	433
	434	err = i2c_add_adapter(adap);
ea734404	435	if (err)
560746eb	436	return err;
560746eb TP	437
	438	platform_set_drvdata(pdev, i2c_dev);
	439
560746eb TP	440	return 0;
	441	}
	442
	443	static int wmt_i2c_remove(struct platform_device *pdev)
	444	{
	445	struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
	446
	447	/* Disable interrupts, clock and delete adapter */
	448	writew(0, i2c_dev->base + REG_IMR);
	449	clk_disable_unprepare(i2c_dev->clk);
	450	i2c_del_adapter(&i2c_dev->adapter);
	451
	452	return 0;
	453	}
	454
eae45e5d	455	static const struct of_device_id wmt_i2c_dt_ids[] = {
560746eb TP	456	{ .compatible = "wm,wm8505-i2c" },
	457	{ /* Sentinel */ },
	458	};
	459
	460	static struct platform_driver wmt_i2c_driver = {
	461	.probe = wmt_i2c_probe,
	462	.remove = wmt_i2c_remove,
	463	.driver = {
	464	.name = "wmt-i2c",
560746eb TP	465	.of_match_table = wmt_i2c_dt_ids,
	466	},
	467	};
	468
	469	module_platform_driver(wmt_i2c_driver);
	470
	471	MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
	472	MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
	473	MODULE_LICENSE("GPL");
	474	MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);