Commit | Line | Data |
---|---|---|
bd7fe5b7 | 1 | /* |
8ecbb3c3 LP |
2 | * 3-axis accelerometer driver supporting following Bosch-Sensortec chips: |
3 | * - BMC150 | |
4 | * - BMI055 | |
5 | * - BMA255 | |
6 | * - BMA250E | |
7 | * - BMA222E | |
8 | * - BMA280 | |
9 | * | |
bd7fe5b7 SP |
10 | * Copyright (c) 2014, Intel Corporation. |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms and conditions of the GNU General Public License, | |
14 | * version 2, as published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/acpi.h> | |
bd7fe5b7 SP |
28 | #include <linux/pm.h> |
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/iio/iio.h> | |
31 | #include <linux/iio/sysfs.h> | |
32 | #include <linux/iio/buffer.h> | |
33 | #include <linux/iio/events.h> | |
34 | #include <linux/iio/trigger.h> | |
35 | #include <linux/iio/trigger_consumer.h> | |
36 | #include <linux/iio/triggered_buffer.h> | |
4011eda6 | 37 | #include <linux/regmap.h> |
bd7fe5b7 | 38 | |
55637c38 MP |
39 | #include "bmc150-accel.h" |
40 | ||
bd7fe5b7 SP |
41 | #define BMC150_ACCEL_DRV_NAME "bmc150_accel" |
42 | #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event" | |
bd7fe5b7 SP |
43 | |
44 | #define BMC150_ACCEL_REG_CHIP_ID 0x00 | |
bd7fe5b7 SP |
45 | |
46 | #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B | |
47 | #define BMC150_ACCEL_ANY_MOTION_MASK 0x07 | |
8d5a9781 SP |
48 | #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0) |
49 | #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1) | |
50 | #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2) | |
bd7fe5b7 SP |
51 | #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3) |
52 | ||
53 | #define BMC150_ACCEL_REG_PMU_LPW 0x11 | |
54 | #define BMC150_ACCEL_PMU_MODE_MASK 0xE0 | |
55 | #define BMC150_ACCEL_PMU_MODE_SHIFT 5 | |
56 | #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17 | |
57 | #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1 | |
58 | ||
59 | #define BMC150_ACCEL_REG_PMU_RANGE 0x0F | |
60 | ||
61 | #define BMC150_ACCEL_DEF_RANGE_2G 0x03 | |
62 | #define BMC150_ACCEL_DEF_RANGE_4G 0x05 | |
63 | #define BMC150_ACCEL_DEF_RANGE_8G 0x08 | |
64 | #define BMC150_ACCEL_DEF_RANGE_16G 0x0C | |
65 | ||
66 | /* Default BW: 125Hz */ | |
67 | #define BMC150_ACCEL_REG_PMU_BW 0x10 | |
68 | #define BMC150_ACCEL_DEF_BW 125 | |
69 | ||
1c500840 OJ |
70 | #define BMC150_ACCEL_REG_RESET 0x14 |
71 | #define BMC150_ACCEL_RESET_VAL 0xB6 | |
72 | ||
bd7fe5b7 SP |
73 | #define BMC150_ACCEL_REG_INT_MAP_0 0x19 |
74 | #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) | |
75 | ||
76 | #define BMC150_ACCEL_REG_INT_MAP_1 0x1A | |
3bbec977 OP |
77 | #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) |
78 | #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1) | |
79 | #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2) | |
bd7fe5b7 SP |
80 | |
81 | #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 | |
82 | #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 | |
83 | #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F | |
84 | #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00 | |
85 | ||
86 | #define BMC150_ACCEL_REG_INT_EN_0 0x16 | |
87 | #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0) | |
88 | #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1) | |
89 | #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) | |
90 | ||
91 | #define BMC150_ACCEL_REG_INT_EN_1 0x17 | |
3bbec977 OP |
92 | #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) |
93 | #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5) | |
94 | #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6) | |
bd7fe5b7 SP |
95 | |
96 | #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 | |
97 | #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) | |
98 | ||
99 | #define BMC150_ACCEL_REG_INT_5 0x27 | |
100 | #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03 | |
101 | ||
102 | #define BMC150_ACCEL_REG_INT_6 0x28 | |
103 | #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF | |
104 | ||
105 | /* Slope duration in terms of number of samples */ | |
9e8e228f | 106 | #define BMC150_ACCEL_DEF_SLOPE_DURATION 1 |
bd7fe5b7 | 107 | /* in terms of multiples of g's/LSB, based on range */ |
9e8e228f | 108 | #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1 |
bd7fe5b7 SP |
109 | |
110 | #define BMC150_ACCEL_REG_XOUT_L 0x02 | |
111 | ||
112 | #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100 | |
113 | ||
114 | /* Sleep Duration values */ | |
115 | #define BMC150_ACCEL_SLEEP_500_MICRO 0x05 | |
116 | #define BMC150_ACCEL_SLEEP_1_MS 0x06 | |
117 | #define BMC150_ACCEL_SLEEP_2_MS 0x07 | |
118 | #define BMC150_ACCEL_SLEEP_4_MS 0x08 | |
119 | #define BMC150_ACCEL_SLEEP_6_MS 0x09 | |
120 | #define BMC150_ACCEL_SLEEP_10_MS 0x0A | |
121 | #define BMC150_ACCEL_SLEEP_25_MS 0x0B | |
122 | #define BMC150_ACCEL_SLEEP_50_MS 0x0C | |
123 | #define BMC150_ACCEL_SLEEP_100_MS 0x0D | |
124 | #define BMC150_ACCEL_SLEEP_500_MS 0x0E | |
125 | #define BMC150_ACCEL_SLEEP_1_SEC 0x0F | |
126 | ||
127 | #define BMC150_ACCEL_REG_TEMP 0x08 | |
128 | #define BMC150_ACCEL_TEMP_CENTER_VAL 24 | |
129 | ||
130 | #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) | |
131 | #define BMC150_AUTO_SUSPEND_DELAY_MS 2000 | |
132 | ||
3bbec977 OP |
133 | #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E |
134 | #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30 | |
135 | #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E | |
136 | #define BMC150_ACCEL_REG_FIFO_DATA 0x3F | |
137 | #define BMC150_ACCEL_FIFO_LENGTH 32 | |
138 | ||
bd7fe5b7 SP |
139 | enum bmc150_accel_axis { |
140 | AXIS_X, | |
141 | AXIS_Y, | |
142 | AXIS_Z, | |
23e758b3 | 143 | AXIS_MAX, |
bd7fe5b7 SP |
144 | }; |
145 | ||
146 | enum bmc150_power_modes { | |
147 | BMC150_ACCEL_SLEEP_MODE_NORMAL, | |
148 | BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, | |
149 | BMC150_ACCEL_SLEEP_MODE_LPM, | |
150 | BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04, | |
151 | }; | |
152 | ||
8ecbb3c3 LP |
153 | struct bmc150_scale_info { |
154 | int scale; | |
155 | u8 reg_range; | |
156 | }; | |
157 | ||
158 | struct bmc150_accel_chip_info { | |
0ad4bf37 | 159 | const char *name; |
8ecbb3c3 LP |
160 | u8 chip_id; |
161 | const struct iio_chan_spec *channels; | |
162 | int num_channels; | |
163 | const struct bmc150_scale_info scale_table[4]; | |
164 | }; | |
165 | ||
3e825ec9 OP |
166 | struct bmc150_accel_interrupt { |
167 | const struct bmc150_accel_interrupt_info *info; | |
168 | atomic_t users; | |
169 | }; | |
170 | ||
7d963215 OP |
171 | struct bmc150_accel_trigger { |
172 | struct bmc150_accel_data *data; | |
173 | struct iio_trigger *indio_trig; | |
174 | int (*setup)(struct bmc150_accel_trigger *t, bool state); | |
175 | int intr; | |
176 | bool enabled; | |
177 | }; | |
178 | ||
3e825ec9 OP |
179 | enum bmc150_accel_interrupt_id { |
180 | BMC150_ACCEL_INT_DATA_READY, | |
181 | BMC150_ACCEL_INT_ANY_MOTION, | |
182 | BMC150_ACCEL_INT_WATERMARK, | |
183 | BMC150_ACCEL_INTERRUPTS, | |
184 | }; | |
185 | ||
7d963215 OP |
186 | enum bmc150_accel_trigger_id { |
187 | BMC150_ACCEL_TRIGGER_DATA_READY, | |
188 | BMC150_ACCEL_TRIGGER_ANY_MOTION, | |
189 | BMC150_ACCEL_TRIGGERS, | |
190 | }; | |
191 | ||
bd7fe5b7 | 192 | struct bmc150_accel_data { |
4011eda6 | 193 | struct regmap *regmap; |
19c95d63 | 194 | int irq; |
3e825ec9 | 195 | struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS]; |
3e825ec9 | 196 | atomic_t active_intr; |
7d963215 | 197 | struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS]; |
bd7fe5b7 | 198 | struct mutex mutex; |
3bbec977 | 199 | u8 fifo_mode, watermark; |
bd7fe5b7 SP |
200 | s16 buffer[8]; |
201 | u8 bw_bits; | |
202 | u32 slope_dur; | |
203 | u32 slope_thres; | |
204 | u32 range; | |
205 | int ev_enable_state; | |
c16bff48 | 206 | int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ |
8ecbb3c3 | 207 | const struct bmc150_accel_chip_info *chip_info; |
bd7fe5b7 SP |
208 | }; |
209 | ||
210 | static const struct { | |
211 | int val; | |
212 | int val2; | |
213 | u8 bw_bits; | |
0ba8da96 SK |
214 | } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08}, |
215 | {31, 260000, 0x09}, | |
216 | {62, 500000, 0x0A}, | |
217 | {125, 0, 0x0B}, | |
218 | {250, 0, 0x0C}, | |
219 | {500, 0, 0x0D}, | |
220 | {1000, 0, 0x0E}, | |
221 | {2000, 0, 0x0F} }; | |
bd7fe5b7 SP |
222 | |
223 | static const struct { | |
224 | int bw_bits; | |
225 | int msec; | |
226 | } bmc150_accel_sample_upd_time[] = { {0x08, 64}, | |
227 | {0x09, 32}, | |
228 | {0x0A, 16}, | |
229 | {0x0B, 8}, | |
230 | {0x0C, 4}, | |
231 | {0x0D, 2}, | |
232 | {0x0E, 1}, | |
233 | {0x0F, 1} }; | |
234 | ||
bd7fe5b7 SP |
235 | static const struct { |
236 | int sleep_dur; | |
8ecbb3c3 | 237 | u8 reg_value; |
bd7fe5b7 SP |
238 | } bmc150_accel_sleep_value_table[] = { {0, 0}, |
239 | {500, BMC150_ACCEL_SLEEP_500_MICRO}, | |
240 | {1000, BMC150_ACCEL_SLEEP_1_MS}, | |
241 | {2000, BMC150_ACCEL_SLEEP_2_MS}, | |
242 | {4000, BMC150_ACCEL_SLEEP_4_MS}, | |
243 | {6000, BMC150_ACCEL_SLEEP_6_MS}, | |
244 | {10000, BMC150_ACCEL_SLEEP_10_MS}, | |
245 | {25000, BMC150_ACCEL_SLEEP_25_MS}, | |
246 | {50000, BMC150_ACCEL_SLEEP_50_MS}, | |
247 | {100000, BMC150_ACCEL_SLEEP_100_MS}, | |
248 | {500000, BMC150_ACCEL_SLEEP_500_MS}, | |
249 | {1000000, BMC150_ACCEL_SLEEP_1_SEC} }; | |
250 | ||
486294f1 | 251 | const struct regmap_config bmc150_regmap_conf = { |
4011eda6 MP |
252 | .reg_bits = 8, |
253 | .val_bits = 8, | |
254 | .max_register = 0x3f, | |
255 | }; | |
486294f1 | 256 | EXPORT_SYMBOL_GPL(bmc150_regmap_conf); |
4011eda6 | 257 | |
bd7fe5b7 SP |
258 | static int bmc150_accel_set_mode(struct bmc150_accel_data *data, |
259 | enum bmc150_power_modes mode, | |
260 | int dur_us) | |
261 | { | |
0ef4c311 | 262 | struct device *dev = regmap_get_device(data->regmap); |
bd7fe5b7 SP |
263 | int i; |
264 | int ret; | |
265 | u8 lpw_bits; | |
266 | int dur_val = -1; | |
267 | ||
268 | if (dur_us > 0) { | |
269 | for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table); | |
270 | ++i) { | |
271 | if (bmc150_accel_sleep_value_table[i].sleep_dur == | |
272 | dur_us) | |
273 | dur_val = | |
274 | bmc150_accel_sleep_value_table[i].reg_value; | |
275 | } | |
e20008ed | 276 | } else { |
bd7fe5b7 | 277 | dur_val = 0; |
e20008ed | 278 | } |
bd7fe5b7 SP |
279 | |
280 | if (dur_val < 0) | |
281 | return -EINVAL; | |
282 | ||
283 | lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT; | |
284 | lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT); | |
285 | ||
0ef4c311 | 286 | dev_dbg(dev, "Set Mode bits %x\n", lpw_bits); |
bd7fe5b7 | 287 | |
4011eda6 | 288 | ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits); |
bd7fe5b7 | 289 | if (ret < 0) { |
0ef4c311 | 290 | dev_err(dev, "Error writing reg_pmu_lpw\n"); |
bd7fe5b7 SP |
291 | return ret; |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
297 | static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, | |
298 | int val2) | |
299 | { | |
300 | int i; | |
301 | int ret; | |
302 | ||
303 | for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { | |
304 | if (bmc150_accel_samp_freq_table[i].val == val && | |
e20008ed | 305 | bmc150_accel_samp_freq_table[i].val2 == val2) { |
4011eda6 | 306 | ret = regmap_write(data->regmap, |
bd7fe5b7 SP |
307 | BMC150_ACCEL_REG_PMU_BW, |
308 | bmc150_accel_samp_freq_table[i].bw_bits); | |
309 | if (ret < 0) | |
310 | return ret; | |
311 | ||
312 | data->bw_bits = | |
313 | bmc150_accel_samp_freq_table[i].bw_bits; | |
314 | return 0; | |
315 | } | |
316 | } | |
317 | ||
318 | return -EINVAL; | |
319 | } | |
320 | ||
802a3aef OP |
321 | static int bmc150_accel_update_slope(struct bmc150_accel_data *data) |
322 | { | |
0ef4c311 | 323 | struct device *dev = regmap_get_device(data->regmap); |
4011eda6 | 324 | int ret; |
802a3aef | 325 | |
4011eda6 | 326 | ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6, |
802a3aef OP |
327 | data->slope_thres); |
328 | if (ret < 0) { | |
0ef4c311 | 329 | dev_err(dev, "Error writing reg_int_6\n"); |
802a3aef OP |
330 | return ret; |
331 | } | |
332 | ||
4011eda6 MP |
333 | ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5, |
334 | BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur); | |
802a3aef | 335 | if (ret < 0) { |
0ef4c311 | 336 | dev_err(dev, "Error updating reg_int_5\n"); |
802a3aef OP |
337 | return ret; |
338 | } | |
339 | ||
0ef4c311 | 340 | dev_dbg(dev, "%s: %x %x\n", __func__, data->slope_thres, |
802a3aef OP |
341 | data->slope_dur); |
342 | ||
343 | return ret; | |
344 | } | |
345 | ||
7d963215 OP |
346 | static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t, |
347 | bool state) | |
348 | { | |
349 | if (state) | |
350 | return bmc150_accel_update_slope(t->data); | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
bd7fe5b7 SP |
355 | static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val, |
356 | int *val2) | |
357 | { | |
358 | int i; | |
359 | ||
360 | for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { | |
361 | if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) { | |
362 | *val = bmc150_accel_samp_freq_table[i].val; | |
363 | *val2 = bmc150_accel_samp_freq_table[i].val2; | |
364 | return IIO_VAL_INT_PLUS_MICRO; | |
365 | } | |
366 | } | |
367 | ||
368 | return -EINVAL; | |
369 | } | |
370 | ||
6f0a13f2 | 371 | #ifdef CONFIG_PM |
bd7fe5b7 SP |
372 | static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data) |
373 | { | |
374 | int i; | |
375 | ||
376 | for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) { | |
377 | if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits) | |
378 | return bmc150_accel_sample_upd_time[i].msec; | |
379 | } | |
380 | ||
381 | return BMC150_ACCEL_MAX_STARTUP_TIME_MS; | |
382 | } | |
383 | ||
384 | static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) | |
385 | { | |
0ef4c311 | 386 | struct device *dev = regmap_get_device(data->regmap); |
bd7fe5b7 SP |
387 | int ret; |
388 | ||
e20008ed | 389 | if (on) { |
0ef4c311 | 390 | ret = pm_runtime_get_sync(dev); |
e20008ed | 391 | } else { |
0ef4c311 AS |
392 | pm_runtime_mark_last_busy(dev); |
393 | ret = pm_runtime_put_autosuspend(dev); | |
bd7fe5b7 | 394 | } |
e20008ed | 395 | |
bd7fe5b7 | 396 | if (ret < 0) { |
0ef4c311 | 397 | dev_err(dev, |
bd7fe5b7 | 398 | "Failed: bmc150_accel_set_power_state for %d\n", on); |
aaeecd80 | 399 | if (on) |
0ef4c311 | 400 | pm_runtime_put_noidle(dev); |
aaeecd80 | 401 | |
bd7fe5b7 SP |
402 | return ret; |
403 | } | |
404 | ||
405 | return 0; | |
406 | } | |
b31b05cf LP |
407 | #else |
408 | static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) | |
409 | { | |
410 | return 0; | |
411 | } | |
412 | #endif | |
bd7fe5b7 | 413 | |
8e22f477 OP |
414 | static const struct bmc150_accel_interrupt_info { |
415 | u8 map_reg; | |
416 | u8 map_bitmask; | |
417 | u8 en_reg; | |
418 | u8 en_bitmask; | |
3e825ec9 | 419 | } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = { |
8e22f477 OP |
420 | { /* data ready interrupt */ |
421 | .map_reg = BMC150_ACCEL_REG_INT_MAP_1, | |
422 | .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA, | |
423 | .en_reg = BMC150_ACCEL_REG_INT_EN_1, | |
424 | .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN, | |
425 | }, | |
426 | { /* motion interrupt */ | |
427 | .map_reg = BMC150_ACCEL_REG_INT_MAP_0, | |
428 | .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE, | |
429 | .en_reg = BMC150_ACCEL_REG_INT_EN_0, | |
430 | .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X | | |
431 | BMC150_ACCEL_INT_EN_BIT_SLP_Y | | |
432 | BMC150_ACCEL_INT_EN_BIT_SLP_Z | |
433 | }, | |
3bbec977 OP |
434 | { /* fifo watermark interrupt */ |
435 | .map_reg = BMC150_ACCEL_REG_INT_MAP_1, | |
436 | .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM, | |
437 | .en_reg = BMC150_ACCEL_REG_INT_EN_1, | |
438 | .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN, | |
439 | }, | |
8e22f477 OP |
440 | }; |
441 | ||
3e825ec9 OP |
442 | static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev, |
443 | struct bmc150_accel_data *data) | |
444 | { | |
445 | int i; | |
446 | ||
447 | for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++) | |
448 | data->interrupts[i].info = &bmc150_accel_interrupts[i]; | |
449 | } | |
450 | ||
451 | static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i, | |
8e22f477 OP |
452 | bool state) |
453 | { | |
0ef4c311 | 454 | struct device *dev = regmap_get_device(data->regmap); |
3e825ec9 OP |
455 | struct bmc150_accel_interrupt *intr = &data->interrupts[i]; |
456 | const struct bmc150_accel_interrupt_info *info = intr->info; | |
8e22f477 OP |
457 | int ret; |
458 | ||
3e825ec9 OP |
459 | if (state) { |
460 | if (atomic_inc_return(&intr->users) > 1) | |
461 | return 0; | |
462 | } else { | |
463 | if (atomic_dec_return(&intr->users) > 0) | |
464 | return 0; | |
465 | } | |
466 | ||
8e22f477 | 467 | /* |
e20008ed HK |
468 | * We will expect the enable and disable to do operation in reverse |
469 | * order. This will happen here anyway, as our resume operation uses | |
470 | * sync mode runtime pm calls. The suspend operation will be delayed | |
471 | * by autosuspend delay. | |
472 | * So the disable operation will still happen in reverse order of | |
473 | * enable operation. When runtime pm is disabled the mode is always on, | |
474 | * so sequence doesn't matter. | |
8e22f477 OP |
475 | */ |
476 | ret = bmc150_accel_set_power_state(data, state); | |
477 | if (ret < 0) | |
478 | return ret; | |
479 | ||
480 | /* map the interrupt to the appropriate pins */ | |
4011eda6 MP |
481 | ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask, |
482 | (state ? info->map_bitmask : 0)); | |
8e22f477 | 483 | if (ret < 0) { |
0ef4c311 | 484 | dev_err(dev, "Error updating reg_int_map\n"); |
8e22f477 OP |
485 | goto out_fix_power_state; |
486 | } | |
487 | ||
488 | /* enable/disable the interrupt */ | |
4011eda6 MP |
489 | ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask, |
490 | (state ? info->en_bitmask : 0)); | |
8e22f477 | 491 | if (ret < 0) { |
0ef4c311 | 492 | dev_err(dev, "Error updating reg_int_en\n"); |
8e22f477 OP |
493 | goto out_fix_power_state; |
494 | } | |
495 | ||
3e825ec9 OP |
496 | if (state) |
497 | atomic_inc(&data->active_intr); | |
498 | else | |
499 | atomic_dec(&data->active_intr); | |
500 | ||
8e22f477 OP |
501 | return 0; |
502 | ||
503 | out_fix_power_state: | |
504 | bmc150_accel_set_power_state(data, false); | |
505 | return ret; | |
506 | } | |
507 | ||
bd7fe5b7 SP |
508 | static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) |
509 | { | |
0ef4c311 | 510 | struct device *dev = regmap_get_device(data->regmap); |
bd7fe5b7 SP |
511 | int ret, i; |
512 | ||
8ecbb3c3 LP |
513 | for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) { |
514 | if (data->chip_info->scale_table[i].scale == val) { | |
4011eda6 | 515 | ret = regmap_write(data->regmap, |
8ecbb3c3 LP |
516 | BMC150_ACCEL_REG_PMU_RANGE, |
517 | data->chip_info->scale_table[i].reg_range); | |
bd7fe5b7 | 518 | if (ret < 0) { |
0ef4c311 | 519 | dev_err(dev, "Error writing pmu_range\n"); |
bd7fe5b7 SP |
520 | return ret; |
521 | } | |
522 | ||
8ecbb3c3 | 523 | data->range = data->chip_info->scale_table[i].reg_range; |
bd7fe5b7 SP |
524 | return 0; |
525 | } | |
526 | } | |
527 | ||
528 | return -EINVAL; | |
529 | } | |
530 | ||
531 | static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val) | |
532 | { | |
0ef4c311 | 533 | struct device *dev = regmap_get_device(data->regmap); |
bd7fe5b7 | 534 | int ret; |
4011eda6 | 535 | unsigned int value; |
bd7fe5b7 SP |
536 | |
537 | mutex_lock(&data->mutex); | |
538 | ||
4011eda6 | 539 | ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value); |
bd7fe5b7 | 540 | if (ret < 0) { |
0ef4c311 | 541 | dev_err(dev, "Error reading reg_temp\n"); |
bd7fe5b7 SP |
542 | mutex_unlock(&data->mutex); |
543 | return ret; | |
544 | } | |
4011eda6 | 545 | *val = sign_extend32(value, 7); |
bd7fe5b7 SP |
546 | |
547 | mutex_unlock(&data->mutex); | |
548 | ||
549 | return IIO_VAL_INT; | |
550 | } | |
551 | ||
8ecbb3c3 LP |
552 | static int bmc150_accel_get_axis(struct bmc150_accel_data *data, |
553 | struct iio_chan_spec const *chan, | |
bd7fe5b7 SP |
554 | int *val) |
555 | { | |
0ef4c311 | 556 | struct device *dev = regmap_get_device(data->regmap); |
bd7fe5b7 | 557 | int ret; |
8ecbb3c3 | 558 | int axis = chan->scan_index; |
2215f31d | 559 | __le16 raw_val; |
bd7fe5b7 SP |
560 | |
561 | mutex_lock(&data->mutex); | |
562 | ret = bmc150_accel_set_power_state(data, true); | |
563 | if (ret < 0) { | |
564 | mutex_unlock(&data->mutex); | |
565 | return ret; | |
566 | } | |
567 | ||
4011eda6 | 568 | ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis), |
2215f31d | 569 | &raw_val, sizeof(raw_val)); |
bd7fe5b7 | 570 | if (ret < 0) { |
0ef4c311 | 571 | dev_err(dev, "Error reading axis %d\n", axis); |
bd7fe5b7 SP |
572 | bmc150_accel_set_power_state(data, false); |
573 | mutex_unlock(&data->mutex); | |
574 | return ret; | |
575 | } | |
2215f31d | 576 | *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift, |
8ecbb3c3 | 577 | chan->scan_type.realbits - 1); |
bd7fe5b7 SP |
578 | ret = bmc150_accel_set_power_state(data, false); |
579 | mutex_unlock(&data->mutex); | |
580 | if (ret < 0) | |
581 | return ret; | |
582 | ||
583 | return IIO_VAL_INT; | |
584 | } | |
585 | ||
586 | static int bmc150_accel_read_raw(struct iio_dev *indio_dev, | |
587 | struct iio_chan_spec const *chan, | |
588 | int *val, int *val2, long mask) | |
589 | { | |
590 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
591 | int ret; | |
592 | ||
593 | switch (mask) { | |
594 | case IIO_CHAN_INFO_RAW: | |
595 | switch (chan->type) { | |
596 | case IIO_TEMP: | |
597 | return bmc150_accel_get_temp(data, val); | |
598 | case IIO_ACCEL: | |
599 | if (iio_buffer_enabled(indio_dev)) | |
600 | return -EBUSY; | |
601 | else | |
8ecbb3c3 | 602 | return bmc150_accel_get_axis(data, chan, val); |
bd7fe5b7 SP |
603 | default: |
604 | return -EINVAL; | |
605 | } | |
606 | case IIO_CHAN_INFO_OFFSET: | |
607 | if (chan->type == IIO_TEMP) { | |
608 | *val = BMC150_ACCEL_TEMP_CENTER_VAL; | |
609 | return IIO_VAL_INT; | |
e20008ed | 610 | } else { |
bd7fe5b7 | 611 | return -EINVAL; |
e20008ed | 612 | } |
bd7fe5b7 SP |
613 | case IIO_CHAN_INFO_SCALE: |
614 | *val = 0; | |
615 | switch (chan->type) { | |
616 | case IIO_TEMP: | |
617 | *val2 = 500000; | |
618 | return IIO_VAL_INT_PLUS_MICRO; | |
619 | case IIO_ACCEL: | |
620 | { | |
621 | int i; | |
8ecbb3c3 LP |
622 | const struct bmc150_scale_info *si; |
623 | int st_size = ARRAY_SIZE(data->chip_info->scale_table); | |
bd7fe5b7 | 624 | |
8ecbb3c3 LP |
625 | for (i = 0; i < st_size; ++i) { |
626 | si = &data->chip_info->scale_table[i]; | |
627 | if (si->reg_range == data->range) { | |
628 | *val2 = si->scale; | |
bd7fe5b7 SP |
629 | return IIO_VAL_INT_PLUS_MICRO; |
630 | } | |
631 | } | |
632 | return -EINVAL; | |
633 | } | |
634 | default: | |
635 | return -EINVAL; | |
636 | } | |
637 | case IIO_CHAN_INFO_SAMP_FREQ: | |
638 | mutex_lock(&data->mutex); | |
639 | ret = bmc150_accel_get_bw(data, val, val2); | |
640 | mutex_unlock(&data->mutex); | |
641 | return ret; | |
642 | default: | |
643 | return -EINVAL; | |
644 | } | |
645 | } | |
646 | ||
647 | static int bmc150_accel_write_raw(struct iio_dev *indio_dev, | |
648 | struct iio_chan_spec const *chan, | |
649 | int val, int val2, long mask) | |
650 | { | |
651 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
652 | int ret; | |
653 | ||
654 | switch (mask) { | |
655 | case IIO_CHAN_INFO_SAMP_FREQ: | |
656 | mutex_lock(&data->mutex); | |
657 | ret = bmc150_accel_set_bw(data, val, val2); | |
658 | mutex_unlock(&data->mutex); | |
659 | break; | |
660 | case IIO_CHAN_INFO_SCALE: | |
661 | if (val) | |
662 | return -EINVAL; | |
663 | ||
664 | mutex_lock(&data->mutex); | |
665 | ret = bmc150_accel_set_scale(data, val2); | |
666 | mutex_unlock(&data->mutex); | |
667 | return ret; | |
668 | default: | |
669 | ret = -EINVAL; | |
670 | } | |
671 | ||
672 | return ret; | |
673 | } | |
674 | ||
675 | static int bmc150_accel_read_event(struct iio_dev *indio_dev, | |
676 | const struct iio_chan_spec *chan, | |
677 | enum iio_event_type type, | |
678 | enum iio_event_direction dir, | |
679 | enum iio_event_info info, | |
680 | int *val, int *val2) | |
681 | { | |
682 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
683 | ||
684 | *val2 = 0; | |
685 | switch (info) { | |
686 | case IIO_EV_INFO_VALUE: | |
687 | *val = data->slope_thres; | |
688 | break; | |
689 | case IIO_EV_INFO_PERIOD: | |
802a3aef | 690 | *val = data->slope_dur; |
bd7fe5b7 SP |
691 | break; |
692 | default: | |
693 | return -EINVAL; | |
694 | } | |
695 | ||
696 | return IIO_VAL_INT; | |
697 | } | |
698 | ||
699 | static int bmc150_accel_write_event(struct iio_dev *indio_dev, | |
700 | const struct iio_chan_spec *chan, | |
701 | enum iio_event_type type, | |
702 | enum iio_event_direction dir, | |
703 | enum iio_event_info info, | |
704 | int val, int val2) | |
705 | { | |
706 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
707 | ||
708 | if (data->ev_enable_state) | |
709 | return -EBUSY; | |
710 | ||
711 | switch (info) { | |
712 | case IIO_EV_INFO_VALUE: | |
fdd15f65 | 713 | data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK; |
bd7fe5b7 SP |
714 | break; |
715 | case IIO_EV_INFO_PERIOD: | |
802a3aef | 716 | data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK; |
bd7fe5b7 SP |
717 | break; |
718 | default: | |
719 | return -EINVAL; | |
720 | } | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
725 | static int bmc150_accel_read_event_config(struct iio_dev *indio_dev, | |
726 | const struct iio_chan_spec *chan, | |
727 | enum iio_event_type type, | |
728 | enum iio_event_direction dir) | |
729 | { | |
bd7fe5b7 SP |
730 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
731 | ||
732 | return data->ev_enable_state; | |
733 | } | |
734 | ||
735 | static int bmc150_accel_write_event_config(struct iio_dev *indio_dev, | |
736 | const struct iio_chan_spec *chan, | |
737 | enum iio_event_type type, | |
738 | enum iio_event_direction dir, | |
739 | int state) | |
740 | { | |
741 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
742 | int ret; | |
743 | ||
14ee64f4 | 744 | if (state == data->ev_enable_state) |
bd7fe5b7 SP |
745 | return 0; |
746 | ||
747 | mutex_lock(&data->mutex); | |
748 | ||
3e825ec9 OP |
749 | ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION, |
750 | state); | |
bd7fe5b7 SP |
751 | if (ret < 0) { |
752 | mutex_unlock(&data->mutex); | |
753 | return ret; | |
754 | } | |
755 | ||
756 | data->ev_enable_state = state; | |
757 | mutex_unlock(&data->mutex); | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
762 | static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, | |
e20008ed | 763 | struct iio_trigger *trig) |
bd7fe5b7 SP |
764 | { |
765 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
7d963215 | 766 | int i; |
bd7fe5b7 | 767 | |
7d963215 OP |
768 | for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { |
769 | if (data->triggers[i].indio_trig == trig) | |
770 | return 0; | |
771 | } | |
bd7fe5b7 | 772 | |
7d963215 | 773 | return -EINVAL; |
bd7fe5b7 SP |
774 | } |
775 | ||
3bbec977 OP |
776 | static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev, |
777 | struct device_attribute *attr, | |
778 | char *buf) | |
779 | { | |
780 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | |
781 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
782 | int wm; | |
783 | ||
784 | mutex_lock(&data->mutex); | |
785 | wm = data->watermark; | |
786 | mutex_unlock(&data->mutex); | |
787 | ||
788 | return sprintf(buf, "%d\n", wm); | |
789 | } | |
790 | ||
791 | static ssize_t bmc150_accel_get_fifo_state(struct device *dev, | |
792 | struct device_attribute *attr, | |
793 | char *buf) | |
794 | { | |
795 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | |
796 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
797 | bool state; | |
798 | ||
799 | mutex_lock(&data->mutex); | |
800 | state = data->fifo_mode; | |
801 | mutex_unlock(&data->mutex); | |
802 | ||
803 | return sprintf(buf, "%d\n", state); | |
804 | } | |
805 | ||
806 | static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); | |
807 | static IIO_CONST_ATTR(hwfifo_watermark_max, | |
808 | __stringify(BMC150_ACCEL_FIFO_LENGTH)); | |
809 | static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO, | |
810 | bmc150_accel_get_fifo_state, NULL, 0); | |
811 | static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO, | |
812 | bmc150_accel_get_fifo_watermark, NULL, 0); | |
813 | ||
814 | static const struct attribute *bmc150_accel_fifo_attributes[] = { | |
815 | &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, | |
816 | &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, | |
817 | &iio_dev_attr_hwfifo_watermark.dev_attr.attr, | |
818 | &iio_dev_attr_hwfifo_enabled.dev_attr.attr, | |
819 | NULL, | |
820 | }; | |
821 | ||
822 | static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val) | |
823 | { | |
824 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
825 | ||
826 | if (val > BMC150_ACCEL_FIFO_LENGTH) | |
827 | val = BMC150_ACCEL_FIFO_LENGTH; | |
828 | ||
829 | mutex_lock(&data->mutex); | |
830 | data->watermark = val; | |
831 | mutex_unlock(&data->mutex); | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
836 | /* | |
837 | * We must read at least one full frame in one burst, otherwise the rest of the | |
838 | * frame data is discarded. | |
839 | */ | |
4011eda6 | 840 | static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data, |
3bbec977 OP |
841 | char *buffer, int samples) |
842 | { | |
0ef4c311 | 843 | struct device *dev = regmap_get_device(data->regmap); |
3bbec977 | 844 | int sample_length = 3 * 2; |
4011eda6 MP |
845 | int ret; |
846 | int total_length = samples * sample_length; | |
847 | int i; | |
848 | size_t step = regmap_get_raw_read_max(data->regmap); | |
3bbec977 | 849 | |
4011eda6 MP |
850 | if (!step || step > total_length) |
851 | step = total_length; | |
852 | else if (step < total_length) | |
853 | step = sample_length; | |
3bbec977 | 854 | |
4011eda6 MP |
855 | /* |
856 | * Seems we have a bus with size limitation so we have to execute | |
857 | * multiple reads | |
858 | */ | |
859 | for (i = 0; i < total_length; i += step) { | |
860 | ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA, | |
861 | &buffer[i], step); | |
862 | if (ret) | |
863 | break; | |
3bbec977 OP |
864 | } |
865 | ||
866 | if (ret) | |
0ef4c311 AS |
867 | dev_err(dev, |
868 | "Error transferring data from fifo in single steps of %zu\n", | |
4011eda6 | 869 | step); |
3bbec977 OP |
870 | |
871 | return ret; | |
872 | } | |
873 | ||
874 | static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev, | |
875 | unsigned samples, bool irq) | |
876 | { | |
877 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
0ef4c311 | 878 | struct device *dev = regmap_get_device(data->regmap); |
3bbec977 OP |
879 | int ret, i; |
880 | u8 count; | |
881 | u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3]; | |
882 | int64_t tstamp; | |
883 | uint64_t sample_period; | |
4011eda6 | 884 | unsigned int val; |
e20008ed | 885 | |
4011eda6 | 886 | ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val); |
3bbec977 | 887 | if (ret < 0) { |
0ef4c311 | 888 | dev_err(dev, "Error reading reg_fifo_status\n"); |
3bbec977 OP |
889 | return ret; |
890 | } | |
891 | ||
4011eda6 | 892 | count = val & 0x7F; |
3bbec977 OP |
893 | |
894 | if (!count) | |
895 | return 0; | |
896 | ||
897 | /* | |
898 | * If we getting called from IRQ handler we know the stored timestamp is | |
899 | * fairly accurate for the last stored sample. Otherwise, if we are | |
900 | * called as a result of a read operation from userspace and hence | |
901 | * before the watermark interrupt was triggered, take a timestamp | |
902 | * now. We can fall anywhere in between two samples so the error in this | |
903 | * case is at most one sample period. | |
904 | */ | |
905 | if (!irq) { | |
906 | data->old_timestamp = data->timestamp; | |
bc2b7dab | 907 | data->timestamp = iio_get_time_ns(indio_dev); |
3bbec977 OP |
908 | } |
909 | ||
910 | /* | |
911 | * Approximate timestamps for each of the sample based on the sampling | |
912 | * frequency, timestamp for last sample and number of samples. | |
913 | * | |
914 | * Note that we can't use the current bandwidth settings to compute the | |
915 | * sample period because the sample rate varies with the device | |
916 | * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That | |
917 | * small variation adds when we store a large number of samples and | |
918 | * creates significant jitter between the last and first samples in | |
919 | * different batches (e.g. 32ms vs 21ms). | |
920 | * | |
921 | * To avoid this issue we compute the actual sample period ourselves | |
922 | * based on the timestamp delta between the last two flush operations. | |
923 | */ | |
924 | sample_period = (data->timestamp - data->old_timestamp); | |
925 | do_div(sample_period, count); | |
926 | tstamp = data->timestamp - (count - 1) * sample_period; | |
927 | ||
928 | if (samples && count > samples) | |
929 | count = samples; | |
930 | ||
4011eda6 | 931 | ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count); |
3bbec977 OP |
932 | if (ret) |
933 | return ret; | |
934 | ||
935 | /* | |
936 | * Ideally we want the IIO core to handle the demux when running in fifo | |
937 | * mode but not when running in triggered buffer mode. Unfortunately | |
938 | * this does not seem to be possible, so stick with driver demux for | |
939 | * now. | |
940 | */ | |
941 | for (i = 0; i < count; i++) { | |
942 | u16 sample[8]; | |
943 | int j, bit; | |
944 | ||
945 | j = 0; | |
946 | for_each_set_bit(bit, indio_dev->active_scan_mask, | |
947 | indio_dev->masklength) | |
948 | memcpy(&sample[j++], &buffer[i * 3 + bit], 2); | |
949 | ||
950 | iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp); | |
951 | ||
952 | tstamp += sample_period; | |
953 | } | |
954 | ||
955 | return count; | |
956 | } | |
957 | ||
958 | static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples) | |
959 | { | |
960 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
961 | int ret; | |
962 | ||
963 | mutex_lock(&data->mutex); | |
964 | ret = __bmc150_accel_fifo_flush(indio_dev, samples, false); | |
965 | mutex_unlock(&data->mutex); | |
966 | ||
967 | return ret; | |
968 | } | |
969 | ||
bd7fe5b7 | 970 | static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( |
0ba8da96 | 971 | "15.620000 31.260000 62.50000 125 250 500 1000 2000"); |
bd7fe5b7 SP |
972 | |
973 | static struct attribute *bmc150_accel_attributes[] = { | |
974 | &iio_const_attr_sampling_frequency_available.dev_attr.attr, | |
975 | NULL, | |
976 | }; | |
977 | ||
978 | static const struct attribute_group bmc150_accel_attrs_group = { | |
979 | .attrs = bmc150_accel_attributes, | |
980 | }; | |
981 | ||
982 | static const struct iio_event_spec bmc150_accel_event = { | |
983 | .type = IIO_EV_TYPE_ROC, | |
1174124c | 984 | .dir = IIO_EV_DIR_EITHER, |
bd7fe5b7 SP |
985 | .mask_separate = BIT(IIO_EV_INFO_VALUE) | |
986 | BIT(IIO_EV_INFO_ENABLE) | | |
987 | BIT(IIO_EV_INFO_PERIOD) | |
988 | }; | |
989 | ||
8ecbb3c3 | 990 | #define BMC150_ACCEL_CHANNEL(_axis, bits) { \ |
bd7fe5b7 SP |
991 | .type = IIO_ACCEL, \ |
992 | .modified = 1, \ | |
993 | .channel2 = IIO_MOD_##_axis, \ | |
994 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
995 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ | |
996 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ | |
997 | .scan_index = AXIS_##_axis, \ | |
998 | .scan_type = { \ | |
999 | .sign = 's', \ | |
8ecbb3c3 | 1000 | .realbits = (bits), \ |
bd7fe5b7 | 1001 | .storagebits = 16, \ |
8ecbb3c3 | 1002 | .shift = 16 - (bits), \ |
1715e0cc | 1003 | .endianness = IIO_LE, \ |
bd7fe5b7 SP |
1004 | }, \ |
1005 | .event_spec = &bmc150_accel_event, \ | |
1006 | .num_event_specs = 1 \ | |
1007 | } | |
1008 | ||
8ecbb3c3 LP |
1009 | #define BMC150_ACCEL_CHANNELS(bits) { \ |
1010 | { \ | |
1011 | .type = IIO_TEMP, \ | |
1012 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ | |
1013 | BIT(IIO_CHAN_INFO_SCALE) | \ | |
1014 | BIT(IIO_CHAN_INFO_OFFSET), \ | |
1015 | .scan_index = -1, \ | |
1016 | }, \ | |
1017 | BMC150_ACCEL_CHANNEL(X, bits), \ | |
1018 | BMC150_ACCEL_CHANNEL(Y, bits), \ | |
1019 | BMC150_ACCEL_CHANNEL(Z, bits), \ | |
1020 | IIO_CHAN_SOFT_TIMESTAMP(3), \ | |
1021 | } | |
1022 | ||
1023 | static const struct iio_chan_spec bma222e_accel_channels[] = | |
1024 | BMC150_ACCEL_CHANNELS(8); | |
1025 | static const struct iio_chan_spec bma250e_accel_channels[] = | |
1026 | BMC150_ACCEL_CHANNELS(10); | |
1027 | static const struct iio_chan_spec bmc150_accel_channels[] = | |
1028 | BMC150_ACCEL_CHANNELS(12); | |
1029 | static const struct iio_chan_spec bma280_accel_channels[] = | |
1030 | BMC150_ACCEL_CHANNELS(14); | |
1031 | ||
8ecbb3c3 LP |
1032 | static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = { |
1033 | [bmc150] = { | |
0ad4bf37 | 1034 | .name = "BMC150A", |
8ecbb3c3 LP |
1035 | .chip_id = 0xFA, |
1036 | .channels = bmc150_accel_channels, | |
1037 | .num_channels = ARRAY_SIZE(bmc150_accel_channels), | |
1038 | .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, | |
1039 | {19122, BMC150_ACCEL_DEF_RANGE_4G}, | |
1040 | {38344, BMC150_ACCEL_DEF_RANGE_8G}, | |
1041 | {76590, BMC150_ACCEL_DEF_RANGE_16G} }, | |
1042 | }, | |
1043 | [bmi055] = { | |
0ad4bf37 | 1044 | .name = "BMI055A", |
8ecbb3c3 LP |
1045 | .chip_id = 0xFA, |
1046 | .channels = bmc150_accel_channels, | |
1047 | .num_channels = ARRAY_SIZE(bmc150_accel_channels), | |
1048 | .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, | |
1049 | {19122, BMC150_ACCEL_DEF_RANGE_4G}, | |
1050 | {38344, BMC150_ACCEL_DEF_RANGE_8G}, | |
1051 | {76590, BMC150_ACCEL_DEF_RANGE_16G} }, | |
1052 | }, | |
1053 | [bma255] = { | |
0ad4bf37 | 1054 | .name = "BMA0255", |
8ecbb3c3 LP |
1055 | .chip_id = 0xFA, |
1056 | .channels = bmc150_accel_channels, | |
1057 | .num_channels = ARRAY_SIZE(bmc150_accel_channels), | |
1058 | .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, | |
1059 | {19122, BMC150_ACCEL_DEF_RANGE_4G}, | |
1060 | {38344, BMC150_ACCEL_DEF_RANGE_8G}, | |
1061 | {76590, BMC150_ACCEL_DEF_RANGE_16G} }, | |
1062 | }, | |
1063 | [bma250e] = { | |
0ad4bf37 | 1064 | .name = "BMA250E", |
8ecbb3c3 LP |
1065 | .chip_id = 0xF9, |
1066 | .channels = bma250e_accel_channels, | |
1067 | .num_channels = ARRAY_SIZE(bma250e_accel_channels), | |
1068 | .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G}, | |
1069 | {76590, BMC150_ACCEL_DEF_RANGE_4G}, | |
1070 | {153277, BMC150_ACCEL_DEF_RANGE_8G}, | |
1071 | {306457, BMC150_ACCEL_DEF_RANGE_16G} }, | |
1072 | }, | |
1073 | [bma222e] = { | |
0ad4bf37 | 1074 | .name = "BMA222E", |
8ecbb3c3 LP |
1075 | .chip_id = 0xF8, |
1076 | .channels = bma222e_accel_channels, | |
1077 | .num_channels = ARRAY_SIZE(bma222e_accel_channels), | |
1078 | .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G}, | |
1079 | {306457, BMC150_ACCEL_DEF_RANGE_4G}, | |
1080 | {612915, BMC150_ACCEL_DEF_RANGE_8G}, | |
1081 | {1225831, BMC150_ACCEL_DEF_RANGE_16G} }, | |
1082 | }, | |
1083 | [bma280] = { | |
0ad4bf37 | 1084 | .name = "BMA0280", |
8ecbb3c3 LP |
1085 | .chip_id = 0xFB, |
1086 | .channels = bma280_accel_channels, | |
1087 | .num_channels = ARRAY_SIZE(bma280_accel_channels), | |
1088 | .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G}, | |
1089 | {4785, BMC150_ACCEL_DEF_RANGE_4G}, | |
1090 | {9581, BMC150_ACCEL_DEF_RANGE_8G}, | |
1091 | {19152, BMC150_ACCEL_DEF_RANGE_16G} }, | |
bd7fe5b7 | 1092 | }, |
bd7fe5b7 SP |
1093 | }; |
1094 | ||
1095 | static const struct iio_info bmc150_accel_info = { | |
1096 | .attrs = &bmc150_accel_attrs_group, | |
1097 | .read_raw = bmc150_accel_read_raw, | |
1098 | .write_raw = bmc150_accel_write_raw, | |
1099 | .read_event_value = bmc150_accel_read_event, | |
1100 | .write_event_value = bmc150_accel_write_event, | |
1101 | .write_event_config = bmc150_accel_write_event_config, | |
1102 | .read_event_config = bmc150_accel_read_event_config, | |
bd7fe5b7 SP |
1103 | .driver_module = THIS_MODULE, |
1104 | }; | |
1105 | ||
3bbec977 OP |
1106 | static const struct iio_info bmc150_accel_info_fifo = { |
1107 | .attrs = &bmc150_accel_attrs_group, | |
1108 | .read_raw = bmc150_accel_read_raw, | |
1109 | .write_raw = bmc150_accel_write_raw, | |
1110 | .read_event_value = bmc150_accel_read_event, | |
1111 | .write_event_value = bmc150_accel_write_event, | |
1112 | .write_event_config = bmc150_accel_write_event_config, | |
1113 | .read_event_config = bmc150_accel_read_event_config, | |
1114 | .validate_trigger = bmc150_accel_validate_trigger, | |
1115 | .hwfifo_set_watermark = bmc150_accel_set_watermark, | |
1116 | .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, | |
1117 | .driver_module = THIS_MODULE, | |
1118 | }; | |
1119 | ||
23e758b3 IT |
1120 | static const unsigned long bmc150_accel_scan_masks[] = { |
1121 | BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), | |
1122 | 0}; | |
1123 | ||
bd7fe5b7 SP |
1124 | static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) |
1125 | { | |
1126 | struct iio_poll_func *pf = p; | |
1127 | struct iio_dev *indio_dev = pf->indio_dev; | |
1128 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1715e0cc | 1129 | int ret; |
bd7fe5b7 SP |
1130 | |
1131 | mutex_lock(&data->mutex); | |
1715e0cc IT |
1132 | ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L, |
1133 | data->buffer, AXIS_MAX * 2); | |
bd7fe5b7 | 1134 | mutex_unlock(&data->mutex); |
1715e0cc IT |
1135 | if (ret < 0) |
1136 | goto err_read; | |
bd7fe5b7 SP |
1137 | |
1138 | iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, | |
c16bff48 | 1139 | pf->timestamp); |
bd7fe5b7 SP |
1140 | err_read: |
1141 | iio_trigger_notify_done(indio_dev->trig); | |
1142 | ||
1143 | return IRQ_HANDLED; | |
1144 | } | |
1145 | ||
1146 | static int bmc150_accel_trig_try_reen(struct iio_trigger *trig) | |
1147 | { | |
7d963215 OP |
1148 | struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); |
1149 | struct bmc150_accel_data *data = t->data; | |
0ef4c311 | 1150 | struct device *dev = regmap_get_device(data->regmap); |
bd7fe5b7 SP |
1151 | int ret; |
1152 | ||
1153 | /* new data interrupts don't need ack */ | |
7d963215 | 1154 | if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY]) |
bd7fe5b7 SP |
1155 | return 0; |
1156 | ||
1157 | mutex_lock(&data->mutex); | |
1158 | /* clear any latched interrupt */ | |
4011eda6 MP |
1159 | ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, |
1160 | BMC150_ACCEL_INT_MODE_LATCH_INT | | |
1161 | BMC150_ACCEL_INT_MODE_LATCH_RESET); | |
bd7fe5b7 SP |
1162 | mutex_unlock(&data->mutex); |
1163 | if (ret < 0) { | |
0ef4c311 | 1164 | dev_err(dev, "Error writing reg_int_rst_latch\n"); |
bd7fe5b7 SP |
1165 | return ret; |
1166 | } | |
1167 | ||
1168 | return 0; | |
1169 | } | |
1170 | ||
7d963215 | 1171 | static int bmc150_accel_trigger_set_state(struct iio_trigger *trig, |
e20008ed | 1172 | bool state) |
bd7fe5b7 | 1173 | { |
7d963215 OP |
1174 | struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); |
1175 | struct bmc150_accel_data *data = t->data; | |
bd7fe5b7 SP |
1176 | int ret; |
1177 | ||
1178 | mutex_lock(&data->mutex); | |
1179 | ||
7d963215 OP |
1180 | if (t->enabled == state) { |
1181 | mutex_unlock(&data->mutex); | |
1182 | return 0; | |
1183 | } | |
1184 | ||
1185 | if (t->setup) { | |
1186 | ret = t->setup(t, state); | |
1187 | if (ret < 0) { | |
14ee64f4 | 1188 | mutex_unlock(&data->mutex); |
7d963215 | 1189 | return ret; |
14ee64f4 OP |
1190 | } |
1191 | } | |
1192 | ||
7d963215 | 1193 | ret = bmc150_accel_set_interrupt(data, t->intr, state); |
bd7fe5b7 SP |
1194 | if (ret < 0) { |
1195 | mutex_unlock(&data->mutex); | |
1196 | return ret; | |
1197 | } | |
7d963215 OP |
1198 | |
1199 | t->enabled = state; | |
bd7fe5b7 SP |
1200 | |
1201 | mutex_unlock(&data->mutex); | |
1202 | ||
1203 | return ret; | |
1204 | } | |
1205 | ||
1206 | static const struct iio_trigger_ops bmc150_accel_trigger_ops = { | |
7d963215 | 1207 | .set_trigger_state = bmc150_accel_trigger_set_state, |
bd7fe5b7 SP |
1208 | .try_reenable = bmc150_accel_trig_try_reen, |
1209 | .owner = THIS_MODULE, | |
1210 | }; | |
1211 | ||
3bbec977 | 1212 | static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) |
bd7fe5b7 | 1213 | { |
bd7fe5b7 | 1214 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
0ef4c311 | 1215 | struct device *dev = regmap_get_device(data->regmap); |
bd7fe5b7 | 1216 | int dir; |
3bbec977 | 1217 | int ret; |
4011eda6 | 1218 | unsigned int val; |
bd7fe5b7 | 1219 | |
4011eda6 | 1220 | ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val); |
bd7fe5b7 | 1221 | if (ret < 0) { |
0ef4c311 | 1222 | dev_err(dev, "Error reading reg_int_status_2\n"); |
3bbec977 | 1223 | return ret; |
bd7fe5b7 SP |
1224 | } |
1225 | ||
4011eda6 | 1226 | if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) |
bd7fe5b7 SP |
1227 | dir = IIO_EV_DIR_FALLING; |
1228 | else | |
1229 | dir = IIO_EV_DIR_RISING; | |
1230 | ||
4011eda6 | 1231 | if (val & BMC150_ACCEL_ANY_MOTION_BIT_X) |
e20008ed HK |
1232 | iio_push_event(indio_dev, |
1233 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | |
1234 | 0, | |
1235 | IIO_MOD_X, | |
1236 | IIO_EV_TYPE_ROC, | |
1237 | dir), | |
1238 | data->timestamp); | |
1239 | ||
4011eda6 | 1240 | if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y) |
e20008ed HK |
1241 | iio_push_event(indio_dev, |
1242 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | |
1243 | 0, | |
1244 | IIO_MOD_Y, | |
1245 | IIO_EV_TYPE_ROC, | |
1246 | dir), | |
1247 | data->timestamp); | |
1248 | ||
4011eda6 | 1249 | if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z) |
e20008ed HK |
1250 | iio_push_event(indio_dev, |
1251 | IIO_MOD_EVENT_CODE(IIO_ACCEL, | |
1252 | 0, | |
1253 | IIO_MOD_Z, | |
1254 | IIO_EV_TYPE_ROC, | |
1255 | dir), | |
1256 | data->timestamp); | |
1257 | ||
3bbec977 OP |
1258 | return ret; |
1259 | } | |
1260 | ||
1261 | static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private) | |
1262 | { | |
1263 | struct iio_dev *indio_dev = private; | |
1264 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
0ef4c311 | 1265 | struct device *dev = regmap_get_device(data->regmap); |
3bbec977 OP |
1266 | bool ack = false; |
1267 | int ret; | |
1268 | ||
1269 | mutex_lock(&data->mutex); | |
1270 | ||
1271 | if (data->fifo_mode) { | |
1272 | ret = __bmc150_accel_fifo_flush(indio_dev, | |
1273 | BMC150_ACCEL_FIFO_LENGTH, true); | |
1274 | if (ret > 0) | |
1275 | ack = true; | |
1276 | } | |
1277 | ||
1278 | if (data->ev_enable_state) { | |
1279 | ret = bmc150_accel_handle_roc_event(indio_dev); | |
1280 | if (ret > 0) | |
1281 | ack = true; | |
1282 | } | |
1283 | ||
1284 | if (ack) { | |
4011eda6 MP |
1285 | ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, |
1286 | BMC150_ACCEL_INT_MODE_LATCH_INT | | |
1287 | BMC150_ACCEL_INT_MODE_LATCH_RESET); | |
3bbec977 | 1288 | if (ret) |
0ef4c311 | 1289 | dev_err(dev, "Error writing reg_int_rst_latch\n"); |
e20008ed | 1290 | |
3bbec977 OP |
1291 | ret = IRQ_HANDLED; |
1292 | } else { | |
1293 | ret = IRQ_NONE; | |
1294 | } | |
bd7fe5b7 | 1295 | |
3bbec977 OP |
1296 | mutex_unlock(&data->mutex); |
1297 | ||
1298 | return ret; | |
bd7fe5b7 SP |
1299 | } |
1300 | ||
3bbec977 | 1301 | static irqreturn_t bmc150_accel_irq_handler(int irq, void *private) |
bd7fe5b7 SP |
1302 | { |
1303 | struct iio_dev *indio_dev = private; | |
1304 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
3bbec977 | 1305 | bool ack = false; |
7d963215 | 1306 | int i; |
bd7fe5b7 | 1307 | |
3bbec977 | 1308 | data->old_timestamp = data->timestamp; |
bc2b7dab | 1309 | data->timestamp = iio_get_time_ns(indio_dev); |
bd7fe5b7 | 1310 | |
7d963215 OP |
1311 | for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { |
1312 | if (data->triggers[i].enabled) { | |
1313 | iio_trigger_poll(data->triggers[i].indio_trig); | |
3bbec977 | 1314 | ack = true; |
7d963215 OP |
1315 | break; |
1316 | } | |
1317 | } | |
bd7fe5b7 | 1318 | |
3bbec977 | 1319 | if (data->ev_enable_state || data->fifo_mode) |
bd7fe5b7 | 1320 | return IRQ_WAKE_THREAD; |
3bbec977 OP |
1321 | |
1322 | if (ack) | |
bd7fe5b7 | 1323 | return IRQ_HANDLED; |
3bbec977 OP |
1324 | |
1325 | return IRQ_NONE; | |
bd7fe5b7 SP |
1326 | } |
1327 | ||
7d963215 OP |
1328 | static const struct { |
1329 | int intr; | |
1330 | const char *name; | |
1331 | int (*setup)(struct bmc150_accel_trigger *t, bool state); | |
1332 | } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = { | |
1333 | { | |
1334 | .intr = 0, | |
1335 | .name = "%s-dev%d", | |
1336 | }, | |
1337 | { | |
1338 | .intr = 1, | |
1339 | .name = "%s-any-motion-dev%d", | |
1340 | .setup = bmc150_accel_any_motion_setup, | |
1341 | }, | |
1342 | }; | |
1343 | ||
1344 | static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data, | |
1345 | int from) | |
1346 | { | |
1347 | int i; | |
1348 | ||
7a1d0d91 | 1349 | for (i = from; i >= 0; i--) { |
7d963215 OP |
1350 | if (data->triggers[i].indio_trig) { |
1351 | iio_trigger_unregister(data->triggers[i].indio_trig); | |
1352 | data->triggers[i].indio_trig = NULL; | |
1353 | } | |
1354 | } | |
1355 | } | |
1356 | ||
1357 | static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev, | |
1358 | struct bmc150_accel_data *data) | |
1359 | { | |
0ef4c311 | 1360 | struct device *dev = regmap_get_device(data->regmap); |
7d963215 OP |
1361 | int i, ret; |
1362 | ||
1363 | for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { | |
1364 | struct bmc150_accel_trigger *t = &data->triggers[i]; | |
1365 | ||
0ef4c311 AS |
1366 | t->indio_trig = devm_iio_trigger_alloc(dev, |
1367 | bmc150_accel_triggers[i].name, | |
7d963215 OP |
1368 | indio_dev->name, |
1369 | indio_dev->id); | |
1370 | if (!t->indio_trig) { | |
1371 | ret = -ENOMEM; | |
1372 | break; | |
1373 | } | |
1374 | ||
0ef4c311 | 1375 | t->indio_trig->dev.parent = dev; |
7d963215 OP |
1376 | t->indio_trig->ops = &bmc150_accel_trigger_ops; |
1377 | t->intr = bmc150_accel_triggers[i].intr; | |
1378 | t->data = data; | |
1379 | t->setup = bmc150_accel_triggers[i].setup; | |
1380 | iio_trigger_set_drvdata(t->indio_trig, t); | |
1381 | ||
1382 | ret = iio_trigger_register(t->indio_trig); | |
1383 | if (ret) | |
1384 | break; | |
1385 | } | |
1386 | ||
1387 | if (ret) | |
1388 | bmc150_accel_unregister_triggers(data, i - 1); | |
1389 | ||
1390 | return ret; | |
1391 | } | |
1392 | ||
3bbec977 OP |
1393 | #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80 |
1394 | #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40 | |
1395 | #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00 | |
1396 | ||
1397 | static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data) | |
1398 | { | |
0ef4c311 | 1399 | struct device *dev = regmap_get_device(data->regmap); |
3bbec977 OP |
1400 | u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1; |
1401 | int ret; | |
1402 | ||
4011eda6 | 1403 | ret = regmap_write(data->regmap, reg, data->fifo_mode); |
3bbec977 | 1404 | if (ret < 0) { |
0ef4c311 | 1405 | dev_err(dev, "Error writing reg_fifo_config1\n"); |
3bbec977 OP |
1406 | return ret; |
1407 | } | |
1408 | ||
1409 | if (!data->fifo_mode) | |
1410 | return 0; | |
1411 | ||
4011eda6 MP |
1412 | ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0, |
1413 | data->watermark); | |
3bbec977 | 1414 | if (ret < 0) |
0ef4c311 | 1415 | dev_err(dev, "Error writing reg_fifo_config0\n"); |
3bbec977 OP |
1416 | |
1417 | return ret; | |
1418 | } | |
1419 | ||
c16bff48 VD |
1420 | static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev) |
1421 | { | |
1422 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1423 | ||
1424 | return bmc150_accel_set_power_state(data, true); | |
1425 | } | |
1426 | ||
3bbec977 OP |
1427 | static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev) |
1428 | { | |
1429 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1430 | int ret = 0; | |
1431 | ||
1432 | if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) | |
1433 | return iio_triggered_buffer_postenable(indio_dev); | |
1434 | ||
1435 | mutex_lock(&data->mutex); | |
1436 | ||
1437 | if (!data->watermark) | |
1438 | goto out; | |
1439 | ||
1440 | ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, | |
1441 | true); | |
1442 | if (ret) | |
1443 | goto out; | |
1444 | ||
1445 | data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO; | |
1446 | ||
1447 | ret = bmc150_accel_fifo_set_mode(data); | |
1448 | if (ret) { | |
1449 | data->fifo_mode = 0; | |
1450 | bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, | |
1451 | false); | |
1452 | } | |
1453 | ||
1454 | out: | |
1455 | mutex_unlock(&data->mutex); | |
1456 | ||
1457 | return ret; | |
1458 | } | |
1459 | ||
1460 | static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev) | |
1461 | { | |
1462 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1463 | ||
1464 | if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) | |
1465 | return iio_triggered_buffer_predisable(indio_dev); | |
1466 | ||
1467 | mutex_lock(&data->mutex); | |
1468 | ||
1469 | if (!data->fifo_mode) | |
1470 | goto out; | |
1471 | ||
1472 | bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false); | |
1473 | __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false); | |
1474 | data->fifo_mode = 0; | |
1475 | bmc150_accel_fifo_set_mode(data); | |
1476 | ||
1477 | out: | |
1478 | mutex_unlock(&data->mutex); | |
1479 | ||
1480 | return 0; | |
1481 | } | |
1482 | ||
c16bff48 VD |
1483 | static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev) |
1484 | { | |
1485 | struct bmc150_accel_data *data = iio_priv(indio_dev); | |
1486 | ||
1487 | return bmc150_accel_set_power_state(data, false); | |
1488 | } | |
1489 | ||
3bbec977 | 1490 | static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = { |
c16bff48 | 1491 | .preenable = bmc150_accel_buffer_preenable, |
3bbec977 OP |
1492 | .postenable = bmc150_accel_buffer_postenable, |
1493 | .predisable = bmc150_accel_buffer_predisable, | |
c16bff48 | 1494 | .postdisable = bmc150_accel_buffer_postdisable, |
3bbec977 OP |
1495 | }; |
1496 | ||
c4eaab79 BN |
1497 | static int bmc150_accel_chip_init(struct bmc150_accel_data *data) |
1498 | { | |
0ef4c311 | 1499 | struct device *dev = regmap_get_device(data->regmap); |
0ad4bf37 | 1500 | int ret, i; |
4011eda6 | 1501 | unsigned int val; |
c4eaab79 | 1502 | |
1c500840 OJ |
1503 | /* |
1504 | * Reset chip to get it in a known good state. A delay of 1.8ms after | |
1505 | * reset is required according to the data sheets of supported chips. | |
1506 | */ | |
1507 | regmap_write(data->regmap, BMC150_ACCEL_REG_RESET, | |
1508 | BMC150_ACCEL_RESET_VAL); | |
1509 | usleep_range(1800, 2500); | |
1510 | ||
4011eda6 | 1511 | ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val); |
c4eaab79 | 1512 | if (ret < 0) { |
0ef4c311 | 1513 | dev_err(dev, "Error: Reading chip id\n"); |
c4eaab79 BN |
1514 | return ret; |
1515 | } | |
1516 | ||
0ef4c311 | 1517 | dev_dbg(dev, "Chip Id %x\n", val); |
0ad4bf37 | 1518 | for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) { |
4011eda6 | 1519 | if (bmc150_accel_chip_info_tbl[i].chip_id == val) { |
0ad4bf37 BN |
1520 | data->chip_info = &bmc150_accel_chip_info_tbl[i]; |
1521 | break; | |
1522 | } | |
1523 | } | |
1524 | ||
1525 | if (!data->chip_info) { | |
0ef4c311 | 1526 | dev_err(dev, "Invalid chip %x\n", val); |
c4eaab79 BN |
1527 | return -ENODEV; |
1528 | } | |
1529 | ||
1530 | ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); | |
1531 | if (ret < 0) | |
1532 | return ret; | |
1533 | ||
1534 | /* Set Bandwidth */ | |
1535 | ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0); | |
1536 | if (ret < 0) | |
1537 | return ret; | |
1538 | ||
1539 | /* Set Default Range */ | |
4011eda6 MP |
1540 | ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE, |
1541 | BMC150_ACCEL_DEF_RANGE_4G); | |
c4eaab79 | 1542 | if (ret < 0) { |
0ef4c311 | 1543 | dev_err(dev, "Error writing reg_pmu_range\n"); |
c4eaab79 BN |
1544 | return ret; |
1545 | } | |
1546 | ||
1547 | data->range = BMC150_ACCEL_DEF_RANGE_4G; | |
1548 | ||
1549 | /* Set default slope duration and thresholds */ | |
1550 | data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD; | |
1551 | data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION; | |
1552 | ret = bmc150_accel_update_slope(data); | |
1553 | if (ret < 0) | |
1554 | return ret; | |
1555 | ||
1556 | /* Set default as latched interrupts */ | |
4011eda6 MP |
1557 | ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, |
1558 | BMC150_ACCEL_INT_MODE_LATCH_INT | | |
1559 | BMC150_ACCEL_INT_MODE_LATCH_RESET); | |
c4eaab79 | 1560 | if (ret < 0) { |
0ef4c311 | 1561 | dev_err(dev, "Error writing reg_int_rst_latch\n"); |
c4eaab79 BN |
1562 | return ret; |
1563 | } | |
1564 | ||
1565 | return 0; | |
1566 | } | |
1567 | ||
55637c38 MP |
1568 | int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq, |
1569 | const char *name, bool block_supported) | |
bd7fe5b7 SP |
1570 | { |
1571 | struct bmc150_accel_data *data; | |
1572 | struct iio_dev *indio_dev; | |
1573 | int ret; | |
1574 | ||
55637c38 | 1575 | indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); |
bd7fe5b7 SP |
1576 | if (!indio_dev) |
1577 | return -ENOMEM; | |
1578 | ||
1579 | data = iio_priv(indio_dev); | |
55637c38 | 1580 | dev_set_drvdata(dev, indio_dev); |
55637c38 | 1581 | data->irq = irq; |
bd7fe5b7 | 1582 | |
55637c38 | 1583 | data->regmap = regmap; |
8ecbb3c3 | 1584 | |
bd7fe5b7 SP |
1585 | ret = bmc150_accel_chip_init(data); |
1586 | if (ret < 0) | |
1587 | return ret; | |
1588 | ||
1589 | mutex_init(&data->mutex); | |
1590 | ||
19c95d63 | 1591 | indio_dev->dev.parent = dev; |
8ecbb3c3 LP |
1592 | indio_dev->channels = data->chip_info->channels; |
1593 | indio_dev->num_channels = data->chip_info->num_channels; | |
0ad4bf37 | 1594 | indio_dev->name = name ? name : data->chip_info->name; |
23e758b3 | 1595 | indio_dev->available_scan_masks = bmc150_accel_scan_masks; |
bd7fe5b7 SP |
1596 | indio_dev->modes = INDIO_DIRECT_MODE; |
1597 | indio_dev->info = &bmc150_accel_info; | |
1598 | ||
c16bff48 VD |
1599 | ret = iio_triggered_buffer_setup(indio_dev, |
1600 | &iio_pollfunc_store_time, | |
1601 | bmc150_accel_trigger_handler, | |
1602 | &bmc150_accel_buffer_ops); | |
1603 | if (ret < 0) { | |
0ef4c311 | 1604 | dev_err(dev, "Failed: iio triggered buffer setup\n"); |
c16bff48 VD |
1605 | return ret; |
1606 | } | |
1607 | ||
19c95d63 | 1608 | if (data->irq > 0) { |
bd7fe5b7 | 1609 | ret = devm_request_threaded_irq( |
0ef4c311 | 1610 | dev, data->irq, |
3bbec977 OP |
1611 | bmc150_accel_irq_handler, |
1612 | bmc150_accel_irq_thread_handler, | |
bd7fe5b7 SP |
1613 | IRQF_TRIGGER_RISING, |
1614 | BMC150_ACCEL_IRQ_NAME, | |
1615 | indio_dev); | |
1616 | if (ret) | |
c16bff48 | 1617 | goto err_buffer_cleanup; |
bd7fe5b7 | 1618 | |
8e22f477 OP |
1619 | /* |
1620 | * Set latched mode interrupt. While certain interrupts are | |
1621 | * non-latched regardless of this settings (e.g. new data) we | |
1622 | * want to use latch mode when we can to prevent interrupt | |
1623 | * flooding. | |
1624 | */ | |
4011eda6 MP |
1625 | ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, |
1626 | BMC150_ACCEL_INT_MODE_LATCH_RESET); | |
8e22f477 | 1627 | if (ret < 0) { |
0ef4c311 | 1628 | dev_err(dev, "Error writing reg_int_rst_latch\n"); |
c16bff48 | 1629 | goto err_buffer_cleanup; |
8e22f477 OP |
1630 | } |
1631 | ||
3e825ec9 OP |
1632 | bmc150_accel_interrupts_setup(indio_dev, data); |
1633 | ||
7d963215 | 1634 | ret = bmc150_accel_triggers_setup(indio_dev, data); |
bd7fe5b7 | 1635 | if (ret) |
c16bff48 | 1636 | goto err_buffer_cleanup; |
3bbec977 | 1637 | |
55637c38 | 1638 | if (block_supported) { |
3bbec977 OP |
1639 | indio_dev->modes |= INDIO_BUFFER_SOFTWARE; |
1640 | indio_dev->info = &bmc150_accel_info_fifo; | |
1641 | indio_dev->buffer->attrs = bmc150_accel_fifo_attributes; | |
1642 | } | |
bd7fe5b7 SP |
1643 | } |
1644 | ||
19c95d63 | 1645 | ret = pm_runtime_set_active(dev); |
bd7fe5b7 | 1646 | if (ret) |
7d0ead5c | 1647 | goto err_trigger_unregister; |
bd7fe5b7 | 1648 | |
19c95d63 MP |
1649 | pm_runtime_enable(dev); |
1650 | pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS); | |
1651 | pm_runtime_use_autosuspend(dev); | |
bd7fe5b7 | 1652 | |
7d0ead5c AR |
1653 | ret = iio_device_register(indio_dev); |
1654 | if (ret < 0) { | |
1655 | dev_err(dev, "Unable to register iio device\n"); | |
1656 | goto err_trigger_unregister; | |
1657 | } | |
1658 | ||
bd7fe5b7 SP |
1659 | return 0; |
1660 | ||
bd7fe5b7 | 1661 | err_trigger_unregister: |
7d963215 | 1662 | bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); |
c16bff48 VD |
1663 | err_buffer_cleanup: |
1664 | iio_triggered_buffer_cleanup(indio_dev); | |
bd7fe5b7 SP |
1665 | |
1666 | return ret; | |
1667 | } | |
55637c38 | 1668 | EXPORT_SYMBOL_GPL(bmc150_accel_core_probe); |
bd7fe5b7 | 1669 | |
55637c38 | 1670 | int bmc150_accel_core_remove(struct device *dev) |
bd7fe5b7 | 1671 | { |
55637c38 | 1672 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
bd7fe5b7 SP |
1673 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
1674 | ||
7d0ead5c AR |
1675 | iio_device_unregister(indio_dev); |
1676 | ||
0ef4c311 AS |
1677 | pm_runtime_disable(dev); |
1678 | pm_runtime_set_suspended(dev); | |
1679 | pm_runtime_put_noidle(dev); | |
bd7fe5b7 | 1680 | |
7d963215 | 1681 | bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); |
bd7fe5b7 | 1682 | |
c16bff48 VD |
1683 | iio_triggered_buffer_cleanup(indio_dev); |
1684 | ||
bd7fe5b7 SP |
1685 | mutex_lock(&data->mutex); |
1686 | bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0); | |
1687 | mutex_unlock(&data->mutex); | |
1688 | ||
1689 | return 0; | |
1690 | } | |
55637c38 | 1691 | EXPORT_SYMBOL_GPL(bmc150_accel_core_remove); |
bd7fe5b7 SP |
1692 | |
1693 | #ifdef CONFIG_PM_SLEEP | |
1694 | static int bmc150_accel_suspend(struct device *dev) | |
1695 | { | |
19c95d63 | 1696 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
bd7fe5b7 SP |
1697 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
1698 | ||
1699 | mutex_lock(&data->mutex); | |
1700 | bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); | |
1701 | mutex_unlock(&data->mutex); | |
1702 | ||
1703 | return 0; | |
1704 | } | |
1705 | ||
1706 | static int bmc150_accel_resume(struct device *dev) | |
1707 | { | |
19c95d63 | 1708 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
bd7fe5b7 SP |
1709 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
1710 | ||
1711 | mutex_lock(&data->mutex); | |
3e825ec9 | 1712 | if (atomic_read(&data->active_intr)) |
bd7fe5b7 | 1713 | bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); |
3bbec977 | 1714 | bmc150_accel_fifo_set_mode(data); |
bd7fe5b7 SP |
1715 | mutex_unlock(&data->mutex); |
1716 | ||
1717 | return 0; | |
1718 | } | |
1719 | #endif | |
1720 | ||
6f0a13f2 | 1721 | #ifdef CONFIG_PM |
bd7fe5b7 SP |
1722 | static int bmc150_accel_runtime_suspend(struct device *dev) |
1723 | { | |
19c95d63 | 1724 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
bd7fe5b7 | 1725 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
aaeecd80 | 1726 | int ret; |
bd7fe5b7 | 1727 | |
0ef4c311 | 1728 | dev_dbg(dev, __func__); |
aaeecd80 SP |
1729 | ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); |
1730 | if (ret < 0) | |
1731 | return -EAGAIN; | |
bd7fe5b7 | 1732 | |
aaeecd80 | 1733 | return 0; |
bd7fe5b7 SP |
1734 | } |
1735 | ||
1736 | static int bmc150_accel_runtime_resume(struct device *dev) | |
1737 | { | |
19c95d63 | 1738 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
bd7fe5b7 SP |
1739 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
1740 | int ret; | |
1741 | int sleep_val; | |
1742 | ||
0ef4c311 | 1743 | dev_dbg(dev, __func__); |
bd7fe5b7 SP |
1744 | |
1745 | ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); | |
3bbec977 OP |
1746 | if (ret < 0) |
1747 | return ret; | |
1748 | ret = bmc150_accel_fifo_set_mode(data); | |
bd7fe5b7 SP |
1749 | if (ret < 0) |
1750 | return ret; | |
1751 | ||
1752 | sleep_val = bmc150_accel_get_startup_times(data); | |
1753 | if (sleep_val < 20) | |
1754 | usleep_range(sleep_val * 1000, 20000); | |
1755 | else | |
1756 | msleep_interruptible(sleep_val); | |
1757 | ||
1758 | return 0; | |
1759 | } | |
1760 | #endif | |
1761 | ||
55637c38 | 1762 | const struct dev_pm_ops bmc150_accel_pm_ops = { |
bd7fe5b7 SP |
1763 | SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume) |
1764 | SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend, | |
1765 | bmc150_accel_runtime_resume, NULL) | |
1766 | }; | |
55637c38 | 1767 | EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops); |
bd7fe5b7 SP |
1768 | |
1769 | MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); | |
1770 | MODULE_LICENSE("GPL v2"); | |
1771 | MODULE_DESCRIPTION("BMC150 accelerometer driver"); |