[deliverable/linux.git] / drivers / iio / adc / ti-ads1015.c

/*
 * ADS1015 - Texas Instruments Analog-to-Digital Converter
 *
 * Copyright (c) 2016, Intel Corporation.
 *
 * This file is subject to the terms and conditions of version 2 of
 * the GNU General Public License.  See the file COPYING in the main
 * directory of this archive for more details.
 *
 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
 *	* 0x48 - ADDR connected to Ground
 *	* 0x49 - ADDR connected to Vdd
 *	* 0x4A - ADDR connected to SDA
 *	* 0x4B - ADDR connected to SCL
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/pm_runtime.h>
#include <linux/mutex.h>
#include <linux/delay.h>

#include <linux/i2c/ads1015.h>

#include <linux/iio/iio.h>
#include <linux/iio/types.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>

#define ADS1015_DRV_NAME "ads1015"

#define ADS1015_CONV_REG	0x00
#define ADS1015_CFG_REG		0x01

#define ADS1015_CFG_DR_SHIFT	5
#define ADS1015_CFG_MOD_SHIFT	8
#define ADS1015_CFG_PGA_SHIFT	9
#define ADS1015_CFG_MUX_SHIFT	12

#define ADS1015_CFG_DR_MASK	GENMASK(7, 5)
#define ADS1015_CFG_MOD_MASK	BIT(8)
#define ADS1015_CFG_PGA_MASK	GENMASK(11, 9)
#define ADS1015_CFG_MUX_MASK	GENMASK(14, 12)

/* device operating modes */
#define ADS1015_CONTINUOUS	0
#define ADS1015_SINGLESHOT	1

#define ADS1015_SLEEP_DELAY_MS		2000
#define ADS1015_DEFAULT_PGA		2
#define ADS1015_DEFAULT_DATA_RATE	4
#define ADS1015_DEFAULT_CHAN		0

enum {
	ADS1015,
	ADS1115,
};

enum ads1015_channels {
	ADS1015_AIN0_AIN1 = 0,
	ADS1015_AIN0_AIN3,
	ADS1015_AIN1_AIN3,
	ADS1015_AIN2_AIN3,
	ADS1015_AIN0,
	ADS1015_AIN1,
	ADS1015_AIN2,
	ADS1015_AIN3,
	ADS1015_TIMESTAMP,
};

static const unsigned int ads1015_data_rate[] = {
	128, 250, 490, 920, 1600, 2400, 3300, 3300
};

static const unsigned int ads1115_data_rate[] = {
	8, 16, 32, 64, 128, 250, 475, 860
};

static const struct {
	int scale;
	int uscale;
} ads1015_scale[] = {
	{3, 0},
	{2, 0},
	{1, 0},
	{0, 500000},
	{0, 250000},
	{0, 125000},
	{0, 125000},
	{0, 125000},
};

#define ADS1015_V_CHAN(_chan, _addr) {				\
	.type = IIO_VOLTAGE,					\
	.indexed = 1,						\
	.address = _addr,					\
	.channel = _chan,					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
				BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
	.scan_index = _addr,					\
	.scan_type = {						\
		.sign = 's',					\
		.realbits = 12,					\
		.storagebits = 16,				\
		.shift = 4,					\
		.endianness = IIO_CPU,				\
	},							\
	.datasheet_name = "AIN"#_chan,				\
}

#define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) {		\
	.type = IIO_VOLTAGE,					\
	.differential = 1,					\
	.indexed = 1,						\
	.address = _addr,					\
	.channel = _chan,					\
	.channel2 = _chan2,					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
				BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
	.scan_index = _addr,					\
	.scan_type = {						\
		.sign = 's',					\
		.realbits = 12,					\
		.storagebits = 16,				\
		.shift = 4,					\
		.endianness = IIO_CPU,				\
	},							\
	.datasheet_name = "AIN"#_chan"-AIN"#_chan2,		\
}

#define ADS1115_V_CHAN(_chan, _addr) {				\
	.type = IIO_VOLTAGE,					\
	.indexed = 1,						\
	.address = _addr,					\
	.channel = _chan,					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
				BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
	.scan_index = _addr,					\
	.scan_type = {						\
		.sign = 's',					\
		.realbits = 16,					\
		.storagebits = 16,				\
		.endianness = IIO_CPU,				\
	},							\
	.datasheet_name = "AIN"#_chan,				\
}

#define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) {		\
	.type = IIO_VOLTAGE,					\
	.differential = 1,					\
	.indexed = 1,						\
	.address = _addr,					\
	.channel = _chan,					\
	.channel2 = _chan2,					\
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
				BIT(IIO_CHAN_INFO_SCALE) |	\
				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
	.scan_index = _addr,					\
	.scan_type = {						\
		.sign = 's',					\
		.realbits = 16,					\
		.storagebits = 16,				\
		.endianness = IIO_CPU,				\
	},							\
	.datasheet_name = "AIN"#_chan"-AIN"#_chan2,		\
}

struct ads1015_data {
	struct regmap *regmap;
	/*
	 * Protects ADC ops, e.g: concurrent sysfs/buffered
	 * data reads, configuration updates
	 */
	struct mutex lock;
	struct ads1015_channel_data channel_data[ADS1015_CHANNELS];

	unsigned int *data_rate;
};

static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
{
	return (reg == ADS1015_CFG_REG);
}

static const struct regmap_config ads1015_regmap_config = {
	.reg_bits = 8,
	.val_bits = 16,
	.max_register = ADS1015_CFG_REG,
	.writeable_reg = ads1015_is_writeable_reg,
};

static const struct iio_chan_spec ads1015_channels[] = {
	ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
	ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
	ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
	ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
	ADS1015_V_CHAN(0, ADS1015_AIN0),
	ADS1015_V_CHAN(1, ADS1015_AIN1),
	ADS1015_V_CHAN(2, ADS1015_AIN2),
	ADS1015_V_CHAN(3, ADS1015_AIN3),
	IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
};

static const struct iio_chan_spec ads1115_channels[] = {
	ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
	ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
	ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
	ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
	ADS1115_V_CHAN(0, ADS1015_AIN0),
	ADS1115_V_CHAN(1, ADS1015_AIN1),
	ADS1115_V_CHAN(2, ADS1015_AIN2),
	ADS1115_V_CHAN(3, ADS1015_AIN3),
	IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
};

static int ads1015_set_power_state(struct ads1015_data *data, bool on)
{
	int ret;
	struct device *dev = regmap_get_device(data->regmap);

	if (on) {
		ret = pm_runtime_get_sync(dev);
		if (ret < 0)
			pm_runtime_put_noidle(dev);
	} else {
		pm_runtime_mark_last_busy(dev);
		ret = pm_runtime_put_autosuspend(dev);
	}

	return ret;
}

static
int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
{
	int ret, pga, dr, conv_time;
	bool change;

	if (chan < 0 || chan >= ADS1015_CHANNELS)
		return -EINVAL;

	pga = data->channel_data[chan].pga;
	dr = data->channel_data[chan].data_rate;

	ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG,
				       ADS1015_CFG_MUX_MASK |
				       ADS1015_CFG_PGA_MASK,
				       chan << ADS1015_CFG_MUX_SHIFT |
				       pga << ADS1015_CFG_PGA_SHIFT,
				       &change);
	if (ret < 0)
		return ret;

	if (change) {
		conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
		usleep_range(conv_time, conv_time + 1);
	}

	return regmap_read(data->regmap, ADS1015_CONV_REG, val);
}

static irqreturn_t ads1015_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct ads1015_data *data = iio_priv(indio_dev);
	s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding +  4x s16 timestamp */
	int chan, ret, res;

	memset(buf, 0, sizeof(buf));

	mutex_lock(&data->lock);
	chan = find_first_bit(indio_dev->active_scan_mask,
			      indio_dev->masklength);
	ret = ads1015_get_adc_result(data, chan, &res);
	if (ret < 0) {
		mutex_unlock(&data->lock);
		goto err;
	}

	buf[0] = res;
	mutex_unlock(&data->lock);

	iio_push_to_buffers_with_timestamp(indio_dev, buf,
					   iio_get_time_ns(indio_dev));

err:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static int ads1015_set_scale(struct ads1015_data *data, int chan,
			     int scale, int uscale)
{
	int i, ret, rindex = -1;

	for (i = 0; i < ARRAY_SIZE(ads1015_scale); i++)
		if (ads1015_scale[i].scale == scale &&
		    ads1015_scale[i].uscale == uscale) {
			rindex = i;
			break;
		}
	if (rindex < 0)
		return -EINVAL;

	ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
				 ADS1015_CFG_PGA_MASK,
				 rindex << ADS1015_CFG_PGA_SHIFT);
	if (ret < 0)
		return ret;

	data->channel_data[chan].pga = rindex;

	return 0;
}

static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
{
	int i, ret, rindex = -1;

	for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++)
		if (data->data_rate[i] == rate) {
			rindex = i;
			break;
		}
	if (rindex < 0)
		return -EINVAL;

	ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
				 ADS1015_CFG_DR_MASK,
				 rindex << ADS1015_CFG_DR_SHIFT);
	if (ret < 0)
		return ret;

	data->channel_data[chan].data_rate = rindex;

	return 0;
}

static int ads1015_read_raw(struct iio_dev *indio_dev,
			    struct iio_chan_spec const *chan, int *val,
			    int *val2, long mask)
{
	int ret, idx;
	struct ads1015_data *data = iio_priv(indio_dev);

	mutex_lock(&indio_dev->mlock);
	mutex_lock(&data->lock);
	switch (mask) {
	case IIO_CHAN_INFO_RAW: {
		int shift = chan->scan_type.shift;

		if (iio_buffer_enabled(indio_dev)) {
			ret = -EBUSY;
			break;
		}

		ret = ads1015_set_power_state(data, true);
		if (ret < 0)
			break;

		ret = ads1015_get_adc_result(data, chan->address, val);
		if (ret < 0) {
			ads1015_set_power_state(data, false);
			break;
		}

		*val = sign_extend32(*val >> shift, 15 - shift);

		ret = ads1015_set_power_state(data, false);
		if (ret < 0)
			break;

		ret = IIO_VAL_INT;
		break;
	}
	case IIO_CHAN_INFO_SCALE:
		idx = data->channel_data[chan->address].pga;
		*val = ads1015_scale[idx].scale;
		*val2 = ads1015_scale[idx].uscale;
		ret = IIO_VAL_INT_PLUS_MICRO;
		break;
	case IIO_CHAN_INFO_SAMP_FREQ:
		idx = data->channel_data[chan->address].data_rate;
		*val = data->data_rate[idx];
		ret = IIO_VAL_INT;
		break;
	default:
		ret = -EINVAL;
		break;
	}
	mutex_unlock(&data->lock);
	mutex_unlock(&indio_dev->mlock);

	return ret;
}

static int ads1015_write_raw(struct iio_dev *indio_dev,
			     struct iio_chan_spec const *chan, int val,
			     int val2, long mask)
{
	struct ads1015_data *data = iio_priv(indio_dev);
	int ret;

	mutex_lock(&data->lock);
	switch (mask) {
	case IIO_CHAN_INFO_SCALE:
		ret = ads1015_set_scale(data, chan->address, val, val2);
		break;
	case IIO_CHAN_INFO_SAMP_FREQ:
		ret = ads1015_set_data_rate(data, chan->address, val);
		break;
	default:
		ret = -EINVAL;
		break;
	}
	mutex_unlock(&data->lock);

	return ret;
}

static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
{
	return ads1015_set_power_state(iio_priv(indio_dev), true);
}

static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
{
	return ads1015_set_power_state(iio_priv(indio_dev), false);
}

static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
	.preenable	= ads1015_buffer_preenable,
	.postenable	= iio_triggered_buffer_postenable,
	.predisable	= iio_triggered_buffer_predisable,
	.postdisable	= ads1015_buffer_postdisable,
	.validate_scan_mask = &iio_validate_scan_mask_onehot,
};

static IIO_CONST_ATTR(scale_available, "3 2 1 0.5 0.25 0.125");

static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
	sampling_frequency_available, "128 250 490 920 1600 2400 3300");
static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
	sampling_frequency_available, "8 16 32 64 128 250 475 860");

static struct attribute *ads1015_attributes[] = {
	&iio_const_attr_scale_available.dev_attr.attr,
	&iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
	NULL,
};

static const struct attribute_group ads1015_attribute_group = {
	.attrs = ads1015_attributes,
};

static struct attribute *ads1115_attributes[] = {
	&iio_const_attr_scale_available.dev_attr.attr,
	&iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
	NULL,
};

static const struct attribute_group ads1115_attribute_group = {
	.attrs = ads1115_attributes,
};

static struct iio_info ads1015_info = {
	.driver_module	= THIS_MODULE,
	.read_raw	= ads1015_read_raw,
	.write_raw	= ads1015_write_raw,
	.attrs          = &ads1015_attribute_group,
};

static struct iio_info ads1115_info = {
	.driver_module	= THIS_MODULE,
	.read_raw	= ads1015_read_raw,
	.write_raw	= ads1015_write_raw,
	.attrs          = &ads1115_attribute_group,
};

#ifdef CONFIG_OF
static int ads1015_get_channels_config_of(struct i2c_client *client)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	struct ads1015_data *data = iio_priv(indio_dev);
	struct device_node *node;

	if (!client->dev.of_node ||
	    !of_get_next_child(client->dev.of_node, NULL))
		return -EINVAL;

	for_each_child_of_node(client->dev.of_node, node) {
		u32 pval;
		unsigned int channel;
		unsigned int pga = ADS1015_DEFAULT_PGA;
		unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;

		if (of_property_read_u32(node, "reg", &pval)) {
			dev_err(&client->dev, "invalid reg on %s\n",
				node->full_name);
			continue;
		}

		channel = pval;
		if (channel >= ADS1015_CHANNELS) {
			dev_err(&client->dev,
				"invalid channel index %d on %s\n",
				channel, node->full_name);
			continue;
		}

		if (!of_property_read_u32(node, "ti,gain", &pval)) {
			pga = pval;
			if (pga > 6) {
				dev_err(&client->dev, "invalid gain on %s\n",
					node->full_name);
				return -EINVAL;
			}
		}

		if (!of_property_read_u32(node, "ti,datarate", &pval)) {
			data_rate = pval;
			if (data_rate > 7) {
				dev_err(&client->dev,
					"invalid data_rate on %s\n",
					node->full_name);
				return -EINVAL;
			}
		}

		data->channel_data[channel].pga = pga;
		data->channel_data[channel].data_rate = data_rate;
	}

	return 0;
}
#endif

static void ads1015_get_channels_config(struct i2c_client *client)
{
	unsigned int k;

	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	struct ads1015_data *data = iio_priv(indio_dev);
	struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);

	/* prefer platform data */
	if (pdata) {
		memcpy(data->channel_data, pdata->channel_data,
		       sizeof(data->channel_data));
		return;
	}

#ifdef CONFIG_OF
	if (!ads1015_get_channels_config_of(client))
		return;
#endif
	/* fallback on default configuration */
	for (k = 0; k < ADS1015_CHANNELS; ++k) {
		data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
		data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
	}
}

static int ads1015_probe(struct i2c_client *client,
			 const struct i2c_device_id *id)
{
	struct iio_dev *indio_dev;
	struct ads1015_data *data;
	int ret;

	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
	if (!indio_dev)
		return -ENOMEM;

	data = iio_priv(indio_dev);
	i2c_set_clientdata(client, indio_dev);

	mutex_init(&data->lock);

	indio_dev->dev.parent = &client->dev;
	indio_dev->dev.of_node = client->dev.of_node;
	indio_dev->name = ADS1015_DRV_NAME;
	indio_dev->modes = INDIO_DIRECT_MODE;

	switch (id->driver_data) {
	case ADS1015:
		indio_dev->channels = ads1015_channels;
		indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
		indio_dev->info = &ads1015_info;
		data->data_rate = (unsigned int *) &ads1015_data_rate;
		break;
	case ADS1115:
		indio_dev->channels = ads1115_channels;
		indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
		indio_dev->info = &ads1115_info;
		data->data_rate = (unsigned int *) &ads1115_data_rate;
		break;
	}

	/* we need to keep this ABI the same as used by hwmon ADS1015 driver */
	ads1015_get_channels_config(client);

	data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
	if (IS_ERR(data->regmap)) {
		dev_err(&client->dev, "Failed to allocate register map\n");
		return PTR_ERR(data->regmap);
	}

	ret = iio_triggered_buffer_setup(indio_dev, NULL,
					 ads1015_trigger_handler,
					 &ads1015_buffer_setup_ops);
	if (ret < 0) {
		dev_err(&client->dev, "iio triggered buffer setup failed\n");
		return ret;
	}
	ret = pm_runtime_set_active(&client->dev);
	if (ret)
		goto err_buffer_cleanup;
	pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
	pm_runtime_use_autosuspend(&client->dev);
	pm_runtime_enable(&client->dev);

	ret = iio_device_register(indio_dev);
	if (ret < 0) {
		dev_err(&client->dev, "Failed to register IIO device\n");
		goto err_buffer_cleanup;
	}

	return 0;

err_buffer_cleanup:
	iio_triggered_buffer_cleanup(indio_dev);

	return ret;
}

static int ads1015_remove(struct i2c_client *client)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	struct ads1015_data *data = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);

	pm_runtime_disable(&client->dev);
	pm_runtime_set_suspended(&client->dev);
	pm_runtime_put_noidle(&client->dev);

	iio_triggered_buffer_cleanup(indio_dev);

	/* power down single shot mode */
	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
				  ADS1015_CFG_MOD_MASK,
				  ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
}

#ifdef CONFIG_PM
static int ads1015_runtime_suspend(struct device *dev)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
	struct ads1015_data *data = iio_priv(indio_dev);

	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
				  ADS1015_CFG_MOD_MASK,
				  ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
}

static int ads1015_runtime_resume(struct device *dev)
{
	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
	struct ads1015_data *data = iio_priv(indio_dev);

	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
				  ADS1015_CFG_MOD_MASK,
				  ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
}
#endif

static const struct dev_pm_ops ads1015_pm_ops = {
	SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
			   ads1015_runtime_resume, NULL)
};

static const struct i2c_device_id ads1015_id[] = {
	{"ads1015", ADS1015},
	{"ads1115", ADS1115},
	{}
};
MODULE_DEVICE_TABLE(i2c, ads1015_id);

static struct i2c_driver ads1015_driver = {
	.driver = {
		.name = ADS1015_DRV_NAME,
		.pm = &ads1015_pm_ops,
	},
	.probe		= ads1015_probe,
	.remove		= ads1015_remove,
	.id_table	= ads1015_id,
};

module_i2c_driver(ads1015_driver);

MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ecc24e72 DB	1	/*
	2	* ADS1015 - Texas Instruments Analog-to-Digital Converter
	3	*
	4	* Copyright (c) 2016, Intel Corporation.
	5	*
	6	* This file is subject to the terms and conditions of version 2 of
	7	* the GNU General Public License. See the file COPYING in the main
	8	* directory of this archive for more details.
	9	*
	10	* IIO driver for ADS1015 ADC 7-bit I2C slave address:
	11	* * 0x48 - ADDR connected to Ground
	12	* * 0x49 - ADDR connected to Vdd
	13	* * 0x4A - ADDR connected to SDA
	14	* * 0x4B - ADDR connected to SCL
	15	*/
	16
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/i2c.h>
	20	#include <linux/regmap.h>
	21	#include <linux/pm_runtime.h>
	22	#include <linux/mutex.h>
	23	#include <linux/delay.h>
	24
	25	#include <linux/i2c/ads1015.h>
	26
	27	#include <linux/iio/iio.h>
	28	#include <linux/iio/types.h>
	29	#include <linux/iio/sysfs.h>
	30	#include <linux/iio/buffer.h>
	31	#include <linux/iio/triggered_buffer.h>
	32	#include <linux/iio/trigger_consumer.h>
	33
	34	#define ADS1015_DRV_NAME "ads1015"
	35
	36	#define ADS1015_CONV_REG 0x00
	37	#define ADS1015_CFG_REG 0x01
	38
	39	#define ADS1015_CFG_DR_SHIFT 5
	40	#define ADS1015_CFG_MOD_SHIFT 8
	41	#define ADS1015_CFG_PGA_SHIFT 9
	42	#define ADS1015_CFG_MUX_SHIFT 12
	43
	44	#define ADS1015_CFG_DR_MASK GENMASK(7, 5)
	45	#define ADS1015_CFG_MOD_MASK BIT(8)
	46	#define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
	47	#define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
	48
	49	/* device operating modes */
	50	#define ADS1015_CONTINUOUS 0
	51	#define ADS1015_SINGLESHOT 1
	52
	53	#define ADS1015_SLEEP_DELAY_MS 2000
	54	#define ADS1015_DEFAULT_PGA 2
	55	#define ADS1015_DEFAULT_DATA_RATE 4
	56	#define ADS1015_DEFAULT_CHAN 0
	57
ba35f111 MR	58	enum {
	59	ADS1015,
	60	ADS1115,
	61	};
	62
ecc24e72 DB	63	enum ads1015_channels {
	64	ADS1015_AIN0_AIN1 = 0,
	65	ADS1015_AIN0_AIN3,
	66	ADS1015_AIN1_AIN3,
	67	ADS1015_AIN2_AIN3,
	68	ADS1015_AIN0,
	69	ADS1015_AIN1,
	70	ADS1015_AIN2,
	71	ADS1015_AIN3,
	72	ADS1015_TIMESTAMP,
	73	};
	74
	75	static const unsigned int ads1015_data_rate[] = {
	76	128, 250, 490, 920, 1600, 2400, 3300, 3300
	77	};
	78
ba35f111 MR	79	static const unsigned int ads1115_data_rate[] = {
	80	8, 16, 32, 64, 128, 250, 475, 860
	81	};
	82
ecc24e72 DB	83	static const struct {
	84	int scale;
	85	int uscale;
	86	} ads1015_scale[] = {
	87	{3, 0},
	88	{2, 0},
	89	{1, 0},
	90	{0, 500000},
	91	{0, 250000},
	92	{0, 125000},
	93	{0, 125000},
	94	{0, 125000},
	95	};
	96
	97	#define ADS1015_V_CHAN(_chan, _addr) { \
	98	.type = IIO_VOLTAGE, \
	99	.indexed = 1, \
	100	.address = _addr, \
	101	.channel = _chan, \
	102	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	103	BIT(IIO_CHAN_INFO_SCALE) \| \
	104	BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	105	.scan_index = _addr, \
	106	.scan_type = { \
	107	.sign = 's', \
	108	.realbits = 12, \
	109	.storagebits = 16, \
	110	.shift = 4, \
	111	.endianness = IIO_CPU, \
	112	}, \
8ac8aa61	113	.datasheet_name = "AIN"#_chan, \
ecc24e72 DB	114	}
	115
	116	#define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
	117	.type = IIO_VOLTAGE, \
	118	.differential = 1, \
	119	.indexed = 1, \
	120	.address = _addr, \
	121	.channel = _chan, \
	122	.channel2 = _chan2, \
	123	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	124	BIT(IIO_CHAN_INFO_SCALE) \| \
	125	BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	126	.scan_index = _addr, \
	127	.scan_type = { \
	128	.sign = 's', \
	129	.realbits = 12, \
	130	.storagebits = 16, \
	131	.shift = 4, \
	132	.endianness = IIO_CPU, \
	133	}, \
8ac8aa61	134	.datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
ecc24e72 DB	135	}
ecc24e72 DB	136
ba35f111 MR	137	#define ADS1115_V_CHAN(_chan, _addr) { \
	138	.type = IIO_VOLTAGE, \
	139	.indexed = 1, \
	140	.address = _addr, \
	141	.channel = _chan, \
	142	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	143	BIT(IIO_CHAN_INFO_SCALE) \| \
	144	BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	145	.scan_index = _addr, \
	146	.scan_type = { \
	147	.sign = 's', \
	148	.realbits = 16, \
	149	.storagebits = 16, \
	150	.endianness = IIO_CPU, \
	151	}, \
8ac8aa61	152	.datasheet_name = "AIN"#_chan, \
ba35f111 MR	153	}
	154
	155	#define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
	156	.type = IIO_VOLTAGE, \
	157	.differential = 1, \
	158	.indexed = 1, \
	159	.address = _addr, \
	160	.channel = _chan, \
	161	.channel2 = _chan2, \
	162	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	163	BIT(IIO_CHAN_INFO_SCALE) \| \
	164	BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	165	.scan_index = _addr, \
	166	.scan_type = { \
	167	.sign = 's', \
	168	.realbits = 16, \
	169	.storagebits = 16, \
	170	.endianness = IIO_CPU, \
	171	}, \
8ac8aa61	172	.datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
ba35f111 MR	173	}
ba35f111 MR	174
ecc24e72 DB	175	struct ads1015_data {
	176	struct regmap *regmap;
	177	/*
	178	* Protects ADC ops, e.g: concurrent sysfs/buffered
	179	* data reads, configuration updates
	180	*/
	181	struct mutex lock;
	182	struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
ba35f111 MR	183
ba35f111 MR	184	unsigned int *data_rate;
ecc24e72 DB	185	};
	186
	187	static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
	188	{
	189	return (reg == ADS1015_CFG_REG);
	190	}
	191
	192	static const struct regmap_config ads1015_regmap_config = {
	193	.reg_bits = 8,
	194	.val_bits = 16,
	195	.max_register = ADS1015_CFG_REG,
	196	.writeable_reg = ads1015_is_writeable_reg,
	197	};
	198
	199	static const struct iio_chan_spec ads1015_channels[] = {
	200	ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
	201	ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
	202	ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
	203	ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
	204	ADS1015_V_CHAN(0, ADS1015_AIN0),
	205	ADS1015_V_CHAN(1, ADS1015_AIN1),
	206	ADS1015_V_CHAN(2, ADS1015_AIN2),
	207	ADS1015_V_CHAN(3, ADS1015_AIN3),
	208	IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
	209	};
	210
ba35f111 MR	211	static const struct iio_chan_spec ads1115_channels[] = {
	212	ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
	213	ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
	214	ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
	215	ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
	216	ADS1115_V_CHAN(0, ADS1015_AIN0),
	217	ADS1115_V_CHAN(1, ADS1015_AIN1),
	218	ADS1115_V_CHAN(2, ADS1015_AIN2),
	219	ADS1115_V_CHAN(3, ADS1015_AIN3),
	220	IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
	221	};
	222
ecc24e72 DB	223	static int ads1015_set_power_state(struct ads1015_data *data, bool on)
	224	{
	225	int ret;
	226	struct device *dev = regmap_get_device(data->regmap);
	227
	228	if (on) {
	229	ret = pm_runtime_get_sync(dev);
	230	if (ret < 0)
	231	pm_runtime_put_noidle(dev);
	232	} else {
	233	pm_runtime_mark_last_busy(dev);
	234	ret = pm_runtime_put_autosuspend(dev);
	235	}
	236
	237	return ret;
	238	}
	239
	240	static
	241	int ads1015_get_adc_result(struct ads1015_data data, int chan, int val)
	242	{
	243	int ret, pga, dr, conv_time;
	244	bool change;
	245
	246	if (chan < 0 \|\| chan >= ADS1015_CHANNELS)
	247	return -EINVAL;
	248
	249	pga = data->channel_data[chan].pga;
	250	dr = data->channel_data[chan].data_rate;
	251
	252	ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG,
	253	ADS1015_CFG_MUX_MASK \|
	254	ADS1015_CFG_PGA_MASK,
	255	chan << ADS1015_CFG_MUX_SHIFT \|
	256	pga << ADS1015_CFG_PGA_SHIFT,
	257	&change);
	258	if (ret < 0)
	259	return ret;
	260
	261	if (change) {
ba35f111	262	conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
ecc24e72 DB	263	usleep_range(conv_time, conv_time + 1);
	264	}
	265
	266	return regmap_read(data->regmap, ADS1015_CONV_REG, val);
	267	}
	268
	269	static irqreturn_t ads1015_trigger_handler(int irq, void *p)
	270	{
	271	struct iio_poll_func *pf = p;
	272	struct iio_dev *indio_dev = pf->indio_dev;
	273	struct ads1015_data *data = iio_priv(indio_dev);
	274	s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */
	275	int chan, ret, res;
	276
	277	memset(buf, 0, sizeof(buf));
	278
	279	mutex_lock(&data->lock);
	280	chan = find_first_bit(indio_dev->active_scan_mask,
	281	indio_dev->masklength);
	282	ret = ads1015_get_adc_result(data, chan, &res);
	283	if (ret < 0) {
	284	mutex_unlock(&data->lock);
	285	goto err;
	286	}
	287
	288	buf[0] = res;
	289	mutex_unlock(&data->lock);
	290
bc2b7dab GB	291	iio_push_to_buffers_with_timestamp(indio_dev, buf,
bc2b7dab GB	292	iio_get_time_ns(indio_dev));
ecc24e72 DB	293
	294	err:
	295	iio_trigger_notify_done(indio_dev->trig);
	296
	297	return IRQ_HANDLED;
	298	}
	299
	300	static int ads1015_set_scale(struct ads1015_data *data, int chan,
	301	int scale, int uscale)
	302	{
	303	int i, ret, rindex = -1;
	304
	305	for (i = 0; i < ARRAY_SIZE(ads1015_scale); i++)
	306	if (ads1015_scale[i].scale == scale &&
	307	ads1015_scale[i].uscale == uscale) {
	308	rindex = i;
	309	break;
	310	}
	311	if (rindex < 0)
	312	return -EINVAL;
	313
	314	ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
	315	ADS1015_CFG_PGA_MASK,
	316	rindex << ADS1015_CFG_PGA_SHIFT);
	317	if (ret < 0)
	318	return ret;
	319
	320	data->channel_data[chan].pga = rindex;
	321
	322	return 0;
	323	}
	324
	325	static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
	326	{
	327	int i, ret, rindex = -1;
	328
	329	for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++)
ba35f111	330	if (data->data_rate[i] == rate) {
ecc24e72 DB	331	rindex = i;
	332	break;
	333	}
	334	if (rindex < 0)
	335	return -EINVAL;
	336
	337	ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
	338	ADS1015_CFG_DR_MASK,
	339	rindex << ADS1015_CFG_DR_SHIFT);
	340	if (ret < 0)
	341	return ret;
	342
	343	data->channel_data[chan].data_rate = rindex;
	344
	345	return 0;
	346	}
	347
	348	static int ads1015_read_raw(struct iio_dev *indio_dev,
	349	struct iio_chan_spec const chan, int val,
	350	int *val2, long mask)
	351	{
	352	int ret, idx;
	353	struct ads1015_data *data = iio_priv(indio_dev);
	354
	355	mutex_lock(&indio_dev->mlock);
	356	mutex_lock(&data->lock);
	357	switch (mask) {
ba35f111 MR	358	case IIO_CHAN_INFO_RAW: {
	359	int shift = chan->scan_type.shift;
	360
ecc24e72 DB	361	if (iio_buffer_enabled(indio_dev)) {
	362	ret = -EBUSY;
	363	break;
	364	}
	365
	366	ret = ads1015_set_power_state(data, true);
	367	if (ret < 0)
	368	break;
	369
	370	ret = ads1015_get_adc_result(data, chan->address, val);
	371	if (ret < 0) {
	372	ads1015_set_power_state(data, false);
	373	break;
	374	}
	375
ba35f111	376	val = sign_extend32(val >> shift, 15 - shift);
ecc24e72 DB	377
	378	ret = ads1015_set_power_state(data, false);
	379	if (ret < 0)
	380	break;
	381
	382	ret = IIO_VAL_INT;
	383	break;
ba35f111	384	}
ecc24e72 DB	385	case IIO_CHAN_INFO_SCALE:
	386	idx = data->channel_data[chan->address].pga;
	387	*val = ads1015_scale[idx].scale;
	388	*val2 = ads1015_scale[idx].uscale;
	389	ret = IIO_VAL_INT_PLUS_MICRO;
	390	break;
	391	case IIO_CHAN_INFO_SAMP_FREQ:
	392	idx = data->channel_data[chan->address].data_rate;
ba35f111	393	*val = data->data_rate[idx];
ecc24e72 DB	394	ret = IIO_VAL_INT;
	395	break;
	396	default:
	397	ret = -EINVAL;
	398	break;
	399	}
	400	mutex_unlock(&data->lock);
	401	mutex_unlock(&indio_dev->mlock);
	402
	403	return ret;
	404	}
	405
	406	static int ads1015_write_raw(struct iio_dev *indio_dev,
	407	struct iio_chan_spec const *chan, int val,
	408	int val2, long mask)
	409	{
	410	struct ads1015_data *data = iio_priv(indio_dev);
	411	int ret;
	412
	413	mutex_lock(&data->lock);
	414	switch (mask) {
	415	case IIO_CHAN_INFO_SCALE:
	416	ret = ads1015_set_scale(data, chan->address, val, val2);
	417	break;
	418	case IIO_CHAN_INFO_SAMP_FREQ:
	419	ret = ads1015_set_data_rate(data, chan->address, val);
	420	break;
	421	default:
	422	ret = -EINVAL;
	423	break;
	424	}
	425	mutex_unlock(&data->lock);
	426
	427	return ret;
	428	}
	429
	430	static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
	431	{
	432	return ads1015_set_power_state(iio_priv(indio_dev), true);
	433	}
	434
	435	static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
	436	{
	437	return ads1015_set_power_state(iio_priv(indio_dev), false);
	438	}
	439
	440	static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
	441	.preenable = ads1015_buffer_preenable,
	442	.postenable = iio_triggered_buffer_postenable,
	443	.predisable = iio_triggered_buffer_predisable,
	444	.postdisable = ads1015_buffer_postdisable,
	445	.validate_scan_mask = &iio_validate_scan_mask_onehot,
	446	};
	447
	448	static IIO_CONST_ATTR(scale_available, "3 2 1 0.5 0.25 0.125");
ba35f111 MR	449
	450	static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
	451	sampling_frequency_available, "128 250 490 920 1600 2400 3300");
	452	static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
	453	sampling_frequency_available, "8 16 32 64 128 250 475 860");
ecc24e72 DB	454
	455	static struct attribute *ads1015_attributes[] = {
	456	&iio_const_attr_scale_available.dev_attr.attr,
ba35f111	457	&iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
ecc24e72 DB	458	NULL,
	459	};
	460
	461	static const struct attribute_group ads1015_attribute_group = {
	462	.attrs = ads1015_attributes,
	463	};
	464
ba35f111 MR	465	static struct attribute *ads1115_attributes[] = {
	466	&iio_const_attr_scale_available.dev_attr.attr,
	467	&iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
	468	NULL,
	469	};
	470
	471	static const struct attribute_group ads1115_attribute_group = {
	472	.attrs = ads1115_attributes,
	473	};
	474
	475	static struct iio_info ads1015_info = {
	476	.driver_module = THIS_MODULE,
	477	.read_raw = ads1015_read_raw,
	478	.write_raw = ads1015_write_raw,
	479	.attrs = &ads1015_attribute_group,
	480	};
	481
	482	static struct iio_info ads1115_info = {
ecc24e72 DB	483	.driver_module = THIS_MODULE,
	484	.read_raw = ads1015_read_raw,
	485	.write_raw = ads1015_write_raw,
ba35f111	486	.attrs = &ads1115_attribute_group,
ecc24e72 DB	487	};
	488
	489	#ifdef CONFIG_OF
	490	static int ads1015_get_channels_config_of(struct i2c_client *client)
	491	{
522caebb GDM	492	struct iio_dev *indio_dev = i2c_get_clientdata(client);
522caebb GDM	493	struct ads1015_data *data = iio_priv(indio_dev);
ecc24e72 DB	494	struct device_node *node;
	495
	496	if (!client->dev.of_node \|\|
	497	!of_get_next_child(client->dev.of_node, NULL))
	498	return -EINVAL;
	499
	500	for_each_child_of_node(client->dev.of_node, node) {
	501	u32 pval;
	502	unsigned int channel;
	503	unsigned int pga = ADS1015_DEFAULT_PGA;
	504	unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
	505
	506	if (of_property_read_u32(node, "reg", &pval)) {
	507	dev_err(&client->dev, "invalid reg on %s\n",
	508	node->full_name);
	509	continue;
	510	}
	511
	512	channel = pval;
	513	if (channel >= ADS1015_CHANNELS) {
	514	dev_err(&client->dev,
	515	"invalid channel index %d on %s\n",
	516	channel, node->full_name);
	517	continue;
	518	}
	519
	520	if (!of_property_read_u32(node, "ti,gain", &pval)) {
	521	pga = pval;
	522	if (pga > 6) {
	523	dev_err(&client->dev, "invalid gain on %s\n",
	524	node->full_name);
	525	return -EINVAL;
	526	}
	527	}
	528
	529	if (!of_property_read_u32(node, "ti,datarate", &pval)) {
	530	data_rate = pval;
	531	if (data_rate > 7) {
	532	dev_err(&client->dev,
	533	"invalid data_rate on %s\n",
	534	node->full_name);
	535	return -EINVAL;
	536	}
	537	}
	538
	539	data->channel_data[channel].pga = pga;
	540	data->channel_data[channel].data_rate = data_rate;
	541	}
	542
	543	return 0;
	544	}
	545	#endif
	546
	547	static void ads1015_get_channels_config(struct i2c_client *client)
	548	{
	549	unsigned int k;
	550
	551	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	552	struct ads1015_data *data = iio_priv(indio_dev);
	553	struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
	554
	555	/* prefer platform data */
	556	if (pdata) {
	557	memcpy(data->channel_data, pdata->channel_data,
558	sizeof(data->channel_data));
559	return;
560	}
561
562	#ifdef CONFIG_OF
563	if (!ads1015_get_channels_config_of(client))
564	return;
565	#endif
566	/* fallback on default configuration */
567	for (k = 0; k < ADS1015_CHANNELS; ++k) {
568	data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
569	data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
570	}
571	}
572
573	static int ads1015_probe(struct i2c_client *client,
574	const struct i2c_device_id *id)
575	{
576	struct iio_dev *indio_dev;
577	struct ads1015_data *data;
578	int ret;
579
580	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
581	if (!indio_dev)
582	return -ENOMEM;
583
584	data = iio_priv(indio_dev);
585	i2c_set_clientdata(client, indio_dev);
586
587	mutex_init(&data->lock);
588
589	indio_dev->dev.parent = &client->dev;
f5241dbd	590	indio_dev->dev.of_node = client->dev.of_node;
ecc24e72	591	indio_dev->name = ADS1015_DRV_NAME;
ecc24e72 DB	592	indio_dev->modes = INDIO_DIRECT_MODE;
ecc24e72 DB	593
ba35f111 MR	594	switch (id->driver_data) {
	595	case ADS1015:
	596	indio_dev->channels = ads1015_channels;
	597	indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
	598	indio_dev->info = &ads1015_info;
	599	data->data_rate = (unsigned int *) &ads1015_data_rate;
	600	break;
	601	case ADS1115:
	602	indio_dev->channels = ads1115_channels;
	603	indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
	604	indio_dev->info = &ads1115_info;
	605	data->data_rate = (unsigned int *) &ads1115_data_rate;
	606	break;
	607	}
	608
ecc24e72 DB	609	/* we need to keep this ABI the same as used by hwmon ADS1015 driver */
	610	ads1015_get_channels_config(client);
	611
	612	data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
	613	if (IS_ERR(data->regmap)) {
	614	dev_err(&client->dev, "Failed to allocate register map\n");
	615	return PTR_ERR(data->regmap);
	616	}
	617
	618	ret = iio_triggered_buffer_setup(indio_dev, NULL,
	619	ads1015_trigger_handler,
	620	&ads1015_buffer_setup_ops);
	621	if (ret < 0) {
	622	dev_err(&client->dev, "iio triggered buffer setup failed\n");
	623	return ret;
	624	}
	625	ret = pm_runtime_set_active(&client->dev);
	626	if (ret)
	627	goto err_buffer_cleanup;
	628	pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
	629	pm_runtime_use_autosuspend(&client->dev);
	630	pm_runtime_enable(&client->dev);
	631
	632	ret = iio_device_register(indio_dev);
	633	if (ret < 0) {
	634	dev_err(&client->dev, "Failed to register IIO device\n");
	635	goto err_buffer_cleanup;
	636	}
	637
	638	return 0;
	639
	640	err_buffer_cleanup:
	641	iio_triggered_buffer_cleanup(indio_dev);
	642
	643	return ret;
	644	}
	645
	646	static int ads1015_remove(struct i2c_client *client)
	647	{
	648	struct iio_dev *indio_dev = i2c_get_clientdata(client);
	649	struct ads1015_data *data = iio_priv(indio_dev);
	650
	651	iio_device_unregister(indio_dev);
	652
	653	pm_runtime_disable(&client->dev);
	654	pm_runtime_set_suspended(&client->dev);
	655	pm_runtime_put_noidle(&client->dev);
	656
	657	iio_triggered_buffer_cleanup(indio_dev);
	658
	659	/* power down single shot mode */
	660	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
	661	ADS1015_CFG_MOD_MASK,
	662	ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
	663	}
	664
	665	#ifdef CONFIG_PM
	666	static int ads1015_runtime_suspend(struct device *dev)
	667	{
	668	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
	669	struct ads1015_data *data = iio_priv(indio_dev);
	670
	671	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
	672	ADS1015_CFG_MOD_MASK,
673	ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
674	}
675
676	static int ads1015_runtime_resume(struct device *dev)
677	{
678	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
679	struct ads1015_data *data = iio_priv(indio_dev);
680
681	return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
682	ADS1015_CFG_MOD_MASK,
683	ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
684	}
685	#endif
686
687	static const struct dev_pm_ops ads1015_pm_ops = {
688	SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
689	ads1015_runtime_resume, NULL)
690	};
691
692	static const struct i2c_device_id ads1015_id[] = {
ba35f111 MR	693	{"ads1015", ADS1015},
ba35f111 MR	694	{"ads1115", ADS1115},
ecc24e72 DB	695	{}
	696	};
	697	MODULE_DEVICE_TABLE(i2c, ads1015_id);
	698
	699	static struct i2c_driver ads1015_driver = {
	700	.driver = {
	701	.name = ADS1015_DRV_NAME,
	702	.pm = &ads1015_pm_ops,
	703	},
	704	.probe = ads1015_probe,
	705	.remove = ads1015_remove,
	706	.id_table = ads1015_id,
	707	};
	708
	709	module_i2c_driver(ads1015_driver);
	710
	711	MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
	712	MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
	713	MODULE_LICENSE("GPL v2");