projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'md/for-next'
[deliverable/linux.git] / drivers / infiniband / hw / i40iw / i40iw_hw.c
CommitLineData
4e9042e6
FL		 1/*******************************************************************************
2*
3* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
4*
5* This software is available to you under a choice of one of two
6* licenses. You may choose to be licensed under the terms of the GNU
7* General Public License (GPL) Version 2, available from the file
8* COPYING in the main directory of this source tree, or the
9* OpenFabrics.org BSD license below:
10*
11* Redistribution and use in source and binary forms, with or
12* without modification, are permitted provided that the following
13* conditions are met:
14*
15* - Redistributions of source code must retain the above
16* copyright notice, this list of conditions and the following
17* disclaimer.
18*
19* - Redistributions in binary form must reproduce the above
20* copyright notice, this list of conditions and the following
21* disclaimer in the documentation and/or other materials
22* provided with the distribution.
23*
24* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31* SOFTWARE.
32*
33*******************************************************************************/
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/ip.h>
40#include <linux/tcp.h>
41#include <linux/if_vlan.h>
42
43#include "i40iw.h"
44
45/**
46 * i40iw_initialize_hw_resources - initialize hw resource during open
47 * @iwdev: iwarp device
48 */
49u32 i40iw_initialize_hw_resources(struct i40iw_device *iwdev)
50{
51 unsigned long num_pds;
52 u32 resources_size;
53 u32 max_mr;
54 u32 max_qp;
55 u32 max_cq;
56 u32 arp_table_size;
57 u32 mrdrvbits;
58 void *resource_ptr;
59
60 max_qp = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt;
61 max_cq = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt;
62 max_mr = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt;
63 arp_table_size = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_ARP].cnt;
64 iwdev->max_cqe = 0xFFFFF;
65 num_pds = max_qp * 4;
66 resources_size = sizeof(struct i40iw_arp_entry) * arp_table_size;
67 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_qp);
68 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_mr);
69 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_cq);
70 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(num_pds);
71 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(arp_table_size);
72 resources_size += sizeof(struct i40iw_qp **) * max_qp;
73 iwdev->mem_resources = kzalloc(resources_size, GFP_KERNEL);
74
75 if (!iwdev->mem_resources)
76 return -ENOMEM;
77
78 iwdev->max_qp = max_qp;
79 iwdev->max_mr = max_mr;
80 iwdev->max_cq = max_cq;
81 iwdev->max_pd = num_pds;
82 iwdev->arp_table_size = arp_table_size;
83 iwdev->arp_table = (struct i40iw_arp_entry *)iwdev->mem_resources;
84 resource_ptr = iwdev->mem_resources + (sizeof(struct i40iw_arp_entry) * arp_table_size);
85
86 iwdev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY |
87 IB_DEVICE_MEM_WINDOW | IB_DEVICE_MEM_MGT_EXTENSIONS;
88
89 iwdev->allocated_qps = resource_ptr;
90 iwdev->allocated_cqs = &iwdev->allocated_qps[BITS_TO_LONGS(max_qp)];
91 iwdev->allocated_mrs = &iwdev->allocated_cqs[BITS_TO_LONGS(max_cq)];
92 iwdev->allocated_pds = &iwdev->allocated_mrs[BITS_TO_LONGS(max_mr)];
93 iwdev->allocated_arps = &iwdev->allocated_pds[BITS_TO_LONGS(num_pds)];
94 iwdev->qp_table = (struct i40iw_qp **)(&iwdev->allocated_arps[BITS_TO_LONGS(arp_table_size)]);
95 set_bit(0, iwdev->allocated_mrs);
96 set_bit(0, iwdev->allocated_qps);
97 set_bit(0, iwdev->allocated_cqs);
98 set_bit(0, iwdev->allocated_pds);
99 set_bit(0, iwdev->allocated_arps);
100
101 /* Following for ILQ/IEQ */
102 set_bit(1, iwdev->allocated_qps);
103 set_bit(1, iwdev->allocated_cqs);
104 set_bit(1, iwdev->allocated_pds);
105 set_bit(2, iwdev->allocated_cqs);
106 set_bit(2, iwdev->allocated_pds);
107
108 spin_lock_init(&iwdev->resource_lock);
996abf0a 109 spin_lock_init(&iwdev->qptable_lock);
8e9f04a7
CTT		 110 /* stag index mask has a minimum of 14 bits */
111 mrdrvbits = 24 - max(get_count_order(iwdev->max_mr), 14);
4e9042e6
FL		 112 iwdev->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits));
113 return 0;
114}
115
116/**
117 * i40iw_cqp_ce_handler - handle cqp completions
118 * @iwdev: iwarp device
119 * @arm: flag to arm after completions
120 * @cq: cq for cqp completions
121 */
122static void i40iw_cqp_ce_handler(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq, bool arm)
123{
124 struct i40iw_cqp_request *cqp_request;
125 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
126 u32 cqe_count = 0;
127 struct i40iw_ccq_cqe_info info;
128 int ret;
129
130 do {
131 memset(&info, 0, sizeof(info));
132 ret = dev->ccq_ops->ccq_get_cqe_info(cq, &info);
133 if (ret)
134 break;
135 cqp_request = (struct i40iw_cqp_request *)(unsigned long)info.scratch;
136 if (info.error)
137 i40iw_pr_err("opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n",
138 info.op_code, info.maj_err_code, info.min_err_code);
139 if (cqp_request) {
140 cqp_request->compl_info.maj_err_code = info.maj_err_code;
141 cqp_request->compl_info.min_err_code = info.min_err_code;
142 cqp_request->compl_info.op_ret_val = info.op_ret_val;
143 cqp_request->compl_info.error = info.error;
144
145 if (cqp_request->waiting) {
146 cqp_request->request_done = true;
147 wake_up(&cqp_request->waitq);
148 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
149 } else {
150 if (cqp_request->callback_fcn)
151 cqp_request->callback_fcn(cqp_request, 1);
152 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
153 }
154 }
155
156 cqe_count++;
157 } while (1);
158
159 if (arm && cqe_count) {
160 i40iw_process_bh(dev);
161 dev->ccq_ops->ccq_arm(cq);
162 }
163}
164
165/**
166 * i40iw_iwarp_ce_handler - handle iwarp completions
167 * @iwdev: iwarp device
168 * @iwcp: iwarp cq receiving event
169 */
170static void i40iw_iwarp_ce_handler(struct i40iw_device *iwdev,
171 struct i40iw_sc_cq *iwcq)
172{
173 struct i40iw_cq *i40iwcq = iwcq->back_cq;
174
175 if (i40iwcq->ibcq.comp_handler)
176 i40iwcq->ibcq.comp_handler(&i40iwcq->ibcq,
177 i40iwcq->ibcq.cq_context);
178}
179
180/**
181 * i40iw_puda_ce_handler - handle puda completion events
182 * @iwdev: iwarp device
183 * @cq: puda completion q for event
184 */
185static void i40iw_puda_ce_handler(struct i40iw_device *iwdev,
186 struct i40iw_sc_cq *cq)
187{
188 struct i40iw_sc_dev *dev = (struct i40iw_sc_dev *)&iwdev->sc_dev;
189 enum i40iw_status_code status;
190 u32 compl_error;
191
192 do {
193 status = i40iw_puda_poll_completion(dev, cq, &compl_error);
194 if (status == I40IW_ERR_QUEUE_EMPTY)
195 break;
196 if (status) {
197 i40iw_pr_err("puda status = %d\n", status);
198 break;
199 }
200 if (compl_error) {
201 i40iw_pr_err("puda compl_err =0x%x\n", compl_error);
202 break;
203 }
204 } while (1);
205
206 dev->ccq_ops->ccq_arm(cq);
207}
208
209/**
210 * i40iw_process_ceq - handle ceq for completions
211 * @iwdev: iwarp device
212 * @ceq: ceq having cq for completion
213 */
214void i40iw_process_ceq(struct i40iw_device *iwdev, struct i40iw_ceq *ceq)
215{
216 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
217 struct i40iw_sc_ceq *sc_ceq;
218 struct i40iw_sc_cq *cq;
219 bool arm = true;
220
221 sc_ceq = &ceq->sc_ceq;
222 do {
223 cq = dev->ceq_ops->process_ceq(dev, sc_ceq);
224 if (!cq)
225 break;
226
227 if (cq->cq_type == I40IW_CQ_TYPE_CQP)
228 i40iw_cqp_ce_handler(iwdev, cq, arm);
229 else if (cq->cq_type == I40IW_CQ_TYPE_IWARP)
230 i40iw_iwarp_ce_handler(iwdev, cq);
231 else if ((cq->cq_type == I40IW_CQ_TYPE_ILQ) ||
232 (cq->cq_type == I40IW_CQ_TYPE_IEQ))
233 i40iw_puda_ce_handler(iwdev, cq);
234 } while (1);
235}
236
237/**
238 * i40iw_next_iw_state - modify qp state
239 * @iwqp: iwarp qp to modify
240 * @state: next state for qp
241 * @del_hash: del hash
242 * @term: term message
243 * @termlen: length of term message
244 */
245void i40iw_next_iw_state(struct i40iw_qp *iwqp,
246 u8 state,
247 u8 del_hash,
248 u8 term,
249 u8 termlen)
250{
251 struct i40iw_modify_qp_info info;
252
253 memset(&info, 0, sizeof(info));
254 info.next_iwarp_state = state;
255 info.remove_hash_idx = del_hash;
256 info.cq_num_valid = true;
257 info.arp_cache_idx_valid = true;
258 info.dont_send_term = true;
259 info.dont_send_fin = true;
260 info.termlen = termlen;
261
262 if (term & I40IWQP_TERM_SEND_TERM_ONLY)
263 info.dont_send_term = false;
264 if (term & I40IWQP_TERM_SEND_FIN_ONLY)
265 info.dont_send_fin = false;
266 if (iwqp->sc_qp.term_flags && (state == I40IW_QP_STATE_ERROR))
267 info.reset_tcp_conn = true;
866e0f4d 268 iwqp->hw_iwarp_state = state;
4e9042e6
FL		 269 i40iw_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0);
270}
271
272/**
273 * i40iw_process_aeq - handle aeq events
274 * @iwdev: iwarp device
275 */
276void i40iw_process_aeq(struct i40iw_device *iwdev)
277{
278 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
279 struct i40iw_aeq *aeq = &iwdev->aeq;
280 struct i40iw_sc_aeq *sc_aeq = &aeq->sc_aeq;
281 struct i40iw_aeqe_info aeinfo;
282 struct i40iw_aeqe_info *info = &aeinfo;
283 int ret;
284 struct i40iw_qp *iwqp = NULL;
285 struct i40iw_sc_cq *cq = NULL;
286 struct i40iw_cq *iwcq = NULL;
287 struct i40iw_sc_qp *qp = NULL;
288 struct i40iw_qp_host_ctx_info *ctx_info = NULL;
289 unsigned long flags;
290
291 u32 aeqcnt = 0;
292
293 if (!sc_aeq->size)
294 return;
295
296 do {
297 memset(info, 0, sizeof(*info));
298 ret = dev->aeq_ops->get_next_aeqe(sc_aeq, info);
299 if (ret)
300 break;
301
302 aeqcnt++;
303 i40iw_debug(dev, I40IW_DEBUG_AEQ,
304 "%s ae_id = 0x%x bool qp=%d qp_id = %d\n",
305 __func__, info->ae_id, info->qp, info->qp_cq_id);
306 if (info->qp) {
996abf0a 307 spin_lock_irqsave(&iwdev->qptable_lock, flags);
4e9042e6
FL		 308 iwqp = iwdev->qp_table[info->qp_cq_id];
309 if (!iwqp) {
996abf0a 310 spin_unlock_irqrestore(&iwdev->qptable_lock, flags);
4e9042e6
FL		 311 i40iw_pr_err("qp_id %d is already freed\n", info->qp_cq_id);
312 continue;
313 }
996abf0a
IM		 314 i40iw_add_ref(&iwqp->ibqp);
315 spin_unlock_irqrestore(&iwdev->qptable_lock, flags);
4e9042e6
FL		 316 qp = &iwqp->sc_qp;
317 spin_lock_irqsave(&iwqp->lock, flags);
318 iwqp->hw_tcp_state = info->tcp_state;
319 iwqp->hw_iwarp_state = info->iwarp_state;
320 iwqp->last_aeq = info->ae_id;
321 spin_unlock_irqrestore(&iwqp->lock, flags);
322 ctx_info = &iwqp->ctx_info;
323 ctx_info->err_rq_idx_valid = true;
324 } else {
325 if (info->ae_id != I40IW_AE_CQ_OPERATION_ERROR)
326 continue;
327 }
328
329 switch (info->ae_id) {
330 case I40IW_AE_LLP_FIN_RECEIVED:
331 if (qp->term_flags)
332 continue;
333 if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
334 iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSE_WAIT;
335 if ((iwqp->hw_tcp_state == I40IW_TCP_STATE_CLOSE_WAIT) &&
336 (iwqp->ibqp_state == IB_QPS_RTS)) {
337 i40iw_next_iw_state(iwqp,
338 I40IW_QP_STATE_CLOSING, 0, 0, 0);
339 i40iw_cm_disconn(iwqp);
340 }
341 iwqp->cm_id->add_ref(iwqp->cm_id);
342 i40iw_schedule_cm_timer(iwqp->cm_node,
343 (struct i40iw_puda_buf *)iwqp,
344 I40IW_TIMER_TYPE_CLOSE, 1, 0);
345 }
346 break;
347 case I40IW_AE_LLP_CLOSE_COMPLETE:
348 if (qp->term_flags)
349 i40iw_terminate_done(qp, 0);
350 else
351 i40iw_cm_disconn(iwqp);
352 break;
353 case I40IW_AE_RESET_SENT:
354 i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 1, 0, 0);
355 i40iw_cm_disconn(iwqp);
356 break;
357 case I40IW_AE_LLP_CONNECTION_RESET:
358 if (atomic_read(&iwqp->close_timer_started))
359 continue;
360 i40iw_cm_disconn(iwqp);
361 break;
362 case I40IW_AE_TERMINATE_SENT:
363 i40iw_terminate_send_fin(qp);
364 break;
365 case I40IW_AE_LLP_TERMINATE_RECEIVED:
366 i40iw_terminate_received(qp, info);
367 break;
368 case I40IW_AE_CQ_OPERATION_ERROR:
369 i40iw_pr_err("Processing an iWARP related AE for CQ misc = 0x%04X\n",
370 info->ae_id);
371 cq = (struct i40iw_sc_cq *)(unsigned long)info->compl_ctx;
372 iwcq = (struct i40iw_cq *)cq->back_cq;
373
374 if (iwcq->ibcq.event_handler) {
375 struct ib_event ibevent;
376
377 ibevent.device = iwcq->ibcq.device;
378 ibevent.event = IB_EVENT_CQ_ERR;
379 ibevent.element.cq = &iwcq->ibcq;
380 iwcq->ibcq.event_handler(&ibevent, iwcq->ibcq.cq_context);
381 }
382 break;
383 case I40IW_AE_PRIV_OPERATION_DENIED:
384 case I40IW_AE_STAG_ZERO_INVALID:
385 case I40IW_AE_IB_RREQ_AND_Q1_FULL:
386 case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION:
387 case I40IW_AE_DDP_UBE_INVALID_MO:
388 case I40IW_AE_DDP_UBE_INVALID_QN:
389 case I40IW_AE_DDP_NO_L_BIT:
390 case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
391 case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
392 case I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST:
393 case I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
394 case I40IW_AE_INVALID_ARP_ENTRY:
395 case I40IW_AE_INVALID_TCP_OPTION_RCVD:
396 case I40IW_AE_STALE_ARP_ENTRY:
397 case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR:
398 case I40IW_AE_LLP_SEGMENT_TOO_SMALL:
399 case I40IW_AE_LLP_SYN_RECEIVED:
400 case I40IW_AE_LLP_TOO_MANY_RETRIES:
401 case I40IW_AE_LLP_DOUBT_REACHABILITY:
402 case I40IW_AE_LCE_QP_CATASTROPHIC:
403 case I40IW_AE_LCE_FUNCTION_CATASTROPHIC:
404 case I40IW_AE_LCE_CQ_CATASTROPHIC:
405 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG:
406 case I40IW_AE_UDA_XMIT_IPADDR_MISMATCH:
407 case I40IW_AE_QP_SUSPEND_COMPLETE:
408 ctx_info->err_rq_idx_valid = false;
409 default:
410 if (!info->sq && ctx_info->err_rq_idx_valid) {
411 ctx_info->err_rq_idx = info->wqe_idx;
412 ctx_info->tcp_info_valid = false;
413 ctx_info->iwarp_info_valid = false;
414 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
415 iwqp->host_ctx.va,
416 ctx_info);
417 }
418 i40iw_terminate_connection(qp, info);
419 break;
420 }
996abf0a
IM		 421 if (info->qp)
422 i40iw_rem_ref(&iwqp->ibqp);
4e9042e6
FL		 423 } while (1);
424
425 if (aeqcnt)
426 dev->aeq_ops->repost_aeq_entries(dev, aeqcnt);
427}
428
429/**
430 * i40iw_manage_apbvt - add or delete tcp port
431 * @iwdev: iwarp device
432 * @accel_local_port: port for apbvt
433 * @add_port: add or delete port
434 */
435int i40iw_manage_apbvt(struct i40iw_device *iwdev, u16 accel_local_port, bool add_port)
436{
437 struct i40iw_apbvt_info *info;
438 enum i40iw_status_code status;
439 struct i40iw_cqp_request *cqp_request;
440 struct cqp_commands_info *cqp_info;
441
442 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, add_port);
443 if (!cqp_request)
444 return -ENOMEM;
445
446 cqp_info = &cqp_request->info;
447 info = &cqp_info->in.u.manage_apbvt_entry.info;
448
449 memset(info, 0, sizeof(*info));
450 info->add = add_port;
451 info->port = cpu_to_le16(accel_local_port);
452
453 cqp_info->cqp_cmd = OP_MANAGE_APBVT_ENTRY;
454 cqp_info->post_sq = 1;
455 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->cqp.sc_cqp;
456 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request;
457 status = i40iw_handle_cqp_op(iwdev, cqp_request);
458 if (status)
459 i40iw_pr_err("CQP-OP Manage APBVT entry fail");
460 return status;
461}
462
463/**
464 * i40iw_manage_arp_cache - manage hw arp cache
465 * @iwdev: iwarp device
466 * @mac_addr: mac address ptr
467 * @ip_addr: ip addr for arp cache
468 * @action: add, delete or modify
469 */
470void i40iw_manage_arp_cache(struct i40iw_device *iwdev,
471 unsigned char *mac_addr,
20c61f7e 472 u32 *ip_addr,
4e9042e6
FL		 473 bool ipv4,
474 u32 action)
475{
476 struct i40iw_add_arp_cache_entry_info *info;
477 struct i40iw_cqp_request *cqp_request;
478 struct cqp_commands_info *cqp_info;
479 int arp_index;
480
481 arp_index = i40iw_arp_table(iwdev, ip_addr, ipv4, mac_addr, action);
482 if (arp_index == -1)
483 return;
484 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
485 if (!cqp_request)
486 return;
487
488 cqp_info = &cqp_request->info;
489 if (action == I40IW_ARP_ADD) {
490 cqp_info->cqp_cmd = OP_ADD_ARP_CACHE_ENTRY;
491 info = &cqp_info->in.u.add_arp_cache_entry.info;
492 memset(info, 0, sizeof(*info));
20c61f7e 493 info->arp_index = cpu_to_le16((u16)arp_index);
4e9042e6
FL		 494 info->permanent = true;
495 ether_addr_copy(info->mac_addr, mac_addr);
496 cqp_info->in.u.add_arp_cache_entry.scratch = (uintptr_t)cqp_request;
497 cqp_info->in.u.add_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
498 } else {
499 cqp_info->cqp_cmd = OP_DELETE_ARP_CACHE_ENTRY;
500 cqp_info->in.u.del_arp_cache_entry.scratch = (uintptr_t)cqp_request;
501 cqp_info->in.u.del_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
502 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index;
503 }
504
505 cqp_info->in.u.add_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
506 cqp_info->in.u.add_arp_cache_entry.scratch = (uintptr_t)cqp_request;
507 cqp_info->post_sq = 1;
508 if (i40iw_handle_cqp_op(iwdev, cqp_request))
509 i40iw_pr_err("CQP-OP Add/Del Arp Cache entry fail");
510}
511
512/**
513 * i40iw_send_syn_cqp_callback - do syn/ack after qhash
514 * @cqp_request: qhash cqp completion
515 * @send_ack: flag send ack
516 */
517static void i40iw_send_syn_cqp_callback(struct i40iw_cqp_request *cqp_request, u32 send_ack)
518{
519 i40iw_send_syn(cqp_request->param, send_ack);
520}
521
522/**
523 * i40iw_manage_qhash - add or modify qhash
524 * @iwdev: iwarp device
525 * @cminfo: cm info for qhash
526 * @etype: type (syn or quad)
527 * @mtype: type of qhash
528 * @cmnode: cmnode associated with connection
529 * @wait: wait for completion
530 * @user_pri:user pri of the connection
531 */
532enum i40iw_status_code i40iw_manage_qhash(struct i40iw_device *iwdev,
533 struct i40iw_cm_info *cminfo,
534 enum i40iw_quad_entry_type etype,
535 enum i40iw_quad_hash_manage_type mtype,
536 void *cmnode,
537 bool wait)
538{
539 struct i40iw_qhash_table_info *info;
540 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
541 enum i40iw_status_code status;
542 struct i40iw_cqp *iwcqp = &iwdev->cqp;
543 struct i40iw_cqp_request *cqp_request;
544 struct cqp_commands_info *cqp_info;
545
546 cqp_request = i40iw_get_cqp_request(iwcqp, wait);
547 if (!cqp_request)
548 return I40IW_ERR_NO_MEMORY;
549 cqp_info = &cqp_request->info;
550 info = &cqp_info->in.u.manage_qhash_table_entry.info;
551 memset(info, 0, sizeof(*info));
552
553 info->manage = mtype;
554 info->entry_type = etype;
555 if (cminfo->vlan_id != 0xFFFF) {
556 info->vlan_valid = true;
557 info->vlan_id = cpu_to_le16(cminfo->vlan_id);
558 } else {
559 info->vlan_valid = false;
560 }
561
562 info->ipv4_valid = cminfo->ipv4;
563 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr);
564 info->qp_num = cpu_to_le32(dev->ilq->qp_id);
8d8cd0bf
FL		 565 info->dest_port = cpu_to_le16(cminfo->loc_port);
566 info->dest_ip[0] = cpu_to_le32(cminfo->loc_addr[0]);
567 info->dest_ip[1] = cpu_to_le32(cminfo->loc_addr[1]);
568 info->dest_ip[2] = cpu_to_le32(cminfo->loc_addr[2]);
569 info->dest_ip[3] = cpu_to_le32(cminfo->loc_addr[3]);
4e9042e6 570 if (etype == I40IW_QHASH_TYPE_TCP_ESTABLISHED) {
8d8cd0bf
FL		 571 info->src_port = cpu_to_le16(cminfo->rem_port);
572 info->src_ip[0] = cpu_to_le32(cminfo->rem_addr[0]);
573 info->src_ip[1] = cpu_to_le32(cminfo->rem_addr[1]);
574 info->src_ip[2] = cpu_to_le32(cminfo->rem_addr[2]);
575 info->src_ip[3] = cpu_to_le32(cminfo->rem_addr[3]);
4e9042e6
FL		 576 }
577 if (cmnode) {
578 cqp_request->callback_fcn = i40iw_send_syn_cqp_callback;
579 cqp_request->param = (void *)cmnode;
580 }
581
582 if (info->ipv4_valid)
583 i40iw_debug(dev, I40IW_DEBUG_CM,
584 "%s:%s IP=%pI4, port=%d, mac=%pM, vlan_id=%d\n",
585 __func__, (!mtype) ? "DELETE" : "ADD",
586 info->dest_ip,
587 info->dest_port, info->mac_addr, cminfo->vlan_id);
588 else
589 i40iw_debug(dev, I40IW_DEBUG_CM,
590 "%s:%s IP=%pI6, port=%d, mac=%pM, vlan_id=%d\n",
591 __func__, (!mtype) ? "DELETE" : "ADD",
592 info->dest_ip,
593 info->dest_port, info->mac_addr, cminfo->vlan_id);
594 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->cqp.sc_cqp;
595 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request;
596 cqp_info->cqp_cmd = OP_MANAGE_QHASH_TABLE_ENTRY;
597 cqp_info->post_sq = 1;
598 status = i40iw_handle_cqp_op(iwdev, cqp_request);
599 if (status)
600 i40iw_pr_err("CQP-OP Manage Qhash Entry fail");
601 return status;
602}
603
604/**
605 * i40iw_hw_flush_wqes - flush qp's wqe
606 * @iwdev: iwarp device
607 * @qp: hardware control qp
608 * @info: info for flush
609 * @wait: flag wait for completion
610 */
611enum i40iw_status_code i40iw_hw_flush_wqes(struct i40iw_device *iwdev,
612 struct i40iw_sc_qp *qp,
613 struct i40iw_qp_flush_info *info,
614 bool wait)
615{
616 enum i40iw_status_code status;
617 struct i40iw_qp_flush_info *hw_info;
618 struct i40iw_cqp_request *cqp_request;
619 struct cqp_commands_info *cqp_info;
620
621 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
622 if (!cqp_request)
623 return I40IW_ERR_NO_MEMORY;
624
625 cqp_info = &cqp_request->info;
626 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info;
627 memcpy(hw_info, info, sizeof(*hw_info));
628
629 cqp_info->cqp_cmd = OP_QP_FLUSH_WQES;
630 cqp_info->post_sq = 1;
631 cqp_info->in.u.qp_flush_wqes.qp = qp;
632 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;
633 status = i40iw_handle_cqp_op(iwdev, cqp_request);
634 if (status)
635 i40iw_pr_err("CQP-OP Flush WQE's fail");
636 return status;
637}
638
639/**
640 * i40iw_hw_manage_vf_pble_bp - manage vf pbles
641 * @iwdev: iwarp device
642 * @info: info for managing pble
643 * @wait: flag wait for completion
644 */
645enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev,
646 struct i40iw_manage_vf_pble_info *info,
647 bool wait)
648{
649 enum i40iw_status_code status;
650 struct i40iw_manage_vf_pble_info *hw_info;
651 struct i40iw_cqp_request *cqp_request;
652 struct cqp_commands_info *cqp_info;
653
654 if ((iwdev->init_state < CCQ_CREATED) && wait)
655 wait = false;
656
657 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
658 if (!cqp_request)
659 return I40IW_ERR_NO_MEMORY;
660
661 cqp_info = &cqp_request->info;
662 hw_info = &cqp_request->info.in.u.manage_vf_pble_bp.info;
663 memcpy(hw_info, info, sizeof(*hw_info));
664
665 cqp_info->cqp_cmd = OP_MANAGE_VF_PBLE_BP;
666 cqp_info->post_sq = 1;
667 cqp_info->in.u.manage_vf_pble_bp.cqp = &iwdev->cqp.sc_cqp;
668 cqp_info->in.u.manage_vf_pble_bp.scratch = (uintptr_t)cqp_request;
669 status = i40iw_handle_cqp_op(iwdev, cqp_request);
670 if (status)
671 i40iw_pr_err("CQP-OP Manage VF pble_bp fail");
672 return status;
673}
674
675/**
676 * i40iw_get_ib_wc - return change flush code to IB's
677 * @opcode: iwarp flush code
678 */
679static enum ib_wc_status i40iw_get_ib_wc(enum i40iw_flush_opcode opcode)
680{
681 switch (opcode) {
682 case FLUSH_PROT_ERR:
683 return IB_WC_LOC_PROT_ERR;
684 case FLUSH_REM_ACCESS_ERR:
685 return IB_WC_REM_ACCESS_ERR;
686 case FLUSH_LOC_QP_OP_ERR:
687 return IB_WC_LOC_QP_OP_ERR;
688 case FLUSH_REM_OP_ERR:
689 return IB_WC_REM_OP_ERR;
690 case FLUSH_LOC_LEN_ERR:
691 return IB_WC_LOC_LEN_ERR;
692 case FLUSH_GENERAL_ERR:
693 return IB_WC_GENERAL_ERR;
694 case FLUSH_FATAL_ERR:
695 default:
696 return IB_WC_FATAL_ERR;
697 }
698}
699
700/**
701 * i40iw_set_flush_info - set flush info
702 * @pinfo: set flush info
703 * @min: minor err
704 * @maj: major err
705 * @opcode: flush error code
706 */
707static void i40iw_set_flush_info(struct i40iw_qp_flush_info *pinfo,
708 u16 *min,
709 u16 *maj,
710 enum i40iw_flush_opcode opcode)
711{
712 *min = (u16)i40iw_get_ib_wc(opcode);
713 *maj = CQE_MAJOR_DRV;
714 pinfo->userflushcode = true;
715}
716
717/**
718 * i40iw_flush_wqes - flush wqe for qp
719 * @iwdev: iwarp device
720 * @iwqp: qp to flush wqes
721 */
722void i40iw_flush_wqes(struct i40iw_device *iwdev, struct i40iw_qp *iwqp)
723{
724 struct i40iw_qp_flush_info info;
725 struct i40iw_qp_flush_info *pinfo = &info;
726
727 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
728
729 memset(pinfo, 0, sizeof(*pinfo));
730 info.sq = true;
731 info.rq = true;
732 if (qp->term_flags) {
733 i40iw_set_flush_info(pinfo, &pinfo->sq_minor_code,
734 &pinfo->sq_major_code, qp->flush_code);
735 i40iw_set_flush_info(pinfo, &pinfo->rq_minor_code,
736 &pinfo->rq_major_code, qp->flush_code);
737 }
738 (void)i40iw_hw_flush_wqes(iwdev, &iwqp->sc_qp, &info, true);
739}
Linux kernel - Deliverables
This page took 0.092534 seconds and 5 git commands to generate.