projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iw_cxgb4: Take clip reference before starting IPv6 listen
[deliverable/linux.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/sched.h>
42#include <rdma/ib_user_verbs.h>
3f89a643 43#include <rdma/ib_addr.h>
2811ba51 44#include <rdma/ib_cache.h>
1b5daf11 45#include <linux/mlx5/vport.h>
e126ba97
EC		 46#include <rdma/ib_smi.h>
47#include <rdma/ib_umem.h>
48#include "user.h"
49#include "mlx5_ib.h"
50
51#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 52#define DRIVER_VERSION "2.2-1"
53#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 54
55MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
56MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
57MODULE_LICENSE("Dual BSD/GPL");
58MODULE_VERSION(DRIVER_VERSION);
59
9603b61d
JM		 60static int deprecated_prof_sel = 2;
61module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
62MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 63
64static char mlx5_version[] =
65 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
66 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
67
da7525d2
EBE		 68enum {
69 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
70};
71
1b5daf11 72static enum rdma_link_layer
ebd61f68 73mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 74{
ebd61f68 75 switch (port_type_cap) {
1b5daf11
MD		 76 case MLX5_CAP_PORT_TYPE_IB:
77 return IB_LINK_LAYER_INFINIBAND;
78 case MLX5_CAP_PORT_TYPE_ETH:
79 return IB_LINK_LAYER_ETHERNET;
80 default:
81 return IB_LINK_LAYER_UNSPECIFIED;
82 }
83}
84
ebd61f68
AS		 85static enum rdma_link_layer
86mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
87{
88 struct mlx5_ib_dev *dev = to_mdev(device);
89 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
90
91 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
92}
93
fc24fc5e
AS		 94static int mlx5_netdev_event(struct notifier_block *this,
95 unsigned long event, void *ptr)
96{
97 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
98 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
99 roce.nb);
100
101 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
102 return NOTIFY_DONE;
103
104 write_lock(&ibdev->roce.netdev_lock);
105 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
106 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
107 write_unlock(&ibdev->roce.netdev_lock);
108
109 return NOTIFY_DONE;
110}
111
112static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
113 u8 port_num)
114{
115 struct mlx5_ib_dev *ibdev = to_mdev(device);
116 struct net_device *ndev;
117
118 /* Ensure ndev does not disappear before we invoke dev_hold()
119 */
120 read_lock(&ibdev->roce.netdev_lock);
121 ndev = ibdev->roce.netdev;
122 if (ndev)
123 dev_hold(ndev);
124 read_unlock(&ibdev->roce.netdev_lock);
125
126 return ndev;
127}
128
3f89a643
AS		 129static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
130 struct ib_port_attr *props)
131{
132 struct mlx5_ib_dev *dev = to_mdev(device);
133 struct net_device *ndev;
134 enum ib_mtu ndev_ib_mtu;
135
136 memset(props, 0, sizeof(*props));
137
138 props->port_cap_flags |= IB_PORT_CM_SUP;
139 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
140
141 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
142 roce_address_table_size);
143 props->max_mtu = IB_MTU_4096;
144 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
145 props->pkey_tbl_len = 1;
146 props->state = IB_PORT_DOWN;
147 props->phys_state = 3;
148
149 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev,
150 (u16 *)&props->qkey_viol_cntr);
151
152 ndev = mlx5_ib_get_netdev(device, port_num);
153 if (!ndev)
154 return 0;
155
156 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
157 props->state = IB_PORT_ACTIVE;
158 props->phys_state = 5;
159 }
160
161 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
162
163 dev_put(ndev);
164
165 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
166
167 props->active_width = IB_WIDTH_4X; /* TODO */
168 props->active_speed = IB_SPEED_QDR; /* TODO */
169
170 return 0;
171}
172
3cca2606
AS		 173static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
174 const struct ib_gid_attr *attr,
175 void *mlx5_addr)
176{
177#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
178 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
179 source_l3_address);
180 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
181 source_mac_47_32);
182
183 if (!gid)
184 return;
185
186 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
187
188 if (is_vlan_dev(attr->ndev)) {
189 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
190 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
191 }
192
193 switch (attr->gid_type) {
194 case IB_GID_TYPE_IB:
195 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
196 break;
197 case IB_GID_TYPE_ROCE_UDP_ENCAP:
198 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
199 break;
200
201 default:
202 WARN_ON(true);
203 }
204
205 if (attr->gid_type != IB_GID_TYPE_IB) {
206 if (ipv6_addr_v4mapped((void *)gid))
207 MLX5_SET_RA(mlx5_addr, roce_l3_type,
208 MLX5_ROCE_L3_TYPE_IPV4);
209 else
210 MLX5_SET_RA(mlx5_addr, roce_l3_type,
211 MLX5_ROCE_L3_TYPE_IPV6);
212 }
213
214 if ((attr->gid_type == IB_GID_TYPE_IB) ||
215 !ipv6_addr_v4mapped((void *)gid))
216 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
217 else
218 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
219}
220
221static int set_roce_addr(struct ib_device *device, u8 port_num,
222 unsigned int index,
223 const union ib_gid *gid,
224 const struct ib_gid_attr *attr)
225{
226 struct mlx5_ib_dev *dev = to_mdev(device);
227 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)];
228 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
229 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
230 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
231
232 if (ll != IB_LINK_LAYER_ETHERNET)
233 return -EINVAL;
234
235 memset(in, 0, sizeof(in));
236
237 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
238
239 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
240 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
241
242 memset(out, 0, sizeof(out));
243 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
244}
245
246static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
247 unsigned int index, const union ib_gid *gid,
248 const struct ib_gid_attr *attr,
249 __always_unused void **context)
250{
251 return set_roce_addr(device, port_num, index, gid, attr);
252}
253
254static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
255 unsigned int index, __always_unused void **context)
256{
257 return set_roce_addr(device, port_num, index, NULL, NULL);
258}
259
2811ba51
AS		 260__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
261 int index)
262{
263 struct ib_gid_attr attr;
264 union ib_gid gid;
265
266 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
267 return 0;
268
269 if (!attr.ndev)
270 return 0;
271
272 dev_put(attr.ndev);
273
274 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
275 return 0;
276
277 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
278}
279
1b5daf11
MD		 280static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
281{
282 return !dev->mdev->issi;
283}
284
285enum {
286 MLX5_VPORT_ACCESS_METHOD_MAD,
287 MLX5_VPORT_ACCESS_METHOD_HCA,
288 MLX5_VPORT_ACCESS_METHOD_NIC,
289};
290
291static int mlx5_get_vport_access_method(struct ib_device *ibdev)
292{
293 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
294 return MLX5_VPORT_ACCESS_METHOD_MAD;
295
ebd61f68 296 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 297 IB_LINK_LAYER_ETHERNET)
298 return MLX5_VPORT_ACCESS_METHOD_NIC;
299
300 return MLX5_VPORT_ACCESS_METHOD_HCA;
301}
302
da7525d2
EBE		 303static void get_atomic_caps(struct mlx5_ib_dev *dev,
304 struct ib_device_attr *props)
305{
306 u8 tmp;
307 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
308 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
309 u8 atomic_req_8B_endianness_mode =
310 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
311
312 /* Check if HW supports 8 bytes standard atomic operations and capable
313 * of host endianness respond
314 */
315 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
316 if (((atomic_operations & tmp) == tmp) &&
317 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
318 (atomic_req_8B_endianness_mode)) {
319 props->atomic_cap = IB_ATOMIC_HCA;
320 } else {
321 props->atomic_cap = IB_ATOMIC_NONE;
322 }
323}
324
1b5daf11
MD		 325static int mlx5_query_system_image_guid(struct ib_device *ibdev,
326 __be64 *sys_image_guid)
327{
328 struct mlx5_ib_dev *dev = to_mdev(ibdev);
329 struct mlx5_core_dev *mdev = dev->mdev;
330 u64 tmp;
331 int err;
332
333 switch (mlx5_get_vport_access_method(ibdev)) {
334 case MLX5_VPORT_ACCESS_METHOD_MAD:
335 return mlx5_query_mad_ifc_system_image_guid(ibdev,
336 sys_image_guid);
337
338 case MLX5_VPORT_ACCESS_METHOD_HCA:
339 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 340 break;
341
342 case MLX5_VPORT_ACCESS_METHOD_NIC:
343 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
344 break;
1b5daf11
MD		 345
346 default:
347 return -EINVAL;
348 }
3f89a643
AS		 349
350 if (!err)
351 *sys_image_guid = cpu_to_be64(tmp);
352
353 return err;
354
1b5daf11
MD		 355}
356
357static int mlx5_query_max_pkeys(struct ib_device *ibdev,
358 u16 *max_pkeys)
359{
360 struct mlx5_ib_dev *dev = to_mdev(ibdev);
361 struct mlx5_core_dev *mdev = dev->mdev;
362
363 switch (mlx5_get_vport_access_method(ibdev)) {
364 case MLX5_VPORT_ACCESS_METHOD_MAD:
365 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
366
367 case MLX5_VPORT_ACCESS_METHOD_HCA:
368 case MLX5_VPORT_ACCESS_METHOD_NIC:
369 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
370 pkey_table_size));
371 return 0;
372
373 default:
374 return -EINVAL;
375 }
376}
377
378static int mlx5_query_vendor_id(struct ib_device *ibdev,
379 u32 *vendor_id)
380{
381 struct mlx5_ib_dev *dev = to_mdev(ibdev);
382
383 switch (mlx5_get_vport_access_method(ibdev)) {
384 case MLX5_VPORT_ACCESS_METHOD_MAD:
385 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
386
387 case MLX5_VPORT_ACCESS_METHOD_HCA:
388 case MLX5_VPORT_ACCESS_METHOD_NIC:
389 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
390
391 default:
392 return -EINVAL;
393 }
394}
395
396static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
397 __be64 *node_guid)
398{
399 u64 tmp;
400 int err;
401
402 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
403 case MLX5_VPORT_ACCESS_METHOD_MAD:
404 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
405
406 case MLX5_VPORT_ACCESS_METHOD_HCA:
407 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 408 break;
409
410 case MLX5_VPORT_ACCESS_METHOD_NIC:
411 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
412 break;
1b5daf11
MD		 413
414 default:
415 return -EINVAL;
416 }
3f89a643
AS		 417
418 if (!err)
419 *node_guid = cpu_to_be64(tmp);
420
421 return err;
1b5daf11
MD		 422}
423
424struct mlx5_reg_node_desc {
425 u8 desc[64];
426};
427
428static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
429{
430 struct mlx5_reg_node_desc in;
431
432 if (mlx5_use_mad_ifc(dev))
433 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
434
435 memset(&in, 0, sizeof(in));
436
437 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
438 sizeof(struct mlx5_reg_node_desc),
439 MLX5_REG_NODE_DESC, 0, 0);
440}
441
e126ba97 442static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 443 struct ib_device_attr *props,
444 struct ib_udata *uhw)
e126ba97
EC		 445{
446 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 447 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 448 int err = -ENOMEM;
449 int max_rq_sg;
450 int max_sq_sg;
e0238a6a 451 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
e126ba97 452
2528e33e
MB		 453 if (uhw->inlen || uhw->outlen)
454 return -EINVAL;
455
1b5daf11
MD		 456 memset(props, 0, sizeof(*props));
457 err = mlx5_query_system_image_guid(ibdev,
458 &props->sys_image_guid);
459 if (err)
460 return err;
e126ba97 461
1b5daf11 462 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 463 if (err)
1b5daf11 464 return err;
e126ba97 465
1b5daf11
MD		 466 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
467 if (err)
468 return err;
e126ba97 469
9603b61d
JM		 470 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
471 (fw_rev_min(dev->mdev) << 16) |
472 fw_rev_sub(dev->mdev);
e126ba97
EC		 473 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
474 IB_DEVICE_PORT_ACTIVE_EVENT |
475 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 476 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 477
478 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 479 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 480 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 481 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 482 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 483 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 484 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97
EC		 485 props->device_cap_flags |= IB_DEVICE_XRC;
486 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 487 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 488 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
489 /* At this stage no support for signature handover */
490 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
491 IB_PROT_T10DIF_TYPE_2 |
492 IB_PROT_T10DIF_TYPE_3;
493 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
494 IB_GUARD_T10DIF_CSUM;
495 }
938fe83c 496 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 497 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 498
88115fe7
BW		 499 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
500 (MLX5_CAP_ETH(dev->mdev, csum_cap)))
501 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
502
1b5daf11
MD		 503 props->vendor_part_id = mdev->pdev->device;
504 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 505
506 props->max_mr_size = ~0ull;
e0238a6a 507 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 508 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
509 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
510 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
511 sizeof(struct mlx5_wqe_data_seg);
512 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
513 sizeof(struct mlx5_wqe_ctrl_seg)) /
514 sizeof(struct mlx5_wqe_data_seg);
e126ba97 515 props->max_sge = min(max_rq_sg, max_sq_sg);
18ebd407 516 props->max_sge_rd = props->max_sge;
938fe83c
SM		 517 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
518 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_eq_sz)) - 1;
519 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
520 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
521 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
522 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
523 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
524 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
525 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 526 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97
EC		 527 props->max_srq_sge = max_rq_sg - 1;
528 props->max_fast_reg_page_list_len = (unsigned int)-1;
da7525d2 529 get_atomic_caps(dev, props);
81bea28f 530 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 531 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
532 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 533 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
534 props->max_mcast_grp;
535 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
7c60bcbb
MB		 536 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
537 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 538
8cdd312c 539#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 540 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 541 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
542 props->odp_caps = dev->odp_caps;
543#endif
544
051f2630
LR		 545 if (MLX5_CAP_GEN(mdev, cd))
546 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
547
1b5daf11 548 return 0;
e126ba97
EC		 549}
550
1b5daf11
MD		 551enum mlx5_ib_width {
552 MLX5_IB_WIDTH_1X = 1 << 0,
553 MLX5_IB_WIDTH_2X = 1 << 1,
554 MLX5_IB_WIDTH_4X = 1 << 2,
555 MLX5_IB_WIDTH_8X = 1 << 3,
556 MLX5_IB_WIDTH_12X = 1 << 4
557};
558
559static int translate_active_width(struct ib_device *ibdev, u8 active_width,
560 u8 *ib_width)
e126ba97
EC		 561{
562 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 563 int err = 0;
564
565 if (active_width & MLX5_IB_WIDTH_1X) {
566 *ib_width = IB_WIDTH_1X;
567 } else if (active_width & MLX5_IB_WIDTH_2X) {
568 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
569 (int)active_width);
570 err = -EINVAL;
571 } else if (active_width & MLX5_IB_WIDTH_4X) {
572 *ib_width = IB_WIDTH_4X;
573 } else if (active_width & MLX5_IB_WIDTH_8X) {
574 *ib_width = IB_WIDTH_8X;
575 } else if (active_width & MLX5_IB_WIDTH_12X) {
576 *ib_width = IB_WIDTH_12X;
577 } else {
578 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
579 (int)active_width);
580 err = -EINVAL;
e126ba97
EC		 581 }
582
1b5daf11
MD		 583 return err;
584}
e126ba97 585
1b5daf11
MD		 586static int mlx5_mtu_to_ib_mtu(int mtu)
587{
588 switch (mtu) {
589 case 256: return 1;
590 case 512: return 2;
591 case 1024: return 3;
592 case 2048: return 4;
593 case 4096: return 5;
594 default:
595 pr_warn("invalid mtu\n");
596 return -1;
e126ba97 597 }
1b5daf11 598}
e126ba97 599
1b5daf11
MD		 600enum ib_max_vl_num {
601 __IB_MAX_VL_0 = 1,
602 __IB_MAX_VL_0_1 = 2,
603 __IB_MAX_VL_0_3 = 3,
604 __IB_MAX_VL_0_7 = 4,
605 __IB_MAX_VL_0_14 = 5,
606};
e126ba97 607
1b5daf11
MD		 608enum mlx5_vl_hw_cap {
609 MLX5_VL_HW_0 = 1,
610 MLX5_VL_HW_0_1 = 2,
611 MLX5_VL_HW_0_2 = 3,
612 MLX5_VL_HW_0_3 = 4,
613 MLX5_VL_HW_0_4 = 5,
614 MLX5_VL_HW_0_5 = 6,
615 MLX5_VL_HW_0_6 = 7,
616 MLX5_VL_HW_0_7 = 8,
617 MLX5_VL_HW_0_14 = 15
618};
e126ba97 619
1b5daf11
MD		 620static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
621 u8 *max_vl_num)
622{
623 switch (vl_hw_cap) {
624 case MLX5_VL_HW_0:
625 *max_vl_num = __IB_MAX_VL_0;
626 break;
627 case MLX5_VL_HW_0_1:
628 *max_vl_num = __IB_MAX_VL_0_1;
629 break;
630 case MLX5_VL_HW_0_3:
631 *max_vl_num = __IB_MAX_VL_0_3;
632 break;
633 case MLX5_VL_HW_0_7:
634 *max_vl_num = __IB_MAX_VL_0_7;
635 break;
636 case MLX5_VL_HW_0_14:
637 *max_vl_num = __IB_MAX_VL_0_14;
638 break;
e126ba97 639
1b5daf11
MD		 640 default:
641 return -EINVAL;
e126ba97 642 }
e126ba97 643
1b5daf11 644 return 0;
e126ba97
EC		 645}
646
1b5daf11
MD		 647static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
648 struct ib_port_attr *props)
e126ba97 649{
1b5daf11
MD		 650 struct mlx5_ib_dev *dev = to_mdev(ibdev);
651 struct mlx5_core_dev *mdev = dev->mdev;
652 struct mlx5_hca_vport_context *rep;
653 int max_mtu;
654 int oper_mtu;
655 int err;
656 u8 ib_link_width_oper;
657 u8 vl_hw_cap;
e126ba97 658
1b5daf11
MD		 659 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
660 if (!rep) {
661 err = -ENOMEM;
e126ba97 662 goto out;
e126ba97 663 }
e126ba97 664
1b5daf11 665 memset(props, 0, sizeof(*props));
e126ba97 666
1b5daf11 667 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 668 if (err)
669 goto out;
670
1b5daf11
MD		 671 props->lid = rep->lid;
672 props->lmc = rep->lmc;
673 props->sm_lid = rep->sm_lid;
674 props->sm_sl = rep->sm_sl;
675 props->state = rep->vport_state;
676 props->phys_state = rep->port_physical_state;
677 props->port_cap_flags = rep->cap_mask1;
678 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
679 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
680 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
681 props->bad_pkey_cntr = rep->pkey_violation_counter;
682 props->qkey_viol_cntr = rep->qkey_violation_counter;
683 props->subnet_timeout = rep->subnet_timeout;
684 props->init_type_reply = rep->init_type_reply;
e126ba97 685
1b5daf11
MD		 686 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
687 if (err)
e126ba97 688 goto out;
e126ba97 689
1b5daf11
MD		 690 err = translate_active_width(ibdev, ib_link_width_oper,
691 &props->active_width);
692 if (err)
693 goto out;
694 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
695 port);
e126ba97
EC		 696 if (err)
697 goto out;
698
facc9699 699 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 700
1b5daf11 701 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 702
facc9699 703 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 704
1b5daf11 705 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 706
1b5daf11
MD		 707 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
708 if (err)
709 goto out;
e126ba97 710
1b5daf11
MD		 711 err = translate_max_vl_num(ibdev, vl_hw_cap,
712 &props->max_vl_num);
e126ba97 713out:
1b5daf11 714 kfree(rep);
e126ba97
EC		 715 return err;
716}
717
1b5daf11
MD		 718int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
719 struct ib_port_attr *props)
e126ba97 720{
1b5daf11
MD		 721 switch (mlx5_get_vport_access_method(ibdev)) {
722 case MLX5_VPORT_ACCESS_METHOD_MAD:
723 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 724
1b5daf11
MD		 725 case MLX5_VPORT_ACCESS_METHOD_HCA:
726 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 727
3f89a643
AS		 728 case MLX5_VPORT_ACCESS_METHOD_NIC:
729 return mlx5_query_port_roce(ibdev, port, props);
730
1b5daf11
MD		 731 default:
732 return -EINVAL;
733 }
734}
e126ba97 735
1b5daf11
MD		 736static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
737 union ib_gid *gid)
738{
739 struct mlx5_ib_dev *dev = to_mdev(ibdev);
740 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 741
1b5daf11
MD		 742 switch (mlx5_get_vport_access_method(ibdev)) {
743 case MLX5_VPORT_ACCESS_METHOD_MAD:
744 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 745
1b5daf11
MD		 746 case MLX5_VPORT_ACCESS_METHOD_HCA:
747 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
748
749 default:
750 return -EINVAL;
751 }
e126ba97 752
e126ba97
EC		 753}
754
1b5daf11
MD		 755static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
756 u16 *pkey)
757{
758 struct mlx5_ib_dev *dev = to_mdev(ibdev);
759 struct mlx5_core_dev *mdev = dev->mdev;
760
761 switch (mlx5_get_vport_access_method(ibdev)) {
762 case MLX5_VPORT_ACCESS_METHOD_MAD:
763 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
764
765 case MLX5_VPORT_ACCESS_METHOD_HCA:
766 case MLX5_VPORT_ACCESS_METHOD_NIC:
767 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
768 pkey);
769 default:
770 return -EINVAL;
771 }
772}
e126ba97
EC		 773
774static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
775 struct ib_device_modify *props)
776{
777 struct mlx5_ib_dev *dev = to_mdev(ibdev);
778 struct mlx5_reg_node_desc in;
779 struct mlx5_reg_node_desc out;
780 int err;
781
782 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
783 return -EOPNOTSUPP;
784
785 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
786 return 0;
787
788 /*
789 * If possible, pass node desc to FW, so it can generate
790 * a 144 trap. If cmd fails, just ignore.
791 */
792 memcpy(&in, props->node_desc, 64);
9603b61d 793 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 794 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
795 if (err)
796 return err;
797
798 memcpy(ibdev->node_desc, props->node_desc, 64);
799
800 return err;
801}
802
803static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
804 struct ib_port_modify *props)
805{
806 struct mlx5_ib_dev *dev = to_mdev(ibdev);
807 struct ib_port_attr attr;
808 u32 tmp;
809 int err;
810
811 mutex_lock(&dev->cap_mask_mutex);
812
813 err = mlx5_ib_query_port(ibdev, port, &attr);
814 if (err)
815 goto out;
816
817 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
818 ~props->clr_port_cap_mask;
819
9603b61d 820 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 821
822out:
823 mutex_unlock(&dev->cap_mask_mutex);
824 return err;
825}
826
827static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
828 struct ib_udata *udata)
829{
830 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 831 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
832 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 833 struct mlx5_ib_ucontext *context;
834 struct mlx5_uuar_info *uuari;
835 struct mlx5_uar *uars;
c1be5232 836 int gross_uuars;
e126ba97 837 int num_uars;
78c0f98c 838 int ver;
e126ba97
EC		 839 int uuarn;
840 int err;
841 int i;
f241e749 842 size_t reqlen;
e126ba97
EC		 843
844 if (!dev->ib_active)
845 return ERR_PTR(-EAGAIN);
846
78c0f98c
EC		 847 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
848 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
849 ver = 0;
b368d7cb 850 else if (reqlen >= sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
78c0f98c
EC		 851 ver = 2;
852 else
853 return ERR_PTR(-EINVAL);
854
b368d7cb 855 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 856 if (err)
857 return ERR_PTR(err);
858
b368d7cb 859 if (req.flags)
78c0f98c
EC		 860 return ERR_PTR(-EINVAL);
861
e126ba97
EC		 862 if (req.total_num_uuars > MLX5_MAX_UUARS)
863 return ERR_PTR(-ENOMEM);
864
865 if (req.total_num_uuars == 0)
866 return ERR_PTR(-EINVAL);
867
b368d7cb
MB		 868 if (req.comp_mask)
869 return ERR_PTR(-EOPNOTSUPP);
870
871 if (reqlen > sizeof(req) &&
872 !ib_is_udata_cleared(udata, sizeof(req),
873 udata->inlen - sizeof(req)))
874 return ERR_PTR(-EOPNOTSUPP);
875
c1be5232
EC		 876 req.total_num_uuars = ALIGN(req.total_num_uuars,
877 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 878 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
879 return ERR_PTR(-EINVAL);
880
c1be5232
EC		 881 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
882 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c
SM		 883 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
884 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
885 resp.cache_line_size = L1_CACHE_BYTES;
886 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
887 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
888 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
889 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
890 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
b368d7cb
MB		 891 resp.response_length = min(offsetof(typeof(resp), response_length) +
892 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 893
894 context = kzalloc(sizeof(*context), GFP_KERNEL);
895 if (!context)
896 return ERR_PTR(-ENOMEM);
897
898 uuari = &context->uuari;
899 mutex_init(&uuari->lock);
900 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
901 if (!uars) {
902 err = -ENOMEM;
903 goto out_ctx;
904 }
905
c1be5232 906 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 907 sizeof(*uuari->bitmap),
908 GFP_KERNEL);
909 if (!uuari->bitmap) {
910 err = -ENOMEM;
911 goto out_uar_ctx;
912 }
913 /*
914 * clear all fast path uuars
915 */
c1be5232 916 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 917 uuarn = i & 3;
918 if (uuarn == 2 || uuarn == 3)
919 set_bit(i, uuari->bitmap);
920 }
921
c1be5232 922 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 923 if (!uuari->count) {
924 err = -ENOMEM;
925 goto out_bitmap;
926 }
927
928 for (i = 0; i < num_uars; i++) {
9603b61d 929 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 930 if (err)
931 goto out_count;
932 }
933
b4cfe447
HE		 934#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
935 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
936#endif
937
e126ba97
EC		 938 INIT_LIST_HEAD(&context->db_page_list);
939 mutex_init(&context->db_page_mutex);
940
941 resp.tot_uuars = req.total_num_uuars;
938fe83c 942 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb
MB		 943
944 if (field_avail(typeof(resp), reserved2, udata->outlen))
945 resp.response_length += sizeof(resp.reserved2);
946
947 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
948 resp.comp_mask |=
949 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
950 resp.hca_core_clock_offset =
951 offsetof(struct mlx5_init_seg, internal_timer_h) %
952 PAGE_SIZE;
953 resp.response_length += sizeof(resp.hca_core_clock_offset);
954 }
955
956 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97
EC		 957 if (err)
958 goto out_uars;
959
78c0f98c 960 uuari->ver = ver;
e126ba97
EC		 961 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
962 uuari->uars = uars;
963 uuari->num_uars = num_uars;
964 return &context->ibucontext;
965
966out_uars:
967 for (i--; i >= 0; i--)
9603b61d 968 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 969out_count:
970 kfree(uuari->count);
971
972out_bitmap:
973 kfree(uuari->bitmap);
974
975out_uar_ctx:
976 kfree(uars);
977
978out_ctx:
979 kfree(context);
980 return ERR_PTR(err);
981}
982
983static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
984{
985 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
986 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
987 struct mlx5_uuar_info *uuari = &context->uuari;
988 int i;
989
990 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 991 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 992 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
993 }
994
995 kfree(uuari->count);
996 kfree(uuari->bitmap);
997 kfree(uuari->uars);
998 kfree(context);
999
1000 return 0;
1001}
1002
1003static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1004{
9603b61d 1005 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1006}
1007
1008static int get_command(unsigned long offset)
1009{
1010 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1011}
1012
1013static int get_arg(unsigned long offset)
1014{
1015 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1016}
1017
1018static int get_index(unsigned long offset)
1019{
1020 return get_arg(offset);
1021}
1022
1023static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1024{
1025 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1026 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1027 struct mlx5_uuar_info *uuari = &context->uuari;
1028 unsigned long command;
1029 unsigned long idx;
1030 phys_addr_t pfn;
1031
1032 command = get_command(vma->vm_pgoff);
1033 switch (command) {
1034 case MLX5_IB_MMAP_REGULAR_PAGE:
1035 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1036 return -EINVAL;
1037
1038 idx = get_index(vma->vm_pgoff);
1c3ce90d
EC		 1039 if (idx >= uuari->num_uars)
1040 return -EINVAL;
1041
e126ba97
EC		 1042 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1043 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
1044 (unsigned long long)pfn);
1045
e126ba97
EC		 1046 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1047 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1048 PAGE_SIZE, vma->vm_page_prot))
1049 return -EAGAIN;
1050
1051 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
1052 vma->vm_start,
1053 (unsigned long long)pfn << PAGE_SHIFT);
1054 break;
1055
1056 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1057 return -ENOSYS;
1058
d69e3bcf
MB		 1059 case MLX5_IB_MMAP_CORE_CLOCK:
1060 {
1061 phys_addr_t pfn;
1062
1063 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1064 return -EINVAL;
1065
1066 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
1067 return -EPERM;
1068
1069 /* Don't expose to user-space information it shouldn't have */
1070 if (PAGE_SIZE > 4096)
1071 return -EOPNOTSUPP;
1072
1073 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1074 pfn = (dev->mdev->iseg_base +
1075 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1076 PAGE_SHIFT;
1077 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1078 PAGE_SIZE, vma->vm_page_prot))
1079 return -EAGAIN;
1080
1081 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1082 vma->vm_start,
1083 (unsigned long long)pfn << PAGE_SHIFT);
1084 break;
1085 }
1086
e126ba97
EC		 1087 default:
1088 return -EINVAL;
1089 }
1090
1091 return 0;
1092}
1093
e126ba97
EC		 1094static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1095 struct ib_ucontext *context,
1096 struct ib_udata *udata)
1097{
1098 struct mlx5_ib_alloc_pd_resp resp;
1099 struct mlx5_ib_pd *pd;
1100 int err;
1101
1102 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1103 if (!pd)
1104 return ERR_PTR(-ENOMEM);
1105
9603b61d 1106 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1107 if (err) {
1108 kfree(pd);
1109 return ERR_PTR(err);
1110 }
1111
1112 if (context) {
1113 resp.pdn = pd->pdn;
1114 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1115 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1116 kfree(pd);
1117 return ERR_PTR(-EFAULT);
1118 }
e126ba97
EC		 1119 }
1120
1121 return &pd->ibpd;
1122}
1123
1124static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1125{
1126 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1127 struct mlx5_ib_pd *mpd = to_mpd(pd);
1128
9603b61d 1129 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1130 kfree(mpd);
1131
1132 return 0;
1133}
1134
1135static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1136{
1137 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1138 int err;
1139
9603b61d 1140 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1141 if (err)
1142 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1143 ibqp->qp_num, gid->raw);
1144
1145 return err;
1146}
1147
1148static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1149{
1150 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1151 int err;
1152
9603b61d 1153 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1154 if (err)
1155 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1156 ibqp->qp_num, gid->raw);
1157
1158 return err;
1159}
1160
1161static int init_node_data(struct mlx5_ib_dev *dev)
1162{
1b5daf11 1163 int err;
e126ba97 1164
1b5daf11 1165 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 1166 if (err)
1b5daf11 1167 return err;
e126ba97 1168
1b5daf11 1169 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 1170
1b5daf11 1171 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 1172}
1173
1174static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1175 char *buf)
1176{
1177 struct mlx5_ib_dev *dev =
1178 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1179
9603b61d 1180 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 1181}
1182
1183static ssize_t show_reg_pages(struct device *device,
1184 struct device_attribute *attr, char *buf)
1185{
1186 struct mlx5_ib_dev *dev =
1187 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1188
6aec21f6 1189 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 1190}
1191
1192static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1193 char *buf)
1194{
1195 struct mlx5_ib_dev *dev =
1196 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1197 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1198}
1199
1200static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1201 char *buf)
1202{
1203 struct mlx5_ib_dev *dev =
1204 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d
JM		 1205 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1206 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
e126ba97
EC		 1207}
1208
1209static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1210 char *buf)
1211{
1212 struct mlx5_ib_dev *dev =
1213 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1214 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1215}
1216
1217static ssize_t show_board(struct device *device, struct device_attribute *attr,
1218 char *buf)
1219{
1220 struct mlx5_ib_dev *dev =
1221 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1222 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1223 dev->mdev->board_id);
e126ba97
EC		 1224}
1225
1226static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1227static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1228static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1229static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1230static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1231static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1232
1233static struct device_attribute *mlx5_class_attributes[] = {
1234 &dev_attr_hw_rev,
1235 &dev_attr_fw_ver,
1236 &dev_attr_hca_type,
1237 &dev_attr_board_id,
1238 &dev_attr_fw_pages,
1239 &dev_attr_reg_pages,
1240};
1241
9603b61d 1242static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 1243 enum mlx5_dev_event event, unsigned long param)
e126ba97 1244{
9603b61d 1245 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 1246 struct ib_event ibev;
9603b61d 1247
e126ba97
EC		 1248 u8 port = 0;
1249
1250 switch (event) {
1251 case MLX5_DEV_EVENT_SYS_ERROR:
1252 ibdev->ib_active = false;
1253 ibev.event = IB_EVENT_DEVICE_FATAL;
1254 break;
1255
1256 case MLX5_DEV_EVENT_PORT_UP:
1257 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 1258 port = (u8)param;
e126ba97
EC		 1259 break;
1260
1261 case MLX5_DEV_EVENT_PORT_DOWN:
1262 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 1263 port = (u8)param;
e126ba97
EC		 1264 break;
1265
1266 case MLX5_DEV_EVENT_PORT_INITIALIZED:
1267 /* not used by ULPs */
1268 return;
1269
1270 case MLX5_DEV_EVENT_LID_CHANGE:
1271 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 1272 port = (u8)param;
e126ba97
EC		 1273 break;
1274
1275 case MLX5_DEV_EVENT_PKEY_CHANGE:
1276 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 1277 port = (u8)param;
e126ba97
EC		 1278 break;
1279
1280 case MLX5_DEV_EVENT_GUID_CHANGE:
1281 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 1282 port = (u8)param;
e126ba97
EC		 1283 break;
1284
1285 case MLX5_DEV_EVENT_CLIENT_REREG:
1286 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 1287 port = (u8)param;
e126ba97
EC		 1288 break;
1289 }
1290
1291 ibev.device = &ibdev->ib_dev;
1292 ibev.element.port_num = port;
1293
a0c84c32
EC		 1294 if (port < 1 || port > ibdev->num_ports) {
1295 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1296 return;
1297 }
1298
e126ba97
EC		 1299 if (ibdev->ib_active)
1300 ib_dispatch_event(&ibev);
1301}
1302
1303static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1304{
1305 int port;
1306
938fe83c 1307 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 1308 mlx5_query_ext_port_caps(dev, port);
1309}
1310
1311static int get_port_caps(struct mlx5_ib_dev *dev)
1312{
1313 struct ib_device_attr *dprops = NULL;
1314 struct ib_port_attr *pprops = NULL;
f614fc15 1315 int err = -ENOMEM;
e126ba97 1316 int port;
2528e33e 1317 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 1318
1319 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1320 if (!pprops)
1321 goto out;
1322
1323 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1324 if (!dprops)
1325 goto out;
1326
2528e33e 1327 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 1328 if (err) {
1329 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1330 goto out;
1331 }
1332
938fe83c 1333 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 1334 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1335 if (err) {
938fe83c
SM		 1336 mlx5_ib_warn(dev, "query_port %d failed %d\n",
1337 port, err);
e126ba97
EC		 1338 break;
1339 }
938fe83c
SM		 1340 dev->mdev->port_caps[port - 1].pkey_table_len =
1341 dprops->max_pkeys;
1342 dev->mdev->port_caps[port - 1].gid_table_len =
1343 pprops->gid_tbl_len;
e126ba97
EC		 1344 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1345 dprops->max_pkeys, pprops->gid_tbl_len);
1346 }
1347
1348out:
1349 kfree(pprops);
1350 kfree(dprops);
1351
1352 return err;
1353}
1354
1355static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1356{
1357 int err;
1358
1359 err = mlx5_mr_cache_cleanup(dev);
1360 if (err)
1361 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1362
1363 mlx5_ib_destroy_qp(dev->umrc.qp);
1364 ib_destroy_cq(dev->umrc.cq);
e126ba97
EC		 1365 ib_dealloc_pd(dev->umrc.pd);
1366}
1367
1368enum {
1369 MAX_UMR_WR = 128,
1370};
1371
1372static int create_umr_res(struct mlx5_ib_dev *dev)
1373{
1374 struct ib_qp_init_attr *init_attr = NULL;
1375 struct ib_qp_attr *attr = NULL;
1376 struct ib_pd *pd;
1377 struct ib_cq *cq;
1378 struct ib_qp *qp;
8e37210b 1379 struct ib_cq_init_attr cq_attr = {};
e126ba97
EC		 1380 int ret;
1381
1382 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1383 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1384 if (!attr || !init_attr) {
1385 ret = -ENOMEM;
1386 goto error_0;
1387 }
1388
1389 pd = ib_alloc_pd(&dev->ib_dev);
1390 if (IS_ERR(pd)) {
1391 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1392 ret = PTR_ERR(pd);
1393 goto error_0;
1394 }
1395
8e37210b
MB		 1396 cq_attr.cqe = 128;
1397 cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL,
1398 &cq_attr);
e126ba97
EC		 1399 if (IS_ERR(cq)) {
1400 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1401 ret = PTR_ERR(cq);
1402 goto error_2;
1403 }
1404 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
1405
1406 init_attr->send_cq = cq;
1407 init_attr->recv_cq = cq;
1408 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1409 init_attr->cap.max_send_wr = MAX_UMR_WR;
1410 init_attr->cap.max_send_sge = 1;
1411 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1412 init_attr->port_num = 1;
1413 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1414 if (IS_ERR(qp)) {
1415 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1416 ret = PTR_ERR(qp);
1417 goto error_3;
1418 }
1419 qp->device = &dev->ib_dev;
1420 qp->real_qp = qp;
1421 qp->uobject = NULL;
1422 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1423
1424 attr->qp_state = IB_QPS_INIT;
1425 attr->port_num = 1;
1426 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1427 IB_QP_PORT, NULL);
1428 if (ret) {
1429 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1430 goto error_4;
1431 }
1432
1433 memset(attr, 0, sizeof(*attr));
1434 attr->qp_state = IB_QPS_RTR;
1435 attr->path_mtu = IB_MTU_256;
1436
1437 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1438 if (ret) {
1439 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1440 goto error_4;
1441 }
1442
1443 memset(attr, 0, sizeof(*attr));
1444 attr->qp_state = IB_QPS_RTS;
1445 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1446 if (ret) {
1447 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1448 goto error_4;
1449 }
1450
1451 dev->umrc.qp = qp;
1452 dev->umrc.cq = cq;
e126ba97
EC		 1453 dev->umrc.pd = pd;
1454
1455 sema_init(&dev->umrc.sem, MAX_UMR_WR);
1456 ret = mlx5_mr_cache_init(dev);
1457 if (ret) {
1458 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1459 goto error_4;
1460 }
1461
1462 kfree(attr);
1463 kfree(init_attr);
1464
1465 return 0;
1466
1467error_4:
1468 mlx5_ib_destroy_qp(qp);
1469
1470error_3:
1471 ib_destroy_cq(cq);
1472
1473error_2:
e126ba97
EC		 1474 ib_dealloc_pd(pd);
1475
1476error_0:
1477 kfree(attr);
1478 kfree(init_attr);
1479 return ret;
1480}
1481
1482static int create_dev_resources(struct mlx5_ib_resources *devr)
1483{
1484 struct ib_srq_init_attr attr;
1485 struct mlx5_ib_dev *dev;
bcf4c1ea 1486 struct ib_cq_init_attr cq_attr = {.cqe = 1};
e126ba97
EC		 1487 int ret = 0;
1488
1489 dev = container_of(devr, struct mlx5_ib_dev, devr);
1490
1491 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
1492 if (IS_ERR(devr->p0)) {
1493 ret = PTR_ERR(devr->p0);
1494 goto error0;
1495 }
1496 devr->p0->device = &dev->ib_dev;
1497 devr->p0->uobject = NULL;
1498 atomic_set(&devr->p0->usecnt, 0);
1499
bcf4c1ea 1500 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 1501 if (IS_ERR(devr->c0)) {
1502 ret = PTR_ERR(devr->c0);
1503 goto error1;
1504 }
1505 devr->c0->device = &dev->ib_dev;
1506 devr->c0->uobject = NULL;
1507 devr->c0->comp_handler = NULL;
1508 devr->c0->event_handler = NULL;
1509 devr->c0->cq_context = NULL;
1510 atomic_set(&devr->c0->usecnt, 0);
1511
1512 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1513 if (IS_ERR(devr->x0)) {
1514 ret = PTR_ERR(devr->x0);
1515 goto error2;
1516 }
1517 devr->x0->device = &dev->ib_dev;
1518 devr->x0->inode = NULL;
1519 atomic_set(&devr->x0->usecnt, 0);
1520 mutex_init(&devr->x0->tgt_qp_mutex);
1521 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
1522
1523 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1524 if (IS_ERR(devr->x1)) {
1525 ret = PTR_ERR(devr->x1);
1526 goto error3;
1527 }
1528 devr->x1->device = &dev->ib_dev;
1529 devr->x1->inode = NULL;
1530 atomic_set(&devr->x1->usecnt, 0);
1531 mutex_init(&devr->x1->tgt_qp_mutex);
1532 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
1533
1534 memset(&attr, 0, sizeof(attr));
1535 attr.attr.max_sge = 1;
1536 attr.attr.max_wr = 1;
1537 attr.srq_type = IB_SRQT_XRC;
1538 attr.ext.xrc.cq = devr->c0;
1539 attr.ext.xrc.xrcd = devr->x0;
1540
1541 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1542 if (IS_ERR(devr->s0)) {
1543 ret = PTR_ERR(devr->s0);
1544 goto error4;
1545 }
1546 devr->s0->device = &dev->ib_dev;
1547 devr->s0->pd = devr->p0;
1548 devr->s0->uobject = NULL;
1549 devr->s0->event_handler = NULL;
1550 devr->s0->srq_context = NULL;
1551 devr->s0->srq_type = IB_SRQT_XRC;
1552 devr->s0->ext.xrc.xrcd = devr->x0;
1553 devr->s0->ext.xrc.cq = devr->c0;
1554 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1555 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
1556 atomic_inc(&devr->p0->usecnt);
1557 atomic_set(&devr->s0->usecnt, 0);
1558
4aa17b28
HA		 1559 memset(&attr, 0, sizeof(attr));
1560 attr.attr.max_sge = 1;
1561 attr.attr.max_wr = 1;
1562 attr.srq_type = IB_SRQT_BASIC;
1563 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1564 if (IS_ERR(devr->s1)) {
1565 ret = PTR_ERR(devr->s1);
1566 goto error5;
1567 }
1568 devr->s1->device = &dev->ib_dev;
1569 devr->s1->pd = devr->p0;
1570 devr->s1->uobject = NULL;
1571 devr->s1->event_handler = NULL;
1572 devr->s1->srq_context = NULL;
1573 devr->s1->srq_type = IB_SRQT_BASIC;
1574 devr->s1->ext.xrc.cq = devr->c0;
1575 atomic_inc(&devr->p0->usecnt);
1576 atomic_set(&devr->s0->usecnt, 0);
1577
e126ba97
EC		 1578 return 0;
1579
4aa17b28
HA		 1580error5:
1581 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 1582error4:
1583 mlx5_ib_dealloc_xrcd(devr->x1);
1584error3:
1585 mlx5_ib_dealloc_xrcd(devr->x0);
1586error2:
1587 mlx5_ib_destroy_cq(devr->c0);
1588error1:
1589 mlx5_ib_dealloc_pd(devr->p0);
1590error0:
1591 return ret;
1592}
1593
1594static void destroy_dev_resources(struct mlx5_ib_resources *devr)
1595{
4aa17b28 1596 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 1597 mlx5_ib_destroy_srq(devr->s0);
1598 mlx5_ib_dealloc_xrcd(devr->x0);
1599 mlx5_ib_dealloc_xrcd(devr->x1);
1600 mlx5_ib_destroy_cq(devr->c0);
1601 mlx5_ib_dealloc_pd(devr->p0);
1602}
1603
e53505a8
AS		 1604static u32 get_core_cap_flags(struct ib_device *ibdev)
1605{
1606 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1607 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
1608 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
1609 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
1610 u32 ret = 0;
1611
1612 if (ll == IB_LINK_LAYER_INFINIBAND)
1613 return RDMA_CORE_PORT_IBA_IB;
1614
1615 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
1616 return 0;
1617
1618 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
1619 return 0;
1620
1621 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
1622 ret |= RDMA_CORE_PORT_IBA_ROCE;
1623
1624 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
1625 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
1626
1627 return ret;
1628}
1629
7738613e
IW		 1630static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
1631 struct ib_port_immutable *immutable)
1632{
1633 struct ib_port_attr attr;
1634 int err;
1635
1636 err = mlx5_ib_query_port(ibdev, port_num, &attr);
1637 if (err)
1638 return err;
1639
1640 immutable->pkey_tbl_len = attr.pkey_tbl_len;
1641 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 1642 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 1643 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 1644
1645 return 0;
1646}
1647
fc24fc5e
AS		 1648static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
1649{
e53505a8
AS		 1650 int err;
1651
fc24fc5e 1652 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8
AS		 1653 err = register_netdevice_notifier(&dev->roce.nb);
1654 if (err)
1655 return err;
1656
1657 err = mlx5_nic_vport_enable_roce(dev->mdev);
1658 if (err)
1659 goto err_unregister_netdevice_notifier;
1660
1661 return 0;
1662
1663err_unregister_netdevice_notifier:
1664 unregister_netdevice_notifier(&dev->roce.nb);
1665 return err;
fc24fc5e
AS		 1666}
1667
1668static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
1669{
e53505a8 1670 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 1671 unregister_netdevice_notifier(&dev->roce.nb);
1672}
1673
9603b61d 1674static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 1675{
e126ba97 1676 struct mlx5_ib_dev *dev;
ebd61f68
AS		 1677 enum rdma_link_layer ll;
1678 int port_type_cap;
e126ba97
EC		 1679 int err;
1680 int i;
1681
ebd61f68
AS		 1682 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
1683 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
1684
e53505a8 1685 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 1686 return NULL;
1687
e126ba97
EC		 1688 printk_once(KERN_INFO "%s", mlx5_version);
1689
1690 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
1691 if (!dev)
9603b61d 1692 return NULL;
e126ba97 1693
9603b61d 1694 dev->mdev = mdev;
e126ba97 1695
fc24fc5e 1696 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 1697 err = get_port_caps(dev);
1698 if (err)
9603b61d 1699 goto err_dealloc;
e126ba97 1700
1b5daf11
MD		 1701 if (mlx5_use_mad_ifc(dev))
1702 get_ext_port_caps(dev);
e126ba97 1703
e126ba97
EC		 1704 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
1705
1706 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
1707 dev->ib_dev.owner = THIS_MODULE;
1708 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 1709 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 1710 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 1711 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 1712 dev->ib_dev.num_comp_vectors =
1713 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 1714 dev->ib_dev.dma_device = &mdev->pdev->dev;
1715
1716 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
1717 dev->ib_dev.uverbs_cmd_mask =
1718 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
1719 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
1720 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
1721 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
1722 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
1723 (1ull << IB_USER_VERBS_CMD_REG_MR) |
1724 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
1725 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
1726 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
1727 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
1728 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
1729 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
1730 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
1731 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
1732 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
1733 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
1734 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
1735 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
1736 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
1737 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
1738 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
1739 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
1740 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a
HE		 1741 dev->ib_dev.uverbs_ex_cmd_mask =
1742 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE);
e126ba97
EC		 1743
1744 dev->ib_dev.query_device = mlx5_ib_query_device;
1745 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 1746 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 1747 if (ll == IB_LINK_LAYER_ETHERNET)
1748 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 1749 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 1750 dev->ib_dev.add_gid = mlx5_ib_add_gid;
1751 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 1752 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
1753 dev->ib_dev.modify_device = mlx5_ib_modify_device;
1754 dev->ib_dev.modify_port = mlx5_ib_modify_port;
1755 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
1756 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
1757 dev->ib_dev.mmap = mlx5_ib_mmap;
1758 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
1759 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
1760 dev->ib_dev.create_ah = mlx5_ib_create_ah;
1761 dev->ib_dev.query_ah = mlx5_ib_query_ah;
1762 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
1763 dev->ib_dev.create_srq = mlx5_ib_create_srq;
1764 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
1765 dev->ib_dev.query_srq = mlx5_ib_query_srq;
1766 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
1767 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
1768 dev->ib_dev.create_qp = mlx5_ib_create_qp;
1769 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
1770 dev->ib_dev.query_qp = mlx5_ib_query_qp;
1771 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
1772 dev->ib_dev.post_send = mlx5_ib_post_send;
1773 dev->ib_dev.post_recv = mlx5_ib_post_recv;
1774 dev->ib_dev.create_cq = mlx5_ib_create_cq;
1775 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
1776 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
1777 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
1778 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
1779 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
1780 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
1781 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
1782 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
1783 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
1784 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
1785 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 1786 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 1787 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 1788 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 1789 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
e126ba97 1790
938fe83c 1791 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 1792
938fe83c 1793 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 1794 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
1795 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
1796 dev->ib_dev.uverbs_cmd_mask |=
1797 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
1798 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
1799 }
1800
1801 err = init_node_data(dev);
1802 if (err)
233d05d2 1803 goto err_dealloc;
e126ba97
EC		 1804
1805 mutex_init(&dev->cap_mask_mutex);
e126ba97 1806
fc24fc5e
AS		 1807 if (ll == IB_LINK_LAYER_ETHERNET) {
1808 err = mlx5_enable_roce(dev);
1809 if (err)
1810 goto err_dealloc;
1811 }
1812
e126ba97
EC		 1813 err = create_dev_resources(&dev->devr);
1814 if (err)
fc24fc5e 1815 goto err_disable_roce;
e126ba97 1816
6aec21f6 1817 err = mlx5_ib_odp_init_one(dev);
281d1a92 1818 if (err)
e126ba97
EC		 1819 goto err_rsrc;
1820
6aec21f6
HE		 1821 err = ib_register_device(&dev->ib_dev, NULL);
1822 if (err)
1823 goto err_odp;
1824
e126ba97
EC		 1825 err = create_umr_res(dev);
1826 if (err)
1827 goto err_dev;
1828
1829 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 1830 err = device_create_file(&dev->ib_dev.dev,
1831 mlx5_class_attributes[i]);
1832 if (err)
e126ba97
EC		 1833 goto err_umrc;
1834 }
1835
1836 dev->ib_active = true;
1837
9603b61d 1838 return dev;
e126ba97
EC		 1839
1840err_umrc:
1841 destroy_umrc_res(dev);
1842
1843err_dev:
1844 ib_unregister_device(&dev->ib_dev);
1845
6aec21f6
HE		 1846err_odp:
1847 mlx5_ib_odp_remove_one(dev);
1848
e126ba97
EC		 1849err_rsrc:
1850 destroy_dev_resources(&dev->devr);
1851
fc24fc5e
AS		 1852err_disable_roce:
1853 if (ll == IB_LINK_LAYER_ETHERNET)
1854 mlx5_disable_roce(dev);
1855
9603b61d 1856err_dealloc:
e126ba97
EC		 1857 ib_dealloc_device((struct ib_device *)dev);
1858
9603b61d 1859 return NULL;
e126ba97
EC		 1860}
1861
9603b61d 1862static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 1863{
9603b61d 1864 struct mlx5_ib_dev *dev = context;
fc24fc5e 1865 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 1866
e126ba97 1867 ib_unregister_device(&dev->ib_dev);
eefd56e5 1868 destroy_umrc_res(dev);
6aec21f6 1869 mlx5_ib_odp_remove_one(dev);
e126ba97 1870 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 1871 if (ll == IB_LINK_LAYER_ETHERNET)
1872 mlx5_disable_roce(dev);
e126ba97
EC		 1873 ib_dealloc_device(&dev->ib_dev);
1874}
1875
9603b61d
JM		 1876static struct mlx5_interface mlx5_ib_interface = {
1877 .add = mlx5_ib_add,
1878 .remove = mlx5_ib_remove,
1879 .event = mlx5_ib_event,
64613d94 1880 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 1881};
1882
1883static int __init mlx5_ib_init(void)
1884{
6aec21f6
HE		 1885 int err;
1886
9603b61d
JM		 1887 if (deprecated_prof_sel != 2)
1888 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
1889
6aec21f6
HE		 1890 err = mlx5_ib_odp_init();
1891 if (err)
1892 return err;
1893
1894 err = mlx5_register_interface(&mlx5_ib_interface);
1895 if (err)
1896 goto clean_odp;
1897
1898 return err;
1899
1900clean_odp:
1901 mlx5_ib_odp_cleanup();
1902 return err;
e126ba97
EC		 1903}
1904
1905static void __exit mlx5_ib_cleanup(void)
1906{
9603b61d 1907 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 1908 mlx5_ib_odp_cleanup();
e126ba97
EC		 1909}
1910
1911module_init(mlx5_ib_init);
1912module_exit(mlx5_ib_cleanup);
Linux kernel - Deliverables
This page took 0.240694 seconds and 5 git commands to generate.