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IB/mlx4: Convert kmalloc to kmalloc_array for checkpatch
[deliverable/linux.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/sched.h>
42#include <rdma/ib_user_verbs.h>
3f89a643 43#include <rdma/ib_addr.h>
2811ba51 44#include <rdma/ib_cache.h>
1b5daf11 45#include <linux/mlx5/vport.h>
e126ba97
EC		 46#include <rdma/ib_smi.h>
47#include <rdma/ib_umem.h>
48#include "user.h"
49#include "mlx5_ib.h"
50
51#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 52#define DRIVER_VERSION "2.2-1"
53#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 54
55MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
56MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
57MODULE_LICENSE("Dual BSD/GPL");
58MODULE_VERSION(DRIVER_VERSION);
59
9603b61d
JM		 60static int deprecated_prof_sel = 2;
61module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
62MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 63
64static char mlx5_version[] =
65 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
66 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
67
da7525d2
EBE		 68enum {
69 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
70};
71
1b5daf11 72static enum rdma_link_layer
ebd61f68 73mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 74{
ebd61f68 75 switch (port_type_cap) {
1b5daf11
MD		 76 case MLX5_CAP_PORT_TYPE_IB:
77 return IB_LINK_LAYER_INFINIBAND;
78 case MLX5_CAP_PORT_TYPE_ETH:
79 return IB_LINK_LAYER_ETHERNET;
80 default:
81 return IB_LINK_LAYER_UNSPECIFIED;
82 }
83}
84
ebd61f68
AS		 85static enum rdma_link_layer
86mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
87{
88 struct mlx5_ib_dev *dev = to_mdev(device);
89 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
90
91 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
92}
93
fc24fc5e
AS		 94static int mlx5_netdev_event(struct notifier_block *this,
95 unsigned long event, void *ptr)
96{
97 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
98 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
99 roce.nb);
100
101 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
102 return NOTIFY_DONE;
103
104 write_lock(&ibdev->roce.netdev_lock);
105 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
106 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
107 write_unlock(&ibdev->roce.netdev_lock);
108
109 return NOTIFY_DONE;
110}
111
112static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
113 u8 port_num)
114{
115 struct mlx5_ib_dev *ibdev = to_mdev(device);
116 struct net_device *ndev;
117
118 /* Ensure ndev does not disappear before we invoke dev_hold()
119 */
120 read_lock(&ibdev->roce.netdev_lock);
121 ndev = ibdev->roce.netdev;
122 if (ndev)
123 dev_hold(ndev);
124 read_unlock(&ibdev->roce.netdev_lock);
125
126 return ndev;
127}
128
3f89a643
AS		 129static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
130 struct ib_port_attr *props)
131{
132 struct mlx5_ib_dev *dev = to_mdev(device);
133 struct net_device *ndev;
134 enum ib_mtu ndev_ib_mtu;
135
136 memset(props, 0, sizeof(*props));
137
138 props->port_cap_flags |= IB_PORT_CM_SUP;
139 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
140
141 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
142 roce_address_table_size);
143 props->max_mtu = IB_MTU_4096;
144 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
145 props->pkey_tbl_len = 1;
146 props->state = IB_PORT_DOWN;
147 props->phys_state = 3;
148
149 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev,
150 (u16 *)&props->qkey_viol_cntr);
151
152 ndev = mlx5_ib_get_netdev(device, port_num);
153 if (!ndev)
154 return 0;
155
156 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
157 props->state = IB_PORT_ACTIVE;
158 props->phys_state = 5;
159 }
160
161 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
162
163 dev_put(ndev);
164
165 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
166
167 props->active_width = IB_WIDTH_4X; /* TODO */
168 props->active_speed = IB_SPEED_QDR; /* TODO */
169
170 return 0;
171}
172
3cca2606
AS		 173static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
174 const struct ib_gid_attr *attr,
175 void *mlx5_addr)
176{
177#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
178 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
179 source_l3_address);
180 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
181 source_mac_47_32);
182
183 if (!gid)
184 return;
185
186 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
187
188 if (is_vlan_dev(attr->ndev)) {
189 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
190 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
191 }
192
193 switch (attr->gid_type) {
194 case IB_GID_TYPE_IB:
195 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
196 break;
197 case IB_GID_TYPE_ROCE_UDP_ENCAP:
198 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
199 break;
200
201 default:
202 WARN_ON(true);
203 }
204
205 if (attr->gid_type != IB_GID_TYPE_IB) {
206 if (ipv6_addr_v4mapped((void *)gid))
207 MLX5_SET_RA(mlx5_addr, roce_l3_type,
208 MLX5_ROCE_L3_TYPE_IPV4);
209 else
210 MLX5_SET_RA(mlx5_addr, roce_l3_type,
211 MLX5_ROCE_L3_TYPE_IPV6);
212 }
213
214 if ((attr->gid_type == IB_GID_TYPE_IB) ||
215 !ipv6_addr_v4mapped((void *)gid))
216 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
217 else
218 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
219}
220
221static int set_roce_addr(struct ib_device *device, u8 port_num,
222 unsigned int index,
223 const union ib_gid *gid,
224 const struct ib_gid_attr *attr)
225{
226 struct mlx5_ib_dev *dev = to_mdev(device);
227 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)];
228 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
229 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
230 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
231
232 if (ll != IB_LINK_LAYER_ETHERNET)
233 return -EINVAL;
234
235 memset(in, 0, sizeof(in));
236
237 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
238
239 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
240 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
241
242 memset(out, 0, sizeof(out));
243 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
244}
245
246static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
247 unsigned int index, const union ib_gid *gid,
248 const struct ib_gid_attr *attr,
249 __always_unused void **context)
250{
251 return set_roce_addr(device, port_num, index, gid, attr);
252}
253
254static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
255 unsigned int index, __always_unused void **context)
256{
257 return set_roce_addr(device, port_num, index, NULL, NULL);
258}
259
2811ba51
AS		 260__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
261 int index)
262{
263 struct ib_gid_attr attr;
264 union ib_gid gid;
265
266 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
267 return 0;
268
269 if (!attr.ndev)
270 return 0;
271
272 dev_put(attr.ndev);
273
274 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
275 return 0;
276
277 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
278}
279
1b5daf11
MD		 280static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
281{
282 return !dev->mdev->issi;
283}
284
285enum {
286 MLX5_VPORT_ACCESS_METHOD_MAD,
287 MLX5_VPORT_ACCESS_METHOD_HCA,
288 MLX5_VPORT_ACCESS_METHOD_NIC,
289};
290
291static int mlx5_get_vport_access_method(struct ib_device *ibdev)
292{
293 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
294 return MLX5_VPORT_ACCESS_METHOD_MAD;
295
ebd61f68 296 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 297 IB_LINK_LAYER_ETHERNET)
298 return MLX5_VPORT_ACCESS_METHOD_NIC;
299
300 return MLX5_VPORT_ACCESS_METHOD_HCA;
301}
302
da7525d2
EBE		 303static void get_atomic_caps(struct mlx5_ib_dev *dev,
304 struct ib_device_attr *props)
305{
306 u8 tmp;
307 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
308 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
309 u8 atomic_req_8B_endianness_mode =
310 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
311
312 /* Check if HW supports 8 bytes standard atomic operations and capable
313 * of host endianness respond
314 */
315 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
316 if (((atomic_operations & tmp) == tmp) &&
317 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
318 (atomic_req_8B_endianness_mode)) {
319 props->atomic_cap = IB_ATOMIC_HCA;
320 } else {
321 props->atomic_cap = IB_ATOMIC_NONE;
322 }
323}
324
1b5daf11
MD		 325static int mlx5_query_system_image_guid(struct ib_device *ibdev,
326 __be64 *sys_image_guid)
327{
328 struct mlx5_ib_dev *dev = to_mdev(ibdev);
329 struct mlx5_core_dev *mdev = dev->mdev;
330 u64 tmp;
331 int err;
332
333 switch (mlx5_get_vport_access_method(ibdev)) {
334 case MLX5_VPORT_ACCESS_METHOD_MAD:
335 return mlx5_query_mad_ifc_system_image_guid(ibdev,
336 sys_image_guid);
337
338 case MLX5_VPORT_ACCESS_METHOD_HCA:
339 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 340 break;
341
342 case MLX5_VPORT_ACCESS_METHOD_NIC:
343 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
344 break;
1b5daf11
MD		 345
346 default:
347 return -EINVAL;
348 }
3f89a643
AS		 349
350 if (!err)
351 *sys_image_guid = cpu_to_be64(tmp);
352
353 return err;
354
1b5daf11
MD		 355}
356
357static int mlx5_query_max_pkeys(struct ib_device *ibdev,
358 u16 *max_pkeys)
359{
360 struct mlx5_ib_dev *dev = to_mdev(ibdev);
361 struct mlx5_core_dev *mdev = dev->mdev;
362
363 switch (mlx5_get_vport_access_method(ibdev)) {
364 case MLX5_VPORT_ACCESS_METHOD_MAD:
365 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
366
367 case MLX5_VPORT_ACCESS_METHOD_HCA:
368 case MLX5_VPORT_ACCESS_METHOD_NIC:
369 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
370 pkey_table_size));
371 return 0;
372
373 default:
374 return -EINVAL;
375 }
376}
377
378static int mlx5_query_vendor_id(struct ib_device *ibdev,
379 u32 *vendor_id)
380{
381 struct mlx5_ib_dev *dev = to_mdev(ibdev);
382
383 switch (mlx5_get_vport_access_method(ibdev)) {
384 case MLX5_VPORT_ACCESS_METHOD_MAD:
385 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
386
387 case MLX5_VPORT_ACCESS_METHOD_HCA:
388 case MLX5_VPORT_ACCESS_METHOD_NIC:
389 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
390
391 default:
392 return -EINVAL;
393 }
394}
395
396static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
397 __be64 *node_guid)
398{
399 u64 tmp;
400 int err;
401
402 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
403 case MLX5_VPORT_ACCESS_METHOD_MAD:
404 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
405
406 case MLX5_VPORT_ACCESS_METHOD_HCA:
407 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 408 break;
409
410 case MLX5_VPORT_ACCESS_METHOD_NIC:
411 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
412 break;
1b5daf11
MD		 413
414 default:
415 return -EINVAL;
416 }
3f89a643
AS		 417
418 if (!err)
419 *node_guid = cpu_to_be64(tmp);
420
421 return err;
1b5daf11
MD		 422}
423
424struct mlx5_reg_node_desc {
425 u8 desc[64];
426};
427
428static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
429{
430 struct mlx5_reg_node_desc in;
431
432 if (mlx5_use_mad_ifc(dev))
433 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
434
435 memset(&in, 0, sizeof(in));
436
437 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
438 sizeof(struct mlx5_reg_node_desc),
439 MLX5_REG_NODE_DESC, 0, 0);
440}
441
e126ba97 442static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 443 struct ib_device_attr *props,
444 struct ib_udata *uhw)
e126ba97
EC		 445{
446 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 447 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 448 int err = -ENOMEM;
449 int max_rq_sg;
450 int max_sq_sg;
e0238a6a 451 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
e126ba97 452
2528e33e
MB		 453 if (uhw->inlen || uhw->outlen)
454 return -EINVAL;
455
1b5daf11
MD		 456 memset(props, 0, sizeof(*props));
457 err = mlx5_query_system_image_guid(ibdev,
458 &props->sys_image_guid);
459 if (err)
460 return err;
e126ba97 461
1b5daf11 462 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 463 if (err)
1b5daf11 464 return err;
e126ba97 465
1b5daf11
MD		 466 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
467 if (err)
468 return err;
e126ba97 469
9603b61d
JM		 470 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
471 (fw_rev_min(dev->mdev) << 16) |
472 fw_rev_sub(dev->mdev);
e126ba97
EC		 473 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
474 IB_DEVICE_PORT_ACTIVE_EVENT |
475 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 476 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 477
478 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 479 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 480 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 481 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 482 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 483 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 484 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97
EC		 485 props->device_cap_flags |= IB_DEVICE_XRC;
486 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 487 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 488 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
489 /* At this stage no support for signature handover */
490 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
491 IB_PROT_T10DIF_TYPE_2 |
492 IB_PROT_T10DIF_TYPE_3;
493 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
494 IB_GUARD_T10DIF_CSUM;
495 }
938fe83c 496 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 497 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 498
1b5daf11
MD		 499 props->vendor_part_id = mdev->pdev->device;
500 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 501
502 props->max_mr_size = ~0ull;
e0238a6a 503 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 504 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
505 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
506 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
507 sizeof(struct mlx5_wqe_data_seg);
508 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
509 sizeof(struct mlx5_wqe_ctrl_seg)) /
510 sizeof(struct mlx5_wqe_data_seg);
e126ba97 511 props->max_sge = min(max_rq_sg, max_sq_sg);
18ebd407 512 props->max_sge_rd = props->max_sge;
938fe83c
SM		 513 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
514 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_eq_sz)) - 1;
515 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
516 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
517 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
518 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
519 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
520 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
521 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 522 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97
EC		 523 props->max_srq_sge = max_rq_sg - 1;
524 props->max_fast_reg_page_list_len = (unsigned int)-1;
da7525d2 525 get_atomic_caps(dev, props);
81bea28f 526 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 527 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
528 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 529 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
530 props->max_mcast_grp;
531 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
7c60bcbb
MB		 532 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
533 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 534
8cdd312c 535#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 536 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 537 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
538 props->odp_caps = dev->odp_caps;
539#endif
540
051f2630
LR		 541 if (MLX5_CAP_GEN(mdev, cd))
542 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
543
1b5daf11 544 return 0;
e126ba97
EC		 545}
546
1b5daf11
MD		 547enum mlx5_ib_width {
548 MLX5_IB_WIDTH_1X = 1 << 0,
549 MLX5_IB_WIDTH_2X = 1 << 1,
550 MLX5_IB_WIDTH_4X = 1 << 2,
551 MLX5_IB_WIDTH_8X = 1 << 3,
552 MLX5_IB_WIDTH_12X = 1 << 4
553};
554
555static int translate_active_width(struct ib_device *ibdev, u8 active_width,
556 u8 *ib_width)
e126ba97
EC		 557{
558 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 559 int err = 0;
560
561 if (active_width & MLX5_IB_WIDTH_1X) {
562 *ib_width = IB_WIDTH_1X;
563 } else if (active_width & MLX5_IB_WIDTH_2X) {
564 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
565 (int)active_width);
566 err = -EINVAL;
567 } else if (active_width & MLX5_IB_WIDTH_4X) {
568 *ib_width = IB_WIDTH_4X;
569 } else if (active_width & MLX5_IB_WIDTH_8X) {
570 *ib_width = IB_WIDTH_8X;
571 } else if (active_width & MLX5_IB_WIDTH_12X) {
572 *ib_width = IB_WIDTH_12X;
573 } else {
574 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
575 (int)active_width);
576 err = -EINVAL;
e126ba97
EC		 577 }
578
1b5daf11
MD		 579 return err;
580}
e126ba97 581
1b5daf11
MD		 582static int mlx5_mtu_to_ib_mtu(int mtu)
583{
584 switch (mtu) {
585 case 256: return 1;
586 case 512: return 2;
587 case 1024: return 3;
588 case 2048: return 4;
589 case 4096: return 5;
590 default:
591 pr_warn("invalid mtu\n");
592 return -1;
e126ba97 593 }
1b5daf11 594}
e126ba97 595
1b5daf11
MD		 596enum ib_max_vl_num {
597 __IB_MAX_VL_0 = 1,
598 __IB_MAX_VL_0_1 = 2,
599 __IB_MAX_VL_0_3 = 3,
600 __IB_MAX_VL_0_7 = 4,
601 __IB_MAX_VL_0_14 = 5,
602};
e126ba97 603
1b5daf11
MD		 604enum mlx5_vl_hw_cap {
605 MLX5_VL_HW_0 = 1,
606 MLX5_VL_HW_0_1 = 2,
607 MLX5_VL_HW_0_2 = 3,
608 MLX5_VL_HW_0_3 = 4,
609 MLX5_VL_HW_0_4 = 5,
610 MLX5_VL_HW_0_5 = 6,
611 MLX5_VL_HW_0_6 = 7,
612 MLX5_VL_HW_0_7 = 8,
613 MLX5_VL_HW_0_14 = 15
614};
e126ba97 615
1b5daf11
MD		 616static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
617 u8 *max_vl_num)
618{
619 switch (vl_hw_cap) {
620 case MLX5_VL_HW_0:
621 *max_vl_num = __IB_MAX_VL_0;
622 break;
623 case MLX5_VL_HW_0_1:
624 *max_vl_num = __IB_MAX_VL_0_1;
625 break;
626 case MLX5_VL_HW_0_3:
627 *max_vl_num = __IB_MAX_VL_0_3;
628 break;
629 case MLX5_VL_HW_0_7:
630 *max_vl_num = __IB_MAX_VL_0_7;
631 break;
632 case MLX5_VL_HW_0_14:
633 *max_vl_num = __IB_MAX_VL_0_14;
634 break;
e126ba97 635
1b5daf11
MD		 636 default:
637 return -EINVAL;
e126ba97 638 }
e126ba97 639
1b5daf11 640 return 0;
e126ba97
EC		 641}
642
1b5daf11
MD		 643static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
644 struct ib_port_attr *props)
e126ba97 645{
1b5daf11
MD		 646 struct mlx5_ib_dev *dev = to_mdev(ibdev);
647 struct mlx5_core_dev *mdev = dev->mdev;
648 struct mlx5_hca_vport_context *rep;
649 int max_mtu;
650 int oper_mtu;
651 int err;
652 u8 ib_link_width_oper;
653 u8 vl_hw_cap;
e126ba97 654
1b5daf11
MD		 655 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
656 if (!rep) {
657 err = -ENOMEM;
e126ba97 658 goto out;
e126ba97 659 }
e126ba97 660
1b5daf11 661 memset(props, 0, sizeof(*props));
e126ba97 662
1b5daf11 663 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 664 if (err)
665 goto out;
666
1b5daf11
MD		 667 props->lid = rep->lid;
668 props->lmc = rep->lmc;
669 props->sm_lid = rep->sm_lid;
670 props->sm_sl = rep->sm_sl;
671 props->state = rep->vport_state;
672 props->phys_state = rep->port_physical_state;
673 props->port_cap_flags = rep->cap_mask1;
674 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
675 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
676 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
677 props->bad_pkey_cntr = rep->pkey_violation_counter;
678 props->qkey_viol_cntr = rep->qkey_violation_counter;
679 props->subnet_timeout = rep->subnet_timeout;
680 props->init_type_reply = rep->init_type_reply;
e126ba97 681
1b5daf11
MD		 682 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
683 if (err)
e126ba97 684 goto out;
e126ba97 685
1b5daf11
MD		 686 err = translate_active_width(ibdev, ib_link_width_oper,
687 &props->active_width);
688 if (err)
689 goto out;
690 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
691 port);
e126ba97
EC		 692 if (err)
693 goto out;
694
facc9699 695 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 696
1b5daf11 697 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 698
facc9699 699 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 700
1b5daf11 701 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 702
1b5daf11
MD		 703 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
704 if (err)
705 goto out;
e126ba97 706
1b5daf11
MD		 707 err = translate_max_vl_num(ibdev, vl_hw_cap,
708 &props->max_vl_num);
e126ba97 709out:
1b5daf11 710 kfree(rep);
e126ba97
EC		 711 return err;
712}
713
1b5daf11
MD		 714int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
715 struct ib_port_attr *props)
e126ba97 716{
1b5daf11
MD		 717 switch (mlx5_get_vport_access_method(ibdev)) {
718 case MLX5_VPORT_ACCESS_METHOD_MAD:
719 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 720
1b5daf11
MD		 721 case MLX5_VPORT_ACCESS_METHOD_HCA:
722 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 723
3f89a643
AS		 724 case MLX5_VPORT_ACCESS_METHOD_NIC:
725 return mlx5_query_port_roce(ibdev, port, props);
726
1b5daf11
MD		 727 default:
728 return -EINVAL;
729 }
730}
e126ba97 731
1b5daf11
MD		 732static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
733 union ib_gid *gid)
734{
735 struct mlx5_ib_dev *dev = to_mdev(ibdev);
736 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 737
1b5daf11
MD		 738 switch (mlx5_get_vport_access_method(ibdev)) {
739 case MLX5_VPORT_ACCESS_METHOD_MAD:
740 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 741
1b5daf11
MD		 742 case MLX5_VPORT_ACCESS_METHOD_HCA:
743 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
744
745 default:
746 return -EINVAL;
747 }
e126ba97 748
e126ba97
EC		 749}
750
1b5daf11
MD		 751static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
752 u16 *pkey)
753{
754 struct mlx5_ib_dev *dev = to_mdev(ibdev);
755 struct mlx5_core_dev *mdev = dev->mdev;
756
757 switch (mlx5_get_vport_access_method(ibdev)) {
758 case MLX5_VPORT_ACCESS_METHOD_MAD:
759 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
760
761 case MLX5_VPORT_ACCESS_METHOD_HCA:
762 case MLX5_VPORT_ACCESS_METHOD_NIC:
763 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
764 pkey);
765 default:
766 return -EINVAL;
767 }
768}
e126ba97
EC		 769
770static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
771 struct ib_device_modify *props)
772{
773 struct mlx5_ib_dev *dev = to_mdev(ibdev);
774 struct mlx5_reg_node_desc in;
775 struct mlx5_reg_node_desc out;
776 int err;
777
778 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
779 return -EOPNOTSUPP;
780
781 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
782 return 0;
783
784 /*
785 * If possible, pass node desc to FW, so it can generate
786 * a 144 trap. If cmd fails, just ignore.
787 */
788 memcpy(&in, props->node_desc, 64);
9603b61d 789 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 790 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
791 if (err)
792 return err;
793
794 memcpy(ibdev->node_desc, props->node_desc, 64);
795
796 return err;
797}
798
799static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
800 struct ib_port_modify *props)
801{
802 struct mlx5_ib_dev *dev = to_mdev(ibdev);
803 struct ib_port_attr attr;
804 u32 tmp;
805 int err;
806
807 mutex_lock(&dev->cap_mask_mutex);
808
809 err = mlx5_ib_query_port(ibdev, port, &attr);
810 if (err)
811 goto out;
812
813 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
814 ~props->clr_port_cap_mask;
815
9603b61d 816 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 817
818out:
819 mutex_unlock(&dev->cap_mask_mutex);
820 return err;
821}
822
823static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
824 struct ib_udata *udata)
825{
826 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 827 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
828 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 829 struct mlx5_ib_ucontext *context;
830 struct mlx5_uuar_info *uuari;
831 struct mlx5_uar *uars;
c1be5232 832 int gross_uuars;
e126ba97 833 int num_uars;
78c0f98c 834 int ver;
e126ba97
EC		 835 int uuarn;
836 int err;
837 int i;
f241e749 838 size_t reqlen;
e126ba97
EC		 839
840 if (!dev->ib_active)
841 return ERR_PTR(-EAGAIN);
842
78c0f98c
EC		 843 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
844 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
845 ver = 0;
b368d7cb 846 else if (reqlen >= sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
78c0f98c
EC		 847 ver = 2;
848 else
849 return ERR_PTR(-EINVAL);
850
b368d7cb 851 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 852 if (err)
853 return ERR_PTR(err);
854
b368d7cb 855 if (req.flags)
78c0f98c
EC		 856 return ERR_PTR(-EINVAL);
857
e126ba97
EC		 858 if (req.total_num_uuars > MLX5_MAX_UUARS)
859 return ERR_PTR(-ENOMEM);
860
861 if (req.total_num_uuars == 0)
862 return ERR_PTR(-EINVAL);
863
b368d7cb
MB		 864 if (req.comp_mask)
865 return ERR_PTR(-EOPNOTSUPP);
866
867 if (reqlen > sizeof(req) &&
868 !ib_is_udata_cleared(udata, sizeof(req),
869 udata->inlen - sizeof(req)))
870 return ERR_PTR(-EOPNOTSUPP);
871
c1be5232
EC		 872 req.total_num_uuars = ALIGN(req.total_num_uuars,
873 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 874 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
875 return ERR_PTR(-EINVAL);
876
c1be5232
EC		 877 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
878 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c
SM		 879 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
880 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
881 resp.cache_line_size = L1_CACHE_BYTES;
882 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
883 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
884 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
885 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
886 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
b368d7cb
MB		 887 resp.response_length = min(offsetof(typeof(resp), response_length) +
888 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 889
890 context = kzalloc(sizeof(*context), GFP_KERNEL);
891 if (!context)
892 return ERR_PTR(-ENOMEM);
893
894 uuari = &context->uuari;
895 mutex_init(&uuari->lock);
896 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
897 if (!uars) {
898 err = -ENOMEM;
899 goto out_ctx;
900 }
901
c1be5232 902 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 903 sizeof(*uuari->bitmap),
904 GFP_KERNEL);
905 if (!uuari->bitmap) {
906 err = -ENOMEM;
907 goto out_uar_ctx;
908 }
909 /*
910 * clear all fast path uuars
911 */
c1be5232 912 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 913 uuarn = i & 3;
914 if (uuarn == 2 || uuarn == 3)
915 set_bit(i, uuari->bitmap);
916 }
917
c1be5232 918 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 919 if (!uuari->count) {
920 err = -ENOMEM;
921 goto out_bitmap;
922 }
923
924 for (i = 0; i < num_uars; i++) {
9603b61d 925 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 926 if (err)
927 goto out_count;
928 }
929
b4cfe447
HE		 930#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
931 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
932#endif
933
e126ba97
EC		 934 INIT_LIST_HEAD(&context->db_page_list);
935 mutex_init(&context->db_page_mutex);
936
937 resp.tot_uuars = req.total_num_uuars;
938fe83c 938 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb
MB		 939
940 if (field_avail(typeof(resp), reserved2, udata->outlen))
941 resp.response_length += sizeof(resp.reserved2);
942
943 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
944 resp.comp_mask |=
945 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
946 resp.hca_core_clock_offset =
947 offsetof(struct mlx5_init_seg, internal_timer_h) %
948 PAGE_SIZE;
949 resp.response_length += sizeof(resp.hca_core_clock_offset);
950 }
951
952 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97
EC		 953 if (err)
954 goto out_uars;
955
78c0f98c 956 uuari->ver = ver;
e126ba97
EC		 957 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
958 uuari->uars = uars;
959 uuari->num_uars = num_uars;
960 return &context->ibucontext;
961
962out_uars:
963 for (i--; i >= 0; i--)
9603b61d 964 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 965out_count:
966 kfree(uuari->count);
967
968out_bitmap:
969 kfree(uuari->bitmap);
970
971out_uar_ctx:
972 kfree(uars);
973
974out_ctx:
975 kfree(context);
976 return ERR_PTR(err);
977}
978
979static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
980{
981 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
982 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
983 struct mlx5_uuar_info *uuari = &context->uuari;
984 int i;
985
986 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 987 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 988 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
989 }
990
991 kfree(uuari->count);
992 kfree(uuari->bitmap);
993 kfree(uuari->uars);
994 kfree(context);
995
996 return 0;
997}
998
999static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1000{
9603b61d 1001 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1002}
1003
1004static int get_command(unsigned long offset)
1005{
1006 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1007}
1008
1009static int get_arg(unsigned long offset)
1010{
1011 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1012}
1013
1014static int get_index(unsigned long offset)
1015{
1016 return get_arg(offset);
1017}
1018
1019static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1020{
1021 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1022 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1023 struct mlx5_uuar_info *uuari = &context->uuari;
1024 unsigned long command;
1025 unsigned long idx;
1026 phys_addr_t pfn;
1027
1028 command = get_command(vma->vm_pgoff);
1029 switch (command) {
1030 case MLX5_IB_MMAP_REGULAR_PAGE:
1031 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1032 return -EINVAL;
1033
1034 idx = get_index(vma->vm_pgoff);
1c3ce90d
EC		 1035 if (idx >= uuari->num_uars)
1036 return -EINVAL;
1037
e126ba97
EC		 1038 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1039 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
1040 (unsigned long long)pfn);
1041
e126ba97
EC		 1042 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1043 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1044 PAGE_SIZE, vma->vm_page_prot))
1045 return -EAGAIN;
1046
1047 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
1048 vma->vm_start,
1049 (unsigned long long)pfn << PAGE_SHIFT);
1050 break;
1051
1052 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1053 return -ENOSYS;
1054
d69e3bcf
MB		 1055 case MLX5_IB_MMAP_CORE_CLOCK:
1056 {
1057 phys_addr_t pfn;
1058
1059 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1060 return -EINVAL;
1061
1062 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
1063 return -EPERM;
1064
1065 /* Don't expose to user-space information it shouldn't have */
1066 if (PAGE_SIZE > 4096)
1067 return -EOPNOTSUPP;
1068
1069 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1070 pfn = (dev->mdev->iseg_base +
1071 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1072 PAGE_SHIFT;
1073 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1074 PAGE_SIZE, vma->vm_page_prot))
1075 return -EAGAIN;
1076
1077 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1078 vma->vm_start,
1079 (unsigned long long)pfn << PAGE_SHIFT);
1080 break;
1081 }
1082
e126ba97
EC		 1083 default:
1084 return -EINVAL;
1085 }
1086
1087 return 0;
1088}
1089
e126ba97
EC		 1090static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1091 struct ib_ucontext *context,
1092 struct ib_udata *udata)
1093{
1094 struct mlx5_ib_alloc_pd_resp resp;
1095 struct mlx5_ib_pd *pd;
1096 int err;
1097
1098 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1099 if (!pd)
1100 return ERR_PTR(-ENOMEM);
1101
9603b61d 1102 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1103 if (err) {
1104 kfree(pd);
1105 return ERR_PTR(err);
1106 }
1107
1108 if (context) {
1109 resp.pdn = pd->pdn;
1110 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1111 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1112 kfree(pd);
1113 return ERR_PTR(-EFAULT);
1114 }
e126ba97
EC		 1115 }
1116
1117 return &pd->ibpd;
1118}
1119
1120static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1121{
1122 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1123 struct mlx5_ib_pd *mpd = to_mpd(pd);
1124
9603b61d 1125 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1126 kfree(mpd);
1127
1128 return 0;
1129}
1130
1131static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1132{
1133 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1134 int err;
1135
9603b61d 1136 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1137 if (err)
1138 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1139 ibqp->qp_num, gid->raw);
1140
1141 return err;
1142}
1143
1144static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1145{
1146 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1147 int err;
1148
9603b61d 1149 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1150 if (err)
1151 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1152 ibqp->qp_num, gid->raw);
1153
1154 return err;
1155}
1156
1157static int init_node_data(struct mlx5_ib_dev *dev)
1158{
1b5daf11 1159 int err;
e126ba97 1160
1b5daf11 1161 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 1162 if (err)
1b5daf11 1163 return err;
e126ba97 1164
1b5daf11 1165 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 1166
1b5daf11 1167 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 1168}
1169
1170static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1171 char *buf)
1172{
1173 struct mlx5_ib_dev *dev =
1174 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1175
9603b61d 1176 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 1177}
1178
1179static ssize_t show_reg_pages(struct device *device,
1180 struct device_attribute *attr, char *buf)
1181{
1182 struct mlx5_ib_dev *dev =
1183 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1184
6aec21f6 1185 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 1186}
1187
1188static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1189 char *buf)
1190{
1191 struct mlx5_ib_dev *dev =
1192 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1193 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1194}
1195
1196static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1197 char *buf)
1198{
1199 struct mlx5_ib_dev *dev =
1200 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d
JM		 1201 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1202 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
e126ba97
EC		 1203}
1204
1205static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1206 char *buf)
1207{
1208 struct mlx5_ib_dev *dev =
1209 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1210 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1211}
1212
1213static ssize_t show_board(struct device *device, struct device_attribute *attr,
1214 char *buf)
1215{
1216 struct mlx5_ib_dev *dev =
1217 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1218 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1219 dev->mdev->board_id);
e126ba97
EC		 1220}
1221
1222static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1223static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1224static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1225static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1226static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1227static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1228
1229static struct device_attribute *mlx5_class_attributes[] = {
1230 &dev_attr_hw_rev,
1231 &dev_attr_fw_ver,
1232 &dev_attr_hca_type,
1233 &dev_attr_board_id,
1234 &dev_attr_fw_pages,
1235 &dev_attr_reg_pages,
1236};
1237
9603b61d 1238static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 1239 enum mlx5_dev_event event, unsigned long param)
e126ba97 1240{
9603b61d 1241 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 1242 struct ib_event ibev;
9603b61d 1243
e126ba97
EC		 1244 u8 port = 0;
1245
1246 switch (event) {
1247 case MLX5_DEV_EVENT_SYS_ERROR:
1248 ibdev->ib_active = false;
1249 ibev.event = IB_EVENT_DEVICE_FATAL;
1250 break;
1251
1252 case MLX5_DEV_EVENT_PORT_UP:
1253 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 1254 port = (u8)param;
e126ba97
EC		 1255 break;
1256
1257 case MLX5_DEV_EVENT_PORT_DOWN:
1258 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 1259 port = (u8)param;
e126ba97
EC		 1260 break;
1261
1262 case MLX5_DEV_EVENT_PORT_INITIALIZED:
1263 /* not used by ULPs */
1264 return;
1265
1266 case MLX5_DEV_EVENT_LID_CHANGE:
1267 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 1268 port = (u8)param;
e126ba97
EC		 1269 break;
1270
1271 case MLX5_DEV_EVENT_PKEY_CHANGE:
1272 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 1273 port = (u8)param;
e126ba97
EC		 1274 break;
1275
1276 case MLX5_DEV_EVENT_GUID_CHANGE:
1277 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 1278 port = (u8)param;
e126ba97
EC		 1279 break;
1280
1281 case MLX5_DEV_EVENT_CLIENT_REREG:
1282 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 1283 port = (u8)param;
e126ba97
EC		 1284 break;
1285 }
1286
1287 ibev.device = &ibdev->ib_dev;
1288 ibev.element.port_num = port;
1289
a0c84c32
EC		 1290 if (port < 1 || port > ibdev->num_ports) {
1291 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1292 return;
1293 }
1294
e126ba97
EC		 1295 if (ibdev->ib_active)
1296 ib_dispatch_event(&ibev);
1297}
1298
1299static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1300{
1301 int port;
1302
938fe83c 1303 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 1304 mlx5_query_ext_port_caps(dev, port);
1305}
1306
1307static int get_port_caps(struct mlx5_ib_dev *dev)
1308{
1309 struct ib_device_attr *dprops = NULL;
1310 struct ib_port_attr *pprops = NULL;
f614fc15 1311 int err = -ENOMEM;
e126ba97 1312 int port;
2528e33e 1313 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 1314
1315 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1316 if (!pprops)
1317 goto out;
1318
1319 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1320 if (!dprops)
1321 goto out;
1322
2528e33e 1323 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 1324 if (err) {
1325 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1326 goto out;
1327 }
1328
938fe83c 1329 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 1330 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1331 if (err) {
938fe83c
SM		 1332 mlx5_ib_warn(dev, "query_port %d failed %d\n",
1333 port, err);
e126ba97
EC		 1334 break;
1335 }
938fe83c
SM		 1336 dev->mdev->port_caps[port - 1].pkey_table_len =
1337 dprops->max_pkeys;
1338 dev->mdev->port_caps[port - 1].gid_table_len =
1339 pprops->gid_tbl_len;
e126ba97
EC		 1340 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1341 dprops->max_pkeys, pprops->gid_tbl_len);
1342 }
1343
1344out:
1345 kfree(pprops);
1346 kfree(dprops);
1347
1348 return err;
1349}
1350
1351static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1352{
1353 int err;
1354
1355 err = mlx5_mr_cache_cleanup(dev);
1356 if (err)
1357 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1358
1359 mlx5_ib_destroy_qp(dev->umrc.qp);
1360 ib_destroy_cq(dev->umrc.cq);
e126ba97
EC		 1361 ib_dealloc_pd(dev->umrc.pd);
1362}
1363
1364enum {
1365 MAX_UMR_WR = 128,
1366};
1367
1368static int create_umr_res(struct mlx5_ib_dev *dev)
1369{
1370 struct ib_qp_init_attr *init_attr = NULL;
1371 struct ib_qp_attr *attr = NULL;
1372 struct ib_pd *pd;
1373 struct ib_cq *cq;
1374 struct ib_qp *qp;
8e37210b 1375 struct ib_cq_init_attr cq_attr = {};
e126ba97
EC		 1376 int ret;
1377
1378 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1379 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1380 if (!attr || !init_attr) {
1381 ret = -ENOMEM;
1382 goto error_0;
1383 }
1384
1385 pd = ib_alloc_pd(&dev->ib_dev);
1386 if (IS_ERR(pd)) {
1387 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1388 ret = PTR_ERR(pd);
1389 goto error_0;
1390 }
1391
8e37210b
MB		 1392 cq_attr.cqe = 128;
1393 cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL,
1394 &cq_attr);
e126ba97
EC		 1395 if (IS_ERR(cq)) {
1396 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1397 ret = PTR_ERR(cq);
1398 goto error_2;
1399 }
1400 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
1401
1402 init_attr->send_cq = cq;
1403 init_attr->recv_cq = cq;
1404 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1405 init_attr->cap.max_send_wr = MAX_UMR_WR;
1406 init_attr->cap.max_send_sge = 1;
1407 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1408 init_attr->port_num = 1;
1409 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1410 if (IS_ERR(qp)) {
1411 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1412 ret = PTR_ERR(qp);
1413 goto error_3;
1414 }
1415 qp->device = &dev->ib_dev;
1416 qp->real_qp = qp;
1417 qp->uobject = NULL;
1418 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1419
1420 attr->qp_state = IB_QPS_INIT;
1421 attr->port_num = 1;
1422 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1423 IB_QP_PORT, NULL);
1424 if (ret) {
1425 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1426 goto error_4;
1427 }
1428
1429 memset(attr, 0, sizeof(*attr));
1430 attr->qp_state = IB_QPS_RTR;
1431 attr->path_mtu = IB_MTU_256;
1432
1433 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1434 if (ret) {
1435 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1436 goto error_4;
1437 }
1438
1439 memset(attr, 0, sizeof(*attr));
1440 attr->qp_state = IB_QPS_RTS;
1441 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1442 if (ret) {
1443 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1444 goto error_4;
1445 }
1446
1447 dev->umrc.qp = qp;
1448 dev->umrc.cq = cq;
e126ba97
EC		 1449 dev->umrc.pd = pd;
1450
1451 sema_init(&dev->umrc.sem, MAX_UMR_WR);
1452 ret = mlx5_mr_cache_init(dev);
1453 if (ret) {
1454 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1455 goto error_4;
1456 }
1457
1458 kfree(attr);
1459 kfree(init_attr);
1460
1461 return 0;
1462
1463error_4:
1464 mlx5_ib_destroy_qp(qp);
1465
1466error_3:
1467 ib_destroy_cq(cq);
1468
1469error_2:
e126ba97
EC		 1470 ib_dealloc_pd(pd);
1471
1472error_0:
1473 kfree(attr);
1474 kfree(init_attr);
1475 return ret;
1476}
1477
1478static int create_dev_resources(struct mlx5_ib_resources *devr)
1479{
1480 struct ib_srq_init_attr attr;
1481 struct mlx5_ib_dev *dev;
bcf4c1ea 1482 struct ib_cq_init_attr cq_attr = {.cqe = 1};
e126ba97
EC		 1483 int ret = 0;
1484
1485 dev = container_of(devr, struct mlx5_ib_dev, devr);
1486
1487 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
1488 if (IS_ERR(devr->p0)) {
1489 ret = PTR_ERR(devr->p0);
1490 goto error0;
1491 }
1492 devr->p0->device = &dev->ib_dev;
1493 devr->p0->uobject = NULL;
1494 atomic_set(&devr->p0->usecnt, 0);
1495
bcf4c1ea 1496 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 1497 if (IS_ERR(devr->c0)) {
1498 ret = PTR_ERR(devr->c0);
1499 goto error1;
1500 }
1501 devr->c0->device = &dev->ib_dev;
1502 devr->c0->uobject = NULL;
1503 devr->c0->comp_handler = NULL;
1504 devr->c0->event_handler = NULL;
1505 devr->c0->cq_context = NULL;
1506 atomic_set(&devr->c0->usecnt, 0);
1507
1508 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1509 if (IS_ERR(devr->x0)) {
1510 ret = PTR_ERR(devr->x0);
1511 goto error2;
1512 }
1513 devr->x0->device = &dev->ib_dev;
1514 devr->x0->inode = NULL;
1515 atomic_set(&devr->x0->usecnt, 0);
1516 mutex_init(&devr->x0->tgt_qp_mutex);
1517 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
1518
1519 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1520 if (IS_ERR(devr->x1)) {
1521 ret = PTR_ERR(devr->x1);
1522 goto error3;
1523 }
1524 devr->x1->device = &dev->ib_dev;
1525 devr->x1->inode = NULL;
1526 atomic_set(&devr->x1->usecnt, 0);
1527 mutex_init(&devr->x1->tgt_qp_mutex);
1528 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
1529
1530 memset(&attr, 0, sizeof(attr));
1531 attr.attr.max_sge = 1;
1532 attr.attr.max_wr = 1;
1533 attr.srq_type = IB_SRQT_XRC;
1534 attr.ext.xrc.cq = devr->c0;
1535 attr.ext.xrc.xrcd = devr->x0;
1536
1537 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1538 if (IS_ERR(devr->s0)) {
1539 ret = PTR_ERR(devr->s0);
1540 goto error4;
1541 }
1542 devr->s0->device = &dev->ib_dev;
1543 devr->s0->pd = devr->p0;
1544 devr->s0->uobject = NULL;
1545 devr->s0->event_handler = NULL;
1546 devr->s0->srq_context = NULL;
1547 devr->s0->srq_type = IB_SRQT_XRC;
1548 devr->s0->ext.xrc.xrcd = devr->x0;
1549 devr->s0->ext.xrc.cq = devr->c0;
1550 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1551 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
1552 atomic_inc(&devr->p0->usecnt);
1553 atomic_set(&devr->s0->usecnt, 0);
1554
4aa17b28
HA		 1555 memset(&attr, 0, sizeof(attr));
1556 attr.attr.max_sge = 1;
1557 attr.attr.max_wr = 1;
1558 attr.srq_type = IB_SRQT_BASIC;
1559 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1560 if (IS_ERR(devr->s1)) {
1561 ret = PTR_ERR(devr->s1);
1562 goto error5;
1563 }
1564 devr->s1->device = &dev->ib_dev;
1565 devr->s1->pd = devr->p0;
1566 devr->s1->uobject = NULL;
1567 devr->s1->event_handler = NULL;
1568 devr->s1->srq_context = NULL;
1569 devr->s1->srq_type = IB_SRQT_BASIC;
1570 devr->s1->ext.xrc.cq = devr->c0;
1571 atomic_inc(&devr->p0->usecnt);
1572 atomic_set(&devr->s0->usecnt, 0);
1573
e126ba97
EC		 1574 return 0;
1575
4aa17b28
HA		 1576error5:
1577 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 1578error4:
1579 mlx5_ib_dealloc_xrcd(devr->x1);
1580error3:
1581 mlx5_ib_dealloc_xrcd(devr->x0);
1582error2:
1583 mlx5_ib_destroy_cq(devr->c0);
1584error1:
1585 mlx5_ib_dealloc_pd(devr->p0);
1586error0:
1587 return ret;
1588}
1589
1590static void destroy_dev_resources(struct mlx5_ib_resources *devr)
1591{
4aa17b28 1592 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 1593 mlx5_ib_destroy_srq(devr->s0);
1594 mlx5_ib_dealloc_xrcd(devr->x0);
1595 mlx5_ib_dealloc_xrcd(devr->x1);
1596 mlx5_ib_destroy_cq(devr->c0);
1597 mlx5_ib_dealloc_pd(devr->p0);
1598}
1599
e53505a8
AS		 1600static u32 get_core_cap_flags(struct ib_device *ibdev)
1601{
1602 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1603 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
1604 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
1605 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
1606 u32 ret = 0;
1607
1608 if (ll == IB_LINK_LAYER_INFINIBAND)
1609 return RDMA_CORE_PORT_IBA_IB;
1610
1611 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
1612 return 0;
1613
1614 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
1615 return 0;
1616
1617 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
1618 ret |= RDMA_CORE_PORT_IBA_ROCE;
1619
1620 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
1621 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
1622
1623 return ret;
1624}
1625
7738613e
IW		 1626static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
1627 struct ib_port_immutable *immutable)
1628{
1629 struct ib_port_attr attr;
1630 int err;
1631
1632 err = mlx5_ib_query_port(ibdev, port_num, &attr);
1633 if (err)
1634 return err;
1635
1636 immutable->pkey_tbl_len = attr.pkey_tbl_len;
1637 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 1638 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 1639 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 1640
1641 return 0;
1642}
1643
fc24fc5e
AS		 1644static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
1645{
e53505a8
AS		 1646 int err;
1647
fc24fc5e 1648 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8
AS		 1649 err = register_netdevice_notifier(&dev->roce.nb);
1650 if (err)
1651 return err;
1652
1653 err = mlx5_nic_vport_enable_roce(dev->mdev);
1654 if (err)
1655 goto err_unregister_netdevice_notifier;
1656
1657 return 0;
1658
1659err_unregister_netdevice_notifier:
1660 unregister_netdevice_notifier(&dev->roce.nb);
1661 return err;
fc24fc5e
AS		 1662}
1663
1664static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
1665{
e53505a8 1666 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 1667 unregister_netdevice_notifier(&dev->roce.nb);
1668}
1669
9603b61d 1670static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 1671{
e126ba97 1672 struct mlx5_ib_dev *dev;
ebd61f68
AS		 1673 enum rdma_link_layer ll;
1674 int port_type_cap;
e126ba97
EC		 1675 int err;
1676 int i;
1677
ebd61f68
AS		 1678 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
1679 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
1680
e53505a8 1681 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 1682 return NULL;
1683
e126ba97
EC		 1684 printk_once(KERN_INFO "%s", mlx5_version);
1685
1686 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
1687 if (!dev)
9603b61d 1688 return NULL;
e126ba97 1689
9603b61d 1690 dev->mdev = mdev;
e126ba97 1691
fc24fc5e 1692 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 1693 err = get_port_caps(dev);
1694 if (err)
9603b61d 1695 goto err_dealloc;
e126ba97 1696
1b5daf11
MD		 1697 if (mlx5_use_mad_ifc(dev))
1698 get_ext_port_caps(dev);
e126ba97 1699
e126ba97
EC		 1700 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
1701
1702 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
1703 dev->ib_dev.owner = THIS_MODULE;
1704 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 1705 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 1706 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 1707 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 1708 dev->ib_dev.num_comp_vectors =
1709 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 1710 dev->ib_dev.dma_device = &mdev->pdev->dev;
1711
1712 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
1713 dev->ib_dev.uverbs_cmd_mask =
1714 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
1715 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
1716 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
1717 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
1718 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
1719 (1ull << IB_USER_VERBS_CMD_REG_MR) |
1720 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
1721 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
1722 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
1723 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
1724 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
1725 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
1726 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
1727 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
1728 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
1729 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
1730 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
1731 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
1732 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
1733 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
1734 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
1735 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
1736 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a
HE		 1737 dev->ib_dev.uverbs_ex_cmd_mask =
1738 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE);
e126ba97
EC		 1739
1740 dev->ib_dev.query_device = mlx5_ib_query_device;
1741 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 1742 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 1743 if (ll == IB_LINK_LAYER_ETHERNET)
1744 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 1745 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 1746 dev->ib_dev.add_gid = mlx5_ib_add_gid;
1747 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 1748 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
1749 dev->ib_dev.modify_device = mlx5_ib_modify_device;
1750 dev->ib_dev.modify_port = mlx5_ib_modify_port;
1751 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
1752 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
1753 dev->ib_dev.mmap = mlx5_ib_mmap;
1754 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
1755 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
1756 dev->ib_dev.create_ah = mlx5_ib_create_ah;
1757 dev->ib_dev.query_ah = mlx5_ib_query_ah;
1758 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
1759 dev->ib_dev.create_srq = mlx5_ib_create_srq;
1760 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
1761 dev->ib_dev.query_srq = mlx5_ib_query_srq;
1762 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
1763 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
1764 dev->ib_dev.create_qp = mlx5_ib_create_qp;
1765 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
1766 dev->ib_dev.query_qp = mlx5_ib_query_qp;
1767 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
1768 dev->ib_dev.post_send = mlx5_ib_post_send;
1769 dev->ib_dev.post_recv = mlx5_ib_post_recv;
1770 dev->ib_dev.create_cq = mlx5_ib_create_cq;
1771 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
1772 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
1773 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
1774 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
1775 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
1776 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
1777 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
1778 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
1779 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
1780 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
1781 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 1782 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 1783 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 1784 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 1785 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
e126ba97 1786
938fe83c 1787 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 1788
938fe83c 1789 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 1790 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
1791 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
1792 dev->ib_dev.uverbs_cmd_mask |=
1793 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
1794 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
1795 }
1796
1797 err = init_node_data(dev);
1798 if (err)
233d05d2 1799 goto err_dealloc;
e126ba97
EC		 1800
1801 mutex_init(&dev->cap_mask_mutex);
e126ba97 1802
fc24fc5e
AS		 1803 if (ll == IB_LINK_LAYER_ETHERNET) {
1804 err = mlx5_enable_roce(dev);
1805 if (err)
1806 goto err_dealloc;
1807 }
1808
e126ba97
EC		 1809 err = create_dev_resources(&dev->devr);
1810 if (err)
fc24fc5e 1811 goto err_disable_roce;
e126ba97 1812
6aec21f6 1813 err = mlx5_ib_odp_init_one(dev);
281d1a92 1814 if (err)
e126ba97
EC		 1815 goto err_rsrc;
1816
6aec21f6
HE		 1817 err = ib_register_device(&dev->ib_dev, NULL);
1818 if (err)
1819 goto err_odp;
1820
e126ba97
EC		 1821 err = create_umr_res(dev);
1822 if (err)
1823 goto err_dev;
1824
1825 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 1826 err = device_create_file(&dev->ib_dev.dev,
1827 mlx5_class_attributes[i]);
1828 if (err)
e126ba97
EC		 1829 goto err_umrc;
1830 }
1831
1832 dev->ib_active = true;
1833
9603b61d 1834 return dev;
e126ba97
EC		 1835
1836err_umrc:
1837 destroy_umrc_res(dev);
1838
1839err_dev:
1840 ib_unregister_device(&dev->ib_dev);
1841
6aec21f6
HE		 1842err_odp:
1843 mlx5_ib_odp_remove_one(dev);
1844
e126ba97
EC		 1845err_rsrc:
1846 destroy_dev_resources(&dev->devr);
1847
fc24fc5e
AS		 1848err_disable_roce:
1849 if (ll == IB_LINK_LAYER_ETHERNET)
1850 mlx5_disable_roce(dev);
1851
9603b61d 1852err_dealloc:
e126ba97
EC		 1853 ib_dealloc_device((struct ib_device *)dev);
1854
9603b61d 1855 return NULL;
e126ba97
EC		 1856}
1857
9603b61d 1858static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 1859{
9603b61d 1860 struct mlx5_ib_dev *dev = context;
fc24fc5e 1861 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 1862
e126ba97 1863 ib_unregister_device(&dev->ib_dev);
eefd56e5 1864 destroy_umrc_res(dev);
6aec21f6 1865 mlx5_ib_odp_remove_one(dev);
e126ba97 1866 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 1867 if (ll == IB_LINK_LAYER_ETHERNET)
1868 mlx5_disable_roce(dev);
e126ba97
EC		 1869 ib_dealloc_device(&dev->ib_dev);
1870}
1871
9603b61d
JM		 1872static struct mlx5_interface mlx5_ib_interface = {
1873 .add = mlx5_ib_add,
1874 .remove = mlx5_ib_remove,
1875 .event = mlx5_ib_event,
64613d94 1876 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 1877};
1878
1879static int __init mlx5_ib_init(void)
1880{
6aec21f6
HE		 1881 int err;
1882
9603b61d
JM		 1883 if (deprecated_prof_sel != 2)
1884 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
1885
6aec21f6
HE		 1886 err = mlx5_ib_odp_init();
1887 if (err)
1888 return err;
1889
1890 err = mlx5_register_interface(&mlx5_ib_interface);
1891 if (err)
1892 goto clean_odp;
1893
1894 return err;
1895
1896clean_odp:
1897 mlx5_ib_odp_cleanup();
1898 return err;
e126ba97
EC		 1899}
1900
1901static void __exit mlx5_ib_cleanup(void)
1902{
9603b61d 1903 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 1904 mlx5_ib_odp_cleanup();
e126ba97
EC		 1905}
1906
1907module_init(mlx5_ib_init);
1908module_exit(mlx5_ib_cleanup);
Linux kernel - Deliverables
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