[deliverable/linux.git] / drivers / infiniband / hw / qib / qib_qp.c

/*
 * Copyright (c) 2012, 2013 Intel Corporation.  All rights reserved.
 * Copyright (c) 2006 - 2012 QLogic Corporation.  * All rights reserved.
 * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/err.h>
#include <linux/vmalloc.h>
#include <rdma/rdma_vt.h>
#ifdef CONFIG_DEBUG_FS
#include <linux/seq_file.h>
#endif

#include "qib.h"

/*
 * mask field which was present in now deleted qib_qpn_table
 * is not present in rvt_qpn_table. Defining the same field
 * as qpt_mask here instead of adding the mask field to
 * rvt_qpn_table.
 */
u16 qpt_mask;

static inline unsigned mk_qpn(struct rvt_qpn_table *qpt,
			      struct rvt_qpn_map *map, unsigned off)
{
	return (map - qpt->map) * RVT_BITS_PER_PAGE + off;
}

static inline unsigned find_next_offset(struct rvt_qpn_table *qpt,
					struct rvt_qpn_map *map, unsigned off,
					unsigned n)
{
	if (qpt_mask) {
		off++;
		if (((off & qpt_mask) >> 1) >= n)
			off = (off | qpt_mask) + 2;
	} else {
		off = find_next_zero_bit(map->page, RVT_BITS_PER_PAGE, off);
	}
	return off;
}

/*
 * Convert the AETH credit code into the number of credits.
 */
static u32 credit_table[31] = {
	0,                      /* 0 */
	1,                      /* 1 */
	2,                      /* 2 */
	3,                      /* 3 */
	4,                      /* 4 */
	6,                      /* 5 */
	8,                      /* 6 */
	12,                     /* 7 */
	16,                     /* 8 */
	24,                     /* 9 */
	32,                     /* A */
	48,                     /* B */
	64,                     /* C */
	96,                     /* D */
	128,                    /* E */
	192,                    /* F */
	256,                    /* 10 */
	384,                    /* 11 */
	512,                    /* 12 */
	768,                    /* 13 */
	1024,                   /* 14 */
	1536,                   /* 15 */
	2048,                   /* 16 */
	3072,                   /* 17 */
	4096,                   /* 18 */
	6144,                   /* 19 */
	8192,                   /* 1A */
	12288,                  /* 1B */
	16384,                  /* 1C */
	24576,                  /* 1D */
	32768                   /* 1E */
};

const struct rvt_operation_params qib_post_parms[RVT_OPERATION_MAX] = {
[IB_WR_RDMA_WRITE] = {
	.length = sizeof(struct ib_rdma_wr),
	.qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
},

[IB_WR_RDMA_READ] = {
	.length = sizeof(struct ib_rdma_wr),
	.qpt_support = BIT(IB_QPT_RC),
	.flags = RVT_OPERATION_ATOMIC,
},

[IB_WR_ATOMIC_CMP_AND_SWP] = {
	.length = sizeof(struct ib_atomic_wr),
	.qpt_support = BIT(IB_QPT_RC),
	.flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE,
},

[IB_WR_ATOMIC_FETCH_AND_ADD] = {
	.length = sizeof(struct ib_atomic_wr),
	.qpt_support = BIT(IB_QPT_RC),
	.flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE,
},

[IB_WR_RDMA_WRITE_WITH_IMM] = {
	.length = sizeof(struct ib_rdma_wr),
	.qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
},

[IB_WR_SEND] = {
	.length = sizeof(struct ib_send_wr),
	.qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) |
		       BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
},

[IB_WR_SEND_WITH_IMM] = {
	.length = sizeof(struct ib_send_wr),
	.qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) |
		       BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
},

};

static void get_map_page(struct rvt_qpn_table *qpt, struct rvt_qpn_map *map,
			 gfp_t gfp)
{
	unsigned long page = get_zeroed_page(gfp);

	/*
	 * Free the page if someone raced with us installing it.
	 */

	spin_lock(&qpt->lock);
	if (map->page)
		free_page(page);
	else
		map->page = (void *)page;
	spin_unlock(&qpt->lock);
}

/*
 * Allocate the next available QPN or
 * zero/one for QP type IB_QPT_SMI/IB_QPT_GSI.
 */
int qib_alloc_qpn(struct rvt_dev_info *rdi, struct rvt_qpn_table *qpt,
		  enum ib_qp_type type, u8 port, gfp_t gfp)
{
	u32 i, offset, max_scan, qpn;
	struct rvt_qpn_map *map;
	u32 ret;
	struct qib_ibdev *verbs_dev = container_of(rdi, struct qib_ibdev, rdi);
	struct qib_devdata *dd = container_of(verbs_dev, struct qib_devdata,
					      verbs_dev);

	if (type == IB_QPT_SMI || type == IB_QPT_GSI) {
		unsigned n;

		ret = type == IB_QPT_GSI;
		n = 1 << (ret + 2 * (port - 1));
		spin_lock(&qpt->lock);
		if (qpt->flags & n)
			ret = -EINVAL;
		else
			qpt->flags |= n;
		spin_unlock(&qpt->lock);
		goto bail;
	}

	qpn = qpt->last + 2;
	if (qpn >= RVT_QPN_MAX)
		qpn = 2;
	if (qpt_mask && ((qpn & qpt_mask) >> 1) >= dd->n_krcv_queues)
		qpn = (qpn | qpt_mask) + 2;
	offset = qpn & RVT_BITS_PER_PAGE_MASK;
	map = &qpt->map[qpn / RVT_BITS_PER_PAGE];
	max_scan = qpt->nmaps - !offset;
	for (i = 0;;) {
		if (unlikely(!map->page)) {
			get_map_page(qpt, map, gfp);
			if (unlikely(!map->page))
				break;
		}
		do {
			if (!test_and_set_bit(offset, map->page)) {
				qpt->last = qpn;
				ret = qpn;
				goto bail;
			}
			offset = find_next_offset(qpt, map, offset,
				dd->n_krcv_queues);
			qpn = mk_qpn(qpt, map, offset);
			/*
			 * This test differs from alloc_pidmap().
			 * If find_next_offset() does find a zero
			 * bit, we don't need to check for QPN
			 * wrapping around past our starting QPN.
			 * We just need to be sure we don't loop
			 * forever.
			 */
		} while (offset < RVT_BITS_PER_PAGE && qpn < RVT_QPN_MAX);
		/*
		 * In order to keep the number of pages allocated to a
		 * minimum, we scan the all existing pages before increasing
		 * the size of the bitmap table.
		 */
		if (++i > max_scan) {
			if (qpt->nmaps == RVT_QPNMAP_ENTRIES)
				break;
			map = &qpt->map[qpt->nmaps++];
			offset = 0;
		} else if (map < &qpt->map[qpt->nmaps]) {
			++map;
			offset = 0;
		} else {
			map = &qpt->map[0];
			offset = 2;
		}
		qpn = mk_qpn(qpt, map, offset);
	}

	ret = -ENOMEM;

bail:
	return ret;
}

/**
 * qib_free_all_qps - check for QPs still in use
 */
unsigned qib_free_all_qps(struct rvt_dev_info *rdi)
{
	struct qib_ibdev *verbs_dev = container_of(rdi, struct qib_ibdev, rdi);
	struct qib_devdata *dd = container_of(verbs_dev, struct qib_devdata,
					      verbs_dev);
	unsigned n, qp_inuse = 0;

	for (n = 0; n < dd->num_pports; n++) {
		struct qib_ibport *ibp = &dd->pport[n].ibport_data;

		rcu_read_lock();
		if (rcu_dereference(ibp->rvp.qp[0]))
			qp_inuse++;
		if (rcu_dereference(ibp->rvp.qp[1]))
			qp_inuse++;
		rcu_read_unlock();
	}
	return qp_inuse;
}

void qib_notify_qp_reset(struct rvt_qp *qp)
{
	struct qib_qp_priv *priv = qp->priv;

	atomic_set(&priv->s_dma_busy, 0);
}

void qib_notify_error_qp(struct rvt_qp *qp)
{
	struct qib_qp_priv *priv = qp->priv;
	struct qib_ibdev *dev = to_idev(qp->ibqp.device);

	spin_lock(&dev->rdi.pending_lock);
	if (!list_empty(&priv->iowait) && !(qp->s_flags & RVT_S_BUSY)) {
		qp->s_flags &= ~RVT_S_ANY_WAIT_IO;
		list_del_init(&priv->iowait);
	}
	spin_unlock(&dev->rdi.pending_lock);

	if (!(qp->s_flags & RVT_S_BUSY)) {
		qp->s_hdrwords = 0;
		if (qp->s_rdma_mr) {
			rvt_put_mr(qp->s_rdma_mr);
			qp->s_rdma_mr = NULL;
		}
		if (priv->s_tx) {
			qib_put_txreq(priv->s_tx);
			priv->s_tx = NULL;
		}
	}
}

static int mtu_to_enum(u32 mtu)
{
	int enum_mtu;

	switch (mtu) {
	case 4096:
		enum_mtu = IB_MTU_4096;
		break;
	case 2048:
		enum_mtu = IB_MTU_2048;
		break;
	case 1024:
		enum_mtu = IB_MTU_1024;
		break;
	case 512:
		enum_mtu = IB_MTU_512;
		break;
	case 256:
		enum_mtu = IB_MTU_256;
		break;
	default:
		enum_mtu = IB_MTU_2048;
	}
	return enum_mtu;
}

int qib_get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp,
			   struct ib_qp_attr *attr)
{
	int mtu, pmtu, pidx = qp->port_num - 1;
	struct qib_ibdev *verbs_dev = container_of(rdi, struct qib_ibdev, rdi);
	struct qib_devdata *dd = container_of(verbs_dev, struct qib_devdata,
					      verbs_dev);
	mtu = ib_mtu_enum_to_int(attr->path_mtu);
	if (mtu == -1)
		return -EINVAL;

	if (mtu > dd->pport[pidx].ibmtu)
		pmtu = mtu_to_enum(dd->pport[pidx].ibmtu);
	else
		pmtu = attr->path_mtu;
	return pmtu;
}

int qib_mtu_to_path_mtu(u32 mtu)
{
	return mtu_to_enum(mtu);
}

u32 qib_mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu)
{
	return ib_mtu_enum_to_int(pmtu);
}

/**
 * qib_compute_aeth - compute the AETH (syndrome + MSN)
 * @qp: the queue pair to compute the AETH for
 *
 * Returns the AETH.
 */
__be32 qib_compute_aeth(struct rvt_qp *qp)
{
	u32 aeth = qp->r_msn & QIB_MSN_MASK;

	if (qp->ibqp.srq) {
		/*
		 * Shared receive queues don't generate credits.
		 * Set the credit field to the invalid value.
		 */
		aeth |= QIB_AETH_CREDIT_INVAL << QIB_AETH_CREDIT_SHIFT;
	} else {
		u32 min, max, x;
		u32 credits;
		struct rvt_rwq *wq = qp->r_rq.wq;
		u32 head;
		u32 tail;

		/* sanity check pointers before trusting them */
		head = wq->head;
		if (head >= qp->r_rq.size)
			head = 0;
		tail = wq->tail;
		if (tail >= qp->r_rq.size)
			tail = 0;
		/*
		 * Compute the number of credits available (RWQEs).
		 * XXX Not holding the r_rq.lock here so there is a small
		 * chance that the pair of reads are not atomic.
		 */
		credits = head - tail;
		if ((int)credits < 0)
			credits += qp->r_rq.size;
		/*
		 * Binary search the credit table to find the code to
		 * use.
		 */
		min = 0;
		max = 31;
		for (;;) {
			x = (min + max) / 2;
			if (credit_table[x] == credits)
				break;
			if (credit_table[x] > credits)
				max = x;
			else if (min == x)
				break;
			else
				min = x;
		}
		aeth |= x << QIB_AETH_CREDIT_SHIFT;
	}
	return cpu_to_be32(aeth);
}

void *qib_qp_priv_alloc(struct rvt_dev_info *rdi, struct rvt_qp *qp, gfp_t gfp)
{
	struct qib_qp_priv *priv;

	priv = kzalloc(sizeof(*priv), gfp);
	if (!priv)
		return ERR_PTR(-ENOMEM);
	priv->owner = qp;

	priv->s_hdr = kzalloc(sizeof(*priv->s_hdr), gfp);
	if (!priv->s_hdr) {
		kfree(priv);
		return ERR_PTR(-ENOMEM);
	}
	init_waitqueue_head(&priv->wait_dma);
	INIT_WORK(&priv->s_work, _qib_do_send);
	INIT_LIST_HEAD(&priv->iowait);

	return priv;
}

void qib_qp_priv_free(struct rvt_dev_info *rdi, struct rvt_qp *qp)
{
	struct qib_qp_priv *priv = qp->priv;

	kfree(priv->s_hdr);
	kfree(priv);
}

void qib_stop_send_queue(struct rvt_qp *qp)
{
	struct qib_qp_priv *priv = qp->priv;

	cancel_work_sync(&priv->s_work);
	del_timer_sync(&qp->s_timer);
}

void qib_quiesce_qp(struct rvt_qp *qp)
{
	struct qib_qp_priv *priv = qp->priv;

	wait_event(priv->wait_dma, !atomic_read(&priv->s_dma_busy));
	if (priv->s_tx) {
		qib_put_txreq(priv->s_tx);
		priv->s_tx = NULL;
	}
}

void qib_flush_qp_waiters(struct rvt_qp *qp)
{
	struct qib_qp_priv *priv = qp->priv;
	struct qib_ibdev *dev = to_idev(qp->ibqp.device);

	spin_lock(&dev->rdi.pending_lock);
	if (!list_empty(&priv->iowait))
		list_del_init(&priv->iowait);
	spin_unlock(&dev->rdi.pending_lock);
}

/**
 * qib_get_credit - flush the send work queue of a QP
 * @qp: the qp who's send work queue to flush
 * @aeth: the Acknowledge Extended Transport Header
 *
 * The QP s_lock should be held.
 */
void qib_get_credit(struct rvt_qp *qp, u32 aeth)
{
	u32 credit = (aeth >> QIB_AETH_CREDIT_SHIFT) & QIB_AETH_CREDIT_MASK;

	/*
	 * If the credit is invalid, we can send
	 * as many packets as we like.  Otherwise, we have to
	 * honor the credit field.
	 */
	if (credit == QIB_AETH_CREDIT_INVAL) {
		if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT)) {
			qp->s_flags |= RVT_S_UNLIMITED_CREDIT;
			if (qp->s_flags & RVT_S_WAIT_SSN_CREDIT) {
				qp->s_flags &= ~RVT_S_WAIT_SSN_CREDIT;
				qib_schedule_send(qp);
			}
		}
	} else if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT)) {
		/* Compute new LSN (i.e., MSN + credit) */
		credit = (aeth + credit_table[credit]) & QIB_MSN_MASK;
		if (qib_cmp24(credit, qp->s_lsn) > 0) {
			qp->s_lsn = credit;
			if (qp->s_flags & RVT_S_WAIT_SSN_CREDIT) {
				qp->s_flags &= ~RVT_S_WAIT_SSN_CREDIT;
				qib_schedule_send(qp);
			}
		}
	}
}

/**
 * qib_check_send_wqe - validate wr/wqe
 * @qp - The qp
 * @wqe - The built wqe
 *
 * validate wr/wqe.  This is called
 * prior to inserting the wqe into
 * the ring but after the wqe has been
 * setup.
 *
 * Returns 1 to force direct progress, 0 otherwise, -EINVAL on failure
 */
int qib_check_send_wqe(struct rvt_qp *qp,
		       struct rvt_swqe *wqe)
{
	struct rvt_ah *ah;
	int ret = 0;

	switch (qp->ibqp.qp_type) {
	case IB_QPT_RC:
	case IB_QPT_UC:
		if (wqe->length > 0x80000000U)
			return -EINVAL;
		break;
	case IB_QPT_SMI:
	case IB_QPT_GSI:
	case IB_QPT_UD:
		ah = ibah_to_rvtah(wqe->ud_wr.ah);
		if (wqe->length > (1 << ah->log_pmtu))
			return -EINVAL;
		/* progress hint */
		ret = 1;
		break;
	default:
		break;
	}
	return ret;
}

#ifdef CONFIG_DEBUG_FS

struct qib_qp_iter {
	struct qib_ibdev *dev;
	struct rvt_qp *qp;
	int n;
};

struct qib_qp_iter *qib_qp_iter_init(struct qib_ibdev *dev)
{
	struct qib_qp_iter *iter;

	iter = kzalloc(sizeof(*iter), GFP_KERNEL);
	if (!iter)
		return NULL;

	iter->dev = dev;

	return iter;
}

int qib_qp_iter_next(struct qib_qp_iter *iter)
{
	struct qib_ibdev *dev = iter->dev;
	int n = iter->n;
	int ret = 1;
	struct rvt_qp *pqp = iter->qp;
	struct rvt_qp *qp;

	for (; n < dev->rdi.qp_dev->qp_table_size; n++) {
		if (pqp)
			qp = rcu_dereference(pqp->next);
		else
			qp = rcu_dereference(dev->rdi.qp_dev->qp_table[n]);
		pqp = qp;
		if (qp) {
			iter->qp = qp;
			iter->n = n;
			return 0;
		}
	}
	return ret;
}

static const char * const qp_type_str[] = {
	"SMI", "GSI", "RC", "UC", "UD",
};

void qib_qp_iter_print(struct seq_file *s, struct qib_qp_iter *iter)
{
	struct rvt_swqe *wqe;
	struct rvt_qp *qp = iter->qp;
	struct qib_qp_priv *priv = qp->priv;

	wqe = rvt_get_swqe_ptr(qp, qp->s_last);
	seq_printf(s,
		   "N %d QP%u %s %u %u %u f=%x %u %u %u %u %u PSN %x %x %x %x %x (%u %u %u %u %u %u) QP%u LID %x\n",
		   iter->n,
		   qp->ibqp.qp_num,
		   qp_type_str[qp->ibqp.qp_type],
		   qp->state,
		   wqe->wr.opcode,
		   qp->s_hdrwords,
		   qp->s_flags,
		   atomic_read(&priv->s_dma_busy),
		   !list_empty(&priv->iowait),
		   qp->timeout,
		   wqe->ssn,
		   qp->s_lsn,
		   qp->s_last_psn,
		   qp->s_psn, qp->s_next_psn,
		   qp->s_sending_psn, qp->s_sending_hpsn,
		   qp->s_last, qp->s_acked, qp->s_cur,
		   qp->s_tail, qp->s_head, qp->s_size,
		   qp->remote_qpn,
		   qp->remote_ah_attr.dlid);
}

#endif
Commit	Line	Data
f931551b	1	/*
f7cf9a61	2	* Copyright (c) 2012, 2013 Intel Corporation. All rights reserved.
1fb9fed6	3	* Copyright (c) 2006 - 2012 QLogic Corporation. * All rights reserved.
f931551b RC	4	* Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
	5	*
	6	* This software is available to you under a choice of one of two
	7	* licenses. You may choose to be licensed under the terms of the GNU
	8	* General Public License (GPL) Version 2, available from the file
	9	* COPYING in the main directory of this source tree, or the
	10	* OpenIB.org BSD license below:
	11	*
	12	* Redistribution and use in source and binary forms, with or
	13	* without modification, are permitted provided that the following
	14	* conditions are met:
	15	*
	16	* - Redistributions of source code must retain the above
	17	* copyright notice, this list of conditions and the following
	18	* disclaimer.
	19	*
	20	* - Redistributions in binary form must reproduce the above
	21	* copyright notice, this list of conditions and the following
	22	* disclaimer in the documentation and/or other materials
	23	* provided with the distribution.
	24	*
	25	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	26	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	27	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	28	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	29	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	30	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	31	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	32	* SOFTWARE.
	33	*/
	34
	35	#include <linux/err.h>
	36	#include <linux/vmalloc.h>
869a2a96	37	#include <rdma/rdma_vt.h>
1dd173b0 MM	38	#ifdef CONFIG_DEBUG_FS
	39	#include <linux/seq_file.h>
	40	#endif
f931551b RC	41
	42	#include "qib.h"
	43
898fa52b HC	44	/*
	45	* mask field which was present in now deleted qib_qpn_table
	46	* is not present in rvt_qpn_table. Defining the same field
	47	* as qpt_mask here instead of adding the mask field to
	48	* rvt_qpn_table.
	49	*/
47c7ea6d	50	u16 qpt_mask;
f931551b	51
898fa52b HC	52	static inline unsigned mk_qpn(struct rvt_qpn_table *qpt,
898fa52b HC	53	struct rvt_qpn_map *map, unsigned off)
f931551b	54	{
898fa52b	55	return (map - qpt->map) * RVT_BITS_PER_PAGE + off;
f931551b RC	56	}
f931551b RC	57
898fa52b HC	58	static inline unsigned find_next_offset(struct rvt_qpn_table *qpt,
898fa52b HC	59	struct rvt_qpn_map *map, unsigned off,
2528ea60	60	unsigned n)
f931551b	61	{
898fa52b	62	if (qpt_mask) {
f931551b	63	off++;
898fa52b HC	64	if (((off & qpt_mask) >> 1) >= n)
	65	off = (off \| qpt_mask) + 2;
	66	} else {
	67	off = find_next_zero_bit(map->page, RVT_BITS_PER_PAGE, off);
	68	}
f931551b RC	69	return off;
	70	}
	71
	72	/*
	73	* Convert the AETH credit code into the number of credits.
	74	*/
	75	static u32 credit_table[31] = {
	76	0, /* 0 */
	77	1, /* 1 */
	78	2, /* 2 */
	79	3, /* 3 */
	80	4, /* 4 */
	81	6, /* 5 */
	82	8, /* 6 */
	83	12, /* 7 */
	84	16, /* 8 */
	85	24, /* 9 */
	86	32, /* A */
	87	48, /* B */
	88	64, /* C */
	89	96, /* D */
	90	128, /* E */
	91	192, /* F */
	92	256, /* 10 */
	93	384, /* 11 */
	94	512, /* 12 */
	95	768, /* 13 */
	96	1024, /* 14 */
	97	1536, /* 15 */
	98	2048, /* 16 */
	99	3072, /* 17 */
	100	4096, /* 18 */
	101	6144, /* 19 */
	102	8192, /* 1A */
	103	12288, /* 1B */
	104	16384, /* 1C */
	105	24576, /* 1D */
	106	32768 /* 1E */
	107	};
	108
9ec4faa3 MM	109	const struct rvt_operation_params qib_post_parms[RVT_OPERATION_MAX] = {
	110	[IB_WR_RDMA_WRITE] = {
	111	.length = sizeof(struct ib_rdma_wr),
	112	.qpt_support = BIT(IB_QPT_UC) \| BIT(IB_QPT_RC),
	113	},
	114
	115	[IB_WR_RDMA_READ] = {
	116	.length = sizeof(struct ib_rdma_wr),
	117	.qpt_support = BIT(IB_QPT_RC),
	118	.flags = RVT_OPERATION_ATOMIC,
	119	},
	120
	121	[IB_WR_ATOMIC_CMP_AND_SWP] = {
	122	.length = sizeof(struct ib_atomic_wr),
	123	.qpt_support = BIT(IB_QPT_RC),
	124	.flags = RVT_OPERATION_ATOMIC \| RVT_OPERATION_ATOMIC_SGE,
	125	},
	126
	127	[IB_WR_ATOMIC_FETCH_AND_ADD] = {
	128	.length = sizeof(struct ib_atomic_wr),
	129	.qpt_support = BIT(IB_QPT_RC),
	130	.flags = RVT_OPERATION_ATOMIC \| RVT_OPERATION_ATOMIC_SGE,
	131	},
	132
	133	[IB_WR_RDMA_WRITE_WITH_IMM] = {
	134	.length = sizeof(struct ib_rdma_wr),
	135	.qpt_support = BIT(IB_QPT_UC) \| BIT(IB_QPT_RC),
	136	},
	137
	138	[IB_WR_SEND] = {
	139	.length = sizeof(struct ib_send_wr),
	140	.qpt_support = BIT(IB_QPT_UD) \| BIT(IB_QPT_SMI) \| BIT(IB_QPT_GSI) \|
	141	BIT(IB_QPT_UC) \| BIT(IB_QPT_RC),
	142	},
	143
	144	[IB_WR_SEND_WITH_IMM] = {
	145	.length = sizeof(struct ib_send_wr),
	146	.qpt_support = BIT(IB_QPT_UD) \| BIT(IB_QPT_SMI) \| BIT(IB_QPT_GSI) \|
	147	BIT(IB_QPT_UC) \| BIT(IB_QPT_RC),
	148	},
	149
	150	};
	151
898fa52b	152	static void get_map_page(struct rvt_qpn_table qpt, struct rvt_qpn_map map,
fbbeb863	153	gfp_t gfp)
f931551b	154	{
fbbeb863	155	unsigned long page = get_zeroed_page(gfp);
f931551b RC	156
	157	/*
	158	* Free the page if someone raced with us installing it.
	159	*/
	160
	161	spin_lock(&qpt->lock);
	162	if (map->page)
	163	free_page(page);
	164	else
	165	map->page = (void *)page;
	166	spin_unlock(&qpt->lock);
	167	}
	168
	169	/*
	170	* Allocate the next available QPN or
	171	* zero/one for QP type IB_QPT_SMI/IB_QPT_GSI.
	172	*/
20f333b6 HC	173	int qib_alloc_qpn(struct rvt_dev_info rdi, struct rvt_qpn_table qpt,
20f333b6 HC	174	enum ib_qp_type type, u8 port, gfp_t gfp)
f931551b RC	175	{
f931551b RC	176	u32 i, offset, max_scan, qpn;
898fa52b	177	struct rvt_qpn_map *map;
f931551b	178	u32 ret;
47c7ea6d HC	179	struct qib_ibdev *verbs_dev = container_of(rdi, struct qib_ibdev, rdi);
	180	struct qib_devdata *dd = container_of(verbs_dev, struct qib_devdata,
	181	verbs_dev);
f931551b RC	182
	183	if (type == IB_QPT_SMI \|\| type == IB_QPT_GSI) {
	184	unsigned n;
	185
	186	ret = type == IB_QPT_GSI;
	187	n = 1 << (ret + 2 * (port - 1));
	188	spin_lock(&qpt->lock);
	189	if (qpt->flags & n)
	190	ret = -EINVAL;
	191	else
	192	qpt->flags \|= n;
	193	spin_unlock(&qpt->lock);
	194	goto bail;
	195	}
	196
7c3edd3f	197	qpn = qpt->last + 2;
898fa52b	198	if (qpn >= RVT_QPN_MAX)
f931551b	199	qpn = 2;
898fa52b HC	200	if (qpt_mask && ((qpn & qpt_mask) >> 1) >= dd->n_krcv_queues)
	201	qpn = (qpn \| qpt_mask) + 2;
	202	offset = qpn & RVT_BITS_PER_PAGE_MASK;
	203	map = &qpt->map[qpn / RVT_BITS_PER_PAGE];
f931551b RC	204	max_scan = qpt->nmaps - !offset;
	205	for (i = 0;;) {
	206	if (unlikely(!map->page)) {
fbbeb863	207	get_map_page(qpt, map, gfp);
f931551b RC	208	if (unlikely(!map->page))
	209	break;
	210	}
	211	do {
	212	if (!test_and_set_bit(offset, map->page)) {
	213	qpt->last = qpn;
	214	ret = qpn;
	215	goto bail;
	216	}
2528ea60 MM	217	offset = find_next_offset(qpt, map, offset,
2528ea60 MM	218	dd->n_krcv_queues);
f931551b RC	219	qpn = mk_qpn(qpt, map, offset);
	220	/*
	221	* This test differs from alloc_pidmap().
	222	* If find_next_offset() does find a zero
	223	* bit, we don't need to check for QPN
	224	* wrapping around past our starting QPN.
	225	* We just need to be sure we don't loop
	226	* forever.
	227	*/
898fa52b	228	} while (offset < RVT_BITS_PER_PAGE && qpn < RVT_QPN_MAX);
f931551b RC	229	/*
	230	* In order to keep the number of pages allocated to a
	231	* minimum, we scan the all existing pages before increasing
	232	* the size of the bitmap table.
	233	*/
	234	if (++i > max_scan) {
898fa52b	235	if (qpt->nmaps == RVT_QPNMAP_ENTRIES)
f931551b RC	236	break;
f931551b RC	237	map = &qpt->map[qpt->nmaps++];
2528ea60	238	offset = 0;
f931551b RC	239	} else if (map < &qpt->map[qpt->nmaps]) {
f931551b RC	240	++map;
2528ea60	241	offset = 0;
f931551b RC	242	} else {
f931551b RC	243	map = &qpt->map[0];
2528ea60	244	offset = 2;
f931551b RC	245	}
	246	qpn = mk_qpn(qpt, map, offset);
	247	}
	248
	249	ret = -ENOMEM;
	250
	251	bail:
	252	return ret;
	253	}
	254
f931551b RC	255	/**
f931551b RC	256	* qib_free_all_qps - check for QPs still in use
f931551b	257	*/
47c7ea6d	258	unsigned qib_free_all_qps(struct rvt_dev_info *rdi)
f931551b	259	{
47c7ea6d HC	260	struct qib_ibdev *verbs_dev = container_of(rdi, struct qib_ibdev, rdi);
	261	struct qib_devdata *dd = container_of(verbs_dev, struct qib_devdata,
	262	verbs_dev);
f931551b RC	263	unsigned n, qp_inuse = 0;
	264
	265	for (n = 0; n < dd->num_pports; n++) {
	266	struct qib_ibport *ibp = &dd->pport[n].ibport_data;
	267
af061a64	268	rcu_read_lock();
f24a6d48	269	if (rcu_dereference(ibp->rvp.qp[0]))
f931551b	270	qp_inuse++;
f24a6d48	271	if (rcu_dereference(ibp->rvp.qp[1]))
f931551b	272	qp_inuse++;
af061a64	273	rcu_read_unlock();
f931551b	274	}
f931551b RC	275	return qp_inuse;
	276	}
	277
20f333b6	278	void qib_notify_qp_reset(struct rvt_qp *qp)
f931551b	279	{
ffc26907	280	struct qib_qp_priv *priv = qp->priv;
47c7ea6d	281
ffc26907	282	atomic_set(&priv->s_dma_busy, 0);
f931551b RC	283	}
f931551b RC	284
20f333b6	285	void qib_notify_error_qp(struct rvt_qp *qp)
f931551b	286	{
ffc26907	287	struct qib_qp_priv *priv = qp->priv;
f931551b	288	struct qib_ibdev *dev = to_idev(qp->ibqp.device);
16028f27	289
cd18201f	290	spin_lock(&dev->rdi.pending_lock);
01ba79d4 HC	291	if (!list_empty(&priv->iowait) && !(qp->s_flags & RVT_S_BUSY)) {
01ba79d4 HC	292	qp->s_flags &= ~RVT_S_ANY_WAIT_IO;
ffc26907	293	list_del_init(&priv->iowait);
f931551b	294	}
cd18201f	295	spin_unlock(&dev->rdi.pending_lock);
f931551b	296
01ba79d4	297	if (!(qp->s_flags & RVT_S_BUSY)) {
f931551b RC	298	qp->s_hdrwords = 0;
f931551b RC	299	if (qp->s_rdma_mr) {
7c2e11fe	300	rvt_put_mr(qp->s_rdma_mr);
f931551b RC	301	qp->s_rdma_mr = NULL;
f931551b RC	302	}
ffc26907 DD	303	if (priv->s_tx) {
	304	qib_put_txreq(priv->s_tx);
	305	priv->s_tx = NULL;
f931551b RC	306	}
f931551b RC	307	}
f931551b RC	308	}
f931551b RC	309
70696ea7	310	static int mtu_to_enum(u32 mtu)
f931551b	311	{
70696ea7	312	int enum_mtu;
f931551b	313
70696ea7 HC	314	switch (mtu) {
	315	case 4096:
	316	enum_mtu = IB_MTU_4096;
f931551b	317	break;
70696ea7 HC	318	case 2048:
70696ea7 HC	319	enum_mtu = IB_MTU_2048;
f931551b	320	break;
70696ea7 HC	321	case 1024:
70696ea7 HC	322	enum_mtu = IB_MTU_1024;
f931551b	323	break;
70696ea7 HC	324	case 512:
70696ea7 HC	325	enum_mtu = IB_MTU_512;
f931551b	326	break;
70696ea7 HC	327	case 256:
70696ea7 HC	328	enum_mtu = IB_MTU_256;
f931551b	329	break;
f931551b	330	default:
70696ea7	331	enum_mtu = IB_MTU_2048;
d0f2faf7	332	}
70696ea7 HC	333	return enum_mtu;
70696ea7 HC	334	}
f931551b	335
20f333b6 HC	336	int qib_get_pmtu_from_attr(struct rvt_dev_info rdi, struct rvt_qp qp,
20f333b6 HC	337	struct ib_qp_attr *attr)
70696ea7 HC	338	{
	339	int mtu, pmtu, pidx = qp->port_num - 1;
	340	struct qib_ibdev *verbs_dev = container_of(rdi, struct qib_ibdev, rdi);
	341	struct qib_devdata *dd = container_of(verbs_dev, struct qib_devdata,
	342	verbs_dev);
	343	mtu = ib_mtu_enum_to_int(attr->path_mtu);
	344	if (mtu == -1)
	345	return -EINVAL;
f931551b	346
70696ea7 HC	347	if (mtu > dd->pport[pidx].ibmtu)
	348	pmtu = mtu_to_enum(dd->pport[pidx].ibmtu);
	349	else
	350	pmtu = attr->path_mtu;
	351	return pmtu;
	352	}
f931551b	353
20f333b6	354	int qib_mtu_to_path_mtu(u32 mtu)
70696ea7 HC	355	{
	356	return mtu_to_enum(mtu);
	357	}
f931551b	358
20f333b6	359	u32 qib_mtu_from_qp(struct rvt_dev_info rdi, struct rvt_qp qp, u32 pmtu)
70696ea7 HC	360	{
70696ea7 HC	361	return ib_mtu_enum_to_int(pmtu);
f931551b RC	362	}
f931551b RC	363
f931551b RC	364	/**
	365	* qib_compute_aeth - compute the AETH (syndrome + MSN)
	366	* @qp: the queue pair to compute the AETH for
	367	*
	368	* Returns the AETH.
	369	*/
7c2e11fe	370	__be32 qib_compute_aeth(struct rvt_qp *qp)
f931551b RC	371	{
	372	u32 aeth = qp->r_msn & QIB_MSN_MASK;
	373
	374	if (qp->ibqp.srq) {
	375	/*
	376	* Shared receive queues don't generate credits.
	377	* Set the credit field to the invalid value.
	378	*/
	379	aeth \|= QIB_AETH_CREDIT_INVAL << QIB_AETH_CREDIT_SHIFT;
	380	} else {
	381	u32 min, max, x;
	382	u32 credits;
7c2e11fe	383	struct rvt_rwq *wq = qp->r_rq.wq;
f931551b RC	384	u32 head;
	385	u32 tail;
	386
	387	/* sanity check pointers before trusting them */
	388	head = wq->head;
	389	if (head >= qp->r_rq.size)
	390	head = 0;
	391	tail = wq->tail;
	392	if (tail >= qp->r_rq.size)
	393	tail = 0;
	394	/*
	395	* Compute the number of credits available (RWQEs).
	396	* XXX Not holding the r_rq.lock here so there is a small
	397	* chance that the pair of reads are not atomic.
	398	*/
	399	credits = head - tail;
	400	if ((int)credits < 0)
	401	credits += qp->r_rq.size;
	402	/*
	403	* Binary search the credit table to find the code to
	404	* use.
	405	*/
	406	min = 0;
	407	max = 31;
	408	for (;;) {
	409	x = (min + max) / 2;
	410	if (credit_table[x] == credits)
	411	break;
	412	if (credit_table[x] > credits)
	413	max = x;
	414	else if (min == x)
	415	break;
	416	else
	417	min = x;
	418	}
	419	aeth \|= x << QIB_AETH_CREDIT_SHIFT;
	420	}
	421	return cpu_to_be32(aeth);
	422	}
	423
20f333b6	424	void qib_qp_priv_alloc(struct rvt_dev_info rdi, struct rvt_qp *qp, gfp_t gfp)
f931551b	425	{
ffc26907	426	struct qib_qp_priv *priv;
f931551b	427
47c7ea6d HC	428	priv = kzalloc(sizeof(*priv), gfp);
	429	if (!priv)
	430	return ERR_PTR(-ENOMEM);
	431	priv->owner = qp;
f931551b	432
47c7ea6d HC	433	priv->s_hdr = kzalloc(sizeof(*priv->s_hdr), gfp);
	434	if (!priv->s_hdr) {
	435	kfree(priv);
	436	return ERR_PTR(-ENOMEM);
f931551b	437	}
47c7ea6d	438	init_waitqueue_head(&priv->wait_dma);
db3ef0eb	439	INIT_WORK(&priv->s_work, _qib_do_send);
47c7ea6d	440	INIT_LIST_HEAD(&priv->iowait);
f931551b	441
47c7ea6d HC	442	return priv;
47c7ea6d HC	443	}
f931551b	444
20f333b6	445	void qib_qp_priv_free(struct rvt_dev_info rdi, struct rvt_qp qp)
47c7ea6d HC	446	{
47c7ea6d HC	447	struct qib_qp_priv *priv = qp->priv;
f931551b	448
ffc26907 DD	449	kfree(priv->s_hdr);
ffc26907 DD	450	kfree(priv);
f931551b RC	451	}
f931551b RC	452
20f333b6	453	void qib_stop_send_queue(struct rvt_qp *qp)
70696ea7 HC	454	{
	455	struct qib_qp_priv *priv = qp->priv;
	456
	457	cancel_work_sync(&priv->s_work);
08279d5c	458	del_timer_sync(&qp->s_timer);
70696ea7 HC	459	}
70696ea7 HC	460
20f333b6	461	void qib_quiesce_qp(struct rvt_qp *qp)
70696ea7 HC	462	{
	463	struct qib_qp_priv *priv = qp->priv;
	464
	465	wait_event(priv->wait_dma, !atomic_read(&priv->s_dma_busy));
	466	if (priv->s_tx) {
	467	qib_put_txreq(priv->s_tx);
	468	priv->s_tx = NULL;
	469	}
	470	}
	471
20f333b6	472	void qib_flush_qp_waiters(struct rvt_qp *qp)
70696ea7 HC	473	{
	474	struct qib_qp_priv *priv = qp->priv;
	475	struct qib_ibdev *dev = to_idev(qp->ibqp.device);
	476
	477	spin_lock(&dev->rdi.pending_lock);
	478	if (!list_empty(&priv->iowait))
	479	list_del_init(&priv->iowait);
	480	spin_unlock(&dev->rdi.pending_lock);
	481	}
	482
f931551b RC	483	/**
	484	* qib_get_credit - flush the send work queue of a QP
	485	* @qp: the qp who's send work queue to flush
	486	* @aeth: the Acknowledge Extended Transport Header
	487	*
	488	* The QP s_lock should be held.
	489	*/
7c2e11fe	490	void qib_get_credit(struct rvt_qp *qp, u32 aeth)
f931551b RC	491	{
	492	u32 credit = (aeth >> QIB_AETH_CREDIT_SHIFT) & QIB_AETH_CREDIT_MASK;
	493
	494	/*
	495	* If the credit is invalid, we can send
	496	* as many packets as we like. Otherwise, we have to
	497	* honor the credit field.
	498	*/
	499	if (credit == QIB_AETH_CREDIT_INVAL) {
01ba79d4 HC	500	if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT)) {
	501	qp->s_flags \|= RVT_S_UNLIMITED_CREDIT;
	502	if (qp->s_flags & RVT_S_WAIT_SSN_CREDIT) {
	503	qp->s_flags &= ~RVT_S_WAIT_SSN_CREDIT;
f931551b RC	504	qib_schedule_send(qp);
	505	}
	506	}
01ba79d4	507	} else if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT)) {
f931551b RC	508	/* Compute new LSN (i.e., MSN + credit) */
	509	credit = (aeth + credit_table[credit]) & QIB_MSN_MASK;
	510	if (qib_cmp24(credit, qp->s_lsn) > 0) {
	511	qp->s_lsn = credit;
01ba79d4 HC	512	if (qp->s_flags & RVT_S_WAIT_SSN_CREDIT) {
01ba79d4 HC	513	qp->s_flags &= ~RVT_S_WAIT_SSN_CREDIT;
f931551b RC	514	qib_schedule_send(qp);
	515	}
	516	}
	517	}
	518	}
1dd173b0	519
46a80d62 MM	520	/**
	521	* qib_check_send_wqe - validate wr/wqe
	522	* @qp - The qp
	523	* @wqe - The built wqe
	524	*
	525	* validate wr/wqe. This is called
	526	* prior to inserting the wqe into
	527	* the ring but after the wqe has been
	528	* setup.
	529	*
91702b4a	530	* Returns 1 to force direct progress, 0 otherwise, -EINVAL on failure
46a80d62 MM	531	*/
	532	int qib_check_send_wqe(struct rvt_qp *qp,
	533	struct rvt_swqe *wqe)
	534	{
	535	struct rvt_ah *ah;
91702b4a	536	int ret = 0;
46a80d62 MM	537
	538	switch (qp->ibqp.qp_type) {
	539	case IB_QPT_RC:
	540	case IB_QPT_UC:
	541	if (wqe->length > 0x80000000U)
	542	return -EINVAL;
	543	break;
	544	case IB_QPT_SMI:
	545	case IB_QPT_GSI:
	546	case IB_QPT_UD:
	547	ah = ibah_to_rvtah(wqe->ud_wr.ah);
	548	if (wqe->length > (1 << ah->log_pmtu))
	549	return -EINVAL;
91702b4a MM	550	/* progress hint */
91702b4a MM	551	ret = 1;
46a80d62 MM	552	break;
	553	default:
	554	break;
	555	}
91702b4a	556	return ret;
46a80d62 MM	557	}
46a80d62 MM	558
1dd173b0 MM	559	#ifdef CONFIG_DEBUG_FS
	560
	561	struct qib_qp_iter {
	562	struct qib_ibdev *dev;
7c2e11fe	563	struct rvt_qp *qp;
1dd173b0 MM	564	int n;
	565	};
	566
	567	struct qib_qp_iter qib_qp_iter_init(struct qib_ibdev dev)
	568	{
	569	struct qib_qp_iter *iter;
	570
	571	iter = kzalloc(sizeof(*iter), GFP_KERNEL);
	572	if (!iter)
	573	return NULL;
	574
	575	iter->dev = dev;
1dd173b0 MM	576
	577	return iter;
	578	}
	579
	580	int qib_qp_iter_next(struct qib_qp_iter *iter)
	581	{
	582	struct qib_ibdev *dev = iter->dev;
	583	int n = iter->n;
	584	int ret = 1;
7c2e11fe DD	585	struct rvt_qp *pqp = iter->qp;
7c2e11fe DD	586	struct rvt_qp *qp;
1dd173b0	587
898fa52b	588	for (; n < dev->rdi.qp_dev->qp_table_size; n++) {
1dd173b0 MM	589	if (pqp)
	590	qp = rcu_dereference(pqp->next);
	591	else
898fa52b	592	qp = rcu_dereference(dev->rdi.qp_dev->qp_table[n]);
1dd173b0 MM	593	pqp = qp;
1dd173b0 MM	594	if (qp) {
1dd173b0 MM	595	iter->qp = qp;
	596	iter->n = n;
	597	return 0;
	598	}
	599	}
1dd173b0 MM	600	return ret;
	601	}
	602
	603	static const char * const qp_type_str[] = {
	604	"SMI", "GSI", "RC", "UC", "UD",
	605	};
	606
	607	void qib_qp_iter_print(struct seq_file s, struct qib_qp_iter iter)
	608	{
7c2e11fe DD	609	struct rvt_swqe *wqe;
7c2e11fe DD	610	struct rvt_qp *qp = iter->qp;
ffc26907	611	struct qib_qp_priv *priv = qp->priv;
1dd173b0	612
db3ef0eb	613	wqe = rvt_get_swqe_ptr(qp, qp->s_last);
1dd173b0 MM	614	seq_printf(s,
	615	"N %d QP%u %s %u %u %u f=%x %u %u %u %u %u PSN %x %x %x %x %x (%u %u %u %u %u %u) QP%u LID %x\n",
	616	iter->n,
	617	qp->ibqp.qp_num,
	618	qp_type_str[qp->ibqp.qp_type],
	619	qp->state,
	620	wqe->wr.opcode,
	621	qp->s_hdrwords,
	622	qp->s_flags,
ffc26907 DD	623	atomic_read(&priv->s_dma_busy),
ffc26907 DD	624	!list_empty(&priv->iowait),
1dd173b0 MM	625	qp->timeout,
	626	wqe->ssn,
	627	qp->s_lsn,
	628	qp->s_last_psn,
	629	qp->s_psn, qp->s_next_psn,
	630	qp->s_sending_psn, qp->s_sending_hpsn,
	631	qp->s_last, qp->s_acked, qp->s_cur,
	632	qp->s_tail, qp->s_head, qp->s_size,
	633	qp->remote_qpn,
	634	qp->remote_ah_attr.dlid);
	635	}
	636
	637	#endif