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e5fc9753 RM |
1 | /* |
2 | * CPU-agnostic ARM page table allocator. | |
3 | * | |
4 | * ARMv7 Short-descriptor format, supporting | |
5 | * - Basic memory attributes | |
6 | * - Simplified access permissions (AP[2:1] model) | |
7 | * - Backwards-compatible TEX remap | |
8 | * - Large pages/supersections (if indicated by the caller) | |
9 | * | |
10 | * Not supporting: | |
11 | * - Legacy access permissions (AP[2:0] model) | |
12 | * | |
13 | * Almost certainly never supporting: | |
14 | * - PXN | |
15 | * - Domains | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
28 | * | |
29 | * Copyright (C) 2014-2015 ARM Limited | |
30 | * Copyright (c) 2014-2015 MediaTek Inc. | |
31 | */ | |
32 | ||
33 | #define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt | |
34 | ||
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/gfp.h> | |
37 | #include <linux/iommu.h> | |
38 | #include <linux/kernel.h> | |
39 | #include <linux/kmemleak.h> | |
40 | #include <linux/sizes.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/types.h> | |
43 | ||
44 | #include <asm/barrier.h> | |
45 | ||
46 | #include "io-pgtable.h" | |
47 | ||
48 | /* Struct accessors */ | |
49 | #define io_pgtable_to_data(x) \ | |
50 | container_of((x), struct arm_v7s_io_pgtable, iop) | |
51 | ||
52 | #define io_pgtable_ops_to_data(x) \ | |
53 | io_pgtable_to_data(io_pgtable_ops_to_pgtable(x)) | |
54 | ||
55 | /* | |
56 | * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2, | |
57 | * and 12 bits in a page. With some carefully-chosen coefficients we can | |
58 | * hide the ugly inconsistencies behind these macros and at least let the | |
59 | * rest of the code pretend to be somewhat sane. | |
60 | */ | |
61 | #define ARM_V7S_ADDR_BITS 32 | |
62 | #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4) | |
63 | #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl))) | |
64 | #define ARM_V7S_TABLE_SHIFT 10 | |
65 | ||
66 | #define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl)) | |
67 | #define ARM_V7S_TABLE_SIZE(lvl) \ | |
68 | (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte)) | |
69 | ||
70 | #define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl)) | |
71 | #define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl))) | |
72 | #define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT)) | |
73 | #define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1) | |
74 | #define ARM_V7S_LVL_IDX(addr, lvl) ({ \ | |
75 | int _l = lvl; \ | |
76 | ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \ | |
77 | }) | |
78 | ||
79 | /* | |
80 | * Large page/supersection entries are effectively a block of 16 page/section | |
81 | * entries, along the lines of the LPAE contiguous hint, but all with the | |
82 | * same output address. For want of a better common name we'll call them | |
83 | * "contiguous" versions of their respective page/section entries here, but | |
84 | * noting the distinction (WRT to TLB maintenance) that they represent *one* | |
85 | * entry repeated 16 times, not 16 separate entries (as in the LPAE case). | |
86 | */ | |
87 | #define ARM_V7S_CONT_PAGES 16 | |
88 | ||
89 | /* PTE type bits: these are all mixed up with XN/PXN bits in most cases */ | |
90 | #define ARM_V7S_PTE_TYPE_TABLE 0x1 | |
91 | #define ARM_V7S_PTE_TYPE_PAGE 0x2 | |
92 | #define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1 | |
93 | ||
94 | #define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0) | |
95 | #define ARM_V7S_PTE_IS_TABLE(pte, lvl) (lvl == 1 && ((pte) & ARM_V7S_PTE_TYPE_TABLE)) | |
96 | ||
97 | /* Page table bits */ | |
98 | #define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl))) | |
99 | #define ARM_V7S_ATTR_B BIT(2) | |
100 | #define ARM_V7S_ATTR_C BIT(3) | |
101 | #define ARM_V7S_ATTR_NS_TABLE BIT(3) | |
102 | #define ARM_V7S_ATTR_NS_SECTION BIT(19) | |
103 | ||
104 | #define ARM_V7S_CONT_SECTION BIT(18) | |
105 | #define ARM_V7S_CONT_PAGE_XN_SHIFT 15 | |
106 | ||
107 | /* | |
108 | * The attribute bits are consistently ordered*, but occupy bits [17:10] of | |
109 | * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual | |
110 | * fields relative to that 8-bit block, plus a total shift relative to the PTE. | |
111 | */ | |
112 | #define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6) | |
113 | ||
114 | #define ARM_V7S_ATTR_MASK 0xff | |
115 | #define ARM_V7S_ATTR_AP0 BIT(0) | |
116 | #define ARM_V7S_ATTR_AP1 BIT(1) | |
117 | #define ARM_V7S_ATTR_AP2 BIT(5) | |
118 | #define ARM_V7S_ATTR_S BIT(6) | |
119 | #define ARM_V7S_ATTR_NG BIT(7) | |
120 | #define ARM_V7S_TEX_SHIFT 2 | |
121 | #define ARM_V7S_TEX_MASK 0x7 | |
122 | #define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT) | |
123 | ||
1afe2319 YW |
124 | #define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */ |
125 | ||
e5fc9753 RM |
126 | /* *well, except for TEX on level 2 large pages, of course :( */ |
127 | #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6 | |
128 | #define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT) | |
129 | ||
130 | /* Simplified access permissions */ | |
131 | #define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0 | |
132 | #define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1 | |
133 | #define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2 | |
134 | ||
135 | /* Register bits */ | |
136 | #define ARM_V7S_RGN_NC 0 | |
137 | #define ARM_V7S_RGN_WBWA 1 | |
138 | #define ARM_V7S_RGN_WT 2 | |
139 | #define ARM_V7S_RGN_WB 3 | |
140 | ||
141 | #define ARM_V7S_PRRR_TYPE_DEVICE 1 | |
142 | #define ARM_V7S_PRRR_TYPE_NORMAL 2 | |
143 | #define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2)) | |
144 | #define ARM_V7S_PRRR_DS0 BIT(16) | |
145 | #define ARM_V7S_PRRR_DS1 BIT(17) | |
146 | #define ARM_V7S_PRRR_NS0 BIT(18) | |
147 | #define ARM_V7S_PRRR_NS1 BIT(19) | |
148 | #define ARM_V7S_PRRR_NOS(n) BIT((n) + 24) | |
149 | ||
150 | #define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2)) | |
151 | #define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16)) | |
152 | ||
153 | #define ARM_V7S_TTBR_S BIT(1) | |
154 | #define ARM_V7S_TTBR_NOS BIT(5) | |
155 | #define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3) | |
156 | #define ARM_V7S_TTBR_IRGN_ATTR(attr) \ | |
157 | ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1)) | |
158 | ||
159 | #define ARM_V7S_TCR_PD1 BIT(5) | |
160 | ||
161 | typedef u32 arm_v7s_iopte; | |
162 | ||
163 | static bool selftest_running; | |
164 | ||
165 | struct arm_v7s_io_pgtable { | |
166 | struct io_pgtable iop; | |
167 | ||
168 | arm_v7s_iopte *pgd; | |
169 | struct kmem_cache *l2_tables; | |
170 | }; | |
171 | ||
172 | static dma_addr_t __arm_v7s_dma_addr(void *pages) | |
173 | { | |
174 | return (dma_addr_t)virt_to_phys(pages); | |
175 | } | |
176 | ||
177 | static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl) | |
178 | { | |
179 | if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) | |
180 | pte &= ARM_V7S_TABLE_MASK; | |
181 | else | |
182 | pte &= ARM_V7S_LVL_MASK(lvl); | |
183 | return phys_to_virt(pte); | |
184 | } | |
185 | ||
186 | static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp, | |
187 | struct arm_v7s_io_pgtable *data) | |
188 | { | |
189 | struct device *dev = data->iop.cfg.iommu_dev; | |
190 | dma_addr_t dma; | |
191 | size_t size = ARM_V7S_TABLE_SIZE(lvl); | |
192 | void *table = NULL; | |
193 | ||
194 | if (lvl == 1) | |
195 | table = (void *)__get_dma_pages(__GFP_ZERO, get_order(size)); | |
196 | else if (lvl == 2) | |
048b31ca | 197 | table = kmem_cache_zalloc(data->l2_tables, gfp | GFP_DMA); |
e5fc9753 RM |
198 | if (table && !selftest_running) { |
199 | dma = dma_map_single(dev, table, size, DMA_TO_DEVICE); | |
200 | if (dma_mapping_error(dev, dma)) | |
201 | goto out_free; | |
202 | /* | |
203 | * We depend on the IOMMU being able to work with any physical | |
204 | * address directly, so if the DMA layer suggests otherwise by | |
205 | * translating or truncating them, that bodes very badly... | |
206 | */ | |
207 | if (dma != virt_to_phys(table)) | |
208 | goto out_unmap; | |
209 | } | |
210 | kmemleak_ignore(table); | |
211 | return table; | |
212 | ||
213 | out_unmap: | |
214 | dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n"); | |
215 | dma_unmap_single(dev, dma, size, DMA_TO_DEVICE); | |
216 | out_free: | |
217 | if (lvl == 1) | |
218 | free_pages((unsigned long)table, get_order(size)); | |
219 | else | |
220 | kmem_cache_free(data->l2_tables, table); | |
221 | return NULL; | |
222 | } | |
223 | ||
224 | static void __arm_v7s_free_table(void *table, int lvl, | |
225 | struct arm_v7s_io_pgtable *data) | |
226 | { | |
227 | struct device *dev = data->iop.cfg.iommu_dev; | |
228 | size_t size = ARM_V7S_TABLE_SIZE(lvl); | |
229 | ||
230 | if (!selftest_running) | |
231 | dma_unmap_single(dev, __arm_v7s_dma_addr(table), size, | |
232 | DMA_TO_DEVICE); | |
233 | if (lvl == 1) | |
234 | free_pages((unsigned long)table, get_order(size)); | |
235 | else | |
236 | kmem_cache_free(data->l2_tables, table); | |
237 | } | |
238 | ||
239 | static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries, | |
240 | struct io_pgtable_cfg *cfg) | |
241 | { | |
242 | if (selftest_running) | |
243 | return; | |
244 | ||
245 | dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep), | |
246 | num_entries * sizeof(*ptep), DMA_TO_DEVICE); | |
247 | } | |
248 | static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte, | |
249 | int num_entries, struct io_pgtable_cfg *cfg) | |
250 | { | |
251 | int i; | |
252 | ||
253 | for (i = 0; i < num_entries; i++) | |
254 | ptep[i] = pte; | |
255 | ||
256 | __arm_v7s_pte_sync(ptep, num_entries, cfg); | |
257 | } | |
258 | ||
259 | static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl, | |
260 | struct io_pgtable_cfg *cfg) | |
261 | { | |
262 | bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS); | |
e88ccab1 | 263 | arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S; |
e5fc9753 | 264 | |
e88ccab1 RM |
265 | if (!(prot & IOMMU_MMIO)) |
266 | pte |= ARM_V7S_ATTR_TEX(1); | |
e5fc9753 RM |
267 | if (ap) { |
268 | pte |= ARM_V7S_PTE_AF | ARM_V7S_PTE_AP_UNPRIV; | |
269 | if (!(prot & IOMMU_WRITE)) | |
270 | pte |= ARM_V7S_PTE_AP_RDONLY; | |
271 | } | |
272 | pte <<= ARM_V7S_ATTR_SHIFT(lvl); | |
273 | ||
274 | if ((prot & IOMMU_NOEXEC) && ap) | |
275 | pte |= ARM_V7S_ATTR_XN(lvl); | |
e88ccab1 RM |
276 | if (prot & IOMMU_MMIO) |
277 | pte |= ARM_V7S_ATTR_B; | |
278 | else if (prot & IOMMU_CACHE) | |
e5fc9753 RM |
279 | pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C; |
280 | ||
281 | return pte; | |
282 | } | |
283 | ||
284 | static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl) | |
285 | { | |
286 | int prot = IOMMU_READ; | |
e88ccab1 | 287 | arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl); |
e5fc9753 | 288 | |
e633fc7a | 289 | if (!(attr & ARM_V7S_PTE_AP_RDONLY)) |
e5fc9753 | 290 | prot |= IOMMU_WRITE; |
e88ccab1 RM |
291 | if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0) |
292 | prot |= IOMMU_MMIO; | |
293 | else if (pte & ARM_V7S_ATTR_C) | |
e5fc9753 | 294 | prot |= IOMMU_CACHE; |
e633fc7a RM |
295 | if (pte & ARM_V7S_ATTR_XN(lvl)) |
296 | prot |= IOMMU_NOEXEC; | |
e5fc9753 RM |
297 | |
298 | return prot; | |
299 | } | |
300 | ||
301 | static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl) | |
302 | { | |
303 | if (lvl == 1) { | |
304 | pte |= ARM_V7S_CONT_SECTION; | |
305 | } else if (lvl == 2) { | |
306 | arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl); | |
307 | arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK; | |
308 | ||
309 | pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE; | |
310 | pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) | | |
311 | (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) | | |
312 | ARM_V7S_PTE_TYPE_CONT_PAGE; | |
313 | } | |
314 | return pte; | |
315 | } | |
316 | ||
317 | static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl) | |
318 | { | |
319 | if (lvl == 1) { | |
320 | pte &= ~ARM_V7S_CONT_SECTION; | |
321 | } else if (lvl == 2) { | |
322 | arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT); | |
323 | arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK << | |
324 | ARM_V7S_CONT_PAGE_TEX_SHIFT); | |
325 | ||
326 | pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE; | |
327 | pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) | | |
328 | (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) | | |
329 | ARM_V7S_PTE_TYPE_PAGE; | |
330 | } | |
331 | return pte; | |
332 | } | |
333 | ||
334 | static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl) | |
335 | { | |
336 | if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl)) | |
337 | return pte & ARM_V7S_CONT_SECTION; | |
338 | else if (lvl == 2) | |
339 | return !(pte & ARM_V7S_PTE_TYPE_PAGE); | |
340 | return false; | |
341 | } | |
342 | ||
343 | static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *, unsigned long, | |
344 | size_t, int, arm_v7s_iopte *); | |
345 | ||
346 | static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data, | |
347 | unsigned long iova, phys_addr_t paddr, int prot, | |
348 | int lvl, int num_entries, arm_v7s_iopte *ptep) | |
349 | { | |
350 | struct io_pgtable_cfg *cfg = &data->iop.cfg; | |
351 | arm_v7s_iopte pte = arm_v7s_prot_to_pte(prot, lvl, cfg); | |
352 | int i; | |
353 | ||
354 | for (i = 0; i < num_entries; i++) | |
355 | if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) { | |
356 | /* | |
357 | * We need to unmap and free the old table before | |
358 | * overwriting it with a block entry. | |
359 | */ | |
360 | arm_v7s_iopte *tblp; | |
361 | size_t sz = ARM_V7S_BLOCK_SIZE(lvl); | |
362 | ||
363 | tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl); | |
364 | if (WARN_ON(__arm_v7s_unmap(data, iova + i * sz, | |
365 | sz, lvl, tblp) != sz)) | |
366 | return -EINVAL; | |
367 | } else if (ptep[i]) { | |
368 | /* We require an unmap first */ | |
369 | WARN_ON(!selftest_running); | |
370 | return -EEXIST; | |
371 | } | |
372 | ||
373 | pte |= ARM_V7S_PTE_TYPE_PAGE; | |
374 | if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)) | |
375 | pte |= ARM_V7S_ATTR_NS_SECTION; | |
376 | ||
1afe2319 YW |
377 | if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB) |
378 | pte |= ARM_V7S_ATTR_MTK_4GB; | |
379 | ||
e5fc9753 RM |
380 | if (num_entries > 1) |
381 | pte = arm_v7s_pte_to_cont(pte, lvl); | |
382 | ||
383 | pte |= paddr & ARM_V7S_LVL_MASK(lvl); | |
384 | ||
385 | __arm_v7s_set_pte(ptep, pte, num_entries, cfg); | |
386 | return 0; | |
387 | } | |
388 | ||
389 | static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova, | |
390 | phys_addr_t paddr, size_t size, int prot, | |
391 | int lvl, arm_v7s_iopte *ptep) | |
392 | { | |
393 | struct io_pgtable_cfg *cfg = &data->iop.cfg; | |
394 | arm_v7s_iopte pte, *cptep; | |
395 | int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl); | |
396 | ||
397 | /* Find our entry at the current level */ | |
398 | ptep += ARM_V7S_LVL_IDX(iova, lvl); | |
399 | ||
400 | /* If we can install a leaf entry at this level, then do so */ | |
401 | if (num_entries) | |
402 | return arm_v7s_init_pte(data, iova, paddr, prot, | |
403 | lvl, num_entries, ptep); | |
404 | ||
405 | /* We can't allocate tables at the final level */ | |
406 | if (WARN_ON(lvl == 2)) | |
407 | return -EINVAL; | |
408 | ||
409 | /* Grab a pointer to the next level */ | |
410 | pte = *ptep; | |
411 | if (!pte) { | |
412 | cptep = __arm_v7s_alloc_table(lvl + 1, GFP_ATOMIC, data); | |
413 | if (!cptep) | |
414 | return -ENOMEM; | |
415 | ||
416 | pte = virt_to_phys(cptep) | ARM_V7S_PTE_TYPE_TABLE; | |
417 | if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) | |
418 | pte |= ARM_V7S_ATTR_NS_TABLE; | |
419 | ||
420 | __arm_v7s_set_pte(ptep, pte, 1, cfg); | |
421 | } else { | |
422 | cptep = iopte_deref(pte, lvl); | |
423 | } | |
424 | ||
425 | /* Rinse, repeat */ | |
426 | return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep); | |
427 | } | |
428 | ||
429 | static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova, | |
430 | phys_addr_t paddr, size_t size, int prot) | |
431 | { | |
432 | struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); | |
507e4c9d | 433 | struct io_pgtable *iop = &data->iop; |
e5fc9753 RM |
434 | int ret; |
435 | ||
436 | /* If no access, then nothing to do */ | |
437 | if (!(prot & (IOMMU_READ | IOMMU_WRITE))) | |
438 | return 0; | |
439 | ||
440 | ret = __arm_v7s_map(data, iova, paddr, size, prot, 1, data->pgd); | |
441 | /* | |
442 | * Synchronise all PTE updates for the new mapping before there's | |
443 | * a chance for anything to kick off a table walk for the new iova. | |
444 | */ | |
507e4c9d RM |
445 | if (iop->cfg.quirks & IO_PGTABLE_QUIRK_TLBI_ON_MAP) { |
446 | io_pgtable_tlb_add_flush(iop, iova, size, | |
447 | ARM_V7S_BLOCK_SIZE(2), false); | |
448 | io_pgtable_tlb_sync(iop); | |
e5fc9753 RM |
449 | } else { |
450 | wmb(); | |
451 | } | |
452 | ||
453 | return ret; | |
454 | } | |
455 | ||
456 | static void arm_v7s_free_pgtable(struct io_pgtable *iop) | |
457 | { | |
458 | struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop); | |
459 | int i; | |
460 | ||
461 | for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) { | |
462 | arm_v7s_iopte pte = data->pgd[i]; | |
463 | ||
464 | if (ARM_V7S_PTE_IS_TABLE(pte, 1)) | |
465 | __arm_v7s_free_table(iopte_deref(pte, 1), 2, data); | |
466 | } | |
467 | __arm_v7s_free_table(data->pgd, 1, data); | |
468 | kmem_cache_destroy(data->l2_tables); | |
469 | kfree(data); | |
470 | } | |
471 | ||
472 | static void arm_v7s_split_cont(struct arm_v7s_io_pgtable *data, | |
473 | unsigned long iova, int idx, int lvl, | |
474 | arm_v7s_iopte *ptep) | |
475 | { | |
507e4c9d | 476 | struct io_pgtable *iop = &data->iop; |
e5fc9753 RM |
477 | arm_v7s_iopte pte; |
478 | size_t size = ARM_V7S_BLOCK_SIZE(lvl); | |
479 | int i; | |
480 | ||
481 | ptep -= idx & (ARM_V7S_CONT_PAGES - 1); | |
482 | pte = arm_v7s_cont_to_pte(*ptep, lvl); | |
483 | for (i = 0; i < ARM_V7S_CONT_PAGES; i++) { | |
484 | ptep[i] = pte; | |
485 | pte += size; | |
486 | } | |
487 | ||
507e4c9d | 488 | __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg); |
e5fc9753 RM |
489 | |
490 | size *= ARM_V7S_CONT_PAGES; | |
507e4c9d RM |
491 | io_pgtable_tlb_add_flush(iop, iova, size, size, true); |
492 | io_pgtable_tlb_sync(iop); | |
e5fc9753 RM |
493 | } |
494 | ||
495 | static int arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data, | |
496 | unsigned long iova, size_t size, | |
497 | arm_v7s_iopte *ptep) | |
498 | { | |
499 | unsigned long blk_start, blk_end, blk_size; | |
500 | phys_addr_t blk_paddr; | |
501 | arm_v7s_iopte table = 0; | |
e5fc9753 RM |
502 | int prot = arm_v7s_pte_to_prot(*ptep, 1); |
503 | ||
504 | blk_size = ARM_V7S_BLOCK_SIZE(1); | |
505 | blk_start = iova & ARM_V7S_LVL_MASK(1); | |
506 | blk_end = blk_start + ARM_V7S_BLOCK_SIZE(1); | |
507 | blk_paddr = *ptep & ARM_V7S_LVL_MASK(1); | |
508 | ||
509 | for (; blk_start < blk_end; blk_start += size, blk_paddr += size) { | |
510 | arm_v7s_iopte *tablep; | |
511 | ||
512 | /* Unmap! */ | |
513 | if (blk_start == iova) | |
514 | continue; | |
515 | ||
516 | /* __arm_v7s_map expects a pointer to the start of the table */ | |
517 | tablep = &table - ARM_V7S_LVL_IDX(blk_start, 1); | |
518 | if (__arm_v7s_map(data, blk_start, blk_paddr, size, prot, 1, | |
519 | tablep) < 0) { | |
520 | if (table) { | |
521 | /* Free the table we allocated */ | |
522 | tablep = iopte_deref(table, 1); | |
523 | __arm_v7s_free_table(tablep, 2, data); | |
524 | } | |
525 | return 0; /* Bytes unmapped */ | |
526 | } | |
527 | } | |
528 | ||
507e4c9d | 529 | __arm_v7s_set_pte(ptep, table, 1, &data->iop.cfg); |
e5fc9753 | 530 | iova &= ~(blk_size - 1); |
507e4c9d | 531 | io_pgtable_tlb_add_flush(&data->iop, iova, blk_size, blk_size, true); |
e5fc9753 RM |
532 | return size; |
533 | } | |
534 | ||
535 | static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *data, | |
536 | unsigned long iova, size_t size, int lvl, | |
537 | arm_v7s_iopte *ptep) | |
538 | { | |
539 | arm_v7s_iopte pte[ARM_V7S_CONT_PAGES]; | |
507e4c9d | 540 | struct io_pgtable *iop = &data->iop; |
e5fc9753 RM |
541 | int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl); |
542 | ||
543 | /* Something went horribly wrong and we ran out of page table */ | |
544 | if (WARN_ON(lvl > 2)) | |
545 | return 0; | |
546 | ||
547 | idx = ARM_V7S_LVL_IDX(iova, lvl); | |
548 | ptep += idx; | |
549 | do { | |
550 | if (WARN_ON(!ARM_V7S_PTE_IS_VALID(ptep[i]))) | |
551 | return 0; | |
552 | pte[i] = ptep[i]; | |
553 | } while (++i < num_entries); | |
554 | ||
555 | /* | |
556 | * If we've hit a contiguous 'large page' entry at this level, it | |
557 | * needs splitting first, unless we're unmapping the whole lot. | |
558 | */ | |
559 | if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl)) | |
560 | arm_v7s_split_cont(data, iova, idx, lvl, ptep); | |
561 | ||
562 | /* If the size matches this level, we're in the right place */ | |
563 | if (num_entries) { | |
564 | size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl); | |
565 | ||
507e4c9d | 566 | __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg); |
e5fc9753 RM |
567 | |
568 | for (i = 0; i < num_entries; i++) { | |
569 | if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) { | |
570 | /* Also flush any partial walks */ | |
507e4c9d RM |
571 | io_pgtable_tlb_add_flush(iop, iova, blk_size, |
572 | ARM_V7S_BLOCK_SIZE(lvl + 1), false); | |
573 | io_pgtable_tlb_sync(iop); | |
e5fc9753 RM |
574 | ptep = iopte_deref(pte[i], lvl); |
575 | __arm_v7s_free_table(ptep, lvl + 1, data); | |
576 | } else { | |
507e4c9d RM |
577 | io_pgtable_tlb_add_flush(iop, iova, blk_size, |
578 | blk_size, true); | |
e5fc9753 RM |
579 | } |
580 | iova += blk_size; | |
581 | } | |
582 | return size; | |
583 | } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) { | |
584 | /* | |
585 | * Insert a table at the next level to map the old region, | |
586 | * minus the part we want to unmap | |
587 | */ | |
588 | return arm_v7s_split_blk_unmap(data, iova, size, ptep); | |
589 | } | |
590 | ||
591 | /* Keep on walkin' */ | |
592 | ptep = iopte_deref(pte[0], lvl); | |
593 | return __arm_v7s_unmap(data, iova, size, lvl + 1, ptep); | |
594 | } | |
595 | ||
596 | static int arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova, | |
597 | size_t size) | |
598 | { | |
e5fc9753 | 599 | struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); |
507e4c9d | 600 | size_t unmapped; |
e5fc9753 RM |
601 | |
602 | unmapped = __arm_v7s_unmap(data, iova, size, 1, data->pgd); | |
603 | if (unmapped) | |
507e4c9d | 604 | io_pgtable_tlb_sync(&data->iop); |
e5fc9753 RM |
605 | |
606 | return unmapped; | |
607 | } | |
608 | ||
609 | static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, | |
610 | unsigned long iova) | |
611 | { | |
612 | struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops); | |
613 | arm_v7s_iopte *ptep = data->pgd, pte; | |
614 | int lvl = 0; | |
615 | u32 mask; | |
616 | ||
617 | do { | |
618 | pte = ptep[ARM_V7S_LVL_IDX(iova, ++lvl)]; | |
619 | ptep = iopte_deref(pte, lvl); | |
620 | } while (ARM_V7S_PTE_IS_TABLE(pte, lvl)); | |
621 | ||
622 | if (!ARM_V7S_PTE_IS_VALID(pte)) | |
623 | return 0; | |
624 | ||
625 | mask = ARM_V7S_LVL_MASK(lvl); | |
626 | if (arm_v7s_pte_is_cont(pte, lvl)) | |
627 | mask *= ARM_V7S_CONT_PAGES; | |
628 | return (pte & mask) | (iova & ~mask); | |
629 | } | |
630 | ||
631 | static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, | |
632 | void *cookie) | |
633 | { | |
634 | struct arm_v7s_io_pgtable *data; | |
635 | ||
636 | if (cfg->ias > ARM_V7S_ADDR_BITS || cfg->oas > ARM_V7S_ADDR_BITS) | |
637 | return NULL; | |
638 | ||
3850db49 RM |
639 | if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | |
640 | IO_PGTABLE_QUIRK_NO_PERMS | | |
1afe2319 YW |
641 | IO_PGTABLE_QUIRK_TLBI_ON_MAP | |
642 | IO_PGTABLE_QUIRK_ARM_MTK_4GB)) | |
3850db49 RM |
643 | return NULL; |
644 | ||
1afe2319 YW |
645 | /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */ |
646 | if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB && | |
647 | !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS)) | |
648 | return NULL; | |
649 | ||
e5fc9753 RM |
650 | data = kmalloc(sizeof(*data), GFP_KERNEL); |
651 | if (!data) | |
652 | return NULL; | |
653 | ||
654 | data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2", | |
655 | ARM_V7S_TABLE_SIZE(2), | |
656 | ARM_V7S_TABLE_SIZE(2), | |
657 | SLAB_CACHE_DMA, NULL); | |
658 | if (!data->l2_tables) | |
659 | goto out_free_data; | |
660 | ||
661 | data->iop.ops = (struct io_pgtable_ops) { | |
662 | .map = arm_v7s_map, | |
663 | .unmap = arm_v7s_unmap, | |
664 | .iova_to_phys = arm_v7s_iova_to_phys, | |
665 | }; | |
666 | ||
667 | /* We have to do this early for __arm_v7s_alloc_table to work... */ | |
668 | data->iop.cfg = *cfg; | |
669 | ||
670 | /* | |
671 | * Unless the IOMMU driver indicates supersection support by | |
672 | * having SZ_16M set in the initial bitmap, they won't be used. | |
673 | */ | |
674 | cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M; | |
675 | ||
676 | /* TCR: T0SZ=0, disable TTBR1 */ | |
677 | cfg->arm_v7s_cfg.tcr = ARM_V7S_TCR_PD1; | |
678 | ||
679 | /* | |
680 | * TEX remap: the indices used map to the closest equivalent types | |
681 | * under the non-TEX-remap interpretation of those attribute bits, | |
682 | * excepting various implementation-defined aspects of shareability. | |
683 | */ | |
684 | cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) | | |
685 | ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) | | |
686 | ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) | | |
687 | ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 | | |
688 | ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7); | |
689 | cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) | | |
690 | ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA); | |
691 | ||
692 | /* Looking good; allocate a pgd */ | |
693 | data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data); | |
694 | if (!data->pgd) | |
695 | goto out_free_data; | |
696 | ||
697 | /* Ensure the empty pgd is visible before any actual TTBR write */ | |
698 | wmb(); | |
699 | ||
700 | /* TTBRs */ | |
701 | cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) | | |
702 | ARM_V7S_TTBR_S | ARM_V7S_TTBR_NOS | | |
703 | ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) | | |
704 | ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA); | |
705 | cfg->arm_v7s_cfg.ttbr[1] = 0; | |
706 | return &data->iop; | |
707 | ||
708 | out_free_data: | |
709 | kmem_cache_destroy(data->l2_tables); | |
710 | kfree(data); | |
711 | return NULL; | |
712 | } | |
713 | ||
714 | struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = { | |
715 | .alloc = arm_v7s_alloc_pgtable, | |
716 | .free = arm_v7s_free_pgtable, | |
717 | }; | |
718 | ||
719 | #ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST | |
720 | ||
721 | static struct io_pgtable_cfg *cfg_cookie; | |
722 | ||
723 | static void dummy_tlb_flush_all(void *cookie) | |
724 | { | |
725 | WARN_ON(cookie != cfg_cookie); | |
726 | } | |
727 | ||
728 | static void dummy_tlb_add_flush(unsigned long iova, size_t size, | |
729 | size_t granule, bool leaf, void *cookie) | |
730 | { | |
731 | WARN_ON(cookie != cfg_cookie); | |
732 | WARN_ON(!(size & cfg_cookie->pgsize_bitmap)); | |
733 | } | |
734 | ||
735 | static void dummy_tlb_sync(void *cookie) | |
736 | { | |
737 | WARN_ON(cookie != cfg_cookie); | |
738 | } | |
739 | ||
740 | static struct iommu_gather_ops dummy_tlb_ops = { | |
741 | .tlb_flush_all = dummy_tlb_flush_all, | |
742 | .tlb_add_flush = dummy_tlb_add_flush, | |
743 | .tlb_sync = dummy_tlb_sync, | |
744 | }; | |
745 | ||
746 | #define __FAIL(ops) ({ \ | |
747 | WARN(1, "selftest: test failed\n"); \ | |
748 | selftest_running = false; \ | |
749 | -EFAULT; \ | |
750 | }) | |
751 | ||
752 | static int __init arm_v7s_do_selftests(void) | |
753 | { | |
754 | struct io_pgtable_ops *ops; | |
755 | struct io_pgtable_cfg cfg = { | |
756 | .tlb = &dummy_tlb_ops, | |
757 | .oas = 32, | |
758 | .ias = 32, | |
759 | .quirks = IO_PGTABLE_QUIRK_ARM_NS, | |
760 | .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, | |
761 | }; | |
762 | unsigned int iova, size, iova_start; | |
763 | unsigned int i, loopnr = 0; | |
764 | ||
765 | selftest_running = true; | |
766 | ||
767 | cfg_cookie = &cfg; | |
768 | ||
769 | ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg); | |
770 | if (!ops) { | |
771 | pr_err("selftest: failed to allocate io pgtable ops\n"); | |
772 | return -EINVAL; | |
773 | } | |
774 | ||
775 | /* | |
776 | * Initial sanity checks. | |
777 | * Empty page tables shouldn't provide any translations. | |
778 | */ | |
779 | if (ops->iova_to_phys(ops, 42)) | |
780 | return __FAIL(ops); | |
781 | ||
782 | if (ops->iova_to_phys(ops, SZ_1G + 42)) | |
783 | return __FAIL(ops); | |
784 | ||
785 | if (ops->iova_to_phys(ops, SZ_2G + 42)) | |
786 | return __FAIL(ops); | |
787 | ||
788 | /* | |
789 | * Distinct mappings of different granule sizes. | |
790 | */ | |
791 | iova = 0; | |
792 | i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG); | |
793 | while (i != BITS_PER_LONG) { | |
794 | size = 1UL << i; | |
795 | if (ops->map(ops, iova, iova, size, IOMMU_READ | | |
796 | IOMMU_WRITE | | |
797 | IOMMU_NOEXEC | | |
798 | IOMMU_CACHE)) | |
799 | return __FAIL(ops); | |
800 | ||
801 | /* Overlapping mappings */ | |
802 | if (!ops->map(ops, iova, iova + size, size, | |
803 | IOMMU_READ | IOMMU_NOEXEC)) | |
804 | return __FAIL(ops); | |
805 | ||
806 | if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) | |
807 | return __FAIL(ops); | |
808 | ||
809 | iova += SZ_16M; | |
810 | i++; | |
811 | i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i); | |
812 | loopnr++; | |
813 | } | |
814 | ||
815 | /* Partial unmap */ | |
816 | i = 1; | |
817 | size = 1UL << __ffs(cfg.pgsize_bitmap); | |
818 | while (i < loopnr) { | |
819 | iova_start = i * SZ_16M; | |
820 | if (ops->unmap(ops, iova_start + size, size) != size) | |
821 | return __FAIL(ops); | |
822 | ||
823 | /* Remap of partial unmap */ | |
824 | if (ops->map(ops, iova_start + size, size, size, IOMMU_READ)) | |
825 | return __FAIL(ops); | |
826 | ||
827 | if (ops->iova_to_phys(ops, iova_start + size + 42) | |
828 | != (size + 42)) | |
829 | return __FAIL(ops); | |
830 | i++; | |
831 | } | |
832 | ||
833 | /* Full unmap */ | |
834 | iova = 0; | |
835 | i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG); | |
836 | while (i != BITS_PER_LONG) { | |
837 | size = 1UL << i; | |
838 | ||
839 | if (ops->unmap(ops, iova, size) != size) | |
840 | return __FAIL(ops); | |
841 | ||
842 | if (ops->iova_to_phys(ops, iova + 42)) | |
843 | return __FAIL(ops); | |
844 | ||
845 | /* Remap full block */ | |
846 | if (ops->map(ops, iova, iova, size, IOMMU_WRITE)) | |
847 | return __FAIL(ops); | |
848 | ||
849 | if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) | |
850 | return __FAIL(ops); | |
851 | ||
852 | iova += SZ_16M; | |
853 | i++; | |
854 | i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i); | |
855 | } | |
856 | ||
857 | free_io_pgtable_ops(ops); | |
858 | ||
859 | selftest_running = false; | |
860 | ||
861 | pr_info("self test ok\n"); | |
862 | return 0; | |
863 | } | |
864 | subsys_initcall(arm_v7s_do_selftests); | |
865 | #endif |