[deliverable/linux.git] / drivers / irqchip / Kconfig

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select MULTI_IRQ_HANDLER

config ARM_GIC_PM
	bool
	depends on PM
	select ARM_GIC
	select PM_CLK

config ARM_GIC_MAX_NR
	int
	default 2 if ARCH_REALVIEW
	default 1

config ARM_GIC_V2M
	bool
	depends on PCI
	select ARM_GIC
	select PCI_MSI

config GIC_NON_BANKED
	bool

config ARM_GIC_V3
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select IRQ_DOMAIN_HIERARCHY
	select PARTITION_PERCPU

config ARM_GIC_V3_ITS
	bool
	depends on PCI
	depends on PCI_MSI

config ARM_NVIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config ARMADA_370_XP_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select PCI_MSI if PCI

config ALPINE_MSI
	bool
	depends on PCI
	select PCI_MSI
	select GENERIC_IRQ_CHIP

config ATMEL_AIC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config ATMEL_AIC5_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config I8259
	bool
	select IRQ_DOMAIN

config BCM6345_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BCM7038_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BCM7120_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BRCMSTB_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config HISILICON_IRQ_MBIGEN
	bool
	select ARM_GIC_V3
	select ARM_GIC_V3_ITS

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IRQ_MIPS_CPU
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ
	default y

config OR1K_PIC
	bool
	select IRQ_DOMAIN

config OMAP_IRQCHIP
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config PIC32_EVIC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config JCORE_AIC
	bool "J-Core integrated AIC"
	depends on OF && (SUPERH || COMPILE_TEST)
	select IRQ_DOMAIN
	help
	  Support for the J-Core integrated AIC.

config RENESAS_INTC_IRQPIN
	bool
	select IRQ_DOMAIN

config RENESAS_IRQC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ST_IRQCHIP
	bool
	select REGMAP
	select MFD_SYSCON
	help
	  Enables SysCfg Controlled IRQs on STi based platforms.

config TANGO_IRQ
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TS4800_IRQ
	tristate "TS-4800 IRQ controller"
	select IRQ_DOMAIN
	depends on HAS_IOMEM
	depends on SOC_IMX51 || COMPILE_TEST
	help
	  Support for the TS-4800 FPGA IRQ controller

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that precedes the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.

config KEYSTONE_IRQ
	tristate "Keystone 2 IRQ controller IP"
	depends on ARCH_KEYSTONE
	help
		Support for Texas Instruments Keystone 2 IRQ controller IP which
		is part of the Keystone 2 IPC mechanism

config MIPS_GIC
	bool
	select GENERIC_IRQ_IPI
	select IRQ_DOMAIN_HIERARCHY
	select MIPS_CM

config INGENIC_IRQ
	bool
	depends on MACH_INGENIC
	default y

config RENESAS_H8300H_INTC
        bool
	select IRQ_DOMAIN

config RENESAS_H8S_INTC
        bool
	select IRQ_DOMAIN

config IMX_GPCV2
	bool
	select IRQ_DOMAIN
	help
	  Enables the wakeup IRQs for IMX platforms with GPCv2 block

config IRQ_MXS
	def_bool y if MACH_ASM9260 || ARCH_MXS
	select IRQ_DOMAIN
	select STMP_DEVICE

config MVEBU_ODMI
	bool

config MVEBU_PIC
	bool

config LS_SCFG_MSI
	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
	depends on PCI && PCI_MSI

config PARTITION_PERCPU
	bool

config EZNPS_GIC
	bool "NPS400 Global Interrupt Manager (GIM)"
	depends on ARC || (COMPILE_TEST && !64BIT)
	select IRQ_DOMAIN
	help
	  Support the EZchip NPS400 global interrupt controller
Commit	Line	Data
f6e916b8 TP	1	config IRQCHIP
	2	def_bool y
	3	depends on OF_IRQ
	4
81243e44 RH	5	config ARM_GIC
	6	bool
	7	select IRQ_DOMAIN
9a1091ef	8	select IRQ_DOMAIN_HIERARCHY
81243e44 RH	9	select MULTI_IRQ_HANDLER
81243e44 RH	10
9c8edddf JH	11	config ARM_GIC_PM
	12	bool
	13	depends on PM
	14	select ARM_GIC
	15	select PM_CLK
	16
a27d21e0 LW	17	config ARM_GIC_MAX_NR
	18	int
	19	default 2 if ARCH_REALVIEW
	20	default 1
	21
853a33ce SS	22	config ARM_GIC_V2M
853a33ce SS	23	bool
3ee80364 AB	24	depends on PCI
	25	select ARM_GIC
	26	select PCI_MSI
853a33ce	27
81243e44 RH	28	config GIC_NON_BANKED
	29	bool
	30
021f6537 MZ	31	config ARM_GIC_V3
	32	bool
	33	select IRQ_DOMAIN
	34	select MULTI_IRQ_HANDLER
443acc4f	35	select IRQ_DOMAIN_HIERARCHY
e3825ba1	36	select PARTITION_PERCPU
021f6537	37
19812729 MZ	38	config ARM_GIC_V3_ITS
19812729 MZ	39	bool
3ee80364 AB	40	depends on PCI
3ee80364 AB	41	depends on PCI_MSI
021f6537	42
292ec080 UKK	43	config ARM_NVIC
	44	bool
	45	select IRQ_DOMAIN
2d9f59f7	46	select IRQ_DOMAIN_HIERARCHY
292ec080 UKK	47	select GENERIC_IRQ_CHIP
292ec080 UKK	48
44430ec0 RH	49	config ARM_VIC
	50	bool
	51	select IRQ_DOMAIN
	52	select MULTI_IRQ_HANDLER
	53
	54	config ARM_VIC_NR
	55	int
	56	default 4 if ARCH_S5PV210
44430ec0 RH	57	default 2
	58	depends on ARM_VIC
	59	help
	60	The maximum number of VICs available in the system, for
	61	power management.
	62
fed6d336 TP	63	config ARMADA_370_XP_IRQ
fed6d336 TP	64	bool
fed6d336	65	select GENERIC_IRQ_CHIP
3ee80364	66	select PCI_MSI if PCI
fed6d336	67
e6b78f2c AT	68	config ALPINE_MSI
e6b78f2c AT	69	bool
3ee80364 AB	70	depends on PCI
3ee80364 AB	71	select PCI_MSI
e6b78f2c	72	select GENERIC_IRQ_CHIP
e6b78f2c	73
b1479ebb BB	74	config ATMEL_AIC_IRQ
	75	bool
	76	select GENERIC_IRQ_CHIP
	77	select IRQ_DOMAIN
	78	select MULTI_IRQ_HANDLER
	79	select SPARSE_IRQ
	80
	81	config ATMEL_AIC5_IRQ
	82	bool
	83	select GENERIC_IRQ_CHIP
	84	select IRQ_DOMAIN
	85	select MULTI_IRQ_HANDLER
	86	select SPARSE_IRQ
	87
0509cfde RB	88	config I8259
	89	bool
	90	select IRQ_DOMAIN
	91
c7c42ec2 SA	92	config BCM6345_L1_IRQ
	93	bool
	94	select GENERIC_IRQ_CHIP
	95	select IRQ_DOMAIN
	96
5f7f0317 KC	97	config BCM7038_L1_IRQ
	98	bool
	99	select GENERIC_IRQ_CHIP
	100	select IRQ_DOMAIN
	101
a4fcbb86 KC	102	config BCM7120_L2_IRQ
	103	bool
	104	select GENERIC_IRQ_CHIP
	105	select IRQ_DOMAIN
	106
7f646e92 FF	107	config BRCMSTB_L2_IRQ
7f646e92 FF	108	bool
7f646e92 FF	109	select GENERIC_IRQ_CHIP
	110	select IRQ_DOMAIN
	111
350d71b9 SH	112	config DW_APB_ICTL
350d71b9 SH	113	bool
e1588490	114	select GENERIC_IRQ_CHIP
350d71b9 SH	115	select IRQ_DOMAIN
350d71b9 SH	116
9a7c4abd M	117	config HISILICON_IRQ_MBIGEN
	118	bool
	119	select ARM_GIC_V3
	120	select ARM_GIC_V3_ITS
9a7c4abd	121
b6ef9161 JH	122	config IMGPDC_IRQ
	123	bool
	124	select GENERIC_IRQ_CHIP
	125	select IRQ_DOMAIN
	126
67e38cf2 RB	127	config IRQ_MIPS_CPU
	128	bool
	129	select GENERIC_IRQ_CHIP
	130	select IRQ_DOMAIN
	131
afc98d90 AS	132	config CLPS711X_IRQCHIP
	133	bool
	134	depends on ARCH_CLPS711X
	135	select IRQ_DOMAIN
	136	select MULTI_IRQ_HANDLER
	137	select SPARSE_IRQ
	138	default y
	139
4db8e6d2 SK	140	config OR1K_PIC
	141	bool
	142	select IRQ_DOMAIN
	143
8598066c FB	144	config OMAP_IRQCHIP
	145	bool
	146	select GENERIC_IRQ_CHIP
	147	select IRQ_DOMAIN
	148
9dbd90f1 SH	149	config ORION_IRQCHIP
	150	bool
	151	select IRQ_DOMAIN
	152	select MULTI_IRQ_HANDLER
	153
aaa8666a CB	154	config PIC32_EVIC
	155	bool
	156	select GENERIC_IRQ_CHIP
	157	select IRQ_DOMAIN
	158
981b58f6 RF	159	config JCORE_AIC
	160	bool "J-Core integrated AIC"
	161	depends on OF && (SUPERH \|\| COMPILE_TEST)
	162	select IRQ_DOMAIN
	163	help
	164	Support for the J-Core integrated AIC.
	165
44358048 MD	166	config RENESAS_INTC_IRQPIN
	167	bool
	168	select IRQ_DOMAIN
	169
fbc83b7f MD	170	config RENESAS_IRQC
fbc83b7f MD	171	bool
99c221df	172	select GENERIC_IRQ_CHIP
fbc83b7f MD	173	select IRQ_DOMAIN
fbc83b7f MD	174
07088484 LJ	175	config ST_IRQCHIP
	176	bool
	177	select REGMAP
	178	select MFD_SYSCON
	179	help
	180	Enables SysCfg Controlled IRQs on STi based platforms.
	181
4bba6689 MR	182	config TANGO_IRQ
	183	bool
	184	select IRQ_DOMAIN
	185	select GENERIC_IRQ_CHIP
	186
b06eb017 CR	187	config TB10X_IRQC
	188	bool
	189	select IRQ_DOMAIN
	190	select GENERIC_IRQ_CHIP
	191
d01f8633 DR	192	config TS4800_IRQ
	193	tristate "TS-4800 IRQ controller"
	194	select IRQ_DOMAIN
0df337cf	195	depends on HAS_IOMEM
d2b383dc	196	depends on SOC_IMX51 \|\| COMPILE_TEST
d01f8633 DR	197	help
	198	Support for the TS-4800 FPGA IRQ controller
	199
2389d501 LW	200	config VERSATILE_FPGA_IRQ
	201	bool
	202	select IRQ_DOMAIN
	203
	204	config VERSATILE_FPGA_IRQ_NR
	205	int
	206	default 4
	207	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	208
	209	config XTENSA_MX
	210	bool
	211	select IRQ_DOMAIN
96ca848e S	212
	213	config IRQ_CROSSBAR
	214	bool
	215	help
f54619f2	216	Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e S	217	The primary irqchip invokes the crossbar's callback which inturn allocates
	218	a free irq and configures the IP. Thus the peripheral interrupts are
	219	routed to one of the free irqchip interrupt lines.
89323f8c GS	220
	221	config KEYSTONE_IRQ
	222	tristate "Keystone 2 IRQ controller IP"
	223	depends on ARCH_KEYSTONE
	224	help
	225	Support for Texas Instruments Keystone 2 IRQ controller IP which
	226	is part of the Keystone 2 IPC mechanism
8a19b8f1 AB	227
	228	config MIPS_GIC
	229	bool
bb11cff3	230	select GENERIC_IRQ_IPI
2af70a96	231	select IRQ_DOMAIN_HIERARCHY
8a19b8f1	232	select MIPS_CM
8a764482	233
44e08e70 PB	234	config INGENIC_IRQ
	235	bool
	236	depends on MACH_INGENIC
	237	default y
78c10e55	238
8a764482 YS	239	config RENESAS_H8300H_INTC
	240	bool
	241	select IRQ_DOMAIN
	242
	243	config RENESAS_H8S_INTC
	244	bool
78c10e55	245	select IRQ_DOMAIN
e324c4dc SW	246
	247	config IMX_GPCV2
	248	bool
	249	select IRQ_DOMAIN
	250	help
	251	Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676 OR	252
	253	config IRQ_MXS
	254	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
	255	select IRQ_DOMAIN
	256	select STMP_DEVICE
c27f29bb TP	257
	258	config MVEBU_ODMI
	259	bool
9e2c986c	260
a109893b TP	261	config MVEBU_PIC
	262	bool
	263
b8f3ebe6 ML	264	config LS_SCFG_MSI
	265	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
	266	depends on PCI && PCI_MSI
b8f3ebe6	267
9e2c986c MZ	268	config PARTITION_PERCPU
9e2c986c MZ	269	bool
0efacbba	270
44df427c NC	271	config EZNPS_GIC
44df427c NC	272	bool "NPS400 Global Interrupt Manager (GIM)"
ffd565e3	273	depends on ARC \|\| (COMPILE_TEST && !64BIT)
44df427c NC	274	select IRQ_DOMAIN
	275	help
	276	Support the EZchip NPS400 global interrupt controller