[deliverable/linux.git] / drivers / irqchip / irq-sunxi-nmi.c

/*
 * Allwinner A20/A31 SoCs NMI IRQ chip driver.
 *
 * Carlo Caione <carlo.caione@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#define DRV_NAME	"sunxi-nmi"
#define pr_fmt(fmt)	DRV_NAME ": " fmt

#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>

#define SUNXI_NMI_SRC_TYPE_MASK	0x00000003

enum {
	SUNXI_SRC_TYPE_LEVEL_LOW = 0,
	SUNXI_SRC_TYPE_EDGE_FALLING,
	SUNXI_SRC_TYPE_LEVEL_HIGH,
	SUNXI_SRC_TYPE_EDGE_RISING,
};

struct sunxi_sc_nmi_reg_offs {
	u32 ctrl;
	u32 pend;
	u32 enable;
};

static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = {
	.ctrl	= 0x00,
	.pend	= 0x04,
	.enable	= 0x08,
};

static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
	.ctrl	= 0x00,
	.pend	= 0x04,
	.enable	= 0x34,
};

static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
	.ctrl	= 0x00,
	.pend	= 0x08,
	.enable	= 0x04,
};

static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
				      u32 val)
{
	irq_reg_writel(gc, val, off);
}

static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
{
	return irq_reg_readl(gc, off);
}

static void sunxi_sc_nmi_handle_irq(struct irq_desc *desc)
{
	struct irq_domain *domain = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int virq = irq_find_mapping(domain, 0);

	chained_irq_enter(chip, desc);
	generic_handle_irq(virq);
	chained_irq_exit(chip, desc);
}

static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	struct irq_chip_type *ct = gc->chip_types;
	u32 src_type_reg;
	u32 ctrl_off = ct->regs.type;
	unsigned int src_type;
	unsigned int i;

	irq_gc_lock(gc);

	switch (flow_type & IRQF_TRIGGER_MASK) {
	case IRQ_TYPE_EDGE_FALLING:
		src_type = SUNXI_SRC_TYPE_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_RISING:
		src_type = SUNXI_SRC_TYPE_EDGE_RISING;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		src_type = SUNXI_SRC_TYPE_LEVEL_HIGH;
		break;
	case IRQ_TYPE_NONE:
	case IRQ_TYPE_LEVEL_LOW:
		src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
		break;
	default:
		irq_gc_unlock(gc);
		pr_err("Cannot assign multiple trigger modes to IRQ %d.\n",
			data->irq);
		return -EBADR;
	}

	irqd_set_trigger_type(data, flow_type);
	irq_setup_alt_chip(data, flow_type);

	for (i = 0; i < gc->num_ct; i++, ct++)
		if (ct->type & flow_type)
			ctrl_off = ct->regs.type;

	src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
	src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK;
	src_type_reg |= src_type;
	sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);

	irq_gc_unlock(gc);

	return IRQ_SET_MASK_OK;
}

static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
					struct sunxi_sc_nmi_reg_offs *reg_offs)
{
	struct irq_domain *domain;
	struct irq_chip_generic *gc;
	unsigned int irq;
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	int ret;


	domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
	if (!domain) {
		pr_err("Could not register interrupt domain.\n");
		return -ENOMEM;
	}

	ret = irq_alloc_domain_generic_chips(domain, 1, 2, DRV_NAME,
					     handle_fasteoi_irq, clr, 0,
					     IRQ_GC_INIT_MASK_CACHE);
	if (ret) {
		pr_err("Could not allocate generic interrupt chip.\n");
		goto fail_irqd_remove;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0) {
		pr_err("unable to parse irq\n");
		ret = -EINVAL;
		goto fail_irqd_remove;
	}

	gc = irq_get_domain_generic_chip(domain, 0);
	gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(gc->reg_base)) {
		pr_err("unable to map resource\n");
		ret = PTR_ERR(gc->reg_base);
		goto fail_irqd_remove;
	}

	gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;
	gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;
	gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;
	gc->chip_types[0].chip.irq_eoi		= irq_gc_ack_set_bit;
	gc->chip_types[0].chip.irq_set_type	= sunxi_sc_nmi_set_type;
	gc->chip_types[0].chip.flags		= IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED;
	gc->chip_types[0].regs.ack		= reg_offs->pend;
	gc->chip_types[0].regs.mask		= reg_offs->enable;
	gc->chip_types[0].regs.type		= reg_offs->ctrl;

	gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;
	gc->chip_types[1].chip.name		= gc->chip_types[0].chip.name;
	gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;
	gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;
	gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;
	gc->chip_types[1].chip.irq_set_type	= sunxi_sc_nmi_set_type;
	gc->chip_types[1].regs.ack		= reg_offs->pend;
	gc->chip_types[1].regs.mask		= reg_offs->enable;
	gc->chip_types[1].regs.type		= reg_offs->ctrl;
	gc->chip_types[1].handler		= handle_edge_irq;

	sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
	sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1);

	irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain);

	return 0;

fail_irqd_remove:
	irq_domain_remove(domain);

	return ret;
}

static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
					struct device_node *parent)
{
	return sunxi_sc_nmi_irq_init(node, &sun6i_reg_offs);
}
IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_irq_init);

static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
					struct device_node *parent)
{
	return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
}
IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);

static int __init sun9i_nmi_irq_init(struct device_node *node,
				     struct device_node *parent)
{
	return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs);
}
IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);
Commit	Line	Data
6058bb36 CC	1	/*
	2	* Allwinner A20/A31 SoCs NMI IRQ chip driver.
	3	*
	4	* Carlo Caione <carlo.caione@gmail.com>
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
2d6caaed CYT	11	#define DRV_NAME "sunxi-nmi"
	12	#define pr_fmt(fmt) DRV_NAME ": " fmt
	13
6058bb36 CC	14	#include <linux/bitops.h>
	15	#include <linux/device.h>
	16	#include <linux/io.h>
	17	#include <linux/irq.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/irqdomain.h>
	20	#include <linux/of_irq.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_platform.h>
41a83e06	23	#include <linux/irqchip.h>
6058bb36	24	#include <linux/irqchip/chained_irq.h>
6058bb36 CC	25
	26	#define SUNXI_NMI_SRC_TYPE_MASK 0x00000003
	27
	28	enum {
	29	SUNXI_SRC_TYPE_LEVEL_LOW = 0,
	30	SUNXI_SRC_TYPE_EDGE_FALLING,
	31	SUNXI_SRC_TYPE_LEVEL_HIGH,
	32	SUNXI_SRC_TYPE_EDGE_RISING,
	33	};
	34
	35	struct sunxi_sc_nmi_reg_offs {
	36	u32 ctrl;
	37	u32 pend;
	38	u32 enable;
	39	};
	40
	41	static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = {
	42	.ctrl = 0x00,
	43	.pend = 0x04,
	44	.enable = 0x08,
	45	};
	46
	47	static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
	48	.ctrl = 0x00,
	49	.pend = 0x04,
	50	.enable = 0x34,
	51	};
	52
bbbb03c1 CYT	53	static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
	54	.ctrl = 0x00,
	55	.pend = 0x08,
	56	.enable = 0x04,
	57	};
	58
6058bb36 CC	59	static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
	60	u32 val)
	61	{
332fd7c4	62	irq_reg_writel(gc, val, off);
6058bb36 CC	63	}
	64
	65	static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
	66	{
332fd7c4	67	return irq_reg_readl(gc, off);
6058bb36 CC	68	}
6058bb36 CC	69
bd0b9ac4	70	static void sunxi_sc_nmi_handle_irq(struct irq_desc *desc)
6058bb36 CC	71	{
6058bb36 CC	72	struct irq_domain *domain = irq_desc_get_handler_data(desc);
5b29264c	73	struct irq_chip *chip = irq_desc_get_chip(desc);
6058bb36 CC	74	unsigned int virq = irq_find_mapping(domain, 0);
	75
	76	chained_irq_enter(chip, desc);
	77	generic_handle_irq(virq);
	78	chained_irq_exit(chip, desc);
	79	}
	80
	81	static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
	82	{
	83	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	84	struct irq_chip_type *ct = gc->chip_types;
	85	u32 src_type_reg;
	86	u32 ctrl_off = ct->regs.type;
	87	unsigned int src_type;
	88	unsigned int i;
	89
	90	irq_gc_lock(gc);
	91
	92	switch (flow_type & IRQF_TRIGGER_MASK) {
	93	case IRQ_TYPE_EDGE_FALLING:
	94	src_type = SUNXI_SRC_TYPE_EDGE_FALLING;
	95	break;
	96	case IRQ_TYPE_EDGE_RISING:
	97	src_type = SUNXI_SRC_TYPE_EDGE_RISING;
	98	break;
	99	case IRQ_TYPE_LEVEL_HIGH:
	100	src_type = SUNXI_SRC_TYPE_LEVEL_HIGH;
	101	break;
	102	case IRQ_TYPE_NONE:
	103	case IRQ_TYPE_LEVEL_LOW:
	104	src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
	105	break;
	106	default:
	107	irq_gc_unlock(gc);
2d6caaed CYT	108	pr_err("Cannot assign multiple trigger modes to IRQ %d.\n",
2d6caaed CYT	109	data->irq);
6058bb36 CC	110	return -EBADR;
	111	}
	112
	113	irqd_set_trigger_type(data, flow_type);
	114	irq_setup_alt_chip(data, flow_type);
	115
febe0696	116	for (i = 0; i < gc->num_ct; i++, ct++)
6058bb36 CC	117	if (ct->type & flow_type)
	118	ctrl_off = ct->regs.type;
	119
	120	src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
	121	src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK;
	122	src_type_reg \|= src_type;
	123	sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
	124
	125	irq_gc_unlock(gc);
	126
	127	return IRQ_SET_MASK_OK;
	128	}
	129
	130	static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
	131	struct sunxi_sc_nmi_reg_offs *reg_offs)
	132	{
	133	struct irq_domain *domain;
	134	struct irq_chip_generic *gc;
	135	unsigned int irq;
	136	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	137	int ret;
	138
	139
	140	domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
	141	if (!domain) {
2d6caaed	142	pr_err("Could not register interrupt domain.\n");
6058bb36 CC	143	return -ENOMEM;
	144	}
	145
2d6caaed	146	ret = irq_alloc_domain_generic_chips(domain, 1, 2, DRV_NAME,
6058bb36 CC	147	handle_fasteoi_irq, clr, 0,
	148	IRQ_GC_INIT_MASK_CACHE);
	149	if (ret) {
2d6caaed CYT	150	pr_err("Could not allocate generic interrupt chip.\n");
2d6caaed CYT	151	goto fail_irqd_remove;
6058bb36 CC	152	}
	153
	154	irq = irq_of_parse_and_map(node, 0);
	155	if (irq <= 0) {
2d6caaed	156	pr_err("unable to parse irq\n");
6058bb36 CC	157	ret = -EINVAL;
	158	goto fail_irqd_remove;
	159	}
	160
	161	gc = irq_get_domain_generic_chip(domain, 0);
0e841b04	162	gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));
cfe199af	163	if (IS_ERR(gc->reg_base)) {
2d6caaed	164	pr_err("unable to map resource\n");
cfe199af	165	ret = PTR_ERR(gc->reg_base);
6058bb36 CC	166	goto fail_irqd_remove;
	167	}
	168
	169	gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	170	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
	171	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
	172	gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit;
	173	gc->chip_types[0].chip.irq_set_type = sunxi_sc_nmi_set_type;
	174	gc->chip_types[0].chip.flags = IRQCHIP_EOI_THREADED \| IRQCHIP_EOI_IF_HANDLED;
	175	gc->chip_types[0].regs.ack = reg_offs->pend;
	176	gc->chip_types[0].regs.mask = reg_offs->enable;
	177	gc->chip_types[0].regs.type = reg_offs->ctrl;
	178
	179	gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	180	gc->chip_types[1].chip.name = gc->chip_types[0].chip.name;
	181	gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
	182	gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
	183	gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
	184	gc->chip_types[1].chip.irq_set_type = sunxi_sc_nmi_set_type;
	185	gc->chip_types[1].regs.ack = reg_offs->pend;
	186	gc->chip_types[1].regs.mask = reg_offs->enable;
	187	gc->chip_types[1].regs.type = reg_offs->ctrl;
	188	gc->chip_types[1].handler = handle_edge_irq;
	189
6058bb36 CC	190	sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
	191	sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1);
	192
3200a712	193	irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain);
1b422ecd	194
6058bb36 CC	195	return 0;
	196
	197	fail_irqd_remove:
	198	irq_domain_remove(domain);
	199
	200	return ret;
	201	}
	202
	203	static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
	204	struct device_node *parent)
	205	{
	206	return sunxi_sc_nmi_irq_init(node, &sun6i_reg_offs);
	207	}
	208	IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_irq_init);
	209
	210	static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
	211	struct device_node *parent)
	212	{
	213	return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
	214	}
	215	IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
bbbb03c1 CYT	216
	217	static int __init sun9i_nmi_irq_init(struct device_node *node,
	218	struct device_node *parent)
	219	{
	220	return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs);
	221	}
	222	IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);