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Merge remote-tracking branch 'xen-tip/linux-next'
[deliverable/linux.git] / drivers / media / dvb-frontends / mb86a20s.c
CommitLineData
b9ede79a
MCC		 1/*
2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
3 *
37e59f87 4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab
b9ede79a
MCC		 5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
6 *
b9ede79a
MCC		 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <asm/div64.h>
19
20#include "dvb_frontend.h"
21#include "mb86a20s.h"
22
4f62a20d
MCC		 23#define NUM_LAYERS 3
24
04fa725e
MCC		 25enum mb86a20s_bandwidth {
26 MB86A20S_13SEG = 0,
27 MB86A20S_13SEG_PARTIAL = 1,
28 MB86A20S_1SEG = 2,
29 MB86A20S_3SEG = 3,
30};
31
ce08131c 32static u8 mb86a20s_subchannel[] = {
04fa725e
MCC		 33 0xb0, 0xc0, 0xd0, 0xe0,
34 0xf0, 0x00, 0x10, 0x20,
35};
36
b9ede79a
MCC		 37struct mb86a20s_state {
38 struct i2c_adapter *i2c;
39 const struct mb86a20s_config *config;
09b6d21e 40 u32 last_frequency;
b9ede79a
MCC		 41
42 struct dvb_frontend frontend;
c736a5f2 43
768e6dad 44 u32 if_freq;
04fa725e
MCC		 45 enum mb86a20s_bandwidth bw;
46 bool inversion;
47 u32 subchannel;
768e6dad 48
4f62a20d 49 u32 estimated_rate[NUM_LAYERS];
0921ecfd 50 unsigned long get_strength_time;
d01a8ee3 51
c736a5f2 52 bool need_init;
b9ede79a
MCC		 53};
54
55struct regdata {
56 u8 reg;
57 u8 data;
58};
59
d01a8ee3
MCC		 60#define BER_SAMPLING_RATE 1 /* Seconds */
61
b9ede79a
MCC		 62/*
63 * Initialization sequence: Use whatevere default values that PV SBTVD
64 * does on its initialisation, obtained via USB snoop
65 */
768e6dad 66static struct regdata mb86a20s_init1[] = {
b9ede79a
MCC		 67 { 0x70, 0x0f },
68 { 0x70, 0xff },
69 { 0x08, 0x01 },
17e67d4c 70 { 0x50, 0xd1 }, { 0x51, 0x20 },
768e6dad
MCC		 71};
72
73static struct regdata mb86a20s_init2[] = {
505a0ea7
MCC		 74 { 0x50, 0xd1 }, { 0x51, 0x22 },
75 { 0x39, 0x01 },
76 { 0x71, 0x00 },
b9ede79a 77 { 0x3b, 0x21 },
505a0ea7 78 { 0x3c, 0x3a },
b9ede79a 79 { 0x01, 0x0d },
505a0ea7 80 { 0x04, 0x08 }, { 0x05, 0x05 },
a7025edf 81 { 0x04, 0x0e }, { 0x05, 0x00 },
505a0ea7
MCC		 82 { 0x04, 0x0f }, { 0x05, 0x14 },
83 { 0x04, 0x0b }, { 0x05, 0x8c },
a7025edf 84 { 0x04, 0x00 }, { 0x05, 0x00 },
505a0ea7
MCC		 85 { 0x04, 0x01 }, { 0x05, 0x07 },
86 { 0x04, 0x02 }, { 0x05, 0x0f },
87 { 0x04, 0x03 }, { 0x05, 0xa0 },
a7025edf
MCC		 88 { 0x04, 0x09 }, { 0x05, 0x00 },
89 { 0x04, 0x0a }, { 0x05, 0xff },
505a0ea7 90 { 0x04, 0x27 }, { 0x05, 0x64 },
a7025edf 91 { 0x04, 0x28 }, { 0x05, 0x00 },
505a0ea7
MCC		 92 { 0x04, 0x1e }, { 0x05, 0xff },
93 { 0x04, 0x29 }, { 0x05, 0x0a },
94 { 0x04, 0x32 }, { 0x05, 0x0a },
a7025edf
MCC		 95 { 0x04, 0x14 }, { 0x05, 0x02 },
96 { 0x04, 0x04 }, { 0x05, 0x00 },
97 { 0x04, 0x05 }, { 0x05, 0x22 },
98 { 0x04, 0x06 }, { 0x05, 0x0e },
99 { 0x04, 0x07 }, { 0x05, 0xd8 },
100 { 0x04, 0x12 }, { 0x05, 0x00 },
101 { 0x04, 0x13 }, { 0x05, 0xff },
09b6d21e
MCC		 102
103 /*
104 * On this demod, when the bit count reaches the count below,
105 * it collects the bit error count. The bit counters are initialized
106 * to 65535 here. This warrants that all of them will be quickly
107 * calculated when device gets locked. As TMCC is parsed, the values
d01a8ee3 108 * will be adjusted later in the driver's code.
09b6d21e
MCC		 109 */
110 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
111 { 0x50, 0xa7 }, { 0x51, 0x00 },
a7025edf
MCC		 112 { 0x50, 0xa8 }, { 0x51, 0xff },
113 { 0x50, 0xa9 }, { 0x51, 0xff },
09b6d21e 114 { 0x50, 0xaa }, { 0x51, 0x00 },
a7025edf
MCC		 115 { 0x50, 0xab }, { 0x51, 0xff },
116 { 0x50, 0xac }, { 0x51, 0xff },
09b6d21e 117 { 0x50, 0xad }, { 0x51, 0x00 },
a7025edf
MCC		 118 { 0x50, 0xae }, { 0x51, 0xff },
119 { 0x50, 0xaf }, { 0x51, 0xff },
09b6d21e 120
d9b6f08a
MCC		 121 /*
122 * On this demod, post BER counts blocks. When the count reaches the
123 * value below, it collects the block error count. The block counters
124 * are initialized to 127 here. This warrants that all of them will be
125 * quickly calculated when device gets locked. As TMCC is parsed, the
126 * values will be adjusted later in the driver's code.
127 */
128 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
129 { 0x50, 0xdc }, { 0x51, 0x00 },
130 { 0x50, 0xdd }, { 0x51, 0x7f },
131 { 0x50, 0xde }, { 0x51, 0x00 },
132 { 0x50, 0xdf }, { 0x51, 0x7f },
133 { 0x50, 0xe0 }, { 0x51, 0x00 },
134 { 0x50, 0xe1 }, { 0x51, 0x7f },
593ae89a
MCC		 135
136 /*
137 * On this demod, when the block count reaches the count below,
138 * it collects the block error count. The block counters are initialized
139 * to 127 here. This warrants that all of them will be quickly
140 * calculated when device gets locked. As TMCC is parsed, the values
141 * will be adjusted later in the driver's code.
142 */
143 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
144 { 0x50, 0xb2 }, { 0x51, 0x00 },
145 { 0x50, 0xb3 }, { 0x51, 0x7f },
146 { 0x50, 0xb4 }, { 0x51, 0x00 },
147 { 0x50, 0xb5 }, { 0x51, 0x7f },
148 { 0x50, 0xb6 }, { 0x51, 0x00 },
149 { 0x50, 0xb7 }, { 0x51, 0x7f },
25188bd0
MCC		 150
151 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
09b6d21e
MCC		 152 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
153 { 0x45, 0x04 }, /* CN symbol 4 */
25188bd0 154 { 0x48, 0x04 }, /* CN manual mode */
505a0ea7 155 { 0x50, 0xd5 }, { 0x51, 0x01 },
a7025edf
MCC		 156 { 0x50, 0xd6 }, { 0x51, 0x1f },
157 { 0x50, 0xd2 }, { 0x51, 0x03 },
505a0ea7 158 { 0x50, 0xd7 }, { 0x51, 0x3f },
b9ede79a 159 { 0x1c, 0x01 },
505a0ea7
MCC		 160 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
161 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
162 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
163 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
164 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
165 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
166 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
167 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
168 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
169 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
170 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
171 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
172 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
173 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
174 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
175 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
176 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
177 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
178 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
179 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
180 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
181 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
182 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
183 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
184 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
a7025edf
MCC		 185 { 0x50, 0x1e }, { 0x51, 0x5d },
186 { 0x50, 0x22 }, { 0x51, 0x00 },
187 { 0x50, 0x23 }, { 0x51, 0xc8 },
188 { 0x50, 0x24 }, { 0x51, 0x00 },
189 { 0x50, 0x25 }, { 0x51, 0xf0 },
190 { 0x50, 0x26 }, { 0x51, 0x00 },
191 { 0x50, 0x27 }, { 0x51, 0xc3 },
192 { 0x50, 0x39 }, { 0x51, 0x02 },
505a0ea7 193 { 0x50, 0xd5 }, { 0x51, 0x01 },
b9ede79a
MCC		 194 { 0xd0, 0x00 },
195};
196
197static struct regdata mb86a20s_reset_reception[] = {
198 { 0x70, 0xf0 },
199 { 0x70, 0xff },
200 { 0x08, 0x01 },
201 { 0x08, 0x00 },
202};
203
d9b6f08a
MCC		 204static struct regdata mb86a20s_per_ber_reset[] = {
205 { 0x53, 0x00 }, /* pre BER Counter reset */
09b6d21e 206 { 0x53, 0x07 },
09b6d21e 207
d9b6f08a
MCC		 208 { 0x5f, 0x00 }, /* post BER Counter reset */
209 { 0x5f, 0x07 },
210
09b6d21e
MCC		 211 { 0x50, 0xb1 }, /* PER Counter reset */
212 { 0x51, 0x07 },
213 { 0x51, 0x00 },
214};
215
dd4493ef
MCC		 216/*
217 * I2C read/write functions and macros
218 */
219
b9ede79a 220static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
09b6d21e 221 u8 i2c_addr, u8 reg, u8 data)
b9ede79a
MCC		 222{
223 u8 buf[] = { reg, data };
224 struct i2c_msg msg = {
225 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
226 };
227 int rc;
228
229 rc = i2c_transfer(state->i2c, &msg, 1);
230 if (rc != 1) {
f66d81b5
MCC		 231 dev_err(&state->i2c->dev,
232 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
233 __func__, rc, reg, data);
b9ede79a
MCC		 234 return rc;
235 }
236
237 return 0;
238}
239
240static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
241 u8 i2c_addr, struct regdata *rd, int size)
242{
243 int i, rc;
244
245 for (i = 0; i < size; i++) {
246 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
247 rd[i].data);
248 if (rc < 0)
249 return rc;
250 }
251 return 0;
252}
253
254static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
255 u8 i2c_addr, u8 reg)
256{
257 u8 val;
258 int rc;
259 struct i2c_msg msg[] = {
260 { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
261 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
262 };
263
264 rc = i2c_transfer(state->i2c, msg, 2);
265
266 if (rc != 2) {
f66d81b5
MCC		 267 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
268 __func__, reg, rc);
269 return (rc < 0) ? rc : -EIO;
b9ede79a
MCC		 270 }
271
272 return val;
273}
274
275#define mb86a20s_readreg(state, reg) \
276 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
277#define mb86a20s_writereg(state, reg, val) \
278 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
279#define mb86a20s_writeregdata(state, regdata) \
280 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
281 regdata, ARRAY_SIZE(regdata))
282
09b6d21e
MCC		 283/*
284 * Ancillary internal routines (likely compiled inlined)
285 *
286 * The functions below assume that gateway lock has already obtained
287 */
288
0df289a2 289static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status)
b9ede79a
MCC		 290{
291 struct mb86a20s_state *state = fe->demodulator_priv;
dd4493ef 292 int val;
b9ede79a 293
dd4493ef 294 *status = 0;
b9ede79a 295
eca2d34b 296 val = mb86a20s_readreg(state, 0x0a);
dd4493ef
MCC		 297 if (val < 0)
298 return val;
68541cda 299
eca2d34b 300 val &= 0xf;
dd4493ef
MCC		 301 if (val >= 2)
302 *status |= FE_HAS_SIGNAL;
b9ede79a 303
dd4493ef
MCC		 304 if (val >= 4)
305 *status |= FE_HAS_CARRIER;
7572f9c5 306
dd4493ef
MCC		 307 if (val >= 5)
308 *status |= FE_HAS_VITERBI;
7572f9c5 309
dd4493ef
MCC		 310 if (val >= 7)
311 *status |= FE_HAS_SYNC;
68541cda 312
dafb65fb
MCC		 313 /*
314 * Actually, on state S8, it starts receiving TS, but the TS
315 * output is only on normal state after the transition to S9.
316 */
317 if (val >= 9)
dd4493ef
MCC		 318 *status |= FE_HAS_LOCK;
319
f66d81b5
MCC		 320 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
321 __func__, *status, val);
dd4493ef 322
15b1c5a0 323 return val;
b9ede79a
MCC		 324}
325
09b6d21e 326static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
b9ede79a
MCC		 327{
328 struct mb86a20s_state *state = fe->demodulator_priv;
0921ecfd 329 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
09b6d21e 330 int rc;
b9ede79a 331 unsigned rf_max, rf_min, rf;
68541cda 332
0921ecfd
MCC		 333 if (state->get_strength_time &&
334 (!time_after(jiffies, state->get_strength_time)))
335 return c->strength.stat[0].uvalue;
336
337 /* Reset its value if an error happen */
338 c->strength.stat[0].uvalue = 0;
339
b9ede79a
MCC		 340 /* Does a binary search to get RF strength */
341 rf_max = 0xfff;
342 rf_min = 0;
343 do {
344 rf = (rf_max + rf_min) / 2;
09b6d21e
MCC		 345 rc = mb86a20s_writereg(state, 0x04, 0x1f);
346 if (rc < 0)
347 return rc;
348 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
349 if (rc < 0)
350 return rc;
351 rc = mb86a20s_writereg(state, 0x04, 0x20);
352 if (rc < 0)
353 return rc;
dad78c56 354 rc = mb86a20s_writereg(state, 0x05, rf);
09b6d21e
MCC		 355 if (rc < 0)
356 return rc;
b9ede79a 357
09b6d21e
MCC		 358 rc = mb86a20s_readreg(state, 0x02);
359 if (rc < 0)
360 return rc;
361 if (rc & 0x08)
b9ede79a
MCC		 362 rf_min = (rf_max + rf_min) / 2;
363 else
364 rf_max = (rf_max + rf_min) / 2;
365 if (rf_max - rf_min < 4) {
09b6d21e
MCC		 366 rf = (rf_max + rf_min) / 2;
367
368 /* Rescale it from 2^12 (4096) to 2^16 */
0921ecfd
MCC		 369 rf = rf << (16 - 12);
370 if (rf)
371 rf |= (1 << 12) - 1;
372
f66d81b5
MCC		 373 dev_dbg(&state->i2c->dev,
374 "%s: signal strength = %d (%d < RF=%d < %d)\n",
375 __func__, rf, rf_min, rf >> 4, rf_max);
0921ecfd
MCC		 376 c->strength.stat[0].uvalue = rf;
377 state->get_strength_time = jiffies +
378 msecs_to_jiffies(1000);
379 return 0;
b9ede79a
MCC		 380 }
381 } while (1);
b9ede79a
MCC		 382}
383
959a119f
MCC		 384static int mb86a20s_get_modulation(struct mb86a20s_state *state,
385 unsigned layer)
386{
387 int rc;
388 static unsigned char reg[] = {
389 [0] = 0x86, /* Layer A */
390 [1] = 0x8a, /* Layer B */
391 [2] = 0x8e, /* Layer C */
392 };
393
82033bc5 394 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 395 return -EINVAL;
396 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
397 if (rc < 0)
398 return rc;
399 rc = mb86a20s_readreg(state, 0x6e);
400 if (rc < 0)
401 return rc;
04585921 402 switch ((rc >> 4) & 0x07) {
959a119f
MCC		 403 case 0:
404 return DQPSK;
405 case 1:
406 return QPSK;
407 case 2:
408 return QAM_16;
409 case 3:
410 return QAM_64;
411 default:
412 return QAM_AUTO;
413 }
414}
415
416static int mb86a20s_get_fec(struct mb86a20s_state *state,
417 unsigned layer)
418{
419 int rc;
420
421 static unsigned char reg[] = {
422 [0] = 0x87, /* Layer A */
423 [1] = 0x8b, /* Layer B */
424 [2] = 0x8f, /* Layer C */
425 };
426
82033bc5 427 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 428 return -EINVAL;
429 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
430 if (rc < 0)
431 return rc;
432 rc = mb86a20s_readreg(state, 0x6e);
433 if (rc < 0)
434 return rc;
04585921 435 switch ((rc >> 4) & 0x07) {
959a119f
MCC		 436 case 0:
437 return FEC_1_2;
438 case 1:
439 return FEC_2_3;
440 case 2:
441 return FEC_3_4;
442 case 3:
443 return FEC_5_6;
444 case 4:
445 return FEC_7_8;
446 default:
447 return FEC_AUTO;
448 }
449}
450
451static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
452 unsigned layer)
453{
454 int rc;
4247368b
MCC		 455 int interleaving[] = {
456 0, 1, 2, 4, 8
457 };
959a119f
MCC		 458
459 static unsigned char reg[] = {
460 [0] = 0x88, /* Layer A */
461 [1] = 0x8c, /* Layer B */
462 [2] = 0x90, /* Layer C */
463 };
464
82033bc5 465 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 466 return -EINVAL;
467 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
468 if (rc < 0)
469 return rc;
470 rc = mb86a20s_readreg(state, 0x6e);
471 if (rc < 0)
472 return rc;
04585921 473
4247368b 474 return interleaving[(rc >> 4) & 0x07];
959a119f
MCC		 475}
476
477static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
478 unsigned layer)
479{
480 int rc, count;
959a119f
MCC		 481 static unsigned char reg[] = {
482 [0] = 0x89, /* Layer A */
483 [1] = 0x8d, /* Layer B */
484 [2] = 0x91, /* Layer C */
485 };
486
f66d81b5
MCC		 487 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
488
82033bc5 489 if (layer >= ARRAY_SIZE(reg))
959a119f 490 return -EINVAL;
f66d81b5 491
959a119f
MCC		 492 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
493 if (rc < 0)
494 return rc;
495 rc = mb86a20s_readreg(state, 0x6e);
496 if (rc < 0)
497 return rc;
498 count = (rc >> 4) & 0x0f;
499
f66d81b5
MCC		 500 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
501
959a119f
MCC		 502 return count;
503}
504
a77cfcac
MCC		 505static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
506{
f66d81b5 507 struct mb86a20s_state *state = fe->demodulator_priv;
a77cfcac
MCC		 508 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
509
f66d81b5
MCC		 510 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
511
a77cfcac
MCC		 512 /* Fixed parameters */
513 c->delivery_system = SYS_ISDBT;
514 c->bandwidth_hz = 6000000;
515
516 /* Initialize values that will be later autodetected */
517 c->isdbt_layer_enabled = 0;
518 c->transmission_mode = TRANSMISSION_MODE_AUTO;
519 c->guard_interval = GUARD_INTERVAL_AUTO;
520 c->isdbt_sb_mode = 0;
521 c->isdbt_sb_segment_count = 0;
522}
523
d01a8ee3
MCC		 524/*
525 * Estimates the bit rate using the per-segment bit rate given by
526 * ABNT/NBR 15601 spec (table 4).
527 */
528static u32 isdbt_rate[3][5][4] = {
529 { /* DQPSK/QPSK */
530 { 280850, 312060, 330420, 340430 }, /* 1/2 */
531 { 374470, 416080, 440560, 453910 }, /* 2/3 */
532 { 421280, 468090, 495630, 510650 }, /* 3/4 */
533 { 468090, 520100, 550700, 567390 }, /* 5/6 */
534 { 491500, 546110, 578230, 595760 }, /* 7/8 */
535 }, { /* QAM16 */
536 { 561710, 624130, 660840, 680870 }, /* 1/2 */
537 { 748950, 832170, 881120, 907820 }, /* 2/3 */
538 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
539 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
540 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
541 }, { /* QAM64 */
542 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
543 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
544 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
545 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
546 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
547 }
548};
549
550static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
0562aef2 551 u32 modulation, u32 forward_error_correction,
277bfd2f 552 u32 guard_interval,
d01a8ee3
MCC		 553 u32 segment)
554{
555 struct mb86a20s_state *state = fe->demodulator_priv;
556 u32 rate;
0562aef2 557 int mod, fec, guard;
d01a8ee3
MCC		 558
559 /*
277bfd2f 560 * If modulation/fec/guard is not detected, the default is
d01a8ee3
MCC		 561 * to consider the lowest bit rate, to avoid taking too long time
562 * to get BER.
563 */
564 switch (modulation) {
565 case DQPSK:
566 case QPSK:
567 default:
0562aef2 568 mod = 0;
d01a8ee3
MCC		 569 break;
570 case QAM_16:
0562aef2 571 mod = 1;
d01a8ee3
MCC		 572 break;
573 case QAM_64:
0562aef2 574 mod = 2;
d01a8ee3
MCC		 575 break;
576 }
577
0562aef2 578 switch (forward_error_correction) {
d01a8ee3
MCC		 579 default:
580 case FEC_1_2:
581 case FEC_AUTO:
0562aef2 582 fec = 0;
d01a8ee3
MCC		 583 break;
584 case FEC_2_3:
0562aef2 585 fec = 1;
d01a8ee3
MCC		 586 break;
587 case FEC_3_4:
0562aef2 588 fec = 2;
d01a8ee3
MCC		 589 break;
590 case FEC_5_6:
0562aef2 591 fec = 3;
d01a8ee3
MCC		 592 break;
593 case FEC_7_8:
0562aef2 594 fec = 4;
d01a8ee3
MCC		 595 break;
596 }
597
277bfd2f 598 switch (guard_interval) {
d01a8ee3
MCC		 599 default:
600 case GUARD_INTERVAL_1_4:
0562aef2 601 guard = 0;
d01a8ee3
MCC		 602 break;
603 case GUARD_INTERVAL_1_8:
0562aef2 604 guard = 1;
d01a8ee3
MCC		 605 break;
606 case GUARD_INTERVAL_1_16:
0562aef2 607 guard = 2;
d01a8ee3
MCC		 608 break;
609 case GUARD_INTERVAL_1_32:
0562aef2 610 guard = 3;
d01a8ee3
MCC		 611 break;
612 }
613
614 /* Samples BER at BER_SAMPLING_RATE seconds */
0562aef2 615 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE;
d01a8ee3
MCC		 616
617 /* Avoids sampling too quickly or to overflow the register */
618 if (rate < 256)
619 rate = 256;
620 else if (rate > (1 << 24) - 1)
621 rate = (1 << 24) - 1;
622
623 dev_dbg(&state->i2c->dev,
624 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
0562aef2
MCC		 625 __func__, 'A' + layer,
626 segment * isdbt_rate[mod][fec][guard]/1000,
d01a8ee3
MCC		 627 rate, rate);
628
b1f89331 629 state->estimated_rate[layer] = rate;
d01a8ee3
MCC		 630}
631
7c61d80a 632static int mb86a20s_get_frontend(struct dvb_frontend *fe)
b9ede79a 633{
959a119f 634 struct mb86a20s_state *state = fe->demodulator_priv;
a77cfcac 635 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
5cb88ca8 636 int layer, rc;
b9ede79a 637
f66d81b5
MCC		 638 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
639
a77cfcac
MCC		 640 /* Reset frontend cache to default values */
641 mb86a20s_reset_frontend_cache(fe);
959a119f 642
959a119f
MCC		 643 /* Check for partial reception */
644 rc = mb86a20s_writereg(state, 0x6d, 0x85);
a77cfcac
MCC		 645 if (rc < 0)
646 return rc;
647 rc = mb86a20s_readreg(state, 0x6e);
648 if (rc < 0)
649 return rc;
650 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
959a119f
MCC		 651
652 /* Get per-layer data */
a77cfcac 653
5cb88ca8 654 for (layer = 0; layer < NUM_LAYERS; layer++) {
f66d81b5 655 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
5cb88ca8 656 __func__, 'A' + layer);
f66d81b5 657
5cb88ca8 658 rc = mb86a20s_get_segment_count(state, layer);
a77cfcac 659 if (rc < 0)
f66d81b5 660 goto noperlayer_error;
d01a8ee3 661 if (rc >= 0 && rc < 14) {
5cb88ca8 662 c->layer[layer].segment_count = rc;
d01a8ee3 663 } else {
5cb88ca8
MCC		 664 c->layer[layer].segment_count = 0;
665 state->estimated_rate[layer] = 0;
959a119f 666 continue;
a77cfcac 667 }
5cb88ca8
MCC		 668 c->isdbt_layer_enabled |= 1 << layer;
669 rc = mb86a20s_get_modulation(state, layer);
a77cfcac 670 if (rc < 0)
f66d81b5
MCC		 671 goto noperlayer_error;
672 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
673 __func__, rc);
5cb88ca8
MCC		 674 c->layer[layer].modulation = rc;
675 rc = mb86a20s_get_fec(state, layer);
a77cfcac 676 if (rc < 0)
f66d81b5
MCC		 677 goto noperlayer_error;
678 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
679 __func__, rc);
5cb88ca8
MCC		 680 c->layer[layer].fec = rc;
681 rc = mb86a20s_get_interleaving(state, layer);
a77cfcac 682 if (rc < 0)
f66d81b5
MCC		 683 goto noperlayer_error;
684 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
685 __func__, rc);
5cb88ca8
MCC		 686 c->layer[layer].interleaving = rc;
687 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
688 c->layer[layer].fec,
277bfd2f 689 c->guard_interval,
5cb88ca8 690 c->layer[layer].segment_count);
959a119f
MCC		 691 }
692
959a119f 693 rc = mb86a20s_writereg(state, 0x6d, 0x84);
a77cfcac
MCC		 694 if (rc < 0)
695 return rc;
696 if ((rc & 0x60) == 0x20) {
697 c->isdbt_sb_mode = 1;
959a119f 698 /* At least, one segment should exist */
a77cfcac
MCC		 699 if (!c->isdbt_sb_segment_count)
700 c->isdbt_sb_segment_count = 1;
701 }
959a119f
MCC		 702
703 /* Get transmission mode and guard interval */
959a119f 704 rc = mb86a20s_readreg(state, 0x07);
a77cfcac
MCC		 705 if (rc < 0)
706 return rc;
276dfc4b 707 c->transmission_mode = TRANSMISSION_MODE_AUTO;
a77cfcac 708 if ((rc & 0x60) == 0x20) {
276dfc4b
MCC		 709 /* Only modes 2 and 3 are supported */
710 switch ((rc >> 2) & 0x03) {
a77cfcac
MCC		 711 case 1:
712 c->transmission_mode = TRANSMISSION_MODE_4K;
713 break;
714 case 2:
715 c->transmission_mode = TRANSMISSION_MODE_8K;
716 break;
959a119f 717 }
a77cfcac 718 }
276dfc4b 719 c->guard_interval = GUARD_INTERVAL_AUTO;
a77cfcac 720 if (!(rc & 0x10)) {
276dfc4b 721 /* Guard interval 1/32 is not supported */
a77cfcac
MCC		 722 switch (rc & 0x3) {
723 case 0:
724 c->guard_interval = GUARD_INTERVAL_1_4;
725 break;
726 case 1:
727 c->guard_interval = GUARD_INTERVAL_1_8;
728 break;
729 case 2:
730 c->guard_interval = GUARD_INTERVAL_1_16;
731 break;
959a119f
MCC		 732 }
733 }
09b6d21e 734 return 0;
959a119f 735
f66d81b5 736noperlayer_error:
b9ede79a 737
09b6d21e
MCC		 738 /* per-layer info is incomplete; discard all per-layer */
739 c->isdbt_layer_enabled = 0;
740
741 return rc;
742}
743
744static int mb86a20s_reset_counters(struct dvb_frontend *fe)
745{
746 struct mb86a20s_state *state = fe->demodulator_priv;
747 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
748 int rc, val;
749
750 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
751
752 /* Reset the counters, if the channel changed */
753 if (state->last_frequency != c->frequency) {
09b6d21e
MCC		 754 memset(&c->cnr, 0, sizeof(c->cnr));
755 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
756 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
d9b6f08a
MCC		 757 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
758 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
09b6d21e
MCC		 759 memset(&c->block_error, 0, sizeof(c->block_error));
760 memset(&c->block_count, 0, sizeof(c->block_count));
761
762 state->last_frequency = c->frequency;
763 }
764
765 /* Clear status for most stats */
766
d9b6f08a
MCC		 767 /* BER/PER counter reset */
768 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
09b6d21e
MCC		 769 if (rc < 0)
770 goto err;
771
772 /* CNR counter reset */
773 rc = mb86a20s_readreg(state, 0x45);
774 if (rc < 0)
775 goto err;
776 val = rc;
777 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
778 if (rc < 0)
779 goto err;
780 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
781 if (rc < 0)
782 goto err;
783
784 /* MER counter reset */
785 rc = mb86a20s_writereg(state, 0x50, 0x50);
786 if (rc < 0)
787 goto err;
788 rc = mb86a20s_readreg(state, 0x51);
789 if (rc < 0)
790 goto err;
791 val = rc;
792 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
793 if (rc < 0)
794 goto err;
795 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
796 if (rc < 0)
797 goto err;
798
149d518a 799 goto ok;
09b6d21e 800err:
149d518a
MCC		 801 dev_err(&state->i2c->dev,
802 "%s: Can't reset FE statistics (error %d).\n",
803 __func__, rc);
804ok:
a77cfcac 805 return rc;
09b6d21e
MCC		 806}
807
ad0abbf1
MCC		 808static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
809 unsigned layer,
810 u32 *error, u32 *count)
149d518a
MCC		 811{
812 struct mb86a20s_state *state = fe->demodulator_priv;
ad0abbf1 813 int rc, val;
149d518a
MCC		 814
815 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
816
4f62a20d 817 if (layer >= NUM_LAYERS)
149d518a
MCC		 818 return -EINVAL;
819
820 /* Check if the BER measures are already available */
821 rc = mb86a20s_readreg(state, 0x54);
822 if (rc < 0)
823 return rc;
824
825 /* Check if data is available for that layer */
826 if (!(rc & (1 << layer))) {
827 dev_dbg(&state->i2c->dev,
ad0abbf1 828 "%s: preBER for layer %c is not available yet.\n",
149d518a
MCC		 829 __func__, 'A' + layer);
830 return -EBUSY;
831 }
832
833 /* Read Bit Error Count */
834 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
835 if (rc < 0)
836 return rc;
837 *error = rc << 16;
838 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
839 if (rc < 0)
840 return rc;
841 *error |= rc << 8;
842 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
843 if (rc < 0)
844 return rc;
845 *error |= rc;
846
847 dev_dbg(&state->i2c->dev,
848 "%s: bit error before Viterbi for layer %c: %d.\n",
849 __func__, 'A' + layer, *error);
850
851 /* Read Bit Count */
852 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
853 if (rc < 0)
854 return rc;
855 rc = mb86a20s_readreg(state, 0x51);
856 if (rc < 0)
857 return rc;
858 *count = rc << 16;
859 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
860 if (rc < 0)
861 return rc;
862 rc = mb86a20s_readreg(state, 0x51);
863 if (rc < 0)
864 return rc;
865 *count |= rc << 8;
866 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
867 if (rc < 0)
868 return rc;
869 rc = mb86a20s_readreg(state, 0x51);
870 if (rc < 0)
871 return rc;
872 *count |= rc;
873
874 dev_dbg(&state->i2c->dev,
875 "%s: bit count before Viterbi for layer %c: %d.\n",
876 __func__, 'A' + layer, *count);
877
878
d01a8ee3
MCC		 879 /*
880 * As we get TMCC data from the frontend, we can better estimate the
881 * BER bit counters, in order to do the BER measure during a longer
882 * time. Use those data, if available, to update the bit count
883 * measure.
884 */
885
886 if (state->estimated_rate[layer]
887 && state->estimated_rate[layer] != *count) {
888 dev_dbg(&state->i2c->dev,
ad0abbf1 889 "%s: updating layer %c preBER counter to %d.\n",
d01a8ee3 890 __func__, 'A' + layer, state->estimated_rate[layer]);
ad0abbf1
MCC		 891
892 /* Turn off BER before Viterbi */
893 rc = mb86a20s_writereg(state, 0x52, 0x00);
894
895 /* Update counter for this layer */
d01a8ee3
MCC		 896 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
897 if (rc < 0)
898 return rc;
899 rc = mb86a20s_writereg(state, 0x51,
900 state->estimated_rate[layer] >> 16);
901 if (rc < 0)
902 return rc;
903 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
904 if (rc < 0)
905 return rc;
906 rc = mb86a20s_writereg(state, 0x51,
907 state->estimated_rate[layer] >> 8);
908 if (rc < 0)
909 return rc;
910 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
911 if (rc < 0)
912 return rc;
913 rc = mb86a20s_writereg(state, 0x51,
914 state->estimated_rate[layer]);
915 if (rc < 0)
916 return rc;
ad0abbf1
MCC		 917
918 /* Turn on BER before Viterbi */
919 rc = mb86a20s_writereg(state, 0x52, 0x01);
920
921 /* Reset all preBER counters */
922 rc = mb86a20s_writereg(state, 0x53, 0x00);
923 if (rc < 0)
924 return rc;
925 rc = mb86a20s_writereg(state, 0x53, 0x07);
926 } else {
927 /* Reset counter to collect new data */
928 rc = mb86a20s_readreg(state, 0x53);
929 if (rc < 0)
930 return rc;
931 val = rc;
932 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
933 if (rc < 0)
934 return rc;
935 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
d01a8ee3
MCC		 936 }
937
d9b6f08a
MCC		 938 return rc;
939}
940
941static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
942 unsigned layer,
943 u32 *error, u32 *count)
944{
945 struct mb86a20s_state *state = fe->demodulator_priv;
946 u32 counter, collect_rate;
947 int rc, val;
948
949 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
950
4f62a20d 951 if (layer >= NUM_LAYERS)
d9b6f08a
MCC		 952 return -EINVAL;
953
954 /* Check if the BER measures are already available */
955 rc = mb86a20s_readreg(state, 0x60);
956 if (rc < 0)
957 return rc;
958
959 /* Check if data is available for that layer */
960 if (!(rc & (1 << layer))) {
961 dev_dbg(&state->i2c->dev,
962 "%s: post BER for layer %c is not available yet.\n",
963 __func__, 'A' + layer);
964 return -EBUSY;
965 }
d01a8ee3 966
d9b6f08a
MCC		 967 /* Read Bit Error Count */
968 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
969 if (rc < 0)
970 return rc;
971 *error = rc << 16;
972 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
973 if (rc < 0)
974 return rc;
975 *error |= rc << 8;
976 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
977 if (rc < 0)
978 return rc;
979 *error |= rc;
980
981 dev_dbg(&state->i2c->dev,
982 "%s: post bit error for layer %c: %d.\n",
983 __func__, 'A' + layer, *error);
984
985 /* Read Bit Count */
986 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
987 if (rc < 0)
988 return rc;
989 rc = mb86a20s_readreg(state, 0x51);
990 if (rc < 0)
991 return rc;
992 counter = rc << 8;
993 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
994 if (rc < 0)
995 return rc;
996 rc = mb86a20s_readreg(state, 0x51);
997 if (rc < 0)
998 return rc;
999 counter |= rc;
1000 *count = counter * 204 * 8;
1001
1002 dev_dbg(&state->i2c->dev,
1003 "%s: post bit count for layer %c: %d.\n",
1004 __func__, 'A' + layer, *count);
1005
1006 /*
1007 * As we get TMCC data from the frontend, we can better estimate the
1008 * BER bit counters, in order to do the BER measure during a longer
1009 * time. Use those data, if available, to update the bit count
1010 * measure.
1011 */
1012
1013 if (!state->estimated_rate[layer])
1014 goto reset_measurement;
1015
1016 collect_rate = state->estimated_rate[layer] / 204 / 8;
1017 if (collect_rate < 32)
1018 collect_rate = 32;
1019 if (collect_rate > 65535)
1020 collect_rate = 65535;
1021 if (collect_rate != counter) {
1022 dev_dbg(&state->i2c->dev,
1023 "%s: updating postBER counter on layer %c to %d.\n",
1024 __func__, 'A' + layer, collect_rate);
1025
1026 /* Turn off BER after Viterbi */
1027 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1028
1029 /* Update counter for this layer */
1030 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1031 if (rc < 0)
1032 return rc;
1033 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1034 if (rc < 0)
1035 return rc;
1036 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1037 if (rc < 0)
1038 return rc;
1039 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1040 if (rc < 0)
1041 return rc;
1042
1043 /* Turn on BER after Viterbi */
1044 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1045
1046 /* Reset all preBER counters */
1047 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1048 if (rc < 0)
1049 return rc;
1050 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1051
1052 return rc;
1053 }
1054
1055reset_measurement:
149d518a 1056 /* Reset counter to collect new data */
ad0abbf1
MCC		 1057 rc = mb86a20s_readreg(state, 0x5f);
1058 if (rc < 0)
1059 return rc;
1060 val = rc;
1061 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
149d518a
MCC		 1062 if (rc < 0)
1063 return rc;
d9b6f08a 1064 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
149d518a 1065
ad0abbf1 1066 return rc;
149d518a
MCC		 1067}
1068
593ae89a
MCC		 1069static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1070 unsigned layer,
1071 u32 *error, u32 *count)
1072{
1073 struct mb86a20s_state *state = fe->demodulator_priv;
313cf4ef 1074 int rc, val;
593ae89a
MCC		 1075 u32 collect_rate;
1076 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1077
4f62a20d 1078 if (layer >= NUM_LAYERS)
593ae89a
MCC		 1079 return -EINVAL;
1080
1081 /* Check if the PER measures are already available */
1082 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1083 if (rc < 0)
1084 return rc;
1085 rc = mb86a20s_readreg(state, 0x51);
1086 if (rc < 0)
1087 return rc;
1088
1089 /* Check if data is available for that layer */
1090
1091 if (!(rc & (1 << layer))) {
1092 dev_dbg(&state->i2c->dev,
1093 "%s: block counts for layer %c aren't available yet.\n",
1094 __func__, 'A' + layer);
1095 return -EBUSY;
1096 }
1097
1098 /* Read Packet error Count */
1099 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1100 if (rc < 0)
1101 return rc;
1102 rc = mb86a20s_readreg(state, 0x51);
1103 if (rc < 0)
1104 return rc;
1105 *error = rc << 8;
1106 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1107 if (rc < 0)
1108 return rc;
1109 rc = mb86a20s_readreg(state, 0x51);
1110 if (rc < 0)
1111 return rc;
1112 *error |= rc;
d56e326f 1113 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
593ae89a
MCC		 1114 __func__, 'A' + layer, *error);
1115
1116 /* Read Bit Count */
1117 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1118 if (rc < 0)
1119 return rc;
1120 rc = mb86a20s_readreg(state, 0x51);
1121 if (rc < 0)
1122 return rc;
1123 *count = rc << 8;
1124 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1125 if (rc < 0)
1126 return rc;
1127 rc = mb86a20s_readreg(state, 0x51);
1128 if (rc < 0)
1129 return rc;
1130 *count |= rc;
1131
1132 dev_dbg(&state->i2c->dev,
1133 "%s: block count for layer %c: %d.\n",
1134 __func__, 'A' + layer, *count);
1135
1136 /*
1137 * As we get TMCC data from the frontend, we can better estimate the
1138 * BER bit counters, in order to do the BER measure during a longer
1139 * time. Use those data, if available, to update the bit count
1140 * measure.
1141 */
1142
1143 if (!state->estimated_rate[layer])
1144 goto reset_measurement;
1145
1146 collect_rate = state->estimated_rate[layer] / 204 / 8;
593ae89a
MCC		 1147 if (collect_rate < 32)
1148 collect_rate = 32;
1149 if (collect_rate > 65535)
1150 collect_rate = 65535;
1151
1152 if (collect_rate != *count) {
1153 dev_dbg(&state->i2c->dev,
1154 "%s: updating PER counter on layer %c to %d.\n",
1155 __func__, 'A' + layer, collect_rate);
313cf4ef
MCC		 1156
1157 /* Stop PER measurement */
1158 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1159 if (rc < 0)
1160 return rc;
1161 rc = mb86a20s_writereg(state, 0x51, 0x00);
1162 if (rc < 0)
1163 return rc;
1164
1165 /* Update this layer's counter */
593ae89a
MCC		 1166 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1167 if (rc < 0)
1168 return rc;
1169 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1170 if (rc < 0)
1171 return rc;
1172 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1173 if (rc < 0)
1174 return rc;
1175 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1176 if (rc < 0)
1177 return rc;
313cf4ef
MCC		 1178
1179 /* start PER measurement */
1180 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1181 if (rc < 0)
1182 return rc;
1183 rc = mb86a20s_writereg(state, 0x51, 0x07);
1184 if (rc < 0)
1185 return rc;
1186
1187 /* Reset all counters to collect new data */
1188 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1189 if (rc < 0)
1190 return rc;
1191 rc = mb86a20s_writereg(state, 0x51, 0x07);
1192 if (rc < 0)
1193 return rc;
1194 rc = mb86a20s_writereg(state, 0x51, 0x00);
1195
1196 return rc;
593ae89a
MCC		 1197 }
1198
1199reset_measurement:
1200 /* Reset counter to collect new data */
1201 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1202 if (rc < 0)
1203 return rc;
313cf4ef 1204 rc = mb86a20s_readreg(state, 0x51);
593ae89a
MCC		 1205 if (rc < 0)
1206 return rc;
313cf4ef
MCC		 1207 val = rc;
1208 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
593ae89a
MCC		 1209 if (rc < 0)
1210 return rc;
313cf4ef 1211 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
593ae89a 1212
313cf4ef 1213 return rc;
593ae89a
MCC		 1214}
1215
25188bd0
MCC		 1216struct linear_segments {
1217 unsigned x, y;
1218};
1219
1220/*
1221 * All tables below return a dB/1000 measurement
1222 */
1223
ce08131c 1224static const struct linear_segments cnr_to_db_table[] = {
25188bd0
MCC		 1225 { 19648, 0},
1226 { 18187, 1000},
1227 { 16534, 2000},
1228 { 14823, 3000},
1229 { 13161, 4000},
1230 { 11622, 5000},
1231 { 10279, 6000},
1232 { 9089, 7000},
1233 { 8042, 8000},
1234 { 7137, 9000},
1235 { 6342, 10000},
1236 { 5641, 11000},
1237 { 5030, 12000},
1238 { 4474, 13000},
1239 { 3988, 14000},
1240 { 3556, 15000},
1241 { 3180, 16000},
1242 { 2841, 17000},
1243 { 2541, 18000},
1244 { 2276, 19000},
1245 { 2038, 20000},
1246 { 1800, 21000},
1247 { 1625, 22000},
1248 { 1462, 23000},
1249 { 1324, 24000},
1250 { 1175, 25000},
1251 { 1063, 26000},
1252 { 980, 27000},
1253 { 907, 28000},
1254 { 840, 29000},
1255 { 788, 30000},
1256};
1257
ce08131c 1258static const struct linear_segments cnr_64qam_table[] = {
25188bd0
MCC		 1259 { 3922688, 0},
1260 { 3920384, 1000},
1261 { 3902720, 2000},
1262 { 3894784, 3000},
1263 { 3882496, 4000},
1264 { 3872768, 5000},
1265 { 3858944, 6000},
1266 { 3851520, 7000},
1267 { 3838976, 8000},
1268 { 3829248, 9000},
1269 { 3818240, 10000},
1270 { 3806976, 11000},
1271 { 3791872, 12000},
1272 { 3767040, 13000},
1273 { 3720960, 14000},
1274 { 3637504, 15000},
1275 { 3498496, 16000},
1276 { 3296000, 17000},
1277 { 3031040, 18000},
1278 { 2715392, 19000},
1279 { 2362624, 20000},
1280 { 1963264, 21000},
1281 { 1649664, 22000},
1282 { 1366784, 23000},
1283 { 1120768, 24000},
1284 { 890880, 25000},
1285 { 723456, 26000},
1286 { 612096, 27000},
1287 { 518912, 28000},
1288 { 448256, 29000},
1289 { 388864, 30000},
1290};
1291
ce08131c 1292static const struct linear_segments cnr_16qam_table[] = {
25188bd0
MCC		 1293 { 5314816, 0},
1294 { 5219072, 1000},
1295 { 5118720, 2000},
1296 { 4998912, 3000},
1297 { 4875520, 4000},
1298 { 4736000, 5000},
1299 { 4604160, 6000},
1300 { 4458752, 7000},
1301 { 4300288, 8000},
1302 { 4092928, 9000},
1303 { 3836160, 10000},
1304 { 3521024, 11000},
1305 { 3155968, 12000},
1306 { 2756864, 13000},
1307 { 2347008, 14000},
1308 { 1955072, 15000},
1309 { 1593600, 16000},
1310 { 1297920, 17000},
1311 { 1043968, 18000},
1312 { 839680, 19000},
1313 { 672256, 20000},
1314 { 523008, 21000},
1315 { 424704, 22000},
1316 { 345088, 23000},
1317 { 280064, 24000},
1318 { 221440, 25000},
1319 { 179712, 26000},
1320 { 151040, 27000},
1321 { 128512, 28000},
1322 { 110080, 29000},
1323 { 95744, 30000},
1324};
1325
ce08131c 1326static const struct linear_segments cnr_qpsk_table[] = {
25188bd0
MCC		 1327 { 2834176, 0},
1328 { 2683648, 1000},
1329 { 2536960, 2000},
1330 { 2391808, 3000},
1331 { 2133248, 4000},
1332 { 1906176, 5000},
1333 { 1666560, 6000},
1334 { 1422080, 7000},
1335 { 1189632, 8000},
1336 { 976384, 9000},
1337 { 790272, 10000},
1338 { 633344, 11000},
1339 { 505600, 12000},
1340 { 402944, 13000},
1341 { 320768, 14000},
1342 { 255488, 15000},
1343 { 204032, 16000},
1344 { 163072, 17000},
1345 { 130304, 18000},
1346 { 105216, 19000},
1347 { 83456, 20000},
1348 { 65024, 21000},
1349 { 52480, 22000},
1350 { 42752, 23000},
1351 { 34560, 24000},
1352 { 27136, 25000},
1353 { 22016, 26000},
1354 { 18432, 27000},
1355 { 15616, 28000},
1356 { 13312, 29000},
1357 { 11520, 30000},
1358};
1359
ce08131c 1360static u32 interpolate_value(u32 value, const struct linear_segments *segments,
25188bd0
MCC		 1361 unsigned len)
1362{
1363 u64 tmp64;
1364 u32 dx, dy;
1365 int i, ret;
1366
1367 if (value >= segments[0].x)
1368 return segments[0].y;
1369 if (value < segments[len-1].x)
1370 return segments[len-1].y;
1371
1372 for (i = 1; i < len - 1; i++) {
1373 /* If value is identical, no need to interpolate */
1374 if (value == segments[i].x)
1375 return segments[i].y;
1376 if (value > segments[i].x)
1377 break;
1378 }
1379
1380 /* Linear interpolation between the two (x,y) points */
1381 dy = segments[i].y - segments[i - 1].y;
1382 dx = segments[i - 1].x - segments[i].x;
1383 tmp64 = value - segments[i].x;
1384 tmp64 *= dy;
1385 do_div(tmp64, dx);
1386 ret = segments[i].y - tmp64;
1387
1388 return ret;
1389}
1390
1391static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1392{
1393 struct mb86a20s_state *state = fe->demodulator_priv;
1394 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1395 u32 cnr_linear, cnr;
1396 int rc, val;
1397
1398 /* Check if CNR is available */
1399 rc = mb86a20s_readreg(state, 0x45);
1400 if (rc < 0)
1401 return rc;
1402
1403 if (!(rc & 0x40)) {
d56e326f 1404 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
25188bd0
MCC		 1405 __func__);
1406 return -EBUSY;
1407 }
1408 val = rc;
1409
1410 rc = mb86a20s_readreg(state, 0x46);
1411 if (rc < 0)
1412 return rc;
1413 cnr_linear = rc << 8;
1414
1415 rc = mb86a20s_readreg(state, 0x46);
1416 if (rc < 0)
1417 return rc;
1418 cnr_linear |= rc;
1419
1420 cnr = interpolate_value(cnr_linear,
1421 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1422
1423 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1424 c->cnr.stat[0].svalue = cnr;
1425
1426 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1427 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1428
1429 /* CNR counter reset */
1430 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1431 if (rc < 0)
1432 return rc;
1433 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1434
1435 return rc;
1436}
1437
593ae89a 1438static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
25188bd0
MCC		 1439{
1440 struct mb86a20s_state *state = fe->demodulator_priv;
1441 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1442 u32 mer, cnr;
5cb88ca8 1443 int rc, val, layer;
ce08131c 1444 const struct linear_segments *segs;
25188bd0
MCC		 1445 unsigned segs_len;
1446
1447 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1448
1449 /* Check if the measures are already available */
1450 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1451 if (rc < 0)
1452 return rc;
1453 rc = mb86a20s_readreg(state, 0x51);
1454 if (rc < 0)
1455 return rc;
1456
1457 /* Check if data is available */
1458 if (!(rc & 0x01)) {
d56e326f 1459 dev_dbg(&state->i2c->dev,
25188bd0
MCC		 1460 "%s: MER measures aren't available yet.\n", __func__);
1461 return -EBUSY;
1462 }
1463
1464 /* Read all layers */
5cb88ca8
MCC		 1465 for (layer = 0; layer < NUM_LAYERS; layer++) {
1466 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1467 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
25188bd0
MCC		 1468 continue;
1469 }
1470
5cb88ca8 1471 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
25188bd0
MCC		 1472 if (rc < 0)
1473 return rc;
1474 rc = mb86a20s_readreg(state, 0x51);
1475 if (rc < 0)
1476 return rc;
1477 mer = rc << 16;
5cb88ca8 1478 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
25188bd0
MCC		 1479 if (rc < 0)
1480 return rc;
1481 rc = mb86a20s_readreg(state, 0x51);
1482 if (rc < 0)
1483 return rc;
1484 mer |= rc << 8;
5cb88ca8 1485 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
25188bd0
MCC		 1486 if (rc < 0)
1487 return rc;
1488 rc = mb86a20s_readreg(state, 0x51);
1489 if (rc < 0)
1490 return rc;
1491 mer |= rc;
1492
5cb88ca8 1493 switch (c->layer[layer].modulation) {
25188bd0
MCC		 1494 case DQPSK:
1495 case QPSK:
1496 segs = cnr_qpsk_table;
1497 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1498 break;
1499 case QAM_16:
1500 segs = cnr_16qam_table;
1501 segs_len = ARRAY_SIZE(cnr_16qam_table);
1502 break;
1503 default:
1504 case QAM_64:
1505 segs = cnr_64qam_table;
1506 segs_len = ARRAY_SIZE(cnr_64qam_table);
1507 break;
1508 }
1509 cnr = interpolate_value(mer, segs, segs_len);
1510
5cb88ca8
MCC		 1511 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1512 c->cnr.stat[1 + layer].svalue = cnr;
25188bd0
MCC		 1513
1514 dev_dbg(&state->i2c->dev,
1515 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
5cb88ca8 1516 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
25188bd0
MCC		 1517
1518 }
1519
1520 /* Start a new MER measurement */
1521 /* MER counter reset */
1522 rc = mb86a20s_writereg(state, 0x50, 0x50);
1523 if (rc < 0)
1524 return rc;
1525 rc = mb86a20s_readreg(state, 0x51);
1526 if (rc < 0)
1527 return rc;
1528 val = rc;
1529
1530 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1531 if (rc < 0)
1532 return rc;
1533 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1534 if (rc < 0)
1535 return rc;
1536
1537 return 0;
1538}
1539
09b6d21e
MCC		 1540static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1541{
1542 struct mb86a20s_state *state = fe->demodulator_priv;
1543 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
5cb88ca8 1544 int layer;
09b6d21e
MCC		 1545
1546 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
a77cfcac 1547
09b6d21e
MCC		 1548 /* Fill the length of each status counter */
1549
1550 /* Only global stats */
1551 c->strength.len = 1;
1552
1553 /* Per-layer stats - 3 layers + global */
4f62a20d
MCC		 1554 c->cnr.len = NUM_LAYERS + 1;
1555 c->pre_bit_error.len = NUM_LAYERS + 1;
1556 c->pre_bit_count.len = NUM_LAYERS + 1;
1557 c->post_bit_error.len = NUM_LAYERS + 1;
1558 c->post_bit_count.len = NUM_LAYERS + 1;
1559 c->block_error.len = NUM_LAYERS + 1;
1560 c->block_count.len = NUM_LAYERS + 1;
09b6d21e
MCC		 1561
1562 /* Signal is always available */
1563 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1564 c->strength.stat[0].uvalue = 0;
1565
1566 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
5cb88ca8
MCC		 1567 for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1568 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1569 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1570 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1571 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1572 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1573 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1574 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
09b6d21e 1575 }
b9ede79a
MCC		 1576}
1577
15b1c5a0 1578static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
149d518a
MCC		 1579{
1580 struct mb86a20s_state *state = fe->demodulator_priv;
1581 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
5cb88ca8 1582 int rc = 0, layer;
149d518a
MCC		 1583 u32 bit_error = 0, bit_count = 0;
1584 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
d9b6f08a 1585 u32 t_post_bit_error = 0, t_post_bit_count = 0;
593ae89a
MCC		 1586 u32 block_error = 0, block_count = 0;
1587 u32 t_block_error = 0, t_block_count = 0;
d9b6f08a
MCC		 1588 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1589 int per_layers = 0;
149d518a 1590
25188bd0
MCC		 1591 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1592
1593 mb86a20s_get_main_CNR(fe);
1594
149d518a 1595 /* Get per-layer stats */
593ae89a 1596 mb86a20s_get_blk_error_layer_CNR(fe);
25188bd0 1597
15b1c5a0
MCC		 1598 /*
1599 * At state 7, only CNR is available
1600 * For BER measures, state=9 is required
1601 * FIXME: we may get MER measures with state=8
1602 */
1603 if (status_nr < 9)
1604 return 0;
1605
5cb88ca8
MCC		 1606 for (layer = 0; layer < NUM_LAYERS; layer++) {
1607 if (c->isdbt_layer_enabled & (1 << layer)) {
149d518a
MCC		 1608 /* Layer is active and has rc segments */
1609 active_layers++;
1610
149d518a 1611 /* Handle BER before vterbi */
5cb88ca8 1612 rc = mb86a20s_get_pre_ber(fe, layer,
ad0abbf1 1613 &bit_error, &bit_count);
149d518a 1614 if (rc >= 0) {
5cb88ca8
MCC		 1615 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1616 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1617 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1618 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
149d518a
MCC		 1619 } else if (rc != -EBUSY) {
1620 /*
1621 * If an I/O error happened,
1622 * measures are now unavailable
1623 */
5cb88ca8
MCC		 1624 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1625 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
149d518a
MCC		 1626 dev_err(&state->i2c->dev,
1627 "%s: Can't get BER for layer %c (error %d).\n",
5cb88ca8 1628 __func__, 'A' + layer, rc);
149d518a 1629 }
5cb88ca8 1630 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
d9b6f08a
MCC		 1631 pre_ber_layers++;
1632
1633 /* Handle BER post vterbi */
5cb88ca8 1634 rc = mb86a20s_get_post_ber(fe, layer,
d9b6f08a
MCC		 1635 &bit_error, &bit_count);
1636 if (rc >= 0) {
5cb88ca8
MCC		 1637 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1638 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1639 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1640 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
d9b6f08a
MCC		 1641 } else if (rc != -EBUSY) {
1642 /*
1643 * If an I/O error happened,
1644 * measures are now unavailable
1645 */
5cb88ca8
MCC		 1646 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1647 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
d9b6f08a
MCC		 1648 dev_err(&state->i2c->dev,
1649 "%s: Can't get BER for layer %c (error %d).\n",
5cb88ca8 1650 __func__, 'A' + layer, rc);
d9b6f08a 1651 }
5cb88ca8 1652 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
d9b6f08a 1653 post_ber_layers++;
149d518a 1654
593ae89a 1655 /* Handle Block errors for PER/UCB reports */
5cb88ca8 1656 rc = mb86a20s_get_blk_error(fe, layer,
593ae89a
MCC		 1657 &block_error,
1658 &block_count);
1659 if (rc >= 0) {
5cb88ca8
MCC		 1660 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1661 c->block_error.stat[1 + layer].uvalue += block_error;
1662 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1663 c->block_count.stat[1 + layer].uvalue += block_count;
593ae89a
MCC		 1664 } else if (rc != -EBUSY) {
1665 /*
1666 * If an I/O error happened,
1667 * measures are now unavailable
1668 */
5cb88ca8
MCC		 1669 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1670 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
593ae89a
MCC		 1671 dev_err(&state->i2c->dev,
1672 "%s: Can't get PER for layer %c (error %d).\n",
5cb88ca8 1673 __func__, 'A' + layer, rc);
593ae89a
MCC		 1674
1675 }
5cb88ca8 1676 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
593ae89a
MCC		 1677 per_layers++;
1678
d9b6f08a 1679 /* Update total preBER */
5cb88ca8
MCC		 1680 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1681 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
593ae89a 1682
d9b6f08a 1683 /* Update total postBER */
5cb88ca8
MCC		 1684 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1685 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
d9b6f08a 1686
593ae89a 1687 /* Update total PER */
5cb88ca8
MCC		 1688 t_block_error += c->block_error.stat[1 + layer].uvalue;
1689 t_block_count += c->block_count.stat[1 + layer].uvalue;
149d518a
MCC		 1690 }
1691 }
1692
1693 /*
1694 * Start showing global count if at least one error count is
1695 * available.
1696 */
d9b6f08a 1697 if (pre_ber_layers) {
149d518a
MCC		 1698 /*
1699 * At least one per-layer BER measure was read. We can now
1700 * calculate the total BER
1701 *
1702 * Total Bit Error/Count is calculated as the sum of the
1703 * bit errors on all active layers.
1704 */
1705 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1706 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1707 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1708 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
f67102c4
MCC		 1709 } else {
1710 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1711 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
149d518a
MCC		 1712 }
1713
d9b6f08a
MCC		 1714 /*
1715 * Start showing global count if at least one error count is
1716 * available.
1717 */
1718 if (post_ber_layers) {
1719 /*
1720 * At least one per-layer BER measure was read. We can now
1721 * calculate the total BER
1722 *
1723 * Total Bit Error/Count is calculated as the sum of the
1724 * bit errors on all active layers.
1725 */
1726 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1727 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1728 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1729 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
f67102c4
MCC		 1730 } else {
1731 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1732 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
d9b6f08a
MCC		 1733 }
1734
593ae89a
MCC		 1735 if (per_layers) {
1736 /*
1737 * At least one per-layer UCB measure was read. We can now
1738 * calculate the total UCB
1739 *
1740 * Total block Error/Count is calculated as the sum of the
1741 * block errors on all active layers.
1742 */
1743 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1744 c->block_error.stat[0].uvalue = t_block_error;
1745 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1746 c->block_count.stat[0].uvalue = t_block_count;
f67102c4
MCC		 1747 } else {
1748 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1749 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
593ae89a
MCC		 1750 }
1751
149d518a
MCC		 1752 return rc;
1753}
09b6d21e
MCC		 1754
1755/*
1756 * The functions below are called via DVB callbacks, so they need to
1757 * properly use the I2C gate control
1758 */
1759
dd4493ef
MCC		 1760static int mb86a20s_initfe(struct dvb_frontend *fe)
1761{
1762 struct mb86a20s_state *state = fe->demodulator_priv;
768e6dad 1763 u64 pll;
0e4bbedd 1764 u32 fclk;
dd4493ef 1765 int rc;
04fa725e 1766 u8 regD5 = 1, reg71, reg09 = 0x3a;
dd4493ef 1767
f66d81b5 1768 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
dd4493ef
MCC		 1769
1770 if (fe->ops.i2c_gate_ctrl)
1771 fe->ops.i2c_gate_ctrl(fe, 0);
1772
1773 /* Initialize the frontend */
768e6dad 1774 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
dd4493ef
MCC		 1775 if (rc < 0)
1776 goto err;
1777
04fa725e
MCC		 1778 if (!state->inversion)
1779 reg09 |= 0x04;
1780 rc = mb86a20s_writereg(state, 0x09, reg09);
1781 if (rc < 0)
1782 goto err;
1783 if (!state->bw)
1784 reg71 = 1;
1785 else
1786 reg71 = 0;
1787 rc = mb86a20s_writereg(state, 0x39, reg71);
1788 if (rc < 0)
1789 goto err;
1790 rc = mb86a20s_writereg(state, 0x71, state->bw);
1791 if (rc < 0)
1792 goto err;
1793 if (state->subchannel) {
1794 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1795 if (rc < 0)
1796 goto err;
1797 }
1798
0e4bbedd
MCC		 1799 fclk = state->config->fclk;
1800 if (!fclk)
1801 fclk = 32571428;
1802
768e6dad
MCC		 1803 /* Adjust IF frequency to match tuner */
1804 if (fe->ops.tuner_ops.get_if_frequency)
1805 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1806
1807 if (!state->if_freq)
1808 state->if_freq = 3300000;
1809
0e4bbedd
MCC		 1810 pll = (((u64)1) << 34) * state->if_freq;
1811 do_div(pll, 63 * fclk);
1812 pll = (1 << 25) - pll;
1813 rc = mb86a20s_writereg(state, 0x28, 0x2a);
1814 if (rc < 0)
1815 goto err;
1816 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1817 if (rc < 0)
1818 goto err;
1819 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1820 if (rc < 0)
1821 goto err;
1822 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1823 if (rc < 0)
1824 goto err;
1825 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1826 __func__, fclk, state->if_freq, (long long)pll);
1827
768e6dad
MCC		 1828 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1829 pll = state->if_freq * 1677721600L;
1830 do_div(pll, 1628571429L);
1831 rc = mb86a20s_writereg(state, 0x28, 0x20);
1832 if (rc < 0)
1833 goto err;
1834 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1835 if (rc < 0)
1836 goto err;
1837 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1838 if (rc < 0)
1839 goto err;
1840 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1841 if (rc < 0)
1842 goto err;
0e4bbedd 1843 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
768e6dad
MCC		 1844 __func__, state->if_freq, (long long)pll);
1845
9d32069f 1846 if (!state->config->is_serial)
dd4493ef
MCC		 1847 regD5 &= ~1;
1848
9d32069f
MCC		 1849 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1850 if (rc < 0)
1851 goto err;
1852 rc = mb86a20s_writereg(state, 0x51, regD5);
1853 if (rc < 0)
1854 goto err;
dd4493ef 1855
768e6dad
MCC		 1856 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1857 if (rc < 0)
1858 goto err;
1859
1860
dd4493ef
MCC		 1861err:
1862 if (fe->ops.i2c_gate_ctrl)
1863 fe->ops.i2c_gate_ctrl(fe, 1);
1864
1865 if (rc < 0) {
1866 state->need_init = true;
f66d81b5
MCC		 1867 dev_info(&state->i2c->dev,
1868 "mb86a20s: Init failed. Will try again later\n");
dd4493ef
MCC		 1869 } else {
1870 state->need_init = false;
f66d81b5 1871 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
dd4493ef
MCC		 1872 }
1873 return rc;
1874}
1875
1876static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1877{
1878 struct mb86a20s_state *state = fe->demodulator_priv;
dd4493ef 1879 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
04fa725e 1880 int rc, if_freq;
f66d81b5 1881 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
dd4493ef 1882
04fa725e
MCC		 1883 if (!c->isdbt_layer_enabled)
1884 c->isdbt_layer_enabled = 7;
1885
1886 if (c->isdbt_layer_enabled == 1)
1887 state->bw = MB86A20S_1SEG;
1888 else if (c->isdbt_partial_reception)
1889 state->bw = MB86A20S_13SEG_PARTIAL;
1890 else
1891 state->bw = MB86A20S_13SEG;
1892
1893 if (c->inversion == INVERSION_ON)
1894 state->inversion = true;
1895 else
1896 state->inversion = false;
1897
1898 if (!c->isdbt_sb_mode) {
1899 state->subchannel = 0;
1900 } else {
41c6e9dd 1901 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
04fa725e
MCC		 1902 c->isdbt_sb_subchannel = 0;
1903
1904 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1905 }
1906
dd4493ef
MCC		 1907 /*
1908 * Gate should already be opened, but it doesn't hurt to
1909 * double-check
1910 */
1911 if (fe->ops.i2c_gate_ctrl)
1912 fe->ops.i2c_gate_ctrl(fe, 1);
dd4493ef
MCC		 1913 fe->ops.tuner_ops.set_params(fe);
1914
a78b41d5 1915 if (fe->ops.tuner_ops.get_if_frequency)
768e6dad
MCC		 1916 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1917
dd4493ef
MCC		 1918 /*
1919 * Make it more reliable: if, for some reason, the initial
1920 * device initialization doesn't happen, initialize it when
1921 * a SBTVD parameters are adjusted.
1922 *
1923 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1924 * the agc callback logic is not called during DVB attach time,
1925 * causing mb86a20s to not be initialized with Kworld SBTVD.
1926 * So, this hack is needed, in order to make Kworld SBTVD to work.
768e6dad
MCC		 1927 *
1928 * It is also needed to change the IF after the initial init.
a78b41d5
MCC		 1929 *
1930 * HACK: Always init the frontend when set_frontend is called:
1931 * it was noticed that, on some devices, it fails to lock on a
1932 * different channel. So, it is better to reset everything, even
1933 * wasting some time, than to loose channel lock.
dd4493ef 1934 */
a78b41d5 1935 mb86a20s_initfe(fe);
dd4493ef
MCC		 1936
1937 if (fe->ops.i2c_gate_ctrl)
1938 fe->ops.i2c_gate_ctrl(fe, 0);
d01a8ee3 1939
dd4493ef 1940 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
09b6d21e 1941 mb86a20s_reset_counters(fe);
3a2e4751 1942 mb86a20s_stats_not_ready(fe);
d01a8ee3 1943
dd4493ef
MCC		 1944 if (fe->ops.i2c_gate_ctrl)
1945 fe->ops.i2c_gate_ctrl(fe, 1);
1946
1947 return rc;
1948}
1949
09b6d21e 1950static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
0df289a2 1951 enum fe_status *status)
d36e418a 1952{
09b6d21e 1953 struct mb86a20s_state *state = fe->demodulator_priv;
15b1c5a0 1954 int rc, status_nr;
d36e418a 1955
09b6d21e 1956 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
d36e418a
MCC		 1957
1958 if (fe->ops.i2c_gate_ctrl)
1959 fe->ops.i2c_gate_ctrl(fe, 0);
1960
09b6d21e 1961 /* Get lock */
15b1c5a0
MCC		 1962 status_nr = mb86a20s_read_status(fe, status);
1963 if (status_nr < 7) {
09b6d21e
MCC		 1964 mb86a20s_stats_not_ready(fe);
1965 mb86a20s_reset_frontend_cache(fe);
1966 }
15b1c5a0 1967 if (status_nr < 0) {
149d518a
MCC		 1968 dev_err(&state->i2c->dev,
1969 "%s: Can't read frontend lock status\n", __func__);
09b6d21e 1970 goto error;
149d518a 1971 }
09b6d21e
MCC		 1972
1973 /* Get signal strength */
1974 rc = mb86a20s_read_signal_strength(fe);
1975 if (rc < 0) {
149d518a
MCC		 1976 dev_err(&state->i2c->dev,
1977 "%s: Can't reset VBER registers.\n", __func__);
09b6d21e
MCC		 1978 mb86a20s_stats_not_ready(fe);
1979 mb86a20s_reset_frontend_cache(fe);
149d518a
MCC		 1980
1981 rc = 0; /* Status is OK */
09b6d21e
MCC		 1982 goto error;
1983 }
09b6d21e 1984
15b1c5a0 1985 if (status_nr >= 7) {
09b6d21e
MCC		 1986 /* Get TMCC info*/
1987 rc = mb86a20s_get_frontend(fe);
149d518a
MCC		 1988 if (rc < 0) {
1989 dev_err(&state->i2c->dev,
1990 "%s: Can't get FE TMCC data.\n", __func__);
1991 rc = 0; /* Status is OK */
1992 goto error;
1993 }
1994
1995 /* Get statistics */
15b1c5a0 1996 rc = mb86a20s_get_stats(fe, status_nr);
149d518a
MCC		 1997 if (rc < 0 && rc != -EBUSY) {
1998 dev_err(&state->i2c->dev,
1999 "%s: Can't get FE statistics.\n", __func__);
2000 rc = 0;
09b6d21e 2001 goto error;
149d518a
MCC		 2002 }
2003 rc = 0; /* Don't return EBUSY to userspace */
09b6d21e 2004 }
149d518a 2005 goto ok;
09b6d21e 2006
149d518a 2007error:
09b6d21e 2008 mb86a20s_stats_not_ready(fe);
d36e418a 2009
149d518a 2010ok:
d36e418a
MCC		 2011 if (fe->ops.i2c_gate_ctrl)
2012 fe->ops.i2c_gate_ctrl(fe, 1);
149d518a 2013
09b6d21e
MCC		 2014 return rc;
2015}
2016
2017static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2018 u16 *strength)
2019{
2020 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2021
2022
2023 *strength = c->strength.stat[0].uvalue;
d36e418a 2024
09b6d21e 2025 return 0;
d36e418a
MCC		 2026}
2027
b9ede79a 2028static int mb86a20s_tune(struct dvb_frontend *fe,
7e072221 2029 bool re_tune,
b9ede79a
MCC		 2030 unsigned int mode_flags,
2031 unsigned int *delay,
0df289a2 2032 enum fe_status *status)
b9ede79a 2033{
f66d81b5 2034 struct mb86a20s_state *state = fe->demodulator_priv;
b9ede79a
MCC		 2035 int rc = 0;
2036
f66d81b5 2037 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
b9ede79a 2038
7e072221 2039 if (re_tune)
2d76e22b 2040 rc = mb86a20s_set_frontend(fe);
b9ede79a
MCC		 2041
2042 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
09b6d21e 2043 mb86a20s_read_status_and_stats(fe, status);
b9ede79a
MCC		 2044
2045 return rc;
2046}
2047
2048static void mb86a20s_release(struct dvb_frontend *fe)
2049{
2050 struct mb86a20s_state *state = fe->demodulator_priv;
2051
f66d81b5 2052 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
b9ede79a
MCC		 2053
2054 kfree(state);
2055}
2056
dafb65fb
MCC		 2057static int mb86a20s_get_frontend_algo(struct dvb_frontend *fe)
2058{
2059 return DVBFE_ALGO_HW;
2060}
2061
b9ede79a
MCC		 2062static struct dvb_frontend_ops mb86a20s_ops;
2063
2064struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2065 struct i2c_adapter *i2c)
2066{
f66d81b5 2067 struct mb86a20s_state *state;
b9ede79a
MCC		 2068 u8 rev;
2069
f167e302
MCC		 2070 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2071
b9ede79a 2072 /* allocate memory for the internal state */
f66d81b5 2073 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
b9ede79a 2074 if (state == NULL) {
f167e302 2075 dev_err(&i2c->dev,
f66d81b5 2076 "%s: unable to allocate memory for state\n", __func__);
b9ede79a
MCC		 2077 goto error;
2078 }
2079
2080 /* setup the state */
2081 state->config = config;
2082 state->i2c = i2c;
2083
2084 /* create dvb_frontend */
2085 memcpy(&state->frontend.ops, &mb86a20s_ops,
2086 sizeof(struct dvb_frontend_ops));
2087 state->frontend.demodulator_priv = state;
2088
2089 /* Check if it is a mb86a20s frontend */
2090 rev = mb86a20s_readreg(state, 0);
2091
2092 if (rev == 0x13) {
f167e302 2093 dev_info(&i2c->dev,
f66d81b5 2094 "Detected a Fujitsu mb86a20s frontend\n");
b9ede79a 2095 } else {
f167e302 2096 dev_dbg(&i2c->dev,
f66d81b5 2097 "Frontend revision %d is unknown - aborting.\n",
b9ede79a
MCC		 2098 rev);
2099 goto error;
2100 }
2101
2102 return &state->frontend;
2103
2104error:
2105 kfree(state);
2106 return NULL;
2107}
2108EXPORT_SYMBOL(mb86a20s_attach);
2109
2110static struct dvb_frontend_ops mb86a20s_ops = {
2d76e22b 2111 .delsys = { SYS_ISDBT },
b9ede79a
MCC		 2112 /* Use dib8000 values per default */
2113 .info = {
2114 .name = "Fujitsu mb86A20s",
04fa725e 2115 .caps = FE_CAN_RECOVER |
b9ede79a
MCC		 2116 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2117 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2118 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2119 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2120 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2121 /* Actually, those values depend on the used tuner */
2122 .frequency_min = 45000000,
2123 .frequency_max = 864000000,
2124 .frequency_stepsize = 62500,
2125 },
2126
2127 .release = mb86a20s_release,
2128
2129 .init = mb86a20s_initfe,
2d76e22b 2130 .set_frontend = mb86a20s_set_frontend,
09b6d21e
MCC		 2131 .read_status = mb86a20s_read_status_and_stats,
2132 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
b9ede79a 2133 .tune = mb86a20s_tune,
dafb65fb 2134 .get_frontend_algo = mb86a20s_get_frontend_algo,
b9ede79a
MCC		 2135};
2136
2137MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
37e59f87 2138MODULE_AUTHOR("Mauro Carvalho Chehab");
b9ede79a 2139MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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