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[deliverable/linux.git] / drivers / media / i2c / adv7511.c
CommitLineData
5a544cce
HV		 1/*
2 * Analog Devices ADV7511 HDMI Transmitter Device Driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 */
19
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/i2c.h>
25#include <linux/delay.h>
26#include <linux/videodev2.h>
27#include <linux/gpio.h>
28#include <linux/workqueue.h>
1fb69bfd 29#include <linux/hdmi.h>
5a544cce
HV		 30#include <linux/v4l2-dv-timings.h>
31#include <media/v4l2-device.h>
32#include <media/v4l2-common.h>
33#include <media/v4l2-ctrls.h>
34#include <media/v4l2-dv-timings.h>
b5dcee22 35#include <media/i2c/adv7511.h>
257d4eae 36#include <media/cec.h>
5a544cce
HV		 37
38static int debug;
39module_param(debug, int, 0644);
40MODULE_PARM_DESC(debug, "debug level (0-2)");
41
42MODULE_DESCRIPTION("Analog Devices ADV7511 HDMI Transmitter Device Driver");
43MODULE_AUTHOR("Hans Verkuil");
8f7a5f46 44MODULE_LICENSE("GPL v2");
5a544cce
HV		 45
46#define MASK_ADV7511_EDID_RDY_INT 0x04
47#define MASK_ADV7511_MSEN_INT 0x40
48#define MASK_ADV7511_HPD_INT 0x80
49
50#define MASK_ADV7511_HPD_DETECT 0x40
51#define MASK_ADV7511_MSEN_DETECT 0x20
52#define MASK_ADV7511_EDID_RDY 0x10
53
54#define EDID_MAX_RETRIES (8)
55#define EDID_DELAY 250
56#define EDID_MAX_SEGM 8
57
58#define ADV7511_MAX_WIDTH 1920
59#define ADV7511_MAX_HEIGHT 1200
60#define ADV7511_MIN_PIXELCLOCK 20000000
61#define ADV7511_MAX_PIXELCLOCK 225000000
62
257d4eae
HV		 63#define ADV7511_MAX_ADDRS (3)
64
5a544cce
HV		 65/*
66**********************************************************************
67*
68* Arrays with configuration parameters for the ADV7511
69*
70**********************************************************************
71*/
72
73struct i2c_reg_value {
74 unsigned char reg;
75 unsigned char value;
76};
77
78struct adv7511_state_edid {
79 /* total number of blocks */
80 u32 blocks;
81 /* Number of segments read */
82 u32 segments;
5be50ef1 83 u8 data[EDID_MAX_SEGM * 256];
5a544cce
HV		 84 /* Number of EDID read retries left */
85 unsigned read_retries;
86 bool complete;
87};
88
89struct adv7511_state {
90 struct adv7511_platform_data pdata;
91 struct v4l2_subdev sd;
92 struct media_pad pad;
93 struct v4l2_ctrl_handler hdl;
94 int chip_revision;
5be50ef1 95 u8 i2c_edid_addr;
b4dbad8f 96 u8 i2c_pktmem_addr;
257d4eae
HV		 97 u8 i2c_cec_addr;
98
99 struct i2c_client *i2c_cec;
100 struct cec_adapter *cec_adap;
101 u8 cec_addr[ADV7511_MAX_ADDRS];
102 u8 cec_valid_addrs;
103 bool cec_enabled_adap;
104
5a544cce
HV		 105 /* Is the adv7511 powered on? */
106 bool power_on;
107 /* Did we receive hotplug and rx-sense signals? */
108 bool have_monitor;
257d4eae 109 bool enabled_irq;
5a544cce
HV		 110 /* timings from s_dv_timings */
111 struct v4l2_dv_timings dv_timings;
1fb69bfd
HV		 112 u32 fmt_code;
113 u32 colorspace;
114 u32 ycbcr_enc;
115 u32 quantization;
e719a51a 116 u32 xfer_func;
df0e5775 117 u32 content_type;
5a544cce
HV		 118 /* controls */
119 struct v4l2_ctrl *hdmi_mode_ctrl;
120 struct v4l2_ctrl *hotplug_ctrl;
121 struct v4l2_ctrl *rx_sense_ctrl;
122 struct v4l2_ctrl *have_edid0_ctrl;
123 struct v4l2_ctrl *rgb_quantization_range_ctrl;
df0e5775 124 struct v4l2_ctrl *content_type_ctrl;
5a544cce 125 struct i2c_client *i2c_edid;
b4dbad8f 126 struct i2c_client *i2c_pktmem;
5a544cce
HV		 127 struct adv7511_state_edid edid;
128 /* Running counter of the number of detected EDIDs (for debugging) */
129 unsigned edid_detect_counter;
130 struct workqueue_struct *work_queue;
131 struct delayed_work edid_handler; /* work entry */
132};
133
134static void adv7511_check_monitor_present_status(struct v4l2_subdev *sd);
135static bool adv7511_check_edid_status(struct v4l2_subdev *sd);
136static void adv7511_setup(struct v4l2_subdev *sd);
137static int adv7511_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
138static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
139
140
141static const struct v4l2_dv_timings_cap adv7511_timings_cap = {
142 .type = V4L2_DV_BT_656_1120,
aefd4a5a
GG		 143 /* keep this initialization for compatibility with GCC < 4.4.6 */
144 .reserved = { 0 },
145 V4L2_INIT_BT_TIMINGS(0, ADV7511_MAX_WIDTH, 0, ADV7511_MAX_HEIGHT,
146 ADV7511_MIN_PIXELCLOCK, ADV7511_MAX_PIXELCLOCK,
147 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
5a544cce 148 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
aefd4a5a
GG		 149 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
150 V4L2_DV_BT_CAP_CUSTOM)
5a544cce
HV		 151};
152
153static inline struct adv7511_state *get_adv7511_state(struct v4l2_subdev *sd)
154{
155 return container_of(sd, struct adv7511_state, sd);
156}
157
158static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
159{
160 return &container_of(ctrl->handler, struct adv7511_state, hdl)->sd;
161}
162
163/* ------------------------ I2C ----------------------------------------------- */
164
165static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
166 u8 command, bool check)
167{
168 union i2c_smbus_data data;
169
170 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
171 I2C_SMBUS_READ, command,
172 I2C_SMBUS_BYTE_DATA, &data))
173 return data.byte;
174 if (check)
175 v4l_err(client, "error reading %02x, %02x\n",
176 client->addr, command);
177 return -1;
178}
179
180static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
181{
182 int i;
183 for (i = 0; i < 3; i++) {
184 int ret = adv_smbus_read_byte_data_check(client, command, true);
185 if (ret >= 0) {
186 if (i)
187 v4l_err(client, "read ok after %d retries\n", i);
188 return ret;
189 }
190 }
191 v4l_err(client, "read failed\n");
192 return -1;
193}
194
195static int adv7511_rd(struct v4l2_subdev *sd, u8 reg)
196{
197 struct i2c_client *client = v4l2_get_subdevdata(sd);
198
199 return adv_smbus_read_byte_data(client, reg);
200}
201
202static int adv7511_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
203{
204 struct i2c_client *client = v4l2_get_subdevdata(sd);
205 int ret;
206 int i;
207
208 for (i = 0; i < 3; i++) {
209 ret = i2c_smbus_write_byte_data(client, reg, val);
210 if (ret == 0)
211 return 0;
212 }
213 v4l2_err(sd, "%s: i2c write error\n", __func__);
214 return ret;
215}
216
217/* To set specific bits in the register, a clear-mask is given (to be AND-ed),
218 and then the value-mask (to be OR-ed). */
5be50ef1 219static inline void adv7511_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask)
5a544cce
HV		 220{
221 adv7511_wr(sd, reg, (adv7511_rd(sd, reg) & clr_mask) | val_mask);
222}
223
224static int adv_smbus_read_i2c_block_data(struct i2c_client *client,
225 u8 command, unsigned length, u8 *values)
226{
227 union i2c_smbus_data data;
228 int ret;
229
230 if (length > I2C_SMBUS_BLOCK_MAX)
231 length = I2C_SMBUS_BLOCK_MAX;
232 data.block[0] = length;
233
234 ret = i2c_smbus_xfer(client->adapter, client->addr, client->flags,
235 I2C_SMBUS_READ, command,
236 I2C_SMBUS_I2C_BLOCK_DATA, &data);
237 memcpy(values, data.block + 1, length);
238 return ret;
239}
240
257d4eae 241static void adv7511_edid_rd(struct v4l2_subdev *sd, uint16_t len, uint8_t *buf)
5a544cce
HV		 242{
243 struct adv7511_state *state = get_adv7511_state(sd);
244 int i;
245 int err = 0;
246
247 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
248
249 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
250 err = adv_smbus_read_i2c_block_data(state->i2c_edid, i,
251 I2C_SMBUS_BLOCK_MAX, buf + i);
252 if (err)
253 v4l2_err(sd, "%s: i2c read error\n", __func__);
254}
255
257d4eae
HV		 256static inline int adv7511_cec_read(struct v4l2_subdev *sd, u8 reg)
257{
258 struct adv7511_state *state = get_adv7511_state(sd);
259
260 return i2c_smbus_read_byte_data(state->i2c_cec, reg);
261}
262
263static int adv7511_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
264{
265 struct adv7511_state *state = get_adv7511_state(sd);
266 int ret;
267 int i;
268
269 for (i = 0; i < 3; i++) {
270 ret = i2c_smbus_write_byte_data(state->i2c_cec, reg, val);
271 if (ret == 0)
272 return 0;
273 }
274 v4l2_err(sd, "%s: I2C Write Problem\n", __func__);
275 return ret;
276}
277
278static inline int adv7511_cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask,
279 u8 val)
280{
281 return adv7511_cec_write(sd, reg, (adv7511_cec_read(sd, reg) & mask) | val);
282}
283
b4dbad8f
HV		 284static int adv7511_pktmem_rd(struct v4l2_subdev *sd, u8 reg)
285{
286 struct adv7511_state *state = get_adv7511_state(sd);
287
288 return adv_smbus_read_byte_data(state->i2c_pktmem, reg);
289}
290
291static int adv7511_pktmem_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
292{
293 struct adv7511_state *state = get_adv7511_state(sd);
294 int ret;
295 int i;
296
297 for (i = 0; i < 3; i++) {
298 ret = i2c_smbus_write_byte_data(state->i2c_pktmem, reg, val);
299 if (ret == 0)
300 return 0;
301 }
302 v4l2_err(sd, "%s: i2c write error\n", __func__);
303 return ret;
304}
305
306/* To set specific bits in the register, a clear-mask is given (to be AND-ed),
307 and then the value-mask (to be OR-ed). */
308static inline void adv7511_pktmem_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask)
309{
310 adv7511_pktmem_wr(sd, reg, (adv7511_pktmem_rd(sd, reg) & clr_mask) | val_mask);
311}
312
5a544cce
HV		 313static inline bool adv7511_have_hotplug(struct v4l2_subdev *sd)
314{
315 return adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT;
316}
317
318static inline bool adv7511_have_rx_sense(struct v4l2_subdev *sd)
319{
320 return adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT;
321}
322
5be50ef1 323static void adv7511_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
5a544cce
HV		 324{
325 adv7511_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
326}
327
328static void adv7511_csc_coeff(struct v4l2_subdev *sd,
329 u16 A1, u16 A2, u16 A3, u16 A4,
330 u16 B1, u16 B2, u16 B3, u16 B4,
331 u16 C1, u16 C2, u16 C3, u16 C4)
332{
333 /* A */
334 adv7511_wr_and_or(sd, 0x18, 0xe0, A1>>8);
335 adv7511_wr(sd, 0x19, A1);
336 adv7511_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
337 adv7511_wr(sd, 0x1B, A2);
338 adv7511_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
339 adv7511_wr(sd, 0x1d, A3);
340 adv7511_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
341 adv7511_wr(sd, 0x1f, A4);
342
343 /* B */
344 adv7511_wr_and_or(sd, 0x20, 0xe0, B1>>8);
345 adv7511_wr(sd, 0x21, B1);
346 adv7511_wr_and_or(sd, 0x22, 0xe0, B2>>8);
347 adv7511_wr(sd, 0x23, B2);
348 adv7511_wr_and_or(sd, 0x24, 0xe0, B3>>8);
349 adv7511_wr(sd, 0x25, B3);
350 adv7511_wr_and_or(sd, 0x26, 0xe0, B4>>8);
351 adv7511_wr(sd, 0x27, B4);
352
353 /* C */
354 adv7511_wr_and_or(sd, 0x28, 0xe0, C1>>8);
355 adv7511_wr(sd, 0x29, C1);
356 adv7511_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
357 adv7511_wr(sd, 0x2B, C2);
358 adv7511_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
359 adv7511_wr(sd, 0x2D, C3);
360 adv7511_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
361 adv7511_wr(sd, 0x2F, C4);
362}
363
364static void adv7511_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
365{
366 if (enable) {
5be50ef1 367 u8 csc_mode = 0;
5a544cce
HV		 368 adv7511_csc_conversion_mode(sd, csc_mode);
369 adv7511_csc_coeff(sd,
370 4096-564, 0, 0, 256,
371 0, 4096-564, 0, 256,
372 0, 0, 4096-564, 256);
373 /* enable CSC */
374 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x80);
375 /* AVI infoframe: Limited range RGB (16-235) */
376 adv7511_wr_and_or(sd, 0x57, 0xf3, 0x04);
377 } else {
378 /* disable CSC */
379 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x0);
380 /* AVI infoframe: Full range RGB (0-255) */
381 adv7511_wr_and_or(sd, 0x57, 0xf3, 0x08);
382 }
383}
384
0a25a012 385static void adv7511_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
5a544cce 386{
0a25a012
HV		 387 struct adv7511_state *state = get_adv7511_state(sd);
388
389 /* Only makes sense for RGB formats */
390 if (state->fmt_code != MEDIA_BUS_FMT_RGB888_1X24) {
391 /* so just keep quantization */
392 adv7511_csc_rgb_full2limit(sd, false);
393 return;
394 }
395
5a544cce 396 switch (ctrl->val) {
0a25a012 397 case V4L2_DV_RGB_RANGE_AUTO:
5a544cce 398 /* automatic */
680fee04
HV		 399 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
400 /* CE format, RGB limited range (16-235) */
5a544cce
HV		 401 adv7511_csc_rgb_full2limit(sd, true);
402 } else {
680fee04 403 /* not CE format, RGB full range (0-255) */
5a544cce
HV		 404 adv7511_csc_rgb_full2limit(sd, false);
405 }
5a544cce
HV		 406 break;
407 case V4L2_DV_RGB_RANGE_LIMITED:
408 /* RGB limited range (16-235) */
409 adv7511_csc_rgb_full2limit(sd, true);
410 break;
411 case V4L2_DV_RGB_RANGE_FULL:
412 /* RGB full range (0-255) */
413 adv7511_csc_rgb_full2limit(sd, false);
414 break;
415 }
5a544cce
HV		 416}
417
418/* ------------------------------ CTRL OPS ------------------------------ */
419
420static int adv7511_s_ctrl(struct v4l2_ctrl *ctrl)
421{
422 struct v4l2_subdev *sd = to_sd(ctrl);
423 struct adv7511_state *state = get_adv7511_state(sd);
424
425 v4l2_dbg(1, debug, sd, "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
426
427 if (state->hdmi_mode_ctrl == ctrl) {
428 /* Set HDMI or DVI-D */
429 adv7511_wr_and_or(sd, 0xaf, 0xfd, ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
430 return 0;
431 }
0a25a012
HV		 432 if (state->rgb_quantization_range_ctrl == ctrl) {
433 adv7511_set_rgb_quantization_mode(sd, ctrl);
434 return 0;
435 }
df0e5775
HV		 436 if (state->content_type_ctrl == ctrl) {
437 u8 itc, cn;
438
439 state->content_type = ctrl->val;
440 itc = state->content_type != V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
441 cn = itc ? state->content_type : V4L2_DV_IT_CONTENT_TYPE_GRAPHICS;
442 adv7511_wr_and_or(sd, 0x57, 0x7f, itc << 7);
443 adv7511_wr_and_or(sd, 0x59, 0xcf, cn << 4);
444 return 0;
445 }
5a544cce
HV		 446
447 return -EINVAL;
448}
449
450static const struct v4l2_ctrl_ops adv7511_ctrl_ops = {
451 .s_ctrl = adv7511_s_ctrl,
452};
453
454/* ---------------------------- CORE OPS ------------------------------------------- */
455
456#ifdef CONFIG_VIDEO_ADV_DEBUG
457static void adv7511_inv_register(struct v4l2_subdev *sd)
458{
257d4eae
HV		 459 struct adv7511_state *state = get_adv7511_state(sd);
460
5a544cce 461 v4l2_info(sd, "0x000-0x0ff: Main Map\n");
257d4eae
HV		 462 if (state->i2c_cec)
463 v4l2_info(sd, "0x100-0x1ff: CEC Map\n");
5a544cce
HV		 464}
465
466static int adv7511_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
467{
257d4eae
HV		 468 struct adv7511_state *state = get_adv7511_state(sd);
469
5a544cce
HV		 470 reg->size = 1;
471 switch (reg->reg >> 8) {
472 case 0:
473 reg->val = adv7511_rd(sd, reg->reg & 0xff);
474 break;
257d4eae
HV		 475 case 1:
476 if (state->i2c_cec) {
477 reg->val = adv7511_cec_read(sd, reg->reg & 0xff);
478 break;
479 }
480 /* fall through */
5a544cce
HV		 481 default:
482 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
483 adv7511_inv_register(sd);
484 break;
485 }
486 return 0;
487}
488
489static int adv7511_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
490{
257d4eae
HV		 491 struct adv7511_state *state = get_adv7511_state(sd);
492
5a544cce
HV		 493 switch (reg->reg >> 8) {
494 case 0:
495 adv7511_wr(sd, reg->reg & 0xff, reg->val & 0xff);
496 break;
257d4eae
HV		 497 case 1:
498 if (state->i2c_cec) {
499 adv7511_cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
500 break;
501 }
502 /* fall through */
5a544cce
HV		 503 default:
504 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
505 adv7511_inv_register(sd);
506 break;
507 }
508 return 0;
509}
510#endif
511
b4dbad8f
HV		 512struct adv7511_cfg_read_infoframe {
513 const char *desc;
514 u8 present_reg;
515 u8 present_mask;
516 u8 header[3];
517 u16 payload_addr;
518};
519
520static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size)
521{
522 u8 csum = 0;
523 size_t i;
524
525 /* compute checksum */
526 for (i = 0; i < size; i++)
527 csum += ptr[i];
528
529 return 256 - csum;
530}
531
532static void log_infoframe(struct v4l2_subdev *sd, const struct adv7511_cfg_read_infoframe *cri)
533{
534 struct i2c_client *client = v4l2_get_subdevdata(sd);
535 struct device *dev = &client->dev;
536 union hdmi_infoframe frame;
537 u8 buffer[32];
538 u8 len;
539 int i;
540
541 if (!(adv7511_rd(sd, cri->present_reg) & cri->present_mask)) {
542 v4l2_info(sd, "%s infoframe not transmitted\n", cri->desc);
543 return;
544 }
545
546 memcpy(buffer, cri->header, sizeof(cri->header));
547
548 len = buffer[2];
549
550 if (len + 4 > sizeof(buffer)) {
551 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
552 return;
553 }
554
555 if (cri->payload_addr >= 0x100) {
556 for (i = 0; i < len; i++)
557 buffer[i + 4] = adv7511_pktmem_rd(sd, cri->payload_addr + i - 0x100);
558 } else {
559 for (i = 0; i < len; i++)
560 buffer[i + 4] = adv7511_rd(sd, cri->payload_addr + i);
561 }
562 buffer[3] = 0;
563 buffer[3] = hdmi_infoframe_checksum(buffer, len + 4);
564
565 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
566 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
567 return;
568 }
569
570 hdmi_infoframe_log(KERN_INFO, dev, &frame);
571}
572
573static void adv7511_log_infoframes(struct v4l2_subdev *sd)
574{
575 static const struct adv7511_cfg_read_infoframe cri[] = {
576 { "AVI", 0x44, 0x10, { 0x82, 2, 13 }, 0x55 },
577 { "Audio", 0x44, 0x08, { 0x84, 1, 10 }, 0x73 },
578 { "SDP", 0x40, 0x40, { 0x83, 1, 25 }, 0x103 },
579 };
580 int i;
581
582 for (i = 0; i < ARRAY_SIZE(cri); i++)
583 log_infoframe(sd, &cri[i]);
584}
585
5a544cce
HV		 586static int adv7511_log_status(struct v4l2_subdev *sd)
587{
588 struct adv7511_state *state = get_adv7511_state(sd);
589 struct adv7511_state_edid *edid = &state->edid;
257d4eae 590 int i;
5a544cce
HV		 591
592 static const char * const states[] = {
593 "in reset",
594 "reading EDID",
595 "idle",
596 "initializing HDCP",
597 "HDCP enabled",
598 "initializing HDCP repeater",
599 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
600 };
601 static const char * const errors[] = {
602 "no error",
603 "bad receiver BKSV",
604 "Ri mismatch",
605 "Pj mismatch",
606 "i2c error",
607 "timed out",
608 "max repeater cascade exceeded",
609 "hash check failed",
610 "too many devices",
611 "9", "A", "B", "C", "D", "E", "F"
612 };
613
614 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
615 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
616 (adv7511_rd(sd, 0x42) & MASK_ADV7511_HPD_DETECT) ? "detected" : "no",
617 (adv7511_rd(sd, 0x42) & MASK_ADV7511_MSEN_DETECT) ? "detected" : "no",
618 edid->segments ? "found" : "no",
619 edid->blocks);
620 v4l2_info(sd, "%s output %s\n",
621 (adv7511_rd(sd, 0xaf) & 0x02) ?
622 "HDMI" : "DVI-D",
623 (adv7511_rd(sd, 0xa1) & 0x3c) ?
624 "disabled" : "enabled");
625 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
626 states[adv7511_rd(sd, 0xc8) & 0xf],
627 errors[adv7511_rd(sd, 0xc8) >> 4], state->edid_detect_counter,
628 adv7511_rd(sd, 0x94), adv7511_rd(sd, 0x96));
629 v4l2_info(sd, "RGB quantization: %s range\n", adv7511_rd(sd, 0x18) & 0x80 ? "limited" : "full");
3ecabed1
MB		 630 if (adv7511_rd(sd, 0xaf) & 0x02) {
631 /* HDMI only */
632 u8 manual_cts = adv7511_rd(sd, 0x0a) & 0x80;
633 u32 N = (adv7511_rd(sd, 0x01) & 0xf) << 16 |
634 adv7511_rd(sd, 0x02) << 8 |
635 adv7511_rd(sd, 0x03);
636 u8 vic_detect = adv7511_rd(sd, 0x3e) >> 2;
637 u8 vic_sent = adv7511_rd(sd, 0x3d) & 0x3f;
638 u32 CTS;
639
640 if (manual_cts)
641 CTS = (adv7511_rd(sd, 0x07) & 0xf) << 16 |
642 adv7511_rd(sd, 0x08) << 8 |
643 adv7511_rd(sd, 0x09);
644 else
645 CTS = (adv7511_rd(sd, 0x04) & 0xf) << 16 |
646 adv7511_rd(sd, 0x05) << 8 |
647 adv7511_rd(sd, 0x06);
648 v4l2_info(sd, "CTS %s mode: N %d, CTS %d\n",
649 manual_cts ? "manual" : "automatic", N, CTS);
650 v4l2_info(sd, "VIC: detected %d, sent %d\n",
651 vic_detect, vic_sent);
b4dbad8f 652 adv7511_log_infoframes(sd);
3ecabed1 653 }
5a544cce
HV		 654 if (state->dv_timings.type == V4L2_DV_BT_656_1120)
655 v4l2_print_dv_timings(sd->name, "timings: ",
656 &state->dv_timings, false);
657 else
658 v4l2_info(sd, "no timings set\n");
659 v4l2_info(sd, "i2c edid addr: 0x%x\n", state->i2c_edid_addr);
257d4eae
HV		 660
661 if (state->i2c_cec == NULL)
662 return 0;
663
5a544cce 664 v4l2_info(sd, "i2c cec addr: 0x%x\n", state->i2c_cec_addr);
257d4eae
HV		 665
666 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
667 "enabled" : "disabled");
668 if (state->cec_enabled_adap) {
669 for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
670 bool is_valid = state->cec_valid_addrs & (1 << i);
671
672 if (is_valid)
673 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
674 state->cec_addr[i]);
675 }
676 }
b4dbad8f 677 v4l2_info(sd, "i2c pktmem addr: 0x%x\n", state->i2c_pktmem_addr);
5a544cce
HV		 678 return 0;
679}
680
681/* Power up/down adv7511 */
682static int adv7511_s_power(struct v4l2_subdev *sd, int on)
683{
684 struct adv7511_state *state = get_adv7511_state(sd);
685 const int retries = 20;
686 int i;
687
688 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
689
690 state->power_on = on;
691
692 if (!on) {
693 /* Power down */
694 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x40);
695 return true;
696 }
697
698 /* Power up */
699 /* The adv7511 does not always come up immediately.
700 Retry multiple times. */
701 for (i = 0; i < retries; i++) {
702 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x0);
703 if ((adv7511_rd(sd, 0x41) & 0x40) == 0)
704 break;
705 adv7511_wr_and_or(sd, 0x41, 0xbf, 0x40);
706 msleep(10);
707 }
708 if (i == retries) {
709 v4l2_dbg(1, debug, sd, "%s: failed to powerup the adv7511!\n", __func__);
710 adv7511_s_power(sd, 0);
711 return false;
712 }
713 if (i > 1)
714 v4l2_dbg(1, debug, sd, "%s: needed %d retries to powerup the adv7511\n", __func__, i);
715
716 /* Reserved registers that must be set */
717 adv7511_wr(sd, 0x98, 0x03);
718 adv7511_wr_and_or(sd, 0x9a, 0xfe, 0x70);
719 adv7511_wr(sd, 0x9c, 0x30);
720 adv7511_wr_and_or(sd, 0x9d, 0xfc, 0x01);
721 adv7511_wr(sd, 0xa2, 0xa4);
722 adv7511_wr(sd, 0xa3, 0xa4);
723 adv7511_wr(sd, 0xe0, 0xd0);
724 adv7511_wr(sd, 0xf9, 0x00);
725
726 adv7511_wr(sd, 0x43, state->i2c_edid_addr);
b4dbad8f 727 adv7511_wr(sd, 0x45, state->i2c_pktmem_addr);
5a544cce
HV		 728
729 /* Set number of attempts to read the EDID */
730 adv7511_wr(sd, 0xc9, 0xf);
731 return true;
732}
733
257d4eae
HV		 734#if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
735static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable)
736{
737 struct adv7511_state *state = adap->priv;
738 struct v4l2_subdev *sd = &state->sd;
739
740 if (state->i2c_cec == NULL)
741 return -EIO;
742
743 if (!state->cec_enabled_adap && enable) {
744 /* power up cec section */
745 adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x01);
746 /* legacy mode and clear all rx buffers */
747 adv7511_cec_write(sd, 0x4a, 0x07);
748 adv7511_cec_write(sd, 0x4a, 0);
749 adv7511_cec_write_and_or(sd, 0x11, 0xfe, 0); /* initially disable tx */
750 /* enabled irqs: */
751 /* tx: ready */
752 /* tx: arbitration lost */
753 /* tx: retry timeout */
754 /* rx: ready 1 */
755 if (state->enabled_irq)
756 adv7511_wr_and_or(sd, 0x95, 0xc0, 0x39);
757 } else if (state->cec_enabled_adap && !enable) {
758 if (state->enabled_irq)
759 adv7511_wr_and_or(sd, 0x95, 0xc0, 0x00);
760 /* disable address mask 1-3 */
761 adv7511_cec_write_and_or(sd, 0x4b, 0x8f, 0x00);
762 /* power down cec section */
763 adv7511_cec_write_and_or(sd, 0x4e, 0xfc, 0x00);
764 state->cec_valid_addrs = 0;
765 }
766 state->cec_enabled_adap = enable;
767 return 0;
768}
769
770static int adv7511_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
771{
772 struct adv7511_state *state = adap->priv;
773 struct v4l2_subdev *sd = &state->sd;
774 unsigned int i, free_idx = ADV7511_MAX_ADDRS;
775
776 if (!state->cec_enabled_adap)
777 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
778
779 if (addr == CEC_LOG_ADDR_INVALID) {
780 adv7511_cec_write_and_or(sd, 0x4b, 0x8f, 0);
781 state->cec_valid_addrs = 0;
782 return 0;
783 }
784
785 for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
786 bool is_valid = state->cec_valid_addrs & (1 << i);
787
788 if (free_idx == ADV7511_MAX_ADDRS && !is_valid)
789 free_idx = i;
790 if (is_valid && state->cec_addr[i] == addr)
791 return 0;
792 }
793 if (i == ADV7511_MAX_ADDRS) {
794 i = free_idx;
795 if (i == ADV7511_MAX_ADDRS)
796 return -ENXIO;
797 }
798 state->cec_addr[i] = addr;
799 state->cec_valid_addrs |= 1 << i;
800
801 switch (i) {
802 case 0:
803 /* enable address mask 0 */
804 adv7511_cec_write_and_or(sd, 0x4b, 0xef, 0x10);
805 /* set address for mask 0 */
806 adv7511_cec_write_and_or(sd, 0x4c, 0xf0, addr);
807 break;
808 case 1:
809 /* enable address mask 1 */
810 adv7511_cec_write_and_or(sd, 0x4b, 0xdf, 0x20);
811 /* set address for mask 1 */
812 adv7511_cec_write_and_or(sd, 0x4c, 0x0f, addr << 4);
813 break;
814 case 2:
815 /* enable address mask 2 */
816 adv7511_cec_write_and_or(sd, 0x4b, 0xbf, 0x40);
817 /* set address for mask 1 */
818 adv7511_cec_write_and_or(sd, 0x4d, 0xf0, addr);
819 break;
820 }
821 return 0;
822}
823
824static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
825 u32 signal_free_time, struct cec_msg *msg)
826{
827 struct adv7511_state *state = adap->priv;
828 struct v4l2_subdev *sd = &state->sd;
829 u8 len = msg->len;
830 unsigned int i;
831
832 v4l2_dbg(1, debug, sd, "%s: len %d\n", __func__, len);
833
834 if (len > 16) {
835 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
836 return -EINVAL;
837 }
838
839 /*
840 * The number of retries is the number of attempts - 1, but retry
841 * at least once. It's not clear if a value of 0 is allowed, so
842 * let's do at least one retry.
843 */
844 adv7511_cec_write_and_or(sd, 0x12, ~0x70, max(1, attempts - 1) << 4);
845
846 /* blocking, clear cec tx irq status */
847 adv7511_wr_and_or(sd, 0x97, 0xc7, 0x38);
848
849 /* write data */
850 for (i = 0; i < len; i++)
851 adv7511_cec_write(sd, i, msg->msg[i]);
852
853 /* set length (data + header) */
854 adv7511_cec_write(sd, 0x10, len);
855 /* start transmit, enable tx */
856 adv7511_cec_write(sd, 0x11, 0x01);
857 return 0;
858}
859
860static void adv_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
861{
862 struct adv7511_state *state = get_adv7511_state(sd);
863
864 if ((adv7511_cec_read(sd, 0x11) & 0x01) == 0) {
865 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
866 return;
867 }
868
869 if (tx_raw_status & 0x10) {
870 v4l2_dbg(1, debug, sd,
871 "%s: tx raw: arbitration lost\n", __func__);
872 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
873 1, 0, 0, 0);
874 return;
875 }
876 if (tx_raw_status & 0x08) {
877 u8 status;
878 u8 nack_cnt;
879 u8 low_drive_cnt;
880
881 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
882 /*
883 * We set this status bit since this hardware performs
884 * retransmissions.
885 */
886 status = CEC_TX_STATUS_MAX_RETRIES;
887 nack_cnt = adv7511_cec_read(sd, 0x14) & 0xf;
888 if (nack_cnt)
889 status |= CEC_TX_STATUS_NACK;
890 low_drive_cnt = adv7511_cec_read(sd, 0x14) >> 4;
891 if (low_drive_cnt)
892 status |= CEC_TX_STATUS_LOW_DRIVE;
893 cec_transmit_done(state->cec_adap, status,
894 0, nack_cnt, low_drive_cnt, 0);
895 return;
896 }
897 if (tx_raw_status & 0x20) {
898 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
899 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
900 return;
901 }
902}
903
904static const struct cec_adap_ops adv7511_cec_adap_ops = {
905 .adap_enable = adv7511_cec_adap_enable,
906 .adap_log_addr = adv7511_cec_adap_log_addr,
907 .adap_transmit = adv7511_cec_adap_transmit,
908};
909#endif
910
5a544cce
HV		 911/* Enable interrupts */
912static void adv7511_set_isr(struct v4l2_subdev *sd, bool enable)
913{
257d4eae 914 struct adv7511_state *state = get_adv7511_state(sd);
5be50ef1
HV		 915 u8 irqs = MASK_ADV7511_HPD_INT | MASK_ADV7511_MSEN_INT;
916 u8 irqs_rd;
5a544cce
HV		 917 int retries = 100;
918
919 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? "enable" : "disable");
920
257d4eae
HV		 921 if (state->enabled_irq == enable)
922 return;
923 state->enabled_irq = enable;
924
5a544cce
HV		 925 /* The datasheet says that the EDID ready interrupt should be
926 disabled if there is no hotplug. */
927 if (!enable)
928 irqs = 0;
929 else if (adv7511_have_hotplug(sd))
930 irqs |= MASK_ADV7511_EDID_RDY_INT;
931
257d4eae
HV		 932 adv7511_wr_and_or(sd, 0x95, 0xc0,
933 (state->cec_enabled_adap && enable) ? 0x39 : 0x00);
934
5a544cce
HV		 935 /*
936 * This i2c write can fail (approx. 1 in 1000 writes). But it
937 * is essential that this register is correct, so retry it
938 * multiple times.
939 *
940 * Note that the i2c write does not report an error, but the readback
941 * clearly shows the wrong value.
942 */
943 do {
944 adv7511_wr(sd, 0x94, irqs);
945 irqs_rd = adv7511_rd(sd, 0x94);
946 } while (retries-- && irqs_rd != irqs);
947
948 if (irqs_rd == irqs)
949 return;
950 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
951}
952
953/* Interrupt handler */
954static int adv7511_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
955{
5be50ef1 956 u8 irq_status;
257d4eae 957 u8 cec_irq;
5a544cce
HV		 958
959 /* disable interrupts to prevent a race condition */
960 adv7511_set_isr(sd, false);
961 irq_status = adv7511_rd(sd, 0x96);
257d4eae 962 cec_irq = adv7511_rd(sd, 0x97);
5a544cce
HV		 963 /* clear detected interrupts */
964 adv7511_wr(sd, 0x96, irq_status);
257d4eae 965 adv7511_wr(sd, 0x97, cec_irq);
5a544cce 966
257d4eae
HV		 967 v4l2_dbg(1, debug, sd, "%s: irq 0x%x, cec-irq 0x%x\n", __func__,
968 irq_status, cec_irq);
5a544cce
HV		 969
970 if (irq_status & (MASK_ADV7511_HPD_INT | MASK_ADV7511_MSEN_INT))
971 adv7511_check_monitor_present_status(sd);
972 if (irq_status & MASK_ADV7511_EDID_RDY_INT)
973 adv7511_check_edid_status(sd);
974
257d4eae
HV		 975#if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
976 if (cec_irq & 0x38)
977 adv_cec_tx_raw_status(sd, cec_irq);
978
979 if (cec_irq & 1) {
980 struct adv7511_state *state = get_adv7511_state(sd);
981 struct cec_msg msg;
982
983 msg.len = adv7511_cec_read(sd, 0x25) & 0x1f;
984
985 v4l2_dbg(1, debug, sd, "%s: cec msg len %d\n", __func__,
986 msg.len);
987
988 if (msg.len > 16)
989 msg.len = 16;
990
991 if (msg.len) {
992 u8 i;
993
994 for (i = 0; i < msg.len; i++)
995 msg.msg[i] = adv7511_cec_read(sd, i + 0x15);
996
997 adv7511_cec_write(sd, 0x4a, 1); /* toggle to re-enable rx 1 */
998 adv7511_cec_write(sd, 0x4a, 0);
999 cec_received_msg(state->cec_adap, &msg);
1000 }
1001 }
1002#endif
1003
5a544cce
HV		 1004 /* enable interrupts */
1005 adv7511_set_isr(sd, true);
1006
1007 if (handled)
1008 *handled = true;
1009 return 0;
1010}
1011
5a544cce
HV		 1012static const struct v4l2_subdev_core_ops adv7511_core_ops = {
1013 .log_status = adv7511_log_status,
1014#ifdef CONFIG_VIDEO_ADV_DEBUG
1015 .g_register = adv7511_g_register,
1016 .s_register = adv7511_s_register,
1017#endif
1018 .s_power = adv7511_s_power,
1019 .interrupt_service_routine = adv7511_isr,
1020};
1021
1022/* ------------------------------ VIDEO OPS ------------------------------ */
1023
1024/* Enable/disable adv7511 output */
1025static int adv7511_s_stream(struct v4l2_subdev *sd, int enable)
1026{
1027 struct adv7511_state *state = get_adv7511_state(sd);
1028
1029 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
1030 adv7511_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
1031 if (enable) {
1032 adv7511_check_monitor_present_status(sd);
1033 } else {
1034 adv7511_s_power(sd, 0);
1035 state->have_monitor = false;
1036 }
1037 return 0;
1038}
1039
1040static int adv7511_s_dv_timings(struct v4l2_subdev *sd,
1041 struct v4l2_dv_timings *timings)
1042{
1043 struct adv7511_state *state = get_adv7511_state(sd);
bd3276a3
HV		 1044 struct v4l2_bt_timings *bt = &timings->bt;
1045 u32 fps;
5a544cce
HV		 1046
1047 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1048
1049 /* quick sanity check */
1050 if (!v4l2_valid_dv_timings(timings, &adv7511_timings_cap, NULL, NULL))
1051 return -EINVAL;
1052
1053 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1054 if the format is one of the CEA or DMT timings. */
1055 v4l2_find_dv_timings_cap(timings, &adv7511_timings_cap, 0, NULL, NULL);
1056
5a544cce
HV		 1057 /* save timings */
1058 state->dv_timings = *timings;
1059
65898fb9
HV		 1060 /* set h/vsync polarities */
1061 adv7511_wr_and_or(sd, 0x17, 0x9f,
bd3276a3
HV		 1062 ((bt->polarities & V4L2_DV_VSYNC_POS_POL) ? 0 : 0x40) |
1063 ((bt->polarities & V4L2_DV_HSYNC_POS_POL) ? 0 : 0x20));
1064
1065 fps = (u32)bt->pixelclock / (V4L2_DV_BT_FRAME_WIDTH(bt) * V4L2_DV_BT_FRAME_HEIGHT(bt));
1066 switch (fps) {
1067 case 24:
1068 adv7511_wr_and_or(sd, 0xfb, 0xf9, 1 << 1);
1069 break;
1070 case 25:
1071 adv7511_wr_and_or(sd, 0xfb, 0xf9, 2 << 1);
1072 break;
1073 case 30:
1074 adv7511_wr_and_or(sd, 0xfb, 0xf9, 3 << 1);
1075 break;
1076 default:
1077 adv7511_wr_and_or(sd, 0xfb, 0xf9, 0);
1078 break;
1079 }
65898fb9 1080
5a544cce
HV		 1081 /* update quantization range based on new dv_timings */
1082 adv7511_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
1083
5a544cce
HV		 1084 return 0;
1085}
1086
1087static int adv7511_g_dv_timings(struct v4l2_subdev *sd,
1088 struct v4l2_dv_timings *timings)
1089{
1090 struct adv7511_state *state = get_adv7511_state(sd);
1091
1092 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1093
1094 if (!timings)
1095 return -EINVAL;
1096
1097 *timings = state->dv_timings;
1098
1099 return 0;
1100}
1101
1102static int adv7511_enum_dv_timings(struct v4l2_subdev *sd,
1103 struct v4l2_enum_dv_timings *timings)
1104{
9646171f
LP		 1105 if (timings->pad != 0)
1106 return -EINVAL;
1107
5a544cce
HV		 1108 return v4l2_enum_dv_timings_cap(timings, &adv7511_timings_cap, NULL, NULL);
1109}
1110
1111static int adv7511_dv_timings_cap(struct v4l2_subdev *sd,
1112 struct v4l2_dv_timings_cap *cap)
1113{
9646171f
LP		 1114 if (cap->pad != 0)
1115 return -EINVAL;
1116
5a544cce
HV		 1117 *cap = adv7511_timings_cap;
1118 return 0;
1119}
1120
1121static const struct v4l2_subdev_video_ops adv7511_video_ops = {
1122 .s_stream = adv7511_s_stream,
1123 .s_dv_timings = adv7511_s_dv_timings,
1124 .g_dv_timings = adv7511_g_dv_timings,
5a544cce
HV		 1125};
1126
1127/* ------------------------------ AUDIO OPS ------------------------------ */
1128static int adv7511_s_audio_stream(struct v4l2_subdev *sd, int enable)
1129{
1130 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
1131
1132 if (enable)
1133 adv7511_wr_and_or(sd, 0x4b, 0x3f, 0x80);
1134 else
1135 adv7511_wr_and_or(sd, 0x4b, 0x3f, 0x40);
1136
1137 return 0;
1138}
1139
1140static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
1141{
1142 u32 N;
1143
1144 switch (freq) {
1145 case 32000: N = 4096; break;
1146 case 44100: N = 6272; break;
1147 case 48000: N = 6144; break;
1148 case 88200: N = 12544; break;
1149 case 96000: N = 12288; break;
1150 case 176400: N = 25088; break;
1151 case 192000: N = 24576; break;
1152 default:
1153 return -EINVAL;
1154 }
1155
1156 /* Set N (used with CTS to regenerate the audio clock) */
1157 adv7511_wr(sd, 0x01, (N >> 16) & 0xf);
1158 adv7511_wr(sd, 0x02, (N >> 8) & 0xff);
1159 adv7511_wr(sd, 0x03, N & 0xff);
1160
1161 return 0;
1162}
1163
1164static int adv7511_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
1165{
1166 u32 i2s_sf;
1167
1168 switch (freq) {
1169 case 32000: i2s_sf = 0x30; break;
1170 case 44100: i2s_sf = 0x00; break;
1171 case 48000: i2s_sf = 0x20; break;
1172 case 88200: i2s_sf = 0x80; break;
1173 case 96000: i2s_sf = 0xa0; break;
1174 case 176400: i2s_sf = 0xc0; break;
1175 case 192000: i2s_sf = 0xe0; break;
1176 default:
1177 return -EINVAL;
1178 }
1179
1180 /* Set sampling frequency for I2S audio to 48 kHz */
1181 adv7511_wr_and_or(sd, 0x15, 0xf, i2s_sf);
1182
1183 return 0;
1184}
1185
1186static int adv7511_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
1187{
1188 /* Only 2 channels in use for application */
1189 adv7511_wr_and_or(sd, 0x73, 0xf8, 0x1);
1190 /* Speaker mapping */
1191 adv7511_wr(sd, 0x76, 0x00);
1192
1193 /* 16 bit audio word length */
1194 adv7511_wr_and_or(sd, 0x14, 0xf0, 0x02);
1195
1196 return 0;
1197}
1198
1199static const struct v4l2_subdev_audio_ops adv7511_audio_ops = {
1200 .s_stream = adv7511_s_audio_stream,
1201 .s_clock_freq = adv7511_s_clock_freq,
1202 .s_i2s_clock_freq = adv7511_s_i2s_clock_freq,
1203 .s_routing = adv7511_s_routing,
1204};
1205
9646171f
LP		 1206/* ---------------------------- PAD OPS ------------------------------------- */
1207
1208static int adv7511_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1209{
1210 struct adv7511_state *state = get_adv7511_state(sd);
1211
c81285ae
HV		 1212 memset(edid->reserved, 0, sizeof(edid->reserved));
1213
9646171f
LP		 1214 if (edid->pad != 0)
1215 return -EINVAL;
c81285ae
HV		 1216
1217 if (edid->start_block == 0 && edid->blocks == 0) {
1218 edid->blocks = state->edid.segments * 2;
1219 return 0;
9646171f 1220 }
c81285ae
HV		 1221
1222 if (state->edid.segments == 0)
1223 return -ENODATA;
1224
9646171f 1225 if (edid->start_block >= state->edid.segments * 2)
c81285ae
HV		 1226 return -EINVAL;
1227
1228 if (edid->start_block + edid->blocks > state->edid.segments * 2)
9646171f
LP		 1229 edid->blocks = state->edid.segments * 2 - edid->start_block;
1230
1231 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
1232 128 * edid->blocks);
c81285ae 1233
9646171f
LP		 1234 return 0;
1235}
1236
1fb69bfd 1237static int adv7511_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 1238 struct v4l2_subdev_pad_config *cfg,
1fb69bfd
HV		 1239 struct v4l2_subdev_mbus_code_enum *code)
1240{
1241 if (code->pad != 0)
1242 return -EINVAL;
1243
1244 switch (code->index) {
1245 case 0:
1246 code->code = MEDIA_BUS_FMT_RGB888_1X24;
1247 break;
1248 case 1:
1249 code->code = MEDIA_BUS_FMT_YUYV8_1X16;
1250 break;
1251 case 2:
1252 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
1253 break;
1254 default:
1255 return -EINVAL;
1256 }
1257 return 0;
1258}
1259
1260static void adv7511_fill_format(struct adv7511_state *state,
1261 struct v4l2_mbus_framefmt *format)
1262{
1fb69bfd
HV		 1263 format->width = state->dv_timings.bt.width;
1264 format->height = state->dv_timings.bt.height;
1265 format->field = V4L2_FIELD_NONE;
1266}
1267
f7234138
HV		 1268static int adv7511_get_fmt(struct v4l2_subdev *sd,
1269 struct v4l2_subdev_pad_config *cfg,
1270 struct v4l2_subdev_format *format)
1fb69bfd
HV		 1271{
1272 struct adv7511_state *state = get_adv7511_state(sd);
1273
1274 if (format->pad != 0)
1275 return -EINVAL;
1276
0a25a012 1277 memset(&format->format, 0, sizeof(format->format));
1fb69bfd
HV		 1278 adv7511_fill_format(state, &format->format);
1279
1280 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1281 struct v4l2_mbus_framefmt *fmt;
1282
f7234138 1283 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1fb69bfd
HV		 1284 format->format.code = fmt->code;
1285 format->format.colorspace = fmt->colorspace;
1286 format->format.ycbcr_enc = fmt->ycbcr_enc;
1287 format->format.quantization = fmt->quantization;
e719a51a 1288 format->format.xfer_func = fmt->xfer_func;
1fb69bfd
HV		 1289 } else {
1290 format->format.code = state->fmt_code;
1291 format->format.colorspace = state->colorspace;
1292 format->format.ycbcr_enc = state->ycbcr_enc;
1293 format->format.quantization = state->quantization;
e719a51a 1294 format->format.xfer_func = state->xfer_func;
1fb69bfd
HV		 1295 }
1296
1297 return 0;
1298}
1299
f7234138
HV		 1300static int adv7511_set_fmt(struct v4l2_subdev *sd,
1301 struct v4l2_subdev_pad_config *cfg,
1302 struct v4l2_subdev_format *format)
1fb69bfd
HV		 1303{
1304 struct adv7511_state *state = get_adv7511_state(sd);
1305 /*
1306 * Bitfield namings come the CEA-861-F standard, table 8 "Auxiliary
1307 * Video Information (AVI) InfoFrame Format"
1308 *
1309 * c = Colorimetry
1310 * ec = Extended Colorimetry
1311 * y = RGB or YCbCr
1312 * q = RGB Quantization Range
1313 * yq = YCC Quantization Range
1314 */
1315 u8 c = HDMI_COLORIMETRY_NONE;
1316 u8 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1317 u8 y = HDMI_COLORSPACE_RGB;
1318 u8 q = HDMI_QUANTIZATION_RANGE_DEFAULT;
1319 u8 yq = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
df0e5775
HV		 1320 u8 itc = state->content_type != V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1321 u8 cn = itc ? state->content_type : V4L2_DV_IT_CONTENT_TYPE_GRAPHICS;
1fb69bfd
HV		 1322
1323 if (format->pad != 0)
1324 return -EINVAL;
1325 switch (format->format.code) {
1326 case MEDIA_BUS_FMT_UYVY8_1X16:
1327 case MEDIA_BUS_FMT_YUYV8_1X16:
1328 case MEDIA_BUS_FMT_RGB888_1X24:
1329 break;
1330 default:
1331 return -EINVAL;
1332 }
1333
1334 adv7511_fill_format(state, &format->format);
1335 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1336 struct v4l2_mbus_framefmt *fmt;
1337
f7234138 1338 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1fb69bfd
HV		 1339 fmt->code = format->format.code;
1340 fmt->colorspace = format->format.colorspace;
1341 fmt->ycbcr_enc = format->format.ycbcr_enc;
1342 fmt->quantization = format->format.quantization;
e719a51a 1343 fmt->xfer_func = format->format.xfer_func;
1fb69bfd
HV		 1344 return 0;
1345 }
1346
1347 switch (format->format.code) {
1348 case MEDIA_BUS_FMT_UYVY8_1X16:
1349 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x01);
1350 adv7511_wr_and_or(sd, 0x16, 0x03, 0xb8);
1351 y = HDMI_COLORSPACE_YUV422;
1352 break;
1353 case MEDIA_BUS_FMT_YUYV8_1X16:
1354 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x01);
1355 adv7511_wr_and_or(sd, 0x16, 0x03, 0xbc);
1356 y = HDMI_COLORSPACE_YUV422;
1357 break;
1358 case MEDIA_BUS_FMT_RGB888_1X24:
1359 default:
1360 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x00);
1361 adv7511_wr_and_or(sd, 0x16, 0x03, 0x00);
1362 break;
1363 }
1364 state->fmt_code = format->format.code;
1365 state->colorspace = format->format.colorspace;
1366 state->ycbcr_enc = format->format.ycbcr_enc;
1367 state->quantization = format->format.quantization;
e719a51a 1368 state->xfer_func = format->format.xfer_func;
1fb69bfd
HV		 1369
1370 switch (format->format.colorspace) {
1371 case V4L2_COLORSPACE_ADOBERGB:
1372 c = HDMI_COLORIMETRY_EXTENDED;
1373 ec = y ? HDMI_EXTENDED_COLORIMETRY_ADOBE_YCC_601 :
1374 HDMI_EXTENDED_COLORIMETRY_ADOBE_RGB;
1375 break;
1376 case V4L2_COLORSPACE_SMPTE170M:
1377 c = y ? HDMI_COLORIMETRY_ITU_601 : HDMI_COLORIMETRY_NONE;
1378 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_XV601) {
1379 c = HDMI_COLORIMETRY_EXTENDED;
1380 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1381 }
1382 break;
1383 case V4L2_COLORSPACE_REC709:
1384 c = y ? HDMI_COLORIMETRY_ITU_709 : HDMI_COLORIMETRY_NONE;
1385 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_XV709) {
1386 c = HDMI_COLORIMETRY_EXTENDED;
1387 ec = HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1388 }
1389 break;
1390 case V4L2_COLORSPACE_SRGB:
1391 c = y ? HDMI_COLORIMETRY_EXTENDED : HDMI_COLORIMETRY_NONE;
1392 ec = y ? HDMI_EXTENDED_COLORIMETRY_S_YCC_601 :
1393 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1394 break;
1395 case V4L2_COLORSPACE_BT2020:
1396 c = HDMI_COLORIMETRY_EXTENDED;
1397 if (y && format->format.ycbcr_enc == V4L2_YCBCR_ENC_BT2020_CONST_LUM)
1398 ec = 5; /* Not yet available in hdmi.h */
1399 else
1400 ec = 6; /* Not yet available in hdmi.h */
1401 break;
1402 default:
1403 break;
1404 }
1405
1406 /*
1407 * CEA-861-F says that for RGB formats the YCC range must match the
1408 * RGB range, although sources should ignore the YCC range.
1409 *
1410 * The RGB quantization range shouldn't be non-zero if the EDID doesn't
1411 * have the Q bit set in the Video Capabilities Data Block, however this
1412 * isn't checked at the moment. The assumption is that the application
1413 * knows the EDID and can detect this.
1414 *
1415 * The same is true for the YCC quantization range: non-standard YCC
1416 * quantization ranges should only be sent if the EDID has the YQ bit
1417 * set in the Video Capabilities Data Block.
1418 */
1419 switch (format->format.quantization) {
1420 case V4L2_QUANTIZATION_FULL_RANGE:
1421 q = y ? HDMI_QUANTIZATION_RANGE_DEFAULT :
1422 HDMI_QUANTIZATION_RANGE_FULL;
1423 yq = q ? q - 1 : HDMI_YCC_QUANTIZATION_RANGE_FULL;
1424 break;
1425 case V4L2_QUANTIZATION_LIM_RANGE:
1426 q = y ? HDMI_QUANTIZATION_RANGE_DEFAULT :
1427 HDMI_QUANTIZATION_RANGE_LIMITED;
1428 yq = q ? q - 1 : HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1429 break;
1430 }
1431
1432 adv7511_wr_and_or(sd, 0x4a, 0xbf, 0);
1433 adv7511_wr_and_or(sd, 0x55, 0x9f, y << 5);
1434 adv7511_wr_and_or(sd, 0x56, 0x3f, c << 6);
df0e5775
HV		 1435 adv7511_wr_and_or(sd, 0x57, 0x83, (ec << 4) | (q << 2) | (itc << 7));
1436 adv7511_wr_and_or(sd, 0x59, 0x0f, (yq << 6) | (cn << 4));
1fb69bfd 1437 adv7511_wr_and_or(sd, 0x4a, 0xff, 1);
0a25a012 1438 adv7511_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
1fb69bfd
HV		 1439
1440 return 0;
1441}
1442
9646171f
LP		 1443static const struct v4l2_subdev_pad_ops adv7511_pad_ops = {
1444 .get_edid = adv7511_get_edid,
1fb69bfd
HV		 1445 .enum_mbus_code = adv7511_enum_mbus_code,
1446 .get_fmt = adv7511_get_fmt,
1447 .set_fmt = adv7511_set_fmt,
9646171f
LP		 1448 .enum_dv_timings = adv7511_enum_dv_timings,
1449 .dv_timings_cap = adv7511_dv_timings_cap,
1450};
1451
5a544cce
HV		 1452/* --------------------- SUBDEV OPS --------------------------------------- */
1453
1454static const struct v4l2_subdev_ops adv7511_ops = {
1455 .core = &adv7511_core_ops,
1456 .pad = &adv7511_pad_ops,
1457 .video = &adv7511_video_ops,
1458 .audio = &adv7511_audio_ops,
1459};
1460
1461/* ----------------------------------------------------------------------- */
5be50ef1 1462static void adv7511_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd, int segment, u8 *buf)
5a544cce
HV		 1463{
1464 if (debug >= lvl) {
1465 int i, j;
1466 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
1467 for (i = 0; i < 256; i += 16) {
1468 u8 b[128];
1469 u8 *bp = b;
1470 if (i == 128)
1471 v4l2_dbg(lvl, debug, sd, "\n");
1472 for (j = i; j < i + 16; j++) {
1473 sprintf(bp, "0x%02x, ", buf[j]);
1474 bp += 6;
1475 }
1476 bp[0] = '\0';
1477 v4l2_dbg(lvl, debug, sd, "%s\n", b);
1478 }
1479 }
1480}
1481
b339a72e
HV		 1482static void adv7511_notify_no_edid(struct v4l2_subdev *sd)
1483{
1484 struct adv7511_state *state = get_adv7511_state(sd);
1485 struct adv7511_edid_detect ed;
1486
1487 /* We failed to read the EDID, so send an event for this. */
1488 ed.present = false;
1489 ed.segment = adv7511_rd(sd, 0xc4);
257d4eae
HV		 1490 ed.phys_addr = CEC_PHYS_ADDR_INVALID;
1491 cec_s_phys_addr(state->cec_adap, ed.phys_addr, false);
b339a72e
HV		 1492 v4l2_subdev_notify(sd, ADV7511_EDID_DETECT, (void *)&ed);
1493 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, 0x0);
1494}
1495
5a544cce
HV		 1496static void adv7511_edid_handler(struct work_struct *work)
1497{
1498 struct delayed_work *dwork = to_delayed_work(work);
1499 struct adv7511_state *state = container_of(dwork, struct adv7511_state, edid_handler);
1500 struct v4l2_subdev *sd = &state->sd;
5a544cce
HV		 1501
1502 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1503
1504 if (adv7511_check_edid_status(sd)) {
1505 /* Return if we received the EDID. */
1506 return;
1507 }
1508
1509 if (adv7511_have_hotplug(sd)) {
1510 /* We must retry reading the EDID several times, it is possible
1511 * that initially the EDID couldn't be read due to i2c errors
1512 * (DVI connectors are particularly prone to this problem). */
1513 if (state->edid.read_retries) {
1514 state->edid.read_retries--;
1515 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
1516 state->have_monitor = false;
1517 adv7511_s_power(sd, false);
1518 adv7511_s_power(sd, true);
1519 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1520 return;
1521 }
1522 }
1523
1524 /* We failed to read the EDID, so send an event for this. */
b339a72e 1525 adv7511_notify_no_edid(sd);
5a544cce
HV		 1526 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
1527}
1528
1529static void adv7511_audio_setup(struct v4l2_subdev *sd)
1530{
1531 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1532
1533 adv7511_s_i2s_clock_freq(sd, 48000);
1534 adv7511_s_clock_freq(sd, 48000);
1535 adv7511_s_routing(sd, 0, 0, 0);
1536}
1537
1538/* Configure hdmi transmitter. */
1539static void adv7511_setup(struct v4l2_subdev *sd)
1540{
1541 struct adv7511_state *state = get_adv7511_state(sd);
1542 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1543
1544 /* Input format: RGB 4:4:4 */
1545 adv7511_wr_and_or(sd, 0x15, 0xf0, 0x0);
1546 /* Output format: RGB 4:4:4 */
1547 adv7511_wr_and_or(sd, 0x16, 0x7f, 0x0);
1548 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion, Aspect ratio: 16:9 */
1549 adv7511_wr_and_or(sd, 0x17, 0xf9, 0x06);
1550 /* Disable pixel repetition */
1551 adv7511_wr_and_or(sd, 0x3b, 0x9f, 0x0);
1552 /* Disable CSC */
1553 adv7511_wr_and_or(sd, 0x18, 0x7f, 0x0);
1554 /* Output format: RGB 4:4:4, Active Format Information is valid,
1555 * underscanned */
1556 adv7511_wr_and_or(sd, 0x55, 0x9c, 0x12);
1557 /* AVI Info frame packet enable, Audio Info frame disable */
1558 adv7511_wr_and_or(sd, 0x44, 0xe7, 0x10);
1559 /* Colorimetry, Active format aspect ratio: same as picure. */
1560 adv7511_wr(sd, 0x56, 0xa8);
1561 /* No encryption */
1562 adv7511_wr_and_or(sd, 0xaf, 0xed, 0x0);
1563
1564 /* Positive clk edge capture for input video clock */
1565 adv7511_wr_and_or(sd, 0xba, 0x1f, 0x60);
1566
1567 adv7511_audio_setup(sd);
1568
1569 v4l2_ctrl_handler_setup(&state->hdl);
1570}
1571
1572static void adv7511_notify_monitor_detect(struct v4l2_subdev *sd)
1573{
1574 struct adv7511_monitor_detect mdt;
1575 struct adv7511_state *state = get_adv7511_state(sd);
1576
1577 mdt.present = state->have_monitor;
1578 v4l2_subdev_notify(sd, ADV7511_MONITOR_DETECT, (void *)&mdt);
1579}
1580
1581static void adv7511_check_monitor_present_status(struct v4l2_subdev *sd)
1582{
1583 struct adv7511_state *state = get_adv7511_state(sd);
1584 /* read hotplug and rx-sense state */
5be50ef1 1585 u8 status = adv7511_rd(sd, 0x42);
5a544cce
HV		 1586
1587 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
1588 __func__,
1589 status,
1590 status & MASK_ADV7511_HPD_DETECT ? ", hotplug" : "",
1591 status & MASK_ADV7511_MSEN_DETECT ? ", rx-sense" : "");
1592
1593 /* update read only ctrls */
1594 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, adv7511_have_hotplug(sd) ? 0x1 : 0x0);
1595 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, adv7511_have_rx_sense(sd) ? 0x1 : 0x0);
5a544cce
HV		 1596
1597 if ((status & MASK_ADV7511_HPD_DETECT) && ((status & MASK_ADV7511_MSEN_DETECT) || state->edid.segments)) {
1598 v4l2_dbg(1, debug, sd, "%s: hotplug and (rx-sense or edid)\n", __func__);
1599 if (!state->have_monitor) {
1600 v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
1601 state->have_monitor = true;
1602 adv7511_set_isr(sd, true);
1603 if (!adv7511_s_power(sd, true)) {
1604 v4l2_dbg(1, debug, sd, "%s: monitor detected, powerup failed\n", __func__);
1605 return;
1606 }
1607 adv7511_setup(sd);
1608 adv7511_notify_monitor_detect(sd);
1609 state->edid.read_retries = EDID_MAX_RETRIES;
1610 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1611 }
1612 } else if (status & MASK_ADV7511_HPD_DETECT) {
1613 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
1614 state->edid.read_retries = EDID_MAX_RETRIES;
1615 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1616 } else if (!(status & MASK_ADV7511_HPD_DETECT)) {
1617 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
1618 if (state->have_monitor) {
1619 v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
1620 state->have_monitor = false;
1621 adv7511_notify_monitor_detect(sd);
1622 }
1623 adv7511_s_power(sd, false);
1624 memset(&state->edid, 0, sizeof(struct adv7511_state_edid));
b339a72e 1625 adv7511_notify_no_edid(sd);
5a544cce
HV		 1626 }
1627}
1628
5be50ef1 1629static bool edid_block_verify_crc(u8 *edid_block)
5a544cce 1630{
5be50ef1 1631 u8 sum = 0;
928b0fe7 1632 int i;
5a544cce
HV		 1633
1634 for (i = 0; i < 128; i++)
928b0fe7
MB		 1635 sum += edid_block[i];
1636 return sum == 0;
5a544cce
HV		 1637}
1638
928b0fe7 1639static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
5a544cce
HV		 1640{
1641 struct adv7511_state *state = get_adv7511_state(sd);
1642 u32 blocks = state->edid.blocks;
5be50ef1 1643 u8 *data = state->edid.data;
5a544cce 1644
928b0fe7
MB		 1645 if (!edid_block_verify_crc(&data[segment * 256]))
1646 return false;
1647 if ((segment + 1) * 2 <= blocks)
1648 return edid_block_verify_crc(&data[segment * 256 + 128]);
1649 return true;
1650}
1651
1652static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
1653{
1654 static const u8 hdmi_header[] = {
1655 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1656 };
1657 struct adv7511_state *state = get_adv7511_state(sd);
1658 u8 *data = state->edid.data;
1659
1660 if (segment != 0)
5a544cce 1661 return true;
928b0fe7 1662 return !memcmp(data, hdmi_header, sizeof(hdmi_header));
5a544cce
HV		 1663}
1664
1665static bool adv7511_check_edid_status(struct v4l2_subdev *sd)
1666{
1667 struct adv7511_state *state = get_adv7511_state(sd);
5be50ef1 1668 u8 edidRdy = adv7511_rd(sd, 0xc5);
5a544cce
HV		 1669
1670 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1671 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1672
1673 if (state->edid.complete)
1674 return true;
1675
1676 if (edidRdy & MASK_ADV7511_EDID_RDY) {
1677 int segment = adv7511_rd(sd, 0xc4);
1678 struct adv7511_edid_detect ed;
1679
1680 if (segment >= EDID_MAX_SEGM) {
1681 v4l2_err(sd, "edid segment number too big\n");
1682 return false;
1683 }
1684 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1685 adv7511_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1686 adv7511_dbg_dump_edid(2, debug, sd, segment, &state->edid.data[segment * 256]);
1687 if (segment == 0) {
1688 state->edid.blocks = state->edid.data[0x7e] + 1;
1689 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n", __func__, state->edid.blocks);
1690 }
928b0fe7
MB		 1691 if (!edid_verify_crc(sd, segment) ||
1692 !edid_verify_header(sd, segment)) {
5a544cce 1693 /* edid crc error, force reread of edid segment */
928b0fe7 1694 v4l2_err(sd, "%s: edid crc or header error\n", __func__);
5a544cce
HV		 1695 state->have_monitor = false;
1696 adv7511_s_power(sd, false);
1697 adv7511_s_power(sd, true);
1698 return false;
1699 }
1700 /* one more segment read ok */
1701 state->edid.segments = segment + 1;
b339a72e 1702 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, 0x1);
5a544cce
HV		 1703 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1704 /* Request next EDID segment */
1705 v4l2_dbg(1, debug, sd, "%s: request segment %d\n", __func__, state->edid.segments);
1706 adv7511_wr(sd, 0xc9, 0xf);
1707 adv7511_wr(sd, 0xc4, state->edid.segments);
1708 state->edid.read_retries = EDID_MAX_RETRIES;
1709 queue_delayed_work(state->work_queue, &state->edid_handler, EDID_DELAY);
1710 return false;
1711 }
1712
1713 v4l2_dbg(1, debug, sd, "%s: edid complete with %d segment(s)\n", __func__, state->edid.segments);
1714 state->edid.complete = true;
257d4eae
HV		 1715 ed.phys_addr = cec_get_edid_phys_addr(state->edid.data,
1716 state->edid.segments * 256,
1717 NULL);
5a544cce
HV		 1718 /* report when we have all segments
1719 but report only for segment 0
1720 */
1721 ed.present = true;
1722 ed.segment = 0;
1723 state->edid_detect_counter++;
257d4eae 1724 cec_s_phys_addr(state->cec_adap, ed.phys_addr, false);
5a544cce
HV		 1725 v4l2_subdev_notify(sd, ADV7511_EDID_DETECT, (void *)&ed);
1726 return ed.present;
1727 }
1728
1729 return false;
1730}
1731
257d4eae
HV		 1732static int adv7511_registered(struct v4l2_subdev *sd)
1733{
1734 struct adv7511_state *state = get_adv7511_state(sd);
1735 int err;
1736
1737 err = cec_register_adapter(state->cec_adap);
1738 if (err)
1739 cec_delete_adapter(state->cec_adap);
1740 return err;
1741}
1742
1743static void adv7511_unregistered(struct v4l2_subdev *sd)
1744{
1745 struct adv7511_state *state = get_adv7511_state(sd);
1746
1747 cec_unregister_adapter(state->cec_adap);
1748}
1749
1750static const struct v4l2_subdev_internal_ops adv7511_int_ops = {
1751 .registered = adv7511_registered,
1752 .unregistered = adv7511_unregistered,
1753};
1754
5a544cce
HV		 1755/* ----------------------------------------------------------------------- */
1756/* Setup ADV7511 */
1757static void adv7511_init_setup(struct v4l2_subdev *sd)
1758{
1759 struct adv7511_state *state = get_adv7511_state(sd);
1760 struct adv7511_state_edid *edid = &state->edid;
257d4eae
HV		 1761 u32 cec_clk = state->pdata.cec_clk;
1762 u8 ratio;
5a544cce
HV		 1763
1764 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1765
1766 /* clear all interrupts */
1767 adv7511_wr(sd, 0x96, 0xff);
257d4eae 1768 adv7511_wr(sd, 0x97, 0xff);
a62c6216
MB		 1769 /*
1770 * Stop HPD from resetting a lot of registers.
1771 * It might leave the chip in a partly un-initialized state,
1772 * in particular with regards to hotplug bounces.
1773 */
1774 adv7511_wr_and_or(sd, 0xd6, 0x3f, 0xc0);
5a544cce
HV		 1775 memset(edid, 0, sizeof(struct adv7511_state_edid));
1776 state->have_monitor = false;
1777 adv7511_set_isr(sd, false);
1778 adv7511_s_stream(sd, false);
1779 adv7511_s_audio_stream(sd, false);
257d4eae
HV		 1780
1781 if (state->i2c_cec == NULL)
1782 return;
1783
1784 v4l2_dbg(1, debug, sd, "%s: cec_clk %d\n", __func__, cec_clk);
1785
1786 /* cec soft reset */
1787 adv7511_cec_write(sd, 0x50, 0x01);
1788 adv7511_cec_write(sd, 0x50, 0x00);
1789
1790 /* legacy mode */
1791 adv7511_cec_write(sd, 0x4a, 0x00);
1792
1793 if (cec_clk % 750000 != 0)
1794 v4l2_err(sd, "%s: cec_clk %d, not multiple of 750 Khz\n",
1795 __func__, cec_clk);
1796
1797 ratio = (cec_clk / 750000) - 1;
1798 adv7511_cec_write(sd, 0x4e, ratio << 2);
5a544cce
HV		 1799}
1800
1801static int adv7511_probe(struct i2c_client *client, const struct i2c_device_id *id)
1802{
1803 struct adv7511_state *state;
1804 struct adv7511_platform_data *pdata = client->dev.platform_data;
1805 struct v4l2_ctrl_handler *hdl;
1806 struct v4l2_subdev *sd;
1807 u8 chip_id[2];
1808 int err = -EIO;
1809
1810 /* Check if the adapter supports the needed features */
1811 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1812 return -EIO;
1813
1814 state = devm_kzalloc(&client->dev, sizeof(struct adv7511_state), GFP_KERNEL);
1815 if (!state)
1816 return -ENOMEM;
1817
1818 /* Platform data */
1819 if (!pdata) {
1820 v4l_err(client, "No platform data!\n");
1821 return -ENODEV;
1822 }
1823 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1fb69bfd
HV		 1824 state->fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
1825 state->colorspace = V4L2_COLORSPACE_SRGB;
5a544cce
HV		 1826
1827 sd = &state->sd;
1828
1829 v4l2_dbg(1, debug, sd, "detecting adv7511 client on address 0x%x\n",
1830 client->addr << 1);
1831
1832 v4l2_i2c_subdev_init(sd, client, &adv7511_ops);
257d4eae 1833 sd->internal_ops = &adv7511_int_ops;
5a544cce
HV		 1834
1835 hdl = &state->hdl;
1836 v4l2_ctrl_handler_init(hdl, 10);
1837 /* add in ascending ID order */
1838 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1839 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1840 0, V4L2_DV_TX_MODE_DVI_D);
1841 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1842 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1843 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1844 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1845 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1846 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1847 state->rgb_quantization_range_ctrl =
1848 v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1849 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1850 0, V4L2_DV_RGB_RANGE_AUTO);
df0e5775
HV		 1851 state->content_type_ctrl =
1852 v4l2_ctrl_new_std_menu(hdl, &adv7511_ctrl_ops,
1853 V4L2_CID_DV_TX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
1854 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
5a544cce
HV		 1855 sd->ctrl_handler = hdl;
1856 if (hdl->error) {
1857 err = hdl->error;
1858 goto err_hdl;
1859 }
5a544cce 1860 state->pad.flags = MEDIA_PAD_FL_SINK;
ab22e77c 1861 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
5a544cce
HV		 1862 if (err)
1863 goto err_hdl;
1864
1865 /* EDID and CEC i2c addr */
1866 state->i2c_edid_addr = state->pdata.i2c_edid << 1;
1867 state->i2c_cec_addr = state->pdata.i2c_cec << 1;
b4dbad8f 1868 state->i2c_pktmem_addr = state->pdata.i2c_pktmem << 1;
5a544cce
HV		 1869
1870 state->chip_revision = adv7511_rd(sd, 0x0);
1871 chip_id[0] = adv7511_rd(sd, 0xf5);
1872 chip_id[1] = adv7511_rd(sd, 0xf6);
1873 if (chip_id[0] != 0x75 || chip_id[1] != 0x11) {
257d4eae
HV		 1874 v4l2_err(sd, "chip_id != 0x7511, read 0x%02x%02x\n", chip_id[0],
1875 chip_id[1]);
5a544cce
HV		 1876 err = -EIO;
1877 goto err_entity;
1878 }
1879
257d4eae
HV		 1880 state->i2c_edid = i2c_new_dummy(client->adapter,
1881 state->i2c_edid_addr >> 1);
5a544cce
HV		 1882 if (state->i2c_edid == NULL) {
1883 v4l2_err(sd, "failed to register edid i2c client\n");
f527b17a 1884 err = -ENOMEM;
5a544cce
HV		 1885 goto err_entity;
1886 }
1887
257d4eae
HV		 1888 adv7511_wr(sd, 0xe1, state->i2c_cec_addr);
1889 if (state->pdata.cec_clk < 3000000 ||
1890 state->pdata.cec_clk > 100000000) {
1891 v4l2_err(sd, "%s: cec_clk %u outside range, disabling cec\n",
1892 __func__, state->pdata.cec_clk);
1893 state->pdata.cec_clk = 0;
1894 }
1895
1896 if (state->pdata.cec_clk) {
1897 state->i2c_cec = i2c_new_dummy(client->adapter,
1898 state->i2c_cec_addr >> 1);
1899 if (state->i2c_cec == NULL) {
1900 v4l2_err(sd, "failed to register cec i2c client\n");
b956fb2d 1901 err = -ENOMEM;
257d4eae
HV		 1902 goto err_unreg_edid;
1903 }
1904 adv7511_wr(sd, 0xe2, 0x00); /* power up cec section */
1905 } else {
1906 adv7511_wr(sd, 0xe2, 0x01); /* power down cec section */
1907 }
1908
b4dbad8f
HV		 1909 state->i2c_pktmem = i2c_new_dummy(client->adapter, state->i2c_pktmem_addr >> 1);
1910 if (state->i2c_pktmem == NULL) {
1911 v4l2_err(sd, "failed to register pktmem i2c client\n");
1912 err = -ENOMEM;
257d4eae 1913 goto err_unreg_cec;
b4dbad8f
HV		 1914 }
1915
5a544cce
HV		 1916 state->work_queue = create_singlethread_workqueue(sd->name);
1917 if (state->work_queue == NULL) {
1918 v4l2_err(sd, "could not create workqueue\n");
f527b17a 1919 err = -ENOMEM;
b4dbad8f 1920 goto err_unreg_pktmem;
5a544cce
HV		 1921 }
1922
1923 INIT_DELAYED_WORK(&state->edid_handler, adv7511_edid_handler);
1924
1925 adv7511_init_setup(sd);
257d4eae
HV		 1926
1927#if IS_ENABLED(CONFIG_VIDEO_ADV7511_CEC)
1928 state->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops,
1929 state, dev_name(&client->dev), CEC_CAP_TRANSMIT |
1930 CEC_CAP_LOG_ADDRS | CEC_CAP_PASSTHROUGH | CEC_CAP_RC,
1931 ADV7511_MAX_ADDRS, &client->dev);
1932 err = PTR_ERR_OR_ZERO(state->cec_adap);
1933 if (err) {
1934 destroy_workqueue(state->work_queue);
1935 goto err_unreg_pktmem;
1936 }
1937#endif
1938
5a544cce
HV		 1939 adv7511_set_isr(sd, true);
1940 adv7511_check_monitor_present_status(sd);
1941
1942 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1943 client->addr << 1, client->adapter->name);
1944 return 0;
1945
b4dbad8f
HV		 1946err_unreg_pktmem:
1947 i2c_unregister_device(state->i2c_pktmem);
257d4eae
HV		 1948err_unreg_cec:
1949 if (state->i2c_cec)
1950 i2c_unregister_device(state->i2c_cec);
b4dbad8f 1951err_unreg_edid:
5a544cce
HV		 1952 i2c_unregister_device(state->i2c_edid);
1953err_entity:
1954 media_entity_cleanup(&sd->entity);
1955err_hdl:
1956 v4l2_ctrl_handler_free(&state->hdl);
1957 return err;
1958}
1959
1960/* ----------------------------------------------------------------------- */
1961
1962static int adv7511_remove(struct i2c_client *client)
1963{
1964 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1965 struct adv7511_state *state = get_adv7511_state(sd);
1966
1967 state->chip_revision = -1;
1968
1969 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1970 client->addr << 1, client->adapter->name);
1971
257d4eae 1972 adv7511_set_isr(sd, false);
5a544cce
HV		 1973 adv7511_init_setup(sd);
1974 cancel_delayed_work(&state->edid_handler);
1975 i2c_unregister_device(state->i2c_edid);
257d4eae
HV		 1976 if (state->i2c_cec)
1977 i2c_unregister_device(state->i2c_cec);
b4dbad8f 1978 i2c_unregister_device(state->i2c_pktmem);
5a544cce
HV		 1979 destroy_workqueue(state->work_queue);
1980 v4l2_device_unregister_subdev(sd);
1981 media_entity_cleanup(&sd->entity);
1982 v4l2_ctrl_handler_free(sd->ctrl_handler);
1983 return 0;
1984}
1985
1986/* ----------------------------------------------------------------------- */
1987
1988static struct i2c_device_id adv7511_id[] = {
1989 { "adv7511", 0 },
1990 { }
1991};
1992MODULE_DEVICE_TABLE(i2c, adv7511_id);
1993
1994static struct i2c_driver adv7511_driver = {
1995 .driver = {
5a544cce
HV		 1996 .name = "adv7511",
1997 },
1998 .probe = adv7511_probe,
1999 .remove = adv7511_remove,
2000 .id_table = adv7511_id,
2001};
2002
2003module_i2c_driver(adv7511_driver);
Linux kernel - Deliverables
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