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Merge drm-fixes into drm-next.
[deliverable/linux.git] / drivers / media / i2c / adv7604.c
CommitLineData
54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
c72a53ce 30#include <linux/delay.h>
e9d50e9e 31#include <linux/gpio/consumer.h>
516613c1 32#include <linux/hdmi.h>
c72a53ce 33#include <linux/i2c.h>
54450f59
HV		 34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/slab.h>
c72a53ce 37#include <linux/v4l2-dv-timings.h>
54450f59
HV		 38#include <linux/videodev2.h>
39#include <linux/workqueue.h>
f862f57d 40#include <linux/regmap.h>
c72a53ce 41
b5dcee22 42#include <media/i2c/adv7604.h>
54450f59 43#include <media/v4l2-ctrls.h>
c72a53ce 44#include <media/v4l2-device.h>
0975626d 45#include <media/v4l2-event.h>
25764158 46#include <media/v4l2-dv-timings.h>
6fa88045 47#include <media/v4l2-of.h>
54450f59
HV		 48
49static int debug;
50module_param(debug, int, 0644);
51MODULE_PARM_DESC(debug, "debug level (0-2)");
52
53MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
54MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
55MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
56MODULE_LICENSE("GPL");
57
58/* ADV7604 system clock frequency */
b44b2e06 59#define ADV76XX_FSC (28636360)
54450f59 60
b44b2e06 61#define ADV76XX_RGB_OUT (1 << 1)
539b33b0 62
b44b2e06 63#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
539b33b0 64#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
b44b2e06 65#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
539b33b0 66
b44b2e06 67#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
539b33b0 68#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
b44b2e06 69#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
539b33b0 70#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
b44b2e06 71#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
539b33b0
LP		 72#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
73
b44b2e06
PA		 74#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
75#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
76#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
77#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
78#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
79#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
539b33b0 80
b44b2e06 81#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
539b33b0 82
b44b2e06 83enum adv76xx_type {
d42010a1
LPC		 84 ADV7604,
85 ADV7611,
8331d30b 86 ADV7612,
d42010a1
LPC		 87};
88
b44b2e06 89struct adv76xx_reg_seq {
d42010a1
LPC		 90 unsigned int reg;
91 u8 val;
92};
93
b44b2e06 94struct adv76xx_format_info {
f5fe58fd 95 u32 code;
539b33b0
LP		 96 u8 op_ch_sel;
97 bool rgb_out;
98 bool swap_cb_cr;
99 u8 op_format_sel;
100};
101
516613c1
HV		 102struct adv76xx_cfg_read_infoframe {
103 const char *desc;
104 u8 present_mask;
105 u8 head_addr;
106 u8 payload_addr;
107};
108
b44b2e06
PA		 109struct adv76xx_chip_info {
110 enum adv76xx_type type;
d42010a1
LPC		 111
112 bool has_afe;
113 unsigned int max_port;
114 unsigned int num_dv_ports;
115
116 unsigned int edid_enable_reg;
117 unsigned int edid_status_reg;
118 unsigned int lcf_reg;
119
120 unsigned int cable_det_mask;
121 unsigned int tdms_lock_mask;
122 unsigned int fmt_change_digital_mask;
80f4944e 123 unsigned int cp_csc;
d42010a1 124
b44b2e06 125 const struct adv76xx_format_info *formats;
539b33b0
LP		 126 unsigned int nformats;
127
d42010a1
LPC		 128 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
129 void (*setup_irqs)(struct v4l2_subdev *sd);
130 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
131 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
132
133 /* 0 = AFE, 1 = HDMI */
b44b2e06 134 const struct adv76xx_reg_seq *recommended_settings[2];
d42010a1
LPC		 135 unsigned int num_recommended_settings[2];
136
137 unsigned long page_mask;
5380baaf 138
139 /* Masks for timings */
140 unsigned int linewidth_mask;
141 unsigned int field0_height_mask;
142 unsigned int field1_height_mask;
143 unsigned int hfrontporch_mask;
144 unsigned int hsync_mask;
145 unsigned int hbackporch_mask;
146 unsigned int field0_vfrontporch_mask;
147 unsigned int field1_vfrontporch_mask;
148 unsigned int field0_vsync_mask;
149 unsigned int field1_vsync_mask;
150 unsigned int field0_vbackporch_mask;
151 unsigned int field1_vbackporch_mask;
d42010a1
LPC		 152};
153
54450f59
HV		 154/*
155 **********************************************************************
156 *
157 * Arrays with configuration parameters for the ADV7604
158 *
159 **********************************************************************
160 */
c784b1e2 161
b44b2e06
PA		 162struct adv76xx_state {
163 const struct adv76xx_chip_info *info;
164 struct adv76xx_platform_data pdata;
539b33b0 165
e9d50e9e
LP		 166 struct gpio_desc *hpd_gpio[4];
167
54450f59 168 struct v4l2_subdev sd;
b44b2e06 169 struct media_pad pads[ADV76XX_PAD_MAX];
c784b1e2 170 unsigned int source_pad;
539b33b0 171
54450f59 172 struct v4l2_ctrl_handler hdl;
539b33b0 173
b44b2e06 174 enum adv76xx_pad selected_input;
539b33b0 175
54450f59 176 struct v4l2_dv_timings timings;
b44b2e06 177 const struct adv76xx_format_info *format;
539b33b0 178
4a31a93a
MR		 179 struct {
180 u8 edid[256];
181 u32 present;
182 unsigned blocks;
183 } edid;
dd08beb9 184 u16 spa_port_a[2];
54450f59
HV		 185 struct v4l2_fract aspect_ratio;
186 u32 rgb_quantization_range;
187 struct workqueue_struct *work_queues;
188 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 189 bool restart_stdi_once;
54450f59
HV		 190
191 /* i2c clients */
b44b2e06 192 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
54450f59 193
f862f57d
PA		 194 /* Regmaps */
195 struct regmap *regmap[ADV76XX_PAGE_MAX];
196
54450f59
HV		 197 /* controls */
198 struct v4l2_ctrl *detect_tx_5v_ctrl;
199 struct v4l2_ctrl *analog_sampling_phase_ctrl;
200 struct v4l2_ctrl *free_run_color_manual_ctrl;
201 struct v4l2_ctrl *free_run_color_ctrl;
202 struct v4l2_ctrl *rgb_quantization_range_ctrl;
203};
204
b44b2e06 205static bool adv76xx_has_afe(struct adv76xx_state *state)
d42010a1
LPC		 206{
207 return state->info->has_afe;
208}
209
bd3e275f
JMH		 210/* Unsupported timings. This device cannot support 720p30. */
211static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
212 V4L2_DV_BT_CEA_1280X720P30,
213 { }
54450f59
HV		 214};
215
bd3e275f
JMH		 216static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
217{
218 int i;
219
220 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
221 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
222 return false;
223 return true;
224}
225
b44b2e06 226struct adv76xx_video_standards {
ccbd5bc4
HV		 227 struct v4l2_dv_timings timings;
228 u8 vid_std;
229 u8 v_freq;
230};
231
232/* sorted by number of lines */
b44b2e06 233static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
ccbd5bc4
HV		 234 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
235 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
236 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
237 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
238 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
239 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
240 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
241 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
242 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
243 /* TODO add 1920x1080P60_RB (CVT timing) */
244 { },
245};
246
247/* sorted by number of lines */
b44b2e06 248static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
ccbd5bc4
HV		 249 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
250 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
251 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
252 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
253 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
254 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
255 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
256 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
257 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
258 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
259 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
260 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
261 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
262 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
263 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
264 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
265 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
266 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
267 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
268 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
269 /* TODO add 1600X1200P60_RB (not a DMT timing) */
270 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
271 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
272 { },
273};
274
275/* sorted by number of lines */
b44b2e06 276static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
ccbd5bc4
HV		 277 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
278 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
279 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
280 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
281 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
282 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
283 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
284 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
285 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
286 { },
287};
288
289/* sorted by number of lines */
b44b2e06 290static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
ccbd5bc4
HV		 291 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
292 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
293 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
294 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
295 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
296 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
297 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
298 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
299 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
300 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
301 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
302 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
303 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
304 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
305 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
306 { },
307};
308
48519838
HV		 309static const struct v4l2_event adv76xx_ev_fmt = {
310 .type = V4L2_EVENT_SOURCE_CHANGE,
311 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
312};
313
54450f59
HV		 314/* ----------------------------------------------------------------------- */
315
b44b2e06 316static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
54450f59 317{
b44b2e06 318 return container_of(sd, struct adv76xx_state, sd);
54450f59
HV		 319}
320
54450f59
HV		 321static inline unsigned htotal(const struct v4l2_bt_timings *t)
322{
eacf8f9a 323 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 324}
325
54450f59
HV		 326static inline unsigned vtotal(const struct v4l2_bt_timings *t)
327{
eacf8f9a 328 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 329}
330
331/* ----------------------------------------------------------------------- */
332
f862f57d
PA		 333static int adv76xx_read_check(struct adv76xx_state *state,
334 int client_page, u8 reg)
54450f59 335{
f862f57d 336 struct i2c_client *client = state->i2c_clients[client_page];
54450f59 337 int err;
f862f57d 338 unsigned int val;
54450f59 339
f862f57d
PA		 340 err = regmap_read(state->regmap[client_page], reg, &val);
341
342 if (err) {
343 v4l_err(client, "error reading %02x, %02x\n",
344 client->addr, reg);
345 return err;
54450f59 346 }
f862f57d 347 return val;
54450f59
HV		 348}
349
f862f57d
PA		 350/* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
351 * size to one or more registers.
352 *
353 * A value of zero will be returned on success, a negative errno will
354 * be returned in error cases.
355 */
356static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
357 unsigned int init_reg, const void *val,
358 size_t val_len)
54450f59 359{
f862f57d
PA		 360 struct regmap *regmap = state->regmap[client_page];
361
362 if (val_len > I2C_SMBUS_BLOCK_MAX)
363 val_len = I2C_SMBUS_BLOCK_MAX;
54450f59 364
f862f57d 365 return regmap_raw_write(regmap, init_reg, val, val_len);
54450f59
HV		 366}
367
368/* ----------------------------------------------------------------------- */
369
370static inline int io_read(struct v4l2_subdev *sd, u8 reg)
371{
b44b2e06 372 struct adv76xx_state *state = to_state(sd);
54450f59 373
f862f57d 374 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
54450f59
HV		 375}
376
377static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
378{
b44b2e06 379 struct adv76xx_state *state = to_state(sd);
54450f59 380
f862f57d 381 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
54450f59
HV		 382}
383
22d97e56 384static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 385{
22d97e56 386 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
54450f59
HV		 387}
388
389static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
390{
b44b2e06 391 struct adv76xx_state *state = to_state(sd);
54450f59 392
f862f57d 393 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
54450f59
HV		 394}
395
396static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
397{
b44b2e06 398 struct adv76xx_state *state = to_state(sd);
54450f59 399
f862f57d 400 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
54450f59
HV		 401}
402
403static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
404{
b44b2e06 405 struct adv76xx_state *state = to_state(sd);
54450f59 406
f862f57d 407 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
54450f59
HV		 408}
409
410static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
411{
b44b2e06 412 struct adv76xx_state *state = to_state(sd);
54450f59 413
f862f57d 414 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
54450f59
HV		 415}
416
54450f59
HV		 417static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
418{
b44b2e06 419 struct adv76xx_state *state = to_state(sd);
54450f59 420
f862f57d 421 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
54450f59
HV		 422}
423
424static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
425{
b44b2e06 426 struct adv76xx_state *state = to_state(sd);
54450f59 427
f862f57d 428 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
54450f59
HV		 429}
430
54450f59
HV		 431static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
432{
b44b2e06 433 struct adv76xx_state *state = to_state(sd);
54450f59 434
f862f57d 435 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
54450f59
HV		 436}
437
438static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
439{
b44b2e06 440 struct adv76xx_state *state = to_state(sd);
54450f59 441
f862f57d 442 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
54450f59
HV		 443}
444
445static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
446{
b44b2e06 447 struct adv76xx_state *state = to_state(sd);
54450f59 448
f862f57d 449 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
54450f59
HV		 450}
451
452static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
453{
b44b2e06 454 struct adv76xx_state *state = to_state(sd);
54450f59 455
f862f57d 456 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
54450f59
HV		 457}
458
22d97e56 459static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 460{
22d97e56 461 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
54450f59
HV		 462}
463
464static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
465{
b44b2e06 466 struct adv76xx_state *state = to_state(sd);
54450f59 467
f862f57d 468 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
54450f59
HV		 469}
470
471static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
472{
b44b2e06 473 struct adv76xx_state *state = to_state(sd);
54450f59 474
f862f57d 475 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
54450f59
HV		 476}
477
54450f59 478static inline int edid_write_block(struct v4l2_subdev *sd,
f862f57d 479 unsigned int total_len, const u8 *val)
54450f59 480{
b44b2e06 481 struct adv76xx_state *state = to_state(sd);
54450f59 482 int err = 0;
f862f57d
PA		 483 int i = 0;
484 int len = 0;
54450f59 485
f862f57d
PA		 486 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
487 __func__, total_len);
488
489 while (!err && i < total_len) {
490 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
491 I2C_SMBUS_BLOCK_MAX :
492 (total_len - i);
493
494 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
495 i, val + i, len);
496 i += len;
497 }
54450f59 498
dd08beb9
MR		 499 return err;
500}
54450f59 501
b44b2e06 502static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
e9d50e9e
LP		 503{
504 unsigned int i;
505
269bd132 506 for (i = 0; i < state->info->num_dv_ports; ++i)
e9d50e9e 507 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
e9d50e9e 508
b44b2e06 509 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
e9d50e9e
LP		 510}
511
b44b2e06 512static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
dd08beb9
MR		 513{
514 struct delayed_work *dwork = to_delayed_work(work);
b44b2e06 515 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
dd08beb9
MR		 516 delayed_work_enable_hotplug);
517 struct v4l2_subdev *sd = &state->sd;
54450f59 518
dd08beb9 519 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 520
b44b2e06 521 adv76xx_set_hpd(state, state->edid.present);
54450f59
HV		 522}
523
524static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
525{
b44b2e06 526 struct adv76xx_state *state = to_state(sd);
54450f59 527
f862f57d 528 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
54450f59
HV		 529}
530
51182a94
LP		 531static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
532{
533 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
534}
535
54450f59
HV		 536static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
537{
b44b2e06 538 struct adv76xx_state *state = to_state(sd);
54450f59 539
f862f57d 540 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
54450f59
HV		 541}
542
22d97e56 543static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
4a31a93a 544{
22d97e56 545 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
4a31a93a
MR		 546}
547
54450f59
HV		 548static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
549{
b44b2e06 550 struct adv76xx_state *state = to_state(sd);
54450f59 551
f862f57d 552 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
54450f59
HV		 553}
554
555static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
556{
b44b2e06 557 struct adv76xx_state *state = to_state(sd);
54450f59 558
f862f57d 559 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
54450f59
HV		 560}
561
51182a94
LP		 562static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
563{
564 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
565}
566
54450f59
HV		 567static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
568{
b44b2e06 569 struct adv76xx_state *state = to_state(sd);
54450f59 570
f862f57d 571 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
54450f59
HV		 572}
573
22d97e56 574static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 575{
22d97e56 576 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
54450f59
HV		 577}
578
579static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
580{
b44b2e06 581 struct adv76xx_state *state = to_state(sd);
54450f59 582
f862f57d 583 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
54450f59
HV		 584}
585
586static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
587{
b44b2e06 588 struct adv76xx_state *state = to_state(sd);
54450f59 589
f862f57d 590 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
05cacb17 591}
d42010a1 592
b44b2e06
PA		 593#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
594#define ADV76XX_REG_SEQ_TERM 0xffff
d42010a1
LPC		 595
596#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 597static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
d42010a1 598{
b44b2e06 599 struct adv76xx_state *state = to_state(sd);
d42010a1 600 unsigned int page = reg >> 8;
f862f57d
PA		 601 unsigned int val;
602 int err;
d42010a1
LPC		 603
604 if (!(BIT(page) & state->info->page_mask))
605 return -EINVAL;
606
607 reg &= 0xff;
f862f57d 608 err = regmap_read(state->regmap[page], reg, &val);
d42010a1 609
f862f57d 610 return err ? err : val;
d42010a1
LPC		 611}
612#endif
613
b44b2e06 614static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
d42010a1 615{
b44b2e06 616 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 617 unsigned int page = reg >> 8;
618
619 if (!(BIT(page) & state->info->page_mask))
620 return -EINVAL;
621
622 reg &= 0xff;
623
f862f57d 624 return regmap_write(state->regmap[page], reg, val);
d42010a1
LPC		 625}
626
b44b2e06
PA		 627static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
628 const struct adv76xx_reg_seq *reg_seq)
d42010a1
LPC		 629{
630 unsigned int i;
631
b44b2e06
PA		 632 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
633 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
d42010a1
LPC		 634}
635
539b33b0
LP		 636/* -----------------------------------------------------------------------------
637 * Format helpers
638 */
639
b44b2e06
PA		 640static const struct adv76xx_format_info adv7604_formats[] = {
641 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
642 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
643 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
644 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
645 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
646 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
647 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
648 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
649 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
650 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
651 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
652 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
653 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
654 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
655 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
656 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
657 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
658 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
659 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
660 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
661 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
662 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
663 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
664 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
665 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
666 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
667 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
668 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
669 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
670 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
671 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
672 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
673 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
674 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
675 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
676 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
677 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
678 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 679};
680
b44b2e06
PA		 681static const struct adv76xx_format_info adv7611_formats[] = {
682 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
683 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
684 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
685 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
686 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
687 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
688 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
689 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
690 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
691 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
692 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
693 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
694 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
695 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
696 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
697 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
698 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
699 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
700 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
701 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
702 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
703 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
704 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
705 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
706 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
707 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 708};
709
8331d30b
WT		 710static const struct adv76xx_format_info adv7612_formats[] = {
711 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
712 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
713 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
714 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
715 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
716 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
717 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
718 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
719 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
720 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
721 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
722 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
723 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
724 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
725};
726
b44b2e06
PA		 727static const struct adv76xx_format_info *
728adv76xx_format_info(struct adv76xx_state *state, u32 code)
539b33b0
LP		 729{
730 unsigned int i;
731
732 for (i = 0; i < state->info->nformats; ++i) {
733 if (state->info->formats[i].code == code)
734 return &state->info->formats[i];
735 }
736
737 return NULL;
738}
739
54450f59
HV		 740/* ----------------------------------------------------------------------- */
741
4a31a93a
MR		 742static inline bool is_analog_input(struct v4l2_subdev *sd)
743{
b44b2e06 744 struct adv76xx_state *state = to_state(sd);
4a31a93a 745
c784b1e2
LP		 746 return state->selected_input == ADV7604_PAD_VGA_RGB ||
747 state->selected_input == ADV7604_PAD_VGA_COMP;
4a31a93a
MR		 748}
749
750static inline bool is_digital_input(struct v4l2_subdev *sd)
751{
b44b2e06 752 struct adv76xx_state *state = to_state(sd);
4a31a93a 753
b44b2e06 754 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
c784b1e2
LP		 755 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
756 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
757 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
4a31a93a
MR		 758}
759
bd3e275f
JMH		 760static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
761 .type = V4L2_DV_BT_656_1120,
762 /* keep this initialization for compatibility with GCC < 4.4.6 */
763 .reserved = { 0 },
764 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
765 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
766 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
767 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
768 V4L2_DV_BT_CAP_CUSTOM)
769};
770
771static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
772 .type = V4L2_DV_BT_656_1120,
773 /* keep this initialization for compatibility with GCC < 4.4.6 */
774 .reserved = { 0 },
775 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
776 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
777 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
778 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
779 V4L2_DV_BT_CAP_CUSTOM)
780};
781
782static inline const struct v4l2_dv_timings_cap *
783adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd)
784{
785 return is_digital_input(sd) ? &adv76xx_timings_cap_digital :
786 &adv7604_timings_cap_analog;
787}
788
789
4a31a93a
MR		 790/* ----------------------------------------------------------------------- */
791
54450f59 792#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 793static void adv76xx_inv_register(struct v4l2_subdev *sd)
54450f59
HV		 794{
795 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
796 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
797 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
798 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
799 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
800 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
801 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
802 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
803 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
804 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
805 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
806 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
807 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
808}
809
b44b2e06 810static int adv76xx_g_register(struct v4l2_subdev *sd,
54450f59
HV		 811 struct v4l2_dbg_register *reg)
812{
d42010a1
LPC		 813 int ret;
814
b44b2e06 815 ret = adv76xx_read_reg(sd, reg->reg);
d42010a1 816 if (ret < 0) {
54450f59 817 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 818 adv76xx_inv_register(sd);
d42010a1 819 return ret;
54450f59 820 }
d42010a1
LPC		 821
822 reg->size = 1;
823 reg->val = ret;
824
54450f59
HV		 825 return 0;
826}
827
b44b2e06 828static int adv76xx_s_register(struct v4l2_subdev *sd,
977ba3b1 829 const struct v4l2_dbg_register *reg)
54450f59 830{
d42010a1 831 int ret;
1577461b 832
b44b2e06 833 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
d42010a1 834 if (ret < 0) {
54450f59 835 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 836 adv76xx_inv_register(sd);
d42010a1 837 return ret;
54450f59 838 }
d42010a1 839
54450f59
HV		 840 return 0;
841}
842#endif
843
d42010a1
LPC		 844static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
845{
846 u8 value = io_read(sd, 0x6f);
847
848 return ((value & 0x10) >> 4)
849 | ((value & 0x08) >> 2)
850 | ((value & 0x04) << 0)
851 | ((value & 0x02) << 2);
852}
853
854static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
855{
856 u8 value = io_read(sd, 0x6f);
857
858 return value & 1;
859}
860
7111cddd
WT		 861static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
862{
863 /* Reads CABLE_DET_A_RAW. For input B support, need to
864 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
865 */
866 u8 value = io_read(sd, 0x6f);
867
868 return value & 1;
869}
870
b44b2e06 871static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
54450f59 872{
b44b2e06
PA		 873 struct adv76xx_state *state = to_state(sd);
874 const struct adv76xx_chip_info *info = state->info;
54450f59 875
54450f59 876 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
d42010a1 877 info->read_cable_det(sd));
54450f59
HV		 878}
879
ccbd5bc4
HV		 880static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
881 u8 prim_mode,
b44b2e06 882 const struct adv76xx_video_standards *predef_vid_timings,
ccbd5bc4
HV		 883 const struct v4l2_dv_timings *timings)
884{
ccbd5bc4
HV		 885 int i;
886
887 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 888 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
85f9e06c 889 is_digital_input(sd) ? 250000 : 1000000, false))
ccbd5bc4
HV		 890 continue;
891 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
892 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
893 prim_mode); /* v_freq and prim mode */
894 return 0;
895 }
896
897 return -1;
898}
899
900static int configure_predefined_video_timings(struct v4l2_subdev *sd,
901 struct v4l2_dv_timings *timings)
54450f59 902{
b44b2e06 903 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 904 int err;
905
906 v4l2_dbg(1, debug, sd, "%s", __func__);
907
b44b2e06 908 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 909 /* reset to default values */
910 io_write(sd, 0x16, 0x43);
911 io_write(sd, 0x17, 0x5a);
912 }
ccbd5bc4 913 /* disable embedded syncs for auto graphics mode */
22d97e56 914 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
ccbd5bc4
HV		 915 cp_write(sd, 0x8f, 0x00);
916 cp_write(sd, 0x90, 0x00);
917 cp_write(sd, 0xa2, 0x00);
918 cp_write(sd, 0xa3, 0x00);
919 cp_write(sd, 0xa4, 0x00);
920 cp_write(sd, 0xa5, 0x00);
921 cp_write(sd, 0xa6, 0x00);
922 cp_write(sd, 0xa7, 0x00);
923 cp_write(sd, 0xab, 0x00);
924 cp_write(sd, 0xac, 0x00);
925
4a31a93a 926 if (is_analog_input(sd)) {
ccbd5bc4
HV		 927 err = find_and_set_predefined_video_timings(sd,
928 0x01, adv7604_prim_mode_comp, timings);
929 if (err)
930 err = find_and_set_predefined_video_timings(sd,
931 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 932 } else if (is_digital_input(sd)) {
ccbd5bc4 933 err = find_and_set_predefined_video_timings(sd,
b44b2e06 934 0x05, adv76xx_prim_mode_hdmi_comp, timings);
ccbd5bc4
HV		 935 if (err)
936 err = find_and_set_predefined_video_timings(sd,
b44b2e06 937 0x06, adv76xx_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 938 } else {
939 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
940 __func__, state->selected_input);
ccbd5bc4 941 err = -1;
ccbd5bc4
HV		 942 }
943
944
945 return err;
946}
947
948static void configure_custom_video_timings(struct v4l2_subdev *sd,
949 const struct v4l2_bt_timings *bt)
950{
b44b2e06 951 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 952 u32 width = htotal(bt);
953 u32 height = vtotal(bt);
954 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
955 u16 cp_start_eav = width - bt->hfrontporch;
956 u16 cp_start_vbi = height - bt->vfrontporch;
957 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
958 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
b44b2e06 959 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
ccbd5bc4
HV		 960 const u8 pll[2] = {
961 0xc0 | ((width >> 8) & 0x1f),
962 width & 0xff
963 };
54450f59
HV		 964
965 v4l2_dbg(2, debug, sd, "%s\n", __func__);
966
4a31a93a 967 if (is_analog_input(sd)) {
ccbd5bc4
HV		 968 /* auto graphics */
969 io_write(sd, 0x00, 0x07); /* video std */
970 io_write(sd, 0x01, 0x02); /* prim mode */
971 /* enable embedded syncs for auto graphics mode */
22d97e56 972 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
54450f59 973
ccbd5bc4 974 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 975 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
976 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
f862f57d
PA		 977 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
978 0x16, pll, 2))
54450f59 979 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 980
981 /* active video - horizontal timing */
54450f59 982 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 983 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 984 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 985 cp_write(sd, 0xa4, cp_start_eav & 0xff);
986
987 /* active video - vertical timing */
54450f59 988 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 989 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 990 ((cp_end_vbi >> 8) & 0xf));
54450f59 991 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 992 } else if (is_digital_input(sd)) {
ccbd5bc4 993 /* set default prim_mode/vid_std for HDMI
39c1cb2b 994 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 995 io_write(sd, 0x00, 0x02); /* video std */
996 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 997 } else {
998 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
999 __func__, state->selected_input);
54450f59 1000 }
54450f59 1001
ccbd5bc4
HV		 1002 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1003 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1004 cp_write(sd, 0xab, (height >> 4) & 0xff);
1005 cp_write(sd, 0xac, (height & 0x0f) << 4);
1006}
54450f59 1007
b44b2e06 1008static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
5c6c6349 1009{
b44b2e06 1010 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1011 u8 offset_buf[4];
1012
1013 if (auto_offset) {
1014 offset_a = 0x3ff;
1015 offset_b = 0x3ff;
1016 offset_c = 0x3ff;
1017 }
1018
1019 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1020 __func__, auto_offset ? "Auto" : "Manual",
1021 offset_a, offset_b, offset_c);
1022
1023 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1024 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1025 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1026 offset_buf[3] = offset_c & 0x0ff;
1027
1028 /* Registers must be written in this order with no i2c access in between */
f862f57d
PA		 1029 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1030 0x77, offset_buf, 4))
5c6c6349
MR		 1031 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1032}
1033
b44b2e06 1034static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
5c6c6349 1035{
b44b2e06 1036 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1037 u8 gain_buf[4];
1038 u8 gain_man = 1;
1039 u8 agc_mode_man = 1;
1040
1041 if (auto_gain) {
1042 gain_man = 0;
1043 agc_mode_man = 0;
1044 gain_a = 0x100;
1045 gain_b = 0x100;
1046 gain_c = 0x100;
1047 }
1048
1049 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1050 __func__, auto_gain ? "Auto" : "Manual",
1051 gain_a, gain_b, gain_c);
1052
1053 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1054 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1055 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1056 gain_buf[3] = ((gain_c & 0x0ff));
1057
1058 /* Registers must be written in this order with no i2c access in between */
f862f57d
PA		 1059 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1060 0x73, gain_buf, 4))
5c6c6349
MR		 1061 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1062}
1063
54450f59
HV		 1064static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1065{
b44b2e06 1066 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1067 bool rgb_output = io_read(sd, 0x02) & 0x02;
1068 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1069
1070 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1071 __func__, state->rgb_quantization_range,
1072 rgb_output, hdmi_signal);
54450f59 1073
b44b2e06
PA		 1074 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1075 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
9833239e 1076
54450f59
HV		 1077 switch (state->rgb_quantization_range) {
1078 case V4L2_DV_RGB_RANGE_AUTO:
c784b1e2 1079 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
9833239e
MR		 1080 /* Receiving analog RGB signal
1081 * Set RGB full range (0-255) */
22d97e56 1082 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
9833239e
MR		 1083 break;
1084 }
1085
c784b1e2 1086 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
9833239e
MR		 1087 /* Receiving analog YPbPr signal
1088 * Set automode */
22d97e56 1089 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1090 break;
1091 }
1092
5c6c6349 1093 if (hdmi_signal) {
9833239e
MR		 1094 /* Receiving HDMI signal
1095 * Set automode */
22d97e56 1096 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1097 break;
1098 }
1099
1100 /* Receiving DVI-D signal
1101 * ADV7604 selects RGB limited range regardless of
1102 * input format (CE/IT) in automatic mode */
680fee04 1103 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
9833239e 1104 /* RGB limited range (16-235) */
22d97e56 1105 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
9833239e
MR		 1106 } else {
1107 /* RGB full range (0-255) */
22d97e56 1108 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1109
1110 if (is_digital_input(sd) && rgb_output) {
b44b2e06 1111 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
5c6c6349 1112 } else {
b44b2e06
PA		 1113 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1114 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
5c6c6349 1115 }
54450f59
HV		 1116 }
1117 break;
1118 case V4L2_DV_RGB_RANGE_LIMITED:
c784b1e2 1119 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1120 /* YCrCb limited range (16-235) */
22d97e56 1121 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
5c6c6349 1122 break;
d261e842 1123 }
5c6c6349
MR		 1124
1125 /* RGB limited range (16-235) */
22d97e56 1126 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
5c6c6349 1127
54450f59
HV		 1128 break;
1129 case V4L2_DV_RGB_RANGE_FULL:
c784b1e2 1130 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1131 /* YCrCb full range (0-255) */
22d97e56 1132 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
5c6c6349
MR		 1133 break;
1134 }
1135
1136 /* RGB full range (0-255) */
22d97e56 1137 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1138
1139 if (is_analog_input(sd) || hdmi_signal)
1140 break;
1141
1142 /* Adjust gain/offset for DVI-D signals only */
1143 if (rgb_output) {
b44b2e06 1144 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
d261e842 1145 } else {
b44b2e06
PA		 1146 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1147 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
d261e842 1148 }
54450f59
HV		 1149 break;
1150 }
1151}
1152
b44b2e06 1153static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
54450f59 1154{
c269887c 1155 struct v4l2_subdev *sd =
b44b2e06 1156 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
c269887c 1157
b44b2e06 1158 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1159
1160 switch (ctrl->id) {
1161 case V4L2_CID_BRIGHTNESS:
1162 cp_write(sd, 0x3c, ctrl->val);
1163 return 0;
1164 case V4L2_CID_CONTRAST:
1165 cp_write(sd, 0x3a, ctrl->val);
1166 return 0;
1167 case V4L2_CID_SATURATION:
1168 cp_write(sd, 0x3b, ctrl->val);
1169 return 0;
1170 case V4L2_CID_HUE:
1171 cp_write(sd, 0x3d, ctrl->val);
1172 return 0;
1173 case V4L2_CID_DV_RX_RGB_RANGE:
1174 state->rgb_quantization_range = ctrl->val;
1175 set_rgb_quantization_range(sd);
1176 return 0;
1177 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
b44b2e06 1178 if (!adv76xx_has_afe(state))
d42010a1 1179 return -EINVAL;
54450f59
HV		 1180 /* Set the analog sampling phase. This is needed to find the
1181 best sampling phase for analog video: an application or
1182 driver has to try a number of phases and analyze the picture
1183 quality before settling on the best performing phase. */
1184 afe_write(sd, 0xc8, ctrl->val);
1185 return 0;
1186 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1187 /* Use the default blue color for free running mode,
1188 or supply your own. */
22d97e56 1189 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
54450f59
HV		 1190 return 0;
1191 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1192 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1193 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1194 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1195 return 0;
1196 }
1197 return -EINVAL;
1198}
1199
297a4144
HV		 1200static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1201{
1202 struct v4l2_subdev *sd =
1203 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1204
1205 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1206 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1207 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1208 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1209 return 0;
1210 }
1211 return -EINVAL;
1212}
1213
54450f59
HV		 1214/* ----------------------------------------------------------------------- */
1215
1216static inline bool no_power(struct v4l2_subdev *sd)
1217{
1218 /* Entire chip or CP powered off */
1219 return io_read(sd, 0x0c) & 0x24;
1220}
1221
1222static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1223{
b44b2e06 1224 struct adv76xx_state *state = to_state(sd);
4a31a93a
MR		 1225
1226 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1227}
1228
1229static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1230{
b44b2e06
PA		 1231 struct adv76xx_state *state = to_state(sd);
1232 const struct adv76xx_chip_info *info = state->info;
d42010a1
LPC		 1233
1234 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
54450f59
HV		 1235}
1236
bb88f325
MB		 1237static inline bool is_hdmi(struct v4l2_subdev *sd)
1238{
1239 return hdmi_read(sd, 0x05) & 0x80;
1240}
1241
54450f59
HV		 1242static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1243{
b44b2e06 1244 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 1245
1246 /*
1247 * Chips without a AFE don't expose registers for the SSPD, so just assume
1248 * that we have a lock.
1249 */
b44b2e06 1250 if (adv76xx_has_afe(state))
d42010a1
LPC		 1251 return false;
1252
54450f59
HV		 1253 /* TODO channel 2 */
1254 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1255}
1256
1257static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1258{
1259 /* TODO channel 2 */
1260 return !(cp_read(sd, 0xb1) & 0x80);
1261}
1262
1263static inline bool no_signal(struct v4l2_subdev *sd)
1264{
54450f59
HV		 1265 bool ret;
1266
1267 ret = no_power(sd);
1268
1269 ret |= no_lock_stdi(sd);
1270 ret |= no_lock_sspd(sd);
1271
4a31a93a 1272 if (is_digital_input(sd)) {
54450f59
HV		 1273 ret |= no_lock_tmds(sd);
1274 ret |= no_signal_tmds(sd);
1275 }
1276
1277 return ret;
1278}
1279
1280static inline bool no_lock_cp(struct v4l2_subdev *sd)
1281{
b44b2e06 1282 struct adv76xx_state *state = to_state(sd);
d42010a1 1283
b44b2e06 1284 if (!adv76xx_has_afe(state))
d42010a1
LPC		 1285 return false;
1286
54450f59
HV		 1287 /* CP has detected a non standard number of lines on the incoming
1288 video compared to what it is configured to receive by s_dv_timings */
1289 return io_read(sd, 0x12) & 0x01;
1290}
1291
58514625 1292static inline bool in_free_run(struct v4l2_subdev *sd)
1293{
1294 return cp_read(sd, 0xff) & 0x10;
1295}
1296
b44b2e06 1297static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
54450f59 1298{
54450f59
HV		 1299 *status = 0;
1300 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1301 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
58514625 1302 if (!in_free_run(sd) && no_lock_cp(sd))
1303 *status |= is_digital_input(sd) ?
1304 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1305
1306 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1307
1308 return 0;
1309}
1310
1311/* ----------------------------------------------------------------------- */
1312
54450f59
HV		 1313struct stdi_readback {
1314 u16 bl, lcf, lcvs;
1315 u8 hs_pol, vs_pol;
1316 bool interlaced;
1317};
1318
1319static int stdi2dv_timings(struct v4l2_subdev *sd,
1320 struct stdi_readback *stdi,
1321 struct v4l2_dv_timings *timings)
1322{
b44b2e06
PA		 1323 struct adv76xx_state *state = to_state(sd);
1324 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
54450f59
HV		 1325 u32 pix_clk;
1326 int i;
1327
bd3e275f
JMH		 1328 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1329 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1330
1331 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1332 adv76xx_get_dv_timings_cap(sd),
1333 adv76xx_check_dv_timings, NULL))
54450f59 1334 continue;
bd3e275f
JMH		 1335 if (vtotal(bt) != stdi->lcf + 1)
1336 continue;
1337 if (bt->vsync != stdi->lcvs)
54450f59
HV		 1338 continue;
1339
bd3e275f 1340 pix_clk = hfreq * htotal(bt);
54450f59 1341
bd3e275f
JMH		 1342 if ((pix_clk < bt->pixelclock + 1000000) &&
1343 (pix_clk > bt->pixelclock - 1000000)) {
1344 *timings = v4l2_dv_timings_presets[i];
54450f59
HV		 1345 return 0;
1346 }
1347 }
1348
5fea1bb7 1349 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
54450f59
HV		 1350 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1351 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1352 false, timings))
54450f59
HV		 1353 return 0;
1354 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1355 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1356 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1357 false, state->aspect_ratio, timings))
54450f59
HV		 1358 return 0;
1359
ccbd5bc4
HV		 1360 v4l2_dbg(2, debug, sd,
1361 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1362 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1363 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1364 return -1;
1365}
1366
d42010a1 1367
54450f59
HV		 1368static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1369{
b44b2e06
PA		 1370 struct adv76xx_state *state = to_state(sd);
1371 const struct adv76xx_chip_info *info = state->info;
4a2ccdd2
LP		 1372 u8 polarity;
1373
54450f59
HV		 1374 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1375 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1376 return -1;
1377 }
1378
1379 /* read STDI */
51182a94 1380 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
d42010a1 1381 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
54450f59
HV		 1382 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1383 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1384
b44b2e06 1385 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1386 /* read SSPD */
1387 polarity = cp_read(sd, 0xb5);
1388 if ((polarity & 0x03) == 0x01) {
1389 stdi->hs_pol = polarity & 0x10
1390 ? (polarity & 0x08 ? '+' : '-') : 'x';
1391 stdi->vs_pol = polarity & 0x40
1392 ? (polarity & 0x20 ? '+' : '-') : 'x';
1393 } else {
1394 stdi->hs_pol = 'x';
1395 stdi->vs_pol = 'x';
1396 }
54450f59 1397 } else {
d42010a1
LPC		 1398 polarity = hdmi_read(sd, 0x05);
1399 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1400 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
54450f59
HV		 1401 }
1402
1403 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1404 v4l2_dbg(2, debug, sd,
1405 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1406 return -1;
1407 }
1408
1409 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1410 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1411 memset(stdi, 0, sizeof(struct stdi_readback));
1412 return -1;
1413 }
1414
1415 v4l2_dbg(2, debug, sd,
1416 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1417 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1418 stdi->hs_pol, stdi->vs_pol,
1419 stdi->interlaced ? "interlaced" : "progressive");
1420
1421 return 0;
1422}
1423
b44b2e06 1424static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1425 struct v4l2_enum_dv_timings *timings)
1426{
b44b2e06 1427 struct adv76xx_state *state = to_state(sd);
afec5599 1428
afec5599
LP		 1429 if (timings->pad >= state->source_pad)
1430 return -EINVAL;
1431
bd3e275f
JMH		 1432 return v4l2_enum_dv_timings_cap(timings,
1433 adv76xx_get_dv_timings_cap(sd), adv76xx_check_dv_timings, NULL);
54450f59
HV		 1434}
1435
b44b2e06 1436static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
7515e096 1437 struct v4l2_dv_timings_cap *cap)
54450f59 1438{
b44b2e06 1439 struct adv76xx_state *state = to_state(sd);
7515e096
LP		 1440
1441 if (cap->pad >= state->source_pad)
1442 return -EINVAL;
1443
bd3e275f 1444 *cap = *adv76xx_get_dv_timings_cap(sd);
54450f59
HV		 1445 return 0;
1446}
1447
1448/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
b44b2e06
PA		 1449 if the format is listed in adv76xx_timings[] */
1450static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
54450f59
HV		 1451 struct v4l2_dv_timings *timings)
1452{
bd3e275f
JMH		 1453 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd),
1454 is_digital_input(sd) ? 250000 : 1000000,
1455 adv76xx_check_dv_timings, NULL);
54450f59
HV		 1456}
1457
d42010a1
LPC		 1458static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1459{
1460 unsigned int freq;
1461 int a, b;
1462
1463 a = hdmi_read(sd, 0x06);
1464 b = hdmi_read(sd, 0x3b);
1465 if (a < 0 || b < 0)
1466 return 0;
1467 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1468
1469 if (is_hdmi(sd)) {
1470 /* adjust for deep color mode */
1471 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1472
1473 freq = freq * 8 / bits_per_channel;
1474 }
1475
1476 return freq;
1477}
1478
1479static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1480{
1481 int a, b;
1482
1483 a = hdmi_read(sd, 0x51);
1484 b = hdmi_read(sd, 0x52);
1485 if (a < 0 || b < 0)
1486 return 0;
1487 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1488}
1489
b44b2e06 1490static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1491 struct v4l2_dv_timings *timings)
1492{
b44b2e06
PA		 1493 struct adv76xx_state *state = to_state(sd);
1494 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 1495 struct v4l2_bt_timings *bt = &timings->bt;
1496 struct stdi_readback stdi;
1497
1498 if (!timings)
1499 return -EINVAL;
1500
1501 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1502
1503 if (no_signal(sd)) {
1e0b9156 1504 state->restart_stdi_once = true;
54450f59
HV		 1505 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1506 return -ENOLINK;
1507 }
1508
1509 /* read STDI */
1510 if (read_stdi(sd, &stdi)) {
1511 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1512 return -ENOLINK;
1513 }
1514 bt->interlaced = stdi.interlaced ?
1515 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1516
4a31a93a 1517 if (is_digital_input(sd)) {
54450f59
HV		 1518 timings->type = V4L2_DV_BT_656_1120;
1519
5380baaf 1520 bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask);
1521 bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask);
d42010a1 1522 bt->pixelclock = info->read_hdmi_pixelclock(sd);
5380baaf 1523 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1524 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1525 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1526 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1527 info->field0_vfrontporch_mask) / 2;
1528 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1529 bt->vbackporch = hdmi_read16(sd, 0x32,
1530 info->field0_vbackporch_mask) / 2;
54450f59
HV		 1531 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1532 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1533 if (bt->interlaced == V4L2_DV_INTERLACED) {
5380baaf 1534 bt->height += hdmi_read16(sd, 0x0b,
1535 info->field1_height_mask);
1536 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1537 info->field1_vfrontporch_mask) / 2;
1538 bt->il_vsync = hdmi_read16(sd, 0x30,
1539 info->field1_vsync_mask) / 2;
1540 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1541 info->field1_vbackporch_mask) / 2;
54450f59 1542 }
b44b2e06 1543 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1544 } else {
1545 /* find format
80939647 1546 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1547 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1548 */
1549 if (!stdi2dv_timings(sd, &stdi, timings))
1550 goto found;
1551 stdi.lcvs += 1;
1552 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1553 if (!stdi2dv_timings(sd, &stdi, timings))
1554 goto found;
1555 stdi.lcvs -= 2;
1556 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1557 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1558 /*
1559 * The STDI block may measure wrong values, especially
1560 * for lcvs and lcf. If the driver can not find any
1561 * valid timing, the STDI block is restarted to measure
1562 * the video timings again. The function will return an
1563 * error, but the restart of STDI will generate a new
1564 * STDI interrupt and the format detection process will
1565 * restart.
1566 */
1567 if (state->restart_stdi_once) {
1568 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1569 /* TODO restart STDI for Sync Channel 2 */
1570 /* enter one-shot mode */
22d97e56 1571 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
cf9afb1d 1572 /* trigger STDI restart */
22d97e56 1573 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
cf9afb1d 1574 /* reset to continuous mode */
22d97e56 1575 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
cf9afb1d
HV		 1576 state->restart_stdi_once = false;
1577 return -ENOLINK;
1578 }
54450f59
HV		 1579 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1580 return -ERANGE;
1581 }
cf9afb1d 1582 state->restart_stdi_once = true;
54450f59
HV		 1583 }
1584found:
1585
1586 if (no_signal(sd)) {
1587 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1588 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1589 return -ENOLINK;
1590 }
1591
4a31a93a
MR		 1592 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1593 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1594 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1595 __func__, (u32)bt->pixelclock);
1596 return -ERANGE;
1597 }
1598
1599 if (debug > 1)
b44b2e06 1600 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
11d034c8 1601 timings, true);
54450f59
HV		 1602
1603 return 0;
1604}
1605
b44b2e06 1606static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1607 struct v4l2_dv_timings *timings)
1608{
b44b2e06 1609 struct adv76xx_state *state = to_state(sd);
54450f59 1610 struct v4l2_bt_timings *bt;
ccbd5bc4 1611 int err;
54450f59
HV		 1612
1613 if (!timings)
1614 return -EINVAL;
1615
85f9e06c 1616 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
d48eb48c
MR		 1617 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1618 return 0;
1619 }
1620
54450f59
HV		 1621 bt = &timings->bt;
1622
bd3e275f
JMH		 1623 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd),
1624 adv76xx_check_dv_timings, NULL))
54450f59 1625 return -ERANGE;
ccbd5bc4 1626
b44b2e06 1627 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1628
1629 state->timings = *timings;
1630
22d97e56 1631 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
ccbd5bc4
HV		 1632
1633 /* Use prim_mode and vid_std when available */
1634 err = configure_predefined_video_timings(sd, timings);
1635 if (err) {
1636 /* custom settings when the video format
1637 does not have prim_mode/vid_std */
1638 configure_custom_video_timings(sd, bt);
1639 }
54450f59
HV		 1640
1641 set_rgb_quantization_range(sd);
1642
54450f59 1643 if (debug > 1)
b44b2e06 1644 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
11d034c8 1645 timings, true);
54450f59
HV		 1646 return 0;
1647}
1648
b44b2e06 1649static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1650 struct v4l2_dv_timings *timings)
1651{
b44b2e06 1652 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1653
1654 *timings = state->timings;
1655 return 0;
1656}
1657
d42010a1
LPC		 1658static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1659{
1660 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1661}
1662
1663static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1664{
1665 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1666}
1667
6b0d5d34 1668static void enable_input(struct v4l2_subdev *sd)
54450f59 1669{
b44b2e06 1670 struct adv76xx_state *state = to_state(sd);
6b0d5d34 1671
4a31a93a 1672 if (is_analog_input(sd)) {
54450f59 1673 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1674 } else if (is_digital_input(sd)) {
22d97e56 1675 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
d42010a1 1676 state->info->set_termination(sd, true);
54450f59 1677 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
22d97e56 1678 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
4a31a93a
MR		 1679 } else {
1680 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1681 __func__, state->selected_input);
54450f59
HV		 1682 }
1683}
1684
1685static void disable_input(struct v4l2_subdev *sd)
1686{
b44b2e06 1687 struct adv76xx_state *state = to_state(sd);
d42010a1 1688
22d97e56 1689 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
5474b983 1690 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1691 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
d42010a1 1692 state->info->set_termination(sd, false);
54450f59
HV		 1693}
1694
6b0d5d34 1695static void select_input(struct v4l2_subdev *sd)
54450f59 1696{
b44b2e06
PA		 1697 struct adv76xx_state *state = to_state(sd);
1698 const struct adv76xx_chip_info *info = state->info;
54450f59 1699
4a31a93a 1700 if (is_analog_input(sd)) {
b44b2e06 1701 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
54450f59
HV		 1702
1703 afe_write(sd, 0x00, 0x08); /* power up ADC */
1704 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1705 afe_write(sd, 0xc8, 0x00); /* phase control */
4a31a93a
MR		 1706 } else if (is_digital_input(sd)) {
1707 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1708
b44b2e06 1709 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
d42010a1 1710
b44b2e06 1711 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1712 afe_write(sd, 0x00, 0xff); /* power down ADC */
1713 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1714 afe_write(sd, 0xc8, 0x40); /* phase control */
1715 }
1716
54450f59
HV		 1717 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1718 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1719 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1720 } else {
1721 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1722 __func__, state->selected_input);
54450f59
HV		 1723 }
1724}
1725
b44b2e06 1726static int adv76xx_s_routing(struct v4l2_subdev *sd,
54450f59
HV		 1727 u32 input, u32 output, u32 config)
1728{
b44b2e06 1729 struct adv76xx_state *state = to_state(sd);
54450f59 1730
ff4f80fd
MR		 1731 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1732 __func__, input, state->selected_input);
1733
1734 if (input == state->selected_input)
1735 return 0;
54450f59 1736
d42010a1
LPC		 1737 if (input > state->info->max_port)
1738 return -EINVAL;
1739
4a31a93a 1740 state->selected_input = input;
54450f59
HV		 1741
1742 disable_input(sd);
6b0d5d34 1743 select_input(sd);
6b0d5d34 1744 enable_input(sd);
54450f59 1745
6f5bcfc3
LPC		 1746 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1747
54450f59
HV		 1748 return 0;
1749}
1750
b44b2e06 1751static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 1752 struct v4l2_subdev_pad_config *cfg,
539b33b0 1753 struct v4l2_subdev_mbus_code_enum *code)
54450f59 1754{
b44b2e06 1755 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1756
1757 if (code->index >= state->info->nformats)
54450f59 1758 return -EINVAL;
539b33b0
LP		 1759
1760 code->code = state->info->formats[code->index].code;
1761
54450f59
HV		 1762 return 0;
1763}
1764
b44b2e06 1765static void adv76xx_fill_format(struct adv76xx_state *state,
539b33b0 1766 struct v4l2_mbus_framefmt *format)
54450f59 1767{
539b33b0 1768 memset(format, 0, sizeof(*format));
54450f59 1769
539b33b0
LP		 1770 format->width = state->timings.bt.width;
1771 format->height = state->timings.bt.height;
1772 format->field = V4L2_FIELD_NONE;
680fee04 1773 format->colorspace = V4L2_COLORSPACE_SRGB;
539b33b0 1774
680fee04 1775 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
539b33b0 1776 format->colorspace = (state->timings.bt.height <= 576) ?
54450f59 1777 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
539b33b0
LP		 1778}
1779
1780/*
1781 * Compute the op_ch_sel value required to obtain on the bus the component order
1782 * corresponding to the selected format taking into account bus reordering
1783 * applied by the board at the output of the device.
1784 *
1785 * The following table gives the op_ch_value from the format component order
1786 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
b44b2e06 1787 * adv76xx_bus_order value in row).
539b33b0
LP		 1788 *
1789 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1790 * ----------+-------------------------------------------------
1791 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1792 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1793 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1794 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1795 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1796 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1797 */
b44b2e06 1798static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
539b33b0
LP		 1799{
1800#define _SEL(a,b,c,d,e,f) { \
b44b2e06
PA		 1801 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1802 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
539b33b0
LP		 1803#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1804
1805 static const unsigned int op_ch_sel[6][6] = {
1806 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1807 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1808 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1809 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1810 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1811 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1812 };
1813
1814 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1815}
1816
b44b2e06 1817static void adv76xx_setup_format(struct adv76xx_state *state)
539b33b0
LP		 1818{
1819 struct v4l2_subdev *sd = &state->sd;
1820
22d97e56 1821 io_write_clr_set(sd, 0x02, 0x02,
b44b2e06 1822 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
539b33b0
LP		 1823 io_write(sd, 0x03, state->format->op_format_sel |
1824 state->pdata.op_format_mode_sel);
b44b2e06 1825 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
22d97e56 1826 io_write_clr_set(sd, 0x05, 0x01,
b44b2e06 1827 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
539b33b0
LP		 1828}
1829
f7234138
HV		 1830static int adv76xx_get_format(struct v4l2_subdev *sd,
1831 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1832 struct v4l2_subdev_format *format)
1833{
b44b2e06 1834 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1835
1836 if (format->pad != state->source_pad)
1837 return -EINVAL;
1838
b44b2e06 1839 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1840
1841 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1842 struct v4l2_mbus_framefmt *fmt;
1843
f7234138 1844 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1845 format->format.code = fmt->code;
1846 } else {
1847 format->format.code = state->format->code;
54450f59 1848 }
539b33b0
LP		 1849
1850 return 0;
1851}
1852
b7d4d2f8
UH		 1853static int adv76xx_get_selection(struct v4l2_subdev *sd,
1854 struct v4l2_subdev_pad_config *cfg,
1855 struct v4l2_subdev_selection *sel)
1856{
1857 struct adv76xx_state *state = to_state(sd);
1858
1859 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1860 return -EINVAL;
1861 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1862 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1863 return -EINVAL;
1864
1865 sel->r.left = 0;
1866 sel->r.top = 0;
1867 sel->r.width = state->timings.bt.width;
1868 sel->r.height = state->timings.bt.height;
1869
1870 return 0;
1871}
1872
f7234138
HV		 1873static int adv76xx_set_format(struct v4l2_subdev *sd,
1874 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1875 struct v4l2_subdev_format *format)
1876{
b44b2e06
PA		 1877 struct adv76xx_state *state = to_state(sd);
1878 const struct adv76xx_format_info *info;
539b33b0
LP		 1879
1880 if (format->pad != state->source_pad)
1881 return -EINVAL;
1882
b44b2e06 1883 info = adv76xx_format_info(state, format->format.code);
539b33b0 1884 if (info == NULL)
b44b2e06 1885 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
539b33b0 1886
b44b2e06 1887 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1888 format->format.code = info->code;
1889
1890 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1891 struct v4l2_mbus_framefmt *fmt;
1892
f7234138 1893 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1894 fmt->code = format->format.code;
1895 } else {
1896 state->format = info;
b44b2e06 1897 adv76xx_setup_format(state);
539b33b0
LP		 1898 }
1899
54450f59
HV		 1900 return 0;
1901}
1902
b44b2e06 1903static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
54450f59 1904{
b44b2e06
PA		 1905 struct adv76xx_state *state = to_state(sd);
1906 const struct adv76xx_chip_info *info = state->info;
f24d229c
MR		 1907 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1908 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1909 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1910 u8 fmt_change_digital;
1911 u8 fmt_change;
1912 u8 tx_5v;
1913
1914 if (irq_reg_0x43)
1915 io_write(sd, 0x44, irq_reg_0x43);
1916 if (irq_reg_0x70)
1917 io_write(sd, 0x71, irq_reg_0x70);
1918 if (irq_reg_0x6b)
1919 io_write(sd, 0x6c, irq_reg_0x6b);
54450f59 1920
ff4f80fd
MR		 1921 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1922
54450f59 1923 /* format change */
f24d229c 1924 fmt_change = irq_reg_0x43 & 0x98;
d42010a1
LPC		 1925 fmt_change_digital = is_digital_input(sd)
1926 ? irq_reg_0x6b & info->fmt_change_digital_mask
1927 : 0;
14d03233 1928
54450f59
HV		 1929 if (fmt_change || fmt_change_digital) {
1930 v4l2_dbg(1, debug, sd,
25a64ac9 1931 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1932 __func__, fmt_change, fmt_change_digital);
25a64ac9 1933
6f5bcfc3 1934 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
25a64ac9 1935
54450f59
HV		 1936 if (handled)
1937 *handled = true;
1938 }
f24d229c
MR		 1939 /* HDMI/DVI mode */
1940 if (irq_reg_0x6b & 0x01) {
1941 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1942 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1943 set_rgb_quantization_range(sd);
1944 if (handled)
1945 *handled = true;
1946 }
1947
54450f59 1948 /* tx 5v detect */
0ba4581c 1949 tx_5v = irq_reg_0x70 & info->cable_det_mask;
54450f59
HV		 1950 if (tx_5v) {
1951 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
b44b2e06 1952 adv76xx_s_detect_tx_5v_ctrl(sd);
54450f59
HV		 1953 if (handled)
1954 *handled = true;
1955 }
1956 return 0;
1957}
1958
b44b2e06 1959static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 1960{
b44b2e06 1961 struct adv76xx_state *state = to_state(sd);
4a31a93a 1962 u8 *data = NULL;
54450f59 1963
dd9ac11a 1964 memset(edid->reserved, 0, sizeof(edid->reserved));
4a31a93a
MR		 1965
1966 switch (edid->pad) {
b44b2e06 1967 case ADV76XX_PAD_HDMI_PORT_A:
c784b1e2
LP		 1968 case ADV7604_PAD_HDMI_PORT_B:
1969 case ADV7604_PAD_HDMI_PORT_C:
1970 case ADV7604_PAD_HDMI_PORT_D:
4a31a93a
MR		 1971 if (state->edid.present & (1 << edid->pad))
1972 data = state->edid.edid;
1973 break;
1974 default:
1975 return -EINVAL;
4a31a93a 1976 }
dd9ac11a
HV		 1977
1978 if (edid->start_block == 0 && edid->blocks == 0) {
1979 edid->blocks = data ? state->edid.blocks : 0;
1980 return 0;
1981 }
1982
1983 if (data == NULL)
4a31a93a
MR		 1984 return -ENODATA;
1985
dd9ac11a
HV		 1986 if (edid->start_block >= state->edid.blocks)
1987 return -EINVAL;
1988
1989 if (edid->start_block + edid->blocks > state->edid.blocks)
1990 edid->blocks = state->edid.blocks - edid->start_block;
1991
1992 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1993
54450f59
HV		 1994 return 0;
1995}
1996
dd08beb9 1997static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 1998{
1999 u8 d;
2000
2001 if ((edid[0x7e] != 1) ||
2002 (edid[0x80] != 0x02) ||
2003 (edid[0x81] != 0x03)) {
2004 return -1;
2005 }
2006
2007 /* search Vendor Specific Data Block (tag 3) */
2008 d = edid[0x82] & 0x7f;
2009 if (d > 4) {
2010 int i = 0x84;
2011 int end = 0x80 + d;
2012
2013 do {
2014 u8 tag = edid[i] >> 5;
2015 u8 len = edid[i] & 0x1f;
2016
2017 if ((tag == 3) && (len >= 5))
2018 return i + 4;
2019 i += len + 1;
2020 } while (i < end);
2021 }
2022 return -1;
2023}
2024
b44b2e06 2025static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 2026{
b44b2e06
PA		 2027 struct adv76xx_state *state = to_state(sd);
2028 const struct adv76xx_chip_info *info = state->info;
dd08beb9 2029 int spa_loc;
54450f59 2030 int err;
dd08beb9 2031 int i;
54450f59 2032
dd9ac11a
HV		 2033 memset(edid->reserved, 0, sizeof(edid->reserved));
2034
c784b1e2 2035 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
54450f59
HV		 2036 return -EINVAL;
2037 if (edid->start_block != 0)
2038 return -EINVAL;
2039 if (edid->blocks == 0) {
3e86aa85 2040 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2041 state->edid.present &= ~(1 << edid->pad);
b44b2e06 2042 adv76xx_set_hpd(state, state->edid.present);
22d97e56 2043 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
3e86aa85 2044
54450f59
HV		 2045 /* Fall back to a 16:9 aspect ratio */
2046 state->aspect_ratio.numerator = 16;
2047 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 2048
2049 if (!state->edid.present)
2050 state->edid.blocks = 0;
2051
2052 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2053 __func__, edid->pad, state->edid.present);
54450f59
HV		 2054 return 0;
2055 }
4a31a93a
MR		 2056 if (edid->blocks > 2) {
2057 edid->blocks = 2;
54450f59 2058 return -E2BIG;
4a31a93a 2059 }
4a31a93a 2060
dd08beb9
MR		 2061 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2062 __func__, edid->pad, state->edid.present);
2063
3e86aa85 2064 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2065 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
b44b2e06 2066 adv76xx_set_hpd(state, 0);
22d97e56 2067 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
3e86aa85 2068
dd08beb9
MR		 2069 spa_loc = get_edid_spa_location(edid->edid);
2070 if (spa_loc < 0)
2071 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2072
3e86aa85 2073 switch (edid->pad) {
b44b2e06 2074 case ADV76XX_PAD_HDMI_PORT_A:
dd08beb9
MR		 2075 state->spa_port_a[0] = edid->edid[spa_loc];
2076 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85 2077 break;
c784b1e2 2078 case ADV7604_PAD_HDMI_PORT_B:
dd08beb9
MR		 2079 rep_write(sd, 0x70, edid->edid[spa_loc]);
2080 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85 2081 break;
c784b1e2 2082 case ADV7604_PAD_HDMI_PORT_C:
dd08beb9
MR		 2083 rep_write(sd, 0x72, edid->edid[spa_loc]);
2084 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85 2085 break;
c784b1e2 2086 case ADV7604_PAD_HDMI_PORT_D:
dd08beb9
MR		 2087 rep_write(sd, 0x74, edid->edid[spa_loc]);
2088 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 2089 break;
dd08beb9
MR		 2090 default:
2091 return -EINVAL;
3e86aa85 2092 }
d42010a1
LPC		 2093
2094 if (info->type == ADV7604) {
2095 rep_write(sd, 0x76, spa_loc & 0xff);
22d97e56 2096 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
d42010a1
LPC		 2097 } else {
2098 /* FIXME: Where is the SPA location LSB register ? */
22d97e56 2099 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
d42010a1 2100 }
3e86aa85 2101
dd08beb9
MR		 2102 edid->edid[spa_loc] = state->spa_port_a[0];
2103 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 2104
2105 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2106 state->edid.blocks = edid->blocks;
54450f59
HV		 2107 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2108 edid->edid[0x16]);
3e86aa85 2109 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 2110
2111 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2112 if (err < 0) {
3e86aa85 2113 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 2114 return err;
2115 }
2116
b44b2e06 2117 /* adv76xx calculates the checksums and enables I2C access to internal
dd08beb9 2118 EDID RAM from DDC port. */
22d97e56 2119 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
dd08beb9
MR		 2120
2121 for (i = 0; i < 1000; i++) {
d42010a1 2122 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
dd08beb9
MR		 2123 break;
2124 mdelay(1);
2125 }
2126 if (i == 1000) {
2127 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2128 return -EIO;
2129 }
2130
4a31a93a
MR		 2131 /* enable hotplug after 100 ms */
2132 queue_delayed_work(state->work_queues,
2133 &state->delayed_work_enable_hotplug, HZ / 10);
2134 return 0;
54450f59
HV		 2135}
2136
2137/*********** avi info frame CEA-861-E **************/
2138
516613c1
HV		 2139static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2140 { "AVI", 0x01, 0xe0, 0x00 },
2141 { "Audio", 0x02, 0xe3, 0x1c },
2142 { "SDP", 0x04, 0xe6, 0x2a },
2143 { "Vendor", 0x10, 0xec, 0x54 }
2144};
2145
2146static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2147 union hdmi_infoframe *frame)
54450f59 2148{
516613c1
HV		 2149 uint8_t buffer[32];
2150 u8 len;
54450f59 2151 int i;
54450f59 2152
516613c1
HV		 2153 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2154 v4l2_info(sd, "%s infoframe not received\n",
2155 adv76xx_cri[index].desc);
2156 return -ENOENT;
54450f59 2157 }
516613c1
HV		 2158
2159 for (i = 0; i < 3; i++)
2160 buffer[i] = infoframe_read(sd,
2161 adv76xx_cri[index].head_addr + i);
2162
2163 len = buffer[2] + 1;
2164
2165 if (len + 3 > sizeof(buffer)) {
2166 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2167 adv76xx_cri[index].desc, len);
2168 return -ENOENT;
54450f59
HV		 2169 }
2170
516613c1
HV		 2171 for (i = 0; i < len; i++)
2172 buffer[i + 3] = infoframe_read(sd,
2173 adv76xx_cri[index].payload_addr + i);
2174
2175 if (hdmi_infoframe_unpack(frame, buffer) < 0) {
2176 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2177 adv76xx_cri[index].desc);
2178 return -ENOENT;
54450f59 2179 }
516613c1
HV		 2180 return 0;
2181}
54450f59 2182
516613c1
HV		 2183static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2184{
2185 int i;
54450f59 2186
516613c1
HV		 2187 if (!is_hdmi(sd)) {
2188 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
54450f59 2189 return;
516613c1 2190 }
54450f59 2191
516613c1
HV		 2192 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2193 union hdmi_infoframe frame;
2194 struct i2c_client *client = v4l2_get_subdevdata(sd);
54450f59 2195
516613c1
HV		 2196 if (adv76xx_read_infoframe(sd, i, &frame))
2197 return;
2198 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2199 }
54450f59
HV		 2200}
2201
b44b2e06 2202static int adv76xx_log_status(struct v4l2_subdev *sd)
54450f59 2203{
b44b2e06
PA		 2204 struct adv76xx_state *state = to_state(sd);
2205 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 2206 struct v4l2_dv_timings timings;
2207 struct stdi_readback stdi;
2208 u8 reg_io_0x02 = io_read(sd, 0x02);
4a2ccdd2
LP		 2209 u8 edid_enabled;
2210 u8 cable_det;
54450f59 2211
f216ccb3 2212 static const char * const csc_coeff_sel_rb[16] = {
54450f59
HV		 2213 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2214 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2215 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2216 "reserved", "reserved", "reserved", "reserved", "manual"
2217 };
f216ccb3 2218 static const char * const input_color_space_txt[16] = {
54450f59
HV		 2219 "RGB limited range (16-235)", "RGB full range (0-255)",
2220 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 2221 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 2222 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2223 "invalid", "invalid", "invalid", "invalid", "invalid",
2224 "invalid", "invalid", "automatic"
2225 };
7a5d99e7
HV		 2226 static const char * const hdmi_color_space_txt[16] = {
2227 "RGB limited range (16-235)", "RGB full range (0-255)",
2228 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2229 "xvYCC Bt.601", "xvYCC Bt.709",
2230 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2231 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid",
2232 "invalid", "invalid", "invalid"
2233 };
f216ccb3 2234 static const char * const rgb_quantization_range_txt[] = {
54450f59
HV		 2235 "Automatic",
2236 "RGB limited range (16-235)",
2237 "RGB full range (0-255)",
2238 };
f216ccb3 2239 static const char * const deep_color_mode_txt[4] = {
bb88f325
MB		 2240 "8-bits per channel",
2241 "10-bits per channel",
2242 "12-bits per channel",
2243 "16-bits per channel (not supported)"
2244 };
54450f59
HV		 2245
2246 v4l2_info(sd, "-----Chip status-----\n");
2247 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
d42010a1 2248 edid_enabled = rep_read(sd, info->edid_status_reg);
4a31a93a 2249 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
4a2ccdd2
LP		 2250 ((edid_enabled & 0x01) ? "Yes" : "No"),
2251 ((edid_enabled & 0x02) ? "Yes" : "No"),
2252 ((edid_enabled & 0x04) ? "Yes" : "No"),
2253 ((edid_enabled & 0x08) ? "Yes" : "No"));
54450f59
HV		 2254 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2255 "enabled" : "disabled");
2256
2257 v4l2_info(sd, "-----Signal status-----\n");
d42010a1 2258 cable_det = info->read_cable_det(sd);
4a31a93a 2259 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
d42010a1
LPC		 2260 ((cable_det & 0x01) ? "Yes" : "No"),
2261 ((cable_det & 0x02) ? "Yes" : "No"),
4a2ccdd2 2262 ((cable_det & 0x04) ? "Yes" : "No"),
d42010a1 2263 ((cable_det & 0x08) ? "Yes" : "No"));
54450f59
HV		 2264 v4l2_info(sd, "TMDS signal detected: %s\n",
2265 no_signal_tmds(sd) ? "false" : "true");
2266 v4l2_info(sd, "TMDS signal locked: %s\n",
2267 no_lock_tmds(sd) ? "false" : "true");
2268 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2269 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2270 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2271 v4l2_info(sd, "CP free run: %s\n",
58514625 2272 (in_free_run(sd)) ? "on" : "off");
ccbd5bc4
HV		 2273 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2274 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2275 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 2276
2277 v4l2_info(sd, "-----Video Timings-----\n");
2278 if (read_stdi(sd, &stdi))
2279 v4l2_info(sd, "STDI: not locked\n");
2280 else
2281 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2282 stdi.lcf, stdi.bl, stdi.lcvs,
2283 stdi.interlaced ? "interlaced" : "progressive",
2284 stdi.hs_pol, stdi.vs_pol);
b44b2e06 2285 if (adv76xx_query_dv_timings(sd, &timings))
54450f59
HV		 2286 v4l2_info(sd, "No video detected\n");
2287 else
11d034c8
HV		 2288 v4l2_print_dv_timings(sd->name, "Detected format: ",
2289 &timings, true);
2290 v4l2_print_dv_timings(sd->name, "Configured format: ",
2291 &state->timings, true);
54450f59 2292
76eb2d30
MR		 2293 if (no_signal(sd))
2294 return 0;
2295
54450f59
HV		 2296 v4l2_info(sd, "-----Color space-----\n");
2297 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2298 rgb_quantization_range_txt[state->rgb_quantization_range]);
2299 v4l2_info(sd, "Input color space: %s\n",
2300 input_color_space_txt[reg_io_0x02 >> 4]);
7a5d99e7 2301 v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n",
54450f59
HV		 2302 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2303 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
5dd7d88a 2304 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
7a5d99e7
HV		 2305 "enabled" : "disabled",
2306 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
54450f59 2307 v4l2_info(sd, "Color space conversion: %s\n",
80f4944e 2308 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
54450f59 2309
4a31a93a 2310 if (!is_digital_input(sd))
76eb2d30
MR		 2311 return 0;
2312
2313 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 2314 v4l2_info(sd, "Digital video port selected: %c\n",
2315 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2316 v4l2_info(sd, "HDCP encrypted content: %s\n",
2317 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 2318 v4l2_info(sd, "HDCP keys read: %s%s\n",
2319 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2320 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
77639ff2 2321 if (is_hdmi(sd)) {
76eb2d30
MR		 2322 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2323 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2324 bool audio_mute = io_read(sd, 0x65) & 0x40;
2325
2326 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2327 audio_pll_locked ? "locked" : "not locked",
2328 audio_sample_packet_detect ? "detected" : "not detected",
2329 audio_mute ? "muted" : "enabled");
2330 if (audio_pll_locked && audio_sample_packet_detect) {
2331 v4l2_info(sd, "Audio format: %s\n",
2332 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2333 }
2334 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2335 (hdmi_read(sd, 0x5c) << 8) +
2336 (hdmi_read(sd, 0x5d) & 0xf0));
2337 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2338 (hdmi_read(sd, 0x5e) << 8) +
2339 hdmi_read(sd, 0x5f));
2340 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2341
2342 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
7a5d99e7 2343 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
76eb2d30 2344
516613c1 2345 adv76xx_log_infoframes(sd);
54450f59
HV		 2346 }
2347
2348 return 0;
2349}
2350
6f5bcfc3
LPC		 2351static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2352 struct v4l2_fh *fh,
2353 struct v4l2_event_subscription *sub)
2354{
2355 switch (sub->type) {
2356 case V4L2_EVENT_SOURCE_CHANGE:
2357 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2358 case V4L2_EVENT_CTRL:
2359 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2360 default:
2361 return -EINVAL;
2362 }
2363}
2364
54450f59
HV		 2365/* ----------------------------------------------------------------------- */
2366
b44b2e06
PA		 2367static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2368 .s_ctrl = adv76xx_s_ctrl,
297a4144 2369 .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
54450f59
HV		 2370};
2371
b44b2e06
PA		 2372static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2373 .log_status = adv76xx_log_status,
2374 .interrupt_service_routine = adv76xx_isr,
6f5bcfc3 2375 .subscribe_event = adv76xx_subscribe_event,
0975626d 2376 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
54450f59 2377#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06
PA		 2378 .g_register = adv76xx_g_register,
2379 .s_register = adv76xx_s_register,
54450f59
HV		 2380#endif
2381};
2382
b44b2e06
PA		 2383static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2384 .s_routing = adv76xx_s_routing,
2385 .g_input_status = adv76xx_g_input_status,
2386 .s_dv_timings = adv76xx_s_dv_timings,
2387 .g_dv_timings = adv76xx_g_dv_timings,
2388 .query_dv_timings = adv76xx_query_dv_timings,
54450f59
HV		 2389};
2390
b44b2e06
PA		 2391static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2392 .enum_mbus_code = adv76xx_enum_mbus_code,
b7d4d2f8 2393 .get_selection = adv76xx_get_selection,
b44b2e06
PA		 2394 .get_fmt = adv76xx_get_format,
2395 .set_fmt = adv76xx_set_format,
2396 .get_edid = adv76xx_get_edid,
2397 .set_edid = adv76xx_set_edid,
2398 .dv_timings_cap = adv76xx_dv_timings_cap,
2399 .enum_dv_timings = adv76xx_enum_dv_timings,
54450f59
HV		 2400};
2401
b44b2e06
PA		 2402static const struct v4l2_subdev_ops adv76xx_ops = {
2403 .core = &adv76xx_core_ops,
2404 .video = &adv76xx_video_ops,
2405 .pad = &adv76xx_pad_ops,
54450f59
HV		 2406};
2407
2408/* -------------------------- custom ctrls ---------------------------------- */
2409
2410static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
b44b2e06 2411 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2412 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2413 .name = "Analog Sampling Phase",
2414 .type = V4L2_CTRL_TYPE_INTEGER,
2415 .min = 0,
2416 .max = 0x1f,
2417 .step = 1,
2418 .def = 0,
2419};
2420
b44b2e06
PA		 2421static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2422 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2423 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2424 .name = "Free Running Color, Manual",
2425 .type = V4L2_CTRL_TYPE_BOOLEAN,
2426 .min = false,
2427 .max = true,
2428 .step = 1,
2429 .def = false,
2430};
2431
b44b2e06
PA		 2432static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2433 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2434 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2435 .name = "Free Running Color",
2436 .type = V4L2_CTRL_TYPE_INTEGER,
2437 .min = 0x0,
2438 .max = 0xffffff,
2439 .step = 0x1,
2440 .def = 0x0,
2441};
2442
2443/* ----------------------------------------------------------------------- */
2444
b44b2e06 2445static int adv76xx_core_init(struct v4l2_subdev *sd)
54450f59 2446{
b44b2e06
PA		 2447 struct adv76xx_state *state = to_state(sd);
2448 const struct adv76xx_chip_info *info = state->info;
2449 struct adv76xx_platform_data *pdata = &state->pdata;
54450f59
HV		 2450
2451 hdmi_write(sd, 0x48,
2452 (pdata->disable_pwrdnb ? 0x80 : 0) |
2453 (pdata->disable_cable_det_rst ? 0x40 : 0));
2454
2455 disable_input(sd);
2456
5ef54b59
LP		 2457 if (pdata->default_input >= 0 &&
2458 pdata->default_input < state->source_pad) {
2459 state->selected_input = pdata->default_input;
2460 select_input(sd);
2461 enable_input(sd);
2462 }
2463
54450f59
HV		 2464 /* power */
2465 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2466 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2467 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2468
2469 /* video format */
22d97e56 2470 io_write_clr_set(sd, 0x02, 0x0f,
54450f59
HV		 2471 pdata->alt_gamma << 3 |
2472 pdata->op_656_range << 2 |
54450f59 2473 pdata->alt_data_sat << 0);
22d97e56 2474 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
539b33b0
LP		 2475 pdata->insert_av_codes << 2 |
2476 pdata->replicate_av_codes << 1);
b44b2e06 2477 adv76xx_setup_format(state);
54450f59 2478
54450f59 2479 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
98908696
MB		 2480
2481 /* VS, HS polarities */
1b5ab875
LP		 2482 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2483 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
f31b62e1
MK		 2484
2485 /* Adjust drive strength */
2486 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2487 pdata->dr_str_clk << 2 |
2488 pdata->dr_str_sync);
2489
54450f59
HV		 2490 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2491 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2492 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2493 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2494 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2495 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2496 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2497 for digital formats */
2498
5474b983 2499 /* HDMI audio */
22d97e56
LP		 2500 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2501 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2502 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
5474b983 2503
54450f59
HV		 2504 /* TODO from platform data */
2505 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2506
b44b2e06 2507 if (adv76xx_has_afe(state)) {
d42010a1 2508 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
22d97e56 2509 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
d42010a1 2510 }
54450f59 2511
54450f59 2512 /* interrupts */
d42010a1 2513 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
54450f59 2514 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
d42010a1
LPC		 2515 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2516 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2517 info->setup_irqs(sd);
54450f59
HV		 2518
2519 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2520}
2521
d42010a1
LPC		 2522static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2523{
2524 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2525}
2526
2527static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2528{
2529 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2530}
2531
8331d30b
WT		 2532static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2533{
2534 io_write(sd, 0x41, 0xd0); /* disable INT2 */
2535}
2536
b44b2e06 2537static void adv76xx_unregister_clients(struct adv76xx_state *state)
54450f59 2538{
05cacb17
LP		 2539 unsigned int i;
2540
2541 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2542 if (state->i2c_clients[i])
2543 i2c_unregister_device(state->i2c_clients[i]);
2544 }
54450f59
HV		 2545}
2546
b44b2e06 2547static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
54450f59
HV		 2548 u8 addr, u8 io_reg)
2549{
2550 struct i2c_client *client = v4l2_get_subdevdata(sd);
2551
2552 if (addr)
2553 io_write(sd, io_reg, addr << 1);
2554 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2555}
2556
b44b2e06 2557static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
d42010a1
LPC		 2558 /* reset ADI recommended settings for HDMI: */
2559 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2560 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2561 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2562 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2563 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2564 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2565 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2566 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2567 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2568 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2569 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2570 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2571 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
d42010a1
LPC		 2572
2573 /* set ADI recommended settings for digitizer */
2574 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2575 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2576 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2577 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2578 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2579 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
d42010a1 2580
b44b2e06 2581 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2582};
2583
b44b2e06 2584static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
d42010a1
LPC		 2585 /* set ADI recommended settings for HDMI: */
2586 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2587 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2588 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2589 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2590 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2591 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2592 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2593 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2594 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2595 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2596 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2597 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
d42010a1
LPC		 2598
2599 /* reset ADI recommended settings for digitizer */
2600 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2601 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2602 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
d42010a1 2603
b44b2e06 2604 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2605};
2606
b44b2e06 2607static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
c41ad9c3 2608 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
b44b2e06
PA		 2609 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2610 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2611 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2612 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2613 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2614 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2615 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2616 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2617 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2618 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2619 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2620
2621 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2622};
2623
8331d30b
WT		 2624static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
2625 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2626 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2627 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2628 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2629 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2630 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2631 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2632 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2633 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2634 { ADV76XX_REG_SEQ_TERM, 0 },
2635};
2636
b44b2e06 2637static const struct adv76xx_chip_info adv76xx_chip_info[] = {
d42010a1
LPC		 2638 [ADV7604] = {
2639 .type = ADV7604,
2640 .has_afe = true,
c784b1e2 2641 .max_port = ADV7604_PAD_VGA_COMP,
d42010a1
LPC		 2642 .num_dv_ports = 4,
2643 .edid_enable_reg = 0x77,
2644 .edid_status_reg = 0x7d,
2645 .lcf_reg = 0xb3,
2646 .tdms_lock_mask = 0xe0,
2647 .cable_det_mask = 0x1e,
2648 .fmt_change_digital_mask = 0xc1,
80f4944e 2649 .cp_csc = 0xfc,
539b33b0
LP		 2650 .formats = adv7604_formats,
2651 .nformats = ARRAY_SIZE(adv7604_formats),
d42010a1
LPC		 2652 .set_termination = adv7604_set_termination,
2653 .setup_irqs = adv7604_setup_irqs,
2654 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2655 .read_cable_det = adv7604_read_cable_det,
2656 .recommended_settings = {
2657 [0] = adv7604_recommended_settings_afe,
2658 [1] = adv7604_recommended_settings_hdmi,
2659 },
2660 .num_recommended_settings = {
2661 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2662 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2663 },
b44b2e06
PA		 2664 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2665 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
d42010a1 2666 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
b44b2e06
PA		 2667 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2668 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2669 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
d42010a1 2670 BIT(ADV7604_PAGE_VDP),
5380baaf 2671 .linewidth_mask = 0xfff,
2672 .field0_height_mask = 0xfff,
2673 .field1_height_mask = 0xfff,
2674 .hfrontporch_mask = 0x3ff,
2675 .hsync_mask = 0x3ff,
2676 .hbackporch_mask = 0x3ff,
2677 .field0_vfrontporch_mask = 0x1fff,
2678 .field0_vsync_mask = 0x1fff,
2679 .field0_vbackporch_mask = 0x1fff,
2680 .field1_vfrontporch_mask = 0x1fff,
2681 .field1_vsync_mask = 0x1fff,
2682 .field1_vbackporch_mask = 0x1fff,
d42010a1
LPC		 2683 },
2684 [ADV7611] = {
2685 .type = ADV7611,
2686 .has_afe = false,
b44b2e06 2687 .max_port = ADV76XX_PAD_HDMI_PORT_A,
d42010a1
LPC		 2688 .num_dv_ports = 1,
2689 .edid_enable_reg = 0x74,
2690 .edid_status_reg = 0x76,
2691 .lcf_reg = 0xa3,
2692 .tdms_lock_mask = 0x43,
2693 .cable_det_mask = 0x01,
2694 .fmt_change_digital_mask = 0x03,
80f4944e 2695 .cp_csc = 0xf4,
539b33b0
LP		 2696 .formats = adv7611_formats,
2697 .nformats = ARRAY_SIZE(adv7611_formats),
d42010a1
LPC		 2698 .set_termination = adv7611_set_termination,
2699 .setup_irqs = adv7611_setup_irqs,
2700 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2701 .read_cable_det = adv7611_read_cable_det,
2702 .recommended_settings = {
2703 [1] = adv7611_recommended_settings_hdmi,
2704 },
2705 .num_recommended_settings = {
2706 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2707 },
b44b2e06
PA		 2708 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2709 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2710 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2711 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
5380baaf 2712 .linewidth_mask = 0x1fff,
2713 .field0_height_mask = 0x1fff,
2714 .field1_height_mask = 0x1fff,
2715 .hfrontporch_mask = 0x1fff,
2716 .hsync_mask = 0x1fff,
2717 .hbackporch_mask = 0x1fff,
2718 .field0_vfrontporch_mask = 0x3fff,
2719 .field0_vsync_mask = 0x3fff,
2720 .field0_vbackporch_mask = 0x3fff,
2721 .field1_vfrontporch_mask = 0x3fff,
2722 .field1_vsync_mask = 0x3fff,
2723 .field1_vbackporch_mask = 0x3fff,
d42010a1 2724 },
8331d30b
WT		 2725 [ADV7612] = {
2726 .type = ADV7612,
2727 .has_afe = false,
7111cddd
WT		 2728 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */
2729 .num_dv_ports = 1, /* normally 2 */
8331d30b
WT		 2730 .edid_enable_reg = 0x74,
2731 .edid_status_reg = 0x76,
2732 .lcf_reg = 0xa3,
2733 .tdms_lock_mask = 0x43,
2734 .cable_det_mask = 0x01,
2735 .fmt_change_digital_mask = 0x03,
7111cddd 2736 .cp_csc = 0xf4,
8331d30b
WT		 2737 .formats = adv7612_formats,
2738 .nformats = ARRAY_SIZE(adv7612_formats),
2739 .set_termination = adv7611_set_termination,
2740 .setup_irqs = adv7612_setup_irqs,
2741 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
7111cddd 2742 .read_cable_det = adv7612_read_cable_det,
8331d30b
WT		 2743 .recommended_settings = {
2744 [1] = adv7612_recommended_settings_hdmi,
2745 },
2746 .num_recommended_settings = {
2747 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
2748 },
2749 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2750 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2751 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2752 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2753 .linewidth_mask = 0x1fff,
2754 .field0_height_mask = 0x1fff,
2755 .field1_height_mask = 0x1fff,
2756 .hfrontporch_mask = 0x1fff,
2757 .hsync_mask = 0x1fff,
2758 .hbackporch_mask = 0x1fff,
2759 .field0_vfrontporch_mask = 0x3fff,
2760 .field0_vsync_mask = 0x3fff,
2761 .field0_vbackporch_mask = 0x3fff,
2762 .field1_vfrontporch_mask = 0x3fff,
2763 .field1_vsync_mask = 0x3fff,
2764 .field1_vbackporch_mask = 0x3fff,
2765 },
d42010a1
LPC		 2766};
2767
7f099a75 2768static const struct i2c_device_id adv76xx_i2c_id[] = {
b44b2e06
PA		 2769 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2770 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
8331d30b 2771 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
f82f313e
LP		 2772 { }
2773};
b44b2e06 2774MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
f82f313e 2775
7f099a75 2776static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
b44b2e06 2777 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
8331d30b 2778 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
f82f313e
LP		 2779 { }
2780};
b44b2e06 2781MODULE_DEVICE_TABLE(of, adv76xx_of_id);
f82f313e 2782
b44b2e06 2783static int adv76xx_parse_dt(struct adv76xx_state *state)
f82f313e 2784{
6fa88045
LP		 2785 struct v4l2_of_endpoint bus_cfg;
2786 struct device_node *endpoint;
2787 struct device_node *np;
2788 unsigned int flags;
7f6cd6c4 2789 int ret;
bf9c8227 2790 u32 v;
6fa88045 2791
b44b2e06 2792 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
6fa88045
LP		 2793
2794 /* Parse the endpoint. */
2795 endpoint = of_graph_get_next_endpoint(np, NULL);
2796 if (!endpoint)
2797 return -EINVAL;
2798
7f6cd6c4
JMC		 2799 ret = v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2800 if (ret) {
2801 of_node_put(endpoint);
2802 return ret;
2803 }
bf9c8227
IM		 2804
2805 if (!of_property_read_u32(endpoint, "default-input", &v))
2806 state->pdata.default_input = v;
2807 else
2808 state->pdata.default_input = -1;
2809
6fa88045
LP		 2810 of_node_put(endpoint);
2811
2812 flags = bus_cfg.bus.parallel.flags;
2813
2814 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2815 state->pdata.inv_hs_pol = 1;
2816
2817 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2818 state->pdata.inv_vs_pol = 1;
2819
2820 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2821 state->pdata.inv_llc_pol = 1;
2822
2823 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2824 state->pdata.insert_av_codes = 1;
2825 state->pdata.op_656_range = 1;
2826 }
2827
f82f313e 2828 /* Disable the interrupt for now as no DT-based board uses it. */
b44b2e06 2829 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
f82f313e
LP		 2830
2831 /* Use the default I2C addresses. */
2832 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
b44b2e06
PA		 2833 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2834 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
f82f313e
LP		 2835 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2836 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
b44b2e06
PA		 2837 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2838 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2839 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2840 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2841 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2842 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
f82f313e
LP		 2843 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2844
2845 /* Hardcode the remaining platform data fields. */
2846 state->pdata.disable_pwrdnb = 0;
2847 state->pdata.disable_cable_det_rst = 0;
f82f313e 2848 state->pdata.blank_data = 1;
f82f313e 2849 state->pdata.alt_data_sat = 1;
f82f313e
LP		 2850 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2851 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2852
2853 return 0;
2854}
2855
f862f57d
PA		 2856static const struct regmap_config adv76xx_regmap_cnf[] = {
2857 {
2858 .name = "io",
2859 .reg_bits = 8,
2860 .val_bits = 8,
2861
2862 .max_register = 0xff,
2863 .cache_type = REGCACHE_NONE,
2864 },
2865 {
2866 .name = "avlink",
2867 .reg_bits = 8,
2868 .val_bits = 8,
2869
2870 .max_register = 0xff,
2871 .cache_type = REGCACHE_NONE,
2872 },
2873 {
2874 .name = "cec",
2875 .reg_bits = 8,
2876 .val_bits = 8,
2877
2878 .max_register = 0xff,
2879 .cache_type = REGCACHE_NONE,
2880 },
2881 {
2882 .name = "infoframe",
2883 .reg_bits = 8,
2884 .val_bits = 8,
2885
2886 .max_register = 0xff,
2887 .cache_type = REGCACHE_NONE,
2888 },
2889 {
2890 .name = "esdp",
2891 .reg_bits = 8,
2892 .val_bits = 8,
2893
2894 .max_register = 0xff,
2895 .cache_type = REGCACHE_NONE,
2896 },
2897 {
2898 .name = "epp",
2899 .reg_bits = 8,
2900 .val_bits = 8,
2901
2902 .max_register = 0xff,
2903 .cache_type = REGCACHE_NONE,
2904 },
2905 {
2906 .name = "afe",
2907 .reg_bits = 8,
2908 .val_bits = 8,
2909
2910 .max_register = 0xff,
2911 .cache_type = REGCACHE_NONE,
2912 },
2913 {
2914 .name = "rep",
2915 .reg_bits = 8,
2916 .val_bits = 8,
2917
2918 .max_register = 0xff,
2919 .cache_type = REGCACHE_NONE,
2920 },
2921 {
2922 .name = "edid",
2923 .reg_bits = 8,
2924 .val_bits = 8,
2925
2926 .max_register = 0xff,
2927 .cache_type = REGCACHE_NONE,
2928 },
2929
2930 {
2931 .name = "hdmi",
2932 .reg_bits = 8,
2933 .val_bits = 8,
2934
2935 .max_register = 0xff,
2936 .cache_type = REGCACHE_NONE,
2937 },
2938 {
2939 .name = "test",
2940 .reg_bits = 8,
2941 .val_bits = 8,
2942
2943 .max_register = 0xff,
2944 .cache_type = REGCACHE_NONE,
2945 },
2946 {
2947 .name = "cp",
2948 .reg_bits = 8,
2949 .val_bits = 8,
2950
2951 .max_register = 0xff,
2952 .cache_type = REGCACHE_NONE,
2953 },
2954 {
2955 .name = "vdp",
2956 .reg_bits = 8,
2957 .val_bits = 8,
2958
2959 .max_register = 0xff,
2960 .cache_type = REGCACHE_NONE,
2961 },
2962};
2963
2964static int configure_regmap(struct adv76xx_state *state, int region)
2965{
2966 int err;
2967
2968 if (!state->i2c_clients[region])
2969 return -ENODEV;
2970
2971 state->regmap[region] =
2972 devm_regmap_init_i2c(state->i2c_clients[region],
2973 &adv76xx_regmap_cnf[region]);
2974
2975 if (IS_ERR(state->regmap[region])) {
2976 err = PTR_ERR(state->regmap[region]);
2977 v4l_err(state->i2c_clients[region],
2978 "Error initializing regmap %d with error %d\n",
2979 region, err);
2980 return -EINVAL;
2981 }
2982
2983 return 0;
2984}
2985
2986static int configure_regmaps(struct adv76xx_state *state)
2987{
2988 int i, err;
2989
2990 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
2991 err = configure_regmap(state, i);
2992 if (err && (err != -ENODEV))
2993 return err;
2994 }
2995 return 0;
2996}
2997
b44b2e06 2998static int adv76xx_probe(struct i2c_client *client,
54450f59
HV		 2999 const struct i2c_device_id *id)
3000{
591b72fe
HV		 3001 static const struct v4l2_dv_timings cea640x480 =
3002 V4L2_DV_BT_CEA_640X480P59_94;
b44b2e06 3003 struct adv76xx_state *state;
54450f59 3004 struct v4l2_ctrl_handler *hdl;
297a4144 3005 struct v4l2_ctrl *ctrl;
54450f59 3006 struct v4l2_subdev *sd;
c784b1e2 3007 unsigned int i;
f862f57d 3008 unsigned int val, val2;
54450f59
HV		 3009 int err;
3010
3011 /* Check if the adapter supports the needed features */
3012 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3013 return -EIO;
b44b2e06 3014 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
54450f59
HV		 3015 client->addr << 1);
3016
c02b211d 3017 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59 3018 if (!state) {
b44b2e06 3019 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
54450f59
HV		 3020 return -ENOMEM;
3021 }
3022
b44b2e06 3023 state->i2c_clients[ADV76XX_PAGE_IO] = client;
d42010a1 3024
25a64ac9
MR		 3025 /* initialize variables */
3026 state->restart_stdi_once = true;
ff4f80fd 3027 state->selected_input = ~0;
25a64ac9 3028
f82f313e
LP		 3029 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3030 const struct of_device_id *oid;
3031
b44b2e06 3032 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
f82f313e
LP		 3033 state->info = oid->data;
3034
b44b2e06 3035 err = adv76xx_parse_dt(state);
f82f313e
LP		 3036 if (err < 0) {
3037 v4l_err(client, "DT parsing error\n");
3038 return err;
3039 }
3040 } else if (client->dev.platform_data) {
b44b2e06 3041 struct adv76xx_platform_data *pdata = client->dev.platform_data;
f82f313e 3042
b44b2e06 3043 state->info = (const struct adv76xx_chip_info *)id->driver_data;
f82f313e
LP		 3044 state->pdata = *pdata;
3045 } else {
54450f59 3046 v4l_err(client, "No platform data!\n");
c02b211d 3047 return -ENODEV;
54450f59 3048 }
e9d50e9e
LP		 3049
3050 /* Request GPIOs. */
3051 for (i = 0; i < state->info->num_dv_ports; ++i) {
3052 state->hpd_gpio[i] =
269bd132
UKK		 3053 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3054 GPIOD_OUT_LOW);
e9d50e9e 3055 if (IS_ERR(state->hpd_gpio[i]))
269bd132 3056 return PTR_ERR(state->hpd_gpio[i]);
e9d50e9e 3057
269bd132
UKK		 3058 if (state->hpd_gpio[i])
3059 v4l_info(client, "Handling HPD %u GPIO\n", i);
e9d50e9e
LP		 3060 }
3061
591b72fe 3062 state->timings = cea640x480;
b44b2e06 3063 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
54450f59
HV		 3064
3065 sd = &state->sd;
b44b2e06 3066 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
d42010a1
LPC		 3067 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3068 id->name, i2c_adapter_id(client->adapter),
3069 client->addr);
0975626d 3070 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
54450f59 3071
f862f57d
PA		 3072 /* Configure IO Regmap region */
3073 err = configure_regmap(state, ADV76XX_PAGE_IO);
3074
3075 if (err) {
3076 v4l2_err(sd, "Error configuring IO regmap region\n");
3077 return -ENODEV;
3078 }
3079
d42010a1
LPC		 3080 /*
3081 * Verify that the chip is present. On ADV7604 the RD_INFO register only
3082 * identifies the revision, while on ADV7611 it identifies the model as
3083 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3084 */
8331d30b
WT		 3085 switch (state->info->type) {
3086 case ADV7604:
f862f57d
PA		 3087 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3088 if (err) {
3089 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3090 return -ENODEV;
3091 }
d42010a1 3092 if (val != 0x68) {
f862f57d 3093 v4l2_err(sd, "not an adv7604 on address 0x%x\n",
d42010a1
LPC		 3094 client->addr << 1);
3095 return -ENODEV;
3096 }
8331d30b
WT		 3097 break;
3098 case ADV7611:
3099 case ADV7612:
f862f57d
PA		 3100 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3101 0xea,
3102 &val);
3103 if (err) {
3104 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3105 return -ENODEV;
3106 }
3107 val2 = val << 8;
3108 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3109 0xeb,
3110 &val);
3111 if (err) {
3112 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3113 return -ENODEV;
3114 }
c1362384 3115 val |= val2;
8331d30b
WT		 3116 if ((state->info->type == ADV7611 && val != 0x2051) ||
3117 (state->info->type == ADV7612 && val != 0x2041)) {
3118 v4l2_err(sd, "not an adv761x on address 0x%x\n",
d42010a1
LPC		 3119 client->addr << 1);
3120 return -ENODEV;
3121 }
8331d30b 3122 break;
54450f59
HV		 3123 }
3124
3125 /* control handlers */
3126 hdl = &state->hdl;
b44b2e06 3127 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
54450f59 3128
b44b2e06 3129 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3130 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
b44b2e06 3131 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3132 V4L2_CID_CONTRAST, 0, 255, 1, 128);
b44b2e06 3133 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3134 V4L2_CID_SATURATION, 0, 255, 1, 128);
b44b2e06 3135 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3136 V4L2_CID_HUE, 0, 128, 1, 0);
297a4144
HV		 3137 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3138 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3139 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3140 if (ctrl)
3141 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
54450f59
HV		 3142
3143 /* private controls */
3144 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
d42010a1
LPC		 3145 V4L2_CID_DV_RX_POWER_PRESENT, 0,
3146 (1 << state->info->num_dv_ports) - 1, 0, 0);
54450f59 3147 state->rgb_quantization_range_ctrl =
b44b2e06 3148 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 3149 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3150 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 3151
3152 /* custom controls */
b44b2e06 3153 if (adv76xx_has_afe(state))
d42010a1
LPC		 3154 state->analog_sampling_phase_ctrl =
3155 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59 3156 state->free_run_color_manual_ctrl =
b44b2e06 3157 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
54450f59 3158 state->free_run_color_ctrl =
b44b2e06 3159 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
54450f59
HV		 3160
3161 sd->ctrl_handler = hdl;
3162 if (hdl->error) {
3163 err = hdl->error;
3164 goto err_hdl;
3165 }
8c0eadb8
HV		 3166 state->detect_tx_5v_ctrl->is_private = true;
3167 state->rgb_quantization_range_ctrl->is_private = true;
b44b2e06 3168 if (adv76xx_has_afe(state))
d42010a1 3169 state->analog_sampling_phase_ctrl->is_private = true;
8c0eadb8
HV		 3170 state->free_run_color_manual_ctrl->is_private = true;
3171 state->free_run_color_ctrl->is_private = true;
3172
b44b2e06 3173 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
54450f59
HV		 3174 err = -ENODEV;
3175 goto err_hdl;
3176 }
3177
b44b2e06 3178 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
05cacb17
LP		 3179 if (!(BIT(i) & state->info->page_mask))
3180 continue;
54450f59 3181
05cacb17 3182 state->i2c_clients[i] =
b44b2e06 3183 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
05cacb17
LP		 3184 0xf2 + i);
3185 if (state->i2c_clients[i] == NULL) {
d42010a1 3186 err = -ENOMEM;
05cacb17 3187 v4l2_err(sd, "failed to create i2c client %u\n", i);
d42010a1
LPC		 3188 goto err_i2c;
3189 }
3190 }
05cacb17 3191
54450f59
HV		 3192 /* work queues */
3193 state->work_queues = create_singlethread_workqueue(client->name);
3194 if (!state->work_queues) {
3195 v4l2_err(sd, "Could not create work queue\n");
3196 err = -ENOMEM;
3197 goto err_i2c;
3198 }
3199
3200 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
b44b2e06 3201 adv76xx_delayed_work_enable_hotplug);
54450f59 3202
c784b1e2
LP		 3203 state->source_pad = state->info->num_dv_ports
3204 + (state->info->has_afe ? 2 : 0);
3205 for (i = 0; i < state->source_pad; ++i)
3206 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3207 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3208
ab22e77c 3209 err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
18095107 3210 state->pads);
54450f59
HV		 3211 if (err)
3212 goto err_work_queues;
3213
f862f57d
PA		 3214 /* Configure regmaps */
3215 err = configure_regmaps(state);
3216 if (err)
3217 goto err_entity;
3218
b44b2e06 3219 err = adv76xx_core_init(sd);
54450f59
HV		 3220 if (err)
3221 goto err_entity;
3222 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3223 client->addr << 1, client->adapter->name);
bedc3939
LPC		 3224
3225 err = v4l2_async_register_subdev(sd);
3226 if (err)
3227 goto err_entity;
3228
54450f59
HV		 3229 return 0;
3230
3231err_entity:
3232 media_entity_cleanup(&sd->entity);
3233err_work_queues:
3234 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3235 destroy_workqueue(state->work_queues);
3236err_i2c:
b44b2e06 3237 adv76xx_unregister_clients(state);
54450f59
HV		 3238err_hdl:
3239 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 3240 return err;
3241}
3242
3243/* ----------------------------------------------------------------------- */
3244
b44b2e06 3245static int adv76xx_remove(struct i2c_client *client)
54450f59
HV		 3246{
3247 struct v4l2_subdev *sd = i2c_get_clientdata(client);
b44b2e06 3248 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 3249
3250 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3251 destroy_workqueue(state->work_queues);
bedc3939 3252 v4l2_async_unregister_subdev(sd);
54450f59 3253 media_entity_cleanup(&sd->entity);
b44b2e06 3254 adv76xx_unregister_clients(to_state(sd));
54450f59 3255 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 3256 return 0;
3257}
3258
3259/* ----------------------------------------------------------------------- */
3260
b44b2e06 3261static struct i2c_driver adv76xx_driver = {
54450f59 3262 .driver = {
54450f59 3263 .name = "adv7604",
b44b2e06 3264 .of_match_table = of_match_ptr(adv76xx_of_id),
54450f59 3265 },
b44b2e06
PA		 3266 .probe = adv76xx_probe,
3267 .remove = adv76xx_remove,
3268 .id_table = adv76xx_i2c_id,
54450f59
HV		 3269};
3270
b44b2e06 3271module_i2c_driver(adv76xx_driver);
Linux kernel - Deliverables
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