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7397bfbe GL |
1 | /* |
2 | * Driver for MT9V022 CMOS Image Sensor from Micron | |
3 | * | |
4 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/videodev2.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/i2c.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/log2.h> | |
7a707b89 | 16 | #include <linux/module.h> |
7397bfbe | 17 | |
b5dcee22 | 18 | #include <media/i2c/mt9v022.h> |
e8e2c70c | 19 | #include <media/soc_camera.h> |
d647f0b7 | 20 | #include <media/drv-intf/soc_mediabus.h> |
979ea1dd | 21 | #include <media/v4l2-subdev.h> |
9aea470b | 22 | #include <media/v4l2-clk.h> |
ab7b50ae | 23 | #include <media/v4l2-ctrls.h> |
7397bfbe | 24 | |
5d28d525 GL |
25 | /* |
26 | * mt9v022 i2c address 0x48, 0x4c, 0x58, 0x5c | |
22cf83fa | 27 | * The platform has to define struct i2c_board_info objects and link to them |
25a34811 | 28 | * from struct soc_camera_host_desc |
5d28d525 | 29 | */ |
7397bfbe GL |
30 | |
31 | static char *sensor_type; | |
32 | module_param(sensor_type, charp, S_IRUGO); | |
61a2d07d | 33 | MODULE_PARM_DESC(sensor_type, "Sensor type: \"colour\" or \"monochrome\""); |
7397bfbe GL |
34 | |
35 | /* mt9v022 selected register addresses */ | |
36 | #define MT9V022_CHIP_VERSION 0x00 | |
37 | #define MT9V022_COLUMN_START 0x01 | |
38 | #define MT9V022_ROW_START 0x02 | |
39 | #define MT9V022_WINDOW_HEIGHT 0x03 | |
40 | #define MT9V022_WINDOW_WIDTH 0x04 | |
41 | #define MT9V022_HORIZONTAL_BLANKING 0x05 | |
42 | #define MT9V022_VERTICAL_BLANKING 0x06 | |
43 | #define MT9V022_CHIP_CONTROL 0x07 | |
44 | #define MT9V022_SHUTTER_WIDTH1 0x08 | |
45 | #define MT9V022_SHUTTER_WIDTH2 0x09 | |
46 | #define MT9V022_SHUTTER_WIDTH_CTRL 0x0a | |
47 | #define MT9V022_TOTAL_SHUTTER_WIDTH 0x0b | |
48 | #define MT9V022_RESET 0x0c | |
49 | #define MT9V022_READ_MODE 0x0d | |
50 | #define MT9V022_MONITOR_MODE 0x0e | |
51 | #define MT9V022_PIXEL_OPERATION_MODE 0x0f | |
52 | #define MT9V022_LED_OUT_CONTROL 0x1b | |
53 | #define MT9V022_ADC_MODE_CONTROL 0x1c | |
d0bac768 | 54 | #define MT9V022_REG32 0x20 |
96c75399 | 55 | #define MT9V022_ANALOG_GAIN 0x35 |
7397bfbe GL |
56 | #define MT9V022_BLACK_LEVEL_CALIB_CTRL 0x47 |
57 | #define MT9V022_PIXCLK_FV_LV 0x74 | |
58 | #define MT9V022_DIGITAL_TEST_PATTERN 0x7f | |
59 | #define MT9V022_AEC_AGC_ENABLE 0xAF | |
60 | #define MT9V022_MAX_TOTAL_SHUTTER_WIDTH 0xBD | |
61 | ||
c078ac18 AG |
62 | /* mt9v024 partial list register addresses changes with respect to mt9v022 */ |
63 | #define MT9V024_PIXCLK_FV_LV 0x72 | |
64 | #define MT9V024_MAX_TOTAL_SHUTTER_WIDTH 0xAD | |
65 | ||
7397bfbe GL |
66 | /* Progressive scan, master, defaults */ |
67 | #define MT9V022_CHIP_CONTROL_DEFAULT 0x188 | |
68 | ||
6a6c8786 GL |
69 | #define MT9V022_MAX_WIDTH 752 |
70 | #define MT9V022_MAX_HEIGHT 480 | |
71 | #define MT9V022_MIN_WIDTH 48 | |
72 | #define MT9V022_MIN_HEIGHT 32 | |
73 | #define MT9V022_COLUMN_SKIP 1 | |
74 | #define MT9V022_ROW_SKIP 4 | |
75 | ||
6cc1eb70 AG |
76 | #define MT9V022_HORIZONTAL_BLANKING_MIN 43 |
77 | #define MT9V022_HORIZONTAL_BLANKING_MAX 1023 | |
78 | #define MT9V022_HORIZONTAL_BLANKING_DEF 94 | |
79 | #define MT9V022_VERTICAL_BLANKING_MIN 2 | |
80 | #define MT9V022_VERTICAL_BLANKING_MAX 3000 | |
81 | #define MT9V022_VERTICAL_BLANKING_DEF 45 | |
82 | ||
d0bac768 AG |
83 | #define is_mt9v022_rev3(id) (id == 0x1313) |
84 | #define is_mt9v024(id) (id == 0x1324) | |
c078ac18 | 85 | |
760697be GL |
86 | /* MT9V022 has only one fixed colorspace per pixelcode */ |
87 | struct mt9v022_datafmt { | |
f5fe58fd | 88 | u32 code; |
760697be GL |
89 | enum v4l2_colorspace colorspace; |
90 | }; | |
91 | ||
92 | /* Find a data format by a pixel code in an array */ | |
93 | static const struct mt9v022_datafmt *mt9v022_find_datafmt( | |
f5fe58fd | 94 | u32 code, const struct mt9v022_datafmt *fmt, |
760697be GL |
95 | int n) |
96 | { | |
97 | int i; | |
98 | for (i = 0; i < n; i++) | |
99 | if (fmt[i].code == code) | |
100 | return fmt + i; | |
101 | ||
102 | return NULL; | |
103 | } | |
104 | ||
105 | static const struct mt9v022_datafmt mt9v022_colour_fmts[] = { | |
5d28d525 GL |
106 | /* |
107 | * Order important: first natively supported, | |
108 | * second supported with a GPIO extender | |
109 | */ | |
f5fe58fd BB |
110 | {MEDIA_BUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB}, |
111 | {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB}, | |
bb55de3b GL |
112 | }; |
113 | ||
760697be | 114 | static const struct mt9v022_datafmt mt9v022_monochrome_fmts[] = { |
bb55de3b | 115 | /* Order important - see above */ |
f5fe58fd BB |
116 | {MEDIA_BUS_FMT_Y10_1X10, V4L2_COLORSPACE_JPEG}, |
117 | {MEDIA_BUS_FMT_Y8_1X8, V4L2_COLORSPACE_JPEG}, | |
7397bfbe GL |
118 | }; |
119 | ||
c078ac18 AG |
120 | /* only registers with different addresses on different mt9v02x sensors */ |
121 | struct mt9v02x_register { | |
122 | u8 max_total_shutter_width; | |
123 | u8 pixclk_fv_lv; | |
124 | }; | |
125 | ||
126 | static const struct mt9v02x_register mt9v022_register = { | |
127 | .max_total_shutter_width = MT9V022_MAX_TOTAL_SHUTTER_WIDTH, | |
128 | .pixclk_fv_lv = MT9V022_PIXCLK_FV_LV, | |
129 | }; | |
130 | ||
131 | static const struct mt9v02x_register mt9v024_register = { | |
132 | .max_total_shutter_width = MT9V024_MAX_TOTAL_SHUTTER_WIDTH, | |
133 | .pixclk_fv_lv = MT9V024_PIXCLK_FV_LV, | |
134 | }; | |
135 | ||
6be89daa HV |
136 | enum mt9v022_model { |
137 | MT9V022IX7ATM, | |
138 | MT9V022IX7ATC, | |
139 | }; | |
140 | ||
7397bfbe | 141 | struct mt9v022 { |
979ea1dd | 142 | struct v4l2_subdev subdev; |
ab7b50ae HV |
143 | struct v4l2_ctrl_handler hdl; |
144 | struct { | |
145 | /* exposure/auto-exposure cluster */ | |
146 | struct v4l2_ctrl *autoexposure; | |
147 | struct v4l2_ctrl *exposure; | |
148 | }; | |
149 | struct { | |
150 | /* gain/auto-gain cluster */ | |
151 | struct v4l2_ctrl *autogain; | |
152 | struct v4l2_ctrl *gain; | |
153 | }; | |
6cc1eb70 AG |
154 | struct v4l2_ctrl *hblank; |
155 | struct v4l2_ctrl *vblank; | |
6a6c8786 | 156 | struct v4l2_rect rect; /* Sensor window */ |
9aea470b | 157 | struct v4l2_clk *clk; |
760697be GL |
158 | const struct mt9v022_datafmt *fmt; |
159 | const struct mt9v022_datafmt *fmts; | |
c078ac18 | 160 | const struct mt9v02x_register *reg; |
760697be | 161 | int num_fmts; |
6be89daa | 162 | enum mt9v022_model model; |
7397bfbe | 163 | u16 chip_control; |
d0bac768 | 164 | u16 chip_version; |
32536108 | 165 | unsigned short y_skip_top; /* Lines to skip at the top */ |
7397bfbe GL |
166 | }; |
167 | ||
979ea1dd GL |
168 | static struct mt9v022 *to_mt9v022(const struct i2c_client *client) |
169 | { | |
170 | return container_of(i2c_get_clientdata(client), struct mt9v022, subdev); | |
171 | } | |
172 | ||
9538e1c2 | 173 | static int reg_read(struct i2c_client *client, const u8 reg) |
7397bfbe | 174 | { |
3f877045 | 175 | return i2c_smbus_read_word_swapped(client, reg); |
7397bfbe GL |
176 | } |
177 | ||
9538e1c2 | 178 | static int reg_write(struct i2c_client *client, const u8 reg, |
7397bfbe GL |
179 | const u16 data) |
180 | { | |
3f877045 | 181 | return i2c_smbus_write_word_swapped(client, reg, data); |
7397bfbe GL |
182 | } |
183 | ||
9538e1c2 | 184 | static int reg_set(struct i2c_client *client, const u8 reg, |
7397bfbe GL |
185 | const u16 data) |
186 | { | |
187 | int ret; | |
188 | ||
9538e1c2 | 189 | ret = reg_read(client, reg); |
7397bfbe GL |
190 | if (ret < 0) |
191 | return ret; | |
9538e1c2 | 192 | return reg_write(client, reg, ret | data); |
7397bfbe GL |
193 | } |
194 | ||
9538e1c2 | 195 | static int reg_clear(struct i2c_client *client, const u8 reg, |
7397bfbe GL |
196 | const u16 data) |
197 | { | |
198 | int ret; | |
199 | ||
9538e1c2 | 200 | ret = reg_read(client, reg); |
7397bfbe GL |
201 | if (ret < 0) |
202 | return ret; | |
9538e1c2 | 203 | return reg_write(client, reg, ret & ~data); |
7397bfbe GL |
204 | } |
205 | ||
a4c56fd8 | 206 | static int mt9v022_init(struct i2c_client *client) |
7397bfbe | 207 | { |
979ea1dd | 208 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
7397bfbe GL |
209 | int ret; |
210 | ||
5d28d525 GL |
211 | /* |
212 | * Almost the default mode: master, parallel, simultaneous, and an | |
7397bfbe | 213 | * undocumented bit 0x200, which is present in table 7, but not in 8, |
5d28d525 GL |
214 | * plus snapshot mode to disable scan for now |
215 | */ | |
7397bfbe | 216 | mt9v022->chip_control |= 0x10; |
9538e1c2 | 217 | ret = reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control); |
11211641 | 218 | if (!ret) |
9538e1c2 | 219 | ret = reg_write(client, MT9V022_READ_MODE, 0x300); |
7397bfbe GL |
220 | |
221 | /* All defaults */ | |
11211641 | 222 | if (!ret) |
7397bfbe | 223 | /* AEC, AGC on */ |
9538e1c2 | 224 | ret = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x3); |
96c75399 GL |
225 | if (!ret) |
226 | ret = reg_write(client, MT9V022_ANALOG_GAIN, 16); | |
227 | if (!ret) | |
228 | ret = reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, 480); | |
11211641 | 229 | if (!ret) |
c078ac18 | 230 | ret = reg_write(client, mt9v022->reg->max_total_shutter_width, 480); |
11211641 | 231 | if (!ret) |
7397bfbe | 232 | /* default - auto */ |
9538e1c2 | 233 | ret = reg_clear(client, MT9V022_BLACK_LEVEL_CALIB_CTRL, 1); |
11211641 | 234 | if (!ret) |
9538e1c2 | 235 | ret = reg_write(client, MT9V022_DIGITAL_TEST_PATTERN, 0); |
ab7b50ae HV |
236 | if (!ret) |
237 | return v4l2_ctrl_handler_setup(&mt9v022->hdl); | |
7397bfbe | 238 | |
11211641 | 239 | return ret; |
7397bfbe GL |
240 | } |
241 | ||
979ea1dd | 242 | static int mt9v022_s_stream(struct v4l2_subdev *sd, int enable) |
7397bfbe | 243 | { |
c4ce6d14 | 244 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
979ea1dd | 245 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
81034663 | 246 | |
d0bac768 | 247 | if (enable) { |
979ea1dd GL |
248 | /* Switch to master "normal" mode */ |
249 | mt9v022->chip_control &= ~0x10; | |
d0bac768 AG |
250 | if (is_mt9v022_rev3(mt9v022->chip_version) || |
251 | is_mt9v024(mt9v022->chip_version)) { | |
252 | /* | |
253 | * Unset snapshot mode specific settings: clear bit 9 | |
254 | * and bit 2 in reg. 0x20 when in normal mode. | |
255 | */ | |
256 | if (reg_clear(client, MT9V022_REG32, 0x204)) | |
257 | return -EIO; | |
258 | } | |
259 | } else { | |
979ea1dd GL |
260 | /* Switch to snapshot mode */ |
261 | mt9v022->chip_control |= 0x10; | |
d0bac768 AG |
262 | if (is_mt9v022_rev3(mt9v022->chip_version) || |
263 | is_mt9v024(mt9v022->chip_version)) { | |
264 | /* | |
265 | * Required settings for snapshot mode: set bit 9 | |
266 | * (RST enable) and bit 2 (CR enable) in reg. 0x20 | |
267 | * See TechNote TN0960 or TN-09-225. | |
268 | */ | |
269 | if (reg_set(client, MT9V022_REG32, 0x204)) | |
270 | return -EIO; | |
271 | } | |
272 | } | |
7397bfbe | 273 | |
979ea1dd | 274 | if (reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control) < 0) |
7397bfbe GL |
275 | return -EIO; |
276 | return 0; | |
277 | } | |
278 | ||
4f996594 | 279 | static int mt9v022_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a) |
ad5f2e85 | 280 | { |
c4ce6d14 | 281 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
6a6c8786 GL |
282 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
283 | struct v4l2_rect rect = a->c; | |
bff79939 | 284 | int min_row, min_blank; |
ad5f2e85 GL |
285 | int ret; |
286 | ||
6a6c8786 | 287 | /* Bayer format - even size lengths */ |
760697be | 288 | if (mt9v022->fmts == mt9v022_colour_fmts) { |
6a6c8786 GL |
289 | rect.width = ALIGN(rect.width, 2); |
290 | rect.height = ALIGN(rect.height, 2); | |
291 | /* Let the user play with the starting pixel */ | |
292 | } | |
293 | ||
294 | soc_camera_limit_side(&rect.left, &rect.width, | |
295 | MT9V022_COLUMN_SKIP, MT9V022_MIN_WIDTH, MT9V022_MAX_WIDTH); | |
296 | ||
297 | soc_camera_limit_side(&rect.top, &rect.height, | |
298 | MT9V022_ROW_SKIP, MT9V022_MIN_HEIGHT, MT9V022_MAX_HEIGHT); | |
299 | ||
7397bfbe | 300 | /* Like in example app. Contradicts the datasheet though */ |
9538e1c2 | 301 | ret = reg_read(client, MT9V022_AEC_AGC_ENABLE); |
7397bfbe GL |
302 | if (ret >= 0) { |
303 | if (ret & 1) /* Autoexposure */ | |
c078ac18 | 304 | ret = reg_write(client, mt9v022->reg->max_total_shutter_width, |
32536108 | 305 | rect.height + mt9v022->y_skip_top + 43); |
9bb047cd AG |
306 | /* |
307 | * If autoexposure is off, there is no need to set | |
308 | * MT9V022_TOTAL_SHUTTER_WIDTH here. Autoexposure can be off | |
309 | * only if the user has set exposure manually, using the | |
310 | * V4L2_CID_EXPOSURE_AUTO with the value V4L2_EXPOSURE_MANUAL. | |
311 | * In this case the register MT9V022_TOTAL_SHUTTER_WIDTH | |
312 | * already contains the correct value. | |
313 | */ | |
7397bfbe GL |
314 | } |
315 | /* Setup frame format: defaults apart from width and height */ | |
11211641 | 316 | if (!ret) |
6a6c8786 | 317 | ret = reg_write(client, MT9V022_COLUMN_START, rect.left); |
11211641 | 318 | if (!ret) |
6a6c8786 | 319 | ret = reg_write(client, MT9V022_ROW_START, rect.top); |
bff79939 AA |
320 | /* |
321 | * mt9v022: min total row time is 660 columns, min blanking is 43 | |
322 | * mt9v024: min total row time is 690 columns, min blanking is 61 | |
323 | */ | |
324 | if (is_mt9v024(mt9v022->chip_version)) { | |
325 | min_row = 690; | |
326 | min_blank = 61; | |
327 | } else { | |
328 | min_row = 660; | |
329 | min_blank = 43; | |
330 | } | |
11211641 | 331 | if (!ret) |
6cc1eb70 | 332 | ret = v4l2_ctrl_s_ctrl(mt9v022->hblank, |
bff79939 AA |
333 | rect.width > min_row - min_blank ? |
334 | min_blank : min_row - rect.width); | |
11211641 | 335 | if (!ret) |
6cc1eb70 | 336 | ret = v4l2_ctrl_s_ctrl(mt9v022->vblank, 45); |
11211641 | 337 | if (!ret) |
6a6c8786 | 338 | ret = reg_write(client, MT9V022_WINDOW_WIDTH, rect.width); |
11211641 | 339 | if (!ret) |
9538e1c2 | 340 | ret = reg_write(client, MT9V022_WINDOW_HEIGHT, |
32536108 | 341 | rect.height + mt9v022->y_skip_top); |
7397bfbe GL |
342 | |
343 | if (ret < 0) | |
344 | return ret; | |
345 | ||
e26b3144 | 346 | dev_dbg(&client->dev, "Frame %dx%d pixel\n", rect.width, rect.height); |
6a6c8786 GL |
347 | |
348 | mt9v022->rect = rect; | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | static int mt9v022_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) | |
354 | { | |
c4ce6d14 | 355 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
6a6c8786 GL |
356 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
357 | ||
358 | a->c = mt9v022->rect; | |
359 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
364 | static int mt9v022_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) | |
365 | { | |
366 | a->bounds.left = MT9V022_COLUMN_SKIP; | |
367 | a->bounds.top = MT9V022_ROW_SKIP; | |
368 | a->bounds.width = MT9V022_MAX_WIDTH; | |
369 | a->bounds.height = MT9V022_MAX_HEIGHT; | |
370 | a->defrect = a->bounds; | |
371 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
372 | a->pixelaspect.numerator = 1; | |
373 | a->pixelaspect.denominator = 1; | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
da298c6d HV |
378 | static int mt9v022_get_fmt(struct v4l2_subdev *sd, |
379 | struct v4l2_subdev_pad_config *cfg, | |
380 | struct v4l2_subdev_format *format) | |
6a6c8786 | 381 | { |
da298c6d | 382 | struct v4l2_mbus_framefmt *mf = &format->format; |
c4ce6d14 | 383 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
6a6c8786 | 384 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
6a6c8786 | 385 | |
da298c6d HV |
386 | if (format->pad) |
387 | return -EINVAL; | |
388 | ||
760697be GL |
389 | mf->width = mt9v022->rect.width; |
390 | mf->height = mt9v022->rect.height; | |
391 | mf->code = mt9v022->fmt->code; | |
392 | mf->colorspace = mt9v022->fmt->colorspace; | |
393 | mf->field = V4L2_FIELD_NONE; | |
7397bfbe | 394 | |
7397bfbe GL |
395 | return 0; |
396 | } | |
397 | ||
760697be GL |
398 | static int mt9v022_s_fmt(struct v4l2_subdev *sd, |
399 | struct v4l2_mbus_framefmt *mf) | |
09e231b3 | 400 | { |
c4ce6d14 | 401 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
979ea1dd | 402 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
08590b96 GL |
403 | struct v4l2_crop a = { |
404 | .c = { | |
6a6c8786 GL |
405 | .left = mt9v022->rect.left, |
406 | .top = mt9v022->rect.top, | |
760697be GL |
407 | .width = mf->width, |
408 | .height = mf->height, | |
08590b96 | 409 | }, |
09e231b3 | 410 | }; |
6a6c8786 | 411 | int ret; |
09e231b3 | 412 | |
5d28d525 GL |
413 | /* |
414 | * The caller provides a supported format, as verified per call to | |
717fd5b4 | 415 | * .set_fmt(FORMAT_TRY), datawidth is from our supported format list |
5d28d525 | 416 | */ |
760697be | 417 | switch (mf->code) { |
f5fe58fd BB |
418 | case MEDIA_BUS_FMT_Y8_1X8: |
419 | case MEDIA_BUS_FMT_Y10_1X10: | |
6be89daa | 420 | if (mt9v022->model != MT9V022IX7ATM) |
09e231b3 GL |
421 | return -EINVAL; |
422 | break; | |
f5fe58fd BB |
423 | case MEDIA_BUS_FMT_SBGGR8_1X8: |
424 | case MEDIA_BUS_FMT_SBGGR10_1X10: | |
6be89daa | 425 | if (mt9v022->model != MT9V022IX7ATC) |
09e231b3 GL |
426 | return -EINVAL; |
427 | break; | |
09e231b3 GL |
428 | default: |
429 | return -EINVAL; | |
430 | } | |
431 | ||
432 | /* No support for scaling on this camera, just crop. */ | |
6a6c8786 GL |
433 | ret = mt9v022_s_crop(sd, &a); |
434 | if (!ret) { | |
760697be GL |
435 | mf->width = mt9v022->rect.width; |
436 | mf->height = mt9v022->rect.height; | |
437 | mt9v022->fmt = mt9v022_find_datafmt(mf->code, | |
438 | mt9v022->fmts, mt9v022->num_fmts); | |
439 | mf->colorspace = mt9v022->fmt->colorspace; | |
6a6c8786 GL |
440 | } |
441 | ||
442 | return ret; | |
09e231b3 GL |
443 | } |
444 | ||
717fd5b4 HV |
445 | static int mt9v022_set_fmt(struct v4l2_subdev *sd, |
446 | struct v4l2_subdev_pad_config *cfg, | |
447 | struct v4l2_subdev_format *format) | |
7397bfbe | 448 | { |
717fd5b4 | 449 | struct v4l2_mbus_framefmt *mf = &format->format; |
c4ce6d14 | 450 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
32536108 | 451 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
760697be | 452 | const struct mt9v022_datafmt *fmt; |
f5fe58fd BB |
453 | int align = mf->code == MEDIA_BUS_FMT_SBGGR8_1X8 || |
454 | mf->code == MEDIA_BUS_FMT_SBGGR10_1X10; | |
64f5905e | 455 | |
717fd5b4 HV |
456 | if (format->pad) |
457 | return -EINVAL; | |
458 | ||
760697be | 459 | v4l_bound_align_image(&mf->width, MT9V022_MIN_WIDTH, |
6a6c8786 | 460 | MT9V022_MAX_WIDTH, align, |
760697be | 461 | &mf->height, MT9V022_MIN_HEIGHT + mt9v022->y_skip_top, |
32536108 | 462 | MT9V022_MAX_HEIGHT + mt9v022->y_skip_top, align, 0); |
7397bfbe | 463 | |
760697be GL |
464 | fmt = mt9v022_find_datafmt(mf->code, mt9v022->fmts, |
465 | mt9v022->num_fmts); | |
466 | if (!fmt) { | |
467 | fmt = mt9v022->fmt; | |
468 | mf->code = fmt->code; | |
469 | } | |
470 | ||
471 | mf->colorspace = fmt->colorspace; | |
472 | ||
717fd5b4 HV |
473 | if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) |
474 | return mt9v022_s_fmt(sd, mf); | |
475 | cfg->try_fmt = *mf; | |
7397bfbe GL |
476 | return 0; |
477 | } | |
478 | ||
7397bfbe | 479 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
979ea1dd GL |
480 | static int mt9v022_g_register(struct v4l2_subdev *sd, |
481 | struct v4l2_dbg_register *reg) | |
7397bfbe | 482 | { |
c4ce6d14 | 483 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
7397bfbe | 484 | |
6be89daa | 485 | if (reg->reg > 0xff) |
7397bfbe GL |
486 | return -EINVAL; |
487 | ||
aecde8b5 | 488 | reg->size = 2; |
9538e1c2 | 489 | reg->val = reg_read(client, reg->reg); |
7397bfbe GL |
490 | |
491 | if (reg->val > 0xffff) | |
492 | return -EIO; | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
979ea1dd | 497 | static int mt9v022_s_register(struct v4l2_subdev *sd, |
977ba3b1 | 498 | const struct v4l2_dbg_register *reg) |
7397bfbe | 499 | { |
c4ce6d14 | 500 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
7397bfbe | 501 | |
6be89daa | 502 | if (reg->reg > 0xff) |
7397bfbe GL |
503 | return -EINVAL; |
504 | ||
9538e1c2 | 505 | if (reg_write(client, reg->reg, reg->val) < 0) |
7397bfbe GL |
506 | return -EIO; |
507 | ||
508 | return 0; | |
509 | } | |
510 | #endif | |
511 | ||
4ec10bac LP |
512 | static int mt9v022_s_power(struct v4l2_subdev *sd, int on) |
513 | { | |
514 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 515 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
9aea470b | 516 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
4ec10bac | 517 | |
9aea470b | 518 | return soc_camera_set_power(&client->dev, ssdd, mt9v022->clk, on); |
4ec10bac LP |
519 | } |
520 | ||
ab7b50ae | 521 | static int mt9v022_g_volatile_ctrl(struct v4l2_ctrl *ctrl) |
7397bfbe | 522 | { |
ab7b50ae HV |
523 | struct mt9v022 *mt9v022 = container_of(ctrl->handler, |
524 | struct mt9v022, hdl); | |
525 | struct v4l2_subdev *sd = &mt9v022->subdev; | |
c4ce6d14 | 526 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
ab7b50ae HV |
527 | struct v4l2_ctrl *gain = mt9v022->gain; |
528 | struct v4l2_ctrl *exp = mt9v022->exposure; | |
96c75399 | 529 | unsigned long range; |
7397bfbe GL |
530 | int data; |
531 | ||
532 | switch (ctrl->id) { | |
7397bfbe | 533 | case V4L2_CID_AUTOGAIN: |
96c75399 GL |
534 | data = reg_read(client, MT9V022_ANALOG_GAIN); |
535 | if (data < 0) | |
536 | return -EIO; | |
537 | ||
ab7b50ae HV |
538 | range = gain->maximum - gain->minimum; |
539 | gain->val = ((data - 16) * range + 24) / 48 + gain->minimum; | |
540 | return 0; | |
541 | case V4L2_CID_EXPOSURE_AUTO: | |
96c75399 GL |
542 | data = reg_read(client, MT9V022_TOTAL_SHUTTER_WIDTH); |
543 | if (data < 0) | |
544 | return -EIO; | |
545 | ||
ab7b50ae HV |
546 | range = exp->maximum - exp->minimum; |
547 | exp->val = ((data - 1) * range + 239) / 479 + exp->minimum; | |
548 | return 0; | |
6cc1eb70 AG |
549 | case V4L2_CID_HBLANK: |
550 | data = reg_read(client, MT9V022_HORIZONTAL_BLANKING); | |
551 | if (data < 0) | |
552 | return -EIO; | |
553 | ctrl->val = data; | |
554 | return 0; | |
555 | case V4L2_CID_VBLANK: | |
556 | data = reg_read(client, MT9V022_VERTICAL_BLANKING); | |
557 | if (data < 0) | |
558 | return -EIO; | |
559 | ctrl->val = data; | |
560 | return 0; | |
7397bfbe | 561 | } |
ab7b50ae | 562 | return -EINVAL; |
7397bfbe GL |
563 | } |
564 | ||
ab7b50ae | 565 | static int mt9v022_s_ctrl(struct v4l2_ctrl *ctrl) |
7397bfbe | 566 | { |
ab7b50ae HV |
567 | struct mt9v022 *mt9v022 = container_of(ctrl->handler, |
568 | struct mt9v022, hdl); | |
569 | struct v4l2_subdev *sd = &mt9v022->subdev; | |
c4ce6d14 | 570 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
ab7b50ae | 571 | int data; |
7397bfbe GL |
572 | |
573 | switch (ctrl->id) { | |
574 | case V4L2_CID_VFLIP: | |
ab7b50ae | 575 | if (ctrl->val) |
9538e1c2 | 576 | data = reg_set(client, MT9V022_READ_MODE, 0x10); |
7397bfbe | 577 | else |
9538e1c2 | 578 | data = reg_clear(client, MT9V022_READ_MODE, 0x10); |
7397bfbe GL |
579 | if (data < 0) |
580 | return -EIO; | |
ab7b50ae | 581 | return 0; |
7397bfbe | 582 | case V4L2_CID_HFLIP: |
ab7b50ae | 583 | if (ctrl->val) |
9538e1c2 | 584 | data = reg_set(client, MT9V022_READ_MODE, 0x20); |
7397bfbe | 585 | else |
9538e1c2 | 586 | data = reg_clear(client, MT9V022_READ_MODE, 0x20); |
7397bfbe GL |
587 | if (data < 0) |
588 | return -EIO; | |
ab7b50ae HV |
589 | return 0; |
590 | case V4L2_CID_AUTOGAIN: | |
591 | if (ctrl->val) { | |
592 | if (reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0) | |
593 | return -EIO; | |
594 | } else { | |
595 | struct v4l2_ctrl *gain = mt9v022->gain; | |
596 | /* mt9v022 has minimum == default */ | |
597 | unsigned long range = gain->maximum - gain->minimum; | |
96c75399 | 598 | /* Valid values 16 to 64, 32 to 64 must be even. */ |
0d5e8c43 | 599 | unsigned long gain_val = ((gain->val - (s32)gain->minimum) * |
96c75399 | 600 | 48 + range / 2) / range + 16; |
ab7b50ae HV |
601 | |
602 | if (gain_val >= 32) | |
603 | gain_val &= ~1; | |
604 | ||
5d28d525 GL |
605 | /* |
606 | * The user wants to set gain manually, hope, she | |
607 | * knows, what she's doing... Switch AGC off. | |
608 | */ | |
9538e1c2 | 609 | if (reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0) |
7397bfbe GL |
610 | return -EIO; |
611 | ||
96c75399 | 612 | dev_dbg(&client->dev, "Setting gain from %d to %lu\n", |
ab7b50ae HV |
613 | reg_read(client, MT9V022_ANALOG_GAIN), gain_val); |
614 | if (reg_write(client, MT9V022_ANALOG_GAIN, gain_val) < 0) | |
7397bfbe | 615 | return -EIO; |
7397bfbe | 616 | } |
ab7b50ae HV |
617 | return 0; |
618 | case V4L2_CID_EXPOSURE_AUTO: | |
619 | if (ctrl->val == V4L2_EXPOSURE_AUTO) { | |
620 | data = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x1); | |
621 | } else { | |
622 | struct v4l2_ctrl *exp = mt9v022->exposure; | |
623 | unsigned long range = exp->maximum - exp->minimum; | |
0d5e8c43 | 624 | unsigned long shutter = ((exp->val - (s32)exp->minimum) * |
ab7b50ae HV |
625 | 479 + range / 2) / range + 1; |
626 | ||
5d28d525 GL |
627 | /* |
628 | * The user wants to set shutter width manually, hope, | |
629 | * she knows, what she's doing... Switch AEC off. | |
630 | */ | |
ab7b50ae HV |
631 | data = reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x1); |
632 | if (data < 0) | |
7397bfbe | 633 | return -EIO; |
85f8be68 | 634 | dev_dbg(&client->dev, "Shutter width from %d to %lu\n", |
ab7b50ae HV |
635 | reg_read(client, MT9V022_TOTAL_SHUTTER_WIDTH), |
636 | shutter); | |
9538e1c2 | 637 | if (reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, |
ab7b50ae | 638 | shutter) < 0) |
7397bfbe | 639 | return -EIO; |
7397bfbe | 640 | } |
ab7b50ae | 641 | return 0; |
6cc1eb70 AG |
642 | case V4L2_CID_HBLANK: |
643 | if (reg_write(client, MT9V022_HORIZONTAL_BLANKING, | |
644 | ctrl->val) < 0) | |
645 | return -EIO; | |
646 | return 0; | |
647 | case V4L2_CID_VBLANK: | |
648 | if (reg_write(client, MT9V022_VERTICAL_BLANKING, | |
649 | ctrl->val) < 0) | |
650 | return -EIO; | |
651 | return 0; | |
7397bfbe | 652 | } |
ab7b50ae | 653 | return -EINVAL; |
7397bfbe GL |
654 | } |
655 | ||
5d28d525 GL |
656 | /* |
657 | * Interface active, can use i2c. If it fails, it can indeed mean, that | |
658 | * this wasn't our capture interface, so, we wait for the right one | |
659 | */ | |
14178aa5 | 660 | static int mt9v022_video_probe(struct i2c_client *client) |
7397bfbe | 661 | { |
979ea1dd | 662 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
25a34811 | 663 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
7397bfbe GL |
664 | s32 data; |
665 | int ret; | |
e958e27a | 666 | unsigned long flags; |
7397bfbe | 667 | |
4bbc6d52 LP |
668 | ret = mt9v022_s_power(&mt9v022->subdev, 1); |
669 | if (ret < 0) | |
670 | return ret; | |
671 | ||
7397bfbe | 672 | /* Read out the chip version register */ |
9538e1c2 | 673 | data = reg_read(client, MT9V022_CHIP_VERSION); |
7397bfbe | 674 | |
c078ac18 AG |
675 | /* must be 0x1311, 0x1313 or 0x1324 */ |
676 | if (data != 0x1311 && data != 0x1313 && data != 0x1324) { | |
7397bfbe | 677 | ret = -ENODEV; |
85f8be68 | 678 | dev_info(&client->dev, "No MT9V022 found, ID register 0x%x\n", |
7397bfbe GL |
679 | data); |
680 | goto ei2c; | |
681 | } | |
682 | ||
d0bac768 AG |
683 | mt9v022->chip_version = data; |
684 | ||
c078ac18 AG |
685 | mt9v022->reg = is_mt9v024(data) ? &mt9v024_register : |
686 | &mt9v022_register; | |
687 | ||
7397bfbe | 688 | /* Soft reset */ |
9538e1c2 | 689 | ret = reg_write(client, MT9V022_RESET, 1); |
7397bfbe GL |
690 | if (ret < 0) |
691 | goto ei2c; | |
692 | /* 15 clock cycles */ | |
693 | udelay(200); | |
9538e1c2 | 694 | if (reg_read(client, MT9V022_RESET)) { |
85f8be68 | 695 | dev_err(&client->dev, "Resetting MT9V022 failed!\n"); |
40e2e092 GL |
696 | if (ret > 0) |
697 | ret = -EIO; | |
7397bfbe GL |
698 | goto ei2c; |
699 | } | |
700 | ||
701 | /* Set monochrome or colour sensor type */ | |
702 | if (sensor_type && (!strcmp("colour", sensor_type) || | |
703 | !strcmp("color", sensor_type))) { | |
9538e1c2 | 704 | ret = reg_write(client, MT9V022_PIXEL_OPERATION_MODE, 4 | 0x11); |
6be89daa | 705 | mt9v022->model = MT9V022IX7ATC; |
760697be | 706 | mt9v022->fmts = mt9v022_colour_fmts; |
7397bfbe | 707 | } else { |
9538e1c2 | 708 | ret = reg_write(client, MT9V022_PIXEL_OPERATION_MODE, 0x11); |
6be89daa | 709 | mt9v022->model = MT9V022IX7ATM; |
760697be | 710 | mt9v022->fmts = mt9v022_monochrome_fmts; |
7397bfbe GL |
711 | } |
712 | ||
e958e27a | 713 | if (ret < 0) |
40e2e092 | 714 | goto ei2c; |
e958e27a | 715 | |
760697be | 716 | mt9v022->num_fmts = 0; |
e958e27a SH |
717 | |
718 | /* | |
719 | * This is a 10bit sensor, so by default we only allow 10bit. | |
720 | * The platform may support different bus widths due to | |
721 | * different routing of the data lines. | |
722 | */ | |
25a34811 GL |
723 | if (ssdd->query_bus_param) |
724 | flags = ssdd->query_bus_param(ssdd); | |
e958e27a SH |
725 | else |
726 | flags = SOCAM_DATAWIDTH_10; | |
727 | ||
728 | if (flags & SOCAM_DATAWIDTH_10) | |
760697be | 729 | mt9v022->num_fmts++; |
e958e27a | 730 | else |
760697be | 731 | mt9v022->fmts++; |
e958e27a SH |
732 | |
733 | if (flags & SOCAM_DATAWIDTH_8) | |
760697be | 734 | mt9v022->num_fmts++; |
e958e27a | 735 | |
760697be | 736 | mt9v022->fmt = &mt9v022->fmts[0]; |
6a6c8786 | 737 | |
85f8be68 | 738 | dev_info(&client->dev, "Detected a MT9V022 chip ID %x, %s sensor\n", |
6be89daa | 739 | data, mt9v022->model == MT9V022IX7ATM ? |
7397bfbe GL |
740 | "monochrome" : "colour"); |
741 | ||
a4c56fd8 GL |
742 | ret = mt9v022_init(client); |
743 | if (ret < 0) | |
744 | dev_err(&client->dev, "Failed to initialise the camera\n"); | |
745 | ||
7397bfbe | 746 | ei2c: |
4bbc6d52 | 747 | mt9v022_s_power(&mt9v022->subdev, 0); |
7397bfbe GL |
748 | return ret; |
749 | } | |
750 | ||
32536108 GL |
751 | static int mt9v022_g_skip_top_lines(struct v4l2_subdev *sd, u32 *lines) |
752 | { | |
c4ce6d14 | 753 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
32536108 GL |
754 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
755 | ||
756 | *lines = mt9v022->y_skip_top; | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
ab7b50ae HV |
761 | static const struct v4l2_ctrl_ops mt9v022_ctrl_ops = { |
762 | .g_volatile_ctrl = mt9v022_g_volatile_ctrl, | |
763 | .s_ctrl = mt9v022_s_ctrl, | |
764 | }; | |
765 | ||
979ea1dd | 766 | static struct v4l2_subdev_core_ops mt9v022_subdev_core_ops = { |
979ea1dd GL |
767 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
768 | .g_register = mt9v022_g_register, | |
769 | .s_register = mt9v022_s_register, | |
770 | #endif | |
4ec10bac | 771 | .s_power = mt9v022_s_power, |
979ea1dd GL |
772 | }; |
773 | ||
ebcff5fc HV |
774 | static int mt9v022_enum_mbus_code(struct v4l2_subdev *sd, |
775 | struct v4l2_subdev_pad_config *cfg, | |
776 | struct v4l2_subdev_mbus_code_enum *code) | |
760697be | 777 | { |
c4ce6d14 | 778 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
760697be GL |
779 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
780 | ||
ebcff5fc | 781 | if (code->pad || code->index >= mt9v022->num_fmts) |
760697be GL |
782 | return -EINVAL; |
783 | ||
ebcff5fc | 784 | code->code = mt9v022->fmts[code->index].code; |
760697be GL |
785 | return 0; |
786 | } | |
787 | ||
e8e2c70c GL |
788 | static int mt9v022_g_mbus_config(struct v4l2_subdev *sd, |
789 | struct v4l2_mbus_config *cfg) | |
790 | { | |
791 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 792 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
e8e2c70c GL |
793 | |
794 | cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE | | |
795 | V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING | | |
796 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
797 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
798 | V4L2_MBUS_DATA_ACTIVE_HIGH; | |
799 | cfg->type = V4L2_MBUS_PARALLEL; | |
25a34811 | 800 | cfg->flags = soc_camera_apply_board_flags(ssdd, cfg); |
e8e2c70c GL |
801 | |
802 | return 0; | |
803 | } | |
804 | ||
805 | static int mt9v022_s_mbus_config(struct v4l2_subdev *sd, | |
806 | const struct v4l2_mbus_config *cfg) | |
807 | { | |
808 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 809 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
e8e2c70c | 810 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
25a34811 | 811 | unsigned long flags = soc_camera_apply_board_flags(ssdd, cfg); |
443f483a | 812 | unsigned int bps = soc_mbus_get_fmtdesc(mt9v022->fmt->code)->bits_per_sample; |
e8e2c70c GL |
813 | int ret; |
814 | u16 pixclk = 0; | |
815 | ||
25a34811 GL |
816 | if (ssdd->set_bus_param) { |
817 | ret = ssdd->set_bus_param(ssdd, 1 << (bps - 1)); | |
e8e2c70c GL |
818 | if (ret) |
819 | return ret; | |
820 | } else if (bps != 10) { | |
821 | /* | |
822 | * Without board specific bus width settings we only support the | |
823 | * sensors native bus width | |
824 | */ | |
825 | return -EINVAL; | |
826 | } | |
827 | ||
828 | if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) | |
829 | pixclk |= 0x10; | |
830 | ||
831 | if (!(flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)) | |
832 | pixclk |= 0x1; | |
833 | ||
834 | if (!(flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)) | |
835 | pixclk |= 0x2; | |
836 | ||
c078ac18 | 837 | ret = reg_write(client, mt9v022->reg->pixclk_fv_lv, pixclk); |
e8e2c70c GL |
838 | if (ret < 0) |
839 | return ret; | |
840 | ||
841 | if (!(flags & V4L2_MBUS_MASTER)) | |
842 | mt9v022->chip_control &= ~0x8; | |
843 | ||
844 | ret = reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control); | |
845 | if (ret < 0) | |
846 | return ret; | |
847 | ||
848 | dev_dbg(&client->dev, "Calculated pixclk 0x%x, chip control 0x%x\n", | |
849 | pixclk, mt9v022->chip_control); | |
850 | ||
851 | return 0; | |
852 | } | |
853 | ||
979ea1dd GL |
854 | static struct v4l2_subdev_video_ops mt9v022_subdev_video_ops = { |
855 | .s_stream = mt9v022_s_stream, | |
08590b96 | 856 | .s_crop = mt9v022_s_crop, |
6a6c8786 GL |
857 | .g_crop = mt9v022_g_crop, |
858 | .cropcap = mt9v022_cropcap, | |
e8e2c70c GL |
859 | .g_mbus_config = mt9v022_g_mbus_config, |
860 | .s_mbus_config = mt9v022_s_mbus_config, | |
979ea1dd GL |
861 | }; |
862 | ||
368a53df | 863 | static const struct v4l2_subdev_sensor_ops mt9v022_subdev_sensor_ops = { |
32536108 GL |
864 | .g_skip_top_lines = mt9v022_g_skip_top_lines, |
865 | }; | |
866 | ||
ebcff5fc HV |
867 | static const struct v4l2_subdev_pad_ops mt9v022_subdev_pad_ops = { |
868 | .enum_mbus_code = mt9v022_enum_mbus_code, | |
da298c6d | 869 | .get_fmt = mt9v022_get_fmt, |
717fd5b4 | 870 | .set_fmt = mt9v022_set_fmt, |
ebcff5fc HV |
871 | }; |
872 | ||
979ea1dd GL |
873 | static struct v4l2_subdev_ops mt9v022_subdev_ops = { |
874 | .core = &mt9v022_subdev_core_ops, | |
875 | .video = &mt9v022_subdev_video_ops, | |
32536108 | 876 | .sensor = &mt9v022_subdev_sensor_ops, |
ebcff5fc | 877 | .pad = &mt9v022_subdev_pad_ops, |
979ea1dd GL |
878 | }; |
879 | ||
d2653e92 JD |
880 | static int mt9v022_probe(struct i2c_client *client, |
881 | const struct i2c_device_id *did) | |
7397bfbe GL |
882 | { |
883 | struct mt9v022 *mt9v022; | |
25a34811 | 884 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
7397bfbe | 885 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
daf16bab | 886 | struct mt9v022_platform_data *pdata; |
7397bfbe GL |
887 | int ret; |
888 | ||
25a34811 | 889 | if (!ssdd) { |
7397bfbe GL |
890 | dev_err(&client->dev, "MT9V022 driver needs platform data\n"); |
891 | return -EINVAL; | |
892 | } | |
893 | ||
894 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { | |
895 | dev_warn(&adapter->dev, | |
896 | "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); | |
897 | return -EIO; | |
898 | } | |
899 | ||
70e176a5 | 900 | mt9v022 = devm_kzalloc(&client->dev, sizeof(struct mt9v022), GFP_KERNEL); |
7397bfbe GL |
901 | if (!mt9v022) |
902 | return -ENOMEM; | |
903 | ||
25a34811 | 904 | pdata = ssdd->drv_priv; |
979ea1dd | 905 | v4l2_i2c_subdev_init(&mt9v022->subdev, client, &mt9v022_subdev_ops); |
ab7b50ae HV |
906 | v4l2_ctrl_handler_init(&mt9v022->hdl, 6); |
907 | v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
908 | V4L2_CID_VFLIP, 0, 1, 1, 0); | |
909 | v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
910 | V4L2_CID_HFLIP, 0, 1, 1, 0); | |
911 | mt9v022->autogain = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
912 | V4L2_CID_AUTOGAIN, 0, 1, 1, 1); | |
913 | mt9v022->gain = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
914 | V4L2_CID_GAIN, 0, 127, 1, 64); | |
915 | ||
916 | /* | |
917 | * Simulated autoexposure. If enabled, we calculate shutter width | |
918 | * ourselves in the driver based on vertical blanking and frame width | |
919 | */ | |
920 | mt9v022->autoexposure = v4l2_ctrl_new_std_menu(&mt9v022->hdl, | |
921 | &mt9v022_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0, | |
922 | V4L2_EXPOSURE_AUTO); | |
923 | mt9v022->exposure = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
924 | V4L2_CID_EXPOSURE, 1, 255, 1, 255); | |
925 | ||
6cc1eb70 AG |
926 | mt9v022->hblank = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, |
927 | V4L2_CID_HBLANK, MT9V022_HORIZONTAL_BLANKING_MIN, | |
928 | MT9V022_HORIZONTAL_BLANKING_MAX, 1, | |
929 | MT9V022_HORIZONTAL_BLANKING_DEF); | |
930 | ||
931 | mt9v022->vblank = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
932 | V4L2_CID_VBLANK, MT9V022_VERTICAL_BLANKING_MIN, | |
933 | MT9V022_VERTICAL_BLANKING_MAX, 1, | |
934 | MT9V022_VERTICAL_BLANKING_DEF); | |
935 | ||
ab7b50ae HV |
936 | mt9v022->subdev.ctrl_handler = &mt9v022->hdl; |
937 | if (mt9v022->hdl.error) { | |
938 | int err = mt9v022->hdl.error; | |
939 | ||
6cc1eb70 | 940 | dev_err(&client->dev, "control initialisation err %d\n", err); |
ab7b50ae HV |
941 | return err; |
942 | } | |
943 | v4l2_ctrl_auto_cluster(2, &mt9v022->autoexposure, | |
944 | V4L2_EXPOSURE_MANUAL, true); | |
945 | v4l2_ctrl_auto_cluster(2, &mt9v022->autogain, 0, true); | |
979ea1dd | 946 | |
7397bfbe | 947 | mt9v022->chip_control = MT9V022_CHIP_CONTROL_DEFAULT; |
7397bfbe | 948 | |
96c75399 | 949 | /* |
b6f50b49 AG |
950 | * On some platforms the first read out line is corrupted. |
951 | * Workaround it by skipping if indicated by platform data. | |
96c75399 | 952 | */ |
b6f50b49 | 953 | mt9v022->y_skip_top = pdata ? pdata->y_skip_top : 0; |
6a6c8786 GL |
954 | mt9v022->rect.left = MT9V022_COLUMN_SKIP; |
955 | mt9v022->rect.top = MT9V022_ROW_SKIP; | |
956 | mt9v022->rect.width = MT9V022_MAX_WIDTH; | |
957 | mt9v022->rect.height = MT9V022_MAX_HEIGHT; | |
958 | ||
9aea470b GL |
959 | mt9v022->clk = v4l2_clk_get(&client->dev, "mclk"); |
960 | if (IS_ERR(mt9v022->clk)) { | |
961 | ret = PTR_ERR(mt9v022->clk); | |
962 | goto eclkget; | |
963 | } | |
964 | ||
14178aa5 | 965 | ret = mt9v022_video_probe(client); |
9aea470b GL |
966 | if (ret) { |
967 | v4l2_clk_put(mt9v022->clk); | |
968 | eclkget: | |
ab7b50ae | 969 | v4l2_ctrl_handler_free(&mt9v022->hdl); |
9aea470b | 970 | } |
7397bfbe | 971 | |
7397bfbe GL |
972 | return ret; |
973 | } | |
974 | ||
975 | static int mt9v022_remove(struct i2c_client *client) | |
976 | { | |
979ea1dd | 977 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
25a34811 | 978 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
7397bfbe | 979 | |
9aea470b | 980 | v4l2_clk_put(mt9v022->clk); |
ab7b50ae | 981 | v4l2_device_unregister_subdev(&mt9v022->subdev); |
25a34811 GL |
982 | if (ssdd->free_bus) |
983 | ssdd->free_bus(ssdd); | |
ab7b50ae | 984 | v4l2_ctrl_handler_free(&mt9v022->hdl); |
7397bfbe GL |
985 | |
986 | return 0; | |
987 | } | |
3760f736 JD |
988 | static const struct i2c_device_id mt9v022_id[] = { |
989 | { "mt9v022", 0 }, | |
990 | { } | |
991 | }; | |
992 | MODULE_DEVICE_TABLE(i2c, mt9v022_id); | |
993 | ||
7397bfbe GL |
994 | static struct i2c_driver mt9v022_i2c_driver = { |
995 | .driver = { | |
996 | .name = "mt9v022", | |
997 | }, | |
998 | .probe = mt9v022_probe, | |
999 | .remove = mt9v022_remove, | |
3760f736 | 1000 | .id_table = mt9v022_id, |
7397bfbe GL |
1001 | }; |
1002 | ||
c6e8d86f | 1003 | module_i2c_driver(mt9v022_i2c_driver); |
7397bfbe GL |
1004 | |
1005 | MODULE_DESCRIPTION("Micron MT9V022 Camera driver"); | |
1006 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1007 | MODULE_LICENSE("GPL"); |