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Merge remote-tracking branch 'selinux/next'
[deliverable/linux.git] / drivers / media / i2c / soc_camera / ov2640.c
CommitLineData
3153ac9c
AP		 1/*
2 * ov2640 Camera Driver
3 *
4 * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
5 *
6 * Based on ov772x, ov9640 drivers and previous non merged implementations.
7 *
8 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
9 * Copyright (C) 2006, OmniVision
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/i2c.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
4e65172f 21#include <linux/gpio.h>
d3633329 22#include <linux/gpio/consumer.h>
4e65172f 23#include <linux/of_gpio.h>
95d20109 24#include <linux/v4l2-mediabus.h>
3153ac9c 25#include <linux/videodev2.h>
d463003b 26
3153ac9c 27#include <media/soc_camera.h>
9aea470b 28#include <media/v4l2-clk.h>
d463003b 29#include <media/v4l2-subdev.h>
f026671d 30#include <media/v4l2-ctrls.h>
650b1815 31#include <media/v4l2-image-sizes.h>
3153ac9c
AP		 32
33#define VAL_SET(x, mask, rshift, lshift) \
34 ((((x) >> rshift) & mask) << lshift)
35/*
36 * DSP registers
37 * register offset for BANK_SEL == BANK_SEL_DSP
38 */
39#define R_BYPASS 0x05 /* Bypass DSP */
40#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */
41#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */
42#define QS 0x44 /* Quantization Scale Factor */
43#define CTRLI 0x50
44#define CTRLI_LP_DP 0x80
45#define CTRLI_ROUND 0x40
46#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3)
47#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0)
48#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */
49#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
50#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */
51#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
52#define XOFFL 0x53 /* OFFSET_X[7:0] */
53#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
54#define YOFFL 0x54 /* OFFSET_Y[7:0] */
55#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
56#define VHYX 0x55 /* Offset and size completion */
57#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7)
58#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3)
59#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4)
60#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0)
61#define DPRP 0x56
62#define TEST 0x57 /* Horizontal size completion */
63#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7)
64#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */
65#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0)
66#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */
67#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0)
68#define ZMHH 0x5C /* Zoom: Speed and H&W completion */
69#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4)
70#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2)
71#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0)
72#define BPADDR 0x7C /* SDE Indirect Register Access: Address */
73#define BPDATA 0x7D /* SDE Indirect Register Access: Data */
74#define CTRL2 0x86 /* DSP Module enable 2 */
75#define CTRL2_DCW_EN 0x20
76#define CTRL2_SDE_EN 0x10
77#define CTRL2_UV_ADJ_EN 0x08
78#define CTRL2_UV_AVG_EN 0x04
79#define CTRL2_CMX_EN 0x01
80#define CTRL3 0x87 /* DSP Module enable 3 */
81#define CTRL3_BPC_EN 0x80
82#define CTRL3_WPC_EN 0x40
83#define SIZEL 0x8C /* Image Size Completion */
84#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
85#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3)
86#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0)
87#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */
88#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
89#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */
90#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
91#define CTRL0 0xC2 /* DSP Module enable 0 */
92#define CTRL0_AEC_EN 0x80
93#define CTRL0_AEC_SEL 0x40
94#define CTRL0_STAT_SEL 0x20
95#define CTRL0_VFIRST 0x10
96#define CTRL0_YUV422 0x08
97#define CTRL0_YUV_EN 0x04
98#define CTRL0_RGB_EN 0x02
99#define CTRL0_RAW_EN 0x01
100#define CTRL1 0xC3 /* DSP Module enable 1 */
101#define CTRL1_CIP 0x80
102#define CTRL1_DMY 0x40
103#define CTRL1_RAW_GMA 0x20
104#define CTRL1_DG 0x10
105#define CTRL1_AWB 0x08
106#define CTRL1_AWB_GAIN 0x04
107#define CTRL1_LENC 0x02
108#define CTRL1_PRE 0x01
109#define R_DVP_SP 0xD3 /* DVP output speed control */
110#define R_DVP_SP_AUTO_MODE 0x80
111#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
112 * = sysclk (48)/(2*[6:0]) (RAW);*/
113#define IMAGE_MODE 0xDA /* Image Output Format Select */
114#define IMAGE_MODE_Y8_DVP_EN 0x40
115#define IMAGE_MODE_JPEG_EN 0x10
116#define IMAGE_MODE_YUV422 0x00
117#define IMAGE_MODE_RAW10 0x04 /* (DVP) */
118#define IMAGE_MODE_RGB565 0x08
119#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output
120 * mode (0 for HREF is same as sensor) */
121#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP
122 * 1: Low byte first UYVY (C2[4] =0)
123 * VYUY (C2[4] =1)
124 * 0: High byte first YUYV (C2[4]=0)
125 * YVYU (C2[4] = 1) */
126#define RESET 0xE0 /* Reset */
127#define RESET_MICROC 0x40
128#define RESET_SCCB 0x20
129#define RESET_JPEG 0x10
130#define RESET_DVP 0x04
131#define RESET_IPU 0x02
132#define RESET_CIF 0x01
133#define REGED 0xED /* Register ED */
134#define REGED_CLK_OUT_DIS 0x10
135#define MS_SP 0xF0 /* SCCB Master Speed */
136#define SS_ID 0xF7 /* SCCB Slave ID */
137#define SS_CTRL 0xF8 /* SCCB Slave Control */
138#define SS_CTRL_ADD_AUTO_INC 0x20
139#define SS_CTRL_EN 0x08
140#define SS_CTRL_DELAY_CLK 0x04
141#define SS_CTRL_ACC_EN 0x02
142#define SS_CTRL_SEN_PASS_THR 0x01
143#define MC_BIST 0xF9 /* Microcontroller misc register */
144#define MC_BIST_RESET 0x80 /* Microcontroller Reset */
145#define MC_BIST_BOOT_ROM_SEL 0x40
146#define MC_BIST_12KB_SEL 0x20
147#define MC_BIST_12KB_MASK 0x30
148#define MC_BIST_512KB_SEL 0x08
149#define MC_BIST_512KB_MASK 0x0C
150#define MC_BIST_BUSY_BIT_R 0x02
151#define MC_BIST_MC_RES_ONE_SH_W 0x02
152#define MC_BIST_LAUNCH 0x01
153#define BANK_SEL 0xFF /* Register Bank Select */
154#define BANK_SEL_DSP 0x00
155#define BANK_SEL_SENS 0x01
156
157/*
158 * Sensor registers
159 * register offset for BANK_SEL == BANK_SEL_SENS
160 */
161#define GAIN 0x00 /* AGC - Gain control gain setting */
162#define COM1 0x03 /* Common control 1 */
163#define COM1_1_DUMMY_FR 0x40
164#define COM1_3_DUMMY_FR 0x80
165#define COM1_7_DUMMY_FR 0xC0
166#define COM1_VWIN_LSB_UXGA 0x0F
167#define COM1_VWIN_LSB_SVGA 0x0A
168#define COM1_VWIN_LSB_CIF 0x06
169#define REG04 0x04 /* Register 04 */
170#define REG04_DEF 0x20 /* Always set */
171#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */
172#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */
173#define REG04_VREF_EN 0x10
174#define REG04_HREF_EN 0x08
175#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0)
176#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */
177#define COM2 0x09 /* Common control 2 */
178#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
179 /* Output drive capability */
180#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */
181#define PID 0x0A /* Product ID Number MSB */
182#define VER 0x0B /* Product ID Number LSB */
183#define COM3 0x0C /* Common control 3 */
184#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */
185#define COM3_BAND_AUTO 0x02 /* Auto Banding */
186#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the
187 * snapshot sequence*/
188#define AEC 0x10 /* AEC[9:2] Exposure Value */
189#define CLKRC 0x11 /* Internal clock */
190#define CLKRC_EN 0x80
191#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */
192#define COM7 0x12 /* Common control 7 */
193#define COM7_SRST 0x80 /* Initiates system reset. All registers are
194 * set to factory default values after which
195 * the chip resumes normal operation */
196#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */
197#define COM7_RES_SVGA 0x40 /* SVGA */
198#define COM7_RES_CIF 0x20 /* CIF */
199#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */
200#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */
201#define COM8 0x13 /* Common control 8 */
202#define COM8_DEF 0xC0 /* Banding filter ON/OFF */
203#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */
204#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
205#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
206#define COM9 0x14 /* Common control 9
207 * Automatic gain ceiling - maximum AGC value [7:5]*/
208#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */
209#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */
210#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */
211#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */
212#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */
213#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */
214#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */
215#define COM10 0x15 /* Common control 10 */
216#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */
217#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of
218 * PCLK (user can latch data at the next
219 * falling edge of PCLK).
220 * 0 otherwise. */
221#define COM10_HREF_INV 0x08 /* Invert HREF polarity:
222 * HREF negative for valid data*/
223#define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */
224#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */
225#define HEND 0x18 /* Horizontal Window end MSB 8 bit */
226#define VSTART 0x19 /* Vertical Window start MSB 8 bit */
227#define VEND 0x1A /* Vertical Window end MSB 8 bit */
228#define MIDH 0x1C /* Manufacturer ID byte - high */
229#define MIDL 0x1D /* Manufacturer ID byte - low */
230#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
231#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
232#define VV 0x26 /* AGC/AEC Fast mode operating region */
233#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4)
234#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0)
235#define REG2A 0x2A /* Dummy pixel insert MSB */
236#define FRARL 0x2B /* Dummy pixel insert LSB */
237#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
238#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */
239#define YAVG 0x2F /* Y/G Channel Average value */
240#define REG32 0x32 /* Common Control 32 */
241#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */
242#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */
243#define ARCOM2 0x34 /* Zoom: Horizontal start point */
244#define REG45 0x45 /* Register 45 */
245#define FLL 0x46 /* Frame Length Adjustment LSBs */
246#define FLH 0x47 /* Frame Length Adjustment MSBs */
247#define COM19 0x48 /* Zoom: Vertical start point */
248#define ZOOMS 0x49 /* Zoom: Vertical start point */
249#define COM22 0x4B /* Flash light control */
250#define COM25 0x4E /* For Banding operations */
251#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */
252#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */
253#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */
254#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */
255#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */
256#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */
257#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */
258#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */
259
260/*
261 * ID
262 */
263#define MANUFACTURER_ID 0x7FA2
264#define PID_OV2640 0x2642
265#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
266
267/*
268 * Struct
269 */
270struct regval_list {
271 u8 reg_num;
272 u8 value;
273};
274
3153ac9c
AP		 275struct ov2640_win_size {
276 char *name;
650b1815
JW		 277 u32 width;
278 u32 height;
3153ac9c
AP		 279 const struct regval_list *regs;
280};
281
282
283struct ov2640_priv {
284 struct v4l2_subdev subdev;
f026671d 285 struct v4l2_ctrl_handler hdl;
f5fe58fd 286 u32 cfmt_code;
9aea470b 287 struct v4l2_clk *clk;
3153ac9c 288 const struct ov2640_win_size *win;
4e65172f
JW		 289
290 struct soc_camera_subdev_desc ssdd_dt;
291 struct gpio_desc *resetb_gpio;
292 struct gpio_desc *pwdn_gpio;
3153ac9c
AP		 293};
294
295/*
296 * Registers settings
297 */
298
299#define ENDMARKER { 0xff, 0xff }
300
301static const struct regval_list ov2640_init_regs[] = {
302 { BANK_SEL, BANK_SEL_DSP },
303 { 0x2c, 0xff },
304 { 0x2e, 0xdf },
305 { BANK_SEL, BANK_SEL_SENS },
306 { 0x3c, 0x32 },
307 { CLKRC, CLKRC_DIV_SET(1) },
308 { COM2, COM2_OCAP_Nx_SET(3) },
309 { REG04, REG04_DEF | REG04_HREF_EN },
310 { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN },
311 { COM9, COM9_AGC_GAIN_8x | 0x08},
312 { 0x2c, 0x0c },
313 { 0x33, 0x78 },
314 { 0x3a, 0x33 },
315 { 0x3b, 0xfb },
316 { 0x3e, 0x00 },
317 { 0x43, 0x11 },
318 { 0x16, 0x10 },
319 { 0x39, 0x02 },
320 { 0x35, 0x88 },
321 { 0x22, 0x0a },
322 { 0x37, 0x40 },
323 { 0x23, 0x00 },
324 { ARCOM2, 0xa0 },
325 { 0x06, 0x02 },
326 { 0x06, 0x88 },
327 { 0x07, 0xc0 },
328 { 0x0d, 0xb7 },
329 { 0x0e, 0x01 },
330 { 0x4c, 0x00 },
331 { 0x4a, 0x81 },
332 { 0x21, 0x99 },
333 { AEW, 0x40 },
334 { AEB, 0x38 },
335 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) },
336 { 0x5c, 0x00 },
337 { 0x63, 0x00 },
338 { FLL, 0x22 },
339 { COM3, 0x38 | COM3_BAND_AUTO },
340 { REG5D, 0x55 },
341 { REG5E, 0x7d },
342 { REG5F, 0x7d },
343 { REG60, 0x55 },
344 { HISTO_LOW, 0x70 },
345 { HISTO_HIGH, 0x80 },
346 { 0x7c, 0x05 },
347 { 0x20, 0x80 },
348 { 0x28, 0x30 },
349 { 0x6c, 0x00 },
350 { 0x6d, 0x80 },
351 { 0x6e, 0x00 },
352 { 0x70, 0x02 },
353 { 0x71, 0x94 },
354 { 0x73, 0xc1 },
355 { 0x3d, 0x34 },
356 { COM7, COM7_RES_UXGA | COM7_ZOOM_EN },
357 { 0x5a, 0x57 },
358 { BD50, 0xbb },
359 { BD60, 0x9c },
360 { BANK_SEL, BANK_SEL_DSP },
361 { 0xe5, 0x7f },
362 { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
363 { 0x41, 0x24 },
364 { RESET, RESET_JPEG | RESET_DVP },
365 { 0x76, 0xff },
366 { 0x33, 0xa0 },
367 { 0x42, 0x20 },
368 { 0x43, 0x18 },
369 { 0x4c, 0x00 },
370 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
371 { 0x88, 0x3f },
372 { 0xd7, 0x03 },
373 { 0xd9, 0x10 },
374 { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 },
375 { 0xc8, 0x08 },
376 { 0xc9, 0x80 },
377 { BPADDR, 0x00 },
378 { BPDATA, 0x00 },
379 { BPADDR, 0x03 },
380 { BPDATA, 0x48 },
381 { BPDATA, 0x48 },
382 { BPADDR, 0x08 },
383 { BPDATA, 0x20 },
384 { BPDATA, 0x10 },
385 { BPDATA, 0x0e },
386 { 0x90, 0x00 },
387 { 0x91, 0x0e },
388 { 0x91, 0x1a },
389 { 0x91, 0x31 },
390 { 0x91, 0x5a },
391 { 0x91, 0x69 },
392 { 0x91, 0x75 },
393 { 0x91, 0x7e },
394 { 0x91, 0x88 },
395 { 0x91, 0x8f },
396 { 0x91, 0x96 },
397 { 0x91, 0xa3 },
398 { 0x91, 0xaf },
399 { 0x91, 0xc4 },
400 { 0x91, 0xd7 },
401 { 0x91, 0xe8 },
402 { 0x91, 0x20 },
403 { 0x92, 0x00 },
404 { 0x93, 0x06 },
405 { 0x93, 0xe3 },
406 { 0x93, 0x03 },
407 { 0x93, 0x03 },
408 { 0x93, 0x00 },
409 { 0x93, 0x02 },
410 { 0x93, 0x00 },
411 { 0x93, 0x00 },
412 { 0x93, 0x00 },
413 { 0x93, 0x00 },
414 { 0x93, 0x00 },
415 { 0x93, 0x00 },
416 { 0x93, 0x00 },
417 { 0x96, 0x00 },
418 { 0x97, 0x08 },
419 { 0x97, 0x19 },
420 { 0x97, 0x02 },
421 { 0x97, 0x0c },
422 { 0x97, 0x24 },
423 { 0x97, 0x30 },
424 { 0x97, 0x28 },
425 { 0x97, 0x26 },
426 { 0x97, 0x02 },
427 { 0x97, 0x98 },
428 { 0x97, 0x80 },
429 { 0x97, 0x00 },
430 { 0x97, 0x00 },
431 { 0xa4, 0x00 },
432 { 0xa8, 0x00 },
433 { 0xc5, 0x11 },
434 { 0xc6, 0x51 },
435 { 0xbf, 0x80 },
436 { 0xc7, 0x10 },
437 { 0xb6, 0x66 },
438 { 0xb8, 0xA5 },
439 { 0xb7, 0x64 },
440 { 0xb9, 0x7C },
441 { 0xb3, 0xaf },
442 { 0xb4, 0x97 },
443 { 0xb5, 0xFF },
444 { 0xb0, 0xC5 },
445 { 0xb1, 0x94 },
446 { 0xb2, 0x0f },
447 { 0xc4, 0x5c },
448 { 0xa6, 0x00 },
449 { 0xa7, 0x20 },
450 { 0xa7, 0xd8 },
451 { 0xa7, 0x1b },
452 { 0xa7, 0x31 },
453 { 0xa7, 0x00 },
454 { 0xa7, 0x18 },
455 { 0xa7, 0x20 },
456 { 0xa7, 0xd8 },
457 { 0xa7, 0x19 },
458 { 0xa7, 0x31 },
459 { 0xa7, 0x00 },
460 { 0xa7, 0x18 },
461 { 0xa7, 0x20 },
462 { 0xa7, 0xd8 },
463 { 0xa7, 0x19 },
464 { 0xa7, 0x31 },
465 { 0xa7, 0x00 },
466 { 0xa7, 0x18 },
467 { 0x7f, 0x00 },
468 { 0xe5, 0x1f },
469 { 0xe1, 0x77 },
470 { 0xdd, 0x7f },
471 { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
472 ENDMARKER,
473};
474
475/*
476 * Register settings for window size
477 * The preamble, setup the internal DSP to input an UXGA (1600x1200) image.
478 * Then the different zooming configurations will setup the output image size.
479 */
480static const struct regval_list ov2640_size_change_preamble_regs[] = {
481 { BANK_SEL, BANK_SEL_DSP },
482 { RESET, RESET_DVP },
650b1815
JW		 483 { HSIZE8, HSIZE8_SET(UXGA_WIDTH) },
484 { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) },
3153ac9c
AP		 485 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
486 CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
650b1815
JW		 487 { HSIZE, HSIZE_SET(UXGA_WIDTH) },
488 { VSIZE, VSIZE_SET(UXGA_HEIGHT) },
3153ac9c
AP		 489 { XOFFL, XOFFL_SET(0) },
490 { YOFFL, YOFFL_SET(0) },
650b1815 491 { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) |
3153ac9c 492 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)},
650b1815 493 { TEST, TEST_HSIZE_SET(UXGA_WIDTH) },
3153ac9c
AP		 494 ENDMARKER,
495};
496
497#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \
498 { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \
499 CTRLI_H_DIV_SET(h_div)}, \
500 { ZMOW, ZMOW_OUTW_SET(x) }, \
501 { ZMOH, ZMOH_OUTH_SET(y) }, \
502 { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \
503 { R_DVP_SP, pclk_div }, \
504 { RESET, 0x00}
505
506static const struct regval_list ov2640_qcif_regs[] = {
650b1815 507 PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4),
3153ac9c
AP		 508 ENDMARKER,
509};
510
511static const struct regval_list ov2640_qvga_regs[] = {
650b1815 512 PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4),
3153ac9c
AP		 513 ENDMARKER,
514};
515
516static const struct regval_list ov2640_cif_regs[] = {
650b1815 517 PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8),
3153ac9c
AP		 518 ENDMARKER,
519};
520
521static const struct regval_list ov2640_vga_regs[] = {
650b1815 522 PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2),
3153ac9c
AP		 523 ENDMARKER,
524};
525
526static const struct regval_list ov2640_svga_regs[] = {
650b1815 527 PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2),
3153ac9c
AP		 528 ENDMARKER,
529};
530
531static const struct regval_list ov2640_xga_regs[] = {
650b1815 532 PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2),
3153ac9c
AP		 533 { CTRLI, 0x00},
534 ENDMARKER,
535};
536
537static const struct regval_list ov2640_sxga_regs[] = {
650b1815 538 PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2),
3153ac9c
AP		 539 { CTRLI, 0x00},
540 { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE },
541 ENDMARKER,
542};
543
544static const struct regval_list ov2640_uxga_regs[] = {
650b1815 545 PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0),
3153ac9c
AP		 546 { CTRLI, 0x00},
547 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
548 ENDMARKER,
549};
550
551#define OV2640_SIZE(n, w, h, r) \
552 {.name = n, .width = w , .height = h, .regs = r }
553
554static const struct ov2640_win_size ov2640_supported_win_sizes[] = {
650b1815
JW		 555 OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs),
556 OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs),
557 OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs),
558 OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs),
559 OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs),
560 OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs),
561 OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs),
562 OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs),
3153ac9c
AP		 563};
564
565/*
566 * Register settings for pixel formats
567 */
568static const struct regval_list ov2640_format_change_preamble_regs[] = {
569 { BANK_SEL, BANK_SEL_DSP },
570 { R_BYPASS, R_BYPASS_USE_DSP },
571 ENDMARKER,
572};
573
d1a49eac
FS		 574static const struct regval_list ov2640_yuyv_regs[] = {
575 { IMAGE_MODE, IMAGE_MODE_YUV422 },
576 { 0xd7, 0x03 },
577 { 0x33, 0xa0 },
578 { 0xe5, 0x1f },
579 { 0xe1, 0x67 },
580 { RESET, 0x00 },
581 { R_BYPASS, R_BYPASS_USE_DSP },
582 ENDMARKER,
583};
584
585static const struct regval_list ov2640_uyvy_regs[] = {
3153ac9c 586 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 },
d1a49eac 587 { 0xd7, 0x01 },
3153ac9c
AP		 588 { 0x33, 0xa0 },
589 { 0xe1, 0x67 },
590 { RESET, 0x00 },
591 { R_BYPASS, R_BYPASS_USE_DSP },
592 ENDMARKER,
593};
594
d1a49eac
FS		 595static const struct regval_list ov2640_rgb565_be_regs[] = {
596 { IMAGE_MODE, IMAGE_MODE_RGB565 },
597 { 0xd7, 0x03 },
598 { RESET, 0x00 },
599 { R_BYPASS, R_BYPASS_USE_DSP },
600 ENDMARKER,
601};
602
603static const struct regval_list ov2640_rgb565_le_regs[] = {
3153ac9c
AP		 604 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 },
605 { 0xd7, 0x03 },
606 { RESET, 0x00 },
607 { R_BYPASS, R_BYPASS_USE_DSP },
608 ENDMARKER,
609};
610
f5fe58fd
BB		 611static u32 ov2640_codes[] = {
612 MEDIA_BUS_FMT_YUYV8_2X8,
613 MEDIA_BUS_FMT_UYVY8_2X8,
614 MEDIA_BUS_FMT_RGB565_2X8_BE,
615 MEDIA_BUS_FMT_RGB565_2X8_LE,
3153ac9c
AP		 616};
617
3153ac9c
AP		 618/*
619 * General functions
620 */
621static struct ov2640_priv *to_ov2640(const struct i2c_client *client)
622{
623 return container_of(i2c_get_clientdata(client), struct ov2640_priv,
624 subdev);
625}
626
627static int ov2640_write_array(struct i2c_client *client,
628 const struct regval_list *vals)
629{
630 int ret;
631
632 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) {
633 ret = i2c_smbus_write_byte_data(client,
634 vals->reg_num, vals->value);
635 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
636 vals->reg_num, vals->value);
637
638 if (ret < 0)
639 return ret;
640 vals++;
641 }
642 return 0;
643}
644
645static int ov2640_mask_set(struct i2c_client *client,
646 u8 reg, u8 mask, u8 set)
647{
648 s32 val = i2c_smbus_read_byte_data(client, reg);
649 if (val < 0)
650 return val;
651
652 val &= ~mask;
653 val |= set & mask;
654
655 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
656
657 return i2c_smbus_write_byte_data(client, reg, val);
658}
659
660static int ov2640_reset(struct i2c_client *client)
661{
662 int ret;
663 const struct regval_list reset_seq[] = {
664 {BANK_SEL, BANK_SEL_SENS},
665 {COM7, COM7_SRST},
666 ENDMARKER,
667 };
668
669 ret = ov2640_write_array(client, reset_seq);
670 if (ret)
671 goto err;
672
673 msleep(5);
674err:
675 dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret);
676 return ret;
677}
678
679/*
680 * soc_camera_ops functions
681 */
682static int ov2640_s_stream(struct v4l2_subdev *sd, int enable)
683{
684 return 0;
685}
686
f026671d 687static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl)
3153ac9c 688{
f026671d
HV		 689 struct v4l2_subdev *sd =
690 &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev;
3153ac9c 691 struct i2c_client *client = v4l2_get_subdevdata(sd);
3153ac9c 692 u8 val;
a52eb6c0
FS		 693 int ret;
694
695 ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
696 if (ret < 0)
697 return ret;
3153ac9c
AP		 698
699 switch (ctrl->id) {
700 case V4L2_CID_VFLIP:
f026671d
HV		 701 val = ctrl->val ? REG04_VFLIP_IMG : 0x00;
702 return ov2640_mask_set(client, REG04, REG04_VFLIP_IMG, val);
3153ac9c 703 case V4L2_CID_HFLIP:
f026671d
HV		 704 val = ctrl->val ? REG04_HFLIP_IMG : 0x00;
705 return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val);
3153ac9c
AP		 706 }
707
f026671d 708 return -EINVAL;
3153ac9c
AP		 709}
710
3153ac9c
AP		 711#ifdef CONFIG_VIDEO_ADV_DEBUG
712static int ov2640_g_register(struct v4l2_subdev *sd,
713 struct v4l2_dbg_register *reg)
714{
715 struct i2c_client *client = v4l2_get_subdevdata(sd);
716 int ret;
717
718 reg->size = 1;
719 if (reg->reg > 0xff)
720 return -EINVAL;
721
722 ret = i2c_smbus_read_byte_data(client, reg->reg);
723 if (ret < 0)
724 return ret;
725
726 reg->val = ret;
727
728 return 0;
729}
730
731static int ov2640_s_register(struct v4l2_subdev *sd,
977ba3b1 732 const struct v4l2_dbg_register *reg)
3153ac9c
AP		 733{
734 struct i2c_client *client = v4l2_get_subdevdata(sd);
735
736 if (reg->reg > 0xff ||
737 reg->val > 0xff)
738 return -EINVAL;
739
740 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
741}
742#endif
743
4ec10bac
LP		 744static int ov2640_s_power(struct v4l2_subdev *sd, int on)
745{
746 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 747 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
9aea470b 748 struct ov2640_priv *priv = to_ov2640(client);
4ec10bac 749
9aea470b 750 return soc_camera_set_power(&client->dev, ssdd, priv->clk, on);
4ec10bac
LP		 751}
752
3153ac9c
AP		 753/* Select the nearest higher resolution for capture */
754static const struct ov2640_win_size *ov2640_select_win(u32 *width, u32 *height)
755{
756 int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1;
757
758 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) {
759 if (ov2640_supported_win_sizes[i].width >= *width &&
760 ov2640_supported_win_sizes[i].height >= *height) {
761 *width = ov2640_supported_win_sizes[i].width;
762 *height = ov2640_supported_win_sizes[i].height;
763 return &ov2640_supported_win_sizes[i];
764 }
765 }
766
767 *width = ov2640_supported_win_sizes[default_size].width;
768 *height = ov2640_supported_win_sizes[default_size].height;
769 return &ov2640_supported_win_sizes[default_size];
770}
771
772static int ov2640_set_params(struct i2c_client *client, u32 *width, u32 *height,
f5fe58fd 773 u32 code)
3153ac9c
AP		 774{
775 struct ov2640_priv *priv = to_ov2640(client);
776 const struct regval_list *selected_cfmt_regs;
777 int ret;
778
779 /* select win */
780 priv->win = ov2640_select_win(width, height);
781
782 /* select format */
783 priv->cfmt_code = 0;
784 switch (code) {
f5fe58fd 785 case MEDIA_BUS_FMT_RGB565_2X8_BE:
d1a49eac
FS		 786 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__);
787 selected_cfmt_regs = ov2640_rgb565_be_regs;
788 break;
f5fe58fd 789 case MEDIA_BUS_FMT_RGB565_2X8_LE:
d1a49eac
FS		 790 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__);
791 selected_cfmt_regs = ov2640_rgb565_le_regs;
792 break;
f5fe58fd 793 case MEDIA_BUS_FMT_YUYV8_2X8:
d1a49eac
FS		 794 dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__);
795 selected_cfmt_regs = ov2640_yuyv_regs;
3153ac9c
AP		 796 break;
797 default:
f5fe58fd 798 case MEDIA_BUS_FMT_UYVY8_2X8:
d1a49eac
FS		 799 dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__);
800 selected_cfmt_regs = ov2640_uyvy_regs;
3153ac9c
AP		 801 }
802
803 /* reset hardware */
804 ov2640_reset(client);
805
806 /* initialize the sensor with default data */
807 dev_dbg(&client->dev, "%s: Init default", __func__);
808 ret = ov2640_write_array(client, ov2640_init_regs);
809 if (ret < 0)
810 goto err;
811
812 /* select preamble */
813 dev_dbg(&client->dev, "%s: Set size to %s", __func__, priv->win->name);
814 ret = ov2640_write_array(client, ov2640_size_change_preamble_regs);
815 if (ret < 0)
816 goto err;
817
818 /* set size win */
819 ret = ov2640_write_array(client, priv->win->regs);
820 if (ret < 0)
821 goto err;
822
823 /* cfmt preamble */
824 dev_dbg(&client->dev, "%s: Set cfmt", __func__);
825 ret = ov2640_write_array(client, ov2640_format_change_preamble_regs);
826 if (ret < 0)
827 goto err;
828
829 /* set cfmt */
830 ret = ov2640_write_array(client, selected_cfmt_regs);
831 if (ret < 0)
832 goto err;
833
834 priv->cfmt_code = code;
835 *width = priv->win->width;
836 *height = priv->win->height;
837
838 return 0;
839
840err:
841 dev_err(&client->dev, "%s: Error %d", __func__, ret);
842 ov2640_reset(client);
843 priv->win = NULL;
844
845 return ret;
846}
847
da298c6d
HV		 848static int ov2640_get_fmt(struct v4l2_subdev *sd,
849 struct v4l2_subdev_pad_config *cfg,
850 struct v4l2_subdev_format *format)
3153ac9c 851{
da298c6d 852 struct v4l2_mbus_framefmt *mf = &format->format;
3153ac9c
AP		 853 struct i2c_client *client = v4l2_get_subdevdata(sd);
854 struct ov2640_priv *priv = to_ov2640(client);
855
da298c6d
HV		 856 if (format->pad)
857 return -EINVAL;
858
3153ac9c 859 if (!priv->win) {
650b1815 860 u32 width = SVGA_WIDTH, height = SVGA_HEIGHT;
f9859839 861 priv->win = ov2640_select_win(&width, &height);
f5fe58fd 862 priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
3153ac9c
AP		 863 }
864
865 mf->width = priv->win->width;
866 mf->height = priv->win->height;
867 mf->code = priv->cfmt_code;
868
869 switch (mf->code) {
f5fe58fd
BB		 870 case MEDIA_BUS_FMT_RGB565_2X8_BE:
871 case MEDIA_BUS_FMT_RGB565_2X8_LE:
3153ac9c
AP		 872 mf->colorspace = V4L2_COLORSPACE_SRGB;
873 break;
874 default:
f5fe58fd
BB		 875 case MEDIA_BUS_FMT_YUYV8_2X8:
876 case MEDIA_BUS_FMT_UYVY8_2X8:
3153ac9c
AP		 877 mf->colorspace = V4L2_COLORSPACE_JPEG;
878 }
879 mf->field = V4L2_FIELD_NONE;
880
881 return 0;
882}
883
717fd5b4
HV		 884static int ov2640_set_fmt(struct v4l2_subdev *sd,
885 struct v4l2_subdev_pad_config *cfg,
886 struct v4l2_subdev_format *format)
3153ac9c 887{
717fd5b4 888 struct v4l2_mbus_framefmt *mf = &format->format;
3153ac9c 889 struct i2c_client *client = v4l2_get_subdevdata(sd);
3153ac9c 890
717fd5b4
HV		 891 if (format->pad)
892 return -EINVAL;
3153ac9c 893
3153ac9c 894 /*
ba400892 895 * select suitable win, but don't store it
3153ac9c 896 */
ba400892 897 ov2640_select_win(&mf->width, &mf->height);
3153ac9c
AP		 898
899 mf->field = V4L2_FIELD_NONE;
900
901 switch (mf->code) {
f5fe58fd
BB		 902 case MEDIA_BUS_FMT_RGB565_2X8_BE:
903 case MEDIA_BUS_FMT_RGB565_2X8_LE:
3153ac9c
AP		 904 mf->colorspace = V4L2_COLORSPACE_SRGB;
905 break;
906 default:
f5fe58fd
BB		 907 mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
908 case MEDIA_BUS_FMT_YUYV8_2X8:
909 case MEDIA_BUS_FMT_UYVY8_2X8:
3153ac9c
AP		 910 mf->colorspace = V4L2_COLORSPACE_JPEG;
911 }
912
717fd5b4
HV		 913 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
914 return ov2640_set_params(client, &mf->width,
915 &mf->height, mf->code);
916 cfg->try_fmt = *mf;
3153ac9c
AP		 917 return 0;
918}
919
ebcff5fc
HV		 920static int ov2640_enum_mbus_code(struct v4l2_subdev *sd,
921 struct v4l2_subdev_pad_config *cfg,
922 struct v4l2_subdev_mbus_code_enum *code)
3153ac9c 923{
ebcff5fc 924 if (code->pad || code->index >= ARRAY_SIZE(ov2640_codes))
3153ac9c
AP		 925 return -EINVAL;
926
ebcff5fc 927 code->code = ov2640_codes[code->index];
3153ac9c
AP		 928 return 0;
929}
930
10d5509c
HV		 931static int ov2640_get_selection(struct v4l2_subdev *sd,
932 struct v4l2_subdev_pad_config *cfg,
933 struct v4l2_subdev_selection *sel)
3153ac9c 934{
10d5509c
HV		 935 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
936 return -EINVAL;
3153ac9c 937
10d5509c
HV		 938 switch (sel->target) {
939 case V4L2_SEL_TGT_CROP_BOUNDS:
940 case V4L2_SEL_TGT_CROP_DEFAULT:
941 case V4L2_SEL_TGT_CROP:
942 sel->r.left = 0;
943 sel->r.top = 0;
944 sel->r.width = UXGA_WIDTH;
945 sel->r.height = UXGA_HEIGHT;
946 return 0;
947 default:
948 return -EINVAL;
949 }
3153ac9c
AP		 950}
951
14178aa5 952static int ov2640_video_probe(struct i2c_client *client)
3153ac9c
AP		 953{
954 struct ov2640_priv *priv = to_ov2640(client);
955 u8 pid, ver, midh, midl;
956 const char *devname;
957 int ret;
958
4bbc6d52
LP		 959 ret = ov2640_s_power(&priv->subdev, 1);
960 if (ret < 0)
961 return ret;
962
3153ac9c
AP		 963 /*
964 * check and show product ID and manufacturer ID
965 */
966 i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
967 pid = i2c_smbus_read_byte_data(client, PID);
968 ver = i2c_smbus_read_byte_data(client, VER);
969 midh = i2c_smbus_read_byte_data(client, MIDH);
970 midl = i2c_smbus_read_byte_data(client, MIDL);
971
972 switch (VERSION(pid, ver)) {
973 case PID_OV2640:
974 devname = "ov2640";
3153ac9c
AP		 975 break;
976 default:
977 dev_err(&client->dev,
978 "Product ID error %x:%x\n", pid, ver);
979 ret = -ENODEV;
4bbc6d52 980 goto done;
3153ac9c
AP		 981 }
982
983 dev_info(&client->dev,
984 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
985 devname, pid, ver, midh, midl);
986
4bbc6d52 987 ret = v4l2_ctrl_handler_setup(&priv->hdl);
3153ac9c 988
4bbc6d52
LP		 989done:
990 ov2640_s_power(&priv->subdev, 0);
3153ac9c
AP		 991 return ret;
992}
993
f026671d
HV		 994static const struct v4l2_ctrl_ops ov2640_ctrl_ops = {
995 .s_ctrl = ov2640_s_ctrl,
3153ac9c
AP		 996};
997
998static struct v4l2_subdev_core_ops ov2640_subdev_core_ops = {
3153ac9c
AP		 999#ifdef CONFIG_VIDEO_ADV_DEBUG
1000 .g_register = ov2640_g_register,
1001 .s_register = ov2640_s_register,
1002#endif
4ec10bac 1003 .s_power = ov2640_s_power,
3153ac9c
AP		 1004};
1005
d463003b
GL		 1006static int ov2640_g_mbus_config(struct v4l2_subdev *sd,
1007 struct v4l2_mbus_config *cfg)
1008{
1009 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 1010 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
d463003b
GL		 1011
1012 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
1013 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1014 V4L2_MBUS_DATA_ACTIVE_HIGH;
1015 cfg->type = V4L2_MBUS_PARALLEL;
25a34811 1016 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
d463003b
GL		 1017
1018 return 0;
1019}
1020
3153ac9c
AP		 1021static struct v4l2_subdev_video_ops ov2640_subdev_video_ops = {
1022 .s_stream = ov2640_s_stream,
d463003b 1023 .g_mbus_config = ov2640_g_mbus_config,
3153ac9c
AP		 1024};
1025
ebcff5fc
HV		 1026static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = {
1027 .enum_mbus_code = ov2640_enum_mbus_code,
10d5509c 1028 .get_selection = ov2640_get_selection,
da298c6d 1029 .get_fmt = ov2640_get_fmt,
717fd5b4 1030 .set_fmt = ov2640_set_fmt,
ebcff5fc
HV		 1031};
1032
3153ac9c
AP		 1033static struct v4l2_subdev_ops ov2640_subdev_ops = {
1034 .core = &ov2640_subdev_core_ops,
1035 .video = &ov2640_subdev_video_ops,
ebcff5fc 1036 .pad = &ov2640_subdev_pad_ops,
3153ac9c
AP		 1037};
1038
4e65172f
JW		 1039/* OF probe functions */
1040static int ov2640_hw_power(struct device *dev, int on)
1041{
1042 struct i2c_client *client = to_i2c_client(dev);
1043 struct ov2640_priv *priv = to_ov2640(client);
1044
1045 dev_dbg(&client->dev, "%s: %s the camera\n",
1046 __func__, on ? "ENABLE" : "DISABLE");
1047
1048 if (priv->pwdn_gpio)
1049 gpiod_direction_output(priv->pwdn_gpio, !on);
1050
1051 return 0;
1052}
1053
1054static int ov2640_hw_reset(struct device *dev)
1055{
1056 struct i2c_client *client = to_i2c_client(dev);
1057 struct ov2640_priv *priv = to_ov2640(client);
1058
1059 if (priv->resetb_gpio) {
1060 /* Active the resetb pin to perform a reset pulse */
1061 gpiod_direction_output(priv->resetb_gpio, 1);
1062 usleep_range(3000, 5000);
1063 gpiod_direction_output(priv->resetb_gpio, 0);
1064 }
1065
1066 return 0;
1067}
1068
1069static int ov2640_probe_dt(struct i2c_client *client,
1070 struct ov2640_priv *priv)
1071{
1072 /* Request the reset GPIO deasserted */
1073 priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
1074 GPIOD_OUT_LOW);
1075 if (!priv->resetb_gpio)
1076 dev_dbg(&client->dev, "resetb gpio is not assigned!\n");
1077 else if (IS_ERR(priv->resetb_gpio))
1078 return PTR_ERR(priv->resetb_gpio);
1079
1080 /* Request the power down GPIO asserted */
1081 priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
1082 GPIOD_OUT_HIGH);
1083 if (!priv->pwdn_gpio)
1084 dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
1085 else if (IS_ERR(priv->pwdn_gpio))
1086 return PTR_ERR(priv->pwdn_gpio);
1087
1088 /* Initialize the soc_camera_subdev_desc */
1089 priv->ssdd_dt.power = ov2640_hw_power;
1090 priv->ssdd_dt.reset = ov2640_hw_reset;
1091 client->dev.platform_data = &priv->ssdd_dt;
1092
1093 return 0;
1094}
1095
3153ac9c
AP		 1096/*
1097 * i2c_driver functions
1098 */
1099static int ov2640_probe(struct i2c_client *client,
1100 const struct i2c_device_id *did)
1101{
14178aa5 1102 struct ov2640_priv *priv;
25a34811 1103 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
14178aa5
GL		 1104 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1105 int ret;
3153ac9c 1106
3153ac9c
AP		 1107 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1108 dev_err(&adapter->dev,
1109 "OV2640: I2C-Adapter doesn't support SMBUS\n");
1110 return -EIO;
1111 }
1112
70e176a5 1113 priv = devm_kzalloc(&client->dev, sizeof(struct ov2640_priv), GFP_KERNEL);
3153ac9c
AP		 1114 if (!priv) {
1115 dev_err(&adapter->dev,
1116 "Failed to allocate memory for private data!\n");
1117 return -ENOMEM;
1118 }
1119
4e65172f 1120 priv->clk = v4l2_clk_get(&client->dev, "xvclk");
f180ebae
JW		 1121 if (IS_ERR(priv->clk))
1122 return -EPROBE_DEFER;
1123
4e65172f
JW		 1124 if (!ssdd && !client->dev.of_node) {
1125 dev_err(&client->dev, "Missing platform_data for driver\n");
1126 ret = -EINVAL;
1127 goto err_clk;
1128 }
1129
1130 if (!ssdd) {
1131 ret = ov2640_probe_dt(client, priv);
1132 if (ret)
1133 goto err_clk;
1134 }
1135
3153ac9c 1136 v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops);
f026671d
HV		 1137 v4l2_ctrl_handler_init(&priv->hdl, 2);
1138 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1139 V4L2_CID_VFLIP, 0, 1, 1, 0);
1140 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1141 V4L2_CID_HFLIP, 0, 1, 1, 0);
1142 priv->subdev.ctrl_handler = &priv->hdl;
f180ebae
JW		 1143 if (priv->hdl.error) {
1144 ret = priv->hdl.error;
1145 goto err_clk;
9aea470b
GL		 1146 }
1147
14178aa5 1148 ret = ov2640_video_probe(client);
f180ebae
JW		 1149 if (ret < 0)
1150 goto err_videoprobe;
3153ac9c 1151
f180ebae
JW		 1152 ret = v4l2_async_register_subdev(&priv->subdev);
1153 if (ret < 0)
1154 goto err_videoprobe;
1155
1156 dev_info(&adapter->dev, "OV2640 Probed\n");
1157
1158 return 0;
1159
1160err_videoprobe:
1161 v4l2_ctrl_handler_free(&priv->hdl);
1162err_clk:
1163 v4l2_clk_put(priv->clk);
3153ac9c
AP		 1164 return ret;
1165}
1166
1167static int ov2640_remove(struct i2c_client *client)
1168{
1169 struct ov2640_priv *priv = to_ov2640(client);
3153ac9c 1170
f180ebae 1171 v4l2_async_unregister_subdev(&priv->subdev);
9aea470b 1172 v4l2_clk_put(priv->clk);
f026671d
HV		 1173 v4l2_device_unregister_subdev(&priv->subdev);
1174 v4l2_ctrl_handler_free(&priv->hdl);
3153ac9c
AP		 1175 return 0;
1176}
1177
1178static const struct i2c_device_id ov2640_id[] = {
1179 { "ov2640", 0 },
1180 { }
1181};
1182MODULE_DEVICE_TABLE(i2c, ov2640_id);
1183
4e65172f
JW		 1184static const struct of_device_id ov2640_of_match[] = {
1185 {.compatible = "ovti,ov2640", },
1186 {},
1187};
1188MODULE_DEVICE_TABLE(of, ov2640_of_match);
1189
3153ac9c
AP		 1190static struct i2c_driver ov2640_i2c_driver = {
1191 .driver = {
1192 .name = "ov2640",
4e65172f 1193 .of_match_table = of_match_ptr(ov2640_of_match),
3153ac9c
AP		 1194 },
1195 .probe = ov2640_probe,
1196 .remove = ov2640_remove,
1197 .id_table = ov2640_id,
1198};
1199
c6e8d86f 1200module_i2c_driver(ov2640_i2c_driver);
3153ac9c
AP		 1201
1202MODULE_DESCRIPTION("SoC Camera driver for Omni Vision 2640 sensor");
1203MODULE_AUTHOR("Alberto Panizzo");
1204MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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