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Merge remote-tracking branch 'iommu/next'
[deliverable/linux.git] / drivers / media / i2c / soc_camera / ov6650.c
CommitLineData
2f6e2404
JK		 1/*
2 * V4L2 SoC Camera driver for OmniVision OV6650 Camera Sensor
3 *
4 * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
5 *
6 * Based on OmniVision OV96xx Camera Driver
7 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
8 *
9 * Based on ov772x camera driver:
10 * Copyright (C) 2008 Renesas Solutions Corp.
11 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
12 *
13 * Based on ov7670 and soc_camera_platform driver,
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
15 * Copyright (C) 2008 Magnus Damm
16 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
17 *
18 * Hardware specific bits initialy based on former work by Matt Callow
19 * drivers/media/video/omap/sensor_ov6650.c
20 * Copyright (C) 2006 Matt Callow
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 */
26
27#include <linux/bitops.h>
28#include <linux/delay.h>
29#include <linux/i2c.h>
30#include <linux/slab.h>
95d20109 31#include <linux/v4l2-mediabus.h>
7a707b89 32#include <linux/module.h>
2f6e2404
JK		 33
34#include <media/soc_camera.h>
9aea470b 35#include <media/v4l2-clk.h>
afd9690c 36#include <media/v4l2-ctrls.h>
2f6e2404 37
2f6e2404
JK		 38/* Register definitions */
39#define REG_GAIN 0x00 /* range 00 - 3F */
40#define REG_BLUE 0x01
41#define REG_RED 0x02
42#define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
43#define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
44
45#define REG_BRT 0x06
46
47#define REG_PIDH 0x0a
48#define REG_PIDL 0x0b
49
50#define REG_AECH 0x10
51#define REG_CLKRC 0x11 /* Data Format and Internal Clock */
52 /* [7:6] Input system clock (MHz)*/
53 /* 00=8, 01=12, 10=16, 11=24 */
54 /* [5:0]: Internal Clock Pre-Scaler */
55#define REG_COMA 0x12 /* [7] Reset */
56#define REG_COMB 0x13
57#define REG_COMC 0x14
58#define REG_COMD 0x15
59#define REG_COML 0x16
60#define REG_HSTRT 0x17
61#define REG_HSTOP 0x18
62#define REG_VSTRT 0x19
63#define REG_VSTOP 0x1a
64#define REG_PSHFT 0x1b
65#define REG_MIDH 0x1c
66#define REG_MIDL 0x1d
67#define REG_HSYNS 0x1e
68#define REG_HSYNE 0x1f
69#define REG_COME 0x20
70#define REG_YOFF 0x21
71#define REG_UOFF 0x22
72#define REG_VOFF 0x23
73#define REG_AEW 0x24
74#define REG_AEB 0x25
75#define REG_COMF 0x26
76#define REG_COMG 0x27
77#define REG_COMH 0x28
78#define REG_COMI 0x29
79
80#define REG_FRARL 0x2b
81#define REG_COMJ 0x2c
82#define REG_COMK 0x2d
83#define REG_AVGY 0x2e
84#define REG_REF0 0x2f
85#define REG_REF1 0x30
86#define REG_REF2 0x31
87#define REG_FRAJH 0x32
88#define REG_FRAJL 0x33
89#define REG_FACT 0x34
90#define REG_L1AEC 0x35
91#define REG_AVGU 0x36
92#define REG_AVGV 0x37
93
94#define REG_SPCB 0x60
95#define REG_SPCC 0x61
96#define REG_GAM1 0x62
97#define REG_GAM2 0x63
98#define REG_GAM3 0x64
99#define REG_SPCD 0x65
100
101#define REG_SPCE 0x68
102#define REG_ADCL 0x69
103
104#define REG_RMCO 0x6c
105#define REG_GMCO 0x6d
106#define REG_BMCO 0x6e
107
108
109/* Register bits, values, etc. */
110#define OV6650_PIDH 0x66 /* high byte of product ID number */
111#define OV6650_PIDL 0x50 /* low byte of product ID number */
112#define OV6650_MIDH 0x7F /* high byte of mfg ID */
113#define OV6650_MIDL 0xA2 /* low byte of mfg ID */
114
115#define DEF_GAIN 0x00
116#define DEF_BLUE 0x80
117#define DEF_RED 0x80
118
119#define SAT_SHIFT 4
120#define SAT_MASK (0xf << SAT_SHIFT)
121#define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
122
123#define HUE_EN BIT(5)
124#define HUE_MASK 0x1f
125#define DEF_HUE 0x10
126#define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
127
128#define DEF_AECH 0x4D
129
130#define CLKRC_6MHz 0x00
131#define CLKRC_12MHz 0x40
132#define CLKRC_16MHz 0x80
133#define CLKRC_24MHz 0xc0
134#define CLKRC_DIV_MASK 0x3f
135#define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
136
137#define COMA_RESET BIT(7)
138#define COMA_QCIF BIT(5)
139#define COMA_RAW_RGB BIT(4)
140#define COMA_RGB BIT(3)
141#define COMA_BW BIT(2)
142#define COMA_WORD_SWAP BIT(1)
143#define COMA_BYTE_SWAP BIT(0)
144#define DEF_COMA 0x00
145
146#define COMB_FLIP_V BIT(7)
147#define COMB_FLIP_H BIT(5)
148#define COMB_BAND_FILTER BIT(4)
149#define COMB_AWB BIT(2)
150#define COMB_AGC BIT(1)
151#define COMB_AEC BIT(0)
152#define DEF_COMB 0x5f
153
154#define COML_ONE_CHANNEL BIT(7)
155
156#define DEF_HSTRT 0x24
157#define DEF_HSTOP 0xd4
158#define DEF_VSTRT 0x04
159#define DEF_VSTOP 0x94
160
161#define COMF_HREF_LOW BIT(4)
162
163#define COMJ_PCLK_RISING BIT(4)
164#define COMJ_VSYNC_HIGH BIT(0)
165
166/* supported resolutions */
167#define W_QCIF (DEF_HSTOP - DEF_HSTRT)
168#define W_CIF (W_QCIF << 1)
169#define H_QCIF (DEF_VSTOP - DEF_VSTRT)
170#define H_CIF (H_QCIF << 1)
171
172#define FRAME_RATE_MAX 30
173
174
175struct ov6650_reg {
176 u8 reg;
177 u8 val;
178};
179
180struct ov6650 {
181 struct v4l2_subdev subdev;
afd9690c
HV		 182 struct v4l2_ctrl_handler hdl;
183 struct {
184 /* exposure/autoexposure cluster */
185 struct v4l2_ctrl *autoexposure;
186 struct v4l2_ctrl *exposure;
187 };
188 struct {
189 /* gain/autogain cluster */
190 struct v4l2_ctrl *autogain;
191 struct v4l2_ctrl *gain;
192 };
193 struct {
194 /* blue/red/autowhitebalance cluster */
195 struct v4l2_ctrl *autowb;
196 struct v4l2_ctrl *blue;
197 struct v4l2_ctrl *red;
198 };
9aea470b 199 struct v4l2_clk *clk;
2f6e2404
JK		 200 bool half_scale; /* scale down output by 2 */
201 struct v4l2_rect rect; /* sensor cropping window */
202 unsigned long pclk_limit; /* from host */
203 unsigned long pclk_max; /* from resolution and format */
204 struct v4l2_fract tpf; /* as requested with s_parm */
f5fe58fd 205 u32 code;
2f6e2404
JK		 206 enum v4l2_colorspace colorspace;
207};
208
209
f5fe58fd
BB		 210static u32 ov6650_codes[] = {
211 MEDIA_BUS_FMT_YUYV8_2X8,
212 MEDIA_BUS_FMT_UYVY8_2X8,
213 MEDIA_BUS_FMT_YVYU8_2X8,
214 MEDIA_BUS_FMT_VYUY8_2X8,
215 MEDIA_BUS_FMT_SBGGR8_1X8,
216 MEDIA_BUS_FMT_Y8_1X8,
2f6e2404
JK		 217};
218
2f6e2404
JK		 219/* read a register */
220static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
221{
222 int ret;
223 u8 data = reg;
224 struct i2c_msg msg = {
225 .addr = client->addr,
226 .flags = 0,
227 .len = 1,
228 .buf = &data,
229 };
230
231 ret = i2c_transfer(client->adapter, &msg, 1);
232 if (ret < 0)
233 goto err;
234
235 msg.flags = I2C_M_RD;
236 ret = i2c_transfer(client->adapter, &msg, 1);
237 if (ret < 0)
238 goto err;
239
240 *val = data;
241 return 0;
242
243err:
244 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
245 return ret;
246}
247
248/* write a register */
249static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
250{
251 int ret;
252 unsigned char data[2] = { reg, val };
253 struct i2c_msg msg = {
254 .addr = client->addr,
255 .flags = 0,
256 .len = 2,
257 .buf = data,
258 };
259
260 ret = i2c_transfer(client->adapter, &msg, 1);
261 udelay(100);
262
263 if (ret < 0) {
264 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
265 return ret;
266 }
267 return 0;
268}
269
270
271/* Read a register, alter its bits, write it back */
272static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
273{
274 u8 val;
275 int ret;
276
277 ret = ov6650_reg_read(client, reg, &val);
278 if (ret) {
279 dev_err(&client->dev,
280 "[Read]-Modify-Write of register 0x%02x failed!\n",
281 reg);
282 return ret;
283 }
284
285 val &= ~mask;
286 val |= set;
287
288 ret = ov6650_reg_write(client, reg, val);
289 if (ret)
290 dev_err(&client->dev,
291 "Read-Modify-[Write] of register 0x%02x failed!\n",
292 reg);
293
294 return ret;
295}
296
297static struct ov6650 *to_ov6650(const struct i2c_client *client)
298{
299 return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
300}
301
302/* Start/Stop streaming from the device */
303static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
304{
305 return 0;
306}
307
2f6e2404 308/* Get status of additional camera capabilities */
afd9690c 309static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
2f6e2404 310{
afd9690c
HV		 311 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
312 struct v4l2_subdev *sd = &priv->subdev;
2f6e2404 313 struct i2c_client *client = v4l2_get_subdevdata(sd);
afd9690c 314 uint8_t reg, reg2;
2e56d933 315 int ret;
2f6e2404
JK		 316
317 switch (ctrl->id) {
318 case V4L2_CID_AUTOGAIN:
afd9690c
HV		 319 ret = ov6650_reg_read(client, REG_GAIN, &reg);
320 if (!ret)
321 priv->gain->val = reg;
322 return ret;
2f6e2404 323 case V4L2_CID_AUTO_WHITE_BALANCE:
afd9690c
HV		 324 ret = ov6650_reg_read(client, REG_BLUE, &reg);
325 if (!ret)
326 ret = ov6650_reg_read(client, REG_RED, &reg2);
327 if (!ret) {
328 priv->blue->val = reg;
329 priv->red->val = reg2;
2f6e2404 330 }
afd9690c 331 return ret;
2f6e2404 332 case V4L2_CID_EXPOSURE_AUTO:
afd9690c
HV		 333 ret = ov6650_reg_read(client, REG_AECH, &reg);
334 if (!ret)
335 priv->exposure->val = reg;
336 return ret;
2f6e2404 337 }
afd9690c 338 return -EINVAL;
2f6e2404
JK		 339}
340
341/* Set status of additional camera capabilities */
afd9690c 342static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
2f6e2404 343{
afd9690c
HV		 344 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
345 struct v4l2_subdev *sd = &priv->subdev;
2f6e2404 346 struct i2c_client *client = v4l2_get_subdevdata(sd);
2e56d933 347 int ret;
2f6e2404
JK		 348
349 switch (ctrl->id) {
350 case V4L2_CID_AUTOGAIN:
351 ret = ov6650_reg_rmw(client, REG_COMB,
afd9690c
HV		 352 ctrl->val ? COMB_AGC : 0, COMB_AGC);
353 if (!ret && !ctrl->val)
354 ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
355 return ret;
2f6e2404
JK		 356 case V4L2_CID_AUTO_WHITE_BALANCE:
357 ret = ov6650_reg_rmw(client, REG_COMB,
afd9690c
HV		 358 ctrl->val ? COMB_AWB : 0, COMB_AWB);
359 if (!ret && !ctrl->val) {
360 ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
361 if (!ret)
362 ret = ov6650_reg_write(client, REG_RED,
363 priv->red->val);
364 }
365 return ret;
2f6e2404 366 case V4L2_CID_SATURATION:
afd9690c 367 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
2f6e2404 368 SAT_MASK);
2f6e2404 369 case V4L2_CID_HUE:
afd9690c 370 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
2f6e2404 371 HUE_MASK);
2f6e2404 372 case V4L2_CID_BRIGHTNESS:
afd9690c 373 return ov6650_reg_write(client, REG_BRT, ctrl->val);
2f6e2404 374 case V4L2_CID_EXPOSURE_AUTO:
2e56d933
JK		 375 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
376 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
afd9690c
HV		 377 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
378 ret = ov6650_reg_write(client, REG_AECH,
379 priv->exposure->val);
380 return ret;
2f6e2404 381 case V4L2_CID_GAMMA:
afd9690c 382 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
2f6e2404 383 case V4L2_CID_VFLIP:
afd9690c
HV		 384 return ov6650_reg_rmw(client, REG_COMB,
385 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
2f6e2404 386 case V4L2_CID_HFLIP:
afd9690c
HV		 387 return ov6650_reg_rmw(client, REG_COMB,
388 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
2f6e2404
JK		 389 }
390
afd9690c 391 return -EINVAL;
2f6e2404
JK		 392}
393
2f6e2404
JK		 394#ifdef CONFIG_VIDEO_ADV_DEBUG
395static int ov6650_get_register(struct v4l2_subdev *sd,
396 struct v4l2_dbg_register *reg)
397{
398 struct i2c_client *client = v4l2_get_subdevdata(sd);
399 int ret;
400 u8 val;
401
402 if (reg->reg & ~0xff)
403 return -EINVAL;
404
405 reg->size = 1;
406
407 ret = ov6650_reg_read(client, reg->reg, &val);
408 if (!ret)
409 reg->val = (__u64)val;
410
411 return ret;
412}
413
414static int ov6650_set_register(struct v4l2_subdev *sd,
977ba3b1 415 const struct v4l2_dbg_register *reg)
2f6e2404
JK		 416{
417 struct i2c_client *client = v4l2_get_subdevdata(sd);
418
419 if (reg->reg & ~0xff || reg->val & ~0xff)
420 return -EINVAL;
421
422 return ov6650_reg_write(client, reg->reg, reg->val);
423}
424#endif
425
4ec10bac
LP		 426static int ov6650_s_power(struct v4l2_subdev *sd, int on)
427{
428 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 429 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
9aea470b 430 struct ov6650 *priv = to_ov6650(client);
4ec10bac 431
9aea470b 432 return soc_camera_set_power(&client->dev, ssdd, priv->clk, on);
4ec10bac
LP		 433}
434
10d5509c
HV		 435static int ov6650_get_selection(struct v4l2_subdev *sd,
436 struct v4l2_subdev_pad_config *cfg,
437 struct v4l2_subdev_selection *sel)
2f6e2404
JK		 438{
439 struct i2c_client *client = v4l2_get_subdevdata(sd);
440 struct ov6650 *priv = to_ov6650(client);
441
10d5509c
HV		 442 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
443 return -EINVAL;
2f6e2404 444
10d5509c
HV		 445 switch (sel->target) {
446 case V4L2_SEL_TGT_CROP_BOUNDS:
447 case V4L2_SEL_TGT_CROP_DEFAULT:
448 sel->r.left = DEF_HSTRT << 1;
449 sel->r.top = DEF_VSTRT << 1;
450 sel->r.width = W_CIF;
451 sel->r.height = H_CIF;
452 return 0;
453 case V4L2_SEL_TGT_CROP:
454 sel->r = priv->rect;
455 return 0;
456 default:
457 return -EINVAL;
458 }
2f6e2404
JK		 459}
460
10d5509c
HV		 461static int ov6650_set_selection(struct v4l2_subdev *sd,
462 struct v4l2_subdev_pad_config *cfg,
463 struct v4l2_subdev_selection *sel)
2f6e2404
JK		 464{
465 struct i2c_client *client = v4l2_get_subdevdata(sd);
466 struct ov6650 *priv = to_ov6650(client);
10d5509c 467 struct v4l2_rect rect = sel->r;
2f6e2404
JK		 468 int ret;
469
10d5509c
HV		 470 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
471 sel->target != V4L2_SEL_TGT_CROP)
2f6e2404
JK		 472 return -EINVAL;
473
4f996594
HV		 474 rect.left = ALIGN(rect.left, 2);
475 rect.width = ALIGN(rect.width, 2);
476 rect.top = ALIGN(rect.top, 2);
477 rect.height = ALIGN(rect.height, 2);
478 soc_camera_limit_side(&rect.left, &rect.width,
2f6e2404 479 DEF_HSTRT << 1, 2, W_CIF);
4f996594 480 soc_camera_limit_side(&rect.top, &rect.height,
2f6e2404
JK		 481 DEF_VSTRT << 1, 2, H_CIF);
482
4f996594 483 ret = ov6650_reg_write(client, REG_HSTRT, rect.left >> 1);
2f6e2404 484 if (!ret) {
4f996594 485 priv->rect.left = rect.left;
2f6e2404 486 ret = ov6650_reg_write(client, REG_HSTOP,
4f996594 487 (rect.left + rect.width) >> 1);
2f6e2404
JK		 488 }
489 if (!ret) {
4f996594
HV		 490 priv->rect.width = rect.width;
491 ret = ov6650_reg_write(client, REG_VSTRT, rect.top >> 1);
2f6e2404
JK		 492 }
493 if (!ret) {
4f996594 494 priv->rect.top = rect.top;
2f6e2404 495 ret = ov6650_reg_write(client, REG_VSTOP,
4f996594 496 (rect.top + rect.height) >> 1);
2f6e2404
JK		 497 }
498 if (!ret)
4f996594 499 priv->rect.height = rect.height;
2f6e2404
JK		 500
501 return ret;
502}
503
da298c6d
HV		 504static int ov6650_get_fmt(struct v4l2_subdev *sd,
505 struct v4l2_subdev_pad_config *cfg,
506 struct v4l2_subdev_format *format)
2f6e2404 507{
da298c6d 508 struct v4l2_mbus_framefmt *mf = &format->format;
2f6e2404
JK		 509 struct i2c_client *client = v4l2_get_subdevdata(sd);
510 struct ov6650 *priv = to_ov6650(client);
511
da298c6d
HV		 512 if (format->pad)
513 return -EINVAL;
514
2f6e2404
JK		 515 mf->width = priv->rect.width >> priv->half_scale;
516 mf->height = priv->rect.height >> priv->half_scale;
517 mf->code = priv->code;
518 mf->colorspace = priv->colorspace;
519 mf->field = V4L2_FIELD_NONE;
520
521 return 0;
522}
523
524static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
525{
d889eb1e 526 return width > rect->width >> 1 || height > rect->height >> 1;
2f6e2404
JK		 527}
528
529static u8 to_clkrc(struct v4l2_fract *timeperframe,
530 unsigned long pclk_limit, unsigned long pclk_max)
531{
532 unsigned long pclk;
533
534 if (timeperframe->numerator && timeperframe->denominator)
535 pclk = pclk_max * timeperframe->denominator /
536 (FRAME_RATE_MAX * timeperframe->numerator);
537 else
538 pclk = pclk_max;
539
540 if (pclk_limit && pclk_limit < pclk)
541 pclk = pclk_limit;
542
543 return (pclk_max - 1) / pclk;
544}
545
546/* set the format we will capture in */
547static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
548{
549 struct i2c_client *client = v4l2_get_subdevdata(sd);
4c0b036d 550 struct soc_camera_device *icd = v4l2_get_subdev_hostdata(sd);
2f6e2404
JK		 551 struct soc_camera_sense *sense = icd->sense;
552 struct ov6650 *priv = to_ov6650(client);
553 bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
10d5509c
HV		 554 struct v4l2_subdev_selection sel = {
555 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
556 .target = V4L2_SEL_TGT_CROP,
557 .r.left = priv->rect.left + (priv->rect.width >> 1) -
558 (mf->width >> (1 - half_scale)),
559 .r.top = priv->rect.top + (priv->rect.height >> 1) -
560 (mf->height >> (1 - half_scale)),
561 .r.width = mf->width << half_scale,
562 .r.height = mf->height << half_scale,
2f6e2404 563 };
f5fe58fd 564 u32 code = mf->code;
2f6e2404
JK		 565 unsigned long mclk, pclk;
566 u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
567 int ret;
568
569 /* select color matrix configuration for given color encoding */
570 switch (code) {
f5fe58fd 571 case MEDIA_BUS_FMT_Y8_1X8:
2f6e2404
JK		 572 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
573 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
574 coma_set |= COMA_BW;
575 break;
f5fe58fd 576 case MEDIA_BUS_FMT_YUYV8_2X8:
2f6e2404
JK		 577 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
578 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
579 coma_set |= COMA_WORD_SWAP;
580 break;
f5fe58fd 581 case MEDIA_BUS_FMT_YVYU8_2X8:
2f6e2404
JK		 582 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
583 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
584 COMA_BYTE_SWAP;
585 break;
f5fe58fd 586 case MEDIA_BUS_FMT_UYVY8_2X8:
2f6e2404
JK		 587 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
588 if (half_scale) {
589 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
590 coma_set |= COMA_BYTE_SWAP;
591 } else {
592 coma_mask |= COMA_RGB | COMA_BW;
593 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
594 }
595 break;
f5fe58fd 596 case MEDIA_BUS_FMT_VYUY8_2X8:
2f6e2404
JK		 597 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
598 if (half_scale) {
599 coma_mask |= COMA_RGB | COMA_BW;
600 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
601 } else {
602 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
603 coma_set |= COMA_BYTE_SWAP;
604 }
605 break;
f5fe58fd 606 case MEDIA_BUS_FMT_SBGGR8_1X8:
2f6e2404
JK		 607 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
608 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
609 coma_set |= COMA_RAW_RGB | COMA_RGB;
610 break;
2f6e2404
JK		 611 default:
612 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
613 return -EINVAL;
614 }
615 priv->code = code;
616
f5fe58fd
BB		 617 if (code == MEDIA_BUS_FMT_Y8_1X8 ||
618 code == MEDIA_BUS_FMT_SBGGR8_1X8) {
2f6e2404
JK		 619 coml_mask = COML_ONE_CHANNEL;
620 coml_set = 0;
621 priv->pclk_max = 4000000;
622 } else {
623 coml_mask = 0;
624 coml_set = COML_ONE_CHANNEL;
625 priv->pclk_max = 8000000;
626 }
627
f5fe58fd 628 if (code == MEDIA_BUS_FMT_SBGGR8_1X8)
2f6e2404
JK		 629 priv->colorspace = V4L2_COLORSPACE_SRGB;
630 else if (code != 0)
631 priv->colorspace = V4L2_COLORSPACE_JPEG;
632
633 if (half_scale) {
634 dev_dbg(&client->dev, "max resolution: QCIF\n");
635 coma_set |= COMA_QCIF;
636 priv->pclk_max /= 2;
637 } else {
638 dev_dbg(&client->dev, "max resolution: CIF\n");
639 coma_mask |= COMA_QCIF;
640 }
641 priv->half_scale = half_scale;
642
643 if (sense) {
644 if (sense->master_clock == 8000000) {
645 dev_dbg(&client->dev, "8MHz input clock\n");
646 clkrc = CLKRC_6MHz;
647 } else if (sense->master_clock == 12000000) {
648 dev_dbg(&client->dev, "12MHz input clock\n");
649 clkrc = CLKRC_12MHz;
650 } else if (sense->master_clock == 16000000) {
651 dev_dbg(&client->dev, "16MHz input clock\n");
652 clkrc = CLKRC_16MHz;
653 } else if (sense->master_clock == 24000000) {
654 dev_dbg(&client->dev, "24MHz input clock\n");
655 clkrc = CLKRC_24MHz;
656 } else {
657 dev_err(&client->dev,
6d73d072 658 "unsupported input clock, check platform data\n");
2f6e2404
JK		 659 return -EINVAL;
660 }
661 mclk = sense->master_clock;
662 priv->pclk_limit = sense->pixel_clock_max;
663 } else {
664 clkrc = CLKRC_24MHz;
665 mclk = 24000000;
666 priv->pclk_limit = 0;
667 dev_dbg(&client->dev, "using default 24MHz input clock\n");
668 }
669
670 clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
671
672 pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
673 dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
674 mclk / pclk, 10 * mclk % pclk / pclk);
675
10d5509c 676 ret = ov6650_set_selection(sd, NULL, &sel);
2f6e2404
JK		 677 if (!ret)
678 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
679 if (!ret)
680 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
681 if (!ret)
682 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
683
684 if (!ret) {
685 mf->colorspace = priv->colorspace;
686 mf->width = priv->rect.width >> half_scale;
687 mf->height = priv->rect.height >> half_scale;
688 }
2f6e2404
JK		 689 return ret;
690}
691
717fd5b4
HV		 692static int ov6650_set_fmt(struct v4l2_subdev *sd,
693 struct v4l2_subdev_pad_config *cfg,
694 struct v4l2_subdev_format *format)
2f6e2404 695{
717fd5b4 696 struct v4l2_mbus_framefmt *mf = &format->format;
2f6e2404
JK		 697 struct i2c_client *client = v4l2_get_subdevdata(sd);
698 struct ov6650 *priv = to_ov6650(client);
699
717fd5b4
HV		 700 if (format->pad)
701 return -EINVAL;
702
2f6e2404
JK		 703 if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
704 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
705 &mf->height, 2, H_CIF, 1, 0);
706
707 mf->field = V4L2_FIELD_NONE;
708
709 switch (mf->code) {
f5fe58fd
BB		 710 case MEDIA_BUS_FMT_Y10_1X10:
711 mf->code = MEDIA_BUS_FMT_Y8_1X8;
712 case MEDIA_BUS_FMT_Y8_1X8:
713 case MEDIA_BUS_FMT_YVYU8_2X8:
714 case MEDIA_BUS_FMT_YUYV8_2X8:
715 case MEDIA_BUS_FMT_VYUY8_2X8:
716 case MEDIA_BUS_FMT_UYVY8_2X8:
2f6e2404
JK		 717 mf->colorspace = V4L2_COLORSPACE_JPEG;
718 break;
719 default:
f5fe58fd
BB		 720 mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
721 case MEDIA_BUS_FMT_SBGGR8_1X8:
2f6e2404
JK		 722 mf->colorspace = V4L2_COLORSPACE_SRGB;
723 break;
724 }
725
717fd5b4
HV		 726 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
727 return ov6650_s_fmt(sd, mf);
728 cfg->try_fmt = *mf;
729
2f6e2404
JK		 730 return 0;
731}
732
ebcff5fc
HV		 733static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
734 struct v4l2_subdev_pad_config *cfg,
735 struct v4l2_subdev_mbus_code_enum *code)
2f6e2404 736{
ebcff5fc 737 if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
2f6e2404
JK		 738 return -EINVAL;
739
ebcff5fc 740 code->code = ov6650_codes[code->index];
2f6e2404
JK		 741 return 0;
742}
743
744static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
745{
746 struct i2c_client *client = v4l2_get_subdevdata(sd);
747 struct ov6650 *priv = to_ov6650(client);
748 struct v4l2_captureparm *cp = &parms->parm.capture;
749
750 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
751 return -EINVAL;
752
753 memset(cp, 0, sizeof(*cp));
754 cp->capability = V4L2_CAP_TIMEPERFRAME;
755 cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
756 priv->pclk_limit, priv->pclk_max));
757 cp->timeperframe.denominator = FRAME_RATE_MAX;
758
759 dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
760 cp->timeperframe.numerator, cp->timeperframe.denominator);
761
762 return 0;
763}
764
765static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
766{
767 struct i2c_client *client = v4l2_get_subdevdata(sd);
768 struct ov6650 *priv = to_ov6650(client);
769 struct v4l2_captureparm *cp = &parms->parm.capture;
770 struct v4l2_fract *tpf = &cp->timeperframe;
771 int div, ret;
772 u8 clkrc;
773
774 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
775 return -EINVAL;
776
777 if (cp->extendedmode != 0)
778 return -EINVAL;
779
780 if (tpf->numerator == 0 || tpf->denominator == 0)
781 div = 1; /* Reset to full rate */
782 else
783 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
784
785 if (div == 0)
786 div = 1;
787 else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
788 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
789
790 /*
791 * Keep result to be used as tpf limit
792 * for subseqent clock divider calculations
793 */
794 priv->tpf.numerator = div;
795 priv->tpf.denominator = FRAME_RATE_MAX;
796
797 clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
798
799 ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
800 if (!ret) {
801 tpf->numerator = GET_CLKRC_DIV(clkrc);
802 tpf->denominator = FRAME_RATE_MAX;
803 }
804
805 return ret;
806}
807
808/* Soft reset the camera. This has nothing to do with the RESET pin! */
809static int ov6650_reset(struct i2c_client *client)
810{
811 int ret;
812
813 dev_dbg(&client->dev, "reset\n");
814
815 ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
816 if (ret)
817 dev_err(&client->dev,
25985edc 818 "An error occurred while entering soft reset!\n");
2f6e2404
JK		 819
820 return ret;
821}
822
823/* program default register values */
824static int ov6650_prog_dflt(struct i2c_client *client)
825{
826 int ret;
827
828 dev_dbg(&client->dev, "initializing\n");
829
830 ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
831 if (!ret)
832 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
833
834 return ret;
835}
836
14178aa5 837static int ov6650_video_probe(struct i2c_client *client)
2f6e2404 838{
4bbc6d52 839 struct ov6650 *priv = to_ov6650(client);
2f6e2404 840 u8 pidh, pidl, midh, midl;
4bbc6d52
LP		 841 int ret;
842
843 ret = ov6650_s_power(&priv->subdev, 1);
844 if (ret < 0)
845 return ret;
2f6e2404
JK		 846
847 /*
848 * check and show product ID and manufacturer ID
849 */
850 ret = ov6650_reg_read(client, REG_PIDH, &pidh);
851 if (!ret)
852 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
853 if (!ret)
854 ret = ov6650_reg_read(client, REG_MIDH, &midh);
855 if (!ret)
856 ret = ov6650_reg_read(client, REG_MIDL, &midl);
857
858 if (ret)
4bbc6d52 859 goto done;
2f6e2404
JK		 860
861 if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
862 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
863 pidh, pidl);
4bbc6d52
LP		 864 ret = -ENODEV;
865 goto done;
2f6e2404
JK		 866 }
867
868 dev_info(&client->dev,
869 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
870 pidh, pidl, midh, midl);
871
872 ret = ov6650_reset(client);
873 if (!ret)
874 ret = ov6650_prog_dflt(client);
4bbc6d52
LP		 875 if (!ret)
876 ret = v4l2_ctrl_handler_setup(&priv->hdl);
2f6e2404 877
4bbc6d52
LP		 878done:
879 ov6650_s_power(&priv->subdev, 0);
2f6e2404
JK		 880 return ret;
881}
882
afd9690c
HV		 883static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
884 .g_volatile_ctrl = ov6550_g_volatile_ctrl,
885 .s_ctrl = ov6550_s_ctrl,
2f6e2404
JK		 886};
887
888static struct v4l2_subdev_core_ops ov6650_core_ops = {
2f6e2404
JK		 889#ifdef CONFIG_VIDEO_ADV_DEBUG
890 .g_register = ov6650_get_register,
891 .s_register = ov6650_set_register,
892#endif
4ec10bac 893 .s_power = ov6650_s_power,
2f6e2404
JK		 894};
895
db669e79 896/* Request bus settings on camera side */
59ca25b7
GL		 897static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
898 struct v4l2_mbus_config *cfg)
899{
900 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 901 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
59ca25b7
GL		 902
903 cfg->flags = V4L2_MBUS_MASTER |
904 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
905 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
906 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
907 V4L2_MBUS_DATA_ACTIVE_HIGH;
908 cfg->type = V4L2_MBUS_PARALLEL;
25a34811 909 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
59ca25b7
GL		 910
911 return 0;
912}
913
db669e79 914/* Alter bus settings on camera side */
59ca25b7
GL		 915static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
916 const struct v4l2_mbus_config *cfg)
917{
918 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811
GL		 919 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
920 unsigned long flags = soc_camera_apply_board_flags(ssdd, cfg);
59ca25b7
GL		 921 int ret;
922
923 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
924 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
925 else
926 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
927 if (ret)
928 return ret;
929
930 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
931 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
932 else
933 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
934 if (ret)
935 return ret;
936
937 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
938 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
939 else
940 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
941
942 return ret;
943}
944
2f6e2404
JK		 945static struct v4l2_subdev_video_ops ov6650_video_ops = {
946 .s_stream = ov6650_s_stream,
2f6e2404
JK		 947 .g_parm = ov6650_g_parm,
948 .s_parm = ov6650_s_parm,
59ca25b7
GL		 949 .g_mbus_config = ov6650_g_mbus_config,
950 .s_mbus_config = ov6650_s_mbus_config,
2f6e2404
JK		 951};
952
ebcff5fc
HV		 953static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
954 .enum_mbus_code = ov6650_enum_mbus_code,
10d5509c
HV		 955 .get_selection = ov6650_get_selection,
956 .set_selection = ov6650_set_selection,
da298c6d 957 .get_fmt = ov6650_get_fmt,
717fd5b4 958 .set_fmt = ov6650_set_fmt,
ebcff5fc
HV		 959};
960
2f6e2404
JK		 961static struct v4l2_subdev_ops ov6650_subdev_ops = {
962 .core = &ov6650_core_ops,
963 .video = &ov6650_video_ops,
ebcff5fc 964 .pad = &ov6650_pad_ops,
2f6e2404
JK		 965};
966
967/*
968 * i2c_driver function
969 */
970static int ov6650_probe(struct i2c_client *client,
971 const struct i2c_device_id *did)
972{
973 struct ov6650 *priv;
25a34811 974 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
2f6e2404
JK		 975 int ret;
976
25a34811 977 if (!ssdd) {
2f6e2404
JK		 978 dev_err(&client->dev, "Missing platform_data for driver\n");
979 return -EINVAL;
980 }
981
70e176a5 982 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
2f6e2404
JK		 983 if (!priv) {
984 dev_err(&client->dev,
985 "Failed to allocate memory for private data!\n");
986 return -ENOMEM;
987 }
988
989 v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
afd9690c
HV		 990 v4l2_ctrl_handler_init(&priv->hdl, 13);
991 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
992 V4L2_CID_VFLIP, 0, 1, 1, 0);
993 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
994 V4L2_CID_HFLIP, 0, 1, 1, 0);
995 priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
996 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
997 priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
998 V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
999 priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1000 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1001 priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1002 V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
1003 priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1004 V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
1005 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1006 V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
1007 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1008 V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
1009 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1010 V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
1011 priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
2e56d933
JK		 1012 &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
1013 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
afd9690c
HV		 1014 priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1015 V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
1016 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1017 V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1018
1019 priv->subdev.ctrl_handler = &priv->hdl;
70e176a5
GL		 1020 if (priv->hdl.error)
1021 return priv->hdl.error;
2f6e2404 1022
afd9690c
HV		 1023 v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1024 v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1025 v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1026 V4L2_EXPOSURE_MANUAL, true);
2f6e2404
JK		 1027
1028 priv->rect.left = DEF_HSTRT << 1;
1029 priv->rect.top = DEF_VSTRT << 1;
1030 priv->rect.width = W_CIF;
1031 priv->rect.height = H_CIF;
1032 priv->half_scale = false;
f5fe58fd 1033 priv->code = MEDIA_BUS_FMT_YUYV8_2X8;
2f6e2404
JK		 1034 priv->colorspace = V4L2_COLORSPACE_JPEG;
1035
9aea470b
GL		 1036 priv->clk = v4l2_clk_get(&client->dev, "mclk");
1037 if (IS_ERR(priv->clk)) {
1038 ret = PTR_ERR(priv->clk);
1039 goto eclkget;
1040 }
1041
14178aa5 1042 ret = ov6650_video_probe(client);
9aea470b
GL		 1043 if (ret) {
1044 v4l2_clk_put(priv->clk);
1045eclkget:
afd9690c 1046 v4l2_ctrl_handler_free(&priv->hdl);
9aea470b 1047 }
2f6e2404
JK		 1048
1049 return ret;
1050}
1051
1052static int ov6650_remove(struct i2c_client *client)
1053{
1054 struct ov6650 *priv = to_ov6650(client);
1055
9aea470b 1056 v4l2_clk_put(priv->clk);
afd9690c
HV		 1057 v4l2_device_unregister_subdev(&priv->subdev);
1058 v4l2_ctrl_handler_free(&priv->hdl);
2f6e2404
JK		 1059 return 0;
1060}
1061
1062static const struct i2c_device_id ov6650_id[] = {
1063 { "ov6650", 0 },
1064 { }
1065};
1066MODULE_DEVICE_TABLE(i2c, ov6650_id);
1067
1068static struct i2c_driver ov6650_i2c_driver = {
1069 .driver = {
1070 .name = "ov6650",
1071 },
1072 .probe = ov6650_probe,
1073 .remove = ov6650_remove,
1074 .id_table = ov6650_id,
1075};
1076
c6e8d86f 1077module_i2c_driver(ov6650_i2c_driver);
2f6e2404
JK		 1078
1079MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1080MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1081MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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