Commit | Line | Data |
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ed922a89 KM |
1 | /* |
2 | * tw9910 Video Driver | |
3 | * | |
4 | * Copyright (C) 2008 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ov772x driver, | |
8 | * | |
9 | * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
10 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> | |
11 | * Copyright (C) 2008 Magnus Damm | |
12 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/i2c.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/delay.h> | |
95d20109 | 25 | #include <linux/v4l2-mediabus.h> |
ed922a89 | 26 | #include <linux/videodev2.h> |
0d3263f9 | 27 | |
ed922a89 | 28 | #include <media/soc_camera.h> |
b5dcee22 | 29 | #include <media/i2c/tw9910.h> |
9aea470b | 30 | #include <media/v4l2-clk.h> |
0d3263f9 | 31 | #include <media/v4l2-subdev.h> |
ed922a89 KM |
32 | |
33 | #define GET_ID(val) ((val & 0xF8) >> 3) | |
6d74e5f3 | 34 | #define GET_REV(val) (val & 0x07) |
ed922a89 KM |
35 | |
36 | /* | |
37 | * register offset | |
38 | */ | |
39 | #define ID 0x00 /* Product ID Code Register */ | |
40 | #define STATUS1 0x01 /* Chip Status Register I */ | |
41 | #define INFORM 0x02 /* Input Format */ | |
42 | #define OPFORM 0x03 /* Output Format Control Register */ | |
43 | #define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */ | |
44 | #define OUTCTR1 0x05 /* Output Control I */ | |
45 | #define ACNTL1 0x06 /* Analog Control Register 1 */ | |
46 | #define CROP_HI 0x07 /* Cropping Register, High */ | |
47 | #define VDELAY_LO 0x08 /* Vertical Delay Register, Low */ | |
48 | #define VACTIVE_LO 0x09 /* Vertical Active Register, Low */ | |
49 | #define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */ | |
50 | #define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */ | |
51 | #define CNTRL1 0x0C /* Control Register I */ | |
52 | #define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */ | |
53 | #define SCALE_HI 0x0E /* Scaling Register, High */ | |
54 | #define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */ | |
55 | #define BRIGHT 0x10 /* BRIGHTNESS Control Register */ | |
56 | #define CONTRAST 0x11 /* CONTRAST Control Register */ | |
57 | #define SHARPNESS 0x12 /* SHARPNESS Control Register I */ | |
58 | #define SAT_U 0x13 /* Chroma (U) Gain Register */ | |
59 | #define SAT_V 0x14 /* Chroma (V) Gain Register */ | |
60 | #define HUE 0x15 /* Hue Control Register */ | |
61 | #define CORING1 0x17 | |
62 | #define CORING2 0x18 /* Coring and IF compensation */ | |
63 | #define VBICNTL 0x19 /* VBI Control Register */ | |
64 | #define ACNTL2 0x1A /* Analog Control 2 */ | |
65 | #define OUTCTR2 0x1B /* Output Control 2 */ | |
66 | #define SDT 0x1C /* Standard Selection */ | |
67 | #define SDTR 0x1D /* Standard Recognition */ | |
68 | #define TEST 0x1F /* Test Control Register */ | |
69 | #define CLMPG 0x20 /* Clamping Gain */ | |
70 | #define IAGC 0x21 /* Individual AGC Gain */ | |
71 | #define AGCGAIN 0x22 /* AGC Gain */ | |
72 | #define PEAKWT 0x23 /* White Peak Threshold */ | |
73 | #define CLMPL 0x24 /* Clamp level */ | |
74 | #define SYNCT 0x25 /* Sync Amplitude */ | |
75 | #define MISSCNT 0x26 /* Sync Miss Count Register */ | |
76 | #define PCLAMP 0x27 /* Clamp Position Register */ | |
77 | #define VCNTL1 0x28 /* Vertical Control I */ | |
78 | #define VCNTL2 0x29 /* Vertical Control II */ | |
79 | #define CKILL 0x2A /* Color Killer Level Control */ | |
80 | #define COMB 0x2B /* Comb Filter Control */ | |
81 | #define LDLY 0x2C /* Luma Delay and H Filter Control */ | |
82 | #define MISC1 0x2D /* Miscellaneous Control I */ | |
83 | #define LOOP 0x2E /* LOOP Control Register */ | |
84 | #define MISC2 0x2F /* Miscellaneous Control II */ | |
85 | #define MVSN 0x30 /* Macrovision Detection */ | |
86 | #define STATUS2 0x31 /* Chip STATUS II */ | |
87 | #define HFREF 0x32 /* H monitor */ | |
88 | #define CLMD 0x33 /* CLAMP MODE */ | |
89 | #define IDCNTL 0x34 /* ID Detection Control */ | |
90 | #define CLCNTL1 0x35 /* Clamp Control I */ | |
91 | #define ANAPLLCTL 0x4C | |
92 | #define VBIMIN 0x4D | |
93 | #define HSLOWCTL 0x4E | |
94 | #define WSS3 0x4F | |
95 | #define FILLDATA 0x50 | |
96 | #define SDID 0x51 | |
97 | #define DID 0x52 | |
98 | #define WSS1 0x53 | |
99 | #define WSS2 0x54 | |
100 | #define VVBI 0x55 | |
101 | #define LCTL6 0x56 | |
102 | #define LCTL7 0x57 | |
103 | #define LCTL8 0x58 | |
104 | #define LCTL9 0x59 | |
105 | #define LCTL10 0x5A | |
106 | #define LCTL11 0x5B | |
107 | #define LCTL12 0x5C | |
108 | #define LCTL13 0x5D | |
109 | #define LCTL14 0x5E | |
110 | #define LCTL15 0x5F | |
111 | #define LCTL16 0x60 | |
112 | #define LCTL17 0x61 | |
113 | #define LCTL18 0x62 | |
114 | #define LCTL19 0x63 | |
115 | #define LCTL20 0x64 | |
116 | #define LCTL21 0x65 | |
117 | #define LCTL22 0x66 | |
118 | #define LCTL23 0x67 | |
119 | #define LCTL24 0x68 | |
120 | #define LCTL25 0x69 | |
121 | #define LCTL26 0x6A | |
faa58261 | 122 | #define HSBEGIN 0x6B |
ed922a89 KM |
123 | #define HSEND 0x6C |
124 | #define OVSDLY 0x6D | |
125 | #define OVSEND 0x6E | |
126 | #define VBIDELAY 0x6F | |
127 | ||
128 | /* | |
129 | * register detail | |
130 | */ | |
131 | ||
132 | /* INFORM */ | |
133 | #define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */ | |
134 | #define FC27_FF 0x00 /* 0 : Square pixel mode. */ | |
135 | /* Must use 24.54MHz for 60Hz field rate */ | |
136 | /* source or 29.5MHz for 50Hz field rate */ | |
137 | #define IFSEL_S 0x10 /* 01 : S-video decoding */ | |
138 | #define IFSEL_C 0x00 /* 00 : Composite video decoding */ | |
139 | /* Y input video selection */ | |
140 | #define YSEL_M0 0x00 /* 00 : Mux0 selected */ | |
141 | #define YSEL_M1 0x04 /* 01 : Mux1 selected */ | |
142 | #define YSEL_M2 0x08 /* 10 : Mux2 selected */ | |
143 | #define YSEL_M3 0x10 /* 11 : Mux3 selected */ | |
144 | ||
145 | /* OPFORM */ | |
146 | #define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */ | |
147 | /* 1 : ITU-R-656 compatible data sequence format */ | |
148 | #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */ | |
149 | /* 1 : 16-bit YCrCb 4:2:2 output format.*/ | |
150 | #define LLCMODE 0x20 /* 1 : LLC output mode. */ | |
151 | /* 0 : free-run output mode */ | |
152 | #define AINC 0x10 /* Serial interface auto-indexing control */ | |
153 | /* 0 : auto-increment */ | |
154 | /* 1 : non-auto */ | |
155 | #define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */ | |
156 | /* 0 : Vertical out ctrl by HACTIVE and DVALID */ | |
06f292e4 KM |
157 | #define OEN_TRI_SEL_MASK 0x07 |
158 | #define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */ | |
159 | #define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */ | |
160 | #define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */ | |
ed922a89 KM |
161 | |
162 | /* OUTCTR1 */ | |
163 | #define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */ | |
164 | #define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */ | |
165 | /* VS pin output control */ | |
166 | #define VSSL_VSYNC 0x00 /* 0 : VSYNC */ | |
167 | #define VSSL_VACT 0x10 /* 1 : VACT */ | |
168 | #define VSSL_FIELD 0x20 /* 2 : FIELD */ | |
169 | #define VSSL_VVALID 0x30 /* 3 : VVALID */ | |
170 | #define VSSL_ZERO 0x70 /* 7 : 0 */ | |
171 | #define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */ | |
172 | #define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/ | |
173 | /* HS pin output control */ | |
174 | #define HSSL_HACT 0x00 /* 0 : HACT */ | |
175 | #define HSSL_HSYNC 0x01 /* 1 : HSYNC */ | |
176 | #define HSSL_DVALID 0x02 /* 2 : DVALID */ | |
177 | #define HSSL_HLOCK 0x03 /* 3 : HLOCK */ | |
178 | #define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */ | |
179 | #define HSSL_ZERO 0x07 /* 7 : 0 */ | |
180 | ||
181 | /* ACNTL1 */ | |
182 | #define SRESET 0x80 /* resets the device to its default state | |
183 | * but all register content remain unchanged. | |
184 | * This bit is self-resetting. | |
185 | */ | |
607e5ad8 KM |
186 | #define ACNTL1_PDN_MASK 0x0e |
187 | #define CLK_PDN 0x08 /* system clock power down */ | |
188 | #define Y_PDN 0x04 /* Luma ADC power down */ | |
189 | #define C_PDN 0x02 /* Chroma ADC power down */ | |
190 | ||
191 | /* ACNTL2 */ | |
192 | #define ACNTL2_PDN_MASK 0x40 | |
193 | #define PLL_PDN 0x40 /* PLL power down */ | |
ed922a89 KM |
194 | |
195 | /* VBICNTL */ | |
5d28d525 GL |
196 | |
197 | /* RTSEL : control the real time signal output from the MPOUT pin */ | |
ed922a89 KM |
198 | #define RTSEL_MASK 0x07 |
199 | #define RTSEL_VLOSS 0x00 /* 0000 = Video loss */ | |
200 | #define RTSEL_HLOCK 0x01 /* 0001 = H-lock */ | |
201 | #define RTSEL_SLOCK 0x02 /* 0010 = S-lock */ | |
202 | #define RTSEL_VLOCK 0x03 /* 0011 = V-lock */ | |
203 | #define RTSEL_MONO 0x04 /* 0100 = MONO */ | |
204 | #define RTSEL_DET50 0x05 /* 0101 = DET50 */ | |
205 | #define RTSEL_FIELD 0x06 /* 0110 = FIELD */ | |
206 | #define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */ | |
207 | ||
2ad90b71 GL |
208 | /* HSYNC start and end are constant for now */ |
209 | #define HSYNC_START 0x0260 | |
210 | #define HSYNC_END 0x0300 | |
211 | ||
ed922a89 KM |
212 | /* |
213 | * structure | |
214 | */ | |
215 | ||
216 | struct regval_list { | |
217 | unsigned char reg_num; | |
218 | unsigned char value; | |
219 | }; | |
220 | ||
221 | struct tw9910_scale_ctrl { | |
222 | char *name; | |
223 | unsigned short width; | |
224 | unsigned short height; | |
225 | u16 hscale; | |
226 | u16 vscale; | |
227 | }; | |
228 | ||
ed922a89 | 229 | struct tw9910_priv { |
906b1018 | 230 | struct v4l2_subdev subdev; |
9aea470b | 231 | struct v4l2_clk *clk; |
906b1018 GL |
232 | struct tw9910_video_info *info; |
233 | const struct tw9910_scale_ctrl *scale; | |
2f0babb7 | 234 | v4l2_std_id norm; |
906b1018 | 235 | u32 revision; |
ed922a89 KM |
236 | }; |
237 | ||
ed922a89 KM |
238 | static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = { |
239 | { | |
240 | .name = "NTSC SQ", | |
241 | .width = 640, | |
242 | .height = 480, | |
243 | .hscale = 0x0100, | |
244 | .vscale = 0x0100, | |
245 | }, | |
246 | { | |
247 | .name = "NTSC CCIR601", | |
248 | .width = 720, | |
249 | .height = 480, | |
250 | .hscale = 0x0100, | |
251 | .vscale = 0x0100, | |
252 | }, | |
253 | { | |
254 | .name = "NTSC SQ (CIF)", | |
255 | .width = 320, | |
256 | .height = 240, | |
257 | .hscale = 0x0200, | |
258 | .vscale = 0x0200, | |
259 | }, | |
260 | { | |
261 | .name = "NTSC CCIR601 (CIF)", | |
262 | .width = 360, | |
263 | .height = 240, | |
264 | .hscale = 0x0200, | |
265 | .vscale = 0x0200, | |
266 | }, | |
267 | { | |
268 | .name = "NTSC SQ (QCIF)", | |
269 | .width = 160, | |
270 | .height = 120, | |
271 | .hscale = 0x0400, | |
272 | .vscale = 0x0400, | |
273 | }, | |
274 | { | |
275 | .name = "NTSC CCIR601 (QCIF)", | |
276 | .width = 180, | |
277 | .height = 120, | |
278 | .hscale = 0x0400, | |
279 | .vscale = 0x0400, | |
280 | }, | |
281 | }; | |
282 | ||
283 | static const struct tw9910_scale_ctrl tw9910_pal_scales[] = { | |
284 | { | |
285 | .name = "PAL SQ", | |
286 | .width = 768, | |
287 | .height = 576, | |
288 | .hscale = 0x0100, | |
289 | .vscale = 0x0100, | |
290 | }, | |
291 | { | |
292 | .name = "PAL CCIR601", | |
293 | .width = 720, | |
294 | .height = 576, | |
295 | .hscale = 0x0100, | |
296 | .vscale = 0x0100, | |
297 | }, | |
298 | { | |
299 | .name = "PAL SQ (CIF)", | |
300 | .width = 384, | |
301 | .height = 288, | |
302 | .hscale = 0x0200, | |
303 | .vscale = 0x0200, | |
304 | }, | |
305 | { | |
306 | .name = "PAL CCIR601 (CIF)", | |
307 | .width = 360, | |
308 | .height = 288, | |
309 | .hscale = 0x0200, | |
310 | .vscale = 0x0200, | |
311 | }, | |
312 | { | |
313 | .name = "PAL SQ (QCIF)", | |
314 | .width = 192, | |
315 | .height = 144, | |
316 | .hscale = 0x0400, | |
317 | .vscale = 0x0400, | |
318 | }, | |
319 | { | |
320 | .name = "PAL CCIR601 (QCIF)", | |
321 | .width = 180, | |
322 | .height = 144, | |
323 | .hscale = 0x0400, | |
324 | .vscale = 0x0400, | |
325 | }, | |
326 | }; | |
327 | ||
ed922a89 KM |
328 | /* |
329 | * general function | |
330 | */ | |
979ea1dd GL |
331 | static struct tw9910_priv *to_tw9910(const struct i2c_client *client) |
332 | { | |
96c75399 GL |
333 | return container_of(i2c_get_clientdata(client), struct tw9910_priv, |
334 | subdev); | |
979ea1dd GL |
335 | } |
336 | ||
20797083 KM |
337 | static int tw9910_mask_set(struct i2c_client *client, u8 command, |
338 | u8 mask, u8 set) | |
339 | { | |
340 | s32 val = i2c_smbus_read_byte_data(client, command); | |
341 | if (val < 0) | |
342 | return val; | |
343 | ||
344 | val &= ~mask; | |
345 | val |= set & mask; | |
346 | ||
347 | return i2c_smbus_write_byte_data(client, command, val); | |
348 | } | |
349 | ||
ed922a89 KM |
350 | static int tw9910_set_scale(struct i2c_client *client, |
351 | const struct tw9910_scale_ctrl *scale) | |
352 | { | |
353 | int ret; | |
354 | ||
355 | ret = i2c_smbus_write_byte_data(client, SCALE_HI, | |
356 | (scale->vscale & 0x0F00) >> 4 | | |
357 | (scale->hscale & 0x0F00) >> 8); | |
358 | if (ret < 0) | |
359 | return ret; | |
360 | ||
361 | ret = i2c_smbus_write_byte_data(client, HSCALE_LO, | |
362 | scale->hscale & 0x00FF); | |
363 | if (ret < 0) | |
364 | return ret; | |
365 | ||
366 | ret = i2c_smbus_write_byte_data(client, VSCALE_LO, | |
367 | scale->vscale & 0x00FF); | |
368 | ||
369 | return ret; | |
370 | } | |
371 | ||
2ad90b71 | 372 | static int tw9910_set_hsync(struct i2c_client *client) |
ed922a89 | 373 | { |
faa58261 | 374 | struct tw9910_priv *priv = to_tw9910(client); |
ed922a89 KM |
375 | int ret; |
376 | ||
377 | /* bit 10 - 3 */ | |
faa58261 | 378 | ret = i2c_smbus_write_byte_data(client, HSBEGIN, |
2ad90b71 | 379 | (HSYNC_START & 0x07F8) >> 3); |
ed922a89 KM |
380 | if (ret < 0) |
381 | return ret; | |
382 | ||
383 | /* bit 10 - 3 */ | |
384 | ret = i2c_smbus_write_byte_data(client, HSEND, | |
2ad90b71 | 385 | (HSYNC_END & 0x07F8) >> 3); |
ed922a89 KM |
386 | if (ret < 0) |
387 | return ret; | |
388 | ||
faa58261 | 389 | /* So far only revisions 0 and 1 have been seen */ |
ed922a89 | 390 | /* bit 2 - 0 */ |
faa58261 KM |
391 | if (1 == priv->revision) |
392 | ret = tw9910_mask_set(client, HSLOWCTL, 0x77, | |
2ad90b71 GL |
393 | (HSYNC_START & 0x0007) << 4 | |
394 | (HSYNC_END & 0x0007)); | |
ed922a89 KM |
395 | |
396 | return ret; | |
397 | } | |
398 | ||
ed922a89 KM |
399 | static void tw9910_reset(struct i2c_client *client) |
400 | { | |
607e5ad8 | 401 | tw9910_mask_set(client, ACNTL1, SRESET, SRESET); |
ed922a89 KM |
402 | msleep(1); |
403 | } | |
404 | ||
607e5ad8 KM |
405 | static int tw9910_power(struct i2c_client *client, int enable) |
406 | { | |
407 | int ret; | |
408 | u8 acntl1; | |
409 | u8 acntl2; | |
410 | ||
411 | if (enable) { | |
412 | acntl1 = 0; | |
413 | acntl2 = 0; | |
414 | } else { | |
415 | acntl1 = CLK_PDN | Y_PDN | C_PDN; | |
416 | acntl2 = PLL_PDN; | |
417 | } | |
418 | ||
419 | ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1); | |
420 | if (ret < 0) | |
421 | return ret; | |
422 | ||
423 | return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2); | |
424 | } | |
425 | ||
2f0babb7 | 426 | static const struct tw9910_scale_ctrl *tw9910_select_norm(v4l2_std_id norm, |
2ad90b71 | 427 | u32 width, u32 height) |
ed922a89 KM |
428 | { |
429 | const struct tw9910_scale_ctrl *scale; | |
430 | const struct tw9910_scale_ctrl *ret = NULL; | |
ed922a89 KM |
431 | __u32 diff = 0xffffffff, tmp; |
432 | int size, i; | |
433 | ||
434 | if (norm & V4L2_STD_NTSC) { | |
435 | scale = tw9910_ntsc_scales; | |
436 | size = ARRAY_SIZE(tw9910_ntsc_scales); | |
437 | } else if (norm & V4L2_STD_PAL) { | |
438 | scale = tw9910_pal_scales; | |
439 | size = ARRAY_SIZE(tw9910_pal_scales); | |
440 | } else { | |
441 | return NULL; | |
442 | } | |
443 | ||
444 | for (i = 0; i < size; i++) { | |
445 | tmp = abs(width - scale[i].width) + | |
446 | abs(height - scale[i].height); | |
447 | if (tmp < diff) { | |
448 | diff = tmp; | |
449 | ret = scale + i; | |
450 | } | |
451 | } | |
452 | ||
453 | return ret; | |
454 | } | |
455 | ||
456 | /* | |
5476ea8d | 457 | * subdevice operations |
ed922a89 | 458 | */ |
979ea1dd | 459 | static int tw9910_s_stream(struct v4l2_subdev *sd, int enable) |
ed922a89 | 460 | { |
c4ce6d14 | 461 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
979ea1dd | 462 | struct tw9910_priv *priv = to_tw9910(client); |
06f292e4 | 463 | u8 val; |
607e5ad8 | 464 | int ret; |
06f292e4 KM |
465 | |
466 | if (!enable) { | |
467 | switch (priv->revision) { | |
468 | case 0: | |
469 | val = OEN_TRI_SEL_ALL_OFF_r0; | |
470 | break; | |
471 | case 1: | |
472 | val = OEN_TRI_SEL_ALL_OFF_r1; | |
473 | break; | |
474 | default: | |
475 | dev_err(&client->dev, "un-supported revision\n"); | |
476 | return -EINVAL; | |
477 | } | |
478 | } else { | |
479 | val = OEN_TRI_SEL_ALL_ON; | |
ed922a89 | 480 | |
06f292e4 KM |
481 | if (!priv->scale) { |
482 | dev_err(&client->dev, "norm select error\n"); | |
483 | return -EPERM; | |
484 | } | |
ed922a89 | 485 | |
06f292e4 KM |
486 | dev_dbg(&client->dev, "%s %dx%d\n", |
487 | priv->scale->name, | |
488 | priv->scale->width, | |
489 | priv->scale->height); | |
490 | } | |
ed922a89 | 491 | |
607e5ad8 KM |
492 | ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val); |
493 | if (ret < 0) | |
494 | return ret; | |
495 | ||
496 | return tw9910_power(client, enable); | |
ed922a89 KM |
497 | } |
498 | ||
2f0babb7 GL |
499 | static int tw9910_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) |
500 | { | |
501 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
502 | struct tw9910_priv *priv = to_tw9910(client); | |
503 | ||
504 | *norm = priv->norm; | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
979ea1dd | 509 | static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) |
ed922a89 | 510 | { |
2f0babb7 GL |
511 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
512 | struct tw9910_priv *priv = to_tw9910(client); | |
1f3375e0 HV |
513 | const unsigned hact = 720; |
514 | const unsigned hdelay = 15; | |
515 | unsigned vact; | |
516 | unsigned vdelay; | |
517 | int ret; | |
ed922a89 | 518 | |
2f0babb7 GL |
519 | if (!(norm & (V4L2_STD_NTSC | V4L2_STD_PAL))) |
520 | return -EINVAL; | |
ed922a89 | 521 | |
2f0babb7 | 522 | priv->norm = norm; |
1f3375e0 HV |
523 | if (norm & V4L2_STD_525_60) { |
524 | vact = 240; | |
525 | vdelay = 18; | |
526 | ret = tw9910_mask_set(client, VVBI, 0x10, 0x10); | |
527 | } else { | |
528 | vact = 288; | |
529 | vdelay = 24; | |
530 | ret = tw9910_mask_set(client, VVBI, 0x10, 0x00); | |
531 | } | |
532 | if (!ret) | |
533 | ret = i2c_smbus_write_byte_data(client, CROP_HI, | |
534 | ((vdelay >> 2) & 0xc0) | | |
535 | ((vact >> 4) & 0x30) | | |
536 | ((hdelay >> 6) & 0x0c) | | |
537 | ((hact >> 8) & 0x03)); | |
538 | if (!ret) | |
539 | ret = i2c_smbus_write_byte_data(client, VDELAY_LO, | |
540 | vdelay & 0xff); | |
541 | if (!ret) | |
542 | ret = i2c_smbus_write_byte_data(client, VACTIVE_LO, | |
543 | vact & 0xff); | |
2f0babb7 | 544 | |
1f3375e0 | 545 | return ret; |
ed922a89 KM |
546 | } |
547 | ||
ed922a89 | 548 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
979ea1dd GL |
549 | static int tw9910_g_register(struct v4l2_subdev *sd, |
550 | struct v4l2_dbg_register *reg) | |
ed922a89 | 551 | { |
c4ce6d14 | 552 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
ed922a89 KM |
553 | int ret; |
554 | ||
555 | if (reg->reg > 0xff) | |
556 | return -EINVAL; | |
557 | ||
15c4fee3 | 558 | reg->size = 1; |
40e2e092 | 559 | ret = i2c_smbus_read_byte_data(client, reg->reg); |
ed922a89 KM |
560 | if (ret < 0) |
561 | return ret; | |
562 | ||
5d28d525 GL |
563 | /* |
564 | * ret = int | |
ed922a89 KM |
565 | * reg->val = __u64 |
566 | */ | |
567 | reg->val = (__u64)ret; | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
979ea1dd | 572 | static int tw9910_s_register(struct v4l2_subdev *sd, |
977ba3b1 | 573 | const struct v4l2_dbg_register *reg) |
ed922a89 | 574 | { |
c4ce6d14 | 575 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
ed922a89 KM |
576 | |
577 | if (reg->reg > 0xff || | |
578 | reg->val > 0xff) | |
579 | return -EINVAL; | |
580 | ||
40e2e092 | 581 | return i2c_smbus_write_byte_data(client, reg->reg, reg->val); |
ed922a89 KM |
582 | } |
583 | #endif | |
584 | ||
4ec10bac LP |
585 | static int tw9910_s_power(struct v4l2_subdev *sd, int on) |
586 | { | |
587 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 588 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
9aea470b | 589 | struct tw9910_priv *priv = to_tw9910(client); |
4ec10bac | 590 | |
9aea470b | 591 | return soc_camera_set_power(&client->dev, ssdd, priv->clk, on); |
4ec10bac LP |
592 | } |
593 | ||
2ad90b71 | 594 | static int tw9910_set_frame(struct v4l2_subdev *sd, u32 *width, u32 *height) |
ed922a89 | 595 | { |
c4ce6d14 | 596 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
979ea1dd | 597 | struct tw9910_priv *priv = to_tw9910(client); |
2ad90b71 GL |
598 | int ret = -EINVAL; |
599 | u8 val; | |
ed922a89 KM |
600 | |
601 | /* | |
602 | * select suitable norm | |
603 | */ | |
2f0babb7 | 604 | priv->scale = tw9910_select_norm(priv->norm, *width, *height); |
ed922a89 | 605 | if (!priv->scale) |
6d756112 | 606 | goto tw9910_set_fmt_error; |
ed922a89 KM |
607 | |
608 | /* | |
609 | * reset hardware | |
610 | */ | |
40e2e092 | 611 | tw9910_reset(client); |
6d756112 | 612 | |
ed922a89 KM |
613 | /* |
614 | * set bus width | |
615 | */ | |
616 | val = 0x00; | |
617 | if (SOCAM_DATAWIDTH_16 == priv->info->buswidth) | |
618 | val = LEN; | |
619 | ||
40e2e092 | 620 | ret = tw9910_mask_set(client, OPFORM, LEN, val); |
ed922a89 | 621 | if (ret < 0) |
6d756112 | 622 | goto tw9910_set_fmt_error; |
ed922a89 KM |
623 | |
624 | /* | |
625 | * select MPOUT behavior | |
626 | */ | |
627 | switch (priv->info->mpout) { | |
628 | case TW9910_MPO_VLOSS: | |
629 | val = RTSEL_VLOSS; break; | |
630 | case TW9910_MPO_HLOCK: | |
631 | val = RTSEL_HLOCK; break; | |
632 | case TW9910_MPO_SLOCK: | |
633 | val = RTSEL_SLOCK; break; | |
634 | case TW9910_MPO_VLOCK: | |
635 | val = RTSEL_VLOCK; break; | |
636 | case TW9910_MPO_MONO: | |
637 | val = RTSEL_MONO; break; | |
638 | case TW9910_MPO_DET50: | |
639 | val = RTSEL_DET50; break; | |
640 | case TW9910_MPO_FIELD: | |
641 | val = RTSEL_FIELD; break; | |
642 | case TW9910_MPO_RTCO: | |
643 | val = RTSEL_RTCO; break; | |
644 | default: | |
645 | val = 0; | |
646 | } | |
647 | ||
40e2e092 | 648 | ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val); |
ed922a89 | 649 | if (ret < 0) |
6d756112 | 650 | goto tw9910_set_fmt_error; |
ed922a89 KM |
651 | |
652 | /* | |
653 | * set scale | |
654 | */ | |
40e2e092 | 655 | ret = tw9910_set_scale(client, priv->scale); |
ed922a89 | 656 | if (ret < 0) |
6d756112 | 657 | goto tw9910_set_fmt_error; |
ed922a89 | 658 | |
ed922a89 KM |
659 | /* |
660 | * set hsync | |
661 | */ | |
2ad90b71 | 662 | ret = tw9910_set_hsync(client); |
6d756112 KM |
663 | if (ret < 0) |
664 | goto tw9910_set_fmt_error; | |
665 | ||
2ad90b71 GL |
666 | *width = priv->scale->width; |
667 | *height = priv->scale->height; | |
123ab622 | 668 | |
6d756112 KM |
669 | return ret; |
670 | ||
671 | tw9910_set_fmt_error: | |
672 | ||
40e2e092 | 673 | tw9910_reset(client); |
6d756112 | 674 | priv->scale = NULL; |
ed922a89 KM |
675 | |
676 | return ret; | |
677 | } | |
678 | ||
10d5509c HV |
679 | static int tw9910_get_selection(struct v4l2_subdev *sd, |
680 | struct v4l2_subdev_pad_config *cfg, | |
681 | struct v4l2_subdev_selection *sel) | |
6a6c8786 | 682 | { |
c4ce6d14 | 683 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2f0babb7 | 684 | struct tw9910_priv *priv = to_tw9910(client); |
6a6c8786 | 685 | |
10d5509c HV |
686 | if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) |
687 | return -EINVAL; | |
688 | /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */ | |
689 | if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS) | |
690 | return -EINVAL; | |
2ad90b71 | 691 | |
10d5509c HV |
692 | sel->r.left = 0; |
693 | sel->r.top = 0; | |
2f0babb7 | 694 | if (priv->norm & V4L2_STD_NTSC) { |
10d5509c HV |
695 | sel->r.width = 640; |
696 | sel->r.height = 480; | |
2ad90b71 | 697 | } else { |
10d5509c HV |
698 | sel->r.width = 768; |
699 | sel->r.height = 576; | |
2ad90b71 | 700 | } |
6a6c8786 GL |
701 | return 0; |
702 | } | |
703 | ||
da298c6d HV |
704 | static int tw9910_get_fmt(struct v4l2_subdev *sd, |
705 | struct v4l2_subdev_pad_config *cfg, | |
706 | struct v4l2_subdev_format *format) | |
6a6c8786 | 707 | { |
da298c6d | 708 | struct v4l2_mbus_framefmt *mf = &format->format; |
c4ce6d14 | 709 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
6a6c8786 | 710 | struct tw9910_priv *priv = to_tw9910(client); |
6a6c8786 | 711 | |
da298c6d HV |
712 | if (format->pad) |
713 | return -EINVAL; | |
714 | ||
6a6c8786 | 715 | if (!priv->scale) { |
7bf6afbb LP |
716 | priv->scale = tw9910_select_norm(priv->norm, 640, 480); |
717 | if (!priv->scale) | |
718 | return -EINVAL; | |
6a6c8786 GL |
719 | } |
720 | ||
760697be GL |
721 | mf->width = priv->scale->width; |
722 | mf->height = priv->scale->height; | |
f5fe58fd | 723 | mf->code = MEDIA_BUS_FMT_UYVY8_2X8; |
9212e1d8 | 724 | mf->colorspace = V4L2_COLORSPACE_SMPTE170M; |
34cae30b | 725 | mf->field = V4L2_FIELD_INTERLACED_BT; |
6a6c8786 GL |
726 | |
727 | return 0; | |
728 | } | |
729 | ||
760697be GL |
730 | static int tw9910_s_fmt(struct v4l2_subdev *sd, |
731 | struct v4l2_mbus_framefmt *mf) | |
09e231b3 | 732 | { |
2ad90b71 | 733 | u32 width = mf->width, height = mf->height; |
760697be GL |
734 | int ret; |
735 | ||
736 | WARN_ON(mf->field != V4L2_FIELD_ANY && | |
34cae30b | 737 | mf->field != V4L2_FIELD_INTERLACED_BT); |
09e231b3 GL |
738 | |
739 | /* | |
740 | * check color format | |
741 | */ | |
f5fe58fd | 742 | if (mf->code != MEDIA_BUS_FMT_UYVY8_2X8) |
09e231b3 GL |
743 | return -EINVAL; |
744 | ||
9212e1d8 | 745 | mf->colorspace = V4L2_COLORSPACE_SMPTE170M; |
760697be | 746 | |
2ad90b71 | 747 | ret = tw9910_set_frame(sd, &width, &height); |
123ab622 | 748 | if (!ret) { |
2ad90b71 GL |
749 | mf->width = width; |
750 | mf->height = height; | |
123ab622 GL |
751 | } |
752 | return ret; | |
09e231b3 GL |
753 | } |
754 | ||
717fd5b4 HV |
755 | static int tw9910_set_fmt(struct v4l2_subdev *sd, |
756 | struct v4l2_subdev_pad_config *cfg, | |
757 | struct v4l2_subdev_format *format) | |
ed922a89 | 758 | { |
717fd5b4 | 759 | struct v4l2_mbus_framefmt *mf = &format->format; |
c4ce6d14 | 760 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2f0babb7 | 761 | struct tw9910_priv *priv = to_tw9910(client); |
ed922a89 KM |
762 | const struct tw9910_scale_ctrl *scale; |
763 | ||
717fd5b4 HV |
764 | if (format->pad) |
765 | return -EINVAL; | |
766 | ||
760697be | 767 | if (V4L2_FIELD_ANY == mf->field) { |
34cae30b KM |
768 | mf->field = V4L2_FIELD_INTERLACED_BT; |
769 | } else if (V4L2_FIELD_INTERLACED_BT != mf->field) { | |
760697be | 770 | dev_err(&client->dev, "Field type %d invalid.\n", mf->field); |
ed922a89 KM |
771 | return -EINVAL; |
772 | } | |
773 | ||
f5fe58fd | 774 | mf->code = MEDIA_BUS_FMT_UYVY8_2X8; |
9212e1d8 | 775 | mf->colorspace = V4L2_COLORSPACE_SMPTE170M; |
760697be | 776 | |
ed922a89 KM |
777 | /* |
778 | * select suitable norm | |
779 | */ | |
2f0babb7 | 780 | scale = tw9910_select_norm(priv->norm, mf->width, mf->height); |
ed922a89 KM |
781 | if (!scale) |
782 | return -EINVAL; | |
783 | ||
760697be GL |
784 | mf->width = scale->width; |
785 | mf->height = scale->height; | |
ed922a89 | 786 | |
717fd5b4 HV |
787 | if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) |
788 | return tw9910_s_fmt(sd, mf); | |
789 | cfg->try_fmt = *mf; | |
ed922a89 KM |
790 | return 0; |
791 | } | |
792 | ||
2f0babb7 | 793 | static int tw9910_video_probe(struct i2c_client *client) |
ed922a89 | 794 | { |
979ea1dd | 795 | struct tw9910_priv *priv = to_tw9910(client); |
88a67c51 | 796 | s32 id; |
4bbc6d52 | 797 | int ret; |
ed922a89 | 798 | |
ed922a89 KM |
799 | /* |
800 | * tw9910 only use 8 or 16 bit bus width | |
801 | */ | |
802 | if (SOCAM_DATAWIDTH_16 != priv->info->buswidth && | |
803 | SOCAM_DATAWIDTH_8 != priv->info->buswidth) { | |
85f8be68 | 804 | dev_err(&client->dev, "bus width error\n"); |
ed922a89 KM |
805 | return -ENODEV; |
806 | } | |
807 | ||
4bbc6d52 LP |
808 | ret = tw9910_s_power(&priv->subdev, 1); |
809 | if (ret < 0) | |
810 | return ret; | |
811 | ||
ed922a89 KM |
812 | /* |
813 | * check and show Product ID | |
4a4bc5e4 | 814 | * So far only revisions 0 and 1 have been seen |
ed922a89 | 815 | */ |
88a67c51 KM |
816 | id = i2c_smbus_read_byte_data(client, ID); |
817 | priv->revision = GET_REV(id); | |
818 | id = GET_ID(id); | |
40e2e092 | 819 | |
88a67c51 | 820 | if (0x0B != id || |
6d74e5f3 | 821 | 0x01 < priv->revision) { |
85f8be68 | 822 | dev_err(&client->dev, |
6d74e5f3 | 823 | "Product ID error %x:%x\n", |
88a67c51 | 824 | id, priv->revision); |
4bbc6d52 LP |
825 | ret = -ENODEV; |
826 | goto done; | |
ed922a89 KM |
827 | } |
828 | ||
85f8be68 | 829 | dev_info(&client->dev, |
88a67c51 | 830 | "tw9910 Product ID %0x:%0x\n", id, priv->revision); |
ed922a89 | 831 | |
2f0babb7 | 832 | priv->norm = V4L2_STD_NTSC; |
1f3375e0 | 833 | priv->scale = &tw9910_ntsc_scales[0]; |
ed922a89 | 834 | |
4bbc6d52 LP |
835 | done: |
836 | tw9910_s_power(&priv->subdev, 0); | |
837 | return ret; | |
ed922a89 KM |
838 | } |
839 | ||
979ea1dd | 840 | static struct v4l2_subdev_core_ops tw9910_subdev_core_ops = { |
ed922a89 | 841 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
979ea1dd GL |
842 | .g_register = tw9910_g_register, |
843 | .s_register = tw9910_s_register, | |
ed922a89 | 844 | #endif |
4ec10bac | 845 | .s_power = tw9910_s_power, |
ed922a89 KM |
846 | }; |
847 | ||
ebcff5fc HV |
848 | static int tw9910_enum_mbus_code(struct v4l2_subdev *sd, |
849 | struct v4l2_subdev_pad_config *cfg, | |
850 | struct v4l2_subdev_mbus_code_enum *code) | |
760697be | 851 | { |
ebcff5fc | 852 | if (code->pad || code->index) |
760697be GL |
853 | return -EINVAL; |
854 | ||
ebcff5fc | 855 | code->code = MEDIA_BUS_FMT_UYVY8_2X8; |
760697be GL |
856 | return 0; |
857 | } | |
858 | ||
0d3263f9 GL |
859 | static int tw9910_g_mbus_config(struct v4l2_subdev *sd, |
860 | struct v4l2_mbus_config *cfg) | |
861 | { | |
862 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 863 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
0d3263f9 GL |
864 | |
865 | cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER | | |
866 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
867 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
868 | V4L2_MBUS_DATA_ACTIVE_HIGH; | |
869 | cfg->type = V4L2_MBUS_PARALLEL; | |
25a34811 | 870 | cfg->flags = soc_camera_apply_board_flags(ssdd, cfg); |
0d3263f9 GL |
871 | |
872 | return 0; | |
873 | } | |
874 | ||
875 | static int tw9910_s_mbus_config(struct v4l2_subdev *sd, | |
876 | const struct v4l2_mbus_config *cfg) | |
877 | { | |
878 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 879 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
0d3263f9 | 880 | u8 val = VSSL_VVALID | HSSL_DVALID; |
25a34811 | 881 | unsigned long flags = soc_camera_apply_board_flags(ssdd, cfg); |
0d3263f9 GL |
882 | |
883 | /* | |
884 | * set OUTCTR1 | |
885 | * | |
886 | * We use VVALID and DVALID signals to control VSYNC and HSYNC | |
887 | * outputs, in this mode their polarity is inverted. | |
888 | */ | |
889 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) | |
890 | val |= HSP_HI; | |
891 | ||
892 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) | |
893 | val |= VSP_HI; | |
894 | ||
895 | return i2c_smbus_write_byte_data(client, OUTCTR1, val); | |
896 | } | |
897 | ||
dc5730f5 HV |
898 | static int tw9910_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm) |
899 | { | |
900 | *norm = V4L2_STD_NTSC | V4L2_STD_PAL; | |
901 | return 0; | |
902 | } | |
903 | ||
979ea1dd | 904 | static struct v4l2_subdev_video_ops tw9910_subdev_video_ops = { |
8774bed9 LP |
905 | .s_std = tw9910_s_std, |
906 | .g_std = tw9910_g_std, | |
979ea1dd | 907 | .s_stream = tw9910_s_stream, |
0d3263f9 GL |
908 | .g_mbus_config = tw9910_g_mbus_config, |
909 | .s_mbus_config = tw9910_s_mbus_config, | |
dc5730f5 | 910 | .g_tvnorms = tw9910_g_tvnorms, |
979ea1dd GL |
911 | }; |
912 | ||
ebcff5fc HV |
913 | static const struct v4l2_subdev_pad_ops tw9910_subdev_pad_ops = { |
914 | .enum_mbus_code = tw9910_enum_mbus_code, | |
10d5509c | 915 | .get_selection = tw9910_get_selection, |
da298c6d | 916 | .get_fmt = tw9910_get_fmt, |
717fd5b4 | 917 | .set_fmt = tw9910_set_fmt, |
ebcff5fc HV |
918 | }; |
919 | ||
979ea1dd GL |
920 | static struct v4l2_subdev_ops tw9910_subdev_ops = { |
921 | .core = &tw9910_subdev_core_ops, | |
922 | .video = &tw9910_subdev_video_ops, | |
ebcff5fc | 923 | .pad = &tw9910_subdev_pad_ops, |
979ea1dd GL |
924 | }; |
925 | ||
ed922a89 KM |
926 | /* |
927 | * i2c_driver function | |
928 | */ | |
929 | ||
930 | static int tw9910_probe(struct i2c_client *client, | |
931 | const struct i2c_device_id *did) | |
932 | ||
933 | { | |
14178aa5 GL |
934 | struct tw9910_priv *priv; |
935 | struct tw9910_video_info *info; | |
14178aa5 | 936 | struct i2c_adapter *adapter = |
40e2e092 | 937 | to_i2c_adapter(client->dev.parent); |
25a34811 | 938 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
9aea470b | 939 | int ret; |
ed922a89 | 940 | |
25a34811 | 941 | if (!ssdd || !ssdd->drv_priv) { |
14178aa5 | 942 | dev_err(&client->dev, "TW9910: missing platform data!\n"); |
ed922a89 | 943 | return -EINVAL; |
40e2e092 | 944 | } |
ed922a89 | 945 | |
25a34811 | 946 | info = ssdd->drv_priv; |
40e2e092 GL |
947 | |
948 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { | |
ed922a89 KM |
949 | dev_err(&client->dev, |
950 | "I2C-Adapter doesn't support " | |
951 | "I2C_FUNC_SMBUS_BYTE_DATA\n"); | |
952 | return -EIO; | |
953 | } | |
954 | ||
70e176a5 | 955 | priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); |
ed922a89 KM |
956 | if (!priv) |
957 | return -ENOMEM; | |
958 | ||
959 | priv->info = info; | |
979ea1dd GL |
960 | |
961 | v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops); | |
ed922a89 | 962 | |
9aea470b GL |
963 | priv->clk = v4l2_clk_get(&client->dev, "mclk"); |
964 | if (IS_ERR(priv->clk)) | |
965 | return PTR_ERR(priv->clk); | |
966 | ||
967 | ret = tw9910_video_probe(client); | |
968 | if (ret < 0) | |
969 | v4l2_clk_put(priv->clk); | |
970 | ||
971 | return ret; | |
972 | } | |
973 | ||
974 | static int tw9910_remove(struct i2c_client *client) | |
975 | { | |
976 | struct tw9910_priv *priv = to_tw9910(client); | |
977 | v4l2_clk_put(priv->clk); | |
978 | return 0; | |
ed922a89 KM |
979 | } |
980 | ||
ed922a89 KM |
981 | static const struct i2c_device_id tw9910_id[] = { |
982 | { "tw9910", 0 }, | |
983 | { } | |
984 | }; | |
985 | MODULE_DEVICE_TABLE(i2c, tw9910_id); | |
986 | ||
987 | static struct i2c_driver tw9910_i2c_driver = { | |
988 | .driver = { | |
989 | .name = "tw9910", | |
990 | }, | |
991 | .probe = tw9910_probe, | |
9aea470b | 992 | .remove = tw9910_remove, |
ed922a89 KM |
993 | .id_table = tw9910_id, |
994 | }; | |
995 | ||
c6e8d86f | 996 | module_i2c_driver(tw9910_i2c_driver); |
ed922a89 KM |
997 | |
998 | MODULE_DESCRIPTION("SoC Camera driver for tw9910"); | |
999 | MODULE_AUTHOR("Kuninori Morimoto"); | |
1000 | MODULE_LICENSE("GPL v2"); |