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Revert "[media] tvp5150: Fix breakage for serial usage"
[deliverable/linux.git] / drivers / media / i2c / tvp5150.c
CommitLineData
cd4665c5 1/*
6ac48b45 2 * tvp5150 - Texas Instruments TVP5150A/AM1 video decoder driver
cd4665c5 3 *
6ac48b45
MCC		 4 * Copyright (c) 2005,2006 Mauro Carvalho Chehab (mchehab@infradead.org)
5 * This code is placed under the terms of the GNU General Public License v2
cd4665c5
MCC		 6 */
7
cd4665c5 8#include <linux/i2c.h>
5a0e3ad6 9#include <linux/slab.h>
33b687cf 10#include <linux/videodev2.h>
cd4665c5 11#include <linux/delay.h>
09aa2609 12#include <linux/gpio/consumer.h>
7a707b89 13#include <linux/module.h>
c7d97499 14#include <media/v4l2-async.h>
6b8fe025 15#include <media/v4l2-device.h>
b5dcee22 16#include <media/i2c/tvp5150.h>
6c45ec71 17#include <media/v4l2-ctrls.h>
a2e5f1b3 18#include <media/v4l2-of.h>
cd4665c5
MCC		 19
20#include "tvp5150_reg.h"
21
785a3de1
PZ		 22#define TVP5150_H_MAX 720U
23#define TVP5150_V_MAX_525_60 480U
24#define TVP5150_V_MAX_OTHERS 576U
963ddc63
JM		 25#define TVP5150_MAX_CROP_LEFT 511
26#define TVP5150_MAX_CROP_TOP 127
27#define TVP5150_CROP_SHIFT 2
28
6ac48b45 29MODULE_DESCRIPTION("Texas Instruments TVP5150A video decoder driver");
cd4665c5
MCC		 30MODULE_AUTHOR("Mauro Carvalho Chehab");
31MODULE_LICENSE("GPL");
32
cd4665c5 33
ff699e6b 34static int debug;
2a0489d3 35module_param(debug, int, 0644);
6b8fe025 36MODULE_PARM_DESC(debug, "Debug level (0-2)");
cd4665c5
MCC		 37
38struct tvp5150 {
6b8fe025 39 struct v4l2_subdev sd;
6c45ec71 40 struct v4l2_ctrl_handler hdl;
963ddc63 41 struct v4l2_rect rect;
84486d53 42
3ad96835 43 v4l2_std_id norm; /* Current set standard */
5325b427
HV		 44 u32 input;
45 u32 output;
84486d53 46 int enable;
a2e5f1b3
JMC		 47
48 enum v4l2_mbus_type mbus_type;
cd4665c5
MCC		 49};
50
6b8fe025 51static inline struct tvp5150 *to_tvp5150(struct v4l2_subdev *sd)
cd4665c5 52{
6b8fe025
HV		 53 return container_of(sd, struct tvp5150, sd);
54}
55
6c45ec71
HV		 56static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
57{
58 return &container_of(ctrl->handler, struct tvp5150, hdl)->sd;
59}
60
6b8fe025
HV		 61static int tvp5150_read(struct v4l2_subdev *sd, unsigned char addr)
62{
63 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5 64 int rc;
e35ce2e4
LP		 65
66 rc = i2c_smbus_read_byte_data(c, addr);
67 if (rc < 0) {
68 v4l2_err(sd, "i2c i/o error: rc == %d\n", rc);
69 return rc;
8cd0d4ca 70 }
e1bc80ad 71
e35ce2e4 72 v4l2_dbg(2, debug, sd, "tvp5150: read 0x%02x = 0x%02x\n", addr, rc);
cd4665c5 73
e35ce2e4 74 return rc;
cd4665c5
MCC		 75}
76
6b8fe025 77static inline void tvp5150_write(struct v4l2_subdev *sd, unsigned char addr,
84486d53 78 unsigned char value)
cd4665c5 79{
6b8fe025 80 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5 81 int rc;
cd4665c5 82
e35ce2e4
LP		 83 v4l2_dbg(2, debug, sd, "tvp5150: writing 0x%02x 0x%02x\n", addr, value);
84 rc = i2c_smbus_write_byte_data(c, addr, value);
85 if (rc < 0)
86 v4l2_dbg(0, debug, sd, "i2c i/o error: rc == %d\n", rc);
cd4665c5
MCC		 87}
88
6b8fe025
HV		 89static void dump_reg_range(struct v4l2_subdev *sd, char *s, u8 init,
90 const u8 end, int max_line)
3ad96835 91{
6b8fe025 92 int i = 0;
3ad96835 93
6b8fe025
HV		 94 while (init != (u8)(end + 1)) {
95 if ((i % max_line) == 0) {
96 if (i > 0)
3ad96835 97 printk("\n");
6b8fe025 98 printk("tvp5150: %s reg 0x%02x = ", s, init);
3ad96835 99 }
6b8fe025 100 printk("%02x ", tvp5150_read(sd, init));
3ad96835
MCC		 101
102 init++;
103 i++;
104 }
105 printk("\n");
106}
107
6b8fe025 108static int tvp5150_log_status(struct v4l2_subdev *sd)
cd4665c5 109{
84486d53 110 printk("tvp5150: Video input source selection #1 = 0x%02x\n",
6b8fe025 111 tvp5150_read(sd, TVP5150_VD_IN_SRC_SEL_1));
84486d53 112 printk("tvp5150: Analog channel controls = 0x%02x\n",
6b8fe025 113 tvp5150_read(sd, TVP5150_ANAL_CHL_CTL));
84486d53 114 printk("tvp5150: Operation mode controls = 0x%02x\n",
6b8fe025 115 tvp5150_read(sd, TVP5150_OP_MODE_CTL));
84486d53 116 printk("tvp5150: Miscellaneous controls = 0x%02x\n",
6b8fe025 117 tvp5150_read(sd, TVP5150_MISC_CTL));
3ad96835 118 printk("tvp5150: Autoswitch mask= 0x%02x\n",
6b8fe025 119 tvp5150_read(sd, TVP5150_AUTOSW_MSK));
84486d53 120 printk("tvp5150: Color killer threshold control = 0x%02x\n",
6b8fe025 121 tvp5150_read(sd, TVP5150_COLOR_KIL_THSH_CTL));
3ad96835 122 printk("tvp5150: Luminance processing controls #1 #2 and #3 = %02x %02x %02x\n",
6b8fe025
HV		 123 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_1),
124 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_2),
125 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_3));
84486d53 126 printk("tvp5150: Brightness control = 0x%02x\n",
6b8fe025 127 tvp5150_read(sd, TVP5150_BRIGHT_CTL));
84486d53 128 printk("tvp5150: Color saturation control = 0x%02x\n",
6b8fe025 129 tvp5150_read(sd, TVP5150_SATURATION_CTL));
84486d53 130 printk("tvp5150: Hue control = 0x%02x\n",
6b8fe025 131 tvp5150_read(sd, TVP5150_HUE_CTL));
84486d53 132 printk("tvp5150: Contrast control = 0x%02x\n",
6b8fe025 133 tvp5150_read(sd, TVP5150_CONTRAST_CTL));
84486d53 134 printk("tvp5150: Outputs and data rates select = 0x%02x\n",
6b8fe025 135 tvp5150_read(sd, TVP5150_DATA_RATE_SEL));
84486d53 136 printk("tvp5150: Configuration shared pins = 0x%02x\n",
6b8fe025 137 tvp5150_read(sd, TVP5150_CONF_SHARED_PIN));
3ad96835 138 printk("tvp5150: Active video cropping start = 0x%02x%02x\n",
6b8fe025
HV		 139 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_MSB),
140 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_LSB));
3ad96835 141 printk("tvp5150: Active video cropping stop = 0x%02x%02x\n",
6b8fe025
HV		 142 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_MSB),
143 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_LSB));
84486d53 144 printk("tvp5150: Genlock/RTC = 0x%02x\n",
6b8fe025 145 tvp5150_read(sd, TVP5150_GENLOCK));
84486d53 146 printk("tvp5150: Horizontal sync start = 0x%02x\n",
6b8fe025 147 tvp5150_read(sd, TVP5150_HORIZ_SYNC_START));
84486d53 148 printk("tvp5150: Vertical blanking start = 0x%02x\n",
6b8fe025 149 tvp5150_read(sd, TVP5150_VERT_BLANKING_START));
84486d53 150 printk("tvp5150: Vertical blanking stop = 0x%02x\n",
6b8fe025 151 tvp5150_read(sd, TVP5150_VERT_BLANKING_STOP));
3ad96835 152 printk("tvp5150: Chrominance processing control #1 and #2 = %02x %02x\n",
6b8fe025
HV		 153 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_1),
154 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_2));
84486d53 155 printk("tvp5150: Interrupt reset register B = 0x%02x\n",
6b8fe025 156 tvp5150_read(sd, TVP5150_INT_RESET_REG_B));
84486d53 157 printk("tvp5150: Interrupt enable register B = 0x%02x\n",
6b8fe025 158 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_B));
84486d53 159 printk("tvp5150: Interrupt configuration register B = 0x%02x\n",
6b8fe025 160 tvp5150_read(sd, TVP5150_INTT_CONFIG_REG_B));
84486d53 161 printk("tvp5150: Video standard = 0x%02x\n",
6b8fe025 162 tvp5150_read(sd, TVP5150_VIDEO_STD));
3ad96835 163 printk("tvp5150: Chroma gain factor: Cb=0x%02x Cr=0x%02x\n",
6b8fe025
HV		 164 tvp5150_read(sd, TVP5150_CB_GAIN_FACT),
165 tvp5150_read(sd, TVP5150_CR_GAIN_FACTOR));
84486d53 166 printk("tvp5150: Macrovision on counter = 0x%02x\n",
6b8fe025 167 tvp5150_read(sd, TVP5150_MACROVISION_ON_CTR));
84486d53 168 printk("tvp5150: Macrovision off counter = 0x%02x\n",
6b8fe025 169 tvp5150_read(sd, TVP5150_MACROVISION_OFF_CTR));
3ad96835 170 printk("tvp5150: ITU-R BT.656.%d timing(TVP5150AM1 only)\n",
6b8fe025 171 (tvp5150_read(sd, TVP5150_REV_SELECT) & 1) ? 3 : 4);
3ad96835 172 printk("tvp5150: Device ID = %02x%02x\n",
6b8fe025
HV		 173 tvp5150_read(sd, TVP5150_MSB_DEV_ID),
174 tvp5150_read(sd, TVP5150_LSB_DEV_ID));
3ad96835 175 printk("tvp5150: ROM version = (hex) %02x.%02x\n",
6b8fe025
HV		 176 tvp5150_read(sd, TVP5150_ROM_MAJOR_VER),
177 tvp5150_read(sd, TVP5150_ROM_MINOR_VER));
3ad96835 178 printk("tvp5150: Vertical line count = 0x%02x%02x\n",
6b8fe025
HV		 179 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_MSB),
180 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_LSB));
84486d53 181 printk("tvp5150: Interrupt status register B = 0x%02x\n",
6b8fe025 182 tvp5150_read(sd, TVP5150_INT_STATUS_REG_B));
84486d53 183 printk("tvp5150: Interrupt active register B = 0x%02x\n",
6b8fe025 184 tvp5150_read(sd, TVP5150_INT_ACTIVE_REG_B));
3ad96835 185 printk("tvp5150: Status regs #1 to #5 = %02x %02x %02x %02x %02x\n",
6b8fe025
HV		 186 tvp5150_read(sd, TVP5150_STATUS_REG_1),
187 tvp5150_read(sd, TVP5150_STATUS_REG_2),
188 tvp5150_read(sd, TVP5150_STATUS_REG_3),
189 tvp5150_read(sd, TVP5150_STATUS_REG_4),
190 tvp5150_read(sd, TVP5150_STATUS_REG_5));
3ad96835 191
6b8fe025
HV		 192 dump_reg_range(sd, "Teletext filter 1", TVP5150_TELETEXT_FIL1_INI,
193 TVP5150_TELETEXT_FIL1_END, 8);
194 dump_reg_range(sd, "Teletext filter 2", TVP5150_TELETEXT_FIL2_INI,
195 TVP5150_TELETEXT_FIL2_END, 8);
3ad96835 196
84486d53 197 printk("tvp5150: Teletext filter enable = 0x%02x\n",
6b8fe025 198 tvp5150_read(sd, TVP5150_TELETEXT_FIL_ENA));
84486d53 199 printk("tvp5150: Interrupt status register A = 0x%02x\n",
6b8fe025 200 tvp5150_read(sd, TVP5150_INT_STATUS_REG_A));
84486d53 201 printk("tvp5150: Interrupt enable register A = 0x%02x\n",
6b8fe025 202 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_A));
84486d53 203 printk("tvp5150: Interrupt configuration = 0x%02x\n",
6b8fe025 204 tvp5150_read(sd, TVP5150_INT_CONF));
84486d53 205 printk("tvp5150: VDP status register = 0x%02x\n",
6b8fe025 206 tvp5150_read(sd, TVP5150_VDP_STATUS_REG));
84486d53 207 printk("tvp5150: FIFO word count = 0x%02x\n",
6b8fe025 208 tvp5150_read(sd, TVP5150_FIFO_WORD_COUNT));
84486d53 209 printk("tvp5150: FIFO interrupt threshold = 0x%02x\n",
6b8fe025 210 tvp5150_read(sd, TVP5150_FIFO_INT_THRESHOLD));
84486d53 211 printk("tvp5150: FIFO reset = 0x%02x\n",
6b8fe025 212 tvp5150_read(sd, TVP5150_FIFO_RESET));
84486d53 213 printk("tvp5150: Line number interrupt = 0x%02x\n",
6b8fe025 214 tvp5150_read(sd, TVP5150_LINE_NUMBER_INT));
3ad96835 215 printk("tvp5150: Pixel alignment register = 0x%02x%02x\n",
6b8fe025
HV		 216 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_HIGH),
217 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_LOW));
84486d53 218 printk("tvp5150: FIFO output control = 0x%02x\n",
6b8fe025 219 tvp5150_read(sd, TVP5150_FIFO_OUT_CTRL));
3ad96835 220 printk("tvp5150: Full field enable = 0x%02x\n",
6b8fe025 221 tvp5150_read(sd, TVP5150_FULL_FIELD_ENA));
84486d53 222 printk("tvp5150: Full field mode register = 0x%02x\n",
6b8fe025 223 tvp5150_read(sd, TVP5150_FULL_FIELD_MODE_REG));
3ad96835 224
6b8fe025
HV		 225 dump_reg_range(sd, "CC data", TVP5150_CC_DATA_INI,
226 TVP5150_CC_DATA_END, 8);
3ad96835 227
6b8fe025
HV		 228 dump_reg_range(sd, "WSS data", TVP5150_WSS_DATA_INI,
229 TVP5150_WSS_DATA_END, 8);
3ad96835 230
6b8fe025
HV		 231 dump_reg_range(sd, "VPS data", TVP5150_VPS_DATA_INI,
232 TVP5150_VPS_DATA_END, 8);
3ad96835 233
6b8fe025
HV		 234 dump_reg_range(sd, "VITC data", TVP5150_VITC_DATA_INI,
235 TVP5150_VITC_DATA_END, 10);
3ad96835 236
6b8fe025
HV		 237 dump_reg_range(sd, "Line mode", TVP5150_LINE_MODE_INI,
238 TVP5150_LINE_MODE_END, 8);
239 return 0;
cd4665c5
MCC		 240}
241
242/****************************************************************************
243 Basic functions
244 ****************************************************************************/
cd4665c5 245
6b8fe025 246static inline void tvp5150_selmux(struct v4l2_subdev *sd)
cd4665c5 247{
2962fc01 248 int opmode = 0;
6b8fe025 249 struct tvp5150 *decoder = to_tvp5150(sd);
c7c0b34c 250 int input = 0;
afcc8e8c 251 int val;
84486d53 252
5325b427 253 if ((decoder->output & TVP5150_BLACK_SCREEN) || !decoder->enable)
c7c0b34c 254 input = 8;
4c86f973 255
5325b427 256 switch (decoder->input) {
c7c0b34c
HV		 257 case TVP5150_COMPOSITE1:
258 input |= 2;
259 /* fall through */
260 case TVP5150_COMPOSITE0:
c0477ad9 261 break;
c7c0b34c 262 case TVP5150_SVIDEO:
c0477ad9 263 default:
c7c0b34c 264 input |= 1;
c0477ad9
MCC		 265 break;
266 }
267
6b8fe025 268 v4l2_dbg(1, debug, sd, "Selecting video route: route input=%i, output=%i "
12500f07 269 "=> tvp5150 input=%i, opmode=%i\n",
5325b427
HV		 270 decoder->input, decoder->output,
271 input, opmode);
12500f07 272
6b8fe025
HV		 273 tvp5150_write(sd, TVP5150_OP_MODE_CTL, opmode);
274 tvp5150_write(sd, TVP5150_VD_IN_SRC_SEL_1, input);
f4b8b3ae
MCC		 275
276 /* Svideo should enable YCrCb output and disable GPCL output
277 * For Composite and TV, it should be the reverse
278 */
6b8fe025 279 val = tvp5150_read(sd, TVP5150_MISC_CTL);
8cd0d4ca
DL		 280 if (val < 0) {
281 v4l2_err(sd, "%s: failed with error = %d\n", __func__, val);
282 return;
283 }
284
5325b427 285 if (decoder->input == TVP5150_SVIDEO)
f4b8b3ae
MCC		 286 val = (val & ~0x40) | 0x10;
287 else
288 val = (val & ~0x10) | 0x40;
6b8fe025 289 tvp5150_write(sd, TVP5150_MISC_CTL, val);
cd4665c5
MCC		 290};
291
e1bc80ad
MCC		 292struct i2c_reg_value {
293 unsigned char reg;
294 unsigned char value;
295};
296
297/* Default values as sugested at TVP5150AM1 datasheet */
298static const struct i2c_reg_value tvp5150_init_default[] = {
299 { /* 0x00 */
300 TVP5150_VD_IN_SRC_SEL_1,0x00
301 },
302 { /* 0x01 */
303 TVP5150_ANAL_CHL_CTL,0x15
304 },
305 { /* 0x02 */
306 TVP5150_OP_MODE_CTL,0x00
307 },
308 { /* 0x03 */
309 TVP5150_MISC_CTL,0x01
310 },
311 { /* 0x06 */
312 TVP5150_COLOR_KIL_THSH_CTL,0x10
313 },
314 { /* 0x07 */
315 TVP5150_LUMA_PROC_CTL_1,0x60
316 },
317 { /* 0x08 */
318 TVP5150_LUMA_PROC_CTL_2,0x00
319 },
320 { /* 0x09 */
321 TVP5150_BRIGHT_CTL,0x80
322 },
323 { /* 0x0a */
324 TVP5150_SATURATION_CTL,0x80
325 },
326 { /* 0x0b */
327 TVP5150_HUE_CTL,0x00
328 },
329 { /* 0x0c */
330 TVP5150_CONTRAST_CTL,0x80
331 },
332 { /* 0x0d */
333 TVP5150_DATA_RATE_SEL,0x47
334 },
335 { /* 0x0e */
336 TVP5150_LUMA_PROC_CTL_3,0x00
337 },
338 { /* 0x0f */
339 TVP5150_CONF_SHARED_PIN,0x08
340 },
341 { /* 0x11 */
342 TVP5150_ACT_VD_CROP_ST_MSB,0x00
343 },
344 { /* 0x12 */
345 TVP5150_ACT_VD_CROP_ST_LSB,0x00
346 },
347 { /* 0x13 */
348 TVP5150_ACT_VD_CROP_STP_MSB,0x00
349 },
350 { /* 0x14 */
351 TVP5150_ACT_VD_CROP_STP_LSB,0x00
352 },
353 { /* 0x15 */
354 TVP5150_GENLOCK,0x01
355 },
356 { /* 0x16 */
357 TVP5150_HORIZ_SYNC_START,0x80
358 },
359 { /* 0x18 */
360 TVP5150_VERT_BLANKING_START,0x00
361 },
362 { /* 0x19 */
363 TVP5150_VERT_BLANKING_STOP,0x00
364 },
365 { /* 0x1a */
366 TVP5150_CHROMA_PROC_CTL_1,0x0c
367 },
368 { /* 0x1b */
369 TVP5150_CHROMA_PROC_CTL_2,0x14
370 },
371 { /* 0x1c */
372 TVP5150_INT_RESET_REG_B,0x00
373 },
374 { /* 0x1d */
375 TVP5150_INT_ENABLE_REG_B,0x00
376 },
377 { /* 0x1e */
378 TVP5150_INTT_CONFIG_REG_B,0x00
379 },
380 { /* 0x28 */
381 TVP5150_VIDEO_STD,0x00
382 },
383 { /* 0x2e */
384 TVP5150_MACROVISION_ON_CTR,0x0f
385 },
386 { /* 0x2f */
387 TVP5150_MACROVISION_OFF_CTR,0x01
388 },
389 { /* 0xbb */
390 TVP5150_TELETEXT_FIL_ENA,0x00
391 },
392 { /* 0xc0 */
393 TVP5150_INT_STATUS_REG_A,0x00
394 },
395 { /* 0xc1 */
396 TVP5150_INT_ENABLE_REG_A,0x00
397 },
398 { /* 0xc2 */
399 TVP5150_INT_CONF,0x04
400 },
401 { /* 0xc8 */
402 TVP5150_FIFO_INT_THRESHOLD,0x80
403 },
404 { /* 0xc9 */
405 TVP5150_FIFO_RESET,0x00
406 },
407 { /* 0xca */
408 TVP5150_LINE_NUMBER_INT,0x00
409 },
410 { /* 0xcb */
411 TVP5150_PIX_ALIGN_REG_LOW,0x4e
412 },
413 { /* 0xcc */
414 TVP5150_PIX_ALIGN_REG_HIGH,0x00
415 },
416 { /* 0xcd */
417 TVP5150_FIFO_OUT_CTRL,0x01
418 },
419 { /* 0xcf */
3ad96835 420 TVP5150_FULL_FIELD_ENA,0x00
e1bc80ad
MCC		 421 },
422 { /* 0xd0 */
3ad96835 423 TVP5150_LINE_MODE_INI,0x00
e1bc80ad
MCC		 424 },
425 { /* 0xfc */
426 TVP5150_FULL_FIELD_MODE_REG,0x7f
427 },
428 { /* end of data */
429 0xff,0xff
430 }
431};
432
433/* Default values as sugested at TVP5150AM1 datasheet */
434static const struct i2c_reg_value tvp5150_init_enable[] = {
435 {
436 TVP5150_CONF_SHARED_PIN, 2
437 },{ /* Automatic offset and AGC enabled */
438 TVP5150_ANAL_CHL_CTL, 0x15
439 },{ /* Activate YCrCb output 0x9 or 0xd ? */
440 TVP5150_MISC_CTL, 0x6f
441 },{ /* Activates video std autodetection for all standards */
442 TVP5150_AUTOSW_MSK, 0x0
443 },{ /* Default format: 0x47. For 4:2:2: 0x40 */
444 TVP5150_DATA_RATE_SEL, 0x47
445 },{
446 TVP5150_CHROMA_PROC_CTL_1, 0x0c
447 },{
448 TVP5150_CHROMA_PROC_CTL_2, 0x54
449 },{ /* Non documented, but initialized on WinTV USB2 */
450 0x27, 0x20
451 },{
452 0xff,0xff
453 }
454};
455
6ac48b45
MCC		 456struct tvp5150_vbi_type {
457 unsigned int vbi_type;
458 unsigned int ini_line;
459 unsigned int end_line;
460 unsigned int by_field :1;
461};
462
e1bc80ad
MCC		 463struct i2c_vbi_ram_value {
464 u16 reg;
6ac48b45
MCC		 465 struct tvp5150_vbi_type type;
466 unsigned char values[16];
e1bc80ad
MCC		 467};
468
6ac48b45
MCC		 469/* This struct have the values for each supported VBI Standard
470 * by
471 tvp5150_vbi_types should follow the same order as vbi_ram_default
3ad96835
MCC		 472 * value 0 means rom position 0x10, value 1 means rom position 0x30
473 * and so on. There are 16 possible locations from 0 to 15.
474 */
3ad96835 475
a9cff90e 476static struct i2c_vbi_ram_value vbi_ram_default[] =
cd4665c5 477{
9bc7400a
HV		 478 /* FIXME: Current api doesn't handle all VBI types, those not
479 yet supported are placed under #if 0 */
480#if 0
6ac48b45
MCC		 481 {0x010, /* Teletext, SECAM, WST System A */
482 {V4L2_SLICED_TELETEXT_SECAM,6,23,1},
483 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x26,
484 0xe6, 0xb4, 0x0e, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 485 },
9bc7400a 486#endif
6ac48b45 487 {0x030, /* Teletext, PAL, WST System B */
9bc7400a 488 {V4L2_SLICED_TELETEXT_B,6,22,1},
6ac48b45
MCC		 489 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x2b,
490 0xa6, 0x72, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 491 },
9bc7400a 492#if 0
6ac48b45
MCC		 493 {0x050, /* Teletext, PAL, WST System C */
494 {V4L2_SLICED_TELETEXT_PAL_C,6,22,1},
495 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
496 0xa6, 0x98, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 497 },
6ac48b45
MCC		 498 {0x070, /* Teletext, NTSC, WST System B */
499 {V4L2_SLICED_TELETEXT_NTSC_B,10,21,1},
500 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x23,
501 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 502 },
6ac48b45
MCC		 503 {0x090, /* Tetetext, NTSC NABTS System C */
504 {V4L2_SLICED_TELETEXT_NTSC_C,10,21,1},
505 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
506 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x15, 0x00 }
e1bc80ad 507 },
6ac48b45
MCC		 508 {0x0b0, /* Teletext, NTSC-J, NABTS System D */
509 {V4L2_SLICED_TELETEXT_NTSC_D,10,21,1},
510 { 0xaa, 0xaa, 0xff, 0xff, 0xa7, 0x2e, 0x20, 0x23,
511 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 512 },
6ac48b45
MCC		 513 {0x0d0, /* Closed Caption, PAL/SECAM */
514 {V4L2_SLICED_CAPTION_625,22,22,1},
515 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
516 0xa6, 0x7b, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 517 },
9bc7400a 518#endif
6ac48b45
MCC		 519 {0x0f0, /* Closed Caption, NTSC */
520 {V4L2_SLICED_CAPTION_525,21,21,1},
521 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
522 0x69, 0x8c, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 523 },
6ac48b45 524 {0x110, /* Wide Screen Signal, PAL/SECAM */
12db5607 525 {V4L2_SLICED_WSS_625,23,23,1},
6ac48b45
MCC		 526 { 0x5b, 0x55, 0xc5, 0xff, 0x00, 0x71, 0x6e, 0x42,
527 0xa6, 0xcd, 0x0f, 0x00, 0x00, 0x00, 0x3a, 0x00 }
e1bc80ad 528 },
9bc7400a 529#if 0
6ac48b45
MCC		 530 {0x130, /* Wide Screen Signal, NTSC C */
531 {V4L2_SLICED_WSS_525,20,20,1},
532 { 0x38, 0x00, 0x3f, 0x00, 0x00, 0x71, 0x6e, 0x43,
533 0x69, 0x7c, 0x08, 0x00, 0x00, 0x00, 0x39, 0x00 }
e1bc80ad 534 },
6ac48b45
MCC		 535 {0x150, /* Vertical Interval Timecode (VITC), PAL/SECAM */
536 {V4l2_SLICED_VITC_625,6,22,0},
537 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
538 0xa6, 0x85, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 539 },
6ac48b45
MCC		 540 {0x170, /* Vertical Interval Timecode (VITC), NTSC */
541 {V4l2_SLICED_VITC_525,10,20,0},
542 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
543 0x69, 0x94, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 544 },
9bc7400a 545#endif
6ac48b45
MCC		 546 {0x190, /* Video Program System (VPS), PAL */
547 {V4L2_SLICED_VPS,16,16,0},
548 { 0xaa, 0xaa, 0xff, 0xff, 0xba, 0xce, 0x2b, 0x0d,
549 0xa6, 0xda, 0x0b, 0x00, 0x00, 0x00, 0x60, 0x00 }
3ad96835 550 },
6ac48b45
MCC		 551 /* 0x1d0 User programmable */
552
553 /* End of struct */
554 { (u16)-1 }
e1bc80ad 555};
4c86f973 556
6b8fe025 557static int tvp5150_write_inittab(struct v4l2_subdev *sd,
6ac48b45 558 const struct i2c_reg_value *regs)
e1bc80ad
MCC		 559{
560 while (regs->reg != 0xff) {
6b8fe025 561 tvp5150_write(sd, regs->reg, regs->value);
e1bc80ad
MCC		 562 regs++;
563 }
564 return 0;
565}
84486d53 566
6b8fe025 567static int tvp5150_vdp_init(struct v4l2_subdev *sd,
6ac48b45 568 const struct i2c_vbi_ram_value *regs)
e1bc80ad
MCC		 569{
570 unsigned int i;
cd4665c5 571
e1bc80ad 572 /* Disable Full Field */
6b8fe025 573 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
cd4665c5 574
e1bc80ad 575 /* Before programming, Line mode should be at 0xff */
6b8fe025
HV		 576 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
577 tvp5150_write(sd, i, 0xff);
cd4665c5 578
e1bc80ad 579 /* Load Ram Table */
6b8fe025
HV		 580 while (regs->reg != (u16)-1) {
581 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_HIGH, regs->reg >> 8);
582 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_LOW, regs->reg);
cd4665c5 583
6b8fe025
HV		 584 for (i = 0; i < 16; i++)
585 tvp5150_write(sd, TVP5150_VDP_CONF_RAM_DATA, regs->values[i]);
84486d53 586
e1bc80ad
MCC		 587 regs++;
588 }
589 return 0;
590}
cd4665c5 591
6ac48b45 592/* Fills VBI capabilities based on i2c_vbi_ram_value struct */
6b8fe025 593static int tvp5150_g_sliced_vbi_cap(struct v4l2_subdev *sd,
6ac48b45
MCC		 594 struct v4l2_sliced_vbi_cap *cap)
595{
6b8fe025 596 const struct i2c_vbi_ram_value *regs = vbi_ram_default;
6ac48b45
MCC		 597 int line;
598
bccfa449 599 v4l2_dbg(1, debug, sd, "g_sliced_vbi_cap\n");
6ac48b45
MCC		 600 memset(cap, 0, sizeof *cap);
601
602 while (regs->reg != (u16)-1 ) {
603 for (line=regs->type.ini_line;line<=regs->type.end_line;line++) {
604 cap->service_lines[0][line] |= regs->type.vbi_type;
605 }
606 cap->service_set |= regs->type.vbi_type;
607
608 regs++;
609 }
6b8fe025 610 return 0;
6ac48b45
MCC		 611}
612
3ad96835
MCC		 613/* Set vbi processing
614 * type - one of tvp5150_vbi_types
615 * line - line to gather data
616 * fields: bit 0 field1, bit 1, field2
617 * flags (default=0xf0) is a bitmask, were set means:
618 * bit 7: enable filtering null bytes on CC
619 * bit 6: send data also to FIFO
620 * bit 5: don't allow data with errors on FIFO
621 * bit 4: enable ECC when possible
622 * pix_align = pix alignment:
623 * LSB = field1
624 * MSB = field2
625 */
6b8fe025 626static int tvp5150_set_vbi(struct v4l2_subdev *sd,
2701dacb
MCC		 627 const struct i2c_vbi_ram_value *regs,
628 unsigned int type,u8 flags, int line,
629 const int fields)
3ad96835 630{
6b8fe025
HV		 631 struct tvp5150 *decoder = to_tvp5150(sd);
632 v4l2_std_id std = decoder->norm;
3ad96835 633 u8 reg;
2701dacb 634 int pos=0;
3ad96835
MCC		 635
636 if (std == V4L2_STD_ALL) {
6b8fe025 637 v4l2_err(sd, "VBI can't be configured without knowing number of lines\n");
12db5607 638 return 0;
7d5b7b98 639 } else if (std & V4L2_STD_625_50) {
3ad96835
MCC		 640 /* Don't follow NTSC Line number convension */
641 line += 3;
642 }
643
644 if (line<6||line>27)
2701dacb
MCC		 645 return 0;
646
647 while (regs->reg != (u16)-1 ) {
648 if ((type & regs->type.vbi_type) &&
649 (line>=regs->type.ini_line) &&
650 (line<=regs->type.end_line)) {
651 type=regs->type.vbi_type;
652 break;
653 }
654
655 regs++;
656 pos++;
657 }
658 if (regs->reg == (u16)-1)
659 return 0;
3ad96835 660
2701dacb 661 type=pos | (flags & 0xf0);
3ad96835
MCC		 662 reg=((line-6)<<1)+TVP5150_LINE_MODE_INI;
663
664 if (fields&1) {
6b8fe025 665 tvp5150_write(sd, reg, type);
3ad96835
MCC		 666 }
667
668 if (fields&2) {
6b8fe025 669 tvp5150_write(sd, reg+1, type);
3ad96835
MCC		 670 }
671
2701dacb 672 return type;
3ad96835
MCC		 673}
674
6b8fe025 675static int tvp5150_get_vbi(struct v4l2_subdev *sd,
12db5607
MCC		 676 const struct i2c_vbi_ram_value *regs, int line)
677{
6b8fe025
HV		 678 struct tvp5150 *decoder = to_tvp5150(sd);
679 v4l2_std_id std = decoder->norm;
12db5607 680 u8 reg;
6b8fe025 681 int pos, type = 0;
8cd0d4ca 682 int i, ret = 0;
12db5607
MCC		 683
684 if (std == V4L2_STD_ALL) {
6b8fe025 685 v4l2_err(sd, "VBI can't be configured without knowing number of lines\n");
12db5607 686 return 0;
7d5b7b98 687 } else if (std & V4L2_STD_625_50) {
12db5607
MCC		 688 /* Don't follow NTSC Line number convension */
689 line += 3;
690 }
691
6b8fe025 692 if (line < 6 || line > 27)
12db5607
MCC		 693 return 0;
694
6b8fe025 695 reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI;
12db5607 696
8cd0d4ca
DL		 697 for (i = 0; i <= 1; i++) {
698 ret = tvp5150_read(sd, reg + i);
699 if (ret < 0) {
700 v4l2_err(sd, "%s: failed with error = %d\n",
701 __func__, ret);
702 return 0;
703 }
704 pos = ret & 0x0f;
705 if (pos < 0x0f)
706 type |= regs[pos].type.vbi_type;
707 }
12db5607
MCC		 708
709 return type;
710}
6b8fe025
HV		 711
712static int tvp5150_set_std(struct v4l2_subdev *sd, v4l2_std_id std)
e1bc80ad 713{
6b8fe025
HV		 714 struct tvp5150 *decoder = to_tvp5150(sd);
715 int fmt = 0;
e1bc80ad 716
6b8fe025 717 decoder->norm = std;
e1bc80ad
MCC		 718
719 /* First tests should be against specific std */
720
26811ae0 721 if (std == V4L2_STD_NTSC_443) {
2da12fcb 722 fmt = VIDEO_STD_NTSC_4_43_BIT;
26811ae0 723 } else if (std == V4L2_STD_PAL_M) {
2da12fcb 724 fmt = VIDEO_STD_PAL_M_BIT;
26811ae0 725 } else if (std == V4L2_STD_PAL_N || std == V4L2_STD_PAL_Nc) {
2da12fcb 726 fmt = VIDEO_STD_PAL_COMBINATION_N_BIT;
e1bc80ad
MCC		 727 } else {
728 /* Then, test against generic ones */
6b8fe025 729 if (std & V4L2_STD_NTSC)
2da12fcb 730 fmt = VIDEO_STD_NTSC_MJ_BIT;
6b8fe025 731 else if (std & V4L2_STD_PAL)
2da12fcb 732 fmt = VIDEO_STD_PAL_BDGHIN_BIT;
6b8fe025 733 else if (std & V4L2_STD_SECAM)
2da12fcb 734 fmt = VIDEO_STD_SECAM_BIT;
e1bc80ad 735 }
84486d53 736
6b8fe025
HV		 737 v4l2_dbg(1, debug, sd, "Set video std register to %d.\n", fmt);
738 tvp5150_write(sd, TVP5150_VIDEO_STD, fmt);
e1bc80ad
MCC		 739 return 0;
740}
741
6b8fe025
HV		 742static int tvp5150_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
743{
744 struct tvp5150 *decoder = to_tvp5150(sd);
745
746 if (decoder->norm == std)
747 return 0;
748
963ddc63
JM		 749 /* Change cropping height limits */
750 if (std & V4L2_STD_525_60)
751 decoder->rect.height = TVP5150_V_MAX_525_60;
752 else
753 decoder->rect.height = TVP5150_V_MAX_OTHERS;
754
755
6b8fe025
HV		 756 return tvp5150_set_std(sd, std);
757}
758
759static int tvp5150_reset(struct v4l2_subdev *sd, u32 val)
e1bc80ad 760{
6b8fe025 761 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 762
e1bc80ad 763 /* Initializes TVP5150 to its default values */
6b8fe025 764 tvp5150_write_inittab(sd, tvp5150_init_default);
e1bc80ad
MCC		 765
766 /* Initializes VDP registers */
6b8fe025 767 tvp5150_vdp_init(sd, vbi_ram_default);
e1bc80ad
MCC		 768
769 /* Selects decoder input */
6b8fe025 770 tvp5150_selmux(sd);
e1bc80ad
MCC		 771
772 /* Initializes TVP5150 to stream enabled values */
6b8fe025 773 tvp5150_write_inittab(sd, tvp5150_init_enable);
e1bc80ad
MCC		 774
775 /* Initialize image preferences */
6c45ec71 776 v4l2_ctrl_handler_setup(&decoder->hdl);
e1bc80ad 777
6b8fe025 778 tvp5150_set_std(sd, decoder->norm);
a2e5f1b3
JMC		 779
780 if (decoder->mbus_type == V4L2_MBUS_PARALLEL)
781 tvp5150_write(sd, TVP5150_DATA_RATE_SEL, 0x40);
782
6b8fe025 783 return 0;
cd4665c5
MCC		 784};
785
6c45ec71 786static int tvp5150_s_ctrl(struct v4l2_ctrl *ctrl)
a6c2ba28 787{
6c45ec71 788 struct v4l2_subdev *sd = to_sd(ctrl);
a6c2ba28 789
790 switch (ctrl->id) {
791 case V4L2_CID_BRIGHTNESS:
6c45ec71 792 tvp5150_write(sd, TVP5150_BRIGHT_CTL, ctrl->val);
a6c2ba28 793 return 0;
794 case V4L2_CID_CONTRAST:
6c45ec71 795 tvp5150_write(sd, TVP5150_CONTRAST_CTL, ctrl->val);
a6c2ba28 796 return 0;
797 case V4L2_CID_SATURATION:
6c45ec71 798 tvp5150_write(sd, TVP5150_SATURATION_CTL, ctrl->val);
a6c2ba28 799 return 0;
800 case V4L2_CID_HUE:
6c45ec71 801 tvp5150_write(sd, TVP5150_HUE_CTL, ctrl->val);
a6c2ba28 802 return 0;
a6c2ba28 803 }
c0477ad9 804 return -EINVAL;
a6c2ba28 805}
806
ec2c4f3f
JM		 807static v4l2_std_id tvp5150_read_std(struct v4l2_subdev *sd)
808{
809 int val = tvp5150_read(sd, TVP5150_STATUS_REG_5);
810
811 switch (val & 0x0F) {
812 case 0x01:
813 return V4L2_STD_NTSC;
814 case 0x03:
815 return V4L2_STD_PAL;
816 case 0x05:
817 return V4L2_STD_PAL_M;
818 case 0x07:
819 return V4L2_STD_PAL_N | V4L2_STD_PAL_Nc;
820 case 0x09:
821 return V4L2_STD_NTSC_443;
822 case 0xb:
823 return V4L2_STD_SECAM;
824 default:
825 return V4L2_STD_UNKNOWN;
826 }
827}
828
ebcff5fc
HV		 829static int tvp5150_enum_mbus_code(struct v4l2_subdev *sd,
830 struct v4l2_subdev_pad_config *cfg,
831 struct v4l2_subdev_mbus_code_enum *code)
ec2c4f3f 832{
ebcff5fc 833 if (code->pad || code->index)
ec2c4f3f
JM		 834 return -EINVAL;
835
ebcff5fc 836 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
ec2c4f3f
JM		 837 return 0;
838}
839
da298c6d
HV		 840static int tvp5150_fill_fmt(struct v4l2_subdev *sd,
841 struct v4l2_subdev_pad_config *cfg,
842 struct v4l2_subdev_format *format)
ec2c4f3f 843{
da298c6d 844 struct v4l2_mbus_framefmt *f;
ec2c4f3f 845 struct tvp5150 *decoder = to_tvp5150(sd);
ec2c4f3f 846
da298c6d 847 if (!format || format->pad)
ec2c4f3f
JM		 848 return -EINVAL;
849
da298c6d
HV		 850 f = &format->format;
851
ec2c4f3f
JM		 852 tvp5150_reset(sd, 0);
853
963ddc63
JM		 854 f->width = decoder->rect.width;
855 f->height = decoder->rect.height;
ec2c4f3f 856
f5fe58fd 857 f->code = MEDIA_BUS_FMT_UYVY8_2X8;
ec2c4f3f
JM		 858 f->field = V4L2_FIELD_SEQ_TB;
859 f->colorspace = V4L2_COLORSPACE_SMPTE170M;
860
861 v4l2_dbg(1, debug, sd, "width = %d, height = %d\n", f->width,
862 f->height);
863 return 0;
864}
865
4f996594 866static int tvp5150_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a)
963ddc63
JM		 867{
868 struct v4l2_rect rect = a->c;
869 struct tvp5150 *decoder = to_tvp5150(sd);
870 v4l2_std_id std;
f90580ca 871 unsigned int hmax;
963ddc63
JM		 872
873 v4l2_dbg(1, debug, sd, "%s left=%d, top=%d, width=%d, height=%d\n",
874 __func__, rect.left, rect.top, rect.width, rect.height);
875
876 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
877 return -EINVAL;
878
879 /* tvp5150 has some special limits */
880 rect.left = clamp(rect.left, 0, TVP5150_MAX_CROP_LEFT);
f90580ca
RR		 881 rect.width = clamp_t(unsigned int, rect.width,
882 TVP5150_H_MAX - TVP5150_MAX_CROP_LEFT - rect.left,
883 TVP5150_H_MAX - rect.left);
963ddc63
JM		 884 rect.top = clamp(rect.top, 0, TVP5150_MAX_CROP_TOP);
885
886 /* Calculate height based on current standard */
887 if (decoder->norm == V4L2_STD_ALL)
888 std = tvp5150_read_std(sd);
889 else
890 std = decoder->norm;
891
892 if (std & V4L2_STD_525_60)
893 hmax = TVP5150_V_MAX_525_60;
894 else
895 hmax = TVP5150_V_MAX_OTHERS;
896
f90580ca
RR		 897 rect.height = clamp_t(unsigned int, rect.height,
898 hmax - TVP5150_MAX_CROP_TOP - rect.top,
899 hmax - rect.top);
963ddc63
JM		 900
901 tvp5150_write(sd, TVP5150_VERT_BLANKING_START, rect.top);
902 tvp5150_write(sd, TVP5150_VERT_BLANKING_STOP,
903 rect.top + rect.height - hmax);
904 tvp5150_write(sd, TVP5150_ACT_VD_CROP_ST_MSB,
905 rect.left >> TVP5150_CROP_SHIFT);
906 tvp5150_write(sd, TVP5150_ACT_VD_CROP_ST_LSB,
907 rect.left | (1 << TVP5150_CROP_SHIFT));
908 tvp5150_write(sd, TVP5150_ACT_VD_CROP_STP_MSB,
909 (rect.left + rect.width - TVP5150_MAX_CROP_LEFT) >>
910 TVP5150_CROP_SHIFT);
911 tvp5150_write(sd, TVP5150_ACT_VD_CROP_STP_LSB,
912 rect.left + rect.width - TVP5150_MAX_CROP_LEFT);
913
914 decoder->rect = rect;
915
916 return 0;
917}
918
919static int tvp5150_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
920{
12bd10c7 921 struct tvp5150 *decoder = to_tvp5150(sd);
963ddc63
JM		 922
923 a->c = decoder->rect;
924 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
925
926 return 0;
927}
928
929static int tvp5150_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
930{
12bd10c7 931 struct tvp5150 *decoder = to_tvp5150(sd);
963ddc63
JM		 932 v4l2_std_id std;
933
934 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
935 return -EINVAL;
936
937 a->bounds.left = 0;
938 a->bounds.top = 0;
939 a->bounds.width = TVP5150_H_MAX;
940
941 /* Calculate height based on current standard */
942 if (decoder->norm == V4L2_STD_ALL)
943 std = tvp5150_read_std(sd);
944 else
945 std = decoder->norm;
946
947 if (std & V4L2_STD_525_60)
948 a->bounds.height = TVP5150_V_MAX_525_60;
949 else
950 a->bounds.height = TVP5150_V_MAX_OTHERS;
951
952 a->defrect = a->bounds;
953 a->pixelaspect.numerator = 1;
954 a->pixelaspect.denominator = 1;
955
956 return 0;
957}
958
dd3a46bb
LP		 959static int tvp5150_g_mbus_config(struct v4l2_subdev *sd,
960 struct v4l2_mbus_config *cfg)
961{
a2e5f1b3
JMC		 962 struct tvp5150 *decoder = to_tvp5150(sd);
963
964 cfg->type = decoder->mbus_type;
dd3a46bb
LP		 965 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING
966 | V4L2_MBUS_FIELD_EVEN_LOW | V4L2_MBUS_DATA_ACTIVE_HIGH;
967
968 return 0;
969}
970
84486d53
MCC		 971/****************************************************************************
972 I2C Command
973 ****************************************************************************/
c7c0b34c 974
460b6c08
LP		 975static int tvp5150_s_stream(struct v4l2_subdev *sd, int enable)
976{
a2e5f1b3 977 struct tvp5150 *decoder = to_tvp5150(sd);
841502d7
MCC		 978 /* Output format: 8-bit ITU-R BT.656 with embedded syncs */
979 int val = 0x09;
a2e5f1b3
JMC		 980
981 /* Output format: 8-bit 4:2:2 YUV with discrete sync */
841502d7
MCC		 982 if (decoder->mbus_type == V4L2_MBUS_PARALLEL)
983 val = 0x0d;
a2e5f1b3 984
460b6c08
LP		 985 /* Initializes TVP5150 to its default values */
986 /* # set PCLK (27MHz) */
987 tvp5150_write(sd, TVP5150_CONF_SHARED_PIN, 0x00);
988
460b6c08 989 if (enable)
841502d7 990 tvp5150_write(sd, TVP5150_MISC_CTL, val);
460b6c08
LP		 991 else
992 tvp5150_write(sd, TVP5150_MISC_CTL, 0x00);
993
994 return 0;
995}
996
5325b427
HV		 997static int tvp5150_s_routing(struct v4l2_subdev *sd,
998 u32 input, u32 output, u32 config)
6b8fe025
HV		 999{
1000 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 1001
5325b427
HV		 1002 decoder->input = input;
1003 decoder->output = output;
6b8fe025
HV		 1004 tvp5150_selmux(sd);
1005 return 0;
1006}
6ac48b45 1007
d37dad49
HV		 1008static int tvp5150_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
1009{
1010 /* this is for capturing 36 raw vbi lines
1011 if there's a way to cut off the beginning 2 vbi lines
1012 with the tvp5150 then the vbi line count could be lowered
1013 to 17 lines/field again, although I couldn't find a register
1014 which could do that cropping */
1015 if (fmt->sample_format == V4L2_PIX_FMT_GREY)
1016 tvp5150_write(sd, TVP5150_LUMA_PROC_CTL_1, 0x70);
1017 if (fmt->count[0] == 18 && fmt->count[1] == 18) {
1018 tvp5150_write(sd, TVP5150_VERT_BLANKING_START, 0x00);
1019 tvp5150_write(sd, TVP5150_VERT_BLANKING_STOP, 0x01);
1020 }
1021 return 0;
1022}
1023
1024static int tvp5150_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
6b8fe025 1025{
6b8fe025
HV		 1026 int i;
1027
6b8fe025
HV		 1028 if (svbi->service_set != 0) {
1029 for (i = 0; i <= 23; i++) {
1030 svbi->service_lines[1][i] = 0;
1031 svbi->service_lines[0][i] =
1032 tvp5150_set_vbi(sd, vbi_ram_default,
1033 svbi->service_lines[0][i], 0xf0, i, 3);
2c5aacc6 1034 }
6b8fe025
HV		 1035 /* Enables FIFO */
1036 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 1);
1037 } else {
1038 /* Disables FIFO*/
1039 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 0);
12db5607 1040
6b8fe025
HV		 1041 /* Disable Full Field */
1042 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
12db5607 1043
6b8fe025
HV		 1044 /* Disable Line modes */
1045 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
1046 tvp5150_write(sd, i, 0xff);
12db5607 1047 }
6b8fe025
HV		 1048 return 0;
1049}
12db5607 1050
d37dad49
HV		 1051static int tvp5150_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
1052{
1053 int i, mask = 0;
1054
30634e8e 1055 memset(svbi->service_lines, 0, sizeof(svbi->service_lines));
12db5607 1056
6b8fe025
HV		 1057 for (i = 0; i <= 23; i++) {
1058 svbi->service_lines[0][i] =
1059 tvp5150_get_vbi(sd, vbi_ram_default, i);
1060 mask |= svbi->service_lines[0][i];
2701dacb 1061 }
6b8fe025
HV		 1062 svbi->service_set = mask;
1063 return 0;
1064}
1065
21dcd8cc 1066#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 1067static int tvp5150_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
6b8fe025 1068{
8cd0d4ca
DL		 1069 int res;
1070
8cd0d4ca
DL		 1071 res = tvp5150_read(sd, reg->reg & 0xff);
1072 if (res < 0) {
1073 v4l2_err(sd, "%s: failed with error = %d\n", __func__, res);
1074 return res;
1075 }
1076
1077 reg->val = res;
aecde8b5 1078 reg->size = 1;
6b8fe025
HV		 1079 return 0;
1080}
84486d53 1081
977ba3b1 1082static int tvp5150_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
6b8fe025 1083{
6b8fe025
HV		 1084 tvp5150_write(sd, reg->reg & 0xff, reg->val & 0xff);
1085 return 0;
1086}
1087#endif
a6c2ba28 1088
6b8fe025
HV		 1089static int tvp5150_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1090{
1091 int status = tvp5150_read(sd, 0x88);
a6c2ba28 1092
6b8fe025
HV		 1093 vt->signal = ((status & 0x04) && (status & 0x02)) ? 0xffff : 0x0;
1094 return 0;
1095}
a6c2ba28 1096
6b8fe025
HV		 1097/* ----------------------------------------------------------------------- */
1098
6c45ec71
HV		 1099static const struct v4l2_ctrl_ops tvp5150_ctrl_ops = {
1100 .s_ctrl = tvp5150_s_ctrl,
1101};
1102
6b8fe025
HV		 1103static const struct v4l2_subdev_core_ops tvp5150_core_ops = {
1104 .log_status = tvp5150_log_status,
6b8fe025
HV		 1105 .reset = tvp5150_reset,
1106#ifdef CONFIG_VIDEO_ADV_DEBUG
1107 .g_register = tvp5150_g_register,
1108 .s_register = tvp5150_s_register,
1109#endif
1110};
1111
1112static const struct v4l2_subdev_tuner_ops tvp5150_tuner_ops = {
6b8fe025
HV		 1113 .g_tuner = tvp5150_g_tuner,
1114};
1115
1116static const struct v4l2_subdev_video_ops tvp5150_video_ops = {
8774bed9 1117 .s_std = tvp5150_s_std,
460b6c08 1118 .s_stream = tvp5150_s_stream,
6b8fe025 1119 .s_routing = tvp5150_s_routing,
963ddc63
JM		 1120 .s_crop = tvp5150_s_crop,
1121 .g_crop = tvp5150_g_crop,
1122 .cropcap = tvp5150_cropcap,
dd3a46bb 1123 .g_mbus_config = tvp5150_g_mbus_config,
32cd527f
HV		 1124};
1125
1126static const struct v4l2_subdev_vbi_ops tvp5150_vbi_ops = {
6b8fe025 1127 .g_sliced_vbi_cap = tvp5150_g_sliced_vbi_cap,
d37dad49
HV		 1128 .g_sliced_fmt = tvp5150_g_sliced_fmt,
1129 .s_sliced_fmt = tvp5150_s_sliced_fmt,
1130 .s_raw_fmt = tvp5150_s_raw_fmt,
6b8fe025
HV		 1131};
1132
ebcff5fc
HV		 1133static const struct v4l2_subdev_pad_ops tvp5150_pad_ops = {
1134 .enum_mbus_code = tvp5150_enum_mbus_code,
da298c6d
HV		 1135 .set_fmt = tvp5150_fill_fmt,
1136 .get_fmt = tvp5150_fill_fmt,
ebcff5fc
HV		 1137};
1138
6b8fe025
HV		 1139static const struct v4l2_subdev_ops tvp5150_ops = {
1140 .core = &tvp5150_core_ops,
1141 .tuner = &tvp5150_tuner_ops,
1142 .video = &tvp5150_video_ops,
32cd527f 1143 .vbi = &tvp5150_vbi_ops,
ebcff5fc 1144 .pad = &tvp5150_pad_ops,
6b8fe025
HV		 1145};
1146
1147
cd4665c5
MCC		 1148/****************************************************************************
1149 I2C Client & Driver
1150 ****************************************************************************/
cd4665c5 1151
7871597a
LP		 1152static int tvp5150_detect_version(struct tvp5150 *core)
1153{
1154 struct v4l2_subdev *sd = &core->sd;
1155 struct i2c_client *c = v4l2_get_subdevdata(sd);
1156 unsigned int i;
1157 u16 dev_id;
1158 u16 rom_ver;
1159 u8 regs[4];
1160 int res;
1161
1162 /*
1163 * Read consequent registers - TVP5150_MSB_DEV_ID, TVP5150_LSB_DEV_ID,
1164 * TVP5150_ROM_MAJOR_VER, TVP5150_ROM_MINOR_VER
1165 */
1166 for (i = 0; i < 4; i++) {
1167 res = tvp5150_read(sd, TVP5150_MSB_DEV_ID + i);
1168 if (res < 0)
1169 return res;
1170 regs[i] = res;
1171 }
1172
1173 dev_id = (regs[0] << 8) | regs[1];
1174 rom_ver = (regs[2] << 8) | regs[3];
1175
1176 v4l2_info(sd, "tvp%04x (%u.%u) chip found @ 0x%02x (%s)\n",
1177 dev_id, regs[2], regs[3], c->addr << 1, c->adapter->name);
1178
1179 if (dev_id == 0x5150 && rom_ver == 0x0321) { /* TVP51510A */
1180 v4l2_info(sd, "tvp5150a detected.\n");
1181 } else if (dev_id == 0x5150 && rom_ver == 0x0400) { /* TVP5150AM1 */
1182 v4l2_info(sd, "tvp5150am1 detected.\n");
1183
1184 /* ITU-T BT.656.4 timing */
1185 tvp5150_write(sd, TVP5150_REV_SELECT, 0);
05676b3e
LP		 1186 } else if (dev_id == 0x5151 && rom_ver == 0x0100) { /* TVP5151 */
1187 v4l2_info(sd, "tvp5151 detected.\n");
7871597a
LP		 1188 } else {
1189 v4l2_info(sd, "*** unknown tvp%04x chip detected.\n", dev_id);
1190 }
1191
1192 return 0;
1193}
1194
09aa2609
JMC		 1195static int tvp5150_init(struct i2c_client *c)
1196{
1197 struct gpio_desc *pdn_gpio;
1198 struct gpio_desc *reset_gpio;
1199
1200 pdn_gpio = devm_gpiod_get_optional(&c->dev, "pdn", GPIOD_OUT_HIGH);
1201 if (IS_ERR(pdn_gpio))
1202 return PTR_ERR(pdn_gpio);
1203
1204 if (pdn_gpio) {
1205 gpiod_set_value_cansleep(pdn_gpio, 0);
1206 /* Delay time between power supplies active and reset */
1207 msleep(20);
1208 }
1209
1210 reset_gpio = devm_gpiod_get_optional(&c->dev, "reset", GPIOD_OUT_HIGH);
1211 if (IS_ERR(reset_gpio))
1212 return PTR_ERR(reset_gpio);
1213
1214 if (reset_gpio) {
1215 /* RESETB pulse duration */
1216 ndelay(500);
1217 gpiod_set_value_cansleep(reset_gpio, 0);
1218 /* Delay time between end of reset to I2C active */
1219 usleep_range(200, 250);
1220 }
1221
1222 return 0;
1223}
1224
a2e5f1b3
JMC		 1225static int tvp5150_parse_dt(struct tvp5150 *decoder, struct device_node *np)
1226{
1227 struct v4l2_of_endpoint bus_cfg;
1228 struct device_node *ep;
1229 unsigned int flags;
1230 int ret = 0;
1231
1232 ep = of_graph_get_next_endpoint(np, NULL);
1233 if (!ep)
1234 return -EINVAL;
1235
1236 ret = v4l2_of_parse_endpoint(ep, &bus_cfg);
1237 if (ret)
1238 goto err;
1239
1240 flags = bus_cfg.bus.parallel.flags;
1241
1242 if (bus_cfg.bus_type == V4L2_MBUS_PARALLEL &&
1243 !(flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH &&
1244 flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH &&
1245 flags & V4L2_MBUS_FIELD_EVEN_LOW))
1246 return -EINVAL;
1247
1248 decoder->mbus_type = bus_cfg.bus_type;
1249
1250err:
1251 of_node_put(ep);
1252 return ret;
1253}
1254
6b8fe025
HV		 1255static int tvp5150_probe(struct i2c_client *c,
1256 const struct i2c_device_id *id)
cd4665c5 1257{
cd4665c5 1258 struct tvp5150 *core;
6b8fe025 1259 struct v4l2_subdev *sd;
a2e5f1b3 1260 struct device_node *np = c->dev.of_node;
7871597a 1261 int res;
cd4665c5
MCC		 1262
1263 /* Check if the adapter supports the needed features */
6b8fe025 1264 if (!i2c_check_functionality(c->adapter,
cd4665c5 1265 I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
6b8fe025 1266 return -EIO;
cd4665c5 1267
09aa2609
JMC		 1268 res = tvp5150_init(c);
1269 if (res)
1270 return res;
1271
c02b211d
LP		 1272 core = devm_kzalloc(&c->dev, sizeof(*core), GFP_KERNEL);
1273 if (!core)
cd4665c5 1274 return -ENOMEM;
a2e5f1b3 1275
6b8fe025 1276 sd = &core->sd;
a2e5f1b3
JMC		 1277
1278 if (IS_ENABLED(CONFIG_OF) && np) {
1279 res = tvp5150_parse_dt(core, np);
1280 if (res) {
1281 v4l2_err(sd, "DT parsing error: %d\n", res);
1282 return res;
1283 }
1284 } else {
1285 /* Default to BT.656 embedded sync */
1286 core->mbus_type = V4L2_MBUS_BT656;
1287 }
1288
6b8fe025 1289 v4l2_i2c_subdev_init(sd, c, &tvp5150_ops);
8cd0d4ca 1290
7871597a
LP		 1291 res = tvp5150_detect_version(core);
1292 if (res < 0)
1293 return res;
0e09a3c9 1294
3ad96835 1295 core->norm = V4L2_STD_ALL; /* Default is autodetect */
5325b427 1296 core->input = TVP5150_COMPOSITE1;
4c86f973 1297 core->enable = 1;
6c45ec71 1298
b1950b8d 1299 v4l2_ctrl_handler_init(&core->hdl, 5);
6c45ec71
HV		 1300 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1301 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1302 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1303 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1304 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1305 V4L2_CID_SATURATION, 0, 255, 1, 128);
1306 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1307 V4L2_CID_HUE, -128, 127, 1, 0);
b1950b8d
LP		 1308 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1309 V4L2_CID_PIXEL_RATE, 27000000,
1310 27000000, 1, 27000000);
6c45ec71
HV		 1311 sd->ctrl_handler = &core->hdl;
1312 if (core->hdl.error) {
8cd0d4ca 1313 res = core->hdl.error;
c7d97499 1314 goto err;
6c45ec71
HV		 1315 }
1316 v4l2_ctrl_handler_setup(&core->hdl);
4c86f973 1317
963ddc63
JM		 1318 /* Default is no cropping */
1319 core->rect.top = 0;
1320 if (tvp5150_read_std(sd) & V4L2_STD_525_60)
1321 core->rect.height = TVP5150_V_MAX_525_60;
1322 else
1323 core->rect.height = TVP5150_V_MAX_OTHERS;
1324 core->rect.left = 0;
1325 core->rect.width = TVP5150_H_MAX;
1326
c7d97499
JMC		 1327 res = v4l2_async_register_subdev(sd);
1328 if (res < 0)
1329 goto err;
1330
f1e5ee45 1331 if (debug > 1)
6b8fe025 1332 tvp5150_log_status(sd);
cd4665c5 1333 return 0;
c7d97499
JMC		 1334
1335err:
1336 v4l2_ctrl_handler_free(&core->hdl);
1337 return res;
cd4665c5
MCC		 1338}
1339
6b8fe025 1340static int tvp5150_remove(struct i2c_client *c)
cd4665c5 1341{
6b8fe025 1342 struct v4l2_subdev *sd = i2c_get_clientdata(c);
6c45ec71 1343 struct tvp5150 *decoder = to_tvp5150(sd);
cd4665c5 1344
6b8fe025 1345 v4l2_dbg(1, debug, sd,
e1bc80ad
MCC		 1346 "tvp5150.c: removing tvp5150 adapter on address 0x%x\n",
1347 c->addr << 1);
1348
c7d97499 1349 v4l2_async_unregister_subdev(sd);
6c45ec71 1350 v4l2_ctrl_handler_free(&decoder->hdl);
cd4665c5
MCC		 1351 return 0;
1352}
1353
1354/* ----------------------------------------------------------------------- */
1355
6b8fe025
HV		 1356static const struct i2c_device_id tvp5150_id[] = {
1357 { "tvp5150", 0 },
1358 { }
1359};
1360MODULE_DEVICE_TABLE(i2c, tvp5150_id);
84486d53 1361
7ef930a7
EG		 1362#if IS_ENABLED(CONFIG_OF)
1363static const struct of_device_id tvp5150_of_match[] = {
1364 { .compatible = "ti,tvp5150", },
1365 { /* sentinel */ },
1366};
1367MODULE_DEVICE_TABLE(of, tvp5150_of_match);
1368#endif
1369
c771145b
HV		 1370static struct i2c_driver tvp5150_driver = {
1371 .driver = {
7ef930a7 1372 .of_match_table = of_match_ptr(tvp5150_of_match),
c771145b
HV		 1373 .name = "tvp5150",
1374 },
1375 .probe = tvp5150_probe,
1376 .remove = tvp5150_remove,
1377 .id_table = tvp5150_id,
cd4665c5 1378};
c771145b 1379
c6e8d86f 1380module_i2c_driver(tvp5150_driver);
Linux kernel - Deliverables
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