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Merge remote-tracking branch 'iommu/next'
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885.h
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
d19770e5
ST		 16 */
17
18#include <linux/pci.h>
19#include <linux/i2c.h>
d19770e5 20#include <linux/kdev_t.h>
5a0e3ad6 21#include <linux/slab.h>
d19770e5 22
c0714f6c 23#include <media/v4l2-device.h>
86dd9831 24#include <media/v4l2-fh.h>
da59a4de 25#include <media/v4l2-ctrls.h>
d19770e5
ST		 26#include <media/tuner.h>
27#include <media/tveeprom.h>
453afdd9
HV		 28#include <media/videobuf2-dma-sg.h>
29#include <media/videobuf2-dvb.h>
6bda9644 30#include <media/rc-core.h>
d19770e5 31
d19770e5 32#include "cx23885-reg.h"
d647f0b7 33#include "media/drv-intf/cx2341x.h"
d19770e5 34
d19770e5
ST		 35#include <linux/mutex.h>
36
453afdd9 37#define CX23885_VERSION "0.0.4"
d19770e5
ST		 38
39#define UNSET (-1U)
40
41#define CX23885_MAXBOARDS 8
42
d19770e5
ST		 43/* Max number of inputs by card */
44#define MAX_CX23885_INPUT 8
7b888014 45#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
d19770e5 46
d19770e5
ST		 47#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
48
49#define CX23885_BOARD_NOAUTO UNSET
50#define CX23885_BOARD_UNKNOWN 0
51#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
52#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc 53#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa 54#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55 55#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835 56#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166 57#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c 58#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373 59#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7 60#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186 61#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a 62#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8 63#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c 64#define CX23885_BOARD_TBS_6920 14
579943f5 65#define CX23885_BOARD_TEVII_S470 15
c9b8b04b 66#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076 67#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
2074dffa 68#define CX23885_BOARD_HAUPPAUGE_HVR1270 18
d099becb 69#define CX23885_BOARD_HAUPPAUGE_HVR1275 19
19bc5796 70#define CX23885_BOARD_HAUPPAUGE_HVR1255 20
6b926eca 71#define CX23885_BOARD_HAUPPAUGE_HVR1210 21
493b7127 72#define CX23885_BOARD_MYGICA_X8506 22
2365b2d3 73#define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
13697380 74#define CX23885_BOARD_HAUPPAUGE_HVR1850 24
34e383dd 75#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
aee0b24c 76#define CX23885_BOARD_HAUPPAUGE_HVR1290 26
ea5697fe 77#define CX23885_BOARD_MYGICA_X8558PRO 27
0b32d65c 78#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
9028f58f 79#define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
78db8547 80#define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
0cf8af57 81#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31
2cb9ccd4 82#define CX23885_BOARD_MPX885 32
87988753 83#define CX23885_BOARD_MYGICA_X8507 33
722c90eb 84#define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34
7b134e85 85#define CX23885_BOARD_TEVII_S471 35
0ac60acb 86#define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36
f667190b 87#define CX23885_BOARD_PROF_8000 37
7c62f5a1 88#define CX23885_BOARD_HAUPPAUGE_HVR4400 38
e8d42373 89#define CX23885_BOARD_AVERMEDIA_HC81R 39
e6001482
LA		 90#define CX23885_BOARD_TBS_6981 40
91#define CX23885_BOARD_TBS_6980 41
642ca1a0 92#define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42
cce11b09 93#define CX23885_BOARD_HAUPPAUGE_IMPACTVCBE 43
46b21bba 94#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2 44
29442266 95#define CX23885_BOARD_DVBSKY_T9580 45
82c10276 96#define CX23885_BOARD_DVBSKY_T980C 46
0e6c7b01 97#define CX23885_BOARD_DVBSKY_S950C 47
61b103e8 98#define CX23885_BOARD_TT_CT2_4500_CI 48
cba5480c 99#define CX23885_BOARD_DVBSKY_S950 49
c29d6a83 100#define CX23885_BOARD_DVBSKY_S952 50
c02ef64a 101#define CX23885_BOARD_DVBSKY_T982 51
1fc77d01 102#define CX23885_BOARD_HAUPPAUGE_HVR5525 52
4a8ba331 103#define CX23885_BOARD_HAUPPAUGE_STARBURST 53
6c43a217
HV		 104#define CX23885_BOARD_VIEWCAST_260E 54
105#define CX23885_BOARD_VIEWCAST_460E 55
dd9ad4fb
SB		 106#define CX23885_BOARD_HAUPPAUGE_QUADHD_DVB 56
107#define CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC 57
d19770e5 108
6f8bee9b
ST		 109#define GPIO_0 0x00000001
110#define GPIO_1 0x00000002
111#define GPIO_2 0x00000004
112#define GPIO_3 0x00000008
113#define GPIO_4 0x00000010
114#define GPIO_5 0x00000020
115#define GPIO_6 0x00000040
116#define GPIO_7 0x00000080
117#define GPIO_8 0x00000100
118#define GPIO_9 0x00000200
f659c513
ST		 119#define GPIO_10 0x00000400
120#define GPIO_11 0x00000800
121#define GPIO_12 0x00001000
122#define GPIO_13 0x00002000
123#define GPIO_14 0x00004000
124#define GPIO_15 0x00008000
6f8bee9b 125
7b888014
ST		 126/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
127#define CX23885_NORMS (\
128 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
129 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
130 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
131 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
132
133struct cx23885_fmt {
134 char *name;
135 u32 fourcc; /* v4l2 format id */
136 int depth;
137 int flags;
138 u32 cxformat;
139};
140
7b888014
ST		 141struct cx23885_tvnorm {
142 char *name;
143 v4l2_std_id id;
144 u32 cxiformat;
145 u32 cxoformat;
146};
147
d19770e5
ST		 148enum cx23885_itype {
149 CX23885_VMUX_COMPOSITE1 = 1,
150 CX23885_VMUX_COMPOSITE2,
151 CX23885_VMUX_COMPOSITE3,
152 CX23885_VMUX_COMPOSITE4,
153 CX23885_VMUX_SVIDEO,
dac65fa1 154 CX23885_VMUX_COMPONENT,
d19770e5
ST		 155 CX23885_VMUX_TELEVISION,
156 CX23885_VMUX_CABLE,
157 CX23885_VMUX_DVB,
158 CX23885_VMUX_DEBUG,
159 CX23885_RADIO,
160};
161
579f1163
ST		 162enum cx23885_src_sel_type {
163 CX23885_SRC_SEL_EXT_656_VIDEO = 0,
164 CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
165};
166
4d63a25c
HV		 167struct cx23885_riscmem {
168 unsigned int size;
169 __le32 *cpu;
170 __le32 *jmp;
171 dma_addr_t dma;
172};
173
d19770e5
ST		 174/* buffer for one video frame */
175struct cx23885_buffer {
176 /* common v4l buffer stuff -- must be first */
2d700715 177 struct vb2_v4l2_buffer vb;
453afdd9 178 struct list_head queue;
d19770e5
ST		 179
180 /* cx23885 specific */
181 unsigned int bpl;
4d63a25c 182 struct cx23885_riscmem risc;
d19770e5
ST		 183 struct cx23885_fmt *fmt;
184 u32 count;
185};
186
187struct cx23885_input {
188 enum cx23885_itype type;
189 unsigned int vmux;
8304be88 190 unsigned int amux;
d19770e5
ST		 191 u32 gpio0, gpio1, gpio2, gpio3;
192};
193
661c7e44
ST		 194typedef enum {
195 CX23885_MPEG_UNDEFINED = 0,
7b888014
ST		 196 CX23885_MPEG_DVB,
197 CX23885_ANALOG_VIDEO,
b1b81f1d 198 CX23885_MPEG_ENCODER,
661c7e44
ST		 199} port_t;
200
d19770e5
ST		 201struct cx23885_board {
202 char *name;
7b888014 203 port_t porta, portb, portc;
10d0dcd7 204 int num_fds_portb, num_fds_portc;
7b888014
ST		 205 unsigned int tuner_type;
206 unsigned int radio_type;
207 unsigned char tuner_addr;
208 unsigned char radio_addr;
557f48d5 209 unsigned int tuner_bus;
c7712613
ST		 210
211 /* Vendors can and do run the PCIe bridge at different
212 * clock rates, driven physically by crystals on the PCBs.
25985edc 213 * The core has to accommodate this. This allows the user
c7712613
ST		 214 * to add new boards with new frequencys. The value is
215 * expressed in Hz.
216 *
217 * The core framework will default this value based on
218 * current designs, but it can vary.
219 */
220 u32 clk_freq;
d19770e5 221 struct cx23885_input input[MAX_CX23885_INPUT];
78db8547 222 int ci_type; /* for NetUP */
35045137
ST		 223 /* Force bottom field first during DMA (888 workaround) */
224 u32 force_bff;
d19770e5
ST		 225};
226
227struct cx23885_subid {
228 u16 subvendor;
229 u16 subdevice;
230 u32 card;
231};
232
233struct cx23885_i2c {
234 struct cx23885_dev *dev;
235
236 int nr;
237
238 /* i2c i/o */
239 struct i2c_adapter i2c_adap;
d19770e5
ST		 240 struct i2c_client i2c_client;
241 u32 i2c_rc;
242
243 /* 885 registers used for raw addess */
244 u32 i2c_period;
245 u32 reg_ctrl;
246 u32 reg_stat;
247 u32 reg_addr;
248 u32 reg_rdata;
249 u32 reg_wdata;
250};
251
252struct cx23885_dmaqueue {
253 struct list_head active;
d19770e5
ST		 254 u32 count;
255};
256
257struct cx23885_tsport {
258 struct cx23885_dev *dev;
259
260 int nr;
261 int sram_chno;
262
453afdd9 263 struct vb2_dvb_frontends frontends;
d19770e5
ST		 264
265 /* dma queues */
266 struct cx23885_dmaqueue mpegq;
267 u32 ts_packet_size;
268 u32 ts_packet_count;
269
270 int width;
271 int height;
272
273 spinlock_t slock;
274
275 /* registers */
276 u32 reg_gpcnt;
277 u32 reg_gpcnt_ctl;
278 u32 reg_dma_ctl;
279 u32 reg_lngth;
280 u32 reg_hw_sop_ctrl;
281 u32 reg_gen_ctrl;
282 u32 reg_bd_pkt_status;
283 u32 reg_sop_status;
284 u32 reg_fifo_ovfl_stat;
285 u32 reg_vld_misc;
286 u32 reg_ts_clk_en;
287 u32 reg_ts_int_msk;
a6a3f140 288 u32 reg_ts_int_stat;
579f1163 289 u32 reg_src_sel;
d19770e5
ST		 290
291 /* Default register vals */
292 int pci_irqmask;
293 u32 dma_ctl_val;
294 u32 ts_int_msk_val;
295 u32 gen_ctrl_val;
296 u32 ts_clk_en_val;
579f1163 297 u32 src_sel_val;
b1b81f1d
ST		 298 u32 vld_misc_val;
299 u32 hw_sop_ctrl_val;
a739a7e4
ST		 300
301 /* Allow a single tsport to have multiple frontends */
302 u32 num_frontends;
78db8547 303 void (*gate_ctrl)(struct cx23885_tsport *port, int open);
5a23b076 304 void *port_priv;
35045137
ST		 305
306 /* Workaround for a temp dvb_frontend that the tuner can attached to */
307 struct dvb_frontend analog_fe;
15472faf 308
b0b12e63
OS		 309 struct i2c_client *i2c_client_demod;
310 struct i2c_client *i2c_client_tuner;
bf5e3ef0 311 struct i2c_client *i2c_client_sec;
e450de45 312 struct i2c_client *i2c_client_ci;
b0b12e63 313
15472faf 314 int (*set_frontend)(struct dvb_frontend *fe);
5cd3b6b4 315 int (*fe_set_voltage)(struct dvb_frontend *fe,
0df289a2 316 enum fe_sec_voltage voltage);
d19770e5
ST		 317};
318
43c24078
AW		 319struct cx23885_kernel_ir {
320 struct cx23885_dev *cx;
eeefae53
AW		 321 char *name;
322 char *phys;
323
d8b4b582 324 struct rc_dev *rc;
eeefae53
AW		 325};
326
9e44d632
MM		 327struct cx23885_audio_buffer {
328 unsigned int bpl;
4d63a25c 329 struct cx23885_riscmem risc;
9529a4b0
HV		 330 void *vaddr;
331 struct scatterlist *sglist;
332 int sglen;
333 int nr_pages;
9e44d632
MM		 334};
335
336struct cx23885_audio_dev {
337 struct cx23885_dev *dev;
338
339 struct pci_dev *pci;
340
341 struct snd_card *card;
342
343 spinlock_t lock;
344
345 atomic_t count;
346
347 unsigned int dma_size;
348 unsigned int period_size;
349 unsigned int num_periods;
350
9e44d632
MM		 351 struct cx23885_audio_buffer *buf;
352
353 struct snd_pcm_substream *substream;
354};
355
d19770e5 356struct cx23885_dev {
d19770e5 357 atomic_t refcount;
c0714f6c 358 struct v4l2_device v4l2_dev;
da59a4de 359 struct v4l2_ctrl_handler ctrl_handler;
d19770e5
ST		 360
361 /* pci stuff */
362 struct pci_dev *pci;
363 unsigned char pci_rev, pci_lat;
364 int pci_bus, pci_slot;
365 u32 __iomem *lmmio;
366 u8 __iomem *bmmio;
d19770e5 367 int pci_irqmask;
dbe83a3b 368 spinlock_t pci_irqmask_lock; /* protects mask reg too */
0ac5881a 369 int hwrevision;
d19770e5 370
c7712613
ST		 371 /* This valud is board specific and is used to configure the
372 * AV core so we see nice clean and stable video and audio. */
373 u32 clk_freq;
374
44a6481d 375 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5
ST		 376 struct cx23885_i2c i2c_bus[3];
377
378 int nr;
379 struct mutex lock;
8386c27f 380 struct mutex gpio_lock;
d19770e5
ST		 381
382 /* board details */
383 unsigned int board;
384 char name[32];
385
a6a3f140 386 struct cx23885_tsport ts1, ts2;
d19770e5
ST		 387
388 /* sram configuration */
389 struct sram_channel *sram_channels;
e133be0f
ST		 390
391 enum {
392 CX23885_BRIDGE_UNDEFINED = 0,
393 CX23885_BRIDGE_885 = 885,
394 CX23885_BRIDGE_887 = 887,
25ea66e2 395 CX23885_BRIDGE_888 = 888,
e133be0f 396 } bridge;
7b888014
ST		 397
398 /* Analog video */
7b888014 399 unsigned int input;
fc1a889d 400 unsigned int audinput; /* Selectable audio input */
7b888014
ST		 401 u32 tvaudio;
402 v4l2_std_id tvnorm;
403 unsigned int tuner_type;
404 unsigned char tuner_addr;
557f48d5 405 unsigned int tuner_bus;
7b888014
ST		 406 unsigned int radio_type;
407 unsigned char radio_addr;
0d5a19f1 408 struct v4l2_subdev *sd_cx25840;
e5514f10 409 struct work_struct cx25840_work;
f59ad611
AW		 410
411 /* Infrared */
412 struct v4l2_subdev *sd_ir;
413 struct work_struct ir_rx_work;
414 unsigned long ir_rx_notifications;
415 struct work_struct ir_tx_work;
416 unsigned long ir_tx_notifications;
7b888014 417
43c24078 418 struct cx23885_kernel_ir *kernel_ir;
dbda8f70
AW		 419 atomic_t ir_input_stopping;
420
7b888014
ST		 421 /* V4l */
422 u32 freq;
423 struct video_device *video_dev;
424 struct video_device *vbi_dev;
7b888014 425
91d2d674
HV		 426 /* video capture */
427 struct cx23885_fmt *fmt;
428 unsigned int width, height;
453afdd9 429 unsigned field;
91d2d674 430
7b888014 431 struct cx23885_dmaqueue vidq;
453afdd9 432 struct vb2_queue vb2_vidq;
7b888014 433 struct cx23885_dmaqueue vbiq;
453afdd9
HV		 434 struct vb2_queue vb2_vbiq;
435
7b888014 436 spinlock_t slock;
b1b81f1d
ST		 437
438 /* MPEG Encoder ONLY settings */
439 u32 cx23417_mailbox;
5150392c 440 struct cx2341x_handler cxhdl;
b1b81f1d 441 struct video_device *v4l_device;
453afdd9 442 struct vb2_queue vb2_mpegq;
b1b81f1d
ST		 443 struct cx23885_tvnorm encodernorm;
444
9e44d632
MM		 445 /* Analog raw audio */
446 struct cx23885_audio_dev *audio_dev;
447
d19770e5
ST		 448};
449
c0714f6c
HV		 450static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
451{
452 return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
453}
454
0d5a19f1
HV		 455#define call_all(dev, o, f, args...) \
456 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
457
d6b1850d
AW		 458#define CX23885_HW_888_IR (1 << 0)
459#define CX23885_HW_AV_CORE (1 << 1)
29f8a0a5
AW		 460
461#define call_hw(dev, grpid, o, f, args...) \
462 v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
463
464extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
465
d19770e5
ST		 466#define SRAM_CH01 0 /* Video A */
467#define SRAM_CH02 1 /* VBI A */
468#define SRAM_CH03 2 /* Video B */
469#define SRAM_CH04 3 /* Transport via B */
470#define SRAM_CH05 4 /* VBI B */
471#define SRAM_CH06 5 /* Video C */
472#define SRAM_CH07 6 /* Transport via C */
473#define SRAM_CH08 7 /* Audio Internal A */
474#define SRAM_CH09 8 /* Audio Internal B */
475#define SRAM_CH10 9 /* Audio External */
476#define SRAM_CH11 10 /* COMB_3D_N */
477#define SRAM_CH12 11 /* Comb 3D N1 */
478#define SRAM_CH13 12 /* Comb 3D N2 */
479#define SRAM_CH14 13 /* MOE Vid */
480#define SRAM_CH15 14 /* MOE RSLT */
481
482struct sram_channel {
483 char *name;
484 u32 cmds_start;
485 u32 ctrl_start;
486 u32 cdt;
1ebcad77 487 u32 fifo_start;
d19770e5
ST		 488 u32 fifo_size;
489 u32 ptr1_reg;
490 u32 ptr2_reg;
491 u32 cnt1_reg;
492 u32 cnt2_reg;
493 u32 jumponly;
494};
495
496/* ----------------------------------------------------------- */
497
498#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51 499#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5 500
9c8ced51 501#define cx_andor(reg, mask, value) \
d19770e5
ST		 502 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
503 ((value) & (mask)), dev->lmmio+((reg)>>2))
504
9c8ced51
ST		 505#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
506#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5 507
d19770e5 508/* ----------------------------------------------------------- */
7b888014
ST		 509/* cx23885-core.c */
510
511extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
512 struct sram_channel *ch,
513 unsigned int bpl, u32 risc);
514
515extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
516 struct sram_channel *ch);
d19770e5 517
4d63a25c 518extern int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
7b888014
ST		 519 struct scatterlist *sglist,
520 unsigned int top_offset, unsigned int bottom_offset,
521 unsigned int bpl, unsigned int padding, unsigned int lines);
522
5ab27e6d 523extern int cx23885_risc_vbibuffer(struct pci_dev *pci,
4d63a25c 524 struct cx23885_riscmem *risc, struct scatterlist *sglist,
5ab27e6d
ST		 525 unsigned int top_offset, unsigned int bottom_offset,
526 unsigned int bpl, unsigned int padding, unsigned int lines);
527
453afdd9
HV		 528int cx23885_start_dma(struct cx23885_tsport *port,
529 struct cx23885_dmaqueue *q,
530 struct cx23885_buffer *buf);
7b888014
ST		 531void cx23885_cancel_buffers(struct cx23885_tsport *port);
532
7b888014 533
6f8bee9b
ST		 534extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
535extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
09ea33e5 536extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
6f8bee9b
ST		 537extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
538 int asoutput);
539
dbe83a3b
AW		 540extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
541extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
542extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
543extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
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ST		 544
545/* ----------------------------------------------------------- */
546/* cx23885-cards.c */
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ST		 547extern struct cx23885_board cx23885_boards[];
548extern const unsigned int cx23885_bcount;
549
550extern struct cx23885_subid cx23885_subids[];
551extern const unsigned int cx23885_idcount;
552
9c8ced51
ST		 553extern int cx23885_tuner_callback(void *priv, int component,
554 int command, int arg);
d19770e5 555extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140 556extern int cx23885_ir_init(struct cx23885_dev *dev);
f59ad611
AW		 557extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
558extern void cx23885_ir_fini(struct cx23885_dev *dev);
a6a3f140 559extern void cx23885_gpio_setup(struct cx23885_dev *dev);
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ST		 560extern void cx23885_card_setup(struct cx23885_dev *dev);
561extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
562
563extern int cx23885_dvb_register(struct cx23885_tsport *port);
564extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
565
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HV		 566extern int cx23885_buf_prepare(struct cx23885_buffer *buf,
567 struct cx23885_tsport *port);
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MK		 568extern void cx23885_buf_queue(struct cx23885_tsport *port,
569 struct cx23885_buffer *buf);
453afdd9 570extern void cx23885_free_buffer(struct cx23885_dev *dev,
44a6481d 571 struct cx23885_buffer *buf);
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ST		 572
573/* ----------------------------------------------------------- */
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ST		 574/* cx23885-video.c */
575/* Video */
576extern int cx23885_video_register(struct cx23885_dev *dev);
577extern void cx23885_video_unregister(struct cx23885_dev *dev);
578extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
b5f74050
ST		 579extern void cx23885_video_wakeup(struct cx23885_dev *dev,
580 struct cx23885_dmaqueue *q, u32 count);
35045137
ST		 581int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i);
582int cx23885_set_input(struct file *file, void *priv, unsigned int i);
583int cx23885_get_input(struct file *file, void *priv, unsigned int *i);
b530a447 584int cx23885_set_frequency(struct file *file, void *priv, const struct v4l2_frequency *f);
35045137 585int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm);
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ST		 586
587/* ----------------------------------------------------------- */
588/* cx23885-vbi.c */
589extern int cx23885_vbi_fmt(struct file *file, void *priv,
590 struct v4l2_format *f);
591extern void cx23885_vbi_timeout(unsigned long data);
453afdd9 592extern struct vb2_ops cx23885_vbi_qops;
b5f74050 593extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status);
7b888014 594
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ST		 595/* cx23885-i2c.c */
596extern int cx23885_i2c_register(struct cx23885_i2c *bus);
597extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665 598extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5 599
b1b81f1d
ST		 600/* ----------------------------------------------------------- */
601/* cx23885-417.c */
602extern int cx23885_417_register(struct cx23885_dev *dev);
603extern void cx23885_417_unregister(struct cx23885_dev *dev);
604extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
605extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
606extern void cx23885_mc417_init(struct cx23885_dev *dev);
607extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
608extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
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AW		 609extern int mc417_register_read(struct cx23885_dev *dev,
610 u16 address, u32 *value);
611extern int mc417_register_write(struct cx23885_dev *dev,
612 u16 address, u32 value);
f659c513
ST		 613extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
614extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
615extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
b1b81f1d 616
9e44d632
MM		 617/* ----------------------------------------------------------- */
618/* cx23885-alsa.c */
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ST		 619extern struct cx23885_audio_dev *cx23885_audio_register(
620 struct cx23885_dev *dev);
621extern void cx23885_audio_unregister(struct cx23885_dev *dev);
9e44d632
MM		 622extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask);
623extern int cx23885_risc_databuffer(struct pci_dev *pci,
4d63a25c 624 struct cx23885_riscmem *risc,
9e44d632
MM		 625 struct scatterlist *sglist,
626 unsigned int bpl,
627 unsigned int lines,
628 unsigned int lpi);
b1b81f1d 629
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ST		 630/* ----------------------------------------------------------- */
631/* tv norms */
632
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ST		 633static inline unsigned int norm_maxh(v4l2_std_id norm)
634{
1c5eaa23 635 return (norm & V4L2_STD_525_60) ? 480 : 576;
7b888014 636}
Linux kernel - Deliverables
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