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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
8efdb135 | 18 | #include <linux/err.h> |
3bc43840 GL |
19 | #include <linux/errno.h> |
20 | #include <linux/fs.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/time.h> | |
3bc43840 GL |
26 | #include <linux/device.h> |
27 | #include <linux/platform_device.h> | |
3bc43840 | 28 | #include <linux/clk.h> |
d514edac | 29 | #include <linux/sched.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1e77d55a RJ |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/dma/pxa-dma.h> | |
3bc43840 GL |
34 | |
35 | #include <media/v4l2-common.h> | |
36 | #include <media/v4l2-dev.h> | |
092d3921 | 37 | #include <media/videobuf-dma-sg.h> |
3bc43840 | 38 | #include <media/soc_camera.h> |
d647f0b7 | 39 | #include <media/drv-intf/soc_mediabus.h> |
e9a1d94f | 40 | #include <media/v4l2-of.h> |
3bc43840 GL |
41 | |
42 | #include <linux/videodev2.h> | |
43 | ||
a71daaa1 | 44 | #include <linux/platform_data/media/camera-pxa.h> |
3bc43840 | 45 | |
64dc3c1a | 46 | #define PXA_CAM_VERSION "0.0.6" |
3bc43840 GL |
47 | #define PXA_CAM_DRV_NAME "pxa27x-camera" |
48 | ||
5ca11fa3 EM |
49 | /* Camera Interface */ |
50 | #define CICR0 0x0000 | |
51 | #define CICR1 0x0004 | |
52 | #define CICR2 0x0008 | |
53 | #define CICR3 0x000C | |
54 | #define CICR4 0x0010 | |
55 | #define CISR 0x0014 | |
56 | #define CIFR 0x0018 | |
57 | #define CITOR 0x001C | |
58 | #define CIBR0 0x0028 | |
59 | #define CIBR1 0x0030 | |
60 | #define CIBR2 0x0038 | |
61 | ||
62 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
63 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
64 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
65 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
66 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
67 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
68 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
69 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
70 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
71 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
72 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
73 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
74 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
75 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
76 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
77 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
78 | ||
79 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
80 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
81 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
82 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
83 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
84 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
85 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
86 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
87 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
88 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
89 | ||
90 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
91 | wait count mask */ | |
92 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
93 | wait count mask */ | |
94 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
95 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
96 | wait count mask */ | |
97 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
98 | wait count mask */ | |
99 | ||
100 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
101 | wait count mask */ | |
102 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
103 | wait count mask */ | |
104 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
105 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
106 | wait count mask */ | |
107 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
108 | ||
109 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
110 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
111 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
112 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
113 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
114 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
115 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
116 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
117 | ||
118 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
119 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
120 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
121 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
122 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
123 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
124 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
125 | #define CISR_EOL (1 << 8) /* End of line */ | |
126 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
127 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
128 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
129 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
130 | #define CISR_EOF (1 << 3) /* End of frame */ | |
131 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
132 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
133 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
134 | ||
135 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
136 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
137 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
138 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
139 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
140 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
141 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
142 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
143 | ||
7102b773 GL |
144 | #define CICR0_SIM_MP (0 << 24) |
145 | #define CICR0_SIM_SP (1 << 24) | |
146 | #define CICR0_SIM_MS (2 << 24) | |
147 | #define CICR0_SIM_EP (3 << 24) | |
148 | #define CICR0_SIM_ES (4 << 24) | |
149 | ||
150 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
151 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
152 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
153 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
154 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
155 | |
156 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
157 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
158 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
159 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
160 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
161 | ||
162 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
163 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
164 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
165 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
166 | ||
3bc43840 GL |
167 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
168 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
169 | CICR0_EOFM | CICR0_FOM) | |
170 | ||
3bc43840 GL |
171 | /* |
172 | * Structures | |
173 | */ | |
a5462e5b MR |
174 | enum pxa_camera_active_dma { |
175 | DMA_Y = 0x1, | |
176 | DMA_U = 0x2, | |
177 | DMA_V = 0x4, | |
178 | }; | |
179 | ||
3bc43840 GL |
180 | /* buffer for one video frame */ |
181 | struct pxa_buffer { | |
182 | /* common v4l buffer stuff -- must be first */ | |
760697be | 183 | struct videobuf_buffer vb; |
27ffaeb0 | 184 | u32 code; |
a5462e5b | 185 | /* our descriptor lists for Y, U and V channels */ |
1e77d55a RJ |
186 | struct dma_async_tx_descriptor *descs[3]; |
187 | dma_cookie_t cookie[3]; | |
188 | struct scatterlist *sg[3]; | |
189 | int sg_len[3]; | |
760697be GL |
190 | int inwork; |
191 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
192 | }; |
193 | ||
3bc43840 | 194 | struct pxa_camera_dev { |
eb6c8558 | 195 | struct soc_camera_host soc_host; |
5d28d525 GL |
196 | /* |
197 | * PXA27x is only supposed to handle one camera on its Quick Capture | |
3bc43840 | 198 | * interface. If anyone ever builds hardware to enable more than |
5d28d525 GL |
199 | * one camera, they will have to modify this driver too |
200 | */ | |
3bc43840 GL |
201 | struct clk *clk; |
202 | ||
203 | unsigned int irq; | |
204 | void __iomem *base; | |
a5462e5b | 205 | |
e7c50688 | 206 | int channels; |
1e77d55a | 207 | struct dma_chan *dma_chans[3]; |
3bc43840 | 208 | |
3bc43840 GL |
209 | struct pxacamera_platform_data *pdata; |
210 | struct resource *res; | |
211 | unsigned long platform_flags; | |
cf34cba7 GL |
212 | unsigned long ciclk; |
213 | unsigned long mclk; | |
214 | u32 mclk_divisor; | |
679419aa | 215 | u16 width_flags; /* max 10 bits */ |
3bc43840 GL |
216 | |
217 | struct list_head capture; | |
218 | ||
219 | spinlock_t lock; | |
220 | ||
3bc43840 | 221 | struct pxa_buffer *active; |
e623ebe6 | 222 | struct tasklet_struct task_eof; |
3f6ac497 RJ |
223 | |
224 | u32 save_cicr[5]; | |
3bc43840 GL |
225 | }; |
226 | ||
6a6c8786 GL |
227 | struct pxa_cam { |
228 | unsigned long flags; | |
229 | }; | |
230 | ||
3bc43840 GL |
231 | static const char *pxa_cam_driver_description = "PXA_Camera"; |
232 | ||
233 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | |
234 | ||
235 | /* | |
236 | * Videobuf operations | |
237 | */ | |
7102b773 GL |
238 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, |
239 | unsigned int *size) | |
3bc43840 GL |
240 | { |
241 | struct soc_camera_device *icd = vq->priv_data; | |
242 | ||
7dfff953 | 243 | dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size); |
3bc43840 | 244 | |
2b61d46e | 245 | *size = icd->sizeimage; |
3bc43840 GL |
246 | |
247 | if (0 == *count) | |
248 | *count = 32; | |
dab7e310 AB |
249 | if (*size * *count > vid_limit * 1024 * 1024) |
250 | *count = (vid_limit * 1024 * 1024) / *size; | |
3bc43840 GL |
251 | |
252 | return 0; | |
253 | } | |
254 | ||
255 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | |
256 | { | |
257 | struct soc_camera_device *icd = vq->priv_data; | |
3bc43840 | 258 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); |
a5462e5b | 259 | int i; |
3bc43840 GL |
260 | |
261 | BUG_ON(in_interrupt()); | |
262 | ||
7dfff953 | 263 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
264 | &buf->vb, buf->vb.baddr, buf->vb.bsize); |
265 | ||
5d28d525 GL |
266 | /* |
267 | * This waits until this buffer is out of danger, i.e., until it is no | |
268 | * longer in STATE_QUEUED or STATE_ACTIVE | |
269 | */ | |
0e0809a5 | 270 | videobuf_waiton(vq, &buf->vb, 0, 0); |
3bc43840 | 271 | |
1e77d55a RJ |
272 | for (i = 0; i < 3 && buf->descs[i]; i++) { |
273 | dmaengine_desc_free(buf->descs[i]); | |
274 | kfree(buf->sg[i]); | |
275 | buf->descs[i] = NULL; | |
276 | buf->sg[i] = NULL; | |
277 | buf->sg_len[i] = 0; | |
a5462e5b | 278 | } |
8f4895f2 RJ |
279 | videobuf_dma_unmap(vq->dev, dma); |
280 | videobuf_dma_free(dma); | |
3bc43840 GL |
281 | |
282 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
37f5aefd | 283 | |
1e77d55a RJ |
284 | dev_dbg(icd->parent, "%s end (vb=0x%p) 0x%08lx %d\n", __func__, |
285 | &buf->vb, buf->vb.baddr, buf->vb.bsize); | |
37f5aefd RJ |
286 | } |
287 | ||
1e77d55a | 288 | static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev, |
e5853918 RJ |
289 | enum pxa_camera_active_dma act_dma); |
290 | ||
1e77d55a | 291 | static void pxa_camera_dma_irq_y(void *data) |
e5853918 RJ |
292 | { |
293 | struct pxa_camera_dev *pcdev = data; | |
294 | ||
1e77d55a | 295 | pxa_camera_dma_irq(pcdev, DMA_Y); |
e5853918 RJ |
296 | } |
297 | ||
1e77d55a | 298 | static void pxa_camera_dma_irq_u(void *data) |
e5853918 RJ |
299 | { |
300 | struct pxa_camera_dev *pcdev = data; | |
301 | ||
1e77d55a | 302 | pxa_camera_dma_irq(pcdev, DMA_U); |
e5853918 RJ |
303 | } |
304 | ||
1e77d55a | 305 | static void pxa_camera_dma_irq_v(void *data) |
e5853918 RJ |
306 | { |
307 | struct pxa_camera_dev *pcdev = data; | |
308 | ||
1e77d55a | 309 | pxa_camera_dma_irq(pcdev, DMA_V); |
e5853918 RJ |
310 | } |
311 | ||
37f5aefd RJ |
312 | /** |
313 | * pxa_init_dma_channel - init dma descriptors | |
314 | * @pcdev: pxa camera device | |
315 | * @buf: pxa buffer to find pxa dma channel | |
316 | * @dma: dma video buffer | |
317 | * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') | |
318 | * @cibr: camera Receive Buffer Register | |
319 | * @size: bytes to transfer | |
1e77d55a | 320 | * @offset: offset in videobuffer of the first byte to transfer |
37f5aefd RJ |
321 | * |
322 | * Prepares the pxa dma descriptors to transfer one camera channel. | |
37f5aefd | 323 | * |
1e77d55a | 324 | * Returns 0 if success or -ENOMEM if no memory is available |
37f5aefd | 325 | */ |
a5462e5b MR |
326 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
327 | struct pxa_buffer *buf, | |
328 | struct videobuf_dmabuf *dma, int channel, | |
1e77d55a | 329 | int cibr, int size, int offset) |
a5462e5b | 330 | { |
1e77d55a RJ |
331 | struct dma_chan *dma_chan = pcdev->dma_chans[channel]; |
332 | struct scatterlist *sg = buf->sg[channel]; | |
333 | int sglen = buf->sg_len[channel]; | |
334 | struct dma_async_tx_descriptor *tx; | |
335 | ||
336 | tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM, | |
337 | DMA_PREP_INTERRUPT | DMA_CTRL_REUSE); | |
338 | if (!tx) { | |
339 | dev_err(pcdev->soc_host.v4l2_dev.dev, | |
340 | "dmaengine_prep_slave_sg failed\n"); | |
341 | goto fail; | |
a5462e5b MR |
342 | } |
343 | ||
1e77d55a RJ |
344 | tx->callback_param = pcdev; |
345 | switch (channel) { | |
346 | case 0: | |
347 | tx->callback = pxa_camera_dma_irq_y; | |
348 | break; | |
349 | case 1: | |
350 | tx->callback = pxa_camera_dma_irq_u; | |
351 | break; | |
352 | case 2: | |
353 | tx->callback = pxa_camera_dma_irq_v; | |
354 | break; | |
37f5aefd RJ |
355 | } |
356 | ||
1e77d55a | 357 | buf->descs[channel] = tx; |
a5462e5b | 358 | return 0; |
1e77d55a RJ |
359 | fail: |
360 | kfree(sg); | |
361 | ||
362 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, | |
363 | "%s (vb=0x%p) dma_tx=%p\n", | |
364 | __func__, &buf->vb, tx); | |
365 | ||
366 | return -ENOMEM; | |
a5462e5b MR |
367 | } |
368 | ||
256b0233 RJ |
369 | static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, |
370 | struct pxa_buffer *buf) | |
371 | { | |
372 | buf->active_dma = DMA_Y; | |
373 | if (pcdev->channels == 3) | |
374 | buf->active_dma |= DMA_U | DMA_V; | |
375 | } | |
376 | ||
377 | /* | |
378 | * Please check the DMA prepared buffer structure in : | |
379 | * Documentation/video4linux/pxa_camera.txt | |
380 | * Please check also in pxa_camera_check_link_miss() to understand why DMA chain | |
381 | * modification while DMA chain is running will work anyway. | |
382 | */ | |
7102b773 GL |
383 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, |
384 | struct videobuf_buffer *vb, enum v4l2_field field) | |
3bc43840 GL |
385 | { |
386 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 387 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
3bc43840 | 388 | struct pxa_camera_dev *pcdev = ici->priv; |
979ea1dd | 389 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
3bc43840 | 390 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); |
a5462e5b | 391 | int ret; |
a5462e5b | 392 | int size_y, size_u = 0, size_v = 0; |
1e77d55a | 393 | size_t sizes[3]; |
3bc43840 | 394 | |
979ea1dd | 395 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
396 | vb, vb->baddr, vb->bsize); |
397 | ||
398 | /* Added list head initialization on alloc */ | |
399 | WARN_ON(!list_empty(&vb->queue)); | |
400 | ||
401 | #ifdef DEBUG | |
5d28d525 GL |
402 | /* |
403 | * This can be useful if you want to see if we actually fill | |
404 | * the buffer with something | |
405 | */ | |
3bc43840 GL |
406 | memset((void *)vb->baddr, 0xaa, vb->bsize); |
407 | #endif | |
408 | ||
409 | BUG_ON(NULL == icd->current_fmt); | |
410 | ||
5d28d525 GL |
411 | /* |
412 | * I think, in buf_prepare you only have to protect global data, | |
413 | * the actual buffer is yours | |
414 | */ | |
3bc43840 GL |
415 | buf->inwork = 1; |
416 | ||
760697be | 417 | if (buf->code != icd->current_fmt->code || |
6a6c8786 GL |
418 | vb->width != icd->user_width || |
419 | vb->height != icd->user_height || | |
3bc43840 | 420 | vb->field != field) { |
760697be | 421 | buf->code = icd->current_fmt->code; |
6a6c8786 GL |
422 | vb->width = icd->user_width; |
423 | vb->height = icd->user_height; | |
3bc43840 GL |
424 | vb->field = field; |
425 | vb->state = VIDEOBUF_NEEDS_INIT; | |
426 | } | |
427 | ||
2b61d46e | 428 | vb->size = icd->sizeimage; |
3bc43840 GL |
429 | if (0 != vb->baddr && vb->bsize < vb->size) { |
430 | ret = -EINVAL; | |
431 | goto out; | |
432 | } | |
433 | ||
434 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
37f5aefd | 435 | int size = vb->size; |
3bc43840 GL |
436 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); |
437 | ||
438 | ret = videobuf_iolock(vq, vb, NULL); | |
439 | if (ret) | |
8f4895f2 | 440 | goto out; |
3bc43840 | 441 | |
5aa2110f | 442 | if (pcdev->channels == 3) { |
a5462e5b MR |
443 | size_y = size / 2; |
444 | size_u = size_v = size / 4; | |
445 | } else { | |
a5462e5b MR |
446 | size_y = size; |
447 | } | |
448 | ||
1e77d55a RJ |
449 | sizes[0] = size_y; |
450 | sizes[1] = size_u; | |
451 | sizes[2] = size_v; | |
452 | ret = sg_split(dma->sglist, dma->sglen, 0, pcdev->channels, | |
453 | sizes, buf->sg, buf->sg_len, GFP_KERNEL); | |
454 | if (ret < 0) { | |
455 | dev_err(dev, "sg_split failed: %d\n", ret); | |
456 | goto fail; | |
457 | } | |
3bc43840 | 458 | |
37f5aefd | 459 | /* init DMA for Y channel */ |
1e77d55a RJ |
460 | ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, |
461 | size_y, 0); | |
a5462e5b | 462 | if (ret) { |
979ea1dd | 463 | dev_err(dev, "DMA initialization for Y/RGB failed\n"); |
3bc43840 GL |
464 | goto fail; |
465 | } | |
466 | ||
37f5aefd RJ |
467 | /* init DMA for U channel */ |
468 | if (size_u) | |
469 | ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1, | |
1e77d55a | 470 | size_u, size_y); |
37f5aefd | 471 | if (ret) { |
979ea1dd | 472 | dev_err(dev, "DMA initialization for U failed\n"); |
8f4895f2 | 473 | goto fail; |
37f5aefd RJ |
474 | } |
475 | ||
476 | /* init DMA for V channel */ | |
477 | if (size_v) | |
478 | ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2, | |
1e77d55a | 479 | size_v, size_y + size_u); |
37f5aefd | 480 | if (ret) { |
979ea1dd | 481 | dev_err(dev, "DMA initialization for V failed\n"); |
8f4895f2 | 482 | goto fail; |
3bc43840 | 483 | } |
3bc43840 GL |
484 | |
485 | vb->state = VIDEOBUF_PREPARED; | |
486 | } | |
487 | ||
488 | buf->inwork = 0; | |
256b0233 | 489 | pxa_videobuf_set_actdma(pcdev, buf); |
3bc43840 GL |
490 | |
491 | return 0; | |
492 | ||
493 | fail: | |
494 | free_buffer(vq, buf); | |
495 | out: | |
496 | buf->inwork = 0; | |
497 | return ret; | |
498 | } | |
499 | ||
256b0233 RJ |
500 | /** |
501 | * pxa_dma_start_channels - start DMA channel for active buffer | |
502 | * @pcdev: pxa camera device | |
503 | * | |
504 | * Initialize DMA channels to the beginning of the active video buffer, and | |
505 | * start these channels. | |
506 | */ | |
507 | static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) | |
508 | { | |
509 | int i; | |
510 | struct pxa_buffer *active; | |
511 | ||
512 | active = pcdev->active; | |
513 | ||
514 | for (i = 0; i < pcdev->channels; i++) { | |
0166b743 | 515 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
1e77d55a RJ |
516 | "%s (channel=%d)\n", __func__, i); |
517 | dma_async_issue_pending(pcdev->dma_chans[i]); | |
256b0233 RJ |
518 | } |
519 | } | |
520 | ||
521 | static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) | |
522 | { | |
523 | int i; | |
524 | ||
525 | for (i = 0; i < pcdev->channels; i++) { | |
0166b743 GL |
526 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
527 | "%s (channel=%d)\n", __func__, i); | |
1e77d55a | 528 | dmaengine_terminate_all(pcdev->dma_chans[i]); |
256b0233 RJ |
529 | } |
530 | } | |
531 | ||
256b0233 RJ |
532 | static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, |
533 | struct pxa_buffer *buf) | |
534 | { | |
535 | int i; | |
256b0233 RJ |
536 | |
537 | for (i = 0; i < pcdev->channels; i++) { | |
1e77d55a RJ |
538 | buf->cookie[i] = dmaengine_submit(buf->descs[i]); |
539 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, | |
540 | "%s (channel=%d) : submit vb=%p cookie=%d\n", | |
541 | __func__, i, buf, buf->descs[i]->cookie); | |
ae7410e7 | 542 | } |
256b0233 RJ |
543 | } |
544 | ||
545 | /** | |
546 | * pxa_camera_start_capture - start video capturing | |
547 | * @pcdev: camera device | |
548 | * | |
549 | * Launch capturing. DMA channels should not be active yet. They should get | |
550 | * activated at the end of frame interrupt, to capture only whole frames, and | |
551 | * never begin the capture of a partial frame. | |
552 | */ | |
553 | static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) | |
554 | { | |
a47f6be4 | 555 | unsigned long cicr0; |
256b0233 | 556 | |
979ea1dd | 557 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); |
e623ebe6 | 558 | __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR); |
256b0233 RJ |
559 | /* Enable End-Of-Frame Interrupt */ |
560 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
561 | cicr0 &= ~CICR0_EOFM; | |
562 | __raw_writel(cicr0, pcdev->base + CICR0); | |
563 | } | |
564 | ||
565 | static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) | |
566 | { | |
567 | unsigned long cicr0; | |
568 | ||
569 | pxa_dma_stop_channels(pcdev); | |
570 | ||
571 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
572 | __raw_writel(cicr0, pcdev->base + CICR0); | |
573 | ||
8c62e221 | 574 | pcdev->active = NULL; |
979ea1dd | 575 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); |
256b0233 RJ |
576 | } |
577 | ||
2dd54a54 | 578 | /* Called under spinlock_irqsave(&pcdev->lock, ...) */ |
7102b773 GL |
579 | static void pxa_videobuf_queue(struct videobuf_queue *vq, |
580 | struct videobuf_buffer *vb) | |
3bc43840 GL |
581 | { |
582 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 583 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
3bc43840 GL |
584 | struct pxa_camera_dev *pcdev = ici->priv; |
585 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
3bc43840 | 586 | |
7dfff953 | 587 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n", |
0166b743 | 588 | __func__, vb, vb->baddr, vb->bsize, pcdev->active); |
256b0233 | 589 | |
3bc43840 GL |
590 | list_add_tail(&vb->queue, &pcdev->capture); |
591 | ||
592 | vb->state = VIDEOBUF_ACTIVE; | |
256b0233 | 593 | pxa_dma_add_tail_buf(pcdev, buf); |
3bc43840 | 594 | |
256b0233 RJ |
595 | if (!pcdev->active) |
596 | pxa_camera_start_capture(pcdev); | |
3bc43840 GL |
597 | } |
598 | ||
599 | static void pxa_videobuf_release(struct videobuf_queue *vq, | |
600 | struct videobuf_buffer *vb) | |
601 | { | |
602 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
603 | #ifdef DEBUG | |
604 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 605 | struct device *dev = icd->parent; |
3bc43840 | 606 | |
0166b743 | 607 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
608 | vb, vb->baddr, vb->bsize); |
609 | ||
610 | switch (vb->state) { | |
611 | case VIDEOBUF_ACTIVE: | |
0166b743 | 612 | dev_dbg(dev, "%s (active)\n", __func__); |
3bc43840 GL |
613 | break; |
614 | case VIDEOBUF_QUEUED: | |
0166b743 | 615 | dev_dbg(dev, "%s (queued)\n", __func__); |
3bc43840 GL |
616 | break; |
617 | case VIDEOBUF_PREPARED: | |
0166b743 | 618 | dev_dbg(dev, "%s (prepared)\n", __func__); |
3bc43840 GL |
619 | break; |
620 | default: | |
0166b743 | 621 | dev_dbg(dev, "%s (unknown)\n", __func__); |
3bc43840 GL |
622 | break; |
623 | } | |
624 | #endif | |
625 | ||
626 | free_buffer(vq, buf); | |
627 | } | |
628 | ||
a5462e5b MR |
629 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
630 | struct videobuf_buffer *vb, | |
631 | struct pxa_buffer *buf) | |
632 | { | |
633 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ | |
634 | list_del_init(&vb->queue); | |
635 | vb->state = VIDEOBUF_DONE; | |
8e6057b5 | 636 | v4l2_get_timestamp(&vb->ts); |
a5462e5b MR |
637 | vb->field_count++; |
638 | wake_up(&vb->done); | |
979ea1dd GL |
639 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n", |
640 | __func__, vb); | |
a5462e5b MR |
641 | |
642 | if (list_empty(&pcdev->capture)) { | |
256b0233 | 643 | pxa_camera_stop_capture(pcdev); |
a5462e5b MR |
644 | return; |
645 | } | |
646 | ||
647 | pcdev->active = list_entry(pcdev->capture.next, | |
648 | struct pxa_buffer, vb.queue); | |
649 | } | |
650 | ||
256b0233 RJ |
651 | /** |
652 | * pxa_camera_check_link_miss - check missed DMA linking | |
653 | * @pcdev: camera device | |
654 | * | |
655 | * The DMA chaining is done with DMA running. This means a tiny temporal window | |
656 | * remains, where a buffer is queued on the chain, while the chain is already | |
25985edc | 657 | * stopped. This means the tailed buffer would never be transferred by DMA. |
256b0233 RJ |
658 | * This function restarts the capture for this corner case, where : |
659 | * - DADR() == DADDR_STOP | |
660 | * - a videobuffer is queued on the pcdev->capture list | |
661 | * | |
662 | * Please check the "DMA hot chaining timeslice issue" in | |
663 | * Documentation/video4linux/pxa_camera.txt | |
664 | * | |
665 | * Context: should only be called within the dma irq handler | |
666 | */ | |
1e77d55a RJ |
667 | static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev, |
668 | dma_cookie_t last_submitted, | |
669 | dma_cookie_t last_issued) | |
256b0233 | 670 | { |
1e77d55a | 671 | bool is_dma_stopped = last_submitted != last_issued; |
256b0233 | 672 | |
979ea1dd | 673 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
1e77d55a | 674 | "%s : top queued buffer=%p, is_dma_stopped=%d\n", |
256b0233 | 675 | __func__, pcdev->active, is_dma_stopped); |
1e77d55a | 676 | |
256b0233 RJ |
677 | if (pcdev->active && is_dma_stopped) |
678 | pxa_camera_start_capture(pcdev); | |
679 | } | |
680 | ||
1e77d55a | 681 | static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev, |
a5462e5b | 682 | enum pxa_camera_active_dma act_dma) |
3bc43840 | 683 | { |
979ea1dd | 684 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
1e77d55a | 685 | struct pxa_buffer *buf, *last_buf; |
3bc43840 | 686 | unsigned long flags; |
1e77d55a RJ |
687 | u32 camera_status, overrun; |
688 | int chan; | |
3bc43840 | 689 | struct videobuf_buffer *vb; |
1e77d55a RJ |
690 | enum dma_status last_status; |
691 | dma_cookie_t last_issued; | |
3bc43840 GL |
692 | |
693 | spin_lock_irqsave(&pcdev->lock, flags); | |
694 | ||
256b0233 | 695 | camera_status = __raw_readl(pcdev->base + CISR); |
1e77d55a RJ |
696 | dev_dbg(dev, "camera dma irq, cisr=0x%x dma=%d\n", |
697 | camera_status, act_dma); | |
256b0233 RJ |
698 | overrun = CISR_IFO_0; |
699 | if (pcdev->channels == 3) | |
700 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
7102b773 | 701 | |
8c62e221 RJ |
702 | /* |
703 | * pcdev->active should not be NULL in DMA irq handler. | |
704 | * | |
705 | * But there is one corner case : if capture was stopped due to an | |
706 | * overrun of channel 1, and at that same channel 2 was completed. | |
707 | * | |
708 | * When handling the overrun in DMA irq for channel 1, we'll stop the | |
709 | * capture and restart it (and thus set pcdev->active to NULL). But the | |
710 | * DMA irq handler will already be pending for channel 2. So on entering | |
711 | * the DMA irq handler for channel 2 there will be no active buffer, yet | |
712 | * that is normal. | |
713 | */ | |
714 | if (!pcdev->active) | |
3bc43840 | 715 | goto out; |
3bc43840 GL |
716 | |
717 | vb = &pcdev->active->vb; | |
718 | buf = container_of(vb, struct pxa_buffer, vb); | |
719 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
3bc43840 | 720 | |
1e77d55a RJ |
721 | /* |
722 | * It's normal if the last frame creates an overrun, as there | |
723 | * are no more DMA descriptors to fetch from QCI fifos | |
724 | */ | |
725 | switch (act_dma) { | |
726 | case DMA_U: | |
727 | chan = 1; | |
728 | break; | |
729 | case DMA_V: | |
730 | chan = 2; | |
731 | break; | |
732 | default: | |
733 | chan = 0; | |
734 | break; | |
735 | } | |
736 | last_buf = list_entry(pcdev->capture.prev, | |
737 | struct pxa_buffer, vb.queue); | |
738 | last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan], | |
739 | last_buf->cookie[chan], | |
740 | NULL, &last_issued); | |
741 | if (camera_status & overrun && | |
742 | last_status != DMA_COMPLETE) { | |
743 | dev_dbg(dev, "FIFO overrun! CISR: %x\n", | |
744 | camera_status); | |
745 | pxa_camera_stop_capture(pcdev); | |
746 | list_for_each_entry(buf, &pcdev->capture, vb.queue) | |
747 | pxa_dma_add_tail_buf(pcdev, buf); | |
748 | pxa_camera_start_capture(pcdev); | |
749 | goto out; | |
750 | } | |
751 | buf->active_dma &= ~act_dma; | |
752 | if (!buf->active_dma) { | |
753 | pxa_camera_wakeup(pcdev, vb, buf); | |
754 | pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan], | |
755 | last_issued); | |
256b0233 | 756 | } |
3bc43840 GL |
757 | |
758 | out: | |
759 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
760 | } | |
761 | ||
7102b773 | 762 | static struct videobuf_queue_ops pxa_videobuf_ops = { |
3bc43840 GL |
763 | .buf_setup = pxa_videobuf_setup, |
764 | .buf_prepare = pxa_videobuf_prepare, | |
765 | .buf_queue = pxa_videobuf_queue, | |
766 | .buf_release = pxa_videobuf_release, | |
767 | }; | |
768 | ||
a034d1b7 | 769 | static void pxa_camera_init_videobuf(struct videobuf_queue *q, |
092d3921 PZ |
770 | struct soc_camera_device *icd) |
771 | { | |
7dfff953 | 772 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
a034d1b7 MD |
773 | struct pxa_camera_dev *pcdev = ici->priv; |
774 | ||
5d28d525 GL |
775 | /* |
776 | * We must pass NULL as dev pointer, then all pci_* dma operations | |
777 | * transform to normal dma_* ones. | |
778 | */ | |
a034d1b7 | 779 | videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, |
092d3921 | 780 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, |
47ebe3f9 | 781 | sizeof(struct pxa_buffer), icd, &ici->host_lock); |
092d3921 PZ |
782 | } |
783 | ||
40e2e092 GL |
784 | static u32 mclk_get_divisor(struct platform_device *pdev, |
785 | struct pxa_camera_dev *pcdev) | |
3bc43840 | 786 | { |
cf34cba7 | 787 | unsigned long mclk = pcdev->mclk; |
6a6c8786 | 788 | struct device *dev = &pdev->dev; |
cf34cba7 | 789 | u32 div; |
3bc43840 GL |
790 | unsigned long lcdclk; |
791 | ||
cf34cba7 GL |
792 | lcdclk = clk_get_rate(pcdev->clk); |
793 | pcdev->ciclk = lcdclk; | |
3bc43840 | 794 | |
cf34cba7 GL |
795 | /* mclk <= ciclk / 4 (27.4.2) */ |
796 | if (mclk > lcdclk / 4) { | |
797 | mclk = lcdclk / 4; | |
979ea1dd | 798 | dev_warn(dev, "Limiting master clock to %lu\n", mclk); |
cf34cba7 GL |
799 | } |
800 | ||
801 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
802 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 803 | |
cf34cba7 GL |
804 | /* If we're not supplying MCLK, leave it at 0 */ |
805 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
806 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 807 | |
979ea1dd | 808 | dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n", |
40e2e092 | 809 | lcdclk, mclk, div); |
3bc43840 GL |
810 | |
811 | return div; | |
812 | } | |
813 | ||
cf34cba7 GL |
814 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
815 | unsigned long pclk) | |
816 | { | |
817 | /* We want a timeout > 1 pixel time, not ">=" */ | |
818 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
819 | ||
820 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
821 | } | |
822 | ||
7102b773 | 823 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 | 824 | { |
3bc43840 GL |
825 | u32 cicr4 = 0; |
826 | ||
5ca11fa3 EM |
827 | /* disable all interrupts */ |
828 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
829 | |
830 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
831 | cicr4 |= CICR4_PCLK_EN; | |
832 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
833 | cicr4 |= CICR4_MCLK_EN; | |
834 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
835 | cicr4 |= CICR4_PCP; | |
836 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
837 | cicr4 |= CICR4_HSP; | |
838 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
839 | cicr4 |= CICR4_VSP; | |
840 | ||
cf34cba7 GL |
841 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
842 | ||
843 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
844 | /* Initialise the timeout under the assumption pclk = mclk */ | |
845 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
846 | else | |
847 | /* "Safe default" - 13MHz */ | |
848 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 | 849 | |
91acd962 | 850 | clk_prepare_enable(pcdev->clk); |
3bc43840 GL |
851 | } |
852 | ||
7102b773 | 853 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 854 | { |
91acd962 | 855 | clk_disable_unprepare(pcdev->clk); |
3bc43840 GL |
856 | } |
857 | ||
e623ebe6 | 858 | static void pxa_camera_eof(unsigned long arg) |
3bc43840 | 859 | { |
e623ebe6 RJ |
860 | struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg; |
861 | unsigned long cifr; | |
256b0233 RJ |
862 | struct pxa_buffer *buf; |
863 | struct videobuf_buffer *vb; | |
3bc43840 | 864 | |
e623ebe6 RJ |
865 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
866 | "Camera interrupt status 0x%x\n", | |
867 | __raw_readl(pcdev->base + CISR)); | |
868 | ||
869 | /* Reset the FIFOs */ | |
870 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
871 | __raw_writel(cifr, pcdev->base + CIFR); | |
872 | ||
873 | pcdev->active = list_first_entry(&pcdev->capture, | |
874 | struct pxa_buffer, vb.queue); | |
875 | vb = &pcdev->active->vb; | |
876 | buf = container_of(vb, struct pxa_buffer, vb); | |
877 | pxa_videobuf_set_actdma(pcdev, buf); | |
878 | ||
879 | pxa_dma_start_channels(pcdev); | |
880 | } | |
881 | ||
882 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
883 | { | |
884 | struct pxa_camera_dev *pcdev = data; | |
885 | unsigned long status, cicr0; | |
886 | ||
5ca11fa3 | 887 | status = __raw_readl(pcdev->base + CISR); |
0166b743 GL |
888 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
889 | "Camera interrupt status 0x%lx\n", status); | |
3bc43840 | 890 | |
e7c50688 GL |
891 | if (!status) |
892 | return IRQ_NONE; | |
893 | ||
5ca11fa3 | 894 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
895 | |
896 | if (status & CISR_EOF) { | |
5ca11fa3 EM |
897 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
898 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e623ebe6 | 899 | tasklet_schedule(&pcdev->task_eof); |
e7c50688 GL |
900 | } |
901 | ||
3bc43840 GL |
902 | return IRQ_HANDLED; |
903 | } | |
904 | ||
39b553db GL |
905 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
906 | { | |
907 | dev_info(icd->parent, "PXA Camera driver attached to camera %d\n", | |
908 | icd->devnum); | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
913 | static void pxa_camera_remove_device(struct soc_camera_device *icd) | |
914 | { | |
915 | dev_info(icd->parent, "PXA Camera driver detached from camera %d\n", | |
916 | icd->devnum); | |
917 | } | |
918 | ||
1c3bb743 GL |
919 | /* |
920 | * The following two functions absolutely depend on the fact, that | |
921 | * there can be only one camera on PXA quick capture interface | |
dd669e90 | 922 | * Called with .host_lock held |
1c3bb743 | 923 | */ |
39b553db | 924 | static int pxa_camera_clock_start(struct soc_camera_host *ici) |
3bc43840 | 925 | { |
3bc43840 | 926 | struct pxa_camera_dev *pcdev = ici->priv; |
3bc43840 | 927 | |
7102b773 | 928 | pxa_camera_activate(pcdev); |
40e2e092 | 929 | |
40e2e092 | 930 | return 0; |
3bc43840 GL |
931 | } |
932 | ||
dd669e90 | 933 | /* Called with .host_lock held */ |
39b553db | 934 | static void pxa_camera_clock_stop(struct soc_camera_host *ici) |
3bc43840 | 935 | { |
3bc43840 GL |
936 | struct pxa_camera_dev *pcdev = ici->priv; |
937 | ||
3bc43840 | 938 | /* disable capture, disable interrupts */ |
5ca11fa3 | 939 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 940 | |
3bc43840 | 941 | /* Stop DMA engine */ |
1e77d55a | 942 | pxa_dma_stop_channels(pcdev); |
7102b773 | 943 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
944 | } |
945 | ||
ad5f2e85 GL |
946 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
947 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 948 | { |
ad5f2e85 GL |
949 | /* |
950 | * Platform specified synchronization and pixel clock polarities are | |
951 | * only a recommendation and are only used during probing. The PXA270 | |
952 | * quick capture interface supports both. | |
953 | */ | |
954 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
679419aa GL |
955 | V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) | |
956 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | | |
957 | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
958 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
959 | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
960 | V4L2_MBUS_DATA_ACTIVE_HIGH | | |
961 | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
962 | V4L2_MBUS_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
963 | |
964 | /* If requested data width is supported by the platform, use it */ | |
679419aa GL |
965 | if ((1 << (buswidth - 1)) & pcdev->width_flags) |
966 | return 0; | |
ad5f2e85 | 967 | |
679419aa | 968 | return -EINVAL; |
ad5f2e85 GL |
969 | } |
970 | ||
6a6c8786 GL |
971 | static void pxa_camera_setup_cicr(struct soc_camera_device *icd, |
972 | unsigned long flags, __u32 pixfmt) | |
ad5f2e85 | 973 | { |
7dfff953 | 974 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
ad5f2e85 | 975 | struct pxa_camera_dev *pcdev = ici->priv; |
32536108 | 976 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
6a6c8786 | 977 | unsigned long dw, bpp; |
32536108 GL |
978 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; |
979 | int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top); | |
980 | ||
981 | if (ret < 0) | |
982 | y_skip_top = 0; | |
3bc43840 | 983 | |
5d28d525 GL |
984 | /* |
985 | * Datawidth is now guaranteed to be equal to one of the three values. | |
986 | * We fix bit-per-pixel equal to data-width... | |
987 | */ | |
679419aa GL |
988 | switch (icd->current_fmt->host_fmt->bits_per_sample) { |
989 | case 10: | |
3bc43840 GL |
990 | dw = 4; |
991 | bpp = 0x40; | |
992 | break; | |
679419aa | 993 | case 9: |
3bc43840 GL |
994 | dw = 3; |
995 | bpp = 0x20; | |
996 | break; | |
997 | default: | |
5d28d525 GL |
998 | /* |
999 | * Actually it can only be 8 now, | |
1000 | * default is just to silence compiler warnings | |
1001 | */ | |
679419aa | 1002 | case 8: |
3bc43840 GL |
1003 | dw = 2; |
1004 | bpp = 0; | |
1005 | } | |
1006 | ||
1007 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1008 | cicr4 |= CICR4_PCLK_EN; | |
1009 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
1010 | cicr4 |= CICR4_MCLK_EN; | |
679419aa | 1011 | if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
3bc43840 | 1012 | cicr4 |= CICR4_PCP; |
679419aa | 1013 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
3bc43840 | 1014 | cicr4 |= CICR4_HSP; |
679419aa | 1015 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
1016 | cicr4 |= CICR4_VSP; |
1017 | ||
5ca11fa3 | 1018 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 1019 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 1020 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b | 1021 | |
6a6c8786 | 1022 | cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw; |
a5462e5b MR |
1023 | |
1024 | switch (pixfmt) { | |
1025 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 1026 | pcdev->channels = 3; |
a5462e5b | 1027 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
1028 | /* |
1029 | * Normally, pxa bus wants as input UYVY format. We allow all | |
1030 | * reorderings of the YUV422 format, as no processing is done, | |
1031 | * and the YUV stream is just passed through without any | |
1032 | * transformation. Note that UYVY is the only format that | |
1033 | * should be used if pxa framebuffer Overlay2 is used. | |
1034 | */ | |
1035 | case V4L2_PIX_FMT_UYVY: | |
1036 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 1037 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 1038 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
1039 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
1040 | break; | |
1041 | case V4L2_PIX_FMT_RGB555: | |
1042 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
1043 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
1044 | break; | |
1045 | case V4L2_PIX_FMT_RGB565: | |
1046 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
1047 | break; | |
1048 | } | |
1049 | ||
5ca11fa3 | 1050 | cicr2 = 0; |
6a6c8786 | 1051 | cicr3 = CICR3_LPF_VAL(icd->user_height - 1) | |
32536108 | 1052 | CICR3_BFW_VAL(min((u32)255, y_skip_top)); |
cf34cba7 | 1053 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
1054 | |
1055 | __raw_writel(cicr1, pcdev->base + CICR1); | |
1056 | __raw_writel(cicr2, pcdev->base + CICR2); | |
1057 | __raw_writel(cicr3, pcdev->base + CICR3); | |
1058 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
1059 | |
1060 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
1061 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
1062 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
1063 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
1064 | __raw_writel(cicr0, pcdev->base + CICR0); | |
6a6c8786 GL |
1065 | } |
1066 | ||
8843d119 | 1067 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd) |
6a6c8786 | 1068 | { |
679419aa | 1069 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1070 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
6a6c8786 | 1071 | struct pxa_camera_dev *pcdev = ici->priv; |
679419aa | 1072 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
8843d119 | 1073 | u32 pixfmt = icd->current_fmt->host_fmt->fourcc; |
679419aa | 1074 | unsigned long bus_flags, common_flags; |
760697be | 1075 | int ret; |
6a6c8786 GL |
1076 | struct pxa_cam *cam = icd->host_priv; |
1077 | ||
d2dcad49 GL |
1078 | ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample, |
1079 | &bus_flags); | |
6a6c8786 GL |
1080 | if (ret < 0) |
1081 | return ret; | |
1082 | ||
679419aa GL |
1083 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1084 | if (!ret) { | |
1085 | common_flags = soc_mbus_config_compatible(&cfg, | |
1086 | bus_flags); | |
1087 | if (!common_flags) { | |
1088 | dev_warn(icd->parent, | |
1089 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1090 | cfg.flags, bus_flags); | |
1091 | return -EINVAL; | |
1092 | } | |
1093 | } else if (ret != -ENOIOCTLCMD) { | |
1094 | return ret; | |
1095 | } else { | |
1096 | common_flags = bus_flags; | |
1097 | } | |
6a6c8786 GL |
1098 | |
1099 | pcdev->channels = 1; | |
1100 | ||
1101 | /* Make choises, based on platform preferences */ | |
679419aa GL |
1102 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
1103 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1104 | if (pcdev->platform_flags & PXA_CAMERA_HSP) |
679419aa | 1105 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
6a6c8786 | 1106 | else |
679419aa | 1107 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1108 | } |
1109 | ||
679419aa GL |
1110 | if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && |
1111 | (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1112 | if (pcdev->platform_flags & PXA_CAMERA_VSP) |
679419aa | 1113 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; |
6a6c8786 | 1114 | else |
679419aa | 1115 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1116 | } |
1117 | ||
679419aa GL |
1118 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1119 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
6a6c8786 | 1120 | if (pcdev->platform_flags & PXA_CAMERA_PCP) |
679419aa | 1121 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
6a6c8786 | 1122 | else |
679419aa | 1123 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
6a6c8786 GL |
1124 | } |
1125 | ||
679419aa GL |
1126 | cfg.flags = common_flags; |
1127 | ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); | |
1128 | if (ret < 0 && ret != -ENOIOCTLCMD) { | |
1129 | dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n", | |
1130 | common_flags, ret); | |
6a6c8786 | 1131 | return ret; |
679419aa GL |
1132 | } |
1133 | ||
1134 | cam->flags = common_flags; | |
6a6c8786 GL |
1135 | |
1136 | pxa_camera_setup_cicr(icd, common_flags, pixfmt); | |
3bc43840 GL |
1137 | |
1138 | return 0; | |
1139 | } | |
1140 | ||
2a48fc73 RJ |
1141 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1142 | unsigned char buswidth) | |
ad5f2e85 | 1143 | { |
679419aa | 1144 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1145 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
ad5f2e85 | 1146 | struct pxa_camera_dev *pcdev = ici->priv; |
679419aa GL |
1147 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
1148 | unsigned long bus_flags, common_flags; | |
2a48fc73 | 1149 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1150 | |
1151 | if (ret < 0) | |
1152 | return ret; | |
1153 | ||
679419aa GL |
1154 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1155 | if (!ret) { | |
1156 | common_flags = soc_mbus_config_compatible(&cfg, | |
1157 | bus_flags); | |
1158 | if (!common_flags) { | |
1159 | dev_warn(icd->parent, | |
1160 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1161 | cfg.flags, bus_flags); | |
1162 | return -EINVAL; | |
1163 | } | |
1164 | } else if (ret == -ENOIOCTLCMD) { | |
1165 | ret = 0; | |
1166 | } | |
ad5f2e85 | 1167 | |
679419aa | 1168 | return ret; |
ad5f2e85 GL |
1169 | } |
1170 | ||
760697be | 1171 | static const struct soc_mbus_pixelfmt pxa_camera_formats[] = { |
2a48fc73 | 1172 | { |
760697be GL |
1173 | .fourcc = V4L2_PIX_FMT_YUV422P, |
1174 | .name = "Planar YUV422 16 bit", | |
1175 | .bits_per_sample = 8, | |
1176 | .packing = SOC_MBUS_PACKING_2X8_PADHI, | |
1177 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 1178 | .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V, |
2a48fc73 RJ |
1179 | }, |
1180 | }; | |
1181 | ||
760697be GL |
1182 | /* This will be corrected as we get more formats */ |
1183 | static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
ad5f2e85 | 1184 | { |
760697be GL |
1185 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
1186 | (fmt->bits_per_sample == 8 && | |
1187 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
1188 | (fmt->bits_per_sample > 8 && | |
1189 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
2a48fc73 RJ |
1190 | } |
1191 | ||
3805f201 | 1192 | static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, |
2a48fc73 RJ |
1193 | struct soc_camera_format_xlate *xlate) |
1194 | { | |
760697be | 1195 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1196 | struct device *dev = icd->parent; |
760697be | 1197 | int formats = 0, ret; |
6a6c8786 | 1198 | struct pxa_cam *cam; |
ebcff5fc HV |
1199 | struct v4l2_subdev_mbus_code_enum code = { |
1200 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1201 | .index = idx, | |
1202 | }; | |
760697be | 1203 | const struct soc_mbus_pixelfmt *fmt; |
2a48fc73 | 1204 | |
ebcff5fc | 1205 | ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code); |
760697be GL |
1206 | if (ret < 0) |
1207 | /* No more formats */ | |
1208 | return 0; | |
2a48fc73 | 1209 | |
ebcff5fc | 1210 | fmt = soc_mbus_get_fmtdesc(code.code); |
760697be | 1211 | if (!fmt) { |
ebcff5fc | 1212 | dev_err(dev, "Invalid format code #%u: %d\n", idx, code.code); |
2a48fc73 | 1213 | return 0; |
760697be | 1214 | } |
3bc43840 | 1215 | |
760697be GL |
1216 | /* This also checks support for the requested bits-per-sample */ |
1217 | ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample); | |
2a48fc73 RJ |
1218 | if (ret < 0) |
1219 | return 0; | |
1220 | ||
6a6c8786 GL |
1221 | if (!icd->host_priv) { |
1222 | cam = kzalloc(sizeof(*cam), GFP_KERNEL); | |
1223 | if (!cam) | |
1224 | return -ENOMEM; | |
1225 | ||
1226 | icd->host_priv = cam; | |
1227 | } else { | |
1228 | cam = icd->host_priv; | |
1229 | } | |
1230 | ||
ebcff5fc | 1231 | switch (code.code) { |
27ffaeb0 | 1232 | case MEDIA_BUS_FMT_UYVY8_2X8: |
2a48fc73 RJ |
1233 | formats++; |
1234 | if (xlate) { | |
760697be | 1235 | xlate->host_fmt = &pxa_camera_formats[0]; |
ebcff5fc | 1236 | xlate->code = code.code; |
2a48fc73 | 1237 | xlate++; |
760697be | 1238 | dev_dbg(dev, "Providing format %s using code %d\n", |
ebcff5fc | 1239 | pxa_camera_formats[0].name, code.code); |
2a48fc73 | 1240 | } |
27ffaeb0 BB |
1241 | case MEDIA_BUS_FMT_VYUY8_2X8: |
1242 | case MEDIA_BUS_FMT_YUYV8_2X8: | |
1243 | case MEDIA_BUS_FMT_YVYU8_2X8: | |
1244 | case MEDIA_BUS_FMT_RGB565_2X8_LE: | |
1245 | case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: | |
760697be | 1246 | if (xlate) |
0166b743 | 1247 | dev_dbg(dev, "Providing format %s packed\n", |
760697be | 1248 | fmt->name); |
2a48fc73 RJ |
1249 | break; |
1250 | default: | |
760697be GL |
1251 | if (!pxa_camera_packing_supported(fmt)) |
1252 | return 0; | |
1253 | if (xlate) | |
0166b743 | 1254 | dev_dbg(dev, |
2a48fc73 | 1255 | "Providing format %s in pass-through mode\n", |
760697be GL |
1256 | fmt->name); |
1257 | } | |
1258 | ||
1259 | /* Generic pass-through */ | |
1260 | formats++; | |
1261 | if (xlate) { | |
1262 | xlate->host_fmt = fmt; | |
ebcff5fc | 1263 | xlate->code = code.code; |
760697be | 1264 | xlate++; |
2a48fc73 RJ |
1265 | } |
1266 | ||
1267 | return formats; | |
1268 | } | |
1269 | ||
6a6c8786 GL |
1270 | static void pxa_camera_put_formats(struct soc_camera_device *icd) |
1271 | { | |
1272 | kfree(icd->host_priv); | |
1273 | icd->host_priv = NULL; | |
1274 | } | |
1275 | ||
760697be | 1276 | static int pxa_camera_check_frame(u32 width, u32 height) |
6a6c8786 GL |
1277 | { |
1278 | /* limit to pxa hardware capabilities */ | |
760697be GL |
1279 | return height < 32 || height > 2048 || width < 48 || width > 2048 || |
1280 | (width & 0x01); | |
6a6c8786 GL |
1281 | } |
1282 | ||
09e231b3 | 1283 | static int pxa_camera_set_crop(struct soc_camera_device *icd, |
448a61f0 | 1284 | const struct v4l2_crop *a) |
09e231b3 | 1285 | { |
448a61f0 | 1286 | const struct v4l2_rect *rect = &a->c; |
7dfff953 GL |
1287 | struct device *dev = icd->parent; |
1288 | struct soc_camera_host *ici = to_soc_camera_host(dev); | |
09e231b3 | 1289 | struct pxa_camera_dev *pcdev = ici->priv; |
c9c1f1c0 | 1290 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
1291 | struct soc_camera_sense sense = { |
1292 | .master_clock = pcdev->mclk, | |
1293 | .pixel_clock_max = pcdev->ciclk / 4, | |
1294 | }; | |
da298c6d HV |
1295 | struct v4l2_subdev_format fmt = { |
1296 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1297 | }; | |
1298 | struct v4l2_mbus_framefmt *mf = &fmt.format; | |
6a6c8786 | 1299 | struct pxa_cam *cam = icd->host_priv; |
760697be | 1300 | u32 fourcc = icd->current_fmt->host_fmt->fourcc; |
09e231b3 GL |
1301 | int ret; |
1302 | ||
1303 | /* If PCLK is used to latch data from the sensor, check sense */ | |
1304 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1305 | icd->sense = &sense; | |
1306 | ||
08590b96 | 1307 | ret = v4l2_subdev_call(sd, video, s_crop, a); |
09e231b3 GL |
1308 | |
1309 | icd->sense = NULL; | |
1310 | ||
1311 | if (ret < 0) { | |
0166b743 | 1312 | dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n", |
09e231b3 | 1313 | rect->width, rect->height, rect->left, rect->top); |
6a6c8786 GL |
1314 | return ret; |
1315 | } | |
1316 | ||
da298c6d | 1317 | ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt); |
6a6c8786 GL |
1318 | if (ret < 0) |
1319 | return ret; | |
1320 | ||
da298c6d | 1321 | if (pxa_camera_check_frame(mf->width, mf->height)) { |
6a6c8786 GL |
1322 | /* |
1323 | * Camera cropping produced a frame beyond our capabilities. | |
1324 | * FIXME: just extract a subframe, that we can process. | |
1325 | */ | |
da298c6d HV |
1326 | v4l_bound_align_image(&mf->width, 48, 2048, 1, |
1327 | &mf->height, 32, 2048, 0, | |
760697be | 1328 | fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
ebf984bb | 1329 | ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &fmt); |
6a6c8786 GL |
1330 | if (ret < 0) |
1331 | return ret; | |
1332 | ||
da298c6d | 1333 | if (pxa_camera_check_frame(mf->width, mf->height)) { |
7dfff953 | 1334 | dev_warn(icd->parent, |
6a6c8786 GL |
1335 | "Inconsistent state. Use S_FMT to repair\n"); |
1336 | return -EINVAL; | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | |
09e231b3 | 1341 | if (sense.pixel_clock > sense.pixel_clock_max) { |
0166b743 | 1342 | dev_err(dev, |
09e231b3 GL |
1343 | "pixel clock %lu set by the camera too high!", |
1344 | sense.pixel_clock); | |
1345 | return -EIO; | |
1346 | } | |
1347 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1348 | } | |
1349 | ||
da298c6d HV |
1350 | icd->user_width = mf->width; |
1351 | icd->user_height = mf->height; | |
6a6c8786 | 1352 | |
760697be | 1353 | pxa_camera_setup_cicr(icd, cam->flags, fourcc); |
6a6c8786 | 1354 | |
09e231b3 GL |
1355 | return ret; |
1356 | } | |
1357 | ||
d8fac217 | 1358 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
09e231b3 | 1359 | struct v4l2_format *f) |
ad5f2e85 | 1360 | { |
7dfff953 GL |
1361 | struct device *dev = icd->parent; |
1362 | struct soc_camera_host *ici = to_soc_camera_host(dev); | |
cf34cba7 | 1363 | struct pxa_camera_dev *pcdev = ici->priv; |
c9c1f1c0 | 1364 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
0ad675eb | 1365 | const struct soc_camera_format_xlate *xlate = NULL; |
cf34cba7 GL |
1366 | struct soc_camera_sense sense = { |
1367 | .master_clock = pcdev->mclk, | |
1368 | .pixel_clock_max = pcdev->ciclk / 4, | |
1369 | }; | |
09e231b3 | 1370 | struct v4l2_pix_format *pix = &f->fmt.pix; |
ebf984bb HV |
1371 | struct v4l2_subdev_format format = { |
1372 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1373 | }; | |
1374 | struct v4l2_mbus_framefmt *mf = &format.format; | |
0ad675eb | 1375 | int ret; |
25c4d74e | 1376 | |
09e231b3 GL |
1377 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1378 | if (!xlate) { | |
0166b743 | 1379 | dev_warn(dev, "Format %x not found\n", pix->pixelformat); |
09e231b3 | 1380 | return -EINVAL; |
0ad675eb | 1381 | } |
2a48fc73 | 1382 | |
cf34cba7 GL |
1383 | /* If PCLK is used to latch data from the sensor, check sense */ |
1384 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
760697be | 1385 | /* The caller holds a mutex. */ |
cf34cba7 GL |
1386 | icd->sense = &sense; |
1387 | ||
ebf984bb HV |
1388 | mf->width = pix->width; |
1389 | mf->height = pix->height; | |
1390 | mf->field = pix->field; | |
1391 | mf->colorspace = pix->colorspace; | |
1392 | mf->code = xlate->code; | |
760697be | 1393 | |
ebf984bb | 1394 | ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &format); |
760697be | 1395 | |
ebf984bb | 1396 | if (mf->code != xlate->code) |
760697be | 1397 | return -EINVAL; |
2a48fc73 | 1398 | |
cf34cba7 GL |
1399 | icd->sense = NULL; |
1400 | ||
1401 | if (ret < 0) { | |
0166b743 | 1402 | dev_warn(dev, "Failed to configure for format %x\n", |
09e231b3 | 1403 | pix->pixelformat); |
ebf984bb | 1404 | } else if (pxa_camera_check_frame(mf->width, mf->height)) { |
6a6c8786 GL |
1405 | dev_warn(dev, |
1406 | "Camera driver produced an unsupported frame %dx%d\n", | |
ebf984bb | 1407 | mf->width, mf->height); |
6a6c8786 | 1408 | ret = -EINVAL; |
cf34cba7 GL |
1409 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1410 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
0166b743 | 1411 | dev_err(dev, |
cf34cba7 GL |
1412 | "pixel clock %lu set by the camera too high!", |
1413 | sense.pixel_clock); | |
1414 | return -EIO; | |
1415 | } | |
1416 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1417 | } | |
2a48fc73 | 1418 | |
760697be GL |
1419 | if (ret < 0) |
1420 | return ret; | |
1421 | ||
ebf984bb HV |
1422 | pix->width = mf->width; |
1423 | pix->height = mf->height; | |
1424 | pix->field = mf->field; | |
1425 | pix->colorspace = mf->colorspace; | |
760697be | 1426 | icd->current_fmt = xlate; |
25c4d74e GL |
1427 | |
1428 | return ret; | |
ad5f2e85 GL |
1429 | } |
1430 | ||
d8fac217 GL |
1431 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1432 | struct v4l2_format *f) | |
3bc43840 | 1433 | { |
c9c1f1c0 | 1434 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
2a48fc73 RJ |
1435 | const struct soc_camera_format_xlate *xlate; |
1436 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
5eab4983 HV |
1437 | struct v4l2_subdev_pad_config pad_cfg; |
1438 | struct v4l2_subdev_format format = { | |
1439 | .which = V4L2_SUBDEV_FORMAT_TRY, | |
1440 | }; | |
1441 | struct v4l2_mbus_framefmt *mf = &format.format; | |
2a48fc73 | 1442 | __u32 pixfmt = pix->pixelformat; |
bf507158 | 1443 | int ret; |
a2c8c68c | 1444 | |
2a48fc73 RJ |
1445 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1446 | if (!xlate) { | |
7dfff953 | 1447 | dev_warn(icd->parent, "Format %x not found\n", pixfmt); |
25c4d74e | 1448 | return -EINVAL; |
2a48fc73 | 1449 | } |
25c4d74e | 1450 | |
92a8337b | 1451 | /* |
4a6b8df2 TP |
1452 | * Limit to pxa hardware capabilities. YUV422P planar format requires |
1453 | * images size to be a multiple of 16 bytes. If not, zeros will be | |
1454 | * inserted between Y and U planes, and U and V planes, which violates | |
1455 | * the YUV422P standard. | |
92a8337b | 1456 | */ |
4a6b8df2 TP |
1457 | v4l_bound_align_image(&pix->width, 48, 2048, 1, |
1458 | &pix->height, 32, 2048, 0, | |
6a6c8786 | 1459 | pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
92a8337b | 1460 | |
ad5f2e85 | 1461 | /* limit to sensor capabilities */ |
5eab4983 HV |
1462 | mf->width = pix->width; |
1463 | mf->height = pix->height; | |
91401219 | 1464 | /* Only progressive video supported so far */ |
5eab4983 HV |
1465 | mf->field = V4L2_FIELD_NONE; |
1466 | mf->colorspace = pix->colorspace; | |
1467 | mf->code = xlate->code; | |
bf507158 | 1468 | |
5eab4983 | 1469 | ret = v4l2_subdev_call(sd, pad, set_fmt, &pad_cfg, &format); |
760697be GL |
1470 | if (ret < 0) |
1471 | return ret; | |
06daa1af | 1472 | |
5eab4983 HV |
1473 | pix->width = mf->width; |
1474 | pix->height = mf->height; | |
1475 | pix->colorspace = mf->colorspace; | |
760697be | 1476 | |
5eab4983 | 1477 | switch (mf->field) { |
760697be GL |
1478 | case V4L2_FIELD_ANY: |
1479 | case V4L2_FIELD_NONE: | |
1480 | pix->field = V4L2_FIELD_NONE; | |
1481 | break; | |
1482 | default: | |
1483 | /* TODO: support interlaced at least in pass-through mode */ | |
7dfff953 | 1484 | dev_err(icd->parent, "Field type %d unsupported.\n", |
5eab4983 | 1485 | mf->field); |
06daa1af GL |
1486 | return -EINVAL; |
1487 | } | |
1488 | ||
bf507158 | 1489 | return ret; |
3bc43840 GL |
1490 | } |
1491 | ||
57bee29d | 1492 | static int pxa_camera_reqbufs(struct soc_camera_device *icd, |
7102b773 | 1493 | struct v4l2_requestbuffers *p) |
3bc43840 GL |
1494 | { |
1495 | int i; | |
1496 | ||
5d28d525 GL |
1497 | /* |
1498 | * This is for locking debugging only. I removed spinlocks and now I | |
3bc43840 GL |
1499 | * check whether .prepare is ever called on a linked buffer, or whether |
1500 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
5d28d525 GL |
1501 | * it hadn't triggered |
1502 | */ | |
3bc43840 | 1503 | for (i = 0; i < p->count; i++) { |
57bee29d | 1504 | struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i], |
3bc43840 GL |
1505 | struct pxa_buffer, vb); |
1506 | buf->inwork = 0; | |
1507 | INIT_LIST_HEAD(&buf->vb.queue); | |
1508 | } | |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
7102b773 | 1513 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 | 1514 | { |
57bee29d | 1515 | struct soc_camera_device *icd = file->private_data; |
3bc43840 GL |
1516 | struct pxa_buffer *buf; |
1517 | ||
57bee29d | 1518 | buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer, |
3bc43840 GL |
1519 | vb.stream); |
1520 | ||
1521 | poll_wait(file, &buf->vb.done, pt); | |
1522 | ||
1523 | if (buf->vb.state == VIDEOBUF_DONE || | |
1524 | buf->vb.state == VIDEOBUF_ERROR) | |
1525 | return POLLIN|POLLRDNORM; | |
1526 | ||
1527 | return 0; | |
1528 | } | |
1529 | ||
7102b773 GL |
1530 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1531 | struct v4l2_capability *cap) | |
3bc43840 GL |
1532 | { |
1533 | /* cap->name is set by the firendly caller:-> */ | |
1534 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
7d96c3e4 GL |
1535 | cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
1536 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; | |
3bc43840 GL |
1537 | |
1538 | return 0; | |
1539 | } | |
1540 | ||
7254026c | 1541 | static int pxa_camera_suspend(struct device *dev) |
3f6ac497 | 1542 | { |
7254026c | 1543 | struct soc_camera_host *ici = to_soc_camera_host(dev); |
3f6ac497 RJ |
1544 | struct pxa_camera_dev *pcdev = ici->priv; |
1545 | int i = 0, ret = 0; | |
1546 | ||
5ca11fa3 EM |
1547 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1548 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1549 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1550 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1551 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 | 1552 | |
f7f6ce2d GL |
1553 | if (pcdev->soc_host.icd) { |
1554 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); | |
497833c6 GL |
1555 | ret = v4l2_subdev_call(sd, core, s_power, 0); |
1556 | if (ret == -ENOIOCTLCMD) | |
1557 | ret = 0; | |
1558 | } | |
3f6ac497 RJ |
1559 | |
1560 | return ret; | |
1561 | } | |
1562 | ||
7254026c | 1563 | static int pxa_camera_resume(struct device *dev) |
3f6ac497 | 1564 | { |
7254026c | 1565 | struct soc_camera_host *ici = to_soc_camera_host(dev); |
3f6ac497 RJ |
1566 | struct pxa_camera_dev *pcdev = ici->priv; |
1567 | int i = 0, ret = 0; | |
1568 | ||
5ca11fa3 EM |
1569 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1570 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1571 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1572 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1573 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 | 1574 | |
f7f6ce2d GL |
1575 | if (pcdev->soc_host.icd) { |
1576 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); | |
497833c6 GL |
1577 | ret = v4l2_subdev_call(sd, core, s_power, 1); |
1578 | if (ret == -ENOIOCTLCMD) | |
1579 | ret = 0; | |
1580 | } | |
3f6ac497 RJ |
1581 | |
1582 | /* Restart frame capture if active buffer exists */ | |
256b0233 RJ |
1583 | if (!ret && pcdev->active) |
1584 | pxa_camera_start_capture(pcdev); | |
3f6ac497 RJ |
1585 | |
1586 | return ret; | |
1587 | } | |
1588 | ||
b8d9904c GL |
1589 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1590 | .owner = THIS_MODULE, | |
1591 | .add = pxa_camera_add_device, | |
1592 | .remove = pxa_camera_remove_device, | |
39b553db GL |
1593 | .clock_start = pxa_camera_clock_start, |
1594 | .clock_stop = pxa_camera_clock_stop, | |
09e231b3 | 1595 | .set_crop = pxa_camera_set_crop, |
2a48fc73 | 1596 | .get_formats = pxa_camera_get_formats, |
6a6c8786 | 1597 | .put_formats = pxa_camera_put_formats, |
d8fac217 GL |
1598 | .set_fmt = pxa_camera_set_fmt, |
1599 | .try_fmt = pxa_camera_try_fmt, | |
092d3921 | 1600 | .init_videobuf = pxa_camera_init_videobuf, |
b8d9904c GL |
1601 | .reqbufs = pxa_camera_reqbufs, |
1602 | .poll = pxa_camera_poll, | |
1603 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1604 | .set_bus_param = pxa_camera_set_bus_param, |
1605 | }; | |
1606 | ||
e9a1d94f RJ |
1607 | static int pxa_camera_pdata_from_dt(struct device *dev, |
1608 | struct pxa_camera_dev *pcdev) | |
1609 | { | |
1610 | u32 mclk_rate; | |
1611 | struct device_node *np = dev->of_node; | |
1612 | struct v4l2_of_endpoint ep; | |
1613 | int err = of_property_read_u32(np, "clock-frequency", | |
1614 | &mclk_rate); | |
1615 | if (!err) { | |
1616 | pcdev->platform_flags |= PXA_CAMERA_MCLK_EN; | |
1617 | pcdev->mclk = mclk_rate; | |
1618 | } | |
1619 | ||
1620 | np = of_graph_get_next_endpoint(np, NULL); | |
1621 | if (!np) { | |
1622 | dev_err(dev, "could not find endpoint\n"); | |
1623 | return -EINVAL; | |
1624 | } | |
1625 | ||
1626 | err = v4l2_of_parse_endpoint(np, &ep); | |
1627 | if (err) { | |
1628 | dev_err(dev, "could not parse endpoint\n"); | |
1629 | goto out; | |
1630 | } | |
1631 | ||
1632 | switch (ep.bus.parallel.bus_width) { | |
1633 | case 4: | |
1634 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4; | |
1635 | break; | |
1636 | case 5: | |
1637 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5; | |
1638 | break; | |
1639 | case 8: | |
1640 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8; | |
1641 | break; | |
1642 | case 9: | |
1643 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9; | |
1644 | break; | |
1645 | case 10: | |
1646 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1647 | break; | |
1648 | default: | |
1649 | break; | |
c611c908 | 1650 | } |
e9a1d94f RJ |
1651 | |
1652 | if (ep.bus.parallel.flags & V4L2_MBUS_MASTER) | |
1653 | pcdev->platform_flags |= PXA_CAMERA_MASTER; | |
1654 | if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) | |
1655 | pcdev->platform_flags |= PXA_CAMERA_HSP; | |
1656 | if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) | |
1657 | pcdev->platform_flags |= PXA_CAMERA_VSP; | |
1658 | if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) | |
1659 | pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP; | |
1660 | if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) | |
1661 | pcdev->platform_flags |= PXA_CAMERA_PCLK_EN; | |
1662 | ||
1663 | out: | |
1664 | of_node_put(np); | |
1665 | ||
1666 | return err; | |
1667 | } | |
1668 | ||
4c62e976 | 1669 | static int pxa_camera_probe(struct platform_device *pdev) |
3bc43840 GL |
1670 | { |
1671 | struct pxa_camera_dev *pcdev; | |
1672 | struct resource *res; | |
1673 | void __iomem *base; | |
1e77d55a RJ |
1674 | struct dma_slave_config config = { |
1675 | .src_addr_width = 0, | |
1676 | .src_maxburst = 8, | |
1677 | .direction = DMA_DEV_TO_MEM, | |
1678 | }; | |
1679 | dma_cap_mask_t mask; | |
1680 | struct pxad_param params; | |
02da4659 | 1681 | int irq; |
1e77d55a | 1682 | int err = 0, i; |
3bc43840 GL |
1683 | |
1684 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1685 | irq = platform_get_irq(pdev, 0); | |
47de201c JL |
1686 | if (!res || irq < 0) |
1687 | return -ENODEV; | |
3bc43840 | 1688 | |
47de201c | 1689 | pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL); |
3bc43840 | 1690 | if (!pcdev) { |
7102b773 | 1691 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
47de201c | 1692 | return -ENOMEM; |
3bc43840 GL |
1693 | } |
1694 | ||
47de201c JL |
1695 | pcdev->clk = devm_clk_get(&pdev->dev, NULL); |
1696 | if (IS_ERR(pcdev->clk)) | |
1697 | return PTR_ERR(pcdev->clk); | |
3bc43840 | 1698 | |
3bc43840 GL |
1699 | pcdev->res = res; |
1700 | ||
1701 | pcdev->pdata = pdev->dev.platform_data; | |
e9a1d94f RJ |
1702 | if (&pdev->dev.of_node && !pcdev->pdata) { |
1703 | err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev); | |
1704 | } else { | |
1705 | pcdev->platform_flags = pcdev->pdata->flags; | |
1706 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; | |
1707 | } | |
1708 | if (err < 0) | |
1709 | return err; | |
1710 | ||
ad5f2e85 GL |
1711 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1712 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
5d28d525 GL |
1713 | /* |
1714 | * Platform hasn't set available data widths. This is bad. | |
1715 | * Warn and use a default. | |
1716 | */ | |
3bc43840 GL |
1717 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1718 | "data widths, using default 10 bit\n"); | |
1719 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1720 | } | |
679419aa GL |
1721 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8) |
1722 | pcdev->width_flags = 1 << 7; | |
1723 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9) | |
1724 | pcdev->width_flags |= 1 << 8; | |
1725 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10) | |
1726 | pcdev->width_flags |= 1 << 9; | |
cf34cba7 | 1727 | if (!pcdev->mclk) { |
3bc43840 | 1728 | dev_warn(&pdev->dev, |
cf34cba7 | 1729 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1730 | "Using default 20MHz\n"); |
cf34cba7 | 1731 | pcdev->mclk = 20000000; |
3bc43840 GL |
1732 | } |
1733 | ||
40e2e092 | 1734 | pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); |
cf34cba7 | 1735 | |
3bc43840 GL |
1736 | INIT_LIST_HEAD(&pcdev->capture); |
1737 | spin_lock_init(&pcdev->lock); | |
1738 | ||
1739 | /* | |
1740 | * Request the regions. | |
1741 | */ | |
8efdb135 SK |
1742 | base = devm_ioremap_resource(&pdev->dev, res); |
1743 | if (IS_ERR(base)) | |
1744 | return PTR_ERR(base); | |
1745 | ||
3bc43840 GL |
1746 | pcdev->irq = irq; |
1747 | pcdev->base = base; | |
3bc43840 GL |
1748 | |
1749 | /* request dma */ | |
1e77d55a RJ |
1750 | dma_cap_zero(mask); |
1751 | dma_cap_set(DMA_SLAVE, mask); | |
1752 | dma_cap_set(DMA_PRIVATE, mask); | |
1753 | ||
1754 | params.prio = 0; | |
1755 | params.drcmr = 68; | |
1756 | pcdev->dma_chans[0] = | |
1757 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1758 | ¶ms, &pdev->dev, "CI_Y"); | |
1759 | if (!pcdev->dma_chans[0]) { | |
eff505fa | 1760 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); |
1e77d55a | 1761 | return -ENODEV; |
3bc43840 | 1762 | } |
a5462e5b | 1763 | |
1e77d55a RJ |
1764 | params.drcmr = 69; |
1765 | pcdev->dma_chans[1] = | |
1766 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1767 | ¶ms, &pdev->dev, "CI_U"); | |
1768 | if (!pcdev->dma_chans[1]) { | |
1769 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); | |
a5462e5b MR |
1770 | goto exit_free_dma_y; |
1771 | } | |
a5462e5b | 1772 | |
1e77d55a RJ |
1773 | params.drcmr = 70; |
1774 | pcdev->dma_chans[2] = | |
1775 | dma_request_slave_channel_compat(mask, pxad_filter_fn, | |
1776 | ¶ms, &pdev->dev, "CI_V"); | |
1777 | if (!pcdev->dma_chans[2]) { | |
eff505fa | 1778 | dev_err(&pdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1779 | goto exit_free_dma_u; |
1780 | } | |
3bc43840 | 1781 | |
1e77d55a RJ |
1782 | for (i = 0; i < 3; i++) { |
1783 | config.src_addr = pcdev->res->start + CIBR0 + i * 8; | |
1784 | err = dmaengine_slave_config(pcdev->dma_chans[i], &config); | |
1785 | if (err < 0) { | |
1786 | dev_err(&pdev->dev, "dma slave config failed: %d\n", | |
1787 | err); | |
1788 | goto exit_free_dma; | |
1789 | } | |
1790 | } | |
3bc43840 GL |
1791 | |
1792 | /* request irq */ | |
47de201c JL |
1793 | err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0, |
1794 | PXA_CAM_DRV_NAME, pcdev); | |
3bc43840 | 1795 | if (err) { |
47de201c | 1796 | dev_err(&pdev->dev, "Camera interrupt register failed\n"); |
3bc43840 GL |
1797 | goto exit_free_dma; |
1798 | } | |
1799 | ||
eb6c8558 GL |
1800 | pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; |
1801 | pcdev->soc_host.ops = &pxa_soc_camera_host_ops; | |
1802 | pcdev->soc_host.priv = pcdev; | |
979ea1dd | 1803 | pcdev->soc_host.v4l2_dev.dev = &pdev->dev; |
eb6c8558 | 1804 | pcdev->soc_host.nr = pdev->id; |
e623ebe6 | 1805 | tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev); |
eff505fa | 1806 | |
eb6c8558 | 1807 | err = soc_camera_host_register(&pcdev->soc_host); |
3bc43840 | 1808 | if (err) |
47de201c | 1809 | goto exit_free_dma; |
3bc43840 GL |
1810 | |
1811 | return 0; | |
1812 | ||
3bc43840 | 1813 | exit_free_dma: |
1e77d55a | 1814 | dma_release_channel(pcdev->dma_chans[2]); |
a5462e5b | 1815 | exit_free_dma_u: |
1e77d55a | 1816 | dma_release_channel(pcdev->dma_chans[1]); |
a5462e5b | 1817 | exit_free_dma_y: |
1e77d55a | 1818 | dma_release_channel(pcdev->dma_chans[0]); |
3bc43840 GL |
1819 | return err; |
1820 | } | |
1821 | ||
4c62e976 | 1822 | static int pxa_camera_remove(struct platform_device *pdev) |
3bc43840 | 1823 | { |
eff505fa GL |
1824 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1825 | struct pxa_camera_dev *pcdev = container_of(soc_host, | |
1826 | struct pxa_camera_dev, soc_host); | |
3bc43840 | 1827 | |
1e77d55a RJ |
1828 | dma_release_channel(pcdev->dma_chans[0]); |
1829 | dma_release_channel(pcdev->dma_chans[1]); | |
1830 | dma_release_channel(pcdev->dma_chans[2]); | |
3bc43840 | 1831 | |
eff505fa | 1832 | soc_camera_host_unregister(soc_host); |
3bc43840 | 1833 | |
7102b773 | 1834 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1835 | |
3bc43840 GL |
1836 | return 0; |
1837 | } | |
1838 | ||
56a49194 | 1839 | static const struct dev_pm_ops pxa_camera_pm = { |
7254026c GL |
1840 | .suspend = pxa_camera_suspend, |
1841 | .resume = pxa_camera_resume, | |
1842 | }; | |
1843 | ||
e9a1d94f RJ |
1844 | static const struct of_device_id pxa_camera_of_match[] = { |
1845 | { .compatible = "marvell,pxa270-qci", }, | |
1846 | {}, | |
1847 | }; | |
1848 | MODULE_DEVICE_TABLE(of, pxa_camera_of_match); | |
1849 | ||
3bc43840 | 1850 | static struct platform_driver pxa_camera_driver = { |
6003b2ad | 1851 | .driver = { |
3bc43840 | 1852 | .name = PXA_CAM_DRV_NAME, |
7254026c | 1853 | .pm = &pxa_camera_pm, |
e9a1d94f | 1854 | .of_match_table = of_match_ptr(pxa_camera_of_match), |
3bc43840 GL |
1855 | }, |
1856 | .probe = pxa_camera_probe, | |
4c62e976 | 1857 | .remove = pxa_camera_remove, |
3bc43840 GL |
1858 | }; |
1859 | ||
1d6629b1 | 1860 | module_platform_driver(pxa_camera_driver); |
3bc43840 GL |
1861 | |
1862 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1863 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1864 | MODULE_LICENSE("GPL"); | |
64dc3c1a | 1865 | MODULE_VERSION(PXA_CAM_VERSION); |
40e2e092 | 1866 | MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); |