Commit | Line | Data |
---|---|---|
dba4a180 LP |
1 | /* |
2 | * vsp1_pipe.c -- R-Car VSP1 Pipeline | |
3 | * | |
4 | * Copyright (C) 2013-2015 Renesas Electronics Corporation | |
5 | * | |
6 | * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
1517b039 | 14 | #include <linux/delay.h> |
dba4a180 LP |
15 | #include <linux/list.h> |
16 | #include <linux/sched.h> | |
17 | #include <linux/wait.h> | |
18 | ||
19 | #include <media/media-entity.h> | |
20 | #include <media/v4l2-subdev.h> | |
21 | ||
22 | #include "vsp1.h" | |
23 | #include "vsp1_bru.h" | |
1517b039 | 24 | #include "vsp1_dl.h" |
dba4a180 LP |
25 | #include "vsp1_entity.h" |
26 | #include "vsp1_pipe.h" | |
27 | #include "vsp1_rwpf.h" | |
28 | #include "vsp1_uds.h" | |
29 | ||
c618b185 LP |
30 | /* ----------------------------------------------------------------------------- |
31 | * Helper Functions | |
32 | */ | |
33 | ||
34 | static const struct vsp1_format_info vsp1_video_formats[] = { | |
35 | { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32, | |
36 | VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
37 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
38 | 1, { 8, 0, 0 }, false, false, 1, 1, false }, | |
39 | { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32, | |
40 | VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
41 | VI6_RPF_DSWAP_P_WDS, | |
42 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, | |
43 | { V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32, | |
44 | VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
45 | VI6_RPF_DSWAP_P_WDS, | |
46 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, | |
47 | { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32, | |
48 | VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
49 | VI6_RPF_DSWAP_P_WDS, | |
50 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, | |
51 | { V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32, | |
52 | VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
53 | VI6_RPF_DSWAP_P_WDS, | |
54 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, | |
55 | { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32, | |
56 | VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
57 | VI6_RPF_DSWAP_P_WDS, | |
58 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, | |
59 | { V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32, | |
60 | VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
61 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
62 | 1, { 24, 0, 0 }, false, false, 1, 1, false }, | |
63 | { V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32, | |
64 | VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
65 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
66 | 1, { 24, 0, 0 }, false, false, 1, 1, false }, | |
67 | { V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32, | |
68 | VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, | |
69 | 1, { 32, 0, 0 }, false, false, 1, 1, true }, | |
70 | { V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32, | |
71 | VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS, | |
72 | 1, { 32, 0, 0 }, false, false, 1, 1, false }, | |
73 | { V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32, | |
74 | VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
75 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
76 | 1, { 32, 0, 0 }, false, false, 1, 1, true }, | |
77 | { V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32, | |
78 | VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
79 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
80 | 1, { 32, 0, 0 }, false, false, 1, 1, false }, | |
81 | { V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32, | |
82 | VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
83 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
84 | 1, { 16, 0, 0 }, false, false, 2, 1, false }, | |
85 | { V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32, | |
86 | VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
87 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
88 | 1, { 16, 0, 0 }, false, true, 2, 1, false }, | |
89 | { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32, | |
90 | VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
91 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
92 | 1, { 16, 0, 0 }, true, false, 2, 1, false }, | |
93 | { V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32, | |
94 | VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
95 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
96 | 1, { 16, 0, 0 }, true, true, 2, 1, false }, | |
97 | { V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32, | |
98 | VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
99 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
100 | 2, { 8, 16, 0 }, false, false, 2, 2, false }, | |
101 | { V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32, | |
102 | VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
103 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
104 | 2, { 8, 16, 0 }, false, true, 2, 2, false }, | |
105 | { V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32, | |
106 | VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
107 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
108 | 2, { 8, 16, 0 }, false, false, 2, 1, false }, | |
109 | { V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32, | |
110 | VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
111 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
112 | 2, { 8, 16, 0 }, false, true, 2, 1, false }, | |
113 | { V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32, | |
114 | VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
115 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
116 | 3, { 8, 8, 8 }, false, false, 2, 2, false }, | |
117 | { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32, | |
118 | VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
119 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
120 | 3, { 8, 8, 8 }, false, true, 2, 2, false }, | |
121 | { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32, | |
122 | VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
123 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
124 | 3, { 8, 8, 8 }, false, false, 2, 1, false }, | |
125 | { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32, | |
126 | VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
127 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
128 | 3, { 8, 8, 8 }, false, true, 2, 1, false }, | |
129 | { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32, | |
130 | VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
131 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
132 | 3, { 8, 8, 8 }, false, false, 1, 1, false }, | |
133 | { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32, | |
134 | VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | |
135 | VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS, | |
136 | 3, { 8, 8, 8 }, false, true, 1, 1, false }, | |
137 | }; | |
138 | ||
139 | /* | |
140 | * vsp1_get_format_info - Retrieve format information for a 4CC | |
141 | * @fourcc: the format 4CC | |
142 | * | |
143 | * Return a pointer to the format information structure corresponding to the | |
144 | * given V4L2 format 4CC, or NULL if no corresponding format can be found. | |
145 | */ | |
146 | const struct vsp1_format_info *vsp1_get_format_info(u32 fourcc) | |
147 | { | |
148 | unsigned int i; | |
149 | ||
150 | for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) { | |
151 | const struct vsp1_format_info *info = &vsp1_video_formats[i]; | |
152 | ||
153 | if (info->fourcc == fourcc) | |
154 | return info; | |
155 | } | |
156 | ||
157 | return NULL; | |
158 | } | |
159 | ||
dba4a180 LP |
160 | /* ----------------------------------------------------------------------------- |
161 | * Pipeline Management | |
162 | */ | |
163 | ||
164 | void vsp1_pipeline_reset(struct vsp1_pipeline *pipe) | |
165 | { | |
96bfa6a5 LP |
166 | unsigned int i; |
167 | ||
dba4a180 LP |
168 | if (pipe->bru) { |
169 | struct vsp1_bru *bru = to_bru(&pipe->bru->subdev); | |
dba4a180 LP |
170 | |
171 | for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i) | |
172 | bru->inputs[i].rpf = NULL; | |
173 | } | |
174 | ||
ff7e97c9 LP |
175 | for (i = 0; i < pipe->num_inputs; ++i) { |
176 | pipe->inputs[i]->pipe = NULL; | |
96bfa6a5 | 177 | pipe->inputs[i] = NULL; |
ff7e97c9 LP |
178 | } |
179 | ||
180 | pipe->output->pipe = NULL; | |
181 | pipe->output = NULL; | |
96bfa6a5 | 182 | |
dba4a180 LP |
183 | INIT_LIST_HEAD(&pipe->entities); |
184 | pipe->state = VSP1_PIPELINE_STOPPED; | |
185 | pipe->buffers_ready = 0; | |
186 | pipe->num_inputs = 0; | |
dba4a180 LP |
187 | pipe->bru = NULL; |
188 | pipe->lif = NULL; | |
189 | pipe->uds = NULL; | |
190 | } | |
191 | ||
f294c2f7 LP |
192 | void vsp1_pipeline_init(struct vsp1_pipeline *pipe) |
193 | { | |
194 | mutex_init(&pipe->lock); | |
195 | spin_lock_init(&pipe->irqlock); | |
196 | init_waitqueue_head(&pipe->wq); | |
197 | ||
198 | INIT_LIST_HEAD(&pipe->entities); | |
199 | pipe->state = VSP1_PIPELINE_STOPPED; | |
200 | } | |
201 | ||
dba4a180 LP |
202 | void vsp1_pipeline_run(struct vsp1_pipeline *pipe) |
203 | { | |
204 | struct vsp1_device *vsp1 = pipe->output->entity.vsp1; | |
205 | ||
1517b039 TS |
206 | if (pipe->state == VSP1_PIPELINE_STOPPED) { |
207 | vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index), | |
208 | VI6_CMD_STRCMD); | |
209 | pipe->state = VSP1_PIPELINE_RUNNING; | |
210 | } | |
211 | ||
dba4a180 LP |
212 | pipe->buffers_ready = 0; |
213 | } | |
214 | ||
215 | bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe) | |
216 | { | |
217 | unsigned long flags; | |
218 | bool stopped; | |
219 | ||
220 | spin_lock_irqsave(&pipe->irqlock, flags); | |
221 | stopped = pipe->state == VSP1_PIPELINE_STOPPED; | |
222 | spin_unlock_irqrestore(&pipe->irqlock, flags); | |
223 | ||
224 | return stopped; | |
225 | } | |
226 | ||
227 | int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) | |
228 | { | |
229 | struct vsp1_entity *entity; | |
230 | unsigned long flags; | |
231 | int ret; | |
232 | ||
c2dd2513 | 233 | if (pipe->lif) { |
1517b039 TS |
234 | /* When using display lists in continuous frame mode the only |
235 | * way to stop the pipeline is to reset the hardware. | |
236 | */ | |
237 | ret = vsp1_reset_wpf(pipe->output->entity.vsp1, | |
238 | pipe->output->entity.index); | |
239 | if (ret == 0) { | |
240 | spin_lock_irqsave(&pipe->irqlock, flags); | |
241 | pipe->state = VSP1_PIPELINE_STOPPED; | |
242 | spin_unlock_irqrestore(&pipe->irqlock, flags); | |
243 | } | |
244 | } else { | |
245 | /* Otherwise just request a stop and wait. */ | |
246 | spin_lock_irqsave(&pipe->irqlock, flags); | |
247 | if (pipe->state == VSP1_PIPELINE_RUNNING) | |
248 | pipe->state = VSP1_PIPELINE_STOPPING; | |
249 | spin_unlock_irqrestore(&pipe->irqlock, flags); | |
250 | ||
251 | ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe), | |
252 | msecs_to_jiffies(500)); | |
253 | ret = ret == 0 ? -ETIMEDOUT : 0; | |
254 | } | |
dba4a180 LP |
255 | |
256 | list_for_each_entry(entity, &pipe->entities, list_pipe) { | |
257 | if (entity->route && entity->route->reg) | |
258 | vsp1_write(entity->vsp1, entity->route->reg, | |
259 | VI6_DPR_NODE_UNUSED); | |
dba4a180 LP |
260 | } |
261 | ||
7b905f05 LP |
262 | v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0); |
263 | ||
dba4a180 LP |
264 | return ret; |
265 | } | |
266 | ||
267 | bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe) | |
268 | { | |
269 | unsigned int mask; | |
270 | ||
271 | mask = ((1 << pipe->num_inputs) - 1) << 1; | |
272 | if (!pipe->lif) | |
273 | mask |= 1 << 0; | |
274 | ||
275 | return pipe->buffers_ready == mask; | |
276 | } | |
277 | ||
278 | void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe) | |
279 | { | |
dba4a180 LP |
280 | if (pipe == NULL) |
281 | return; | |
282 | ||
351bbf99 LP |
283 | vsp1_dlm_irq_frame_end(pipe->output->dlm); |
284 | ||
f9df34f8 LP |
285 | if (pipe->frame_end) |
286 | pipe->frame_end(pipe); | |
dba4a180 LP |
287 | } |
288 | ||
289 | /* | |
290 | * Propagate the alpha value through the pipeline. | |
291 | * | |
292 | * As the UDS has restricted scaling capabilities when the alpha component needs | |
293 | * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha | |
294 | * value. The UDS then outputs a fixed alpha value which needs to be programmed | |
295 | * from the input RPF alpha. | |
c9e645a5 LP |
296 | * |
297 | * This function can only be called from a subdev s_stream handler as it | |
298 | * requires a valid display list context. | |
dba4a180 LP |
299 | */ |
300 | void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe, | |
301 | struct vsp1_entity *input, | |
5e8dbbf3 | 302 | struct vsp1_dl_list *dl, |
dba4a180 LP |
303 | unsigned int alpha) |
304 | { | |
305 | struct vsp1_entity *entity; | |
306 | struct media_pad *pad; | |
307 | ||
308 | pad = media_entity_remote_pad(&input->pads[RWPF_PAD_SOURCE]); | |
309 | ||
310 | while (pad) { | |
311 | if (!is_media_entity_v4l2_subdev(pad->entity)) | |
312 | break; | |
313 | ||
314 | entity = to_vsp1_entity(media_entity_to_v4l2_subdev(pad->entity)); | |
315 | ||
316 | /* The BRU background color has a fixed alpha value set to 255, | |
317 | * the output alpha value is thus always equal to 255. | |
318 | */ | |
319 | if (entity->type == VSP1_ENTITY_BRU) | |
320 | alpha = 255; | |
321 | ||
322 | if (entity->type == VSP1_ENTITY_UDS) { | |
323 | struct vsp1_uds *uds = to_uds(&entity->subdev); | |
324 | ||
5e8dbbf3 | 325 | vsp1_uds_set_alpha(uds, dl, alpha); |
dba4a180 LP |
326 | break; |
327 | } | |
328 | ||
329 | pad = &entity->pads[entity->source_pad]; | |
330 | pad = media_entity_remote_pad(pad); | |
331 | } | |
332 | } | |
333 | ||
334 | void vsp1_pipelines_suspend(struct vsp1_device *vsp1) | |
335 | { | |
336 | unsigned long flags; | |
337 | unsigned int i; | |
338 | int ret; | |
339 | ||
340 | /* To avoid increasing the system suspend time needlessly, loop over the | |
341 | * pipelines twice, first to set them all to the stopping state, and | |
342 | * then to wait for the stop to complete. | |
343 | */ | |
5aa2eb3c | 344 | for (i = 0; i < vsp1->info->wpf_count; ++i) { |
dba4a180 LP |
345 | struct vsp1_rwpf *wpf = vsp1->wpf[i]; |
346 | struct vsp1_pipeline *pipe; | |
347 | ||
348 | if (wpf == NULL) | |
349 | continue; | |
350 | ||
ff7e97c9 | 351 | pipe = wpf->pipe; |
dba4a180 LP |
352 | if (pipe == NULL) |
353 | continue; | |
354 | ||
355 | spin_lock_irqsave(&pipe->irqlock, flags); | |
356 | if (pipe->state == VSP1_PIPELINE_RUNNING) | |
357 | pipe->state = VSP1_PIPELINE_STOPPING; | |
358 | spin_unlock_irqrestore(&pipe->irqlock, flags); | |
359 | } | |
360 | ||
5aa2eb3c | 361 | for (i = 0; i < vsp1->info->wpf_count; ++i) { |
dba4a180 LP |
362 | struct vsp1_rwpf *wpf = vsp1->wpf[i]; |
363 | struct vsp1_pipeline *pipe; | |
364 | ||
365 | if (wpf == NULL) | |
366 | continue; | |
367 | ||
ff7e97c9 | 368 | pipe = wpf->pipe; |
dba4a180 LP |
369 | if (pipe == NULL) |
370 | continue; | |
371 | ||
372 | ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe), | |
373 | msecs_to_jiffies(500)); | |
374 | if (ret == 0) | |
375 | dev_warn(vsp1->dev, "pipeline %u stop timeout\n", | |
376 | wpf->entity.index); | |
377 | } | |
378 | } | |
379 | ||
380 | void vsp1_pipelines_resume(struct vsp1_device *vsp1) | |
381 | { | |
382 | unsigned int i; | |
383 | ||
384 | /* Resume pipeline all running pipelines. */ | |
5aa2eb3c | 385 | for (i = 0; i < vsp1->info->wpf_count; ++i) { |
dba4a180 LP |
386 | struct vsp1_rwpf *wpf = vsp1->wpf[i]; |
387 | struct vsp1_pipeline *pipe; | |
388 | ||
389 | if (wpf == NULL) | |
390 | continue; | |
391 | ||
ff7e97c9 | 392 | pipe = wpf->pipe; |
dba4a180 LP |
393 | if (pipe == NULL) |
394 | continue; | |
395 | ||
396 | if (vsp1_pipeline_ready(pipe)) | |
397 | vsp1_pipeline_run(pipe); | |
398 | } | |
399 | } |