Commit | Line | Data |
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6d2f5c27 JW |
1 | /* |
2 | * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR | |
3 | * | |
4 | * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> | |
5 | * Copyright (C) 2009 Nuvoton PS Team | |
6 | * | |
7 | * Special thanks to Nuvoton for providing hardware, spec sheets and | |
8 | * sample code upon which portions of this driver are based. Indirect | |
9 | * thanks also to Maxim Levitsky, whose ene_ir driver this driver is | |
10 | * modeled after. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but | |
18 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
20 | * General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
25 | * USA | |
26 | */ | |
27 | ||
563cd5ce JP |
28 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
29 | ||
6d2f5c27 JW |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/pnp.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/sched.h> | |
36 | #include <linux/slab.h> | |
6bda9644 | 37 | #include <media/rc-core.h> |
6d2f5c27 JW |
38 | #include <linux/pci_ids.h> |
39 | ||
40 | #include "nuvoton-cir.h" | |
41 | ||
449c1fcd HK |
42 | static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt); |
43 | ||
b5cf725c HK |
44 | static const struct nvt_chip nvt_chips[] = { |
45 | { "w83667hg", NVT_W83667HG }, | |
46 | { "NCT6775F", NVT_6775F }, | |
47 | { "NCT6776F", NVT_6776F }, | |
d0b528d5 | 48 | { "NCT6779D", NVT_6779D }, |
b5cf725c HK |
49 | }; |
50 | ||
51 | static inline bool is_w83667hg(struct nvt_dev *nvt) | |
52 | { | |
53 | return nvt->chip_ver == NVT_W83667HG; | |
54 | } | |
55 | ||
6d2f5c27 JW |
56 | /* write val to config reg */ |
57 | static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) | |
58 | { | |
59 | outb(reg, nvt->cr_efir); | |
60 | outb(val, nvt->cr_efdr); | |
61 | } | |
62 | ||
63 | /* read val from config reg */ | |
64 | static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg) | |
65 | { | |
66 | outb(reg, nvt->cr_efir); | |
67 | return inb(nvt->cr_efdr); | |
68 | } | |
69 | ||
70 | /* update config register bit without changing other bits */ | |
71 | static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) | |
72 | { | |
73 | u8 tmp = nvt_cr_read(nvt, reg) | val; | |
74 | nvt_cr_write(nvt, tmp, reg); | |
75 | } | |
76 | ||
77 | /* clear config register bit without changing other bits */ | |
78 | static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) | |
79 | { | |
80 | u8 tmp = nvt_cr_read(nvt, reg) & ~val; | |
81 | nvt_cr_write(nvt, tmp, reg); | |
82 | } | |
83 | ||
84 | /* enter extended function mode */ | |
3def9ad6 | 85 | static inline int nvt_efm_enable(struct nvt_dev *nvt) |
6d2f5c27 | 86 | { |
3def9ad6 HK |
87 | if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME)) |
88 | return -EBUSY; | |
89 | ||
6d2f5c27 JW |
90 | /* Enabling Extended Function Mode explicitly requires writing 2x */ |
91 | outb(EFER_EFM_ENABLE, nvt->cr_efir); | |
92 | outb(EFER_EFM_ENABLE, nvt->cr_efir); | |
3def9ad6 HK |
93 | |
94 | return 0; | |
6d2f5c27 JW |
95 | } |
96 | ||
97 | /* exit extended function mode */ | |
98 | static inline void nvt_efm_disable(struct nvt_dev *nvt) | |
99 | { | |
100 | outb(EFER_EFM_DISABLE, nvt->cr_efir); | |
3def9ad6 HK |
101 | |
102 | release_region(nvt->cr_efir, 2); | |
6d2f5c27 JW |
103 | } |
104 | ||
105 | /* | |
106 | * When you want to address a specific logical device, write its logical | |
107 | * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing | |
108 | * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN. | |
109 | */ | |
110 | static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
111 | { | |
7a89836e | 112 | nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL); |
6d2f5c27 JW |
113 | } |
114 | ||
0890655c HK |
115 | /* select and enable logical device with setting EFM mode*/ |
116 | static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
117 | { | |
118 | nvt_efm_enable(nvt); | |
119 | nvt_select_logical_dev(nvt, ldev); | |
120 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
121 | nvt_efm_disable(nvt); | |
122 | } | |
123 | ||
a17ede9a HK |
124 | /* select and disable logical device with setting EFM mode*/ |
125 | static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
126 | { | |
127 | nvt_efm_enable(nvt); | |
128 | nvt_select_logical_dev(nvt, ldev); | |
129 | nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); | |
130 | nvt_efm_disable(nvt); | |
131 | } | |
132 | ||
6d2f5c27 JW |
133 | /* write val to cir config register */ |
134 | static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset) | |
135 | { | |
136 | outb(val, nvt->cir_addr + offset); | |
137 | } | |
138 | ||
139 | /* read val from cir config register */ | |
140 | static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset) | |
141 | { | |
142 | u8 val; | |
143 | ||
144 | val = inb(nvt->cir_addr + offset); | |
145 | ||
146 | return val; | |
147 | } | |
148 | ||
149 | /* write val to cir wake register */ | |
150 | static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt, | |
151 | u8 val, u8 offset) | |
152 | { | |
153 | outb(val, nvt->cir_wake_addr + offset); | |
154 | } | |
155 | ||
156 | /* read val from cir wake config register */ | |
157 | static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset) | |
158 | { | |
159 | u8 val; | |
160 | ||
161 | val = inb(nvt->cir_wake_addr + offset); | |
162 | ||
163 | return val; | |
164 | } | |
165 | ||
fb16aaf5 HK |
166 | /* don't override io address if one is set already */ |
167 | static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr) | |
168 | { | |
169 | unsigned long old_addr; | |
170 | ||
171 | old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8; | |
172 | old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO); | |
173 | ||
174 | if (old_addr) | |
175 | *ioaddr = old_addr; | |
176 | else { | |
177 | nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI); | |
178 | nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO); | |
179 | } | |
180 | } | |
181 | ||
02212001 HK |
182 | static ssize_t wakeup_data_show(struct device *dev, |
183 | struct device_attribute *attr, | |
184 | char *buf) | |
449c1fcd | 185 | { |
449c1fcd HK |
186 | struct rc_dev *rc_dev = to_rc_dev(dev); |
187 | struct nvt_dev *nvt = rc_dev->priv; | |
02212001 | 188 | int fifo_len, duration; |
449c1fcd | 189 | unsigned long flags; |
02212001 | 190 | ssize_t buf_len = 0; |
449c1fcd HK |
191 | int i; |
192 | ||
193 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
194 | ||
195 | fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); | |
02212001 | 196 | fifo_len = min(fifo_len, WAKEUP_MAX_SIZE); |
449c1fcd HK |
197 | |
198 | /* go to first element to be read */ | |
02212001 | 199 | while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) |
449c1fcd HK |
200 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); |
201 | ||
02212001 HK |
202 | for (i = 0; i < fifo_len; i++) { |
203 | duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); | |
204 | duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD; | |
205 | buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, | |
206 | "%d ", duration); | |
207 | } | |
208 | buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n"); | |
449c1fcd HK |
209 | |
210 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
211 | ||
02212001 | 212 | return buf_len; |
449c1fcd HK |
213 | } |
214 | ||
02212001 HK |
215 | static ssize_t wakeup_data_store(struct device *dev, |
216 | struct device_attribute *attr, | |
217 | const char *buf, size_t len) | |
449c1fcd | 218 | { |
449c1fcd HK |
219 | struct rc_dev *rc_dev = to_rc_dev(dev); |
220 | struct nvt_dev *nvt = rc_dev->priv; | |
221 | unsigned long flags; | |
02212001 HK |
222 | u8 tolerance, config, wake_buf[WAKEUP_MAX_SIZE]; |
223 | char **argv; | |
224 | int i, count; | |
225 | unsigned int val; | |
226 | ssize_t ret; | |
227 | ||
228 | argv = argv_split(GFP_KERNEL, buf, &count); | |
229 | if (!argv) | |
230 | return -ENOMEM; | |
231 | if (!count || count > WAKEUP_MAX_SIZE) { | |
232 | ret = -EINVAL; | |
233 | goto out; | |
234 | } | |
449c1fcd | 235 | |
02212001 HK |
236 | for (i = 0; i < count; i++) { |
237 | ret = kstrtouint(argv[i], 10, &val); | |
238 | if (ret) | |
239 | goto out; | |
240 | val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD); | |
241 | if (!val || val > 0x7f) { | |
242 | ret = -EINVAL; | |
243 | goto out; | |
244 | } | |
245 | wake_buf[i] = val; | |
246 | /* sequence must start with a pulse */ | |
247 | if (i % 2 == 0) | |
248 | wake_buf[i] |= BUF_PULSE_BIT; | |
249 | } | |
449c1fcd HK |
250 | |
251 | /* hardcode the tolerance to 10% */ | |
252 | tolerance = DIV_ROUND_UP(count, 10); | |
253 | ||
254 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
255 | ||
256 | nvt_clear_cir_wake_fifo(nvt); | |
257 | nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP); | |
258 | nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL); | |
259 | ||
260 | config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON); | |
261 | ||
262 | /* enable writes to wake fifo */ | |
263 | nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1, | |
264 | CIR_WAKE_IRCON); | |
265 | ||
266 | for (i = 0; i < count; i++) | |
02212001 | 267 | nvt_cir_wake_reg_write(nvt, wake_buf[i], CIR_WAKE_WR_FIFO_DATA); |
449c1fcd HK |
268 | |
269 | nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON); | |
270 | ||
271 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
272 | ||
02212001 HK |
273 | ret = len; |
274 | out: | |
275 | argv_free(argv); | |
276 | return ret; | |
449c1fcd | 277 | } |
02212001 | 278 | static DEVICE_ATTR_RW(wakeup_data); |
449c1fcd | 279 | |
6d2f5c27 JW |
280 | /* dump current cir register contents */ |
281 | static void cir_dump_regs(struct nvt_dev *nvt) | |
282 | { | |
283 | nvt_efm_enable(nvt); | |
284 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
285 | ||
563cd5ce JP |
286 | pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME); |
287 | pr_info(" * CR CIR ACTIVE : 0x%x\n", | |
288 | nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); | |
289 | pr_info(" * CR CIR BASE ADDR: 0x%x\n", | |
290 | (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | | |
6d2f5c27 | 291 | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); |
563cd5ce JP |
292 | pr_info(" * CR CIR IRQ NUM: 0x%x\n", |
293 | nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); | |
6d2f5c27 JW |
294 | |
295 | nvt_efm_disable(nvt); | |
296 | ||
563cd5ce JP |
297 | pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME); |
298 | pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); | |
299 | pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); | |
300 | pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); | |
301 | pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); | |
302 | pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); | |
303 | pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); | |
304 | pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); | |
305 | pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); | |
306 | pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); | |
307 | pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); | |
308 | pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); | |
309 | pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); | |
310 | pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); | |
311 | pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); | |
312 | pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); | |
313 | pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); | |
6d2f5c27 JW |
314 | } |
315 | ||
316 | /* dump current cir wake register contents */ | |
317 | static void cir_wake_dump_regs(struct nvt_dev *nvt) | |
318 | { | |
319 | u8 i, fifo_len; | |
320 | ||
321 | nvt_efm_enable(nvt); | |
322 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
323 | ||
563cd5ce JP |
324 | pr_info("%s: Dump CIR WAKE logical device registers:\n", |
325 | NVT_DRIVER_NAME); | |
326 | pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n", | |
327 | nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); | |
328 | pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n", | |
329 | (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | | |
4e6e29ad | 330 | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); |
563cd5ce JP |
331 | pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n", |
332 | nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); | |
6d2f5c27 JW |
333 | |
334 | nvt_efm_disable(nvt); | |
335 | ||
563cd5ce JP |
336 | pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME); |
337 | pr_info(" * IRCON: 0x%x\n", | |
338 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); | |
339 | pr_info(" * IRSTS: 0x%x\n", | |
340 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); | |
341 | pr_info(" * IREN: 0x%x\n", | |
342 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); | |
343 | pr_info(" * FIFO CMP DEEP: 0x%x\n", | |
344 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); | |
345 | pr_info(" * FIFO CMP TOL: 0x%x\n", | |
346 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); | |
347 | pr_info(" * FIFO COUNT: 0x%x\n", | |
348 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); | |
349 | pr_info(" * SLCH: 0x%x\n", | |
350 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); | |
351 | pr_info(" * SLCL: 0x%x\n", | |
352 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); | |
353 | pr_info(" * FIFOCON: 0x%x\n", | |
354 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); | |
355 | pr_info(" * SRXFSTS: 0x%x\n", | |
356 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); | |
357 | pr_info(" * SAMPLE RX FIFO: 0x%x\n", | |
358 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); | |
359 | pr_info(" * WR FIFO DATA: 0x%x\n", | |
360 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); | |
361 | pr_info(" * RD FIFO ONLY: 0x%x\n", | |
362 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); | |
363 | pr_info(" * RD FIFO ONLY IDX: 0x%x\n", | |
364 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); | |
365 | pr_info(" * FIFO IGNORE: 0x%x\n", | |
366 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); | |
367 | pr_info(" * IRFSM: 0x%x\n", | |
368 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); | |
6d2f5c27 JW |
369 | |
370 | fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); | |
563cd5ce JP |
371 | pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len); |
372 | pr_info("* Contents ="); | |
6d2f5c27 | 373 | for (i = 0; i < fifo_len; i++) |
563cd5ce JP |
374 | pr_cont(" %02x", |
375 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); | |
376 | pr_cont("\n"); | |
6d2f5c27 JW |
377 | } |
378 | ||
b5cf725c HK |
379 | static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id) |
380 | { | |
381 | int i; | |
382 | ||
383 | for (i = 0; i < ARRAY_SIZE(nvt_chips); i++) | |
384 | if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) { | |
385 | nvt->chip_ver = nvt_chips[i].chip_ver; | |
386 | return nvt_chips[i].name; | |
387 | } | |
388 | ||
389 | return NULL; | |
390 | } | |
391 | ||
392 | ||
6d2f5c27 | 393 | /* detect hardware features */ |
3f1321cb | 394 | static int nvt_hw_detect(struct nvt_dev *nvt) |
6d2f5c27 | 395 | { |
b5cf725c HK |
396 | const char *chip_name; |
397 | int chip_id; | |
6d2f5c27 JW |
398 | |
399 | nvt_efm_enable(nvt); | |
400 | ||
401 | /* Check if we're wired for the alternate EFER setup */ | |
b5cf725c HK |
402 | nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); |
403 | if (nvt->chip_major == 0xff) { | |
6d2f5c27 JW |
404 | nvt->cr_efir = CR_EFIR2; |
405 | nvt->cr_efdr = CR_EFDR2; | |
406 | nvt_efm_enable(nvt); | |
b5cf725c | 407 | nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); |
6d2f5c27 | 408 | } |
b5cf725c HK |
409 | nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO); |
410 | ||
3f1321cb HK |
411 | nvt_efm_disable(nvt); |
412 | ||
b5cf725c | 413 | chip_id = nvt->chip_major << 8 | nvt->chip_minor; |
3f1321cb HK |
414 | if (chip_id == NVT_INVALID) { |
415 | dev_err(&nvt->pdev->dev, | |
416 | "No device found on either EFM port\n"); | |
417 | return -ENODEV; | |
418 | } | |
419 | ||
b5cf725c | 420 | chip_name = nvt_find_chip(nvt, chip_id); |
6d2f5c27 | 421 | |
362d3a3a | 422 | /* warn, but still let the driver load, if we don't know this chip */ |
b5cf725c | 423 | if (!chip_name) |
211477fe HK |
424 | dev_warn(&nvt->pdev->dev, |
425 | "unknown chip, id: 0x%02x 0x%02x, it may not work...", | |
426 | nvt->chip_major, nvt->chip_minor); | |
362d3a3a | 427 | else |
af082334 HK |
428 | dev_info(&nvt->pdev->dev, |
429 | "found %s or compatible: chip id: 0x%02x 0x%02x", | |
430 | chip_name, nvt->chip_major, nvt->chip_minor); | |
362d3a3a | 431 | |
3f1321cb | 432 | return 0; |
6d2f5c27 JW |
433 | } |
434 | ||
435 | static void nvt_cir_ldev_init(struct nvt_dev *nvt) | |
436 | { | |
39381d4f JW |
437 | u8 val, psreg, psmask, psval; |
438 | ||
b5cf725c | 439 | if (is_w83667hg(nvt)) { |
39381d4f JW |
440 | psreg = CR_MULTIFUNC_PIN_SEL; |
441 | psmask = MULTIFUNC_PIN_SEL_MASK; | |
442 | psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB; | |
443 | } else { | |
444 | psreg = CR_OUTPUT_PIN_SEL; | |
445 | psmask = OUTPUT_PIN_SEL_MASK; | |
446 | psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB; | |
447 | } | |
6d2f5c27 | 448 | |
39381d4f JW |
449 | /* output pin selection: enable CIR, with WB sensor enabled */ |
450 | val = nvt_cr_read(nvt, psreg); | |
451 | val &= psmask; | |
452 | val |= psval; | |
453 | nvt_cr_write(nvt, val, psreg); | |
6d2f5c27 | 454 | |
ccca00d6 | 455 | /* Select CIR logical device */ |
6d2f5c27 | 456 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); |
6d2f5c27 | 457 | |
fb16aaf5 | 458 | nvt_set_ioaddr(nvt, &nvt->cir_addr); |
6d2f5c27 JW |
459 | |
460 | nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC); | |
461 | ||
462 | nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d", | |
463 | nvt->cir_addr, nvt->cir_irq); | |
464 | } | |
465 | ||
466 | static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt) | |
467 | { | |
ccca00d6 | 468 | /* Select ACPI logical device and anable it */ |
6d2f5c27 JW |
469 | nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); |
470 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
471 | ||
472 | /* Enable CIR Wake via PSOUT# (Pin60) */ | |
473 | nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); | |
474 | ||
6d2f5c27 JW |
475 | /* enable pme interrupt of cir wakeup event */ |
476 | nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); | |
477 | ||
ccca00d6 | 478 | /* Select CIR Wake logical device */ |
6d2f5c27 | 479 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); |
6d2f5c27 | 480 | |
fb16aaf5 | 481 | nvt_set_ioaddr(nvt, &nvt->cir_wake_addr); |
6d2f5c27 | 482 | |
cb48b369 HK |
483 | nvt_dbg("CIR Wake initialized, base io port address: 0x%lx", |
484 | nvt->cir_wake_addr); | |
6d2f5c27 JW |
485 | } |
486 | ||
487 | /* clear out the hardware's cir rx fifo */ | |
488 | static void nvt_clear_cir_fifo(struct nvt_dev *nvt) | |
489 | { | |
490 | u8 val; | |
491 | ||
492 | val = nvt_cir_reg_read(nvt, CIR_FIFOCON); | |
493 | nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); | |
494 | } | |
495 | ||
496 | /* clear out the hardware's cir wake rx fifo */ | |
497 | static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt) | |
498 | { | |
e1a7d981 HK |
499 | u8 val, config; |
500 | ||
501 | config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON); | |
502 | ||
503 | /* clearing wake fifo works in learning mode only */ | |
504 | nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0, | |
505 | CIR_WAKE_IRCON); | |
6d2f5c27 JW |
506 | |
507 | val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON); | |
508 | nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR, | |
509 | CIR_WAKE_FIFOCON); | |
e1a7d981 HK |
510 | |
511 | nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON); | |
6d2f5c27 JW |
512 | } |
513 | ||
514 | /* clear out the hardware's cir tx fifo */ | |
515 | static void nvt_clear_tx_fifo(struct nvt_dev *nvt) | |
516 | { | |
517 | u8 val; | |
518 | ||
519 | val = nvt_cir_reg_read(nvt, CIR_FIFOCON); | |
520 | nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON); | |
521 | } | |
522 | ||
fbdc781c JW |
523 | /* enable RX Trigger Level Reach and Packet End interrupts */ |
524 | static void nvt_set_cir_iren(struct nvt_dev *nvt) | |
525 | { | |
526 | u8 iren; | |
527 | ||
398d9da8 | 528 | iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO; |
fbdc781c JW |
529 | nvt_cir_reg_write(nvt, iren, CIR_IREN); |
530 | } | |
531 | ||
6d2f5c27 JW |
532 | static void nvt_cir_regs_init(struct nvt_dev *nvt) |
533 | { | |
534 | /* set sample limit count (PE interrupt raised when reached) */ | |
535 | nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH); | |
536 | nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL); | |
537 | ||
538 | /* set fifo irq trigger levels */ | |
539 | nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV | | |
540 | CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON); | |
541 | ||
542 | /* | |
543 | * Enable TX and RX, specify carrier on = low, off = high, and set | |
544 | * sample period (currently 50us) | |
545 | */ | |
4e6e29ad JW |
546 | nvt_cir_reg_write(nvt, |
547 | CIR_IRCON_TXEN | CIR_IRCON_RXEN | | |
548 | CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, | |
549 | CIR_IRCON); | |
6d2f5c27 JW |
550 | |
551 | /* clear hardware rx and tx fifos */ | |
552 | nvt_clear_cir_fifo(nvt); | |
553 | nvt_clear_tx_fifo(nvt); | |
554 | ||
555 | /* clear any and all stray interrupts */ | |
556 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
557 | ||
fbdc781c JW |
558 | /* and finally, enable interrupts */ |
559 | nvt_set_cir_iren(nvt); | |
ccca00d6 HK |
560 | |
561 | /* enable the CIR logical device */ | |
562 | nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR); | |
6d2f5c27 JW |
563 | } |
564 | ||
565 | static void nvt_cir_wake_regs_init(struct nvt_dev *nvt) | |
566 | { | |
6d2f5c27 | 567 | /* |
594ccee6 HK |
568 | * Disable RX, set specific carrier on = low, off = high, |
569 | * and sample period (currently 50us) | |
6d2f5c27 | 570 | */ |
594ccee6 | 571 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | |
6d2f5c27 JW |
572 | CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | |
573 | CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, | |
574 | CIR_WAKE_IRCON); | |
575 | ||
6d2f5c27 JW |
576 | /* clear any and all stray interrupts */ |
577 | nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); | |
ccca00d6 HK |
578 | |
579 | /* enable the CIR WAKE logical device */ | |
580 | nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
6d2f5c27 JW |
581 | } |
582 | ||
583 | static void nvt_enable_wake(struct nvt_dev *nvt) | |
584 | { | |
b883af30 HK |
585 | unsigned long flags; |
586 | ||
6d2f5c27 JW |
587 | nvt_efm_enable(nvt); |
588 | ||
589 | nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); | |
590 | nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); | |
6d2f5c27 JW |
591 | nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); |
592 | ||
593 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
594 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
595 | ||
596 | nvt_efm_disable(nvt); | |
597 | ||
b883af30 HK |
598 | spin_lock_irqsave(&nvt->nvt_lock, flags); |
599 | ||
6d2f5c27 JW |
600 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | |
601 | CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | | |
4e6e29ad JW |
602 | CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, |
603 | CIR_WAKE_IRCON); | |
6d2f5c27 JW |
604 | nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); |
605 | nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); | |
b883af30 HK |
606 | |
607 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
6d2f5c27 JW |
608 | } |
609 | ||
230dc94a | 610 | #if 0 /* Currently unused */ |
6d2f5c27 JW |
611 | /* rx carrier detect only works in learning mode, must be called w/nvt_lock */ |
612 | static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt) | |
613 | { | |
614 | u32 count, carrier, duration = 0; | |
615 | int i; | |
616 | ||
617 | count = nvt_cir_reg_read(nvt, CIR_FCCL) | | |
618 | nvt_cir_reg_read(nvt, CIR_FCCH) << 8; | |
619 | ||
620 | for (i = 0; i < nvt->pkts; i++) { | |
621 | if (nvt->buf[i] & BUF_PULSE_BIT) | |
622 | duration += nvt->buf[i] & BUF_LEN_MASK; | |
623 | } | |
624 | ||
625 | duration *= SAMPLE_PERIOD; | |
626 | ||
627 | if (!count || !duration) { | |
211477fe HK |
628 | dev_notice(&nvt->pdev->dev, |
629 | "Unable to determine carrier! (c:%u, d:%u)", | |
630 | count, duration); | |
6d2f5c27 JW |
631 | return 0; |
632 | } | |
633 | ||
b4608fae | 634 | carrier = MS_TO_NS(count) / duration; |
6d2f5c27 JW |
635 | |
636 | if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER)) | |
637 | nvt_dbg("WTF? Carrier frequency out of range!"); | |
638 | ||
639 | nvt_dbg("Carrier frequency: %u (count %u, duration %u)", | |
640 | carrier, count, duration); | |
641 | ||
642 | return carrier; | |
643 | } | |
230dc94a | 644 | #endif |
6d2f5c27 JW |
645 | /* |
646 | * set carrier frequency | |
647 | * | |
648 | * set carrier on 2 registers: CP & CC | |
649 | * always set CP as 0x81 | |
650 | * set CC by SPEC, CC = 3MHz/carrier - 1 | |
651 | */ | |
d8b4b582 | 652 | static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier) |
6d2f5c27 | 653 | { |
d8b4b582 | 654 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
655 | u16 val; |
656 | ||
48cafec9 DC |
657 | if (carrier == 0) |
658 | return -EINVAL; | |
659 | ||
6d2f5c27 JW |
660 | nvt_cir_reg_write(nvt, 1, CIR_CP); |
661 | val = 3000000 / (carrier) - 1; | |
662 | nvt_cir_reg_write(nvt, val & 0xff, CIR_CC); | |
663 | ||
664 | nvt_dbg("cp: 0x%x cc: 0x%x\n", | |
665 | nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC)); | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
670 | /* | |
671 | * nvt_tx_ir | |
672 | * | |
673 | * 1) clean TX fifo first (handled by AP) | |
674 | * 2) copy data from user space | |
675 | * 3) disable RX interrupts, enable TX interrupts: TTR & TFU | |
676 | * 4) send 9 packets to TX FIFO to open TTR | |
677 | * in interrupt_handler: | |
678 | * 5) send all data out | |
679 | * go back to write(): | |
680 | * 6) disable TX interrupts, re-enable RX interupts | |
681 | * | |
682 | * The key problem of this function is user space data may larger than | |
683 | * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to | |
684 | * buf, and keep current copied data buf num in cur_buf_num. But driver's buf | |
685 | * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to | |
686 | * set TXFCONT as 0xff, until buf_count less than 0xff. | |
687 | */ | |
5588dc2b | 688 | static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n) |
6d2f5c27 | 689 | { |
d8b4b582 | 690 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 | 691 | unsigned long flags; |
6d2f5c27 JW |
692 | unsigned int i; |
693 | u8 iren; | |
694 | int ret; | |
695 | ||
696 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
697 | ||
5588dc2b DH |
698 | ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n); |
699 | nvt->tx.buf_count = (ret * sizeof(unsigned)); | |
6d2f5c27 JW |
700 | |
701 | memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count); | |
702 | ||
703 | nvt->tx.cur_buf_num = 0; | |
704 | ||
705 | /* save currently enabled interrupts */ | |
706 | iren = nvt_cir_reg_read(nvt, CIR_IREN); | |
707 | ||
708 | /* now disable all interrupts, save TFU & TTR */ | |
709 | nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN); | |
710 | ||
711 | nvt->tx.tx_state = ST_TX_REPLY; | |
712 | ||
713 | nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 | | |
714 | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); | |
715 | ||
716 | /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */ | |
717 | for (i = 0; i < 9; i++) | |
718 | nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO); | |
719 | ||
720 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
721 | ||
722 | wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST); | |
723 | ||
724 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
725 | nvt->tx.tx_state = ST_TX_NONE; | |
726 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
727 | ||
728 | /* restore enabled interrupts to prior state */ | |
729 | nvt_cir_reg_write(nvt, iren, CIR_IREN); | |
730 | ||
731 | return ret; | |
732 | } | |
733 | ||
734 | /* dump contents of the last rx buffer we got from the hw rx fifo */ | |
735 | static void nvt_dump_rx_buf(struct nvt_dev *nvt) | |
736 | { | |
737 | int i; | |
738 | ||
4e6e29ad | 739 | printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts); |
6d2f5c27 | 740 | for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++) |
4e6e29ad JW |
741 | printk(KERN_CONT "0x%02x ", nvt->buf[i]); |
742 | printk(KERN_CONT "\n"); | |
6d2f5c27 JW |
743 | } |
744 | ||
745 | /* | |
746 | * Process raw data in rx driver buffer, store it in raw IR event kfifo, | |
747 | * trigger decode when appropriate. | |
748 | * | |
749 | * We get IR data samples one byte at a time. If the msb is set, its a pulse, | |
750 | * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD | |
751 | * (default 50us) intervals for that pulse/space. A discrete signal is | |
752 | * followed by a series of 0x7f packets, then either 0x7<something> or 0x80 | |
753 | * to signal more IR coming (repeats) or end of IR, respectively. We store | |
754 | * sample data in the raw event kfifo until we see 0x7<something> (except f) | |
755 | * or 0x80, at which time, we trigger a decode operation. | |
756 | */ | |
757 | static void nvt_process_rx_ir_data(struct nvt_dev *nvt) | |
758 | { | |
4651918a | 759 | DEFINE_IR_RAW_EVENT(rawir); |
6d2f5c27 JW |
760 | u8 sample; |
761 | int i; | |
762 | ||
763 | nvt_dbg_verbose("%s firing", __func__); | |
764 | ||
765 | if (debug) | |
766 | nvt_dump_rx_buf(nvt); | |
767 | ||
de4ed0c1 | 768 | nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts); |
6d2f5c27 | 769 | |
b7582815 JW |
770 | init_ir_raw_event(&rawir); |
771 | ||
de4ed0c1 | 772 | for (i = 0; i < nvt->pkts; i++) { |
6d2f5c27 JW |
773 | sample = nvt->buf[i]; |
774 | ||
775 | rawir.pulse = ((sample & BUF_PULSE_BIT) != 0); | |
b4608fae JW |
776 | rawir.duration = US_TO_NS((sample & BUF_LEN_MASK) |
777 | * SAMPLE_PERIOD); | |
6d2f5c27 | 778 | |
de4ed0c1 JW |
779 | nvt_dbg("Storing %s with duration %d", |
780 | rawir.pulse ? "pulse" : "space", rawir.duration); | |
4651918a | 781 | |
de4ed0c1 | 782 | ir_raw_event_store_with_filter(nvt->rdev, &rawir); |
6d2f5c27 JW |
783 | |
784 | /* | |
785 | * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE | |
786 | * indicates end of IR signal, but new data incoming. In both | |
787 | * cases, it means we're ready to call ir_raw_event_handle | |
788 | */ | |
de4ed0c1 | 789 | if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) { |
b7582815 | 790 | nvt_dbg("Calling ir_raw_event_handle (signal end)\n"); |
6d2f5c27 | 791 | ir_raw_event_handle(nvt->rdev); |
b7582815 | 792 | } |
6d2f5c27 JW |
793 | } |
794 | ||
de4ed0c1 JW |
795 | nvt->pkts = 0; |
796 | ||
b7582815 JW |
797 | nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n"); |
798 | ir_raw_event_handle(nvt->rdev); | |
799 | ||
6d2f5c27 JW |
800 | nvt_dbg_verbose("%s done", __func__); |
801 | } | |
802 | ||
fbdc781c JW |
803 | static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt) |
804 | { | |
211477fe | 805 | dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!"); |
fbdc781c JW |
806 | |
807 | nvt->pkts = 0; | |
808 | nvt_clear_cir_fifo(nvt); | |
809 | ir_raw_event_reset(nvt->rdev); | |
810 | } | |
811 | ||
6d2f5c27 JW |
812 | /* copy data from hardware rx fifo into driver buffer */ |
813 | static void nvt_get_rx_ir_data(struct nvt_dev *nvt) | |
814 | { | |
6d2f5c27 JW |
815 | u8 fifocount, val; |
816 | unsigned int b_idx; | |
817 | int i; | |
818 | ||
819 | /* Get count of how many bytes to read from RX FIFO */ | |
820 | fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT); | |
821 | /* if we get 0xff, probably means the logical dev is disabled */ | |
822 | if (fifocount == 0xff) | |
823 | return; | |
6d2f5c27 JW |
824 | |
825 | nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount); | |
826 | ||
6d2f5c27 JW |
827 | b_idx = nvt->pkts; |
828 | ||
829 | /* This should never happen, but lets check anyway... */ | |
830 | if (b_idx + fifocount > RX_BUF_LEN) { | |
831 | nvt_process_rx_ir_data(nvt); | |
832 | b_idx = 0; | |
833 | } | |
834 | ||
835 | /* Read fifocount bytes from CIR Sample RX FIFO register */ | |
836 | for (i = 0; i < fifocount; i++) { | |
837 | val = nvt_cir_reg_read(nvt, CIR_SRXFIFO); | |
838 | nvt->buf[b_idx + i] = val; | |
839 | } | |
840 | ||
841 | nvt->pkts += fifocount; | |
842 | nvt_dbg("%s: pkts now %d", __func__, nvt->pkts); | |
843 | ||
844 | nvt_process_rx_ir_data(nvt); | |
6d2f5c27 JW |
845 | } |
846 | ||
847 | static void nvt_cir_log_irqs(u8 status, u8 iren) | |
848 | { | |
068fb7dd | 849 | nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s", |
6d2f5c27 JW |
850 | status, iren, |
851 | status & CIR_IRSTS_RDR ? " RDR" : "", | |
852 | status & CIR_IRSTS_RTR ? " RTR" : "", | |
853 | status & CIR_IRSTS_PE ? " PE" : "", | |
854 | status & CIR_IRSTS_RFO ? " RFO" : "", | |
855 | status & CIR_IRSTS_TE ? " TE" : "", | |
856 | status & CIR_IRSTS_TTR ? " TTR" : "", | |
857 | status & CIR_IRSTS_TFU ? " TFU" : "", | |
858 | status & CIR_IRSTS_GH ? " GH" : "", | |
859 | status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE | | |
860 | CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR | | |
861 | CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : ""); | |
862 | } | |
863 | ||
864 | static bool nvt_cir_tx_inactive(struct nvt_dev *nvt) | |
865 | { | |
866 | unsigned long flags; | |
6d2f5c27 JW |
867 | u8 tx_state; |
868 | ||
869 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
870 | tx_state = nvt->tx.tx_state; | |
871 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
872 | ||
1feac493 | 873 | return tx_state == ST_TX_NONE; |
6d2f5c27 JW |
874 | } |
875 | ||
876 | /* interrupt service routine for incoming and outgoing CIR data */ | |
877 | static irqreturn_t nvt_cir_isr(int irq, void *data) | |
878 | { | |
879 | struct nvt_dev *nvt = data; | |
880 | u8 status, iren, cur_state; | |
881 | unsigned long flags; | |
882 | ||
883 | nvt_dbg_verbose("%s firing", __func__); | |
884 | ||
e60c1e87 HK |
885 | spin_lock_irqsave(&nvt->nvt_lock, flags); |
886 | ||
6d2f5c27 JW |
887 | /* |
888 | * Get IR Status register contents. Write 1 to ack/clear | |
889 | * | |
890 | * bit: reg name - description | |
891 | * 7: CIR_IRSTS_RDR - RX Data Ready | |
892 | * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach | |
893 | * 5: CIR_IRSTS_PE - Packet End | |
894 | * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set) | |
895 | * 3: CIR_IRSTS_TE - TX FIFO Empty | |
896 | * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach | |
897 | * 1: CIR_IRSTS_TFU - TX FIFO Underrun | |
898 | * 0: CIR_IRSTS_GH - Min Length Detected | |
899 | */ | |
900 | status = nvt_cir_reg_read(nvt, CIR_IRSTS); | |
d42fd297 HK |
901 | iren = nvt_cir_reg_read(nvt, CIR_IREN); |
902 | ||
903 | /* IRQ may be shared with CIR WAKE, therefore check for each | |
904 | * status bit whether the related interrupt source is enabled | |
905 | */ | |
906 | if (!(status & iren)) { | |
e60c1e87 | 907 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
6d2f5c27 | 908 | nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__); |
2bbf9e06 | 909 | return IRQ_NONE; |
6d2f5c27 JW |
910 | } |
911 | ||
912 | /* ack/clear all irq flags we've got */ | |
913 | nvt_cir_reg_write(nvt, status, CIR_IRSTS); | |
914 | nvt_cir_reg_write(nvt, 0, CIR_IRSTS); | |
915 | ||
068fb7dd | 916 | nvt_cir_log_irqs(status, iren); |
6d2f5c27 | 917 | |
398d9da8 HK |
918 | if (status & CIR_IRSTS_RFO) |
919 | nvt_handle_rx_fifo_overrun(nvt); | |
920 | ||
6d2f5c27 JW |
921 | if (status & CIR_IRSTS_RTR) { |
922 | /* FIXME: add code for study/learn mode */ | |
923 | /* We only do rx if not tx'ing */ | |
924 | if (nvt_cir_tx_inactive(nvt)) | |
925 | nvt_get_rx_ir_data(nvt); | |
926 | } | |
927 | ||
928 | if (status & CIR_IRSTS_PE) { | |
929 | if (nvt_cir_tx_inactive(nvt)) | |
930 | nvt_get_rx_ir_data(nvt); | |
931 | ||
6d2f5c27 JW |
932 | cur_state = nvt->study_state; |
933 | ||
6d2f5c27 JW |
934 | if (cur_state == ST_STUDY_NONE) |
935 | nvt_clear_cir_fifo(nvt); | |
936 | } | |
937 | ||
e60c1e87 HK |
938 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
939 | ||
6d2f5c27 JW |
940 | if (status & CIR_IRSTS_TE) |
941 | nvt_clear_tx_fifo(nvt); | |
942 | ||
943 | if (status & CIR_IRSTS_TTR) { | |
944 | unsigned int pos, count; | |
945 | u8 tmp; | |
946 | ||
947 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
948 | ||
949 | pos = nvt->tx.cur_buf_num; | |
950 | count = nvt->tx.buf_count; | |
951 | ||
952 | /* Write data into the hardware tx fifo while pos < count */ | |
953 | if (pos < count) { | |
954 | nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO); | |
955 | nvt->tx.cur_buf_num++; | |
956 | /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */ | |
957 | } else { | |
958 | tmp = nvt_cir_reg_read(nvt, CIR_IREN); | |
959 | nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN); | |
960 | } | |
961 | ||
962 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
963 | ||
964 | } | |
965 | ||
966 | if (status & CIR_IRSTS_TFU) { | |
967 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
968 | if (nvt->tx.tx_state == ST_TX_REPLY) { | |
969 | nvt->tx.tx_state = ST_TX_REQUEST; | |
970 | wake_up(&nvt->tx.queue); | |
971 | } | |
972 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
973 | } | |
974 | ||
975 | nvt_dbg_verbose("%s done", __func__); | |
2bbf9e06 | 976 | return IRQ_HANDLED; |
6d2f5c27 JW |
977 | } |
978 | ||
6d2f5c27 JW |
979 | static void nvt_disable_cir(struct nvt_dev *nvt) |
980 | { | |
137aa361 HK |
981 | unsigned long flags; |
982 | ||
983 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
984 | ||
6d2f5c27 JW |
985 | /* disable CIR interrupts */ |
986 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
987 | ||
988 | /* clear any and all pending interrupts */ | |
989 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
990 | ||
991 | /* clear all function enable flags */ | |
992 | nvt_cir_reg_write(nvt, 0, CIR_IRCON); | |
993 | ||
994 | /* clear hardware rx and tx fifos */ | |
995 | nvt_clear_cir_fifo(nvt); | |
996 | nvt_clear_tx_fifo(nvt); | |
997 | ||
137aa361 HK |
998 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
999 | ||
6d2f5c27 | 1000 | /* disable the CIR logical device */ |
a17ede9a | 1001 | nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR); |
6d2f5c27 JW |
1002 | } |
1003 | ||
d8b4b582 | 1004 | static int nvt_open(struct rc_dev *dev) |
6d2f5c27 | 1005 | { |
d8b4b582 | 1006 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
1007 | unsigned long flags; |
1008 | ||
1009 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
842096fc HK |
1010 | |
1011 | /* set function enable flags */ | |
1012 | nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | | |
1013 | CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, | |
1014 | CIR_IRCON); | |
1015 | ||
1016 | /* clear all pending interrupts */ | |
1017 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
1018 | ||
1019 | /* enable interrupts */ | |
1020 | nvt_set_cir_iren(nvt); | |
1021 | ||
6d2f5c27 JW |
1022 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
1023 | ||
842096fc HK |
1024 | /* enable the CIR logical device */ |
1025 | nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR); | |
1026 | ||
6d2f5c27 JW |
1027 | return 0; |
1028 | } | |
1029 | ||
d8b4b582 | 1030 | static void nvt_close(struct rc_dev *dev) |
6d2f5c27 | 1031 | { |
d8b4b582 | 1032 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 | 1033 | |
6d2f5c27 | 1034 | nvt_disable_cir(nvt); |
6d2f5c27 JW |
1035 | } |
1036 | ||
1037 | /* Allocate memory, probe hardware, and initialize everything */ | |
1038 | static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) | |
1039 | { | |
d8b4b582 DH |
1040 | struct nvt_dev *nvt; |
1041 | struct rc_dev *rdev; | |
6d2f5c27 JW |
1042 | int ret = -ENOMEM; |
1043 | ||
099256e5 | 1044 | nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL); |
6d2f5c27 JW |
1045 | if (!nvt) |
1046 | return ret; | |
1047 | ||
6d2f5c27 | 1048 | /* input device for IR remote (and tx) */ |
d8b4b582 | 1049 | rdev = rc_allocate_device(); |
6d2f5c27 | 1050 | if (!rdev) |
70ef6991 | 1051 | goto exit_free_dev_rdev; |
6d2f5c27 JW |
1052 | |
1053 | ret = -ENODEV; | |
c3c2077d AS |
1054 | /* activate pnp device */ |
1055 | if (pnp_activate_dev(pdev) < 0) { | |
1056 | dev_err(&pdev->dev, "Could not activate PNP device!\n"); | |
1057 | goto exit_free_dev_rdev; | |
1058 | } | |
1059 | ||
6d2f5c27 JW |
1060 | /* validate pnp resources */ |
1061 | if (!pnp_port_valid(pdev, 0) || | |
1062 | pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) { | |
1063 | dev_err(&pdev->dev, "IR PNP Port not valid!\n"); | |
70ef6991 | 1064 | goto exit_free_dev_rdev; |
6d2f5c27 JW |
1065 | } |
1066 | ||
1067 | if (!pnp_irq_valid(pdev, 0)) { | |
1068 | dev_err(&pdev->dev, "PNP IRQ not valid!\n"); | |
70ef6991 | 1069 | goto exit_free_dev_rdev; |
6d2f5c27 JW |
1070 | } |
1071 | ||
1072 | if (!pnp_port_valid(pdev, 1) || | |
1073 | pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) { | |
1074 | dev_err(&pdev->dev, "Wake PNP Port not valid!\n"); | |
70ef6991 | 1075 | goto exit_free_dev_rdev; |
6d2f5c27 JW |
1076 | } |
1077 | ||
1078 | nvt->cir_addr = pnp_port_start(pdev, 0); | |
1079 | nvt->cir_irq = pnp_irq(pdev, 0); | |
1080 | ||
1081 | nvt->cir_wake_addr = pnp_port_start(pdev, 1); | |
6d2f5c27 JW |
1082 | |
1083 | nvt->cr_efir = CR_EFIR; | |
1084 | nvt->cr_efdr = CR_EFDR; | |
1085 | ||
1086 | spin_lock_init(&nvt->nvt_lock); | |
1087 | spin_lock_init(&nvt->tx.lock); | |
1088 | ||
6d2f5c27 JW |
1089 | pnp_set_drvdata(pdev, nvt); |
1090 | nvt->pdev = pdev; | |
1091 | ||
1092 | init_waitqueue_head(&nvt->tx.queue); | |
1093 | ||
3f1321cb HK |
1094 | ret = nvt_hw_detect(nvt); |
1095 | if (ret) | |
1096 | goto exit_free_dev_rdev; | |
6d2f5c27 JW |
1097 | |
1098 | /* Initialize CIR & CIR Wake Logical Devices */ | |
1099 | nvt_efm_enable(nvt); | |
1100 | nvt_cir_ldev_init(nvt); | |
1101 | nvt_cir_wake_ldev_init(nvt); | |
1102 | nvt_efm_disable(nvt); | |
1103 | ||
ccca00d6 HK |
1104 | /* |
1105 | * Initialize CIR & CIR Wake Config Registers | |
1106 | * and enable logical devices | |
1107 | */ | |
6d2f5c27 JW |
1108 | nvt_cir_regs_init(nvt); |
1109 | nvt_cir_wake_regs_init(nvt); | |
1110 | ||
d8b4b582 DH |
1111 | /* Set up the rc device */ |
1112 | rdev->priv = nvt; | |
1113 | rdev->driver_type = RC_DRIVER_IR_RAW; | |
c5540fbb | 1114 | rdev->allowed_protocols = RC_BIT_ALL; |
d8b4b582 DH |
1115 | rdev->open = nvt_open; |
1116 | rdev->close = nvt_close; | |
1117 | rdev->tx_ir = nvt_tx_ir; | |
1118 | rdev->s_tx_carrier = nvt_set_tx_carrier; | |
1119 | rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver"; | |
46872d27 | 1120 | rdev->input_phys = "nuvoton/cir0"; |
d8b4b582 DH |
1121 | rdev->input_id.bustype = BUS_HOST; |
1122 | rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2; | |
1123 | rdev->input_id.product = nvt->chip_major; | |
1124 | rdev->input_id.version = nvt->chip_minor; | |
46872d27 | 1125 | rdev->dev.parent = &pdev->dev; |
d8b4b582 DH |
1126 | rdev->driver_name = NVT_DRIVER_NAME; |
1127 | rdev->map_name = RC_MAP_RC6_MCE; | |
d7b290a1 | 1128 | rdev->timeout = MS_TO_NS(100); |
46872d27 JW |
1129 | /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ |
1130 | rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD); | |
6d2f5c27 | 1131 | #if 0 |
d8b4b582 DH |
1132 | rdev->min_timeout = XYZ; |
1133 | rdev->max_timeout = XYZ; | |
6d2f5c27 | 1134 | /* tx bits */ |
d8b4b582 | 1135 | rdev->tx_resolution = XYZ; |
6d2f5c27 | 1136 | #endif |
d62b6818 | 1137 | nvt->rdev = rdev; |
6d2f5c27 | 1138 | |
9fa35204 MK |
1139 | ret = rc_register_device(rdev); |
1140 | if (ret) | |
1141 | goto exit_free_dev_rdev; | |
1142 | ||
9ef449c6 LH |
1143 | ret = -EBUSY; |
1144 | /* now claim resources */ | |
099256e5 | 1145 | if (!devm_request_region(&pdev->dev, nvt->cir_addr, |
9ef449c6 | 1146 | CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) |
9fa35204 | 1147 | goto exit_unregister_device; |
9ef449c6 | 1148 | |
099256e5 HK |
1149 | if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr, |
1150 | IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt)) | |
1151 | goto exit_unregister_device; | |
9ef449c6 | 1152 | |
099256e5 | 1153 | if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr, |
33cb5401 | 1154 | CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake")) |
099256e5 | 1155 | goto exit_unregister_device; |
9ef449c6 | 1156 | |
02212001 | 1157 | ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data); |
449c1fcd HK |
1158 | if (ret) |
1159 | goto exit_unregister_device; | |
1160 | ||
46872d27 | 1161 | device_init_wakeup(&pdev->dev, true); |
d62b6818 | 1162 | |
211477fe | 1163 | dev_notice(&pdev->dev, "driver has been successfully loaded\n"); |
6d2f5c27 JW |
1164 | if (debug) { |
1165 | cir_dump_regs(nvt); | |
1166 | cir_wake_dump_regs(nvt); | |
1167 | } | |
1168 | ||
1169 | return 0; | |
1170 | ||
9fa35204 MK |
1171 | exit_unregister_device: |
1172 | rc_unregister_device(rdev); | |
f73e1851 | 1173 | rdev = NULL; |
70ef6991 | 1174 | exit_free_dev_rdev: |
d8b4b582 | 1175 | rc_free_device(rdev); |
6d2f5c27 JW |
1176 | |
1177 | return ret; | |
1178 | } | |
1179 | ||
4c62e976 | 1180 | static void nvt_remove(struct pnp_dev *pdev) |
6d2f5c27 JW |
1181 | { |
1182 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
6d2f5c27 | 1183 | |
02212001 | 1184 | device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data); |
449c1fcd | 1185 | |
6d2f5c27 | 1186 | nvt_disable_cir(nvt); |
b883af30 | 1187 | |
6d2f5c27 JW |
1188 | /* enable CIR Wake (for IR power-on) */ |
1189 | nvt_enable_wake(nvt); | |
6d2f5c27 | 1190 | |
d8b4b582 | 1191 | rc_unregister_device(nvt->rdev); |
6d2f5c27 JW |
1192 | } |
1193 | ||
1194 | static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state) | |
1195 | { | |
1196 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
1197 | unsigned long flags; | |
1198 | ||
1199 | nvt_dbg("%s called", __func__); | |
1200 | ||
6d2f5c27 JW |
1201 | spin_lock_irqsave(&nvt->tx.lock, flags); |
1202 | nvt->tx.tx_state = ST_TX_NONE; | |
1203 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
1204 | ||
fb2b0065 HK |
1205 | spin_lock_irqsave(&nvt->nvt_lock, flags); |
1206 | ||
1207 | /* zero out misc state tracking */ | |
1208 | nvt->study_state = ST_STUDY_NONE; | |
1209 | nvt->wake_state = ST_WAKE_NONE; | |
1210 | ||
6d2f5c27 JW |
1211 | /* disable all CIR interrupts */ |
1212 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
1213 | ||
b883af30 HK |
1214 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
1215 | ||
6d2f5c27 | 1216 | /* disable cir logical dev */ |
a17ede9a | 1217 | nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR); |
6d2f5c27 JW |
1218 | |
1219 | /* make sure wake is enabled */ | |
1220 | nvt_enable_wake(nvt); | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
1225 | static int nvt_resume(struct pnp_dev *pdev) | |
1226 | { | |
6d2f5c27 JW |
1227 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); |
1228 | ||
1229 | nvt_dbg("%s called", __func__); | |
1230 | ||
6d2f5c27 JW |
1231 | nvt_cir_regs_init(nvt); |
1232 | nvt_cir_wake_regs_init(nvt); | |
1233 | ||
f2747cf6 | 1234 | return 0; |
6d2f5c27 JW |
1235 | } |
1236 | ||
1237 | static void nvt_shutdown(struct pnp_dev *pdev) | |
1238 | { | |
1239 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
fb2b0065 | 1240 | |
6d2f5c27 JW |
1241 | nvt_enable_wake(nvt); |
1242 | } | |
1243 | ||
1244 | static const struct pnp_device_id nvt_ids[] = { | |
1245 | { "WEC0530", 0 }, /* CIR */ | |
1246 | { "NTN0530", 0 }, /* CIR for new chip's pnp id*/ | |
1247 | { "", 0 }, | |
1248 | }; | |
1249 | ||
1250 | static struct pnp_driver nvt_driver = { | |
1251 | .name = NVT_DRIVER_NAME, | |
1252 | .id_table = nvt_ids, | |
1253 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
1254 | .probe = nvt_probe, | |
4c62e976 | 1255 | .remove = nvt_remove, |
6d2f5c27 JW |
1256 | .suspend = nvt_suspend, |
1257 | .resume = nvt_resume, | |
1258 | .shutdown = nvt_shutdown, | |
1259 | }; | |
1260 | ||
6d2f5c27 JW |
1261 | module_param(debug, int, S_IRUGO | S_IWUSR); |
1262 | MODULE_PARM_DESC(debug, "Enable debugging output"); | |
1263 | ||
1264 | MODULE_DEVICE_TABLE(pnp, nvt_ids); | |
1265 | MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver"); | |
1266 | ||
1267 | MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>"); | |
1268 | MODULE_LICENSE("GPL"); | |
1269 | ||
af638a04 | 1270 | module_pnp_driver(nvt_driver); |