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[media] media: rc: nuvoton-cir: improve chip detection
[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
CommitLineData
6d2f5c27
JW		 1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
563cd5ce
JP		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
6d2f5c27
JW		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pnp.h>
33#include <linux/io.h>
34#include <linux/interrupt.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
6bda9644 37#include <media/rc-core.h>
6d2f5c27
JW		 38#include <linux/pci_ids.h>
39
40#include "nuvoton-cir.h"
41
b5cf725c
HK		 42static const struct nvt_chip nvt_chips[] = {
43 { "w83667hg", NVT_W83667HG },
44 { "NCT6775F", NVT_6775F },
45 { "NCT6776F", NVT_6776F },
46};
47
48static inline bool is_w83667hg(struct nvt_dev *nvt)
49{
50 return nvt->chip_ver == NVT_W83667HG;
51}
52
6d2f5c27
JW		 53/* write val to config reg */
54static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
55{
56 outb(reg, nvt->cr_efir);
57 outb(val, nvt->cr_efdr);
58}
59
60/* read val from config reg */
61static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
62{
63 outb(reg, nvt->cr_efir);
64 return inb(nvt->cr_efdr);
65}
66
67/* update config register bit without changing other bits */
68static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
69{
70 u8 tmp = nvt_cr_read(nvt, reg) | val;
71 nvt_cr_write(nvt, tmp, reg);
72}
73
74/* clear config register bit without changing other bits */
75static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
76{
77 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
78 nvt_cr_write(nvt, tmp, reg);
79}
80
81/* enter extended function mode */
82static inline void nvt_efm_enable(struct nvt_dev *nvt)
83{
84 /* Enabling Extended Function Mode explicitly requires writing 2x */
85 outb(EFER_EFM_ENABLE, nvt->cr_efir);
86 outb(EFER_EFM_ENABLE, nvt->cr_efir);
87}
88
89/* exit extended function mode */
90static inline void nvt_efm_disable(struct nvt_dev *nvt)
91{
92 outb(EFER_EFM_DISABLE, nvt->cr_efir);
93}
94
95/*
96 * When you want to address a specific logical device, write its logical
97 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
98 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
99 */
100static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
101{
102 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
103 outb(ldev, nvt->cr_efdr);
104}
105
106/* write val to cir config register */
107static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
108{
109 outb(val, nvt->cir_addr + offset);
110}
111
112/* read val from cir config register */
113static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
114{
115 u8 val;
116
117 val = inb(nvt->cir_addr + offset);
118
119 return val;
120}
121
122/* write val to cir wake register */
123static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
124 u8 val, u8 offset)
125{
126 outb(val, nvt->cir_wake_addr + offset);
127}
128
129/* read val from cir wake config register */
130static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
131{
132 u8 val;
133
134 val = inb(nvt->cir_wake_addr + offset);
135
136 return val;
137}
138
139/* dump current cir register contents */
140static void cir_dump_regs(struct nvt_dev *nvt)
141{
142 nvt_efm_enable(nvt);
143 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
144
563cd5ce
JP		 145 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
146 pr_info(" * CR CIR ACTIVE : 0x%x\n",
147 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
148 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
149 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
6d2f5c27 150 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 151 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
152 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 153
154 nvt_efm_disable(nvt);
155
563cd5ce
JP		 156 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
157 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
158 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
159 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
160 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
161 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
162 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
163 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
164 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
165 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
166 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
167 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
168 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
169 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
170 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
171 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
172 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
6d2f5c27
JW		 173}
174
175/* dump current cir wake register contents */
176static void cir_wake_dump_regs(struct nvt_dev *nvt)
177{
178 u8 i, fifo_len;
179
180 nvt_efm_enable(nvt);
181 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
182
563cd5ce
JP		 183 pr_info("%s: Dump CIR WAKE logical device registers:\n",
184 NVT_DRIVER_NAME);
185 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
186 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
187 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
188 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
4e6e29ad 189 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 190 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
191 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 192
193 nvt_efm_disable(nvt);
194
563cd5ce
JP		 195 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
196 pr_info(" * IRCON: 0x%x\n",
197 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
198 pr_info(" * IRSTS: 0x%x\n",
199 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
200 pr_info(" * IREN: 0x%x\n",
201 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
202 pr_info(" * FIFO CMP DEEP: 0x%x\n",
203 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
204 pr_info(" * FIFO CMP TOL: 0x%x\n",
205 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
206 pr_info(" * FIFO COUNT: 0x%x\n",
207 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
208 pr_info(" * SLCH: 0x%x\n",
209 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
210 pr_info(" * SLCL: 0x%x\n",
211 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
212 pr_info(" * FIFOCON: 0x%x\n",
213 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
214 pr_info(" * SRXFSTS: 0x%x\n",
215 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
216 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
217 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
218 pr_info(" * WR FIFO DATA: 0x%x\n",
219 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
220 pr_info(" * RD FIFO ONLY: 0x%x\n",
221 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
222 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
223 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
224 pr_info(" * FIFO IGNORE: 0x%x\n",
225 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
226 pr_info(" * IRFSM: 0x%x\n",
227 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
6d2f5c27
JW		 228
229 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
563cd5ce
JP		 230 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
231 pr_info("* Contents =");
6d2f5c27 232 for (i = 0; i < fifo_len; i++)
563cd5ce
JP		 233 pr_cont(" %02x",
234 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
235 pr_cont("\n");
6d2f5c27
JW		 236}
237
b5cf725c
HK		 238static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
239{
240 int i;
241
242 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
243 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
244 nvt->chip_ver = nvt_chips[i].chip_ver;
245 return nvt_chips[i].name;
246 }
247
248 return NULL;
249}
250
251
6d2f5c27
JW		 252/* detect hardware features */
253static int nvt_hw_detect(struct nvt_dev *nvt)
254{
b5cf725c
HK		 255 const char *chip_name;
256 int chip_id;
6d2f5c27
JW		 257
258 nvt_efm_enable(nvt);
259
260 /* Check if we're wired for the alternate EFER setup */
b5cf725c
HK		 261 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
262 if (nvt->chip_major == 0xff) {
6d2f5c27
JW		 263 nvt->cr_efir = CR_EFIR2;
264 nvt->cr_efdr = CR_EFDR2;
265 nvt_efm_enable(nvt);
b5cf725c 266 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
6d2f5c27
JW		 267 }
268
b5cf725c
HK		 269 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
270
271 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
272 chip_name = nvt_find_chip(nvt, chip_id);
6d2f5c27 273
362d3a3a 274 /* warn, but still let the driver load, if we don't know this chip */
b5cf725c
HK		 275 if (!chip_name)
276 nvt_pr(KERN_WARNING,
277 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
278 nvt->chip_major, nvt->chip_minor);
362d3a3a 279 else
b5cf725c
HK		 280 nvt_dbg("found %s or compatible: chip id: 0x%02x 0x%02x",
281 chip_name, nvt->chip_major, nvt->chip_minor);
362d3a3a 282
6d2f5c27
JW		 283 nvt_efm_disable(nvt);
284
f2747cf6 285 return 0;
6d2f5c27
JW		 286}
287
288static void nvt_cir_ldev_init(struct nvt_dev *nvt)
289{
39381d4f
JW		 290 u8 val, psreg, psmask, psval;
291
b5cf725c 292 if (is_w83667hg(nvt)) {
39381d4f
JW		 293 psreg = CR_MULTIFUNC_PIN_SEL;
294 psmask = MULTIFUNC_PIN_SEL_MASK;
295 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
296 } else {
297 psreg = CR_OUTPUT_PIN_SEL;
298 psmask = OUTPUT_PIN_SEL_MASK;
299 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
300 }
6d2f5c27 301
39381d4f
JW		 302 /* output pin selection: enable CIR, with WB sensor enabled */
303 val = nvt_cr_read(nvt, psreg);
304 val &= psmask;
305 val |= psval;
306 nvt_cr_write(nvt, val, psreg);
6d2f5c27
JW		 307
308 /* Select CIR logical device and enable */
309 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
310 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
311
312 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
313 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
314
315 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
316
317 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
318 nvt->cir_addr, nvt->cir_irq);
319}
320
321static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
322{
323 /* Select ACPI logical device, enable it and CIR Wake */
324 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
325 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
326
327 /* Enable CIR Wake via PSOUT# (Pin60) */
328 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
329
6d2f5c27
JW		 330 /* enable pme interrupt of cir wakeup event */
331 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
332
333 /* Select CIR Wake logical device and enable */
334 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
335 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
336
337 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
338 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
339
340 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
341
342 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
343 nvt->cir_wake_addr, nvt->cir_wake_irq);
344}
345
346/* clear out the hardware's cir rx fifo */
347static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
348{
349 u8 val;
350
351 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
352 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
353}
354
355/* clear out the hardware's cir wake rx fifo */
356static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
357{
358 u8 val;
359
360 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
361 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
362 CIR_WAKE_FIFOCON);
363}
364
365/* clear out the hardware's cir tx fifo */
366static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
367{
368 u8 val;
369
370 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
371 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
372}
373
fbdc781c
JW		 374/* enable RX Trigger Level Reach and Packet End interrupts */
375static void nvt_set_cir_iren(struct nvt_dev *nvt)
376{
377 u8 iren;
378
379 iren = CIR_IREN_RTR | CIR_IREN_PE;
380 nvt_cir_reg_write(nvt, iren, CIR_IREN);
381}
382
6d2f5c27
JW		 383static void nvt_cir_regs_init(struct nvt_dev *nvt)
384{
385 /* set sample limit count (PE interrupt raised when reached) */
386 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
387 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
388
389 /* set fifo irq trigger levels */
390 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
391 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
392
393 /*
394 * Enable TX and RX, specify carrier on = low, off = high, and set
395 * sample period (currently 50us)
396 */
4e6e29ad
JW		 397 nvt_cir_reg_write(nvt,
398 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
399 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
400 CIR_IRCON);
6d2f5c27
JW		 401
402 /* clear hardware rx and tx fifos */
403 nvt_clear_cir_fifo(nvt);
404 nvt_clear_tx_fifo(nvt);
405
406 /* clear any and all stray interrupts */
407 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
408
fbdc781c
JW		 409 /* and finally, enable interrupts */
410 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 411}
412
413static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
414{
3198ed16
JW		 415 /* set number of bytes needed for wake from s3 (default 65) */
416 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
417 CIR_WAKE_FIFO_CMP_DEEP);
6d2f5c27
JW		 418
419 /* set tolerance/variance allowed per byte during wake compare */
420 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
421 CIR_WAKE_FIFO_CMP_TOL);
422
423 /* set sample limit count (PE interrupt raised when reached) */
424 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
425 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
426
427 /* set cir wake fifo rx trigger level (currently 67) */
428 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
429 CIR_WAKE_FIFOCON);
430
431 /*
432 * Enable TX and RX, specific carrier on = low, off = high, and set
433 * sample period (currently 50us)
434 */
435 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
436 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
437 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
438 CIR_WAKE_IRCON);
439
440 /* clear cir wake rx fifo */
441 nvt_clear_cir_wake_fifo(nvt);
442
443 /* clear any and all stray interrupts */
444 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
445}
446
447static void nvt_enable_wake(struct nvt_dev *nvt)
448{
449 nvt_efm_enable(nvt);
450
451 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
452 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
6d2f5c27
JW		 453 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
454
455 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
456 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
457
458 nvt_efm_disable(nvt);
459
460 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
461 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
4e6e29ad
JW		 462 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
463 CIR_WAKE_IRCON);
6d2f5c27
JW		 464 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
465 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
466}
467
230dc94a 468#if 0 /* Currently unused */
6d2f5c27
JW		 469/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
470static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
471{
472 u32 count, carrier, duration = 0;
473 int i;
474
475 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
476 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
477
478 for (i = 0; i < nvt->pkts; i++) {
479 if (nvt->buf[i] & BUF_PULSE_BIT)
480 duration += nvt->buf[i] & BUF_LEN_MASK;
481 }
482
483 duration *= SAMPLE_PERIOD;
484
485 if (!count || !duration) {
486 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
487 count, duration);
488 return 0;
489 }
490
b4608fae 491 carrier = MS_TO_NS(count) / duration;
6d2f5c27
JW		 492
493 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
494 nvt_dbg("WTF? Carrier frequency out of range!");
495
496 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
497 carrier, count, duration);
498
499 return carrier;
500}
230dc94a 501#endif
6d2f5c27
JW		 502/*
503 * set carrier frequency
504 *
505 * set carrier on 2 registers: CP & CC
506 * always set CP as 0x81
507 * set CC by SPEC, CC = 3MHz/carrier - 1
508 */
d8b4b582 509static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
6d2f5c27 510{
d8b4b582 511 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 512 u16 val;
513
48cafec9
DC		 514 if (carrier == 0)
515 return -EINVAL;
516
6d2f5c27
JW		 517 nvt_cir_reg_write(nvt, 1, CIR_CP);
518 val = 3000000 / (carrier) - 1;
519 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
520
521 nvt_dbg("cp: 0x%x cc: 0x%x\n",
522 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
523
524 return 0;
525}
526
527/*
528 * nvt_tx_ir
529 *
530 * 1) clean TX fifo first (handled by AP)
531 * 2) copy data from user space
532 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
533 * 4) send 9 packets to TX FIFO to open TTR
534 * in interrupt_handler:
535 * 5) send all data out
536 * go back to write():
537 * 6) disable TX interrupts, re-enable RX interupts
538 *
539 * The key problem of this function is user space data may larger than
540 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
541 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
542 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
543 * set TXFCONT as 0xff, until buf_count less than 0xff.
544 */
5588dc2b 545static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
6d2f5c27 546{
d8b4b582 547 struct nvt_dev *nvt = dev->priv;
6d2f5c27 548 unsigned long flags;
6d2f5c27
JW		 549 unsigned int i;
550 u8 iren;
551 int ret;
552
553 spin_lock_irqsave(&nvt->tx.lock, flags);
554
5588dc2b
DH		 555 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
556 nvt->tx.buf_count = (ret * sizeof(unsigned));
6d2f5c27
JW		 557
558 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
559
560 nvt->tx.cur_buf_num = 0;
561
562 /* save currently enabled interrupts */
563 iren = nvt_cir_reg_read(nvt, CIR_IREN);
564
565 /* now disable all interrupts, save TFU & TTR */
566 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
567
568 nvt->tx.tx_state = ST_TX_REPLY;
569
570 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
571 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
572
573 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
574 for (i = 0; i < 9; i++)
575 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
576
577 spin_unlock_irqrestore(&nvt->tx.lock, flags);
578
579 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
580
581 spin_lock_irqsave(&nvt->tx.lock, flags);
582 nvt->tx.tx_state = ST_TX_NONE;
583 spin_unlock_irqrestore(&nvt->tx.lock, flags);
584
585 /* restore enabled interrupts to prior state */
586 nvt_cir_reg_write(nvt, iren, CIR_IREN);
587
588 return ret;
589}
590
591/* dump contents of the last rx buffer we got from the hw rx fifo */
592static void nvt_dump_rx_buf(struct nvt_dev *nvt)
593{
594 int i;
595
4e6e29ad 596 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
6d2f5c27 597 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
4e6e29ad
JW		 598 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
599 printk(KERN_CONT "\n");
6d2f5c27
JW		 600}
601
602/*
603 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
604 * trigger decode when appropriate.
605 *
606 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
607 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
608 * (default 50us) intervals for that pulse/space. A discrete signal is
609 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
610 * to signal more IR coming (repeats) or end of IR, respectively. We store
611 * sample data in the raw event kfifo until we see 0x7<something> (except f)
612 * or 0x80, at which time, we trigger a decode operation.
613 */
614static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
615{
4651918a 616 DEFINE_IR_RAW_EVENT(rawir);
6d2f5c27
JW		 617 u8 sample;
618 int i;
619
620 nvt_dbg_verbose("%s firing", __func__);
621
622 if (debug)
623 nvt_dump_rx_buf(nvt);
624
de4ed0c1 625 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
6d2f5c27 626
b7582815
JW		 627 init_ir_raw_event(&rawir);
628
de4ed0c1 629 for (i = 0; i < nvt->pkts; i++) {
6d2f5c27
JW		 630 sample = nvt->buf[i];
631
632 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
b4608fae
JW		 633 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
634 * SAMPLE_PERIOD);
6d2f5c27 635
de4ed0c1
JW		 636 nvt_dbg("Storing %s with duration %d",
637 rawir.pulse ? "pulse" : "space", rawir.duration);
4651918a 638
de4ed0c1 639 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
6d2f5c27
JW		 640
641 /*
642 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
643 * indicates end of IR signal, but new data incoming. In both
644 * cases, it means we're ready to call ir_raw_event_handle
645 */
de4ed0c1 646 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
b7582815 647 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
6d2f5c27 648 ir_raw_event_handle(nvt->rdev);
b7582815 649 }
6d2f5c27
JW		 650 }
651
de4ed0c1
JW		 652 nvt->pkts = 0;
653
b7582815
JW		 654 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
655 ir_raw_event_handle(nvt->rdev);
656
6d2f5c27
JW		 657 nvt_dbg_verbose("%s done", __func__);
658}
659
fbdc781c
JW		 660static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
661{
662 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
663
664 nvt->pkts = 0;
665 nvt_clear_cir_fifo(nvt);
666 ir_raw_event_reset(nvt->rdev);
667}
668
6d2f5c27
JW		 669/* copy data from hardware rx fifo into driver buffer */
670static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
671{
672 unsigned long flags;
673 u8 fifocount, val;
674 unsigned int b_idx;
fbdc781c 675 bool overrun = false;
6d2f5c27
JW		 676 int i;
677
678 /* Get count of how many bytes to read from RX FIFO */
679 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
680 /* if we get 0xff, probably means the logical dev is disabled */
681 if (fifocount == 0xff)
682 return;
fbdc781c 683 /* watch out for a fifo overrun condition */
6d2f5c27 684 else if (fifocount > RX_BUF_LEN) {
fbdc781c
JW		 685 overrun = true;
686 fifocount = RX_BUF_LEN;
6d2f5c27
JW		 687 }
688
689 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
690
691 spin_lock_irqsave(&nvt->nvt_lock, flags);
692
693 b_idx = nvt->pkts;
694
695 /* This should never happen, but lets check anyway... */
696 if (b_idx + fifocount > RX_BUF_LEN) {
697 nvt_process_rx_ir_data(nvt);
698 b_idx = 0;
699 }
700
701 /* Read fifocount bytes from CIR Sample RX FIFO register */
702 for (i = 0; i < fifocount; i++) {
703 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
704 nvt->buf[b_idx + i] = val;
705 }
706
707 nvt->pkts += fifocount;
708 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
709
710 nvt_process_rx_ir_data(nvt);
711
fbdc781c
JW		 712 if (overrun)
713 nvt_handle_rx_fifo_overrun(nvt);
714
6d2f5c27
JW		 715 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
716}
717
718static void nvt_cir_log_irqs(u8 status, u8 iren)
719{
720 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
721 status, iren,
722 status & CIR_IRSTS_RDR ? " RDR" : "",
723 status & CIR_IRSTS_RTR ? " RTR" : "",
724 status & CIR_IRSTS_PE ? " PE" : "",
725 status & CIR_IRSTS_RFO ? " RFO" : "",
726 status & CIR_IRSTS_TE ? " TE" : "",
727 status & CIR_IRSTS_TTR ? " TTR" : "",
728 status & CIR_IRSTS_TFU ? " TFU" : "",
729 status & CIR_IRSTS_GH ? " GH" : "",
730 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
731 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
732 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
733}
734
735static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
736{
737 unsigned long flags;
738 bool tx_inactive;
739 u8 tx_state;
740
741 spin_lock_irqsave(&nvt->tx.lock, flags);
742 tx_state = nvt->tx.tx_state;
743 spin_unlock_irqrestore(&nvt->tx.lock, flags);
744
745 tx_inactive = (tx_state == ST_TX_NONE);
746
747 return tx_inactive;
748}
749
750/* interrupt service routine for incoming and outgoing CIR data */
751static irqreturn_t nvt_cir_isr(int irq, void *data)
752{
753 struct nvt_dev *nvt = data;
754 u8 status, iren, cur_state;
755 unsigned long flags;
756
757 nvt_dbg_verbose("%s firing", __func__);
758
759 nvt_efm_enable(nvt);
760 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
761 nvt_efm_disable(nvt);
762
763 /*
764 * Get IR Status register contents. Write 1 to ack/clear
765 *
766 * bit: reg name - description
767 * 7: CIR_IRSTS_RDR - RX Data Ready
768 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
769 * 5: CIR_IRSTS_PE - Packet End
770 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
771 * 3: CIR_IRSTS_TE - TX FIFO Empty
772 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
773 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
774 * 0: CIR_IRSTS_GH - Min Length Detected
775 */
776 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
777 if (!status) {
778 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
779 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
2bbf9e06 780 return IRQ_NONE;
6d2f5c27
JW		 781 }
782
783 /* ack/clear all irq flags we've got */
784 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
785 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
786
787 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
788 iren = nvt_cir_reg_read(nvt, CIR_IREN);
789 if (!iren) {
790 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
2bbf9e06 791 return IRQ_NONE;
6d2f5c27
JW		 792 }
793
794 if (debug)
795 nvt_cir_log_irqs(status, iren);
796
797 if (status & CIR_IRSTS_RTR) {
798 /* FIXME: add code for study/learn mode */
799 /* We only do rx if not tx'ing */
800 if (nvt_cir_tx_inactive(nvt))
801 nvt_get_rx_ir_data(nvt);
802 }
803
804 if (status & CIR_IRSTS_PE) {
805 if (nvt_cir_tx_inactive(nvt))
806 nvt_get_rx_ir_data(nvt);
807
808 spin_lock_irqsave(&nvt->nvt_lock, flags);
809
810 cur_state = nvt->study_state;
811
812 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
813
814 if (cur_state == ST_STUDY_NONE)
815 nvt_clear_cir_fifo(nvt);
816 }
817
818 if (status & CIR_IRSTS_TE)
819 nvt_clear_tx_fifo(nvt);
820
821 if (status & CIR_IRSTS_TTR) {
822 unsigned int pos, count;
823 u8 tmp;
824
825 spin_lock_irqsave(&nvt->tx.lock, flags);
826
827 pos = nvt->tx.cur_buf_num;
828 count = nvt->tx.buf_count;
829
830 /* Write data into the hardware tx fifo while pos < count */
831 if (pos < count) {
832 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
833 nvt->tx.cur_buf_num++;
834 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
835 } else {
836 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
837 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
838 }
839
840 spin_unlock_irqrestore(&nvt->tx.lock, flags);
841
842 }
843
844 if (status & CIR_IRSTS_TFU) {
845 spin_lock_irqsave(&nvt->tx.lock, flags);
846 if (nvt->tx.tx_state == ST_TX_REPLY) {
847 nvt->tx.tx_state = ST_TX_REQUEST;
848 wake_up(&nvt->tx.queue);
849 }
850 spin_unlock_irqrestore(&nvt->tx.lock, flags);
851 }
852
853 nvt_dbg_verbose("%s done", __func__);
2bbf9e06 854 return IRQ_HANDLED;
6d2f5c27
JW		 855}
856
857/* Interrupt service routine for CIR Wake */
858static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
859{
860 u8 status, iren, val;
861 struct nvt_dev *nvt = data;
862 unsigned long flags;
863
864 nvt_dbg_wake("%s firing", __func__);
865
866 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
867 if (!status)
2bbf9e06 868 return IRQ_NONE;
6d2f5c27
JW		 869
870 if (status & CIR_WAKE_IRSTS_IR_PENDING)
871 nvt_clear_cir_wake_fifo(nvt);
872
873 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
874 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
875
876 /* Interrupt may be shared with CIR, bail if Wake not enabled */
877 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
878 if (!iren) {
879 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
2bbf9e06 880 return IRQ_HANDLED;
6d2f5c27
JW		 881 }
882
883 if ((status & CIR_WAKE_IRSTS_PE) &&
884 (nvt->wake_state == ST_WAKE_START)) {
885 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
886 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
887 nvt_dbg("setting wake up key: 0x%x", val);
888 }
889
890 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
891 spin_lock_irqsave(&nvt->nvt_lock, flags);
892 nvt->wake_state = ST_WAKE_FINISH;
893 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
894 }
895
896 nvt_dbg_wake("%s done", __func__);
2bbf9e06 897 return IRQ_HANDLED;
6d2f5c27
JW		 898}
899
900static void nvt_enable_cir(struct nvt_dev *nvt)
901{
902 /* set function enable flags */
903 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
904 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
905 CIR_IRCON);
906
907 nvt_efm_enable(nvt);
908
909 /* enable the CIR logical device */
910 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
911 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
912
913 nvt_efm_disable(nvt);
914
915 /* clear all pending interrupts */
916 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
917
918 /* enable interrupts */
fbdc781c 919 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 920}
921
922static void nvt_disable_cir(struct nvt_dev *nvt)
923{
924 /* disable CIR interrupts */
925 nvt_cir_reg_write(nvt, 0, CIR_IREN);
926
927 /* clear any and all pending interrupts */
928 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
929
930 /* clear all function enable flags */
931 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
932
933 /* clear hardware rx and tx fifos */
934 nvt_clear_cir_fifo(nvt);
935 nvt_clear_tx_fifo(nvt);
936
937 nvt_efm_enable(nvt);
938
939 /* disable the CIR logical device */
940 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
941 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
942
943 nvt_efm_disable(nvt);
944}
945
d8b4b582 946static int nvt_open(struct rc_dev *dev)
6d2f5c27 947{
d8b4b582 948 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 949 unsigned long flags;
950
951 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 952 nvt_enable_cir(nvt);
953 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
954
955 return 0;
956}
957
d8b4b582 958static void nvt_close(struct rc_dev *dev)
6d2f5c27 959{
d8b4b582 960 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 961 unsigned long flags;
962
963 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 964 nvt_disable_cir(nvt);
965 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
966}
967
968/* Allocate memory, probe hardware, and initialize everything */
969static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
970{
d8b4b582
DH		 971 struct nvt_dev *nvt;
972 struct rc_dev *rdev;
6d2f5c27
JW		 973 int ret = -ENOMEM;
974
099256e5 975 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
6d2f5c27
JW		 976 if (!nvt)
977 return ret;
978
6d2f5c27 979 /* input device for IR remote (and tx) */
d8b4b582 980 rdev = rc_allocate_device();
6d2f5c27 981 if (!rdev)
70ef6991 982 goto exit_free_dev_rdev;
6d2f5c27
JW		 983
984 ret = -ENODEV;
c3c2077d
AS		 985 /* activate pnp device */
986 if (pnp_activate_dev(pdev) < 0) {
987 dev_err(&pdev->dev, "Could not activate PNP device!\n");
988 goto exit_free_dev_rdev;
989 }
990
6d2f5c27
JW		 991 /* validate pnp resources */
992 if (!pnp_port_valid(pdev, 0) ||
993 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
994 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
70ef6991 995 goto exit_free_dev_rdev;
6d2f5c27
JW		 996 }
997
998 if (!pnp_irq_valid(pdev, 0)) {
999 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
70ef6991 1000 goto exit_free_dev_rdev;
6d2f5c27
JW		 1001 }
1002
1003 if (!pnp_port_valid(pdev, 1) ||
1004 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1005 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
70ef6991 1006 goto exit_free_dev_rdev;
6d2f5c27
JW		 1007 }
1008
1009 nvt->cir_addr = pnp_port_start(pdev, 0);
1010 nvt->cir_irq = pnp_irq(pdev, 0);
1011
1012 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1013 /* irq is always shared between cir and cir wake */
1014 nvt->cir_wake_irq = nvt->cir_irq;
1015
1016 nvt->cr_efir = CR_EFIR;
1017 nvt->cr_efdr = CR_EFDR;
1018
1019 spin_lock_init(&nvt->nvt_lock);
1020 spin_lock_init(&nvt->tx.lock);
1021
6d2f5c27
JW		 1022 pnp_set_drvdata(pdev, nvt);
1023 nvt->pdev = pdev;
1024
1025 init_waitqueue_head(&nvt->tx.queue);
1026
1027 ret = nvt_hw_detect(nvt);
1028 if (ret)
70ef6991 1029 goto exit_free_dev_rdev;
6d2f5c27
JW		 1030
1031 /* Initialize CIR & CIR Wake Logical Devices */
1032 nvt_efm_enable(nvt);
1033 nvt_cir_ldev_init(nvt);
1034 nvt_cir_wake_ldev_init(nvt);
1035 nvt_efm_disable(nvt);
1036
1037 /* Initialize CIR & CIR Wake Config Registers */
1038 nvt_cir_regs_init(nvt);
1039 nvt_cir_wake_regs_init(nvt);
1040
d8b4b582
DH		 1041 /* Set up the rc device */
1042 rdev->priv = nvt;
1043 rdev->driver_type = RC_DRIVER_IR_RAW;
c5540fbb 1044 rdev->allowed_protocols = RC_BIT_ALL;
d8b4b582
DH		 1045 rdev->open = nvt_open;
1046 rdev->close = nvt_close;
1047 rdev->tx_ir = nvt_tx_ir;
1048 rdev->s_tx_carrier = nvt_set_tx_carrier;
1049 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
46872d27 1050 rdev->input_phys = "nuvoton/cir0";
d8b4b582
DH		 1051 rdev->input_id.bustype = BUS_HOST;
1052 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1053 rdev->input_id.product = nvt->chip_major;
1054 rdev->input_id.version = nvt->chip_minor;
46872d27 1055 rdev->dev.parent = &pdev->dev;
d8b4b582
DH		 1056 rdev->driver_name = NVT_DRIVER_NAME;
1057 rdev->map_name = RC_MAP_RC6_MCE;
d7b290a1 1058 rdev->timeout = MS_TO_NS(100);
46872d27
JW		 1059 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1060 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
6d2f5c27 1061#if 0
d8b4b582
DH		 1062 rdev->min_timeout = XYZ;
1063 rdev->max_timeout = XYZ;
6d2f5c27 1064 /* tx bits */
d8b4b582 1065 rdev->tx_resolution = XYZ;
6d2f5c27 1066#endif
d62b6818 1067 nvt->rdev = rdev;
6d2f5c27 1068
9fa35204
MK		 1069 ret = rc_register_device(rdev);
1070 if (ret)
1071 goto exit_free_dev_rdev;
1072
9ef449c6
LH		 1073 ret = -EBUSY;
1074 /* now claim resources */
099256e5 1075 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
9ef449c6 1076 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
9fa35204 1077 goto exit_unregister_device;
9ef449c6 1078
099256e5
HK		 1079 if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1080 IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt))
1081 goto exit_unregister_device;
9ef449c6 1082
099256e5 1083 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
9ef449c6 1084 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
099256e5 1085 goto exit_unregister_device;
9ef449c6 1086
099256e5
HK		 1087 if (devm_request_irq(&pdev->dev, nvt->cir_wake_irq,
1088 nvt_cir_wake_isr, IRQF_SHARED,
1089 NVT_DRIVER_NAME, (void *)nvt))
1090 goto exit_unregister_device;
9ef449c6 1091
46872d27 1092 device_init_wakeup(&pdev->dev, true);
d62b6818 1093
6d2f5c27
JW		 1094 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1095 if (debug) {
1096 cir_dump_regs(nvt);
1097 cir_wake_dump_regs(nvt);
1098 }
1099
1100 return 0;
1101
9fa35204
MK		 1102exit_unregister_device:
1103 rc_unregister_device(rdev);
f73e1851 1104 rdev = NULL;
70ef6991 1105exit_free_dev_rdev:
d8b4b582 1106 rc_free_device(rdev);
6d2f5c27
JW		 1107
1108 return ret;
1109}
1110
4c62e976 1111static void nvt_remove(struct pnp_dev *pdev)
6d2f5c27
JW		 1112{
1113 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1114 unsigned long flags;
1115
1116 spin_lock_irqsave(&nvt->nvt_lock, flags);
1117 /* disable CIR */
1118 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1119 nvt_disable_cir(nvt);
1120 /* enable CIR Wake (for IR power-on) */
1121 nvt_enable_wake(nvt);
1122 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1123
d8b4b582 1124 rc_unregister_device(nvt->rdev);
6d2f5c27
JW		 1125}
1126
1127static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1128{
1129 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1130 unsigned long flags;
1131
1132 nvt_dbg("%s called", __func__);
1133
1134 /* zero out misc state tracking */
1135 spin_lock_irqsave(&nvt->nvt_lock, flags);
1136 nvt->study_state = ST_STUDY_NONE;
1137 nvt->wake_state = ST_WAKE_NONE;
1138 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1139
1140 spin_lock_irqsave(&nvt->tx.lock, flags);
1141 nvt->tx.tx_state = ST_TX_NONE;
1142 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1143
1144 /* disable all CIR interrupts */
1145 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1146
1147 nvt_efm_enable(nvt);
1148
1149 /* disable cir logical dev */
1150 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1151 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1152
1153 nvt_efm_disable(nvt);
1154
1155 /* make sure wake is enabled */
1156 nvt_enable_wake(nvt);
1157
1158 return 0;
1159}
1160
1161static int nvt_resume(struct pnp_dev *pdev)
1162{
6d2f5c27
JW		 1163 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1164
1165 nvt_dbg("%s called", __func__);
1166
1167 /* open interrupt */
fbdc781c 1168 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 1169
1170 /* Enable CIR logical device */
1171 nvt_efm_enable(nvt);
1172 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1173 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1174
1175 nvt_efm_disable(nvt);
1176
1177 nvt_cir_regs_init(nvt);
1178 nvt_cir_wake_regs_init(nvt);
1179
f2747cf6 1180 return 0;
6d2f5c27
JW		 1181}
1182
1183static void nvt_shutdown(struct pnp_dev *pdev)
1184{
1185 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1186 nvt_enable_wake(nvt);
1187}
1188
1189static const struct pnp_device_id nvt_ids[] = {
1190 { "WEC0530", 0 }, /* CIR */
1191 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1192 { "", 0 },
1193};
1194
1195static struct pnp_driver nvt_driver = {
1196 .name = NVT_DRIVER_NAME,
1197 .id_table = nvt_ids,
1198 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1199 .probe = nvt_probe,
4c62e976 1200 .remove = nvt_remove,
6d2f5c27
JW		 1201 .suspend = nvt_suspend,
1202 .resume = nvt_resume,
1203 .shutdown = nvt_shutdown,
1204};
1205
6d2f5c27
JW		 1206module_param(debug, int, S_IRUGO | S_IWUSR);
1207MODULE_PARM_DESC(debug, "Enable debugging output");
1208
1209MODULE_DEVICE_TABLE(pnp, nvt_ids);
1210MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1211
1212MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1213MODULE_LICENSE("GPL");
1214
af638a04 1215module_pnp_driver(nvt_driver);
Linux kernel - Deliverables
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