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[media] rc/nuvoton_cir: fix locking issue when calling nvt_enable_wake
[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
CommitLineData
6d2f5c27
JW		 1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
563cd5ce
JP		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
6d2f5c27
JW		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pnp.h>
33#include <linux/io.h>
34#include <linux/interrupt.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
6bda9644 37#include <media/rc-core.h>
6d2f5c27
JW		 38#include <linux/pci_ids.h>
39
40#include "nuvoton-cir.h"
41
b5cf725c
HK		 42static const struct nvt_chip nvt_chips[] = {
43 { "w83667hg", NVT_W83667HG },
44 { "NCT6775F", NVT_6775F },
45 { "NCT6776F", NVT_6776F },
d0b528d5 46 { "NCT6779D", NVT_6779D },
b5cf725c
HK		 47};
48
49static inline bool is_w83667hg(struct nvt_dev *nvt)
50{
51 return nvt->chip_ver == NVT_W83667HG;
52}
53
6d2f5c27
JW		 54/* write val to config reg */
55static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
56{
57 outb(reg, nvt->cr_efir);
58 outb(val, nvt->cr_efdr);
59}
60
61/* read val from config reg */
62static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
63{
64 outb(reg, nvt->cr_efir);
65 return inb(nvt->cr_efdr);
66}
67
68/* update config register bit without changing other bits */
69static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
70{
71 u8 tmp = nvt_cr_read(nvt, reg) | val;
72 nvt_cr_write(nvt, tmp, reg);
73}
74
75/* clear config register bit without changing other bits */
76static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
77{
78 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
79 nvt_cr_write(nvt, tmp, reg);
80}
81
82/* enter extended function mode */
3def9ad6 83static inline int nvt_efm_enable(struct nvt_dev *nvt)
6d2f5c27 84{
3def9ad6
HK		 85 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
86 return -EBUSY;
87
6d2f5c27
JW		 88 /* Enabling Extended Function Mode explicitly requires writing 2x */
89 outb(EFER_EFM_ENABLE, nvt->cr_efir);
90 outb(EFER_EFM_ENABLE, nvt->cr_efir);
3def9ad6
HK		 91
92 return 0;
6d2f5c27
JW		 93}
94
95/* exit extended function mode */
96static inline void nvt_efm_disable(struct nvt_dev *nvt)
97{
98 outb(EFER_EFM_DISABLE, nvt->cr_efir);
3def9ad6
HK		 99
100 release_region(nvt->cr_efir, 2);
6d2f5c27
JW		 101}
102
103/*
104 * When you want to address a specific logical device, write its logical
105 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
106 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
107 */
108static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
109{
7a89836e 110 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
6d2f5c27
JW		 111}
112
0890655c
HK		 113/* select and enable logical device with setting EFM mode*/
114static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
115{
116 nvt_efm_enable(nvt);
117 nvt_select_logical_dev(nvt, ldev);
118 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
119 nvt_efm_disable(nvt);
120}
121
a17ede9a
HK		 122/* select and disable logical device with setting EFM mode*/
123static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
124{
125 nvt_efm_enable(nvt);
126 nvt_select_logical_dev(nvt, ldev);
127 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
128 nvt_efm_disable(nvt);
129}
130
6d2f5c27
JW		 131/* write val to cir config register */
132static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
133{
134 outb(val, nvt->cir_addr + offset);
135}
136
137/* read val from cir config register */
138static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
139{
140 u8 val;
141
142 val = inb(nvt->cir_addr + offset);
143
144 return val;
145}
146
147/* write val to cir wake register */
148static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
149 u8 val, u8 offset)
150{
151 outb(val, nvt->cir_wake_addr + offset);
152}
153
154/* read val from cir wake config register */
155static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
156{
157 u8 val;
158
159 val = inb(nvt->cir_wake_addr + offset);
160
161 return val;
162}
163
fb16aaf5
HK		 164/* don't override io address if one is set already */
165static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
166{
167 unsigned long old_addr;
168
169 old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
170 old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
171
172 if (old_addr)
173 *ioaddr = old_addr;
174 else {
175 nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
176 nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
177 }
178}
179
6d2f5c27
JW		 180/* dump current cir register contents */
181static void cir_dump_regs(struct nvt_dev *nvt)
182{
183 nvt_efm_enable(nvt);
184 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
185
563cd5ce
JP		 186 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
187 pr_info(" * CR CIR ACTIVE : 0x%x\n",
188 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
189 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
190 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
6d2f5c27 191 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 192 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
193 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 194
195 nvt_efm_disable(nvt);
196
563cd5ce
JP		 197 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
198 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
199 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
200 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
201 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
202 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
203 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
204 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
205 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
206 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
207 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
208 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
209 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
210 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
211 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
212 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
213 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
6d2f5c27
JW		 214}
215
216/* dump current cir wake register contents */
217static void cir_wake_dump_regs(struct nvt_dev *nvt)
218{
219 u8 i, fifo_len;
220
221 nvt_efm_enable(nvt);
222 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
223
563cd5ce
JP		 224 pr_info("%s: Dump CIR WAKE logical device registers:\n",
225 NVT_DRIVER_NAME);
226 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
227 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
228 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
229 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
4e6e29ad 230 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 231 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
232 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 233
234 nvt_efm_disable(nvt);
235
563cd5ce
JP		 236 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
237 pr_info(" * IRCON: 0x%x\n",
238 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
239 pr_info(" * IRSTS: 0x%x\n",
240 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
241 pr_info(" * IREN: 0x%x\n",
242 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
243 pr_info(" * FIFO CMP DEEP: 0x%x\n",
244 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
245 pr_info(" * FIFO CMP TOL: 0x%x\n",
246 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
247 pr_info(" * FIFO COUNT: 0x%x\n",
248 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
249 pr_info(" * SLCH: 0x%x\n",
250 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
251 pr_info(" * SLCL: 0x%x\n",
252 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
253 pr_info(" * FIFOCON: 0x%x\n",
254 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
255 pr_info(" * SRXFSTS: 0x%x\n",
256 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
257 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
258 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
259 pr_info(" * WR FIFO DATA: 0x%x\n",
260 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
261 pr_info(" * RD FIFO ONLY: 0x%x\n",
262 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
263 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
264 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
265 pr_info(" * FIFO IGNORE: 0x%x\n",
266 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
267 pr_info(" * IRFSM: 0x%x\n",
268 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
6d2f5c27
JW		 269
270 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
563cd5ce
JP		 271 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
272 pr_info("* Contents =");
6d2f5c27 273 for (i = 0; i < fifo_len; i++)
563cd5ce
JP		 274 pr_cont(" %02x",
275 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
276 pr_cont("\n");
6d2f5c27
JW		 277}
278
b5cf725c
HK		 279static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
280{
281 int i;
282
283 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
284 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
285 nvt->chip_ver = nvt_chips[i].chip_ver;
286 return nvt_chips[i].name;
287 }
288
289 return NULL;
290}
291
292
6d2f5c27 293/* detect hardware features */
3f1321cb 294static int nvt_hw_detect(struct nvt_dev *nvt)
6d2f5c27 295{
b5cf725c
HK		 296 const char *chip_name;
297 int chip_id;
6d2f5c27
JW		 298
299 nvt_efm_enable(nvt);
300
301 /* Check if we're wired for the alternate EFER setup */
b5cf725c
HK		 302 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
303 if (nvt->chip_major == 0xff) {
6d2f5c27
JW		 304 nvt->cr_efir = CR_EFIR2;
305 nvt->cr_efdr = CR_EFDR2;
306 nvt_efm_enable(nvt);
b5cf725c 307 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
6d2f5c27 308 }
b5cf725c
HK		 309 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
310
3f1321cb
HK		 311 nvt_efm_disable(nvt);
312
b5cf725c 313 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
3f1321cb
HK		 314 if (chip_id == NVT_INVALID) {
315 dev_err(&nvt->pdev->dev,
316 "No device found on either EFM port\n");
317 return -ENODEV;
318 }
319
b5cf725c 320 chip_name = nvt_find_chip(nvt, chip_id);
6d2f5c27 321
362d3a3a 322 /* warn, but still let the driver load, if we don't know this chip */
b5cf725c 323 if (!chip_name)
211477fe
HK		 324 dev_warn(&nvt->pdev->dev,
325 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
326 nvt->chip_major, nvt->chip_minor);
362d3a3a 327 else
af082334
HK		 328 dev_info(&nvt->pdev->dev,
329 "found %s or compatible: chip id: 0x%02x 0x%02x",
330 chip_name, nvt->chip_major, nvt->chip_minor);
362d3a3a 331
3f1321cb 332 return 0;
6d2f5c27
JW		 333}
334
335static void nvt_cir_ldev_init(struct nvt_dev *nvt)
336{
39381d4f
JW		 337 u8 val, psreg, psmask, psval;
338
b5cf725c 339 if (is_w83667hg(nvt)) {
39381d4f
JW		 340 psreg = CR_MULTIFUNC_PIN_SEL;
341 psmask = MULTIFUNC_PIN_SEL_MASK;
342 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
343 } else {
344 psreg = CR_OUTPUT_PIN_SEL;
345 psmask = OUTPUT_PIN_SEL_MASK;
346 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
347 }
6d2f5c27 348
39381d4f
JW		 349 /* output pin selection: enable CIR, with WB sensor enabled */
350 val = nvt_cr_read(nvt, psreg);
351 val &= psmask;
352 val |= psval;
353 nvt_cr_write(nvt, val, psreg);
6d2f5c27 354
ccca00d6 355 /* Select CIR logical device */
6d2f5c27 356 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
6d2f5c27 357
fb16aaf5 358 nvt_set_ioaddr(nvt, &nvt->cir_addr);
6d2f5c27
JW		 359
360 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
361
362 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
363 nvt->cir_addr, nvt->cir_irq);
364}
365
366static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
367{
ccca00d6 368 /* Select ACPI logical device and anable it */
6d2f5c27
JW		 369 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
370 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
371
372 /* Enable CIR Wake via PSOUT# (Pin60) */
373 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
374
6d2f5c27
JW		 375 /* enable pme interrupt of cir wakeup event */
376 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
377
ccca00d6 378 /* Select CIR Wake logical device */
6d2f5c27 379 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
6d2f5c27 380
fb16aaf5 381 nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
6d2f5c27
JW		 382
383 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
384
385 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
386 nvt->cir_wake_addr, nvt->cir_wake_irq);
387}
388
389/* clear out the hardware's cir rx fifo */
390static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
391{
392 u8 val;
393
394 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
395 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
396}
397
398/* clear out the hardware's cir wake rx fifo */
399static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
400{
e1a7d981
HK		 401 u8 val, config;
402
403 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
404
405 /* clearing wake fifo works in learning mode only */
406 nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
407 CIR_WAKE_IRCON);
6d2f5c27
JW		 408
409 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
410 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
411 CIR_WAKE_FIFOCON);
e1a7d981
HK		 412
413 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
6d2f5c27
JW		 414}
415
416/* clear out the hardware's cir tx fifo */
417static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
418{
419 u8 val;
420
421 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
422 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
423}
424
fbdc781c
JW		 425/* enable RX Trigger Level Reach and Packet End interrupts */
426static void nvt_set_cir_iren(struct nvt_dev *nvt)
427{
428 u8 iren;
429
430 iren = CIR_IREN_RTR | CIR_IREN_PE;
431 nvt_cir_reg_write(nvt, iren, CIR_IREN);
432}
433
6d2f5c27
JW		 434static void nvt_cir_regs_init(struct nvt_dev *nvt)
435{
436 /* set sample limit count (PE interrupt raised when reached) */
437 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
438 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
439
440 /* set fifo irq trigger levels */
441 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
442 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
443
444 /*
445 * Enable TX and RX, specify carrier on = low, off = high, and set
446 * sample period (currently 50us)
447 */
4e6e29ad
JW		 448 nvt_cir_reg_write(nvt,
449 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
450 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
451 CIR_IRCON);
6d2f5c27
JW		 452
453 /* clear hardware rx and tx fifos */
454 nvt_clear_cir_fifo(nvt);
455 nvt_clear_tx_fifo(nvt);
456
457 /* clear any and all stray interrupts */
458 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
459
fbdc781c
JW		 460 /* and finally, enable interrupts */
461 nvt_set_cir_iren(nvt);
ccca00d6
HK		 462
463 /* enable the CIR logical device */
464 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
6d2f5c27
JW		 465}
466
467static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
468{
3198ed16
JW		 469 /* set number of bytes needed for wake from s3 (default 65) */
470 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
471 CIR_WAKE_FIFO_CMP_DEEP);
6d2f5c27
JW		 472
473 /* set tolerance/variance allowed per byte during wake compare */
474 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
475 CIR_WAKE_FIFO_CMP_TOL);
476
477 /* set sample limit count (PE interrupt raised when reached) */
478 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
479 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
480
481 /* set cir wake fifo rx trigger level (currently 67) */
482 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
483 CIR_WAKE_FIFOCON);
484
485 /*
486 * Enable TX and RX, specific carrier on = low, off = high, and set
487 * sample period (currently 50us)
488 */
489 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
490 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
491 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
492 CIR_WAKE_IRCON);
493
494 /* clear cir wake rx fifo */
495 nvt_clear_cir_wake_fifo(nvt);
496
497 /* clear any and all stray interrupts */
498 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
ccca00d6
HK		 499
500 /* enable the CIR WAKE logical device */
501 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
6d2f5c27
JW		 502}
503
504static void nvt_enable_wake(struct nvt_dev *nvt)
505{
b883af30
HK		 506 unsigned long flags;
507
6d2f5c27
JW		 508 nvt_efm_enable(nvt);
509
510 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
511 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
6d2f5c27
JW		 512 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
513
514 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
515 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
516
517 nvt_efm_disable(nvt);
518
b883af30
HK		 519 spin_lock_irqsave(&nvt->nvt_lock, flags);
520
6d2f5c27
JW		 521 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
522 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
4e6e29ad
JW		 523 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
524 CIR_WAKE_IRCON);
6d2f5c27
JW		 525 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
526 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
b883af30
HK		 527
528 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
6d2f5c27
JW		 529}
530
230dc94a 531#if 0 /* Currently unused */
6d2f5c27
JW		 532/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
533static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
534{
535 u32 count, carrier, duration = 0;
536 int i;
537
538 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
539 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
540
541 for (i = 0; i < nvt->pkts; i++) {
542 if (nvt->buf[i] & BUF_PULSE_BIT)
543 duration += nvt->buf[i] & BUF_LEN_MASK;
544 }
545
546 duration *= SAMPLE_PERIOD;
547
548 if (!count || !duration) {
211477fe
HK		 549 dev_notice(&nvt->pdev->dev,
550 "Unable to determine carrier! (c:%u, d:%u)",
551 count, duration);
6d2f5c27
JW		 552 return 0;
553 }
554
b4608fae 555 carrier = MS_TO_NS(count) / duration;
6d2f5c27
JW		 556
557 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
558 nvt_dbg("WTF? Carrier frequency out of range!");
559
560 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
561 carrier, count, duration);
562
563 return carrier;
564}
230dc94a 565#endif
6d2f5c27
JW		 566/*
567 * set carrier frequency
568 *
569 * set carrier on 2 registers: CP & CC
570 * always set CP as 0x81
571 * set CC by SPEC, CC = 3MHz/carrier - 1
572 */
d8b4b582 573static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
6d2f5c27 574{
d8b4b582 575 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 576 u16 val;
577
48cafec9
DC		 578 if (carrier == 0)
579 return -EINVAL;
580
6d2f5c27
JW		 581 nvt_cir_reg_write(nvt, 1, CIR_CP);
582 val = 3000000 / (carrier) - 1;
583 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
584
585 nvt_dbg("cp: 0x%x cc: 0x%x\n",
586 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
587
588 return 0;
589}
590
591/*
592 * nvt_tx_ir
593 *
594 * 1) clean TX fifo first (handled by AP)
595 * 2) copy data from user space
596 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
597 * 4) send 9 packets to TX FIFO to open TTR
598 * in interrupt_handler:
599 * 5) send all data out
600 * go back to write():
601 * 6) disable TX interrupts, re-enable RX interupts
602 *
603 * The key problem of this function is user space data may larger than
604 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
605 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
606 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
607 * set TXFCONT as 0xff, until buf_count less than 0xff.
608 */
5588dc2b 609static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
6d2f5c27 610{
d8b4b582 611 struct nvt_dev *nvt = dev->priv;
6d2f5c27 612 unsigned long flags;
6d2f5c27
JW		 613 unsigned int i;
614 u8 iren;
615 int ret;
616
617 spin_lock_irqsave(&nvt->tx.lock, flags);
618
5588dc2b
DH		 619 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
620 nvt->tx.buf_count = (ret * sizeof(unsigned));
6d2f5c27
JW		 621
622 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
623
624 nvt->tx.cur_buf_num = 0;
625
626 /* save currently enabled interrupts */
627 iren = nvt_cir_reg_read(nvt, CIR_IREN);
628
629 /* now disable all interrupts, save TFU & TTR */
630 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
631
632 nvt->tx.tx_state = ST_TX_REPLY;
633
634 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
635 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
636
637 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
638 for (i = 0; i < 9; i++)
639 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
640
641 spin_unlock_irqrestore(&nvt->tx.lock, flags);
642
643 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
644
645 spin_lock_irqsave(&nvt->tx.lock, flags);
646 nvt->tx.tx_state = ST_TX_NONE;
647 spin_unlock_irqrestore(&nvt->tx.lock, flags);
648
649 /* restore enabled interrupts to prior state */
650 nvt_cir_reg_write(nvt, iren, CIR_IREN);
651
652 return ret;
653}
654
655/* dump contents of the last rx buffer we got from the hw rx fifo */
656static void nvt_dump_rx_buf(struct nvt_dev *nvt)
657{
658 int i;
659
4e6e29ad 660 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
6d2f5c27 661 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
4e6e29ad
JW		 662 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
663 printk(KERN_CONT "\n");
6d2f5c27
JW		 664}
665
666/*
667 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
668 * trigger decode when appropriate.
669 *
670 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
671 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
672 * (default 50us) intervals for that pulse/space. A discrete signal is
673 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
674 * to signal more IR coming (repeats) or end of IR, respectively. We store
675 * sample data in the raw event kfifo until we see 0x7<something> (except f)
676 * or 0x80, at which time, we trigger a decode operation.
677 */
678static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
679{
4651918a 680 DEFINE_IR_RAW_EVENT(rawir);
6d2f5c27
JW		 681 u8 sample;
682 int i;
683
684 nvt_dbg_verbose("%s firing", __func__);
685
686 if (debug)
687 nvt_dump_rx_buf(nvt);
688
de4ed0c1 689 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
6d2f5c27 690
b7582815
JW		 691 init_ir_raw_event(&rawir);
692
de4ed0c1 693 for (i = 0; i < nvt->pkts; i++) {
6d2f5c27
JW		 694 sample = nvt->buf[i];
695
696 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
b4608fae
JW		 697 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
698 * SAMPLE_PERIOD);
6d2f5c27 699
de4ed0c1
JW		 700 nvt_dbg("Storing %s with duration %d",
701 rawir.pulse ? "pulse" : "space", rawir.duration);
4651918a 702
de4ed0c1 703 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
6d2f5c27
JW		 704
705 /*
706 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
707 * indicates end of IR signal, but new data incoming. In both
708 * cases, it means we're ready to call ir_raw_event_handle
709 */
de4ed0c1 710 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
b7582815 711 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
6d2f5c27 712 ir_raw_event_handle(nvt->rdev);
b7582815 713 }
6d2f5c27
JW		 714 }
715
de4ed0c1
JW		 716 nvt->pkts = 0;
717
b7582815
JW		 718 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
719 ir_raw_event_handle(nvt->rdev);
720
6d2f5c27
JW		 721 nvt_dbg_verbose("%s done", __func__);
722}
723
fbdc781c
JW		 724static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
725{
211477fe 726 dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!");
fbdc781c
JW		 727
728 nvt->pkts = 0;
729 nvt_clear_cir_fifo(nvt);
730 ir_raw_event_reset(nvt->rdev);
731}
732
6d2f5c27
JW		 733/* copy data from hardware rx fifo into driver buffer */
734static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
735{
6d2f5c27
JW		 736 u8 fifocount, val;
737 unsigned int b_idx;
fbdc781c 738 bool overrun = false;
6d2f5c27
JW		 739 int i;
740
741 /* Get count of how many bytes to read from RX FIFO */
742 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
743 /* if we get 0xff, probably means the logical dev is disabled */
744 if (fifocount == 0xff)
745 return;
fbdc781c 746 /* watch out for a fifo overrun condition */
6d2f5c27 747 else if (fifocount > RX_BUF_LEN) {
fbdc781c
JW		 748 overrun = true;
749 fifocount = RX_BUF_LEN;
6d2f5c27
JW		 750 }
751
752 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
753
6d2f5c27
JW		 754 b_idx = nvt->pkts;
755
756 /* This should never happen, but lets check anyway... */
757 if (b_idx + fifocount > RX_BUF_LEN) {
758 nvt_process_rx_ir_data(nvt);
759 b_idx = 0;
760 }
761
762 /* Read fifocount bytes from CIR Sample RX FIFO register */
763 for (i = 0; i < fifocount; i++) {
764 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
765 nvt->buf[b_idx + i] = val;
766 }
767
768 nvt->pkts += fifocount;
769 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
770
771 nvt_process_rx_ir_data(nvt);
772
fbdc781c
JW		 773 if (overrun)
774 nvt_handle_rx_fifo_overrun(nvt);
6d2f5c27
JW		 775}
776
777static void nvt_cir_log_irqs(u8 status, u8 iren)
778{
068fb7dd 779 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
6d2f5c27
JW		 780 status, iren,
781 status & CIR_IRSTS_RDR ? " RDR" : "",
782 status & CIR_IRSTS_RTR ? " RTR" : "",
783 status & CIR_IRSTS_PE ? " PE" : "",
784 status & CIR_IRSTS_RFO ? " RFO" : "",
785 status & CIR_IRSTS_TE ? " TE" : "",
786 status & CIR_IRSTS_TTR ? " TTR" : "",
787 status & CIR_IRSTS_TFU ? " TFU" : "",
788 status & CIR_IRSTS_GH ? " GH" : "",
789 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
790 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
791 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
792}
793
794static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
795{
796 unsigned long flags;
6d2f5c27
JW		 797 u8 tx_state;
798
799 spin_lock_irqsave(&nvt->tx.lock, flags);
800 tx_state = nvt->tx.tx_state;
801 spin_unlock_irqrestore(&nvt->tx.lock, flags);
802
1feac493 803 return tx_state == ST_TX_NONE;
6d2f5c27
JW		 804}
805
806/* interrupt service routine for incoming and outgoing CIR data */
807static irqreturn_t nvt_cir_isr(int irq, void *data)
808{
809 struct nvt_dev *nvt = data;
810 u8 status, iren, cur_state;
811 unsigned long flags;
812
813 nvt_dbg_verbose("%s firing", __func__);
814
e60c1e87
HK		 815 spin_lock_irqsave(&nvt->nvt_lock, flags);
816
6d2f5c27
JW		 817 /*
818 * Get IR Status register contents. Write 1 to ack/clear
819 *
820 * bit: reg name - description
821 * 7: CIR_IRSTS_RDR - RX Data Ready
822 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
823 * 5: CIR_IRSTS_PE - Packet End
824 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
825 * 3: CIR_IRSTS_TE - TX FIFO Empty
826 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
827 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
828 * 0: CIR_IRSTS_GH - Min Length Detected
829 */
830 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
d42fd297
HK		 831 iren = nvt_cir_reg_read(nvt, CIR_IREN);
832
833 /* IRQ may be shared with CIR WAKE, therefore check for each
834 * status bit whether the related interrupt source is enabled
835 */
836 if (!(status & iren)) {
e60c1e87 837 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
6d2f5c27 838 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
2bbf9e06 839 return IRQ_NONE;
6d2f5c27
JW		 840 }
841
842 /* ack/clear all irq flags we've got */
843 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
844 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
845
068fb7dd 846 nvt_cir_log_irqs(status, iren);
6d2f5c27
JW		 847
848 if (status & CIR_IRSTS_RTR) {
849 /* FIXME: add code for study/learn mode */
850 /* We only do rx if not tx'ing */
851 if (nvt_cir_tx_inactive(nvt))
852 nvt_get_rx_ir_data(nvt);
853 }
854
855 if (status & CIR_IRSTS_PE) {
856 if (nvt_cir_tx_inactive(nvt))
857 nvt_get_rx_ir_data(nvt);
858
6d2f5c27
JW		 859 cur_state = nvt->study_state;
860
6d2f5c27
JW		 861 if (cur_state == ST_STUDY_NONE)
862 nvt_clear_cir_fifo(nvt);
863 }
864
e60c1e87
HK		 865 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
866
6d2f5c27
JW		 867 if (status & CIR_IRSTS_TE)
868 nvt_clear_tx_fifo(nvt);
869
870 if (status & CIR_IRSTS_TTR) {
871 unsigned int pos, count;
872 u8 tmp;
873
874 spin_lock_irqsave(&nvt->tx.lock, flags);
875
876 pos = nvt->tx.cur_buf_num;
877 count = nvt->tx.buf_count;
878
879 /* Write data into the hardware tx fifo while pos < count */
880 if (pos < count) {
881 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
882 nvt->tx.cur_buf_num++;
883 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
884 } else {
885 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
886 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
887 }
888
889 spin_unlock_irqrestore(&nvt->tx.lock, flags);
890
891 }
892
893 if (status & CIR_IRSTS_TFU) {
894 spin_lock_irqsave(&nvt->tx.lock, flags);
895 if (nvt->tx.tx_state == ST_TX_REPLY) {
896 nvt->tx.tx_state = ST_TX_REQUEST;
897 wake_up(&nvt->tx.queue);
898 }
899 spin_unlock_irqrestore(&nvt->tx.lock, flags);
900 }
901
902 nvt_dbg_verbose("%s done", __func__);
2bbf9e06 903 return IRQ_HANDLED;
6d2f5c27
JW		 904}
905
906/* Interrupt service routine for CIR Wake */
907static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
908{
909 u8 status, iren, val;
910 struct nvt_dev *nvt = data;
911 unsigned long flags;
912
913 nvt_dbg_wake("%s firing", __func__);
914
e60c1e87
HK		 915 spin_lock_irqsave(&nvt->nvt_lock, flags);
916
6d2f5c27 917 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
d42fd297
HK		 918 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
919
920 /* IRQ may be shared with CIR, therefore check for each
921 * status bit whether the related interrupt source is enabled
922 */
e60c1e87
HK		 923 if (!(status & iren)) {
924 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
2bbf9e06 925 return IRQ_NONE;
e60c1e87 926 }
6d2f5c27
JW		 927
928 if (status & CIR_WAKE_IRSTS_IR_PENDING)
929 nvt_clear_cir_wake_fifo(nvt);
930
931 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
932 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
933
6d2f5c27
JW		 934 if ((status & CIR_WAKE_IRSTS_PE) &&
935 (nvt->wake_state == ST_WAKE_START)) {
936 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
937 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
938 nvt_dbg("setting wake up key: 0x%x", val);
939 }
940
941 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
6d2f5c27 942 nvt->wake_state = ST_WAKE_FINISH;
6d2f5c27
JW		 943 }
944
e60c1e87
HK		 945 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
946
6d2f5c27 947 nvt_dbg_wake("%s done", __func__);
2bbf9e06 948 return IRQ_HANDLED;
6d2f5c27
JW		 949}
950
6d2f5c27
JW		 951static void nvt_disable_cir(struct nvt_dev *nvt)
952{
953 /* disable CIR interrupts */
954 nvt_cir_reg_write(nvt, 0, CIR_IREN);
955
956 /* clear any and all pending interrupts */
957 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
958
959 /* clear all function enable flags */
960 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
961
962 /* clear hardware rx and tx fifos */
963 nvt_clear_cir_fifo(nvt);
964 nvt_clear_tx_fifo(nvt);
965
6d2f5c27 966 /* disable the CIR logical device */
a17ede9a 967 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
6d2f5c27
JW		 968}
969
d8b4b582 970static int nvt_open(struct rc_dev *dev)
6d2f5c27 971{
d8b4b582 972 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 973 unsigned long flags;
974
975 spin_lock_irqsave(&nvt->nvt_lock, flags);
842096fc
HK		 976
977 /* set function enable flags */
978 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
979 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
980 CIR_IRCON);
981
982 /* clear all pending interrupts */
983 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
984
985 /* enable interrupts */
986 nvt_set_cir_iren(nvt);
987
6d2f5c27
JW		 988 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
989
842096fc
HK		 990 /* enable the CIR logical device */
991 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
992
6d2f5c27
JW		 993 return 0;
994}
995
d8b4b582 996static void nvt_close(struct rc_dev *dev)
6d2f5c27 997{
d8b4b582 998 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 999 unsigned long flags;
1000
1001 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 1002 nvt_disable_cir(nvt);
1003 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1004}
1005
1006/* Allocate memory, probe hardware, and initialize everything */
1007static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
1008{
d8b4b582
DH		 1009 struct nvt_dev *nvt;
1010 struct rc_dev *rdev;
6d2f5c27
JW		 1011 int ret = -ENOMEM;
1012
099256e5 1013 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
6d2f5c27
JW		 1014 if (!nvt)
1015 return ret;
1016
6d2f5c27 1017 /* input device for IR remote (and tx) */
d8b4b582 1018 rdev = rc_allocate_device();
6d2f5c27 1019 if (!rdev)
70ef6991 1020 goto exit_free_dev_rdev;
6d2f5c27
JW		 1021
1022 ret = -ENODEV;
c3c2077d
AS		 1023 /* activate pnp device */
1024 if (pnp_activate_dev(pdev) < 0) {
1025 dev_err(&pdev->dev, "Could not activate PNP device!\n");
1026 goto exit_free_dev_rdev;
1027 }
1028
6d2f5c27
JW		 1029 /* validate pnp resources */
1030 if (!pnp_port_valid(pdev, 0) ||
1031 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1032 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
70ef6991 1033 goto exit_free_dev_rdev;
6d2f5c27
JW		 1034 }
1035
1036 if (!pnp_irq_valid(pdev, 0)) {
1037 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
70ef6991 1038 goto exit_free_dev_rdev;
6d2f5c27
JW		 1039 }
1040
1041 if (!pnp_port_valid(pdev, 1) ||
1042 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1043 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
70ef6991 1044 goto exit_free_dev_rdev;
6d2f5c27
JW		 1045 }
1046
1047 nvt->cir_addr = pnp_port_start(pdev, 0);
1048 nvt->cir_irq = pnp_irq(pdev, 0);
1049
1050 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1051 /* irq is always shared between cir and cir wake */
1052 nvt->cir_wake_irq = nvt->cir_irq;
1053
1054 nvt->cr_efir = CR_EFIR;
1055 nvt->cr_efdr = CR_EFDR;
1056
1057 spin_lock_init(&nvt->nvt_lock);
1058 spin_lock_init(&nvt->tx.lock);
1059
6d2f5c27
JW		 1060 pnp_set_drvdata(pdev, nvt);
1061 nvt->pdev = pdev;
1062
1063 init_waitqueue_head(&nvt->tx.queue);
1064
3f1321cb
HK		 1065 ret = nvt_hw_detect(nvt);
1066 if (ret)
1067 goto exit_free_dev_rdev;
6d2f5c27
JW		 1068
1069 /* Initialize CIR & CIR Wake Logical Devices */
1070 nvt_efm_enable(nvt);
1071 nvt_cir_ldev_init(nvt);
1072 nvt_cir_wake_ldev_init(nvt);
1073 nvt_efm_disable(nvt);
1074
ccca00d6
HK		 1075 /*
1076 * Initialize CIR & CIR Wake Config Registers
1077 * and enable logical devices
1078 */
6d2f5c27
JW		 1079 nvt_cir_regs_init(nvt);
1080 nvt_cir_wake_regs_init(nvt);
1081
d8b4b582
DH		 1082 /* Set up the rc device */
1083 rdev->priv = nvt;
1084 rdev->driver_type = RC_DRIVER_IR_RAW;
c5540fbb 1085 rdev->allowed_protocols = RC_BIT_ALL;
d8b4b582
DH		 1086 rdev->open = nvt_open;
1087 rdev->close = nvt_close;
1088 rdev->tx_ir = nvt_tx_ir;
1089 rdev->s_tx_carrier = nvt_set_tx_carrier;
1090 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
46872d27 1091 rdev->input_phys = "nuvoton/cir0";
d8b4b582
DH		 1092 rdev->input_id.bustype = BUS_HOST;
1093 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1094 rdev->input_id.product = nvt->chip_major;
1095 rdev->input_id.version = nvt->chip_minor;
46872d27 1096 rdev->dev.parent = &pdev->dev;
d8b4b582
DH		 1097 rdev->driver_name = NVT_DRIVER_NAME;
1098 rdev->map_name = RC_MAP_RC6_MCE;
d7b290a1 1099 rdev->timeout = MS_TO_NS(100);
46872d27
JW		 1100 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1101 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
6d2f5c27 1102#if 0
d8b4b582
DH		 1103 rdev->min_timeout = XYZ;
1104 rdev->max_timeout = XYZ;
6d2f5c27 1105 /* tx bits */
d8b4b582 1106 rdev->tx_resolution = XYZ;
6d2f5c27 1107#endif
d62b6818 1108 nvt->rdev = rdev;
6d2f5c27 1109
9fa35204
MK		 1110 ret = rc_register_device(rdev);
1111 if (ret)
1112 goto exit_free_dev_rdev;
1113
9ef449c6
LH		 1114 ret = -EBUSY;
1115 /* now claim resources */
099256e5 1116 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
9ef449c6 1117 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
9fa35204 1118 goto exit_unregister_device;
9ef449c6 1119
099256e5
HK		 1120 if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1121 IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt))
1122 goto exit_unregister_device;
9ef449c6 1123
099256e5 1124 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
33cb5401 1125 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
099256e5 1126 goto exit_unregister_device;
9ef449c6 1127
099256e5
HK		 1128 if (devm_request_irq(&pdev->dev, nvt->cir_wake_irq,
1129 nvt_cir_wake_isr, IRQF_SHARED,
33cb5401 1130 NVT_DRIVER_NAME "-wake", (void *)nvt))
099256e5 1131 goto exit_unregister_device;
9ef449c6 1132
46872d27 1133 device_init_wakeup(&pdev->dev, true);
d62b6818 1134
211477fe 1135 dev_notice(&pdev->dev, "driver has been successfully loaded\n");
6d2f5c27
JW		 1136 if (debug) {
1137 cir_dump_regs(nvt);
1138 cir_wake_dump_regs(nvt);
1139 }
1140
1141 return 0;
1142
9fa35204
MK		 1143exit_unregister_device:
1144 rc_unregister_device(rdev);
f73e1851 1145 rdev = NULL;
70ef6991 1146exit_free_dev_rdev:
d8b4b582 1147 rc_free_device(rdev);
6d2f5c27
JW		 1148
1149 return ret;
1150}
1151
4c62e976 1152static void nvt_remove(struct pnp_dev *pdev)
6d2f5c27
JW		 1153{
1154 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1155 unsigned long flags;
1156
1157 spin_lock_irqsave(&nvt->nvt_lock, flags);
1158 /* disable CIR */
1159 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1160 nvt_disable_cir(nvt);
b883af30
HK		 1161 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1162
6d2f5c27
JW		 1163 /* enable CIR Wake (for IR power-on) */
1164 nvt_enable_wake(nvt);
6d2f5c27 1165
d8b4b582 1166 rc_unregister_device(nvt->rdev);
6d2f5c27
JW		 1167}
1168
1169static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1170{
1171 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1172 unsigned long flags;
1173
1174 nvt_dbg("%s called", __func__);
1175
6d2f5c27
JW		 1176 spin_lock_irqsave(&nvt->tx.lock, flags);
1177 nvt->tx.tx_state = ST_TX_NONE;
1178 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1179
fb2b0065
HK		 1180 spin_lock_irqsave(&nvt->nvt_lock, flags);
1181
1182 /* zero out misc state tracking */
1183 nvt->study_state = ST_STUDY_NONE;
1184 nvt->wake_state = ST_WAKE_NONE;
1185
6d2f5c27
JW		 1186 /* disable all CIR interrupts */
1187 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1188
b883af30
HK		 1189 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1190
6d2f5c27 1191 /* disable cir logical dev */
a17ede9a 1192 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
6d2f5c27
JW		 1193
1194 /* make sure wake is enabled */
1195 nvt_enable_wake(nvt);
1196
1197 return 0;
1198}
1199
1200static int nvt_resume(struct pnp_dev *pdev)
1201{
6d2f5c27
JW		 1202 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1203
1204 nvt_dbg("%s called", __func__);
1205
6d2f5c27
JW		 1206 nvt_cir_regs_init(nvt);
1207 nvt_cir_wake_regs_init(nvt);
1208
f2747cf6 1209 return 0;
6d2f5c27
JW		 1210}
1211
1212static void nvt_shutdown(struct pnp_dev *pdev)
1213{
1214 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
fb2b0065 1215
6d2f5c27
JW		 1216 nvt_enable_wake(nvt);
1217}
1218
1219static const struct pnp_device_id nvt_ids[] = {
1220 { "WEC0530", 0 }, /* CIR */
1221 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1222 { "", 0 },
1223};
1224
1225static struct pnp_driver nvt_driver = {
1226 .name = NVT_DRIVER_NAME,
1227 .id_table = nvt_ids,
1228 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1229 .probe = nvt_probe,
4c62e976 1230 .remove = nvt_remove,
6d2f5c27
JW		 1231 .suspend = nvt_suspend,
1232 .resume = nvt_resume,
1233 .shutdown = nvt_shutdown,
1234};
1235
6d2f5c27
JW		 1236module_param(debug, int, S_IRUGO | S_IWUSR);
1237MODULE_PARM_DESC(debug, "Enable debugging output");
1238
1239MODULE_DEVICE_TABLE(pnp, nvt_ids);
1240MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1241
1242MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1243MODULE_LICENSE("GPL");
1244
af638a04 1245module_pnp_driver(nvt_driver);
Linux kernel - Deliverables
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