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[media] media: rc: nuvoton-cir: remove unneeded lock
[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
CommitLineData
6d2f5c27
JW		 1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
563cd5ce
JP		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
6d2f5c27
JW		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pnp.h>
33#include <linux/io.h>
34#include <linux/interrupt.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
6bda9644 37#include <media/rc-core.h>
6d2f5c27
JW		 38#include <linux/pci_ids.h>
39
40#include "nuvoton-cir.h"
41
6d2f5c27
JW		 42/* write val to config reg */
43static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
44{
45 outb(reg, nvt->cr_efir);
46 outb(val, nvt->cr_efdr);
47}
48
49/* read val from config reg */
50static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
51{
52 outb(reg, nvt->cr_efir);
53 return inb(nvt->cr_efdr);
54}
55
56/* update config register bit without changing other bits */
57static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
58{
59 u8 tmp = nvt_cr_read(nvt, reg) | val;
60 nvt_cr_write(nvt, tmp, reg);
61}
62
63/* clear config register bit without changing other bits */
64static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
65{
66 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
67 nvt_cr_write(nvt, tmp, reg);
68}
69
70/* enter extended function mode */
71static inline void nvt_efm_enable(struct nvt_dev *nvt)
72{
73 /* Enabling Extended Function Mode explicitly requires writing 2x */
74 outb(EFER_EFM_ENABLE, nvt->cr_efir);
75 outb(EFER_EFM_ENABLE, nvt->cr_efir);
76}
77
78/* exit extended function mode */
79static inline void nvt_efm_disable(struct nvt_dev *nvt)
80{
81 outb(EFER_EFM_DISABLE, nvt->cr_efir);
82}
83
84/*
85 * When you want to address a specific logical device, write its logical
86 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
87 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
88 */
89static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
90{
91 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
92 outb(ldev, nvt->cr_efdr);
93}
94
95/* write val to cir config register */
96static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
97{
98 outb(val, nvt->cir_addr + offset);
99}
100
101/* read val from cir config register */
102static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
103{
104 u8 val;
105
106 val = inb(nvt->cir_addr + offset);
107
108 return val;
109}
110
111/* write val to cir wake register */
112static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
113 u8 val, u8 offset)
114{
115 outb(val, nvt->cir_wake_addr + offset);
116}
117
118/* read val from cir wake config register */
119static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
120{
121 u8 val;
122
123 val = inb(nvt->cir_wake_addr + offset);
124
125 return val;
126}
127
128/* dump current cir register contents */
129static void cir_dump_regs(struct nvt_dev *nvt)
130{
131 nvt_efm_enable(nvt);
132 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
133
563cd5ce
JP		 134 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
135 pr_info(" * CR CIR ACTIVE : 0x%x\n",
136 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
137 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
138 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
6d2f5c27 139 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 140 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
141 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 142
143 nvt_efm_disable(nvt);
144
563cd5ce
JP		 145 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
146 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
147 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
148 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
149 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
150 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
151 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
152 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
153 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
154 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
155 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
156 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
157 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
158 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
159 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
160 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
161 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
6d2f5c27
JW		 162}
163
164/* dump current cir wake register contents */
165static void cir_wake_dump_regs(struct nvt_dev *nvt)
166{
167 u8 i, fifo_len;
168
169 nvt_efm_enable(nvt);
170 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
171
563cd5ce
JP		 172 pr_info("%s: Dump CIR WAKE logical device registers:\n",
173 NVT_DRIVER_NAME);
174 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
175 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
176 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
177 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
4e6e29ad 178 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 179 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
180 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 181
182 nvt_efm_disable(nvt);
183
563cd5ce
JP		 184 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
185 pr_info(" * IRCON: 0x%x\n",
186 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
187 pr_info(" * IRSTS: 0x%x\n",
188 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
189 pr_info(" * IREN: 0x%x\n",
190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
191 pr_info(" * FIFO CMP DEEP: 0x%x\n",
192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
193 pr_info(" * FIFO CMP TOL: 0x%x\n",
194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
195 pr_info(" * FIFO COUNT: 0x%x\n",
196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
197 pr_info(" * SLCH: 0x%x\n",
198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
199 pr_info(" * SLCL: 0x%x\n",
200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
201 pr_info(" * FIFOCON: 0x%x\n",
202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
203 pr_info(" * SRXFSTS: 0x%x\n",
204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
205 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
207 pr_info(" * WR FIFO DATA: 0x%x\n",
208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
209 pr_info(" * RD FIFO ONLY: 0x%x\n",
210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
211 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
213 pr_info(" * FIFO IGNORE: 0x%x\n",
214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
215 pr_info(" * IRFSM: 0x%x\n",
216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
6d2f5c27
JW		 217
218 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
563cd5ce
JP		 219 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
220 pr_info("* Contents =");
6d2f5c27 221 for (i = 0; i < fifo_len; i++)
563cd5ce
JP		 222 pr_cont(" %02x",
223 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
224 pr_cont("\n");
6d2f5c27
JW		 225}
226
227/* detect hardware features */
228static int nvt_hw_detect(struct nvt_dev *nvt)
229{
6d2f5c27 230 u8 chip_major, chip_minor;
362d3a3a
JW		 231 char chip_id[12];
232 bool chip_unknown = false;
6d2f5c27
JW		 233
234 nvt_efm_enable(nvt);
235
236 /* Check if we're wired for the alternate EFER setup */
237 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
238 if (chip_major == 0xff) {
239 nvt->cr_efir = CR_EFIR2;
240 nvt->cr_efdr = CR_EFDR2;
241 nvt_efm_enable(nvt);
242 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
243 }
244
245 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
6d2f5c27 246
362d3a3a
JW		 247 /* these are the known working chip revisions... */
248 switch (chip_major) {
249 case CHIP_ID_HIGH_667:
250 strcpy(chip_id, "w83667hg\0");
251 if (chip_minor != CHIP_ID_LOW_667)
252 chip_unknown = true;
253 break;
254 case CHIP_ID_HIGH_677B:
255 strcpy(chip_id, "w83677hg\0");
256 if (chip_minor != CHIP_ID_LOW_677B2 &&
257 chip_minor != CHIP_ID_LOW_677B3)
258 chip_unknown = true;
259 break;
260 case CHIP_ID_HIGH_677C:
261 strcpy(chip_id, "w83677hg-c\0");
262 if (chip_minor != CHIP_ID_LOW_677C)
263 chip_unknown = true;
264 break;
265 default:
266 strcpy(chip_id, "w836x7hg\0");
267 chip_unknown = true;
268 break;
5df465df 269 }
6d2f5c27 270
362d3a3a
JW		 271 /* warn, but still let the driver load, if we don't know this chip */
272 if (chip_unknown)
273 nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, "
274 "it may not work...", chip_id, chip_major, chip_minor);
275 else
276 nvt_dbg("%s: chip id: 0x%02x 0x%02x",
277 chip_id, chip_major, chip_minor);
278
6d2f5c27
JW		 279 nvt_efm_disable(nvt);
280
6d2f5c27
JW		 281 nvt->chip_major = chip_major;
282 nvt->chip_minor = chip_minor;
6d2f5c27 283
f2747cf6 284 return 0;
6d2f5c27
JW		 285}
286
287static void nvt_cir_ldev_init(struct nvt_dev *nvt)
288{
39381d4f
JW		 289 u8 val, psreg, psmask, psval;
290
291 if (nvt->chip_major == CHIP_ID_HIGH_667) {
292 psreg = CR_MULTIFUNC_PIN_SEL;
293 psmask = MULTIFUNC_PIN_SEL_MASK;
294 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
295 } else {
296 psreg = CR_OUTPUT_PIN_SEL;
297 psmask = OUTPUT_PIN_SEL_MASK;
298 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
299 }
6d2f5c27 300
39381d4f
JW		 301 /* output pin selection: enable CIR, with WB sensor enabled */
302 val = nvt_cr_read(nvt, psreg);
303 val &= psmask;
304 val |= psval;
305 nvt_cr_write(nvt, val, psreg);
6d2f5c27
JW		 306
307 /* Select CIR logical device and enable */
308 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
309 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
310
311 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
312 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
313
314 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
315
316 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
317 nvt->cir_addr, nvt->cir_irq);
318}
319
320static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
321{
322 /* Select ACPI logical device, enable it and CIR Wake */
323 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
324 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
325
326 /* Enable CIR Wake via PSOUT# (Pin60) */
327 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
328
6d2f5c27
JW		 329 /* enable pme interrupt of cir wakeup event */
330 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
331
332 /* Select CIR Wake logical device and enable */
333 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
334 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
335
336 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
337 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
338
339 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
340
341 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
342 nvt->cir_wake_addr, nvt->cir_wake_irq);
343}
344
345/* clear out the hardware's cir rx fifo */
346static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
347{
348 u8 val;
349
350 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
351 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
352}
353
354/* clear out the hardware's cir wake rx fifo */
355static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
356{
357 u8 val;
358
359 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
360 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
361 CIR_WAKE_FIFOCON);
362}
363
364/* clear out the hardware's cir tx fifo */
365static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
366{
367 u8 val;
368
369 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
370 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
371}
372
fbdc781c
JW		 373/* enable RX Trigger Level Reach and Packet End interrupts */
374static void nvt_set_cir_iren(struct nvt_dev *nvt)
375{
376 u8 iren;
377
378 iren = CIR_IREN_RTR | CIR_IREN_PE;
379 nvt_cir_reg_write(nvt, iren, CIR_IREN);
380}
381
6d2f5c27
JW		 382static void nvt_cir_regs_init(struct nvt_dev *nvt)
383{
384 /* set sample limit count (PE interrupt raised when reached) */
385 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
386 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
387
388 /* set fifo irq trigger levels */
389 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
390 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
391
392 /*
393 * Enable TX and RX, specify carrier on = low, off = high, and set
394 * sample period (currently 50us)
395 */
4e6e29ad
JW		 396 nvt_cir_reg_write(nvt,
397 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
398 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
399 CIR_IRCON);
6d2f5c27
JW		 400
401 /* clear hardware rx and tx fifos */
402 nvt_clear_cir_fifo(nvt);
403 nvt_clear_tx_fifo(nvt);
404
405 /* clear any and all stray interrupts */
406 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
407
fbdc781c
JW		 408 /* and finally, enable interrupts */
409 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 410}
411
412static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
413{
3198ed16
JW		 414 /* set number of bytes needed for wake from s3 (default 65) */
415 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
416 CIR_WAKE_FIFO_CMP_DEEP);
6d2f5c27
JW		 417
418 /* set tolerance/variance allowed per byte during wake compare */
419 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
420 CIR_WAKE_FIFO_CMP_TOL);
421
422 /* set sample limit count (PE interrupt raised when reached) */
423 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
424 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
425
426 /* set cir wake fifo rx trigger level (currently 67) */
427 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
428 CIR_WAKE_FIFOCON);
429
430 /*
431 * Enable TX and RX, specific carrier on = low, off = high, and set
432 * sample period (currently 50us)
433 */
434 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
435 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
436 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
437 CIR_WAKE_IRCON);
438
439 /* clear cir wake rx fifo */
440 nvt_clear_cir_wake_fifo(nvt);
441
442 /* clear any and all stray interrupts */
443 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
444}
445
446static void nvt_enable_wake(struct nvt_dev *nvt)
447{
448 nvt_efm_enable(nvt);
449
450 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
451 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
6d2f5c27
JW		 452 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
453
454 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
455 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
456
457 nvt_efm_disable(nvt);
458
459 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
460 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
4e6e29ad
JW		 461 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
462 CIR_WAKE_IRCON);
6d2f5c27
JW		 463 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
464 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
465}
466
230dc94a 467#if 0 /* Currently unused */
6d2f5c27
JW		 468/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
469static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
470{
471 u32 count, carrier, duration = 0;
472 int i;
473
474 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
475 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
476
477 for (i = 0; i < nvt->pkts; i++) {
478 if (nvt->buf[i] & BUF_PULSE_BIT)
479 duration += nvt->buf[i] & BUF_LEN_MASK;
480 }
481
482 duration *= SAMPLE_PERIOD;
483
484 if (!count || !duration) {
485 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
486 count, duration);
487 return 0;
488 }
489
b4608fae 490 carrier = MS_TO_NS(count) / duration;
6d2f5c27
JW		 491
492 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
493 nvt_dbg("WTF? Carrier frequency out of range!");
494
495 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
496 carrier, count, duration);
497
498 return carrier;
499}
230dc94a 500#endif
6d2f5c27
JW		 501/*
502 * set carrier frequency
503 *
504 * set carrier on 2 registers: CP & CC
505 * always set CP as 0x81
506 * set CC by SPEC, CC = 3MHz/carrier - 1
507 */
d8b4b582 508static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
6d2f5c27 509{
d8b4b582 510 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 511 u16 val;
512
48cafec9
DC		 513 if (carrier == 0)
514 return -EINVAL;
515
6d2f5c27
JW		 516 nvt_cir_reg_write(nvt, 1, CIR_CP);
517 val = 3000000 / (carrier) - 1;
518 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
519
520 nvt_dbg("cp: 0x%x cc: 0x%x\n",
521 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
522
523 return 0;
524}
525
526/*
527 * nvt_tx_ir
528 *
529 * 1) clean TX fifo first (handled by AP)
530 * 2) copy data from user space
531 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
532 * 4) send 9 packets to TX FIFO to open TTR
533 * in interrupt_handler:
534 * 5) send all data out
535 * go back to write():
536 * 6) disable TX interrupts, re-enable RX interupts
537 *
538 * The key problem of this function is user space data may larger than
539 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
540 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
541 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
542 * set TXFCONT as 0xff, until buf_count less than 0xff.
543 */
5588dc2b 544static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
6d2f5c27 545{
d8b4b582 546 struct nvt_dev *nvt = dev->priv;
6d2f5c27 547 unsigned long flags;
6d2f5c27
JW		 548 unsigned int i;
549 u8 iren;
550 int ret;
551
552 spin_lock_irqsave(&nvt->tx.lock, flags);
553
5588dc2b
DH		 554 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
555 nvt->tx.buf_count = (ret * sizeof(unsigned));
6d2f5c27
JW		 556
557 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
558
559 nvt->tx.cur_buf_num = 0;
560
561 /* save currently enabled interrupts */
562 iren = nvt_cir_reg_read(nvt, CIR_IREN);
563
564 /* now disable all interrupts, save TFU & TTR */
565 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
566
567 nvt->tx.tx_state = ST_TX_REPLY;
568
569 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
570 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
571
572 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
573 for (i = 0; i < 9; i++)
574 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
575
576 spin_unlock_irqrestore(&nvt->tx.lock, flags);
577
578 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
579
580 spin_lock_irqsave(&nvt->tx.lock, flags);
581 nvt->tx.tx_state = ST_TX_NONE;
582 spin_unlock_irqrestore(&nvt->tx.lock, flags);
583
584 /* restore enabled interrupts to prior state */
585 nvt_cir_reg_write(nvt, iren, CIR_IREN);
586
587 return ret;
588}
589
590/* dump contents of the last rx buffer we got from the hw rx fifo */
591static void nvt_dump_rx_buf(struct nvt_dev *nvt)
592{
593 int i;
594
4e6e29ad 595 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
6d2f5c27 596 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
4e6e29ad
JW		 597 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
598 printk(KERN_CONT "\n");
6d2f5c27
JW		 599}
600
601/*
602 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
603 * trigger decode when appropriate.
604 *
605 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
606 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
607 * (default 50us) intervals for that pulse/space. A discrete signal is
608 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
609 * to signal more IR coming (repeats) or end of IR, respectively. We store
610 * sample data in the raw event kfifo until we see 0x7<something> (except f)
611 * or 0x80, at which time, we trigger a decode operation.
612 */
613static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
614{
4651918a 615 DEFINE_IR_RAW_EVENT(rawir);
6d2f5c27
JW		 616 u8 sample;
617 int i;
618
619 nvt_dbg_verbose("%s firing", __func__);
620
621 if (debug)
622 nvt_dump_rx_buf(nvt);
623
de4ed0c1 624 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
6d2f5c27 625
b7582815
JW		 626 init_ir_raw_event(&rawir);
627
de4ed0c1 628 for (i = 0; i < nvt->pkts; i++) {
6d2f5c27
JW		 629 sample = nvt->buf[i];
630
631 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
b4608fae
JW		 632 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
633 * SAMPLE_PERIOD);
6d2f5c27 634
de4ed0c1
JW		 635 nvt_dbg("Storing %s with duration %d",
636 rawir.pulse ? "pulse" : "space", rawir.duration);
4651918a 637
de4ed0c1 638 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
6d2f5c27
JW		 639
640 /*
641 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
642 * indicates end of IR signal, but new data incoming. In both
643 * cases, it means we're ready to call ir_raw_event_handle
644 */
de4ed0c1 645 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
b7582815 646 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
6d2f5c27 647 ir_raw_event_handle(nvt->rdev);
b7582815 648 }
6d2f5c27
JW		 649 }
650
de4ed0c1
JW		 651 nvt->pkts = 0;
652
b7582815
JW		 653 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
654 ir_raw_event_handle(nvt->rdev);
655
6d2f5c27
JW		 656 nvt_dbg_verbose("%s done", __func__);
657}
658
fbdc781c
JW		 659static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
660{
661 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
662
663 nvt->pkts = 0;
664 nvt_clear_cir_fifo(nvt);
665 ir_raw_event_reset(nvt->rdev);
666}
667
6d2f5c27
JW		 668/* copy data from hardware rx fifo into driver buffer */
669static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
670{
671 unsigned long flags;
672 u8 fifocount, val;
673 unsigned int b_idx;
fbdc781c 674 bool overrun = false;
6d2f5c27
JW		 675 int i;
676
677 /* Get count of how many bytes to read from RX FIFO */
678 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
679 /* if we get 0xff, probably means the logical dev is disabled */
680 if (fifocount == 0xff)
681 return;
fbdc781c 682 /* watch out for a fifo overrun condition */
6d2f5c27 683 else if (fifocount > RX_BUF_LEN) {
fbdc781c
JW		 684 overrun = true;
685 fifocount = RX_BUF_LEN;
6d2f5c27
JW		 686 }
687
688 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
689
690 spin_lock_irqsave(&nvt->nvt_lock, flags);
691
692 b_idx = nvt->pkts;
693
694 /* This should never happen, but lets check anyway... */
695 if (b_idx + fifocount > RX_BUF_LEN) {
696 nvt_process_rx_ir_data(nvt);
697 b_idx = 0;
698 }
699
700 /* Read fifocount bytes from CIR Sample RX FIFO register */
701 for (i = 0; i < fifocount; i++) {
702 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
703 nvt->buf[b_idx + i] = val;
704 }
705
706 nvt->pkts += fifocount;
707 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
708
709 nvt_process_rx_ir_data(nvt);
710
fbdc781c
JW		 711 if (overrun)
712 nvt_handle_rx_fifo_overrun(nvt);
713
6d2f5c27
JW		 714 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
715}
716
717static void nvt_cir_log_irqs(u8 status, u8 iren)
718{
719 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
720 status, iren,
721 status & CIR_IRSTS_RDR ? " RDR" : "",
722 status & CIR_IRSTS_RTR ? " RTR" : "",
723 status & CIR_IRSTS_PE ? " PE" : "",
724 status & CIR_IRSTS_RFO ? " RFO" : "",
725 status & CIR_IRSTS_TE ? " TE" : "",
726 status & CIR_IRSTS_TTR ? " TTR" : "",
727 status & CIR_IRSTS_TFU ? " TFU" : "",
728 status & CIR_IRSTS_GH ? " GH" : "",
729 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
730 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
731 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
732}
733
734static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
735{
736 unsigned long flags;
737 bool tx_inactive;
738 u8 tx_state;
739
740 spin_lock_irqsave(&nvt->tx.lock, flags);
741 tx_state = nvt->tx.tx_state;
742 spin_unlock_irqrestore(&nvt->tx.lock, flags);
743
744 tx_inactive = (tx_state == ST_TX_NONE);
745
746 return tx_inactive;
747}
748
749/* interrupt service routine for incoming and outgoing CIR data */
750static irqreturn_t nvt_cir_isr(int irq, void *data)
751{
752 struct nvt_dev *nvt = data;
753 u8 status, iren, cur_state;
754 unsigned long flags;
755
756 nvt_dbg_verbose("%s firing", __func__);
757
758 nvt_efm_enable(nvt);
759 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
760 nvt_efm_disable(nvt);
761
762 /*
763 * Get IR Status register contents. Write 1 to ack/clear
764 *
765 * bit: reg name - description
766 * 7: CIR_IRSTS_RDR - RX Data Ready
767 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
768 * 5: CIR_IRSTS_PE - Packet End
769 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
770 * 3: CIR_IRSTS_TE - TX FIFO Empty
771 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
772 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
773 * 0: CIR_IRSTS_GH - Min Length Detected
774 */
775 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
776 if (!status) {
777 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
778 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
2bbf9e06 779 return IRQ_NONE;
6d2f5c27
JW		 780 }
781
782 /* ack/clear all irq flags we've got */
783 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
784 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
785
786 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
787 iren = nvt_cir_reg_read(nvt, CIR_IREN);
788 if (!iren) {
789 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
2bbf9e06 790 return IRQ_NONE;
6d2f5c27
JW		 791 }
792
793 if (debug)
794 nvt_cir_log_irqs(status, iren);
795
796 if (status & CIR_IRSTS_RTR) {
797 /* FIXME: add code for study/learn mode */
798 /* We only do rx if not tx'ing */
799 if (nvt_cir_tx_inactive(nvt))
800 nvt_get_rx_ir_data(nvt);
801 }
802
803 if (status & CIR_IRSTS_PE) {
804 if (nvt_cir_tx_inactive(nvt))
805 nvt_get_rx_ir_data(nvt);
806
807 spin_lock_irqsave(&nvt->nvt_lock, flags);
808
809 cur_state = nvt->study_state;
810
811 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
812
813 if (cur_state == ST_STUDY_NONE)
814 nvt_clear_cir_fifo(nvt);
815 }
816
817 if (status & CIR_IRSTS_TE)
818 nvt_clear_tx_fifo(nvt);
819
820 if (status & CIR_IRSTS_TTR) {
821 unsigned int pos, count;
822 u8 tmp;
823
824 spin_lock_irqsave(&nvt->tx.lock, flags);
825
826 pos = nvt->tx.cur_buf_num;
827 count = nvt->tx.buf_count;
828
829 /* Write data into the hardware tx fifo while pos < count */
830 if (pos < count) {
831 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
832 nvt->tx.cur_buf_num++;
833 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
834 } else {
835 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
836 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
837 }
838
839 spin_unlock_irqrestore(&nvt->tx.lock, flags);
840
841 }
842
843 if (status & CIR_IRSTS_TFU) {
844 spin_lock_irqsave(&nvt->tx.lock, flags);
845 if (nvt->tx.tx_state == ST_TX_REPLY) {
846 nvt->tx.tx_state = ST_TX_REQUEST;
847 wake_up(&nvt->tx.queue);
848 }
849 spin_unlock_irqrestore(&nvt->tx.lock, flags);
850 }
851
852 nvt_dbg_verbose("%s done", __func__);
2bbf9e06 853 return IRQ_HANDLED;
6d2f5c27
JW		 854}
855
856/* Interrupt service routine for CIR Wake */
857static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
858{
859 u8 status, iren, val;
860 struct nvt_dev *nvt = data;
861 unsigned long flags;
862
863 nvt_dbg_wake("%s firing", __func__);
864
865 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
866 if (!status)
2bbf9e06 867 return IRQ_NONE;
6d2f5c27
JW		 868
869 if (status & CIR_WAKE_IRSTS_IR_PENDING)
870 nvt_clear_cir_wake_fifo(nvt);
871
872 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
873 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
874
875 /* Interrupt may be shared with CIR, bail if Wake not enabled */
876 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
877 if (!iren) {
878 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
2bbf9e06 879 return IRQ_HANDLED;
6d2f5c27
JW		 880 }
881
882 if ((status & CIR_WAKE_IRSTS_PE) &&
883 (nvt->wake_state == ST_WAKE_START)) {
884 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
885 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
886 nvt_dbg("setting wake up key: 0x%x", val);
887 }
888
889 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
890 spin_lock_irqsave(&nvt->nvt_lock, flags);
891 nvt->wake_state = ST_WAKE_FINISH;
892 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
893 }
894
895 nvt_dbg_wake("%s done", __func__);
2bbf9e06 896 return IRQ_HANDLED;
6d2f5c27
JW		 897}
898
899static void nvt_enable_cir(struct nvt_dev *nvt)
900{
901 /* set function enable flags */
902 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
903 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
904 CIR_IRCON);
905
906 nvt_efm_enable(nvt);
907
908 /* enable the CIR logical device */
909 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
910 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
911
912 nvt_efm_disable(nvt);
913
914 /* clear all pending interrupts */
915 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
916
917 /* enable interrupts */
fbdc781c 918 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 919}
920
921static void nvt_disable_cir(struct nvt_dev *nvt)
922{
923 /* disable CIR interrupts */
924 nvt_cir_reg_write(nvt, 0, CIR_IREN);
925
926 /* clear any and all pending interrupts */
927 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
928
929 /* clear all function enable flags */
930 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
931
932 /* clear hardware rx and tx fifos */
933 nvt_clear_cir_fifo(nvt);
934 nvt_clear_tx_fifo(nvt);
935
936 nvt_efm_enable(nvt);
937
938 /* disable the CIR logical device */
939 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
940 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
941
942 nvt_efm_disable(nvt);
943}
944
d8b4b582 945static int nvt_open(struct rc_dev *dev)
6d2f5c27 946{
d8b4b582 947 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 948 unsigned long flags;
949
950 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 951 nvt_enable_cir(nvt);
952 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
953
954 return 0;
955}
956
d8b4b582 957static void nvt_close(struct rc_dev *dev)
6d2f5c27 958{
d8b4b582 959 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 960 unsigned long flags;
961
962 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 963 nvt_disable_cir(nvt);
964 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
965}
966
967/* Allocate memory, probe hardware, and initialize everything */
968static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
969{
d8b4b582
DH		 970 struct nvt_dev *nvt;
971 struct rc_dev *rdev;
6d2f5c27
JW		 972 int ret = -ENOMEM;
973
974 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
975 if (!nvt)
976 return ret;
977
6d2f5c27 978 /* input device for IR remote (and tx) */
d8b4b582 979 rdev = rc_allocate_device();
6d2f5c27 980 if (!rdev)
70ef6991 981 goto exit_free_dev_rdev;
6d2f5c27
JW		 982
983 ret = -ENODEV;
c3c2077d
AS		 984 /* activate pnp device */
985 if (pnp_activate_dev(pdev) < 0) {
986 dev_err(&pdev->dev, "Could not activate PNP device!\n");
987 goto exit_free_dev_rdev;
988 }
989
6d2f5c27
JW		 990 /* validate pnp resources */
991 if (!pnp_port_valid(pdev, 0) ||
992 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
993 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
70ef6991 994 goto exit_free_dev_rdev;
6d2f5c27
JW		 995 }
996
997 if (!pnp_irq_valid(pdev, 0)) {
998 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
70ef6991 999 goto exit_free_dev_rdev;
6d2f5c27
JW		 1000 }
1001
1002 if (!pnp_port_valid(pdev, 1) ||
1003 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1004 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
70ef6991 1005 goto exit_free_dev_rdev;
6d2f5c27
JW		 1006 }
1007
1008 nvt->cir_addr = pnp_port_start(pdev, 0);
1009 nvt->cir_irq = pnp_irq(pdev, 0);
1010
1011 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1012 /* irq is always shared between cir and cir wake */
1013 nvt->cir_wake_irq = nvt->cir_irq;
1014
1015 nvt->cr_efir = CR_EFIR;
1016 nvt->cr_efdr = CR_EFDR;
1017
1018 spin_lock_init(&nvt->nvt_lock);
1019 spin_lock_init(&nvt->tx.lock);
1020
6d2f5c27
JW		 1021 pnp_set_drvdata(pdev, nvt);
1022 nvt->pdev = pdev;
1023
1024 init_waitqueue_head(&nvt->tx.queue);
1025
1026 ret = nvt_hw_detect(nvt);
1027 if (ret)
70ef6991 1028 goto exit_free_dev_rdev;
6d2f5c27
JW		 1029
1030 /* Initialize CIR & CIR Wake Logical Devices */
1031 nvt_efm_enable(nvt);
1032 nvt_cir_ldev_init(nvt);
1033 nvt_cir_wake_ldev_init(nvt);
1034 nvt_efm_disable(nvt);
1035
1036 /* Initialize CIR & CIR Wake Config Registers */
1037 nvt_cir_regs_init(nvt);
1038 nvt_cir_wake_regs_init(nvt);
1039
d8b4b582
DH		 1040 /* Set up the rc device */
1041 rdev->priv = nvt;
1042 rdev->driver_type = RC_DRIVER_IR_RAW;
c5540fbb 1043 rdev->allowed_protocols = RC_BIT_ALL;
d8b4b582
DH		 1044 rdev->open = nvt_open;
1045 rdev->close = nvt_close;
1046 rdev->tx_ir = nvt_tx_ir;
1047 rdev->s_tx_carrier = nvt_set_tx_carrier;
1048 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
46872d27 1049 rdev->input_phys = "nuvoton/cir0";
d8b4b582
DH		 1050 rdev->input_id.bustype = BUS_HOST;
1051 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1052 rdev->input_id.product = nvt->chip_major;
1053 rdev->input_id.version = nvt->chip_minor;
46872d27 1054 rdev->dev.parent = &pdev->dev;
d8b4b582
DH		 1055 rdev->driver_name = NVT_DRIVER_NAME;
1056 rdev->map_name = RC_MAP_RC6_MCE;
d7b290a1 1057 rdev->timeout = MS_TO_NS(100);
46872d27
JW		 1058 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1059 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
6d2f5c27 1060#if 0
d8b4b582
DH		 1061 rdev->min_timeout = XYZ;
1062 rdev->max_timeout = XYZ;
6d2f5c27 1063 /* tx bits */
d8b4b582 1064 rdev->tx_resolution = XYZ;
6d2f5c27 1065#endif
d62b6818 1066 nvt->rdev = rdev;
6d2f5c27 1067
9fa35204
MK		 1068 ret = rc_register_device(rdev);
1069 if (ret)
1070 goto exit_free_dev_rdev;
1071
9ef449c6
LH		 1072 ret = -EBUSY;
1073 /* now claim resources */
1074 if (!request_region(nvt->cir_addr,
1075 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
9fa35204 1076 goto exit_unregister_device;
9ef449c6
LH		 1077
1078 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1079 NVT_DRIVER_NAME, (void *)nvt))
70ef6991 1080 goto exit_release_cir_addr;
9ef449c6
LH		 1081
1082 if (!request_region(nvt->cir_wake_addr,
1083 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
70ef6991 1084 goto exit_free_irq;
9ef449c6
LH		 1085
1086 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1087 NVT_DRIVER_NAME, (void *)nvt))
70ef6991 1088 goto exit_release_cir_wake_addr;
9ef449c6 1089
46872d27 1090 device_init_wakeup(&pdev->dev, true);
d62b6818 1091
6d2f5c27
JW		 1092 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1093 if (debug) {
1094 cir_dump_regs(nvt);
1095 cir_wake_dump_regs(nvt);
1096 }
1097
1098 return 0;
1099
70ef6991 1100exit_release_cir_wake_addr:
f27b853e 1101 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
70ef6991 1102exit_free_irq:
f27b853e 1103 free_irq(nvt->cir_irq, nvt);
70ef6991 1104exit_release_cir_addr:
f27b853e 1105 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
9fa35204
MK		 1106exit_unregister_device:
1107 rc_unregister_device(rdev);
f73e1851 1108 rdev = NULL;
70ef6991 1109exit_free_dev_rdev:
d8b4b582 1110 rc_free_device(rdev);
6d2f5c27
JW		 1111 kfree(nvt);
1112
1113 return ret;
1114}
1115
4c62e976 1116static void nvt_remove(struct pnp_dev *pdev)
6d2f5c27
JW		 1117{
1118 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1119 unsigned long flags;
1120
1121 spin_lock_irqsave(&nvt->nvt_lock, flags);
1122 /* disable CIR */
1123 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1124 nvt_disable_cir(nvt);
1125 /* enable CIR Wake (for IR power-on) */
1126 nvt_enable_wake(nvt);
1127 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1128
1129 /* free resources */
1130 free_irq(nvt->cir_irq, nvt);
1131 free_irq(nvt->cir_wake_irq, nvt);
1132 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1133 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1134
d8b4b582 1135 rc_unregister_device(nvt->rdev);
6d2f5c27 1136
6d2f5c27
JW		 1137 kfree(nvt);
1138}
1139
1140static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1141{
1142 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1143 unsigned long flags;
1144
1145 nvt_dbg("%s called", __func__);
1146
1147 /* zero out misc state tracking */
1148 spin_lock_irqsave(&nvt->nvt_lock, flags);
1149 nvt->study_state = ST_STUDY_NONE;
1150 nvt->wake_state = ST_WAKE_NONE;
1151 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1152
1153 spin_lock_irqsave(&nvt->tx.lock, flags);
1154 nvt->tx.tx_state = ST_TX_NONE;
1155 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1156
1157 /* disable all CIR interrupts */
1158 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1159
1160 nvt_efm_enable(nvt);
1161
1162 /* disable cir logical dev */
1163 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1164 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1165
1166 nvt_efm_disable(nvt);
1167
1168 /* make sure wake is enabled */
1169 nvt_enable_wake(nvt);
1170
1171 return 0;
1172}
1173
1174static int nvt_resume(struct pnp_dev *pdev)
1175{
6d2f5c27
JW		 1176 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1177
1178 nvt_dbg("%s called", __func__);
1179
1180 /* open interrupt */
fbdc781c 1181 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 1182
1183 /* Enable CIR logical device */
1184 nvt_efm_enable(nvt);
1185 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1186 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1187
1188 nvt_efm_disable(nvt);
1189
1190 nvt_cir_regs_init(nvt);
1191 nvt_cir_wake_regs_init(nvt);
1192
f2747cf6 1193 return 0;
6d2f5c27
JW		 1194}
1195
1196static void nvt_shutdown(struct pnp_dev *pdev)
1197{
1198 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1199 nvt_enable_wake(nvt);
1200}
1201
1202static const struct pnp_device_id nvt_ids[] = {
1203 { "WEC0530", 0 }, /* CIR */
1204 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1205 { "", 0 },
1206};
1207
1208static struct pnp_driver nvt_driver = {
1209 .name = NVT_DRIVER_NAME,
1210 .id_table = nvt_ids,
1211 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1212 .probe = nvt_probe,
4c62e976 1213 .remove = nvt_remove,
6d2f5c27
JW		 1214 .suspend = nvt_suspend,
1215 .resume = nvt_resume,
1216 .shutdown = nvt_shutdown,
1217};
1218
6d2f5c27
JW		 1219module_param(debug, int, S_IRUGO | S_IWUSR);
1220MODULE_PARM_DESC(debug, "Enable debugging output");
1221
1222MODULE_DEVICE_TABLE(pnp, nvt_ids);
1223MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1224
1225MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1226MODULE_LICENSE("GPL");
1227
af638a04 1228module_pnp_driver(nvt_driver);
Linux kernel - Deliverables
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