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[media] nuvoton-cir: remove unneeded call to nvt_set_cir_iren
[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
CommitLineData
6d2f5c27
JW		 1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
563cd5ce
JP		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
6d2f5c27
JW		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pnp.h>
33#include <linux/io.h>
34#include <linux/interrupt.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
6bda9644 37#include <media/rc-core.h>
6d2f5c27
JW		 38#include <linux/pci_ids.h>
39
40#include "nuvoton-cir.h"
41
b5cf725c
HK		 42static const struct nvt_chip nvt_chips[] = {
43 { "w83667hg", NVT_W83667HG },
44 { "NCT6775F", NVT_6775F },
45 { "NCT6776F", NVT_6776F },
d0b528d5 46 { "NCT6779D", NVT_6779D },
b5cf725c
HK		 47};
48
49static inline bool is_w83667hg(struct nvt_dev *nvt)
50{
51 return nvt->chip_ver == NVT_W83667HG;
52}
53
6d2f5c27
JW		 54/* write val to config reg */
55static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
56{
57 outb(reg, nvt->cr_efir);
58 outb(val, nvt->cr_efdr);
59}
60
61/* read val from config reg */
62static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
63{
64 outb(reg, nvt->cr_efir);
65 return inb(nvt->cr_efdr);
66}
67
68/* update config register bit without changing other bits */
69static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
70{
71 u8 tmp = nvt_cr_read(nvt, reg) | val;
72 nvt_cr_write(nvt, tmp, reg);
73}
74
75/* clear config register bit without changing other bits */
76static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
77{
78 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
79 nvt_cr_write(nvt, tmp, reg);
80}
81
82/* enter extended function mode */
3def9ad6 83static inline int nvt_efm_enable(struct nvt_dev *nvt)
6d2f5c27 84{
3def9ad6
HK		 85 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
86 return -EBUSY;
87
6d2f5c27
JW		 88 /* Enabling Extended Function Mode explicitly requires writing 2x */
89 outb(EFER_EFM_ENABLE, nvt->cr_efir);
90 outb(EFER_EFM_ENABLE, nvt->cr_efir);
3def9ad6
HK		 91
92 return 0;
6d2f5c27
JW		 93}
94
95/* exit extended function mode */
96static inline void nvt_efm_disable(struct nvt_dev *nvt)
97{
98 outb(EFER_EFM_DISABLE, nvt->cr_efir);
3def9ad6
HK		 99
100 release_region(nvt->cr_efir, 2);
6d2f5c27
JW		 101}
102
103/*
104 * When you want to address a specific logical device, write its logical
105 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
106 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
107 */
108static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
109{
7a89836e 110 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
6d2f5c27
JW		 111}
112
0890655c
HK		 113/* select and enable logical device with setting EFM mode*/
114static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
115{
116 nvt_efm_enable(nvt);
117 nvt_select_logical_dev(nvt, ldev);
118 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
119 nvt_efm_disable(nvt);
120}
121
a17ede9a
HK		 122/* select and disable logical device with setting EFM mode*/
123static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
124{
125 nvt_efm_enable(nvt);
126 nvt_select_logical_dev(nvt, ldev);
127 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
128 nvt_efm_disable(nvt);
129}
130
6d2f5c27
JW		 131/* write val to cir config register */
132static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
133{
134 outb(val, nvt->cir_addr + offset);
135}
136
137/* read val from cir config register */
138static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
139{
140 u8 val;
141
142 val = inb(nvt->cir_addr + offset);
143
144 return val;
145}
146
147/* write val to cir wake register */
148static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
149 u8 val, u8 offset)
150{
151 outb(val, nvt->cir_wake_addr + offset);
152}
153
154/* read val from cir wake config register */
155static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
156{
157 u8 val;
158
159 val = inb(nvt->cir_wake_addr + offset);
160
161 return val;
162}
163
164/* dump current cir register contents */
165static void cir_dump_regs(struct nvt_dev *nvt)
166{
167 nvt_efm_enable(nvt);
168 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
169
563cd5ce
JP		 170 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
171 pr_info(" * CR CIR ACTIVE : 0x%x\n",
172 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
173 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
174 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
6d2f5c27 175 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 176 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
177 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 178
179 nvt_efm_disable(nvt);
180
563cd5ce
JP		 181 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
182 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
183 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
184 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
185 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
186 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
187 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
188 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
189 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
190 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
191 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
192 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
193 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
194 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
195 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
196 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
197 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
6d2f5c27
JW		 198}
199
200/* dump current cir wake register contents */
201static void cir_wake_dump_regs(struct nvt_dev *nvt)
202{
203 u8 i, fifo_len;
204
205 nvt_efm_enable(nvt);
206 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
207
563cd5ce
JP		 208 pr_info("%s: Dump CIR WAKE logical device registers:\n",
209 NVT_DRIVER_NAME);
210 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
211 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
212 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
213 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
4e6e29ad 214 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
563cd5ce
JP		 215 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
216 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
6d2f5c27
JW		 217
218 nvt_efm_disable(nvt);
219
563cd5ce
JP		 220 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
221 pr_info(" * IRCON: 0x%x\n",
222 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
223 pr_info(" * IRSTS: 0x%x\n",
224 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
225 pr_info(" * IREN: 0x%x\n",
226 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
227 pr_info(" * FIFO CMP DEEP: 0x%x\n",
228 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
229 pr_info(" * FIFO CMP TOL: 0x%x\n",
230 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
231 pr_info(" * FIFO COUNT: 0x%x\n",
232 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
233 pr_info(" * SLCH: 0x%x\n",
234 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
235 pr_info(" * SLCL: 0x%x\n",
236 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
237 pr_info(" * FIFOCON: 0x%x\n",
238 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
239 pr_info(" * SRXFSTS: 0x%x\n",
240 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
241 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
242 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
243 pr_info(" * WR FIFO DATA: 0x%x\n",
244 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
245 pr_info(" * RD FIFO ONLY: 0x%x\n",
246 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
247 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
248 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
249 pr_info(" * FIFO IGNORE: 0x%x\n",
250 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
251 pr_info(" * IRFSM: 0x%x\n",
252 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
6d2f5c27
JW		 253
254 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
563cd5ce
JP		 255 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
256 pr_info("* Contents =");
6d2f5c27 257 for (i = 0; i < fifo_len; i++)
563cd5ce
JP		 258 pr_cont(" %02x",
259 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
260 pr_cont("\n");
6d2f5c27
JW		 261}
262
b5cf725c
HK		 263static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
264{
265 int i;
266
267 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
268 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
269 nvt->chip_ver = nvt_chips[i].chip_ver;
270 return nvt_chips[i].name;
271 }
272
273 return NULL;
274}
275
276
6d2f5c27 277/* detect hardware features */
6a5a3360 278static void nvt_hw_detect(struct nvt_dev *nvt)
6d2f5c27 279{
b5cf725c
HK		 280 const char *chip_name;
281 int chip_id;
6d2f5c27
JW		 282
283 nvt_efm_enable(nvt);
284
285 /* Check if we're wired for the alternate EFER setup */
b5cf725c
HK		 286 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
287 if (nvt->chip_major == 0xff) {
6d2f5c27
JW		 288 nvt->cr_efir = CR_EFIR2;
289 nvt->cr_efdr = CR_EFDR2;
290 nvt_efm_enable(nvt);
b5cf725c 291 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
6d2f5c27
JW		 292 }
293
b5cf725c
HK		 294 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
295
296 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
297 chip_name = nvt_find_chip(nvt, chip_id);
6d2f5c27 298
362d3a3a 299 /* warn, but still let the driver load, if we don't know this chip */
b5cf725c 300 if (!chip_name)
211477fe
HK		 301 dev_warn(&nvt->pdev->dev,
302 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
303 nvt->chip_major, nvt->chip_minor);
362d3a3a 304 else
af082334
HK		 305 dev_info(&nvt->pdev->dev,
306 "found %s or compatible: chip id: 0x%02x 0x%02x",
307 chip_name, nvt->chip_major, nvt->chip_minor);
362d3a3a 308
6d2f5c27 309 nvt_efm_disable(nvt);
6d2f5c27
JW		 310}
311
312static void nvt_cir_ldev_init(struct nvt_dev *nvt)
313{
39381d4f
JW		 314 u8 val, psreg, psmask, psval;
315
b5cf725c 316 if (is_w83667hg(nvt)) {
39381d4f
JW		 317 psreg = CR_MULTIFUNC_PIN_SEL;
318 psmask = MULTIFUNC_PIN_SEL_MASK;
319 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
320 } else {
321 psreg = CR_OUTPUT_PIN_SEL;
322 psmask = OUTPUT_PIN_SEL_MASK;
323 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
324 }
6d2f5c27 325
39381d4f
JW		 326 /* output pin selection: enable CIR, with WB sensor enabled */
327 val = nvt_cr_read(nvt, psreg);
328 val &= psmask;
329 val |= psval;
330 nvt_cr_write(nvt, val, psreg);
6d2f5c27 331
ccca00d6 332 /* Select CIR logical device */
6d2f5c27 333 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
6d2f5c27
JW		 334
335 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
336 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
337
338 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
339
340 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
341 nvt->cir_addr, nvt->cir_irq);
342}
343
344static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
345{
ccca00d6 346 /* Select ACPI logical device and anable it */
6d2f5c27
JW		 347 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
348 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
349
350 /* Enable CIR Wake via PSOUT# (Pin60) */
351 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
352
6d2f5c27
JW		 353 /* enable pme interrupt of cir wakeup event */
354 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
355
ccca00d6 356 /* Select CIR Wake logical device */
6d2f5c27 357 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
6d2f5c27
JW		 358
359 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
360 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
361
362 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
363
364 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
365 nvt->cir_wake_addr, nvt->cir_wake_irq);
366}
367
368/* clear out the hardware's cir rx fifo */
369static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
370{
371 u8 val;
372
373 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
374 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
375}
376
377/* clear out the hardware's cir wake rx fifo */
378static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
379{
e1a7d981
HK		 380 u8 val, config;
381
382 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
383
384 /* clearing wake fifo works in learning mode only */
385 nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
386 CIR_WAKE_IRCON);
6d2f5c27
JW		 387
388 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
389 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
390 CIR_WAKE_FIFOCON);
e1a7d981
HK		 391
392 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
6d2f5c27
JW		 393}
394
395/* clear out the hardware's cir tx fifo */
396static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
397{
398 u8 val;
399
400 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
401 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
402}
403
fbdc781c
JW		 404/* enable RX Trigger Level Reach and Packet End interrupts */
405static void nvt_set_cir_iren(struct nvt_dev *nvt)
406{
407 u8 iren;
408
409 iren = CIR_IREN_RTR | CIR_IREN_PE;
410 nvt_cir_reg_write(nvt, iren, CIR_IREN);
411}
412
6d2f5c27
JW		 413static void nvt_cir_regs_init(struct nvt_dev *nvt)
414{
415 /* set sample limit count (PE interrupt raised when reached) */
416 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
417 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
418
419 /* set fifo irq trigger levels */
420 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
421 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
422
423 /*
424 * Enable TX and RX, specify carrier on = low, off = high, and set
425 * sample period (currently 50us)
426 */
4e6e29ad
JW		 427 nvt_cir_reg_write(nvt,
428 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
429 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
430 CIR_IRCON);
6d2f5c27
JW		 431
432 /* clear hardware rx and tx fifos */
433 nvt_clear_cir_fifo(nvt);
434 nvt_clear_tx_fifo(nvt);
435
436 /* clear any and all stray interrupts */
437 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
438
fbdc781c
JW		 439 /* and finally, enable interrupts */
440 nvt_set_cir_iren(nvt);
ccca00d6
HK		 441
442 /* enable the CIR logical device */
443 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
6d2f5c27
JW		 444}
445
446static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
447{
3198ed16
JW		 448 /* set number of bytes needed for wake from s3 (default 65) */
449 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
450 CIR_WAKE_FIFO_CMP_DEEP);
6d2f5c27
JW		 451
452 /* set tolerance/variance allowed per byte during wake compare */
453 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
454 CIR_WAKE_FIFO_CMP_TOL);
455
456 /* set sample limit count (PE interrupt raised when reached) */
457 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
458 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
459
460 /* set cir wake fifo rx trigger level (currently 67) */
461 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
462 CIR_WAKE_FIFOCON);
463
464 /*
465 * Enable TX and RX, specific carrier on = low, off = high, and set
466 * sample period (currently 50us)
467 */
468 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
469 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
470 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
471 CIR_WAKE_IRCON);
472
473 /* clear cir wake rx fifo */
474 nvt_clear_cir_wake_fifo(nvt);
475
476 /* clear any and all stray interrupts */
477 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
ccca00d6
HK		 478
479 /* enable the CIR WAKE logical device */
480 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
6d2f5c27
JW		 481}
482
483static void nvt_enable_wake(struct nvt_dev *nvt)
484{
485 nvt_efm_enable(nvt);
486
487 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
488 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
6d2f5c27
JW		 489 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
490
491 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
492 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
493
494 nvt_efm_disable(nvt);
495
496 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
497 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
4e6e29ad
JW		 498 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
499 CIR_WAKE_IRCON);
6d2f5c27
JW		 500 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
501 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
502}
503
230dc94a 504#if 0 /* Currently unused */
6d2f5c27
JW		 505/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
506static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
507{
508 u32 count, carrier, duration = 0;
509 int i;
510
511 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
512 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
513
514 for (i = 0; i < nvt->pkts; i++) {
515 if (nvt->buf[i] & BUF_PULSE_BIT)
516 duration += nvt->buf[i] & BUF_LEN_MASK;
517 }
518
519 duration *= SAMPLE_PERIOD;
520
521 if (!count || !duration) {
211477fe
HK		 522 dev_notice(&nvt->pdev->dev,
523 "Unable to determine carrier! (c:%u, d:%u)",
524 count, duration);
6d2f5c27
JW		 525 return 0;
526 }
527
b4608fae 528 carrier = MS_TO_NS(count) / duration;
6d2f5c27
JW		 529
530 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
531 nvt_dbg("WTF? Carrier frequency out of range!");
532
533 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
534 carrier, count, duration);
535
536 return carrier;
537}
230dc94a 538#endif
6d2f5c27
JW		 539/*
540 * set carrier frequency
541 *
542 * set carrier on 2 registers: CP & CC
543 * always set CP as 0x81
544 * set CC by SPEC, CC = 3MHz/carrier - 1
545 */
d8b4b582 546static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
6d2f5c27 547{
d8b4b582 548 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 549 u16 val;
550
48cafec9
DC		 551 if (carrier == 0)
552 return -EINVAL;
553
6d2f5c27
JW		 554 nvt_cir_reg_write(nvt, 1, CIR_CP);
555 val = 3000000 / (carrier) - 1;
556 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
557
558 nvt_dbg("cp: 0x%x cc: 0x%x\n",
559 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
560
561 return 0;
562}
563
564/*
565 * nvt_tx_ir
566 *
567 * 1) clean TX fifo first (handled by AP)
568 * 2) copy data from user space
569 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
570 * 4) send 9 packets to TX FIFO to open TTR
571 * in interrupt_handler:
572 * 5) send all data out
573 * go back to write():
574 * 6) disable TX interrupts, re-enable RX interupts
575 *
576 * The key problem of this function is user space data may larger than
577 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
578 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
579 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
580 * set TXFCONT as 0xff, until buf_count less than 0xff.
581 */
5588dc2b 582static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
6d2f5c27 583{
d8b4b582 584 struct nvt_dev *nvt = dev->priv;
6d2f5c27 585 unsigned long flags;
6d2f5c27
JW		 586 unsigned int i;
587 u8 iren;
588 int ret;
589
590 spin_lock_irqsave(&nvt->tx.lock, flags);
591
5588dc2b
DH		 592 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
593 nvt->tx.buf_count = (ret * sizeof(unsigned));
6d2f5c27
JW		 594
595 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
596
597 nvt->tx.cur_buf_num = 0;
598
599 /* save currently enabled interrupts */
600 iren = nvt_cir_reg_read(nvt, CIR_IREN);
601
602 /* now disable all interrupts, save TFU & TTR */
603 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
604
605 nvt->tx.tx_state = ST_TX_REPLY;
606
607 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
608 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
609
610 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
611 for (i = 0; i < 9; i++)
612 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
613
614 spin_unlock_irqrestore(&nvt->tx.lock, flags);
615
616 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
617
618 spin_lock_irqsave(&nvt->tx.lock, flags);
619 nvt->tx.tx_state = ST_TX_NONE;
620 spin_unlock_irqrestore(&nvt->tx.lock, flags);
621
622 /* restore enabled interrupts to prior state */
623 nvt_cir_reg_write(nvt, iren, CIR_IREN);
624
625 return ret;
626}
627
628/* dump contents of the last rx buffer we got from the hw rx fifo */
629static void nvt_dump_rx_buf(struct nvt_dev *nvt)
630{
631 int i;
632
4e6e29ad 633 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
6d2f5c27 634 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
4e6e29ad
JW		 635 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
636 printk(KERN_CONT "\n");
6d2f5c27
JW		 637}
638
639/*
640 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
641 * trigger decode when appropriate.
642 *
643 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
644 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
645 * (default 50us) intervals for that pulse/space. A discrete signal is
646 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
647 * to signal more IR coming (repeats) or end of IR, respectively. We store
648 * sample data in the raw event kfifo until we see 0x7<something> (except f)
649 * or 0x80, at which time, we trigger a decode operation.
650 */
651static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
652{
4651918a 653 DEFINE_IR_RAW_EVENT(rawir);
6d2f5c27
JW		 654 u8 sample;
655 int i;
656
657 nvt_dbg_verbose("%s firing", __func__);
658
659 if (debug)
660 nvt_dump_rx_buf(nvt);
661
de4ed0c1 662 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
6d2f5c27 663
b7582815
JW		 664 init_ir_raw_event(&rawir);
665
de4ed0c1 666 for (i = 0; i < nvt->pkts; i++) {
6d2f5c27
JW		 667 sample = nvt->buf[i];
668
669 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
b4608fae
JW		 670 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
671 * SAMPLE_PERIOD);
6d2f5c27 672
de4ed0c1
JW		 673 nvt_dbg("Storing %s with duration %d",
674 rawir.pulse ? "pulse" : "space", rawir.duration);
4651918a 675
de4ed0c1 676 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
6d2f5c27
JW		 677
678 /*
679 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
680 * indicates end of IR signal, but new data incoming. In both
681 * cases, it means we're ready to call ir_raw_event_handle
682 */
de4ed0c1 683 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
b7582815 684 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
6d2f5c27 685 ir_raw_event_handle(nvt->rdev);
b7582815 686 }
6d2f5c27
JW		 687 }
688
de4ed0c1
JW		 689 nvt->pkts = 0;
690
b7582815
JW		 691 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
692 ir_raw_event_handle(nvt->rdev);
693
6d2f5c27
JW		 694 nvt_dbg_verbose("%s done", __func__);
695}
696
fbdc781c
JW		 697static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
698{
211477fe 699 dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!");
fbdc781c
JW		 700
701 nvt->pkts = 0;
702 nvt_clear_cir_fifo(nvt);
703 ir_raw_event_reset(nvt->rdev);
704}
705
6d2f5c27
JW		 706/* copy data from hardware rx fifo into driver buffer */
707static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
708{
709 unsigned long flags;
710 u8 fifocount, val;
711 unsigned int b_idx;
fbdc781c 712 bool overrun = false;
6d2f5c27
JW		 713 int i;
714
715 /* Get count of how many bytes to read from RX FIFO */
716 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
717 /* if we get 0xff, probably means the logical dev is disabled */
718 if (fifocount == 0xff)
719 return;
fbdc781c 720 /* watch out for a fifo overrun condition */
6d2f5c27 721 else if (fifocount > RX_BUF_LEN) {
fbdc781c
JW		 722 overrun = true;
723 fifocount = RX_BUF_LEN;
6d2f5c27
JW		 724 }
725
726 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
727
728 spin_lock_irqsave(&nvt->nvt_lock, flags);
729
730 b_idx = nvt->pkts;
731
732 /* This should never happen, but lets check anyway... */
733 if (b_idx + fifocount > RX_BUF_LEN) {
734 nvt_process_rx_ir_data(nvt);
735 b_idx = 0;
736 }
737
738 /* Read fifocount bytes from CIR Sample RX FIFO register */
739 for (i = 0; i < fifocount; i++) {
740 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
741 nvt->buf[b_idx + i] = val;
742 }
743
744 nvt->pkts += fifocount;
745 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
746
747 nvt_process_rx_ir_data(nvt);
748
fbdc781c
JW		 749 if (overrun)
750 nvt_handle_rx_fifo_overrun(nvt);
751
6d2f5c27
JW		 752 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
753}
754
755static void nvt_cir_log_irqs(u8 status, u8 iren)
756{
068fb7dd 757 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
6d2f5c27
JW		 758 status, iren,
759 status & CIR_IRSTS_RDR ? " RDR" : "",
760 status & CIR_IRSTS_RTR ? " RTR" : "",
761 status & CIR_IRSTS_PE ? " PE" : "",
762 status & CIR_IRSTS_RFO ? " RFO" : "",
763 status & CIR_IRSTS_TE ? " TE" : "",
764 status & CIR_IRSTS_TTR ? " TTR" : "",
765 status & CIR_IRSTS_TFU ? " TFU" : "",
766 status & CIR_IRSTS_GH ? " GH" : "",
767 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
768 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
769 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
770}
771
772static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
773{
774 unsigned long flags;
6d2f5c27
JW		 775 u8 tx_state;
776
777 spin_lock_irqsave(&nvt->tx.lock, flags);
778 tx_state = nvt->tx.tx_state;
779 spin_unlock_irqrestore(&nvt->tx.lock, flags);
780
1feac493 781 return tx_state == ST_TX_NONE;
6d2f5c27
JW		 782}
783
784/* interrupt service routine for incoming and outgoing CIR data */
785static irqreturn_t nvt_cir_isr(int irq, void *data)
786{
787 struct nvt_dev *nvt = data;
788 u8 status, iren, cur_state;
789 unsigned long flags;
790
791 nvt_dbg_verbose("%s firing", __func__);
792
6d2f5c27
JW		 793 /*
794 * Get IR Status register contents. Write 1 to ack/clear
795 *
796 * bit: reg name - description
797 * 7: CIR_IRSTS_RDR - RX Data Ready
798 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
799 * 5: CIR_IRSTS_PE - Packet End
800 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
801 * 3: CIR_IRSTS_TE - TX FIFO Empty
802 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
803 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
804 * 0: CIR_IRSTS_GH - Min Length Detected
805 */
806 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
807 if (!status) {
808 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
809 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
2bbf9e06 810 return IRQ_NONE;
6d2f5c27
JW		 811 }
812
813 /* ack/clear all irq flags we've got */
814 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
815 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
816
817 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
818 iren = nvt_cir_reg_read(nvt, CIR_IREN);
819 if (!iren) {
820 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
2bbf9e06 821 return IRQ_NONE;
6d2f5c27
JW		 822 }
823
068fb7dd 824 nvt_cir_log_irqs(status, iren);
6d2f5c27
JW		 825
826 if (status & CIR_IRSTS_RTR) {
827 /* FIXME: add code for study/learn mode */
828 /* We only do rx if not tx'ing */
829 if (nvt_cir_tx_inactive(nvt))
830 nvt_get_rx_ir_data(nvt);
831 }
832
833 if (status & CIR_IRSTS_PE) {
834 if (nvt_cir_tx_inactive(nvt))
835 nvt_get_rx_ir_data(nvt);
836
837 spin_lock_irqsave(&nvt->nvt_lock, flags);
838
839 cur_state = nvt->study_state;
840
841 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
842
843 if (cur_state == ST_STUDY_NONE)
844 nvt_clear_cir_fifo(nvt);
845 }
846
847 if (status & CIR_IRSTS_TE)
848 nvt_clear_tx_fifo(nvt);
849
850 if (status & CIR_IRSTS_TTR) {
851 unsigned int pos, count;
852 u8 tmp;
853
854 spin_lock_irqsave(&nvt->tx.lock, flags);
855
856 pos = nvt->tx.cur_buf_num;
857 count = nvt->tx.buf_count;
858
859 /* Write data into the hardware tx fifo while pos < count */
860 if (pos < count) {
861 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
862 nvt->tx.cur_buf_num++;
863 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
864 } else {
865 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
866 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
867 }
868
869 spin_unlock_irqrestore(&nvt->tx.lock, flags);
870
871 }
872
873 if (status & CIR_IRSTS_TFU) {
874 spin_lock_irqsave(&nvt->tx.lock, flags);
875 if (nvt->tx.tx_state == ST_TX_REPLY) {
876 nvt->tx.tx_state = ST_TX_REQUEST;
877 wake_up(&nvt->tx.queue);
878 }
879 spin_unlock_irqrestore(&nvt->tx.lock, flags);
880 }
881
882 nvt_dbg_verbose("%s done", __func__);
2bbf9e06 883 return IRQ_HANDLED;
6d2f5c27
JW		 884}
885
886/* Interrupt service routine for CIR Wake */
887static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
888{
889 u8 status, iren, val;
890 struct nvt_dev *nvt = data;
891 unsigned long flags;
892
893 nvt_dbg_wake("%s firing", __func__);
894
895 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
896 if (!status)
2bbf9e06 897 return IRQ_NONE;
6d2f5c27
JW		 898
899 if (status & CIR_WAKE_IRSTS_IR_PENDING)
900 nvt_clear_cir_wake_fifo(nvt);
901
902 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
903 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
904
905 /* Interrupt may be shared with CIR, bail if Wake not enabled */
906 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
907 if (!iren) {
908 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
2bbf9e06 909 return IRQ_HANDLED;
6d2f5c27
JW		 910 }
911
912 if ((status & CIR_WAKE_IRSTS_PE) &&
913 (nvt->wake_state == ST_WAKE_START)) {
914 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
915 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
916 nvt_dbg("setting wake up key: 0x%x", val);
917 }
918
919 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
920 spin_lock_irqsave(&nvt->nvt_lock, flags);
921 nvt->wake_state = ST_WAKE_FINISH;
922 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
923 }
924
925 nvt_dbg_wake("%s done", __func__);
2bbf9e06 926 return IRQ_HANDLED;
6d2f5c27
JW		 927}
928
929static void nvt_enable_cir(struct nvt_dev *nvt)
930{
931 /* set function enable flags */
932 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
933 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
934 CIR_IRCON);
935
6d2f5c27 936 /* enable the CIR logical device */
0890655c 937 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
6d2f5c27
JW		 938
939 /* clear all pending interrupts */
940 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
941
942 /* enable interrupts */
fbdc781c 943 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 944}
945
946static void nvt_disable_cir(struct nvt_dev *nvt)
947{
948 /* disable CIR interrupts */
949 nvt_cir_reg_write(nvt, 0, CIR_IREN);
950
951 /* clear any and all pending interrupts */
952 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
953
954 /* clear all function enable flags */
955 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
956
957 /* clear hardware rx and tx fifos */
958 nvt_clear_cir_fifo(nvt);
959 nvt_clear_tx_fifo(nvt);
960
6d2f5c27 961 /* disable the CIR logical device */
a17ede9a 962 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
6d2f5c27
JW		 963}
964
d8b4b582 965static int nvt_open(struct rc_dev *dev)
6d2f5c27 966{
d8b4b582 967 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 968 unsigned long flags;
969
970 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 971 nvt_enable_cir(nvt);
972 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
973
974 return 0;
975}
976
d8b4b582 977static void nvt_close(struct rc_dev *dev)
6d2f5c27 978{
d8b4b582 979 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 980 unsigned long flags;
981
982 spin_lock_irqsave(&nvt->nvt_lock, flags);
6d2f5c27
JW		 983 nvt_disable_cir(nvt);
984 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
985}
986
987/* Allocate memory, probe hardware, and initialize everything */
988static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
989{
d8b4b582
DH		 990 struct nvt_dev *nvt;
991 struct rc_dev *rdev;
6d2f5c27
JW		 992 int ret = -ENOMEM;
993
099256e5 994 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
6d2f5c27
JW		 995 if (!nvt)
996 return ret;
997
6d2f5c27 998 /* input device for IR remote (and tx) */
d8b4b582 999 rdev = rc_allocate_device();
6d2f5c27 1000 if (!rdev)
70ef6991 1001 goto exit_free_dev_rdev;
6d2f5c27
JW		 1002
1003 ret = -ENODEV;
c3c2077d
AS		 1004 /* activate pnp device */
1005 if (pnp_activate_dev(pdev) < 0) {
1006 dev_err(&pdev->dev, "Could not activate PNP device!\n");
1007 goto exit_free_dev_rdev;
1008 }
1009
6d2f5c27
JW		 1010 /* validate pnp resources */
1011 if (!pnp_port_valid(pdev, 0) ||
1012 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1013 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
70ef6991 1014 goto exit_free_dev_rdev;
6d2f5c27
JW		 1015 }
1016
1017 if (!pnp_irq_valid(pdev, 0)) {
1018 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
70ef6991 1019 goto exit_free_dev_rdev;
6d2f5c27
JW		 1020 }
1021
1022 if (!pnp_port_valid(pdev, 1) ||
1023 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1024 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
70ef6991 1025 goto exit_free_dev_rdev;
6d2f5c27
JW		 1026 }
1027
1028 nvt->cir_addr = pnp_port_start(pdev, 0);
1029 nvt->cir_irq = pnp_irq(pdev, 0);
1030
1031 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1032 /* irq is always shared between cir and cir wake */
1033 nvt->cir_wake_irq = nvt->cir_irq;
1034
1035 nvt->cr_efir = CR_EFIR;
1036 nvt->cr_efdr = CR_EFDR;
1037
1038 spin_lock_init(&nvt->nvt_lock);
1039 spin_lock_init(&nvt->tx.lock);
1040
6d2f5c27
JW		 1041 pnp_set_drvdata(pdev, nvt);
1042 nvt->pdev = pdev;
1043
1044 init_waitqueue_head(&nvt->tx.queue);
1045
6a5a3360 1046 nvt_hw_detect(nvt);
6d2f5c27
JW		 1047
1048 /* Initialize CIR & CIR Wake Logical Devices */
1049 nvt_efm_enable(nvt);
1050 nvt_cir_ldev_init(nvt);
1051 nvt_cir_wake_ldev_init(nvt);
1052 nvt_efm_disable(nvt);
1053
ccca00d6
HK		 1054 /*
1055 * Initialize CIR & CIR Wake Config Registers
1056 * and enable logical devices
1057 */
6d2f5c27
JW		 1058 nvt_cir_regs_init(nvt);
1059 nvt_cir_wake_regs_init(nvt);
1060
d8b4b582
DH		 1061 /* Set up the rc device */
1062 rdev->priv = nvt;
1063 rdev->driver_type = RC_DRIVER_IR_RAW;
c5540fbb 1064 rdev->allowed_protocols = RC_BIT_ALL;
d8b4b582
DH		 1065 rdev->open = nvt_open;
1066 rdev->close = nvt_close;
1067 rdev->tx_ir = nvt_tx_ir;
1068 rdev->s_tx_carrier = nvt_set_tx_carrier;
1069 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
46872d27 1070 rdev->input_phys = "nuvoton/cir0";
d8b4b582
DH		 1071 rdev->input_id.bustype = BUS_HOST;
1072 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1073 rdev->input_id.product = nvt->chip_major;
1074 rdev->input_id.version = nvt->chip_minor;
46872d27 1075 rdev->dev.parent = &pdev->dev;
d8b4b582
DH		 1076 rdev->driver_name = NVT_DRIVER_NAME;
1077 rdev->map_name = RC_MAP_RC6_MCE;
d7b290a1 1078 rdev->timeout = MS_TO_NS(100);
46872d27
JW		 1079 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1080 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
6d2f5c27 1081#if 0
d8b4b582
DH		 1082 rdev->min_timeout = XYZ;
1083 rdev->max_timeout = XYZ;
6d2f5c27 1084 /* tx bits */
d8b4b582 1085 rdev->tx_resolution = XYZ;
6d2f5c27 1086#endif
d62b6818 1087 nvt->rdev = rdev;
6d2f5c27 1088
9fa35204
MK		 1089 ret = rc_register_device(rdev);
1090 if (ret)
1091 goto exit_free_dev_rdev;
1092
9ef449c6
LH		 1093 ret = -EBUSY;
1094 /* now claim resources */
099256e5 1095 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
9ef449c6 1096 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
9fa35204 1097 goto exit_unregister_device;
9ef449c6 1098
099256e5
HK		 1099 if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1100 IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt))
1101 goto exit_unregister_device;
9ef449c6 1102
099256e5 1103 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
33cb5401 1104 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
099256e5 1105 goto exit_unregister_device;
9ef449c6 1106
099256e5
HK		 1107 if (devm_request_irq(&pdev->dev, nvt->cir_wake_irq,
1108 nvt_cir_wake_isr, IRQF_SHARED,
33cb5401 1109 NVT_DRIVER_NAME "-wake", (void *)nvt))
099256e5 1110 goto exit_unregister_device;
9ef449c6 1111
46872d27 1112 device_init_wakeup(&pdev->dev, true);
d62b6818 1113
211477fe 1114 dev_notice(&pdev->dev, "driver has been successfully loaded\n");
6d2f5c27
JW		 1115 if (debug) {
1116 cir_dump_regs(nvt);
1117 cir_wake_dump_regs(nvt);
1118 }
1119
1120 return 0;
1121
9fa35204
MK		 1122exit_unregister_device:
1123 rc_unregister_device(rdev);
f73e1851 1124 rdev = NULL;
70ef6991 1125exit_free_dev_rdev:
d8b4b582 1126 rc_free_device(rdev);
6d2f5c27
JW		 1127
1128 return ret;
1129}
1130
4c62e976 1131static void nvt_remove(struct pnp_dev *pdev)
6d2f5c27
JW		 1132{
1133 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1134 unsigned long flags;
1135
1136 spin_lock_irqsave(&nvt->nvt_lock, flags);
1137 /* disable CIR */
1138 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1139 nvt_disable_cir(nvt);
1140 /* enable CIR Wake (for IR power-on) */
1141 nvt_enable_wake(nvt);
1142 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1143
d8b4b582 1144 rc_unregister_device(nvt->rdev);
6d2f5c27
JW		 1145}
1146
1147static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1148{
1149 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1150 unsigned long flags;
1151
1152 nvt_dbg("%s called", __func__);
1153
1154 /* zero out misc state tracking */
1155 spin_lock_irqsave(&nvt->nvt_lock, flags);
1156 nvt->study_state = ST_STUDY_NONE;
1157 nvt->wake_state = ST_WAKE_NONE;
1158 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1159
1160 spin_lock_irqsave(&nvt->tx.lock, flags);
1161 nvt->tx.tx_state = ST_TX_NONE;
1162 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1163
1164 /* disable all CIR interrupts */
1165 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1166
6d2f5c27 1167 /* disable cir logical dev */
a17ede9a 1168 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
6d2f5c27
JW		 1169
1170 /* make sure wake is enabled */
1171 nvt_enable_wake(nvt);
1172
1173 return 0;
1174}
1175
1176static int nvt_resume(struct pnp_dev *pdev)
1177{
6d2f5c27
JW		 1178 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1179
1180 nvt_dbg("%s called", __func__);
1181
6d2f5c27
JW		 1182 nvt_cir_regs_init(nvt);
1183 nvt_cir_wake_regs_init(nvt);
1184
f2747cf6 1185 return 0;
6d2f5c27
JW		 1186}
1187
1188static void nvt_shutdown(struct pnp_dev *pdev)
1189{
1190 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1191 nvt_enable_wake(nvt);
1192}
1193
1194static const struct pnp_device_id nvt_ids[] = {
1195 { "WEC0530", 0 }, /* CIR */
1196 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1197 { "", 0 },
1198};
1199
1200static struct pnp_driver nvt_driver = {
1201 .name = NVT_DRIVER_NAME,
1202 .id_table = nvt_ids,
1203 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1204 .probe = nvt_probe,
4c62e976 1205 .remove = nvt_remove,
6d2f5c27
JW		 1206 .suspend = nvt_suspend,
1207 .resume = nvt_resume,
1208 .shutdown = nvt_shutdown,
1209};
1210
6d2f5c27
JW		 1211module_param(debug, int, S_IRUGO | S_IWUSR);
1212MODULE_PARM_DESC(debug, "Enable debugging output");
1213
1214MODULE_DEVICE_TABLE(pnp, nvt_ids);
1215MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1216
1217MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1218MODULE_LICENSE("GPL");
1219
af638a04 1220module_pnp_driver(nvt_driver);
Linux kernel - Deliverables
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