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Merge remote-tracking branch 'regulator/for-next'
[deliverable/linux.git] / drivers / media / usb / cx231xx / cx231xx-avcore.c
CommitLineData
e0d3bafd 1/*
cde4362f
MCC		 2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
e0d3bafd
SD		 4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
589dadf2 25#include "cx231xx.h"
e0d3bafd
SD		 26#include <linux/init.h>
27#include <linux/list.h>
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/bitmap.h>
e0d3bafd 31#include <linux/i2c.h>
e0d3bafd
SD		 32#include <linux/mm.h>
33#include <linux/mutex.h>
64fbf444 34#include <media/tuner.h>
e0d3bafd
SD		 35
36#include <media/v4l2-common.h>
37#include <media/v4l2-ioctl.h>
e0d3bafd 38
64fbf444 39#include "cx231xx-dif.h"
e0d3bafd 40
64fbf444 41#define TUNER_MODE_FM_RADIO 0
cde4362f 42/******************************************************************************
ecc67d10
SD		 43 -: BLOCK ARRANGEMENT :-
44 I2S block ----------------------|
45 [I2S audio] |
46 |
47 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
48 [video & audio] | [Audio]
49 |
50 |-> Cx25840 --> Video
51 [Video]
52
53*******************************************************************************/
64fbf444
PB		 54/******************************************************************************
55 * VERVE REGISTER *
955e6ed8 56 * *
64fbf444
PB		 57 ******************************************************************************/
58static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
59{
60 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
61 saddr, 1, data, 1);
62}
63
64static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
65{
66 int status;
67 u32 temp = 0;
68
69 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
70 saddr, 1, &temp, 1);
71 *data = (u8) temp;
72 return status;
73}
74void initGPIO(struct cx231xx *dev)
75{
76 u32 _gpio_direction = 0;
77 u32 value = 0;
78 u8 val = 0;
79
80 _gpio_direction = _gpio_direction & 0xFC0003FF;
81 _gpio_direction = _gpio_direction | 0x03FDFC00;
82 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
83
84 verve_read_byte(dev, 0x07, &val);
336fea92 85 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val);
64fbf444
PB		 86 verve_write_byte(dev, 0x07, 0xF4);
87 verve_read_byte(dev, 0x07, &val);
336fea92 88 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val);
64fbf444 89
460a4de7 90 cx231xx_capture_start(dev, 1, Vbi);
64fbf444
PB		 91
92 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
93 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
94
95}
96void uninitGPIO(struct cx231xx *dev)
97{
98 u8 value[4] = { 0, 0, 0, 0 };
99
460a4de7 100 cx231xx_capture_start(dev, 0, Vbi);
64fbf444
PB		 101 verve_write_byte(dev, 0x07, 0x14);
102 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
103 0x68, value, 4);
104}
ecc67d10
SD		 105
106/******************************************************************************
107 * A F E - B L O C K C O N T R O L functions *
108 * [ANALOG FRONT END] *
6e4f574b 109 ******************************************************************************/
ecc67d10
SD		 110static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
111{
112 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
113 saddr, 2, data, 1);
114}
115
116static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
117{
118 int status;
119 u32 temp = 0;
120
121 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
122 saddr, 2, &temp, 1);
123 *data = (u8) temp;
124 return status;
125}
126
127int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
e0d3bafd 128{
84b5dbf3
MCC		 129 int status = 0;
130 u8 temp = 0;
ecc67d10 131 u8 afe_power_status = 0;
84b5dbf3
MCC		 132 int i = 0;
133
134 /* super block initialize */
135 temp = (u8) (ref_count & 0xff);
ecc67d10 136 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
6e4f574b
SD		 137 if (status < 0)
138 return status;
84b5dbf3 139
ecc67d10 140 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
6e4f574b
SD		 141 if (status < 0)
142 return status;
84b5dbf3
MCC		 143
144 temp = (u8) ((ref_count & 0x300) >> 8);
145 temp |= 0x40;
ecc67d10 146 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
6e4f574b
SD		 147 if (status < 0)
148 return status;
149
ecc67d10 150 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
6e4f574b
SD		 151 if (status < 0)
152 return status;
84b5dbf3
MCC		 153
154 /* enable pll */
ecc67d10
SD		 155 while (afe_power_status != 0x18) {
156 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
6e4f574b 157 if (status < 0) {
336fea92 158 dev_dbg(dev->dev,
b7085c08 159 "%s: Init Super Block failed in send cmd\n",
ed0e3729 160 __func__);
6e4f574b
SD		 161 break;
162 }
163
ecc67d10
SD		 164 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
165 afe_power_status &= 0xff;
84b5dbf3 166 if (status < 0) {
336fea92 167 dev_dbg(dev->dev,
b7085c08 168 "%s: Init Super Block failed in receive cmd\n",
ed0e3729 169 __func__);
84b5dbf3
MCC		 170 break;
171 }
172 i++;
173 if (i == 10) {
336fea92 174 dev_dbg(dev->dev,
b7085c08 175 "%s: Init Super Block force break in loop !!!!\n",
ed0e3729 176 __func__);
84b5dbf3
MCC		 177 status = -1;
178 break;
179 }
180 }
181
182 if (status < 0)
183 return status;
184
185 /* start tuning filter */
ecc67d10 186 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
6e4f574b
SD		 187 if (status < 0)
188 return status;
189
84b5dbf3
MCC		 190 msleep(5);
191
192 /* exit tuning */
ecc67d10 193 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
84b5dbf3
MCC		 194
195 return status;
e0d3bafd
SD		 196}
197
ecc67d10 198int cx231xx_afe_init_channels(struct cx231xx *dev)
e0d3bafd 199{
84b5dbf3
MCC		 200 int status = 0;
201
202 /* power up all 3 channels, clear pd_buffer */
ecc67d10
SD		 203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
205 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
84b5dbf3
MCC		 206
207 /* Enable quantizer calibration */
ecc67d10 208 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
84b5dbf3
MCC		 209
210 /* channel initialize, force modulator (fb) reset */
ecc67d10
SD		 211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
213 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
84b5dbf3
MCC		 214
215 /* start quantilizer calibration */
ecc67d10
SD		 216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
218 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
84b5dbf3
MCC		 219 msleep(5);
220
221 /* exit modulator (fb) reset */
ecc67d10
SD		 222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
224 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
84b5dbf3
MCC		 225
226 /* enable the pre_clamp in each channel for single-ended input */
ecc67d10
SD		 227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
229 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
84b5dbf3
MCC		 230
231 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
ecc67d10 232 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
84b5dbf3 233 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
ecc67d10 234 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
84b5dbf3 235 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
ecc67d10 236 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
84b5dbf3
MCC		 237 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
238
239 /* dynamic element matching off */
ecc67d10
SD		 240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
242 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
84b5dbf3
MCC		 243
244 return status;
e0d3bafd
SD		 245}
246
ecc67d10 247int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
e0d3bafd 248{
ecc67d10 249 u8 c_value = 0;
84b5dbf3 250 int status = 0;
e0d3bafd 251
ecc67d10 252 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
84b5dbf3 253 c_value &= (~(0x50));
ecc67d10 254 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
e0d3bafd 255
84b5dbf3 256 return status;
e0d3bafd
SD		 257}
258
259/*
6e4f574b
SD		 260 The Analog Front End in Cx231xx has 3 channels. These
261 channels are used to share between different inputs
262 like tuner, s-video and composite inputs.
263
e0d3bafd
SD		 264 channel 1 ----- pin 1 to pin4(in reg is 1-4)
265 channel 2 ----- pin 5 to pin8(in reg is 5-8)
266 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
267*/
ecc67d10 268int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
e0d3bafd 269{
84b5dbf3
MCC		 270 u8 ch1_setting = (u8) input_mux;
271 u8 ch2_setting = (u8) (input_mux >> 8);
272 u8 ch3_setting = (u8) (input_mux >> 16);
273 int status = 0;
ecc67d10 274 u8 value = 0;
84b5dbf3
MCC		 275
276 if (ch1_setting != 0) {
ecc67d10 277 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
5f63306d 278 value &= ~INPUT_SEL_MASK;
84b5dbf3
MCC		 279 value |= (ch1_setting - 1) << 4;
280 value &= 0xff;
ecc67d10 281 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
84b5dbf3
MCC		 282 }
283
284 if (ch2_setting != 0) {
ecc67d10 285 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
5f63306d 286 value &= ~INPUT_SEL_MASK;
84b5dbf3
MCC		 287 value |= (ch2_setting - 1) << 4;
288 value &= 0xff;
ecc67d10 289 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
84b5dbf3
MCC		 290 }
291
cde4362f
MCC		 292 /* For ch3_setting, the value to put in the register is
293 7 less than the input number */
84b5dbf3 294 if (ch3_setting != 0) {
ecc67d10 295 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
5f63306d 296 value &= ~INPUT_SEL_MASK;
84b5dbf3
MCC		 297 value |= (ch3_setting - 1) << 4;
298 value &= 0xff;
ecc67d10 299 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
84b5dbf3
MCC		 300 }
301
302 return status;
e0d3bafd
SD		 303}
304
ecc67d10 305int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
e0d3bafd 306{
84b5dbf3
MCC		 307 int status = 0;
308
6e4f574b
SD		 309 /*
310 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
311 * Currently, only baseband works.
312 */
313
84b5dbf3
MCC		 314 switch (mode) {
315 case AFE_MODE_LOW_IF:
64fbf444 316 cx231xx_Setup_AFE_for_LowIF(dev);
84b5dbf3
MCC		 317 break;
318 case AFE_MODE_BASEBAND:
ecc67d10 319 status = cx231xx_afe_setup_AFE_for_baseband(dev);
84b5dbf3
MCC		 320 break;
321 case AFE_MODE_EU_HI_IF:
322 /* SetupAFEforEuHiIF(); */
323 break;
324 case AFE_MODE_US_HI_IF:
325 /* SetupAFEforUsHiIF(); */
326 break;
327 case AFE_MODE_JAPAN_HI_IF:
328 /* SetupAFEforJapanHiIF(); */
329 break;
330 }
331
ecc67d10 332 if ((mode != dev->afe_mode) &&
b9255176 333 (dev->video_input == CX231XX_VMUX_TELEVISION))
ecc67d10 334 status = cx231xx_afe_adjust_ref_count(dev,
84b5dbf3 335 CX231XX_VMUX_TELEVISION);
84b5dbf3 336
ecc67d10 337 dev->afe_mode = mode;
84b5dbf3
MCC		 338
339 return status;
e0d3bafd
SD		 340}
341
ecc67d10 342int cx231xx_afe_update_power_control(struct cx231xx *dev,
6e4f574b 343 enum AV_MODE avmode)
e0d3bafd 344{
ecc67d10 345 u8 afe_power_status = 0;
84b5dbf3
MCC		 346 int status = 0;
347
348 switch (dev->model) {
64fbf444 349 case CX231XX_BOARD_CNXT_CARRAERA:
84b5dbf3 350 case CX231XX_BOARD_CNXT_RDE_250:
64fbf444 351 case CX231XX_BOARD_CNXT_SHELBY:
84b5dbf3 352 case CX231XX_BOARD_CNXT_RDU_250:
64fbf444
PB		 353 case CX231XX_BOARD_CNXT_RDE_253S:
354 case CX231XX_BOARD_CNXT_RDU_253S:
355 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1a50fdde 356 case CX231XX_BOARD_HAUPPAUGE_EXETER:
dd2e7dd2 357 case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx:
4270c3ca 358 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
9417bc6d 359 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
de8ae0d5
PM		 360 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
361 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
3ead1ba3 362 case CX231XX_BOARD_OTG102:
84b5dbf3 363 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
ecc67d10 364 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
6e4f574b 365 FLD_PWRDN_ENABLE_PLL)) {
ecc67d10 366 status = afe_write_byte(dev, SUP_BLK_PWRDN,
6e4f574b 367 FLD_PWRDN_TUNING_BIAS |
ecc67d10
SD		 368 FLD_PWRDN_ENABLE_PLL);
369 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
370 &afe_power_status);
84b5dbf3
MCC		 371 if (status < 0)
372 break;
373 }
374
ecc67d10
SD		 375 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
376 0x00);
377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
378 0x00);
379 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
380 0x00);
84b5dbf3 381 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
ecc67d10
SD		 382 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
383 0x70);
384 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
385 0x70);
386 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
387 0x70);
388
389 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
390 &afe_power_status);
391 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
6e4f574b
SD		 392 FLD_PWRDN_PD_BIAS |
393 FLD_PWRDN_PD_TUNECK;
ecc67d10
SD		 394 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
395 afe_power_status);
84b5dbf3 396 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
ecc67d10 397 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
6e4f574b 398 FLD_PWRDN_ENABLE_PLL)) {
ecc67d10 399 status = afe_write_byte(dev, SUP_BLK_PWRDN,
6e4f574b 400 FLD_PWRDN_TUNING_BIAS |
ecc67d10
SD		 401 FLD_PWRDN_ENABLE_PLL);
402 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
403 &afe_power_status);
84b5dbf3
MCC		 404 if (status < 0)
405 break;
406 }
407
ecc67d10
SD		 408 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
409 0x00);
410 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
411 0x00);
412 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
413 0x00);
84b5dbf3 414 } else {
336fea92 415 dev_dbg(dev->dev, "Invalid AV mode input\n");
84b5dbf3
MCC		 416 status = -1;
417 }
418 break;
419 default:
420 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
ecc67d10 421 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
6e4f574b 422 FLD_PWRDN_ENABLE_PLL)) {
ecc67d10 423 status = afe_write_byte(dev, SUP_BLK_PWRDN,
6e4f574b 424 FLD_PWRDN_TUNING_BIAS |
ecc67d10
SD		 425 FLD_PWRDN_ENABLE_PLL);
426 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
427 &afe_power_status);
84b5dbf3
MCC		 428 if (status < 0)
429 break;
430 }
431
ecc67d10
SD		 432 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
433 0x40);
434 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
435 0x40);
436 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
437 0x00);
84b5dbf3 438 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
ecc67d10
SD		 439 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
440 0x70);
441 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
442 0x70);
443 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
444 0x70);
445
446 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
447 &afe_power_status);
448 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
6e4f574b
SD		 449 FLD_PWRDN_PD_BIAS |
450 FLD_PWRDN_PD_TUNECK;
ecc67d10
SD		 451 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
452 afe_power_status);
84b5dbf3 453 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
ecc67d10 454 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
6e4f574b 455 FLD_PWRDN_ENABLE_PLL)) {
ecc67d10 456 status = afe_write_byte(dev, SUP_BLK_PWRDN,
6e4f574b 457 FLD_PWRDN_TUNING_BIAS |
ecc67d10
SD		 458 FLD_PWRDN_ENABLE_PLL);
459 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
460 &afe_power_status);
84b5dbf3
MCC		 461 if (status < 0)
462 break;
463 }
464
ecc67d10
SD		 465 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
466 0x00);
467 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
468 0x00);
469 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
470 0x40);
84b5dbf3 471 } else {
336fea92 472 dev_dbg(dev->dev, "Invalid AV mode input\n");
84b5dbf3
MCC		 473 status = -1;
474 }
475 } /* switch */
476
477 return status;
e0d3bafd
SD		 478}
479
ecc67d10 480int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
e0d3bafd 481{
ecc67d10
SD		 482 u8 input_mode = 0;
483 u8 ntf_mode = 0;
84b5dbf3
MCC		 484 int status = 0;
485
486 dev->video_input = video_input;
487
488 if (video_input == CX231XX_VMUX_TELEVISION) {
ecc67d10
SD		 489 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
490 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
491 &ntf_mode);
84b5dbf3 492 } else {
ecc67d10
SD		 493 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
494 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
495 &ntf_mode);
84b5dbf3 496 }
e0d3bafd 497
84b5dbf3
MCC		 498 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
499
500 switch (input_mode) {
501 case SINGLE_ENDED:
ecc67d10 502 dev->afe_ref_count = 0x23C;
84b5dbf3
MCC		 503 break;
504 case LOW_IF:
ecc67d10 505 dev->afe_ref_count = 0x24C;
84b5dbf3
MCC		 506 break;
507 case EU_IF:
ecc67d10 508 dev->afe_ref_count = 0x258;
84b5dbf3
MCC		 509 break;
510 case US_IF:
ecc67d10 511 dev->afe_ref_count = 0x260;
84b5dbf3
MCC		 512 break;
513 default:
514 break;
515 }
516
ecc67d10 517 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
e0d3bafd 518
84b5dbf3
MCC		 519 return status;
520}
e0d3bafd 521
cde4362f
MCC		 522/******************************************************************************
523 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
6e4f574b 524 ******************************************************************************/
ecc67d10
SD		 525static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
526{
527 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
528 saddr, 2, data, 1);
529}
530
531static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
532{
533 int status;
534 u32 temp = 0;
535
536 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
537 saddr, 2, &temp, 1);
538 *data = (u8) temp;
539 return status;
540}
541
542static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
543{
544 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
545 saddr, 2, data, 4);
546}
547
548static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
549{
550 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
551 saddr, 2, data, 4);
552}
64fbf444
PB		 553int cx231xx_check_fw(struct cx231xx *dev)
554{
555 u8 temp = 0;
556 int status = 0;
557 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
558 if (status < 0)
559 return status;
560 else
561 return temp;
562
563}
ecc67d10 564
e0d3bafd
SD		 565int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
566{
84b5dbf3
MCC		 567 int status = 0;
568
569 switch (INPUT(input)->type) {
570 case CX231XX_VMUX_COMPOSITE1:
571 case CX231XX_VMUX_SVIDEO:
572 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
573 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
cde4362f
MCC		 574 /* External AV */
575 status = cx231xx_set_power_mode(dev,
576 POLARIS_AVMODE_ENXTERNAL_AV);
84b5dbf3 577 if (status < 0) {
336fea92 578 dev_err(dev->dev,
b7085c08
MCC		 579 "%s: Failed to set Power - errCode [%d]!\n",
580 __func__, status);
84b5dbf3
MCC		 581 return status;
582 }
583 }
cde4362f
MCC		 584 status = cx231xx_set_decoder_video_input(dev,
585 INPUT(input)->type,
586 INPUT(input)->vmux);
84b5dbf3
MCC		 587 break;
588 case CX231XX_VMUX_TELEVISION:
589 case CX231XX_VMUX_CABLE:
590 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
591 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
cde4362f
MCC		 592 /* Tuner */
593 status = cx231xx_set_power_mode(dev,
594 POLARIS_AVMODE_ANALOGT_TV);
84b5dbf3 595 if (status < 0) {
336fea92 596 dev_err(dev->dev,
b7085c08 597 "%s: Failed to set Power - errCode [%d]!\n",
b9255176 598 __func__, status);
84b5dbf3
MCC		 599 return status;
600 }
601 }
64fbf444
PB		 602 if (dev->tuner_type == TUNER_NXP_TDA18271)
603 status = cx231xx_set_decoder_video_input(dev,
604 CX231XX_VMUX_TELEVISION,
605 INPUT(input)->vmux);
606 else
607 status = cx231xx_set_decoder_video_input(dev,
cde4362f
MCC		 608 CX231XX_VMUX_COMPOSITE1,
609 INPUT(input)->vmux);
64fbf444 610
84b5dbf3
MCC		 611 break;
612 default:
336fea92 613 dev_err(dev->dev, "%s: Unknown Input %d !\n",
b7085c08 614 __func__, INPUT(input)->type);
84b5dbf3
MCC		 615 break;
616 }
617
618 /* save the selection */
619 dev->video_input = input;
620
621 return status;
e0d3bafd
SD		 622}
623
b9255176
SD		 624int cx231xx_set_decoder_video_input(struct cx231xx *dev,
625 u8 pin_type, u8 input)
e0d3bafd 626{
84b5dbf3
MCC		 627 int status = 0;
628 u32 value = 0;
629
630 if (pin_type != dev->video_input) {
ecc67d10 631 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
84b5dbf3 632 if (status < 0) {
336fea92 633 dev_err(dev->dev,
b7085c08 634 "%s: adjust_ref_count :Failed to set AFE input mux - errCode [%d]!\n",
b9255176 635 __func__, status);
84b5dbf3
MCC		 636 return status;
637 }
638 }
e0d3bafd 639
ecc67d10
SD		 640 /* call afe block to set video inputs */
641 status = cx231xx_afe_set_input_mux(dev, input);
84b5dbf3 642 if (status < 0) {
336fea92 643 dev_err(dev->dev,
b7085c08 644 "%s: set_input_mux :Failed to set AFE input mux - errCode [%d]!\n",
ed0e3729 645 __func__, status);
84b5dbf3
MCC		 646 return status;
647 }
648
649 switch (pin_type) {
650 case CX231XX_VMUX_COMPOSITE1:
ecc67d10 651 status = vid_blk_read_word(dev, AFE_CTRL, &value);
cde4362f
MCC		 652 value |= (0 << 13) | (1 << 4);
653 value &= ~(1 << 5);
654
b9255176
SD		 655 /* set [24:23] [22:15] to 0 */
656 value &= (~(0x1ff8000));
657 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
658 value |= 0x1000000;
ecc67d10 659 status = vid_blk_write_word(dev, AFE_CTRL, value);
cde4362f 660
ecc67d10 661 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
cde4362f 662 value |= (1 << 7);
ecc67d10 663 status = vid_blk_write_word(dev, OUT_CTRL1, value);
cde4362f 664
88806218 665 /* Set output mode */
cde4362f 666 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 667 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 668 OUT_CTRL1,
669 FLD_OUT_MODE,
88806218 670 dev->board.output_mode);
cde4362f
MCC		 671
672 /* Tell DIF object to go to baseband mode */
673 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
674 if (status < 0) {
336fea92 675 dev_err(dev->dev,
b7085c08 676 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
cde4362f
MCC		 677 __func__, status);
678 return status;
679 }
680
681 /* Read the DFE_CTRL1 register */
ecc67d10 682 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
cde4362f
MCC		 683
684 /* enable the VBI_GATE_EN */
685 value |= FLD_VBI_GATE_EN;
686
687 /* Enable the auto-VGA enable */
688 value |= FLD_VGA_AUTO_EN;
689
690 /* Write it back */
ecc67d10 691 status = vid_blk_write_word(dev, DFE_CTRL1, value);
cde4362f
MCC		 692
693 /* Disable auto config of registers */
694 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 695 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 696 MODE_CTRL, FLD_ACFG_DIS,
697 cx231xx_set_field(FLD_ACFG_DIS, 1));
698
699 /* Set CVBS input mode */
700 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 701 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 702 MODE_CTRL, FLD_INPUT_MODE,
703 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
704 break;
705 case CX231XX_VMUX_SVIDEO:
706 /* Disable the use of DIF */
707
ecc67d10 708 status = vid_blk_read_word(dev, AFE_CTRL, &value);
cde4362f 709
b9255176
SD		 710 /* set [24:23] [22:15] to 0 */
711 value &= (~(0x1ff8000));
712 /* set FUNC_MODE[24:23] = 2
713 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
714 value |= 0x1000010;
ecc67d10 715 status = vid_blk_write_word(dev, AFE_CTRL, value);
cde4362f
MCC		 716
717 /* Tell DIF object to go to baseband mode */
718 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
719 if (status < 0) {
336fea92 720 dev_err(dev->dev,
b7085c08 721 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
cde4362f
MCC		 722 __func__, status);
723 return status;
724 }
725
726 /* Read the DFE_CTRL1 register */
ecc67d10 727 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
cde4362f
MCC		 728
729 /* enable the VBI_GATE_EN */
730 value |= FLD_VBI_GATE_EN;
731
732 /* Enable the auto-VGA enable */
733 value |= FLD_VGA_AUTO_EN;
734
735 /* Write it back */
ecc67d10 736 status = vid_blk_write_word(dev, DFE_CTRL1, value);
cde4362f
MCC		 737
738 /* Disable auto config of registers */
739 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 740 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 741 MODE_CTRL, FLD_ACFG_DIS,
742 cx231xx_set_field(FLD_ACFG_DIS, 1));
743
744 /* Set YC input mode */
745 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 746 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 747 MODE_CTRL,
748 FLD_INPUT_MODE,
749 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
750
751 /* Chroma to ADC2 */
ecc67d10 752 status = vid_blk_read_word(dev, AFE_CTRL, &value);
cde4362f
MCC		 753 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
754
755 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
756 This sets them to use video
757 rather than audio. Only one of the two will be in use. */
758 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
759
ecc67d10 760 status = vid_blk_write_word(dev, AFE_CTRL, value);
cde4362f 761
ecc67d10 762 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
cde4362f
MCC		 763 break;
764 case CX231XX_VMUX_TELEVISION:
765 case CX231XX_VMUX_CABLE:
766 default:
2f861387
MCC		 767 /* TODO: Test if this is also needed for xc2028/xc3028 */
768 if (dev->board.tuner_type == TUNER_XC5000) {
cde4362f
MCC		 769 /* Disable the use of DIF */
770
ecc67d10 771 status = vid_blk_read_word(dev, AFE_CTRL, &value);
84b5dbf3
MCC		 772 value |= (0 << 13) | (1 << 4);
773 value &= ~(1 << 5);
774
b9255176
SD		 775 /* set [24:23] [22:15] to 0 */
776 value &= (~(0x1FF8000));
777 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
778 value |= 0x1000000;
ecc67d10
SD		 779 status = vid_blk_write_word(dev, AFE_CTRL, value);
780
781 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
84b5dbf3 782 value |= (1 << 7);
ecc67d10 783 status = vid_blk_write_word(dev, OUT_CTRL1, value);
84b5dbf3 784
88806218 785 /* Set output mode */
cde4362f 786 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 787 VID_BLK_I2C_ADDRESS,
cde4362f 788 OUT_CTRL1, FLD_OUT_MODE,
88806218 789 dev->board.output_mode);
84b5dbf3 790
cde4362f
MCC		 791 /* Tell DIF object to go to baseband mode */
792 status = cx231xx_dif_set_standard(dev,
793 DIF_USE_BASEBAND);
84b5dbf3 794 if (status < 0) {
336fea92 795 dev_err(dev->dev,
b7085c08 796 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
ed0e3729 797 __func__, status);
84b5dbf3
MCC		 798 return status;
799 }
800
801 /* Read the DFE_CTRL1 register */
ecc67d10 802 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
84b5dbf3
MCC		 803
804 /* enable the VBI_GATE_EN */
805 value |= FLD_VBI_GATE_EN;
806
807 /* Enable the auto-VGA enable */
808 value |= FLD_VGA_AUTO_EN;
809
810 /* Write it back */
ecc67d10 811 status = vid_blk_write_word(dev, DFE_CTRL1, value);
84b5dbf3
MCC		 812
813 /* Disable auto config of registers */
cde4362f 814 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 815 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 816 MODE_CTRL, FLD_ACFG_DIS,
817 cx231xx_set_field(FLD_ACFG_DIS, 1));
84b5dbf3
MCC		 818
819 /* Set CVBS input mode */
cde4362f 820 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 821 VID_BLK_I2C_ADDRESS,
cde4362f 822 MODE_CTRL, FLD_INPUT_MODE,
b9255176
SD		 823 cx231xx_set_field(FLD_INPUT_MODE,
824 INPUT_MODE_CVBS_0));
2f861387 825 } else {
cde4362f 826 /* Enable the DIF for the tuner */
84b5dbf3 827
cde4362f
MCC		 828 /* Reinitialize the DIF */
829 status = cx231xx_dif_set_standard(dev, dev->norm);
84b5dbf3 830 if (status < 0) {
336fea92 831 dev_err(dev->dev,
b7085c08 832 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
ed0e3729 833 __func__, status);
84b5dbf3
MCC		 834 return status;
835 }
836
cde4362f 837 /* Make sure bypass is cleared */
ecc67d10 838 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
cde4362f
MCC		 839
840 /* Clear the bypass bit */
841 value &= ~FLD_DIF_DIF_BYPASS;
842
843 /* Enable the use of the DIF block */
ecc67d10 844 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
cde4362f 845
84b5dbf3 846 /* Read the DFE_CTRL1 register */
ecc67d10 847 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
84b5dbf3 848
cde4362f
MCC		 849 /* Disable the VBI_GATE_EN */
850 value &= ~FLD_VBI_GATE_EN;
84b5dbf3 851
cde4362f
MCC		 852 /* Enable the auto-VGA enable, AGC, and
853 set the skip count to 2 */
854 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
84b5dbf3
MCC		 855
856 /* Write it back */
ecc67d10 857 status = vid_blk_write_word(dev, DFE_CTRL1, value);
84b5dbf3 858
6e4f574b 859 /* Wait until AGC locks up */
cde4362f 860 msleep(1);
84b5dbf3 861
cde4362f
MCC		 862 /* Disable the auto-VGA enable AGC */
863 value &= ~(FLD_VGA_AUTO_EN);
84b5dbf3 864
cde4362f 865 /* Write it back */
ecc67d10 866 status = vid_blk_write_word(dev, DFE_CTRL1, value);
84b5dbf3 867
cde4362f 868 /* Enable Polaris B0 AGC output */
ecc67d10 869 status = vid_blk_read_word(dev, PIN_CTRL, &value);
cde4362f
MCC		 870 value |= (FLD_OEF_AGC_RF) |
871 (FLD_OEF_AGC_IFVGA) |
872 (FLD_OEF_AGC_IF);
ecc67d10 873 status = vid_blk_write_word(dev, PIN_CTRL, value);
cde4362f 874
88806218 875 /* Set output mode */
cde4362f 876 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 877 VID_BLK_I2C_ADDRESS,
cde4362f 878 OUT_CTRL1, FLD_OUT_MODE,
88806218 879 dev->board.output_mode);
cde4362f
MCC		 880
881 /* Disable auto config of registers */
882 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 883 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 884 MODE_CTRL, FLD_ACFG_DIS,
885 cx231xx_set_field(FLD_ACFG_DIS, 1));
886
887 /* Set CVBS input mode */
888 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 889 VID_BLK_I2C_ADDRESS,
cde4362f 890 MODE_CTRL, FLD_INPUT_MODE,
b9255176
SD		 891 cx231xx_set_field(FLD_INPUT_MODE,
892 INPUT_MODE_CVBS_0));
cde4362f 893
b9255176
SD		 894 /* Set some bits in AFE_CTRL so that channel 2 or 3
895 * is ready to receive audio */
cde4362f
MCC		 896 /* Clear clamp for channels 2 and 3 (bit 16-17) */
897 /* Clear droop comp (bit 19-20) */
898 /* Set VGA_SEL (for audio control) (bit 7-8) */
ecc67d10 899 status = vid_blk_read_word(dev, AFE_CTRL, &value);
cde4362f 900
64fbf444
PB		 901 /*Set Func mode:01-DIF 10-baseband 11-YUV*/
902 value &= (~(FLD_FUNC_MODE));
903 value |= 0x800000;
904
cde4362f
MCC		 905 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
906
ecc67d10 907 status = vid_blk_write_word(dev, AFE_CTRL, value);
64fbf444
PB		 908
909 if (dev->tuner_type == TUNER_NXP_TDA18271) {
910 status = vid_blk_read_word(dev, PIN_CTRL,
911 &value);
912 status = vid_blk_write_word(dev, PIN_CTRL,
913 (value & 0xFFFFFFEF));
914 }
915
cde4362f 916 break;
84b5dbf3 917
84b5dbf3
MCC		 918 }
919 break;
920 }
921
922 /* Set raw VBI mode */
cde4362f 923 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 924 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 925 OUT_CTRL1, FLD_VBIHACTRAW_EN,
926 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
84b5dbf3 927
ecc67d10 928 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
84b5dbf3
MCC		 929 if (value & 0x02) {
930 value |= (1 << 19);
ecc67d10 931 status = vid_blk_write_word(dev, OUT_CTRL1, value);
84b5dbf3
MCC		 932 }
933
934 return status;
e0d3bafd
SD		 935}
936
64fbf444
PB		 937void cx231xx_enable656(struct cx231xx *dev)
938{
939 u8 temp = 0;
955e6ed8 940 /*enable TS1 data[0:7] as output to export 656*/
64fbf444 941
da983503 942 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
64fbf444 943
955e6ed8 944 /*enable TS1 clock as output to export 656*/
64fbf444 945
da983503 946 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
64fbf444
PB		 947 temp = temp|0x04;
948
da983503 949 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
64fbf444
PB		 950}
951EXPORT_SYMBOL_GPL(cx231xx_enable656);
952
953void cx231xx_disable656(struct cx231xx *dev)
954{
955 u8 temp = 0;
64fbf444 956
da983503 957 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
64fbf444 958
da983503 959 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
64fbf444
PB		 960 temp = temp&0xFB;
961
da983503 962 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
64fbf444
PB		 963}
964EXPORT_SYMBOL_GPL(cx231xx_disable656);
965
e0d3bafd 966/*
b9255176
SD		 967 * Handle any video-mode specific overrides that are different
968 * on a per video standards basis after touching the MODE_CTRL
969 * register which resets many values for autodetect
e0d3bafd
SD		 970 */
971int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
972{
84b5dbf3
MCC		 973 int status = 0;
974
336fea92 975 dev_dbg(dev->dev, "%s: 0x%x\n",
ed0e3729 976 __func__, (unsigned int)dev->norm);
84b5dbf3
MCC		 977
978 /* Change the DFE_CTRL3 bp_percent to fix flagging */
ecc67d10 979 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
84b5dbf3 980
6e4f574b 981 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
336fea92 982 dev_dbg(dev->dev, "%s: NTSC\n", __func__);
84b5dbf3 983
cde4362f
MCC		 984 /* Move the close caption lines out of active video,
985 adjust the active video start point */
986 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 987 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 988 VERT_TIM_CTRL,
989 FLD_VBLANK_CNT, 0x18);
cde4362f 990 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 991 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 992 VERT_TIM_CTRL,
993 FLD_VACTIVE_CNT,
435b4f78 994 0x1E7000);
cde4362f 995 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 996 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 997 VERT_TIM_CTRL,
998 FLD_V656BLANK_CNT,
64fbf444 999 0x1C000000);
84b5dbf3 1000
cde4362f 1001 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 1002 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 1003 HORIZ_TIM_CTRL,
1004 FLD_HBLANK_CNT,
1005 cx231xx_set_field
1006 (FLD_HBLANK_CNT, 0x79));
64fbf444 1007
6e4f574b 1008 } else if (dev->norm & V4L2_STD_SECAM) {
336fea92 1009 dev_dbg(dev->dev, "%s: SECAM\n", __func__);
6e4f574b 1010 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 1011 VID_BLK_I2C_ADDRESS,
84b5dbf3 1012 VERT_TIM_CTRL,
6af8cc0b 1013 FLD_VBLANK_CNT, 0x20);
222c4352
DH		 1014 status = cx231xx_read_modify_write_i2c_dword(dev,
1015 VID_BLK_I2C_ADDRESS,
1016 VERT_TIM_CTRL,
1017 FLD_VACTIVE_CNT,
1018 cx231xx_set_field
1019 (FLD_VACTIVE_CNT,
6af8cc0b 1020 0x244));
64fbf444
PB		 1021 status = cx231xx_read_modify_write_i2c_dword(dev,
1022 VID_BLK_I2C_ADDRESS,
1023 VERT_TIM_CTRL,
1024 FLD_V656BLANK_CNT,
1025 cx231xx_set_field
1026 (FLD_V656BLANK_CNT,
6af8cc0b 1027 0x24));
84b5dbf3 1028 /* Adjust the active video horizontal start point */
cde4362f 1029 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 1030 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 1031 HORIZ_TIM_CTRL,
1032 FLD_HBLANK_CNT,
1033 cx231xx_set_field
1034 (FLD_HBLANK_CNT, 0x85));
6e4f574b 1035 } else {
336fea92 1036 dev_dbg(dev->dev, "%s: PAL\n", __func__);
6e4f574b 1037 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 1038 VID_BLK_I2C_ADDRESS,
84b5dbf3 1039 VERT_TIM_CTRL,
6af8cc0b 1040 FLD_VBLANK_CNT, 0x20);
222c4352
DH		 1041 status = cx231xx_read_modify_write_i2c_dword(dev,
1042 VID_BLK_I2C_ADDRESS,
1043 VERT_TIM_CTRL,
1044 FLD_VACTIVE_CNT,
1045 cx231xx_set_field
1046 (FLD_VACTIVE_CNT,
6af8cc0b 1047 0x244));
64fbf444
PB		 1048 status = cx231xx_read_modify_write_i2c_dword(dev,
1049 VID_BLK_I2C_ADDRESS,
1050 VERT_TIM_CTRL,
1051 FLD_V656BLANK_CNT,
1052 cx231xx_set_field
1053 (FLD_V656BLANK_CNT,
6af8cc0b 1054 0x24));
84b5dbf3 1055 /* Adjust the active video horizontal start point */
cde4362f 1056 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 1057 VID_BLK_I2C_ADDRESS,
84b5dbf3
MCC		 1058 HORIZ_TIM_CTRL,
1059 FLD_HBLANK_CNT,
1060 cx231xx_set_field
1061 (FLD_HBLANK_CNT, 0x85));
64fbf444 1062
84b5dbf3
MCC		 1063 }
1064
1065 return status;
e0d3bafd
SD		 1066}
1067
64fbf444
PB		 1068int cx231xx_unmute_audio(struct cx231xx *dev)
1069{
1070 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1071}
1072EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1073
d4c06133 1074static int stopAudioFirmware(struct cx231xx *dev)
64fbf444
PB		 1075{
1076 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1077}
1078
d4c06133 1079static int restartAudioFirmware(struct cx231xx *dev)
64fbf444
PB		 1080{
1081 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1082}
1083
e0d3bafd
SD		 1084int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1085{
84b5dbf3
MCC		 1086 int status = 0;
1087 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1088
1089 switch (INPUT(input)->amux) {
1090 case CX231XX_AMUX_VIDEO:
1091 ainput = AUDIO_INPUT_TUNER_TV;
1092 break;
1093 case CX231XX_AMUX_LINE_IN:
ecc67d10 1094 status = cx231xx_i2s_blk_set_audio_input(dev, input);
84b5dbf3
MCC		 1095 ainput = AUDIO_INPUT_LINE;
1096 break;
1097 default:
1098 break;
1099 }
1100
1101 status = cx231xx_set_audio_decoder_input(dev, ainput);
1102
1103 return status;
e0d3bafd
SD		 1104}
1105
84b5dbf3
MCC		 1106int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1107 enum AUDIO_INPUT audio_input)
e0d3bafd 1108{
84b5dbf3
MCC		 1109 u32 dwval;
1110 int status;
ecc67d10 1111 u8 gen_ctrl;
84b5dbf3
MCC		 1112 u32 value = 0;
1113
1114 /* Put it in soft reset */
ecc67d10 1115 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
84b5dbf3 1116 gen_ctrl |= 1;
ecc67d10 1117 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
84b5dbf3
MCC		 1118
1119 switch (audio_input) {
1120 case AUDIO_INPUT_LINE:
84b5dbf3 1121 /* setup AUD_IO control from Merlin paralle output */
cde4362f
MCC		 1122 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1123 AUD_CHAN_SRC_PARALLEL);
ecc67d10 1124 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
84b5dbf3
MCC		 1125
1126 /* setup input to Merlin, SRC2 connect to AC97
1127 bypass upsample-by-2, slave mode, sony mode, left justify
1128 adr 091c, dat 01000000 */
ecc67d10 1129 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
84b5dbf3 1130
ecc67d10
SD		 1131 status = vid_blk_write_word(dev, AC97_CTL,
1132 (dwval | FLD_AC97_UP2X_BYPASS));
84b5dbf3
MCC		 1133
1134 /* select the parallel1 and SRC3 */
ecc67d10 1135 status = vid_blk_write_word(dev, BAND_OUT_SEL,
cde4362f
MCC		 1136 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1137 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
ecc67d10 1138 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
84b5dbf3
MCC		 1139
1140 /* unmute all, AC97 in, independence mode
1141 adr 08d0, data 0x00063073 */
64fbf444 1142 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
ecc67d10 1143 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
84b5dbf3
MCC		 1144
1145 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
ecc67d10
SD		 1146 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1147 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1148 (dwval | FLD_PATH1_AVC_THRESHOLD));
84b5dbf3
MCC		 1149
1150 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
ecc67d10
SD		 1151 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1152 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1153 (dwval | FLD_PATH1_SC_THRESHOLD));
84b5dbf3
MCC		 1154 break;
1155
1156 case AUDIO_INPUT_TUNER_TV:
1157 default:
64fbf444 1158 status = stopAudioFirmware(dev);
84b5dbf3 1159 /* Setup SRC sources and clocks */
ecc67d10 1160 status = vid_blk_write_word(dev, BAND_OUT_SEL,
cde4362f
MCC		 1161 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1162 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1163 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1164 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1165 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1166 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1167 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1168 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1169 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1170 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1171 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1172 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
ecc67d10 1173 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
84b5dbf3
MCC		 1174
1175 /* Setup the AUD_IO control */
ecc67d10 1176 status = vid_blk_write_word(dev, AUD_IO_CTRL,
cde4362f
MCC		 1177 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1178 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1179 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1180 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
ecc67d10 1181 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
84b5dbf3 1182
ecc67d10 1183 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
84b5dbf3
MCC		 1184
1185 /* setAudioStandard(_audio_standard); */
ecc67d10 1186 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
64fbf444
PB		 1187
1188 status = restartAudioFirmware(dev);
1189
8aed3f47
DH		 1190 switch (dev->board.tuner_type) {
1191 case TUNER_XC5000:
1192 /* SIF passthrough at 28.6363 MHz sample rate */
cde4362f 1193 status = cx231xx_read_modify_write_i2c_dword(dev,
ecc67d10 1194 VID_BLK_I2C_ADDRESS,
cde4362f
MCC		 1195 CHIP_CTRL,
1196 FLD_SIF_EN,
1197 cx231xx_set_field(FLD_SIF_EN, 1));
84b5dbf3 1198 break;
8aed3f47
DH		 1199 case TUNER_NXP_TDA18271:
1200 /* Normal mode: SIF passthrough at 14.32 MHz */
64fbf444
PB		 1201 status = cx231xx_read_modify_write_i2c_dword(dev,
1202 VID_BLK_I2C_ADDRESS,
1203 CHIP_CTRL,
1204 FLD_SIF_EN,
1205 cx231xx_set_field(FLD_SIF_EN, 0));
1206 break;
84b5dbf3 1207 default:
8aed3f47
DH		 1208 /* This is just a casual suggestion to people adding
1209 new boards in case they use a tuner type we don't
1210 currently know about */
336fea92 1211 dev_info(dev->dev,
3b795d01 1212 "Unknown tuner type configuring SIF");
84b5dbf3
MCC		 1213 break;
1214 }
1215 break;
1216
1217 case AUDIO_INPUT_TUNER_FM:
1218 /* use SIF for FM radio
1219 setupFM();
1220 setAudioStandard(_audio_standard);
1221 */
1222 break;
1223
1224 case AUDIO_INPUT_MUTE:
ecc67d10 1225 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
84b5dbf3
MCC		 1226 break;
1227 }
e0d3bafd 1228
84b5dbf3 1229 /* Take it out of soft reset */
ecc67d10 1230 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
84b5dbf3 1231 gen_ctrl &= ~1;
ecc67d10 1232 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
e0d3bafd 1233
84b5dbf3
MCC		 1234 return status;
1235}
e0d3bafd 1236
cde4362f
MCC		 1237/******************************************************************************
1238 * C H I P Specific C O N T R O L functions *
1239 ******************************************************************************/
e0d3bafd
SD		 1240int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1241{
84b5dbf3
MCC		 1242 u32 value;
1243 int status = 0;
e0d3bafd 1244
ecc67d10 1245 status = vid_blk_read_word(dev, PIN_CTRL, &value);
84b5dbf3 1246 value |= (~dev->board.ctl_pin_status_mask);
ecc67d10 1247 status = vid_blk_write_word(dev, PIN_CTRL, value);
e0d3bafd 1248
84b5dbf3 1249 return status;
e0d3bafd
SD		 1250}
1251
84b5dbf3
MCC		 1252int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1253 u8 analog_or_digital)
e0d3bafd 1254{
84b5dbf3 1255 int status = 0;
e0d3bafd 1256
84b5dbf3 1257 /* first set the direction to output */
cde4362f
MCC		 1258 status = cx231xx_set_gpio_direction(dev,
1259 dev->board.
1260 agc_analog_digital_select_gpio, 1);
e0d3bafd 1261
84b5dbf3 1262 /* 0 - demod ; 1 - Analog mode */
cde4362f 1263 status = cx231xx_set_gpio_value(dev,
84b5dbf3
MCC		 1264 dev->board.agc_analog_digital_select_gpio,
1265 analog_or_digital);
e0d3bafd 1266
1871d718
MCC		 1267 if (status < 0)
1268 return status;
1269
1270 return 0;
e0d3bafd
SD		 1271}
1272
a6f6fb9c 1273int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
e0d3bafd 1274{
84b5dbf3
MCC		 1275 u8 value[4] = { 0, 0, 0, 0 };
1276 int status = 0;
a6f6fb9c 1277 bool current_is_port_3;
e0d3bafd 1278
a1f26765
MS		 1279 /*
1280 * Should this code check dev->port_3_switch_enabled first
1281 * to skip unnecessary reading of the register?
1282 * If yes, the flag dev->port_3_switch_enabled must be initialized
1283 * correctly.
1284 */
1285
cde4362f
MCC		 1286 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1287 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 1288 if (status < 0)
1289 return status;
e0d3bafd 1290
a6f6fb9c
MCC		 1291 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false;
1292
1293 /* Just return, if already using the right port */
1294 if (current_is_port_3 == is_port_3)
1295 return 0;
1296
1297 if (is_port_3)
1298 value[0] |= I2C_DEMOD_EN;
1299 else
1300 value[0] &= ~I2C_DEMOD_EN;
1301
a6f6fb9c
MCC		 1302 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1303 PWR_CTL_EN, value, 4);
e0d3bafd 1304
a1f26765
MS		 1305 /* remember status of the switch for usage in is_tuner */
1306 if (status >= 0)
1307 dev->port_3_switch_enabled = is_port_3;
1308
84b5dbf3 1309 return status;
e0d3bafd 1310
64fbf444 1311}
a6f6fb9c
MCC		 1312EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3);
1313
64fbf444
PB		 1314void update_HH_register_after_set_DIF(struct cx231xx *dev)
1315{
1316/*
1317 u8 status = 0;
1318 u32 value = 0;
1319
1320 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1321 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1322 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1323
1324 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1325 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1326 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1327*/
1328}
1329
1330void cx231xx_dump_HH_reg(struct cx231xx *dev)
1331{
64fbf444
PB		 1332 u32 value = 0;
1333 u16 i = 0;
1334
1335 value = 0x45005390;
da983503 1336 vid_blk_write_word(dev, 0x104, value);
64fbf444
PB		 1337
1338 for (i = 0x100; i < 0x140; i++) {
da983503 1339 vid_blk_read_word(dev, i, &value);
336fea92 1340 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value);
64fbf444
PB		 1341 i = i+3;
1342 }
1343
1344 for (i = 0x300; i < 0x400; i++) {
da983503 1345 vid_blk_read_word(dev, i, &value);
336fea92 1346 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value);
64fbf444
PB		 1347 i = i+3;
1348 }
1349
1350 for (i = 0x400; i < 0x440; i++) {
da983503 1351 vid_blk_read_word(dev, i, &value);
336fea92 1352 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value);
64fbf444
PB		 1353 i = i+3;
1354 }
1355
da983503 1356 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
336fea92 1357 dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
955e6ed8 1358 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
da983503 1359 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
336fea92 1360 dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
64fbf444 1361}
955e6ed8 1362
ed0e3729
MCC		 1363#if 0
1364static void cx231xx_dump_SC_reg(struct cx231xx *dev)
64fbf444
PB		 1365{
1366 u8 value[4] = { 0, 0, 0, 0 };
336fea92 1367 dev_dbg(dev->dev, "%s!\n", __func__);
64fbf444 1368
da983503 1369 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
64fbf444 1370 value, 4);
336fea92 1371 dev_dbg(dev->dev,
b7085c08
MCC		 1372 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1373 value[1], value[2], value[3]);
da983503 1374 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
64fbf444 1375 value, 4);
336fea92 1376 dev_dbg(dev->dev,
b7085c08
MCC		 1377 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1378 value[1], value[2], value[3]);
da983503 1379 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
64fbf444 1380 value, 4);
336fea92 1381 dev_dbg(dev->dev,
b7085c08
MCC		 1382 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1383 value[1], value[2], value[3]);
da983503 1384 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
64fbf444 1385 value, 4);
336fea92 1386 dev_dbg(dev->dev,
b7085c08
MCC		 1387 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1388 value[1], value[2], value[3]);
64fbf444 1389
da983503 1390 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
64fbf444 1391 value, 4);
336fea92 1392 dev_dbg(dev->dev,
b7085c08
MCC		 1393 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1394 value[1], value[2], value[3]);
da983503 1395 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
64fbf444 1396 value, 4);
336fea92 1397 dev_dbg(dev->dev,
b7085c08
MCC		 1398 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1399 value[1], value[2], value[3]);
da983503 1400 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
64fbf444 1401 value, 4);
336fea92 1402 dev_dbg(dev->dev,
b7085c08
MCC		 1403 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1404 value[1], value[2], value[3]);
da983503 1405 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
64fbf444 1406 value, 4);
336fea92 1407 dev_dbg(dev->dev,
b7085c08
MCC		 1408 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1409 value[1], value[2], value[3]);
64fbf444 1410
da983503 1411 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
64fbf444 1412 value, 4);
336fea92 1413 dev_dbg(dev->dev,
b7085c08
MCC		 1414 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1415 value[1], value[2], value[3]);
da983503 1416 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
64fbf444 1417 value, 4);
336fea92 1418 dev_dbg(dev->dev,
b7085c08
MCC		 1419 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1420 value[1], value[2], value[3]);
da983503 1421 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
64fbf444 1422 value, 4);
336fea92 1423 dev_dbg(dev->dev,
b7085c08
MCC		 1424 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1425 value[1], value[2], value[3]);
da983503 1426 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
64fbf444 1427 value, 4);
336fea92 1428 dev_dbg(dev->dev,
b7085c08
MCC		 1429 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1430 value[1], value[2], value[3]);
64fbf444 1431
da983503 1432 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
64fbf444 1433 value, 4);
336fea92 1434 dev_dbg(dev->dev,
b7085c08
MCC		 1435 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1436 value[1], value[2], value[3]);
da983503 1437 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
64fbf444 1438 value, 4);
336fea92 1439 dev_dbg(dev->dev,
b7085c08
MCC		 1440 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1441 value[1], value[2], value[3]);
da983503 1442 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
64fbf444 1443 value, 4);
336fea92 1444 dev_dbg(dev->dev,
b7085c08
MCC		 1445 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1446 value[1], value[2], value[3]);
da983503 1447 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
64fbf444 1448 value, 4);
336fea92 1449 dev_dbg(dev->dev,
b7085c08
MCC		 1450 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1451 value[1], value[2], value[3]);
64fbf444 1452
da983503 1453 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
64fbf444 1454 value, 4);
336fea92 1455 dev_dbg(dev->dev,
b7085c08
MCC		 1456 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1457 value[1], value[2], value[3]);
da983503 1458 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
64fbf444 1459 value, 4);
336fea92 1460 dev_dbg(dev->dev,
b7085c08
MCC		 1461 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1462 value[1], value[2], value[3]);
64fbf444 1463}
ed0e3729 1464#endif
64fbf444
PB		 1465
1466void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1467
1468{
64fbf444
PB		 1469 u8 value = 0;
1470
da983503 1471 afe_read_byte(dev, ADC_STATUS2_CH3, &value);
64fbf444 1472 value = (value & 0xFE)|0x01;
da983503 1473 afe_write_byte(dev, ADC_STATUS2_CH3, value);
64fbf444 1474
da983503 1475 afe_read_byte(dev, ADC_STATUS2_CH3, &value);
64fbf444 1476 value = (value & 0xFE)|0x00;
da983503 1477 afe_write_byte(dev, ADC_STATUS2_CH3, value);
64fbf444
PB		 1478
1479
1480/*
955e6ed8 1481 config colibri to lo-if mode
64fbf444 1482
955e6ed8
MCC		 1483 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1484 the diff IF input by half,
64fbf444 1485
955e6ed8 1486 for low-if agc defect
64fbf444
PB		 1487*/
1488
da983503 1489 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
64fbf444 1490 value = (value & 0xFC)|0x00;
da983503 1491 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
64fbf444 1492
da983503 1493 afe_read_byte(dev, ADC_INPUT_CH3, &value);
64fbf444 1494 value = (value & 0xF9)|0x02;
da983503 1495 afe_write_byte(dev, ADC_INPUT_CH3, value);
64fbf444 1496
da983503 1497 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
64fbf444 1498 value = (value & 0xFB)|0x04;
da983503 1499 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
64fbf444 1500
da983503 1501 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
64fbf444 1502 value = (value & 0xFC)|0x03;
da983503 1503 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
64fbf444 1504
da983503 1505 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
64fbf444 1506 value = (value & 0xFB)|0x04;
da983503 1507 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
64fbf444 1508
da983503 1509 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
64fbf444 1510 value = (value & 0xF8)|0x06;
da983503 1511 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
64fbf444 1512
da983503 1513 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
64fbf444 1514 value = (value & 0x8F)|0x40;
da983503 1515 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
64fbf444 1516
da983503 1517 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
64fbf444 1518 value = (value & 0xDF)|0x20;
da983503 1519 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
64fbf444
PB		 1520}
1521
1522void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1523 u8 spectral_invert, u32 mode)
1524{
2ded0fe1 1525 u32 colibri_carrier_offset = 0;
2ded0fe1
DH		 1526 u32 func_mode = 0x01; /* Device has a DIF if this function is called */
1527 u32 standard = 0;
64fbf444
PB		 1528 u8 value[4] = { 0, 0, 0, 0 };
1529
336fea92 1530 dev_dbg(dev->dev, "Enter cx231xx_set_Colibri_For_LowIF()\n");
2ded0fe1
DH		 1531 value[0] = (u8) 0x6F;
1532 value[1] = (u8) 0x6F;
1533 value[2] = (u8) 0x6F;
1534 value[3] = (u8) 0x6F;
da983503 1535 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2ded0fe1 1536 PWR_CTL_EN, value, 4);
64fbf444
PB		 1537
1538 /*Set colibri for low IF*/
da983503 1539 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
64fbf444 1540
64fbf444
PB		 1541 /* Set C2HH for low IF operation.*/
1542 standard = dev->norm;
da983503 1543 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
2ded0fe1 1544 func_mode, standard);
64fbf444
PB		 1545
1546 /* Get colibri offsets.*/
1547 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
2ded0fe1 1548 standard);
64fbf444 1549
336fea92 1550 dev_dbg(dev->dev, "colibri_carrier_offset=%d, standard=0x%x\n",
2ded0fe1 1551 colibri_carrier_offset, standard);
64fbf444
PB		 1552
1553 /* Set the band Pass filter for DIF*/
2ded0fe1
DH		 1554 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
1555 spectral_invert, mode);
64fbf444
PB		 1556}
1557
1558u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1559{
955e6ed8 1560 u32 colibri_carrier_offset = 0;
64fbf444 1561
955e6ed8 1562 if (mode == TUNER_MODE_FM_RADIO) {
64fbf444 1563 colibri_carrier_offset = 1100000;
0f861583 1564 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) {
64fbf444
PB		 1565 colibri_carrier_offset = 4832000; /*4.83MHz */
1566 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1567 colibri_carrier_offset = 2700000; /*2.70MHz */
1568 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1569 | V4L2_STD_SECAM)) {
1570 colibri_carrier_offset = 2100000; /*2.10MHz */
1571 }
1572
955e6ed8 1573 return colibri_carrier_offset;
64fbf444
PB		 1574}
1575
1576void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1577 u8 spectral_invert, u32 mode)
1578{
955e6ed8 1579 unsigned long pll_freq_word;
955e6ed8
MCC		 1580 u32 dif_misc_ctrl_value = 0;
1581 u64 pll_freq_u64 = 0;
1582 u32 i = 0;
64fbf444 1583
336fea92 1584 dev_dbg(dev->dev, "if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
b7085c08 1585 if_freq, spectral_invert, mode);
64fbf444
PB		 1586
1587
955e6ed8
MCC		 1588 if (mode == TUNER_MODE_FM_RADIO) {
1589 pll_freq_word = 0x905A1CAC;
da983503 1590 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
64fbf444 1591
955e6ed8
MCC		 1592 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1593 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1594 pll_freq_word = if_freq;
1595 pll_freq_u64 = (u64)pll_freq_word << 28L;
1596 do_div(pll_freq_u64, 50000000);
1597 pll_freq_word = (u32)pll_freq_u64;
1598 /*pll_freq_word = 0x3463497;*/
da983503 1599 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
64fbf444 1600
69626853
MCC		 1601 if (spectral_invert) {
1602 if_freq -= 400000;
1603 /* Enable Spectral Invert*/
1604 vid_blk_read_word(dev, DIF_MISC_CTRL,
1605 &dif_misc_ctrl_value);
1606 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1607 vid_blk_write_word(dev, DIF_MISC_CTRL,
1608 dif_misc_ctrl_value);
1609 } else {
1610 if_freq += 400000;
1611 /* Disable Spectral Invert*/
1612 vid_blk_read_word(dev, DIF_MISC_CTRL,
1613 &dif_misc_ctrl_value);
1614 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1615 vid_blk_write_word(dev, DIF_MISC_CTRL,
1616 dif_misc_ctrl_value);
1617 }
955e6ed8 1618
69626853 1619 if_freq = (if_freq / 100000) * 100000;
64fbf444 1620
69626853
MCC		 1621 if (if_freq < 3000000)
1622 if_freq = 3000000;
64fbf444 1623
69626853
MCC		 1624 if (if_freq > 16000000)
1625 if_freq = 16000000;
64fbf444 1626 }
64fbf444 1627
336fea92 1628 dev_dbg(dev->dev, "Enter IF=%zu\n", ARRAY_SIZE(Dif_set_array));
272ed119 1629 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) {
955e6ed8 1630 if (Dif_set_array[i].if_freq == if_freq) {
da983503 1631 vid_blk_write_word(dev,
955e6ed8
MCC		 1632 Dif_set_array[i].register_address, Dif_set_array[i].value);
1633 }
1634 }
e0d3bafd
SD		 1635}
1636
cde4362f
MCC		 1637/******************************************************************************
1638 * D I F - B L O C K C O N T R O L functions *
1639 ******************************************************************************/
e0d3bafd 1640int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
84b5dbf3 1641 u32 function_mode, u32 standard)
e0d3bafd 1642{
84b5dbf3
MCC		 1643 int status = 0;
1644
64fbf444 1645
84b5dbf3
MCC		 1646 if (mode == V4L2_TUNER_RADIO) {
1647 /* C2HH */
b9255176
SD		 1648 /* lo if big signal */
1649 status = cx231xx_reg_mask_write(dev,
ecc67d10 1650 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1651 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1652 /* FUNC_MODE = DIF */
1653 status = cx231xx_reg_mask_write(dev,
ecc67d10 1654 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1655 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1656 /* IF_MODE */
1657 status = cx231xx_reg_mask_write(dev,
ecc67d10 1658 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1659 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1660 /* no inv */
1661 status = cx231xx_reg_mask_write(dev,
ecc67d10 1662 VID_BLK_I2C_ADDRESS, 32,
b9255176 1663 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
6e4f574b
SD		 1664 } else if (standard != DIF_USE_BASEBAND) {
1665 if (standard & V4L2_STD_MN) {
b9255176 1666 /* lo if big signal */
cde4362f 1667 status = cx231xx_reg_mask_write(dev,
ecc67d10 1668 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1669 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1670 /* FUNC_MODE = DIF */
cde4362f 1671 status = cx231xx_reg_mask_write(dev,
ecc67d10 1672 VID_BLK_I2C_ADDRESS, 32,
cde4362f 1673 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
b9255176
SD		 1674 function_mode);
1675 /* IF_MODE */
cde4362f 1676 status = cx231xx_reg_mask_write(dev,
ecc67d10 1677 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1678 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1679 /* no inv */
cde4362f 1680 status = cx231xx_reg_mask_write(dev,
ecc67d10 1681 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1682 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1683 /* 0x124, AUD_CHAN1_SRC = 0x3 */
cde4362f 1684 status = cx231xx_reg_mask_write(dev,
ecc67d10 1685 VID_BLK_I2C_ADDRESS, 32,
b9255176 1686 AUD_IO_CTRL, 0, 31, 0x00000003);
6e4f574b 1687 } else if ((standard == V4L2_STD_PAL_I) |
64fbf444 1688 (standard & V4L2_STD_PAL_D) |
6e4f574b 1689 (standard & V4L2_STD_SECAM)) {
84b5dbf3 1690 /* C2HH setup */
b9255176 1691 /* lo if big signal */
cde4362f 1692 status = cx231xx_reg_mask_write(dev,
ecc67d10 1693 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1694 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1695 /* FUNC_MODE = DIF */
cde4362f 1696 status = cx231xx_reg_mask_write(dev,
ecc67d10 1697 VID_BLK_I2C_ADDRESS, 32,
cde4362f 1698 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
b9255176
SD		 1699 function_mode);
1700 /* IF_MODE */
cde4362f 1701 status = cx231xx_reg_mask_write(dev,
ecc67d10 1702 VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1703 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
b9255176 1704 /* no inv */
cde4362f 1705 status = cx231xx_reg_mask_write(dev,
ecc67d10 1706 VID_BLK_I2C_ADDRESS, 32,
b9255176 1707 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
6e4f574b
SD		 1708 } else {
1709 /* default PAL BG */
84b5dbf3 1710 /* C2HH setup */
b9255176 1711 /* lo if big signal */
cde4362f 1712 status = cx231xx_reg_mask_write(dev,
ecc67d10 1713 VID_BLK_I2C_ADDRESS, 32,
b9255176
SD		 1714 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1715 /* FUNC_MODE = DIF */
cde4362f 1716 status = cx231xx_reg_mask_write(dev,
ecc67d10 1717 VID_BLK_I2C_ADDRESS, 32,
cde4362f 1718 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
b9255176
SD		 1719 function_mode);
1720 /* IF_MODE */
cde4362f 1721 status = cx231xx_reg_mask_write(dev,
ecc67d10 1722 VID_BLK_I2C_ADDRESS, 32,
6e4f574b 1723 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
b9255176 1724 /* no inv */
cde4362f 1725 status = cx231xx_reg_mask_write(dev,
ecc67d10 1726 VID_BLK_I2C_ADDRESS, 32,
b9255176 1727 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
84b5dbf3
MCC		 1728 }
1729 }
1730
1731 return status;
e0d3bafd
SD		 1732}
1733
1734int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1735{
84b5dbf3
MCC		 1736 int status = 0;
1737 u32 dif_misc_ctrl_value = 0;
1738 u32 func_mode = 0;
1739
336fea92 1740 dev_dbg(dev->dev, "%s: setStandard to %x\n", __func__, standard);
84b5dbf3 1741
ecc67d10 1742 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
84b5dbf3
MCC		 1743 if (standard != DIF_USE_BASEBAND)
1744 dev->norm = standard;
1745
1746 switch (dev->model) {
64fbf444 1747 case CX231XX_BOARD_CNXT_CARRAERA:
84b5dbf3 1748 case CX231XX_BOARD_CNXT_RDE_250:
64fbf444 1749 case CX231XX_BOARD_CNXT_SHELBY:
84b5dbf3 1750 case CX231XX_BOARD_CNXT_RDU_250:
64fbf444 1751 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1a50fdde 1752 case CX231XX_BOARD_HAUPPAUGE_EXETER:
3ead1ba3 1753 case CX231XX_BOARD_OTG102:
84b5dbf3
MCC		 1754 func_mode = 0x03;
1755 break;
64fbf444
PB		 1756 case CX231XX_BOARD_CNXT_RDE_253S:
1757 case CX231XX_BOARD_CNXT_RDU_253S:
de8ae0d5
PM		 1758 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
1759 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
64fbf444
PB		 1760 func_mode = 0x01;
1761 break;
84b5dbf3
MCC		 1762 default:
1763 func_mode = 0x01;
1764 }
1765
cde4362f 1766 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
84b5dbf3
MCC		 1767 func_mode, standard);
1768
1769 if (standard == DIF_USE_BASEBAND) { /* base band */
cde4362f
MCC		 1770 /* There is a different SRC_PHASE_INC value
1771 for baseband vs. DIF */
ecc67d10
SD		 1772 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1773 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1774 &dif_misc_ctrl_value);
84b5dbf3 1775 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
ecc67d10
SD		 1776 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1777 dif_misc_ctrl_value);
84b5dbf3 1778 } else if (standard & V4L2_STD_PAL_D) {
ecc67d10 1779 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1780 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
ecc67d10 1781 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1782 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
ecc67d10 1783 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1784 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
ecc67d10 1785 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1786 DIF_PLL_CTRL3, 0, 31, 0x00008800);
ecc67d10 1787 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1788 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
ecc67d10 1789 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1790 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
ecc67d10 1791 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1792 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
ecc67d10 1793 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1794 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
ecc67d10 1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1796 DIF_AGC_IF_INT_CURRENT, 0, 31,
1797 0x26001700);
ecc67d10 1798 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1799 DIF_AGC_RF_CURRENT, 0, 31,
1800 0x00002660);
ecc67d10 1801 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1802 DIF_VIDEO_AGC_CTRL, 0, 31,
1803 0x72500800);
ecc67d10 1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1805 DIF_VID_AUD_OVERRIDE, 0, 31,
1806 0x27000100);
ecc67d10 1807 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1808 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
ecc67d10 1809 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1810 DIF_COMP_FLT_CTRL, 0, 31,
1811 0x00000000);
ecc67d10 1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1813 DIF_SRC_PHASE_INC, 0, 31,
1814 0x1befbf06);
ecc67d10 1815 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1816 DIF_SRC_GAIN_CONTROL, 0, 31,
1817 0x000035e8);
ecc67d10 1818 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1819 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1820 /* Save the Spec Inversion value */
1821 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1822 dif_misc_ctrl_value |= 0x3a023F11;
84b5dbf3 1823 } else if (standard & V4L2_STD_PAL_I) {
ecc67d10 1824 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1825 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
ecc67d10 1826 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1827 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
ecc67d10 1828 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1829 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
ecc67d10 1830 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1831 DIF_PLL_CTRL3, 0, 31, 0x00008800);
ecc67d10 1832 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1833 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
ecc67d10 1834 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1835 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
ecc67d10 1836 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1837 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
ecc67d10 1838 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1839 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
ecc67d10 1840 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1841 DIF_AGC_IF_INT_CURRENT, 0, 31,
1842 0x26001700);
ecc67d10 1843 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1844 DIF_AGC_RF_CURRENT, 0, 31,
1845 0x00002660);
ecc67d10 1846 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1847 DIF_VIDEO_AGC_CTRL, 0, 31,
1848 0x72500800);
ecc67d10 1849 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1850 DIF_VID_AUD_OVERRIDE, 0, 31,
1851 0x27000100);
ecc67d10 1852 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1853 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
ecc67d10 1854 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1855 DIF_COMP_FLT_CTRL, 0, 31,
1856 0x00000000);
ecc67d10 1857 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1858 DIF_SRC_PHASE_INC, 0, 31,
1859 0x1befbf06);
ecc67d10 1860 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1861 DIF_SRC_GAIN_CONTROL, 0, 31,
1862 0x000035e8);
ecc67d10 1863 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1864 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1865 /* Save the Spec Inversion value */
1866 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1867 dif_misc_ctrl_value |= 0x3a033F11;
84b5dbf3 1868 } else if (standard & V4L2_STD_PAL_M) {
84b5dbf3 1869 /* improved Low Frequency Phase Noise */
ecc67d10
SD		 1870 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1871 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1872 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1873 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1874 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1875 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1876 0x26001700);
1877 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1878 0x00002660);
1879 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1880 0x72500800);
1881 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1882 0x27000100);
1883 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1884 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1885 0x009f50c1);
1886 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1887 0x1befbf06);
1888 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1889 0x000035e8);
1890 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1891 0x00000000);
84b5dbf3
MCC		 1892 /* Save the Spec Inversion value */
1893 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1894 dif_misc_ctrl_value |= 0x3A0A3F10;
84b5dbf3 1895 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
84b5dbf3 1896 /* improved Low Frequency Phase Noise */
ecc67d10
SD		 1897 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1898 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1899 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1900 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1901 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1902 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1903 0x26001700);
1904 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1905 0x00002660);
1906 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1907 0x72500800);
1908 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1909 0x27000100);
1910 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1911 0x012c405d);
1912 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1913 0x009f50c1);
1914 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1915 0x1befbf06);
1916 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1917 0x000035e8);
1918 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1919 0x00000000);
84b5dbf3
MCC		 1920 /* Save the Spec Inversion value */
1921 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1922 dif_misc_ctrl_value = 0x3A093F10;
84b5dbf3 1923 } else if (standard &
6e4f574b
SD		 1924 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1925 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
84b5dbf3 1926
ecc67d10 1927 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1928 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
ecc67d10 1929 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1930 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
ecc67d10 1931 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1932 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
ecc67d10 1933 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1934 DIF_PLL_CTRL3, 0, 31, 0x00008800);
ecc67d10 1935 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1936 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
ecc67d10 1937 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1938 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
ecc67d10 1939 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1940 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
ecc67d10 1941 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1942 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
ecc67d10 1943 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1944 DIF_AGC_IF_INT_CURRENT, 0, 31,
1945 0x26001700);
ecc67d10 1946 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1947 DIF_AGC_RF_CURRENT, 0, 31,
1948 0x00002660);
ecc67d10 1949 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1950 DIF_VID_AUD_OVERRIDE, 0, 31,
1951 0x27000100);
ecc67d10 1952 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1953 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
ecc67d10 1954 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1955 DIF_COMP_FLT_CTRL, 0, 31,
1956 0x00000000);
ecc67d10 1957 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1958 DIF_SRC_PHASE_INC, 0, 31,
1959 0x1befbf06);
ecc67d10 1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1961 DIF_SRC_GAIN_CONTROL, 0, 31,
1962 0x000035e8);
ecc67d10 1963 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1964 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
ecc67d10 1965 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1966 DIF_VIDEO_AGC_CTRL, 0, 31,
1967 0xf4000000);
1968
1969 /* Save the Spec Inversion value */
1970 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1971 dif_misc_ctrl_value |= 0x3a023F11;
84b5dbf3 1972 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
84b5dbf3 1973 /* Is it SECAM_L1? */
ecc67d10 1974 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1975 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
ecc67d10 1976 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1977 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
ecc67d10 1978 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1979 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
ecc67d10 1980 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1981 DIF_PLL_CTRL3, 0, 31, 0x00008800);
ecc67d10 1982 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1983 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
ecc67d10 1984 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1985 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
ecc67d10 1986 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1987 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
ecc67d10 1988 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 1989 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
ecc67d10 1990 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1991 DIF_AGC_IF_INT_CURRENT, 0, 31,
1992 0x26001700);
ecc67d10 1993 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1994 DIF_AGC_RF_CURRENT, 0, 31,
1995 0x00002660);
ecc67d10 1996 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 1997 DIF_VID_AUD_OVERRIDE, 0, 31,
1998 0x27000100);
ecc67d10 1999 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 2000 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
ecc67d10 2001 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 2002 DIF_COMP_FLT_CTRL, 0, 31,
2003 0x00000000);
ecc67d10 2004 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 2005 DIF_SRC_PHASE_INC, 0, 31,
2006 0x1befbf06);
ecc67d10 2007 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 2008 DIF_SRC_GAIN_CONTROL, 0, 31,
2009 0x000035e8);
ecc67d10 2010 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3 2011 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
ecc67d10 2012 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
84b5dbf3
MCC		 2013 DIF_VIDEO_AGC_CTRL, 0, 31,
2014 0xf2560000);
2015
2016 /* Save the Spec Inversion value */
2017 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2018 dif_misc_ctrl_value |= 0x3a023F11;
2019
6e4f574b 2020 } else if (standard & V4L2_STD_NTSC_M) {
cde4362f
MCC		 2021 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
2022 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
84b5dbf3 2023
cde4362f
MCC		 2024 /* For NTSC the centre frequency of video coming out of
2025 sidewinder is around 7.1MHz or 3.6MHz depending on the
2026 spectral inversion. so for a non spectrally inverted channel
2027 the pll freq word is 0x03420c49
84b5dbf3
MCC		 2028 */
2029
ecc67d10
SD		 2030 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2031 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2032 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2033 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2034 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2035 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2036 0x26001700);
2037 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2038 0x00002660);
2039 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2040 0x04000800);
2041 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2042 0x27000100);
2043 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2044
2045 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2046 0x009f50c1);
2047 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2048 0x1befbf06);
2049 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2050 0x000035e8);
2051
2052 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2053 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2054 0xC2262600);
2055 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
84b5dbf3
MCC		 2056
2057 /* Save the Spec Inversion value */
2058 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2059 dif_misc_ctrl_value |= 0x3a003F10;
6e4f574b
SD		 2060 } else {
2061 /* default PAL BG */
ecc67d10 2062 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 2063 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
ecc67d10 2064 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 2065 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
ecc67d10 2066 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 2067 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
ecc67d10 2068 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 2069 DIF_PLL_CTRL3, 0, 31, 0x00008800);
ecc67d10 2070 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 2071 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
ecc67d10 2072 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 2073 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
ecc67d10 2074 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 2075 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
ecc67d10 2076 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 2077 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
ecc67d10 2078 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 2079 DIF_AGC_IF_INT_CURRENT, 0, 31,
2080 0x26001700);
ecc67d10 2081 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 2082 DIF_AGC_RF_CURRENT, 0, 31,
2083 0x00002660);
ecc67d10 2084 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 2085 DIF_VIDEO_AGC_CTRL, 0, 31,
2086 0x72500800);
ecc67d10 2087 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 2088 DIF_VID_AUD_OVERRIDE, 0, 31,
2089 0x27000100);
ecc67d10 2090 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b 2091 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
ecc67d10 2092 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 2093 DIF_COMP_FLT_CTRL, 0, 31,
2094 0x00A653A8);
ecc67d10 2095 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 2096 DIF_SRC_PHASE_INC, 0, 31,
2097 0x1befbf06);
ecc67d10 2098 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 2099 DIF_SRC_GAIN_CONTROL, 0, 31,
2100 0x000035e8);
ecc67d10 2101 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
6e4f574b
SD		 2102 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2103 /* Save the Spec Inversion value */
2104 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2105 dif_misc_ctrl_value |= 0x3a013F11;
84b5dbf3
MCC		 2106 }
2107
2108 /* The AGC values should be the same for all standards,
2109 AUD_SRC_SEL[19] should always be disabled */
2110 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2111
cde4362f
MCC		 2112 /* It is still possible to get Set Standard calls even when we
2113 are in FM mode.
84b5dbf3
MCC		 2114 This is done to override the value for FM. */
2115 if (dev->active_mode == V4L2_TUNER_RADIO)
2116 dif_misc_ctrl_value = 0x7a080000;
2117
2118 /* Write the calculated value for misc ontrol register */
ecc67d10 2119 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
84b5dbf3
MCC		 2120
2121 return status;
e0d3bafd
SD		 2122}
2123
2124int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2125{
2126 int status = 0;
2127 u32 dwval;
2128
2129 /* Set the RF and IF k_agc values to 3 */
ecc67d10 2130 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
e0d3bafd
SD		 2131 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2132 dwval |= 0x33000000;
2133
ecc67d10 2134 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
e0d3bafd 2135
84b5dbf3 2136 return status;
e0d3bafd
SD		 2137}
2138
2139int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2140{
84b5dbf3 2141 int status = 0;
e0d3bafd 2142 u32 dwval;
336fea92 2143 dev_dbg(dev->dev, "%s: dev->tuner_type =0%d\n",
b7085c08 2144 __func__, dev->tuner_type);
6e4f574b
SD		 2145 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2146 * SECAM L/B/D standards */
ecc67d10 2147 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
84b5dbf3 2148 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
e0d3bafd 2149
cde4362f 2150 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
64fbf444
PB		 2151 V4L2_STD_SECAM_D)) {
2152 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2153 dwval &= ~FLD_DIF_IF_REF;
2154 dwval |= 0x88000300;
2155 } else
2156 dwval |= 0x88000000;
2157 } else {
2158 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2159 dwval &= ~FLD_DIF_IF_REF;
2160 dwval |= 0xCC000300;
2161 } else
2162 dwval |= 0x44000000;
2163 }
e0d3bafd 2164
ecc67d10 2165 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
e0d3bafd 2166
b251f957 2167 return status == sizeof(dwval) ? 0 : -EIO;
e0d3bafd
SD		 2168}
2169
cde4362f 2170/******************************************************************************
ecc67d10 2171 * I 2 S - B L O C K C O N T R O L functions *
cde4362f 2172 ******************************************************************************/
ecc67d10 2173int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
e0d3bafd 2174{
84b5dbf3
MCC		 2175 int status = 0;
2176 u32 value;
2177
ecc67d10 2178 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
cde4362f 2179 CH_PWR_CTRL1, 1, &value, 1);
84b5dbf3
MCC		 2180 /* enables clock to delta-sigma and decimation filter */
2181 value |= 0x80;
ecc67d10 2182 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 2183 CH_PWR_CTRL1, 1, value, 1);
2184 /* power up all channel */
ecc67d10 2185 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 2186 CH_PWR_CTRL2, 1, 0x00, 1);
2187
2188 return status;
e0d3bafd
SD		 2189}
2190
ecc67d10 2191int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
6e4f574b 2192 enum AV_MODE avmode)
e0d3bafd 2193{
84b5dbf3
MCC		 2194 int status = 0;
2195 u32 value = 0;
2196
2197 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
ecc67d10 2198 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 2199 CH_PWR_CTRL2, 1, &value, 1);
2200 value |= 0xfe;
ecc67d10 2201 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 2202 CH_PWR_CTRL2, 1, value, 1);
2203 } else {
ecc67d10 2204 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 2205 CH_PWR_CTRL2, 1, 0x00, 1);
2206 }
2207
2208 return status;
e0d3bafd
SD		 2209}
2210
ecc67d10
SD		 2211/* set i2s_blk for audio input types */
2212int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
e0d3bafd 2213{
84b5dbf3 2214 int status = 0;
e0d3bafd 2215
84b5dbf3
MCC		 2216 switch (audio_input) {
2217 case CX231XX_AMUX_LINE_IN:
ecc67d10 2218 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3 2219 CH_PWR_CTRL2, 1, 0x00, 1);
ecc67d10 2220 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
84b5dbf3
MCC		 2221 CH_PWR_CTRL1, 1, 0x80, 1);
2222 break;
2223 case CX231XX_AMUX_VIDEO:
2224 default:
2225 break;
2226 }
e0d3bafd 2227
84b5dbf3 2228 dev->ctl_ainput = audio_input;
e0d3bafd 2229
84b5dbf3 2230 return status;
e0d3bafd
SD		 2231}
2232
cde4362f
MCC		 2233/******************************************************************************
2234 * P O W E R C O N T R O L functions *
2235 ******************************************************************************/
6e4f574b 2236int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
e0d3bafd 2237{
84b5dbf3
MCC		 2238 u8 value[4] = { 0, 0, 0, 0 };
2239 u32 tmp = 0;
2240 int status = 0;
2241
2242 if (dev->power_mode != mode)
2243 dev->power_mode = mode;
2244 else {
336fea92 2245 dev_dbg(dev->dev, "%s: mode = %d, No Change req.\n",
ed0e3729 2246 __func__, mode);
84b5dbf3
MCC		 2247 return 0;
2248 }
2249
cde4362f
MCC		 2250 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2251 4);
84b5dbf3
MCC		 2252 if (status < 0)
2253 return status;
2254
3f9280a8 2255 tmp = le32_to_cpu(*((__le32 *) value));
84b5dbf3
MCC		 2256
2257 switch (mode) {
2258 case POLARIS_AVMODE_ENXTERNAL_AV:
2259
2260 tmp &= (~PWR_MODE_MASK);
2261
2262 tmp |= PWR_AV_EN;
2263 value[0] = (u8) tmp;
2264 value[1] = (u8) (tmp >> 8);
2265 value[2] = (u8) (tmp >> 16);
2266 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2267 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2268 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2269 msleep(PWR_SLEEP_INTERVAL);
2270
2271 tmp |= PWR_ISO_EN;
2272 value[0] = (u8) tmp;
2273 value[1] = (u8) (tmp >> 8);
2274 value[2] = (u8) (tmp >> 16);
2275 value[3] = (u8) (tmp >> 24);
2276 status =
2277 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2278 value, 4);
2279 msleep(PWR_SLEEP_INTERVAL);
2280
2281 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2282 value[0] = (u8) tmp;
2283 value[1] = (u8) (tmp >> 8);
2284 value[2] = (u8) (tmp >> 16);
2285 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2286 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2287 PWR_CTL_EN, value, 4);
84b5dbf3 2288
b9255176
SD		 2289 /* reset state of xceive tuner */
2290 dev->xc_fw_load_done = 0;
84b5dbf3
MCC		 2291 break;
2292
2293 case POLARIS_AVMODE_ANALOGT_TV:
2294
64fbf444 2295 tmp |= PWR_DEMOD_EN;
84b5dbf3
MCC		 2296 value[0] = (u8) tmp;
2297 value[1] = (u8) (tmp >> 8);
2298 value[2] = (u8) (tmp >> 16);
2299 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2300 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2301 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2302 msleep(PWR_SLEEP_INTERVAL);
2303
2304 if (!(tmp & PWR_TUNER_EN)) {
2305 tmp |= (PWR_TUNER_EN);
2306 value[0] = (u8) tmp;
2307 value[1] = (u8) (tmp >> 8);
2308 value[2] = (u8) (tmp >> 16);
2309 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2310 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2311 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2312 msleep(PWR_SLEEP_INTERVAL);
2313 }
2314
2315 if (!(tmp & PWR_AV_EN)) {
2316 tmp |= PWR_AV_EN;
2317 value[0] = (u8) tmp;
2318 value[1] = (u8) (tmp >> 8);
2319 value[2] = (u8) (tmp >> 16);
2320 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2321 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2322 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2323 msleep(PWR_SLEEP_INTERVAL);
2324 }
2325 if (!(tmp & PWR_ISO_EN)) {
2326 tmp |= PWR_ISO_EN;
2327 value[0] = (u8) tmp;
2328 value[1] = (u8) (tmp >> 8);
2329 value[2] = (u8) (tmp >> 16);
2330 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2331 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2332 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2333 msleep(PWR_SLEEP_INTERVAL);
2334 }
2335
2336 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2337 tmp |= POLARIS_AVMODE_ANALOGT_TV;
2338 value[0] = (u8) tmp;
2339 value[1] = (u8) (tmp >> 8);
2340 value[2] = (u8) (tmp >> 16);
2341 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2342 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2343 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2344 msleep(PWR_SLEEP_INTERVAL);
2345 }
2346
a6f6fb9c 2347 if (dev->board.tuner_type != TUNER_ABSENT) {
64fbf444 2348 /* reset the Tuner */
a6f6fb9c
MCC		 2349 if (dev->board.tuner_gpio)
2350 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
64fbf444 2351
84b5dbf3
MCC		 2352 if (dev->cx231xx_reset_analog_tuner)
2353 dev->cx231xx_reset_analog_tuner(dev);
2354 }
64fbf444 2355
84b5dbf3
MCC		 2356 break;
2357
2358 case POLARIS_AVMODE_DIGITAL:
84b5dbf3
MCC		 2359 if (!(tmp & PWR_TUNER_EN)) {
2360 tmp |= (PWR_TUNER_EN);
2361 value[0] = (u8) tmp;
2362 value[1] = (u8) (tmp >> 8);
2363 value[2] = (u8) (tmp >> 16);
2364 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2365 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2366 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2367 msleep(PWR_SLEEP_INTERVAL);
2368 }
2369 if (!(tmp & PWR_AV_EN)) {
2370 tmp |= PWR_AV_EN;
2371 value[0] = (u8) tmp;
2372 value[1] = (u8) (tmp >> 8);
2373 value[2] = (u8) (tmp >> 16);
2374 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2375 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2376 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2377 msleep(PWR_SLEEP_INTERVAL);
2378 }
2379 if (!(tmp & PWR_ISO_EN)) {
2380 tmp |= PWR_ISO_EN;
2381 value[0] = (u8) tmp;
2382 value[1] = (u8) (tmp >> 8);
2383 value[2] = (u8) (tmp >> 16);
2384 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2385 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2386 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2387 msleep(PWR_SLEEP_INTERVAL);
2388 }
2389
cc355753 2390 tmp &= (~PWR_AV_MODE);
082417d1 2391 tmp |= POLARIS_AVMODE_DIGITAL;
84b5dbf3
MCC		 2392 value[0] = (u8) tmp;
2393 value[1] = (u8) (tmp >> 8);
2394 value[2] = (u8) (tmp >> 16);
2395 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2396 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2397 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2398 msleep(PWR_SLEEP_INTERVAL);
2399
2400 if (!(tmp & PWR_DEMOD_EN)) {
2401 tmp |= PWR_DEMOD_EN;
2402 value[0] = (u8) tmp;
2403 value[1] = (u8) (tmp >> 8);
2404 value[2] = (u8) (tmp >> 16);
2405 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2406 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2407 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2408 msleep(PWR_SLEEP_INTERVAL);
2409 }
2410
a6f6fb9c 2411 if (dev->board.tuner_type != TUNER_ABSENT) {
64fbf444 2412 /* reset the Tuner */
a6f6fb9c
MCC		 2413 if (dev->board.tuner_gpio)
2414 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
1a50fdde 2415
84b5dbf3
MCC		 2416 if (dev->cx231xx_reset_analog_tuner)
2417 dev->cx231xx_reset_analog_tuner(dev);
2418 }
2419 break;
2420
2421 default:
2422 break;
2423 }
2424
2425 msleep(PWR_SLEEP_INTERVAL);
2426
cde4362f
MCC		 2427 /* For power saving, only enable Pwr_resetout_n
2428 when digital TV is selected. */
84b5dbf3
MCC		 2429 if (mode == POLARIS_AVMODE_DIGITAL) {
2430 tmp |= PWR_RESETOUT_EN;
2431 value[0] = (u8) tmp;
2432 value[1] = (u8) (tmp >> 8);
2433 value[2] = (u8) (tmp >> 16);
2434 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2435 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2436 PWR_CTL_EN, value, 4);
84b5dbf3
MCC		 2437 msleep(PWR_SLEEP_INTERVAL);
2438 }
2439
ecc67d10
SD		 2440 /* update power control for afe */
2441 status = cx231xx_afe_update_power_control(dev, mode);
84b5dbf3 2442
ecc67d10
SD		 2443 /* update power control for i2s_blk */
2444 status = cx231xx_i2s_blk_update_power_control(dev, mode);
84b5dbf3 2445
cde4362f
MCC		 2446 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2447 4);
84b5dbf3
MCC		 2448
2449 return status;
e0d3bafd
SD		 2450}
2451
2452int cx231xx_power_suspend(struct cx231xx *dev)
2453{
84b5dbf3
MCC		 2454 u8 value[4] = { 0, 0, 0, 0 };
2455 u32 tmp = 0;
2456 int status = 0;
e0d3bafd 2457
cde4362f
MCC		 2458 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2459 value, 4);
84b5dbf3
MCC		 2460 if (status > 0)
2461 return status;
e0d3bafd 2462
3f9280a8 2463 tmp = le32_to_cpu(*((__le32 *) value));
84b5dbf3 2464 tmp &= (~PWR_MODE_MASK);
e0d3bafd 2465
84b5dbf3
MCC		 2466 value[0] = (u8) tmp;
2467 value[1] = (u8) (tmp >> 8);
2468 value[2] = (u8) (tmp >> 16);
2469 value[3] = (u8) (tmp >> 24);
cde4362f
MCC		 2470 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2471 value, 4);
e0d3bafd 2472
84b5dbf3 2473 return status;
e0d3bafd
SD		 2474}
2475
cde4362f
MCC		 2476/******************************************************************************
2477 * S T R E A M C O N T R O L functions *
2478 ******************************************************************************/
e0d3bafd
SD		 2479int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2480{
84b5dbf3
MCC		 2481 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2482 u32 tmp = 0;
2483 int status = 0;
e0d3bafd 2484
336fea92 2485 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask);
cde4362f
MCC		 2486 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2487 value, 4);
84b5dbf3
MCC		 2488 if (status < 0)
2489 return status;
e0d3bafd 2490
3f9280a8 2491 tmp = le32_to_cpu(*((__le32 *) value));
84b5dbf3
MCC		 2492 tmp |= ep_mask;
2493 value[0] = (u8) tmp;
2494 value[1] = (u8) (tmp >> 8);
2495 value[2] = (u8) (tmp >> 16);
2496 value[3] = (u8) (tmp >> 24);
e0d3bafd 2497
cde4362f
MCC		 2498 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2499 value, 4);
e0d3bafd 2500
84b5dbf3 2501 return status;
e0d3bafd
SD		 2502}
2503
2504int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2505{
84b5dbf3
MCC		 2506 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2507 u32 tmp = 0;
2508 int status = 0;
e0d3bafd 2509
336fea92 2510 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask);
84b5dbf3
MCC		 2511 status =
2512 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2513 if (status < 0)
2514 return status;
e0d3bafd 2515
3f9280a8 2516 tmp = le32_to_cpu(*((__le32 *) value));
84b5dbf3
MCC		 2517 tmp &= (~ep_mask);
2518 value[0] = (u8) tmp;
2519 value[1] = (u8) (tmp >> 8);
2520 value[2] = (u8) (tmp >> 16);
2521 value[3] = (u8) (tmp >> 24);
e0d3bafd 2522
cde4362f
MCC		 2523 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2524 value, 4);
e0d3bafd 2525
84b5dbf3 2526 return status;
e0d3bafd
SD		 2527}
2528
2529int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2530{
84b5dbf3 2531 int status = 0;
64fbf444
PB		 2532 u32 value = 0;
2533 u8 val[4] = { 0, 0, 0, 0 };
e0d3bafd 2534
84b5dbf3
MCC		 2535 if (dev->udev->speed == USB_SPEED_HIGH) {
2536 switch (media_type) {
460a4de7 2537 case Audio:
336fea92 2538 dev_dbg(dev->dev,
b7085c08 2539 "%s: Audio enter HANC\n", __func__);
84b5dbf3
MCC		 2540 status =
2541 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2542 break;
2543
460a4de7 2544 case Vbi:
336fea92 2545 dev_dbg(dev->dev,
b7085c08 2546 "%s: set vanc registers\n", __func__);
84b5dbf3
MCC		 2547 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2548 break;
2549
460a4de7 2550 case Sliced_cc:
336fea92 2551 dev_dbg(dev->dev,
b7085c08 2552 "%s: set hanc registers\n", __func__);
84b5dbf3
MCC		 2553 status =
2554 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2555 break;
2556
460a4de7 2557 case Raw_Video:
336fea92 2558 dev_dbg(dev->dev,
b7085c08 2559 "%s: set video registers\n", __func__);
84b5dbf3
MCC		 2560 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2561 break;
2562
460a4de7 2563 case TS1_serial_mode:
336fea92 2564 dev_dbg(dev->dev,
b7085c08 2565 "%s: set ts1 registers", __func__);
88538bb5
MCC		 2566
2567 if (dev->board.has_417) {
336fea92 2568 dev_dbg(dev->dev,
b7085c08 2569 "%s: MPEG\n", __func__);
88538bb5
MCC		 2570 value &= 0xFFFFFFFC;
2571 value |= 0x3;
2572
2573 status = cx231xx_mode_register(dev,
2574 TS_MODE_REG, value);
2575
2576 val[0] = 0x04;
2577 val[1] = 0xA3;
2578 val[2] = 0x3B;
2579 val[3] = 0x00;
2580 status = cx231xx_write_ctrl_reg(dev,
2581 VRT_SET_REGISTER,
2582 TS1_CFG_REG, val, 4);
2583
2584 val[0] = 0x00;
2585 val[1] = 0x08;
2586 val[2] = 0x00;
2587 val[3] = 0x08;
2588 status = cx231xx_write_ctrl_reg(dev,
2589 VRT_SET_REGISTER,
2590 TS1_LENGTH_REG, val, 4);
2591 } else {
336fea92 2592 dev_dbg(dev->dev, "%s: BDA\n", __func__);
88538bb5
MCC		 2593 status = cx231xx_mode_register(dev,
2594 TS_MODE_REG, 0x101);
2595 status = cx231xx_mode_register(dev,
2596 TS1_CFG_REG, 0x010);
2597 }
84b5dbf3 2598 break;
64fbf444 2599
460a4de7 2600 case TS1_parallel_mode:
336fea92 2601 dev_dbg(dev->dev,
b7085c08
MCC		 2602 "%s: set ts1 parallel mode registers\n",
2603 __func__);
84b5dbf3
MCC		 2604 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2605 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2606 break;
2607 }
2608 } else {
2609 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2610 }
e0d3bafd 2611
84b5dbf3
MCC		 2612 return status;
2613}
e0d3bafd
SD		 2614
2615int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2616{
aad40d3d 2617 int rc = -1;
84b5dbf3 2618 u32 ep_mask = -1;
b9255176 2619 struct pcb_config *pcb_config;
84b5dbf3
MCC		 2620
2621 /* get EP for media type */
b9255176 2622 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
84b5dbf3 2623
460a4de7 2624 if (pcb_config->config_num) {
84b5dbf3 2625 switch (media_type) {
460a4de7 2626 case Raw_Video:
84b5dbf3
MCC		 2627 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2628 break;
460a4de7 2629 case Audio:
84b5dbf3
MCC		 2630 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2631 break;
460a4de7 2632 case Vbi:
84b5dbf3
MCC		 2633 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2634 break;
460a4de7 2635 case Sliced_cc:
84b5dbf3
MCC		 2636 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2637 break;
460a4de7
DD		 2638 case TS1_serial_mode:
2639 case TS1_parallel_mode:
84b5dbf3
MCC		 2640 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2641 break;
460a4de7 2642 case TS2:
84b5dbf3
MCC		 2643 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2644 break;
2645 }
84b5dbf3
MCC		 2646 }
2647
2648 if (start) {
2649 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2650
cde4362f 2651 if (rc < 0)
84b5dbf3 2652 return rc;
84b5dbf3
MCC		 2653
2654 /* enable video capture */
2655 if (ep_mask > 0)
2656 rc = cx231xx_start_stream(dev, ep_mask);
2657 } else {
2658 /* disable video capture */
2659 if (ep_mask > 0)
2660 rc = cx231xx_stop_stream(dev, ep_mask);
2661 }
2662
e0d3bafd
SD		 2663 return rc;
2664}
84b5dbf3 2665EXPORT_SYMBOL_GPL(cx231xx_capture_start);
e0d3bafd 2666
cde4362f
MCC		 2667/*****************************************************************************
2668* G P I O B I T control functions *
2669******************************************************************************/
6b236a37 2670static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val)
e0d3bafd 2671{
84b5dbf3 2672 int status = 0;
e0d3bafd 2673
3f9280a8 2674 gpio_val = (__force u32)cpu_to_le32(gpio_val);
6b236a37 2675 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0);
e0d3bafd 2676
84b5dbf3 2677 return status;
e0d3bafd
SD		 2678}
2679
6b236a37 2680static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val)
e0d3bafd 2681{
3f9280a8 2682 __le32 tmp;
84b5dbf3 2683 int status = 0;
e0d3bafd 2684
6b236a37
HV		 2685 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1);
2686 *gpio_val = le32_to_cpu(tmp);
e0d3bafd 2687
84b5dbf3 2688 return status;
e0d3bafd
SD		 2689}
2690
2691/*
2692* cx231xx_set_gpio_direction
2693* Sets the direction of the GPIO pin to input or output
2694*
2695* Parameters :
2696* pin_number : The GPIO Pin number to program the direction for
2697* from 0 to 31
2698* pin_value : The Direction of the GPIO Pin under reference.
2699* 0 = Input direction
2700* 1 = Output direction
2701*/
2702int cx231xx_set_gpio_direction(struct cx231xx *dev,
84b5dbf3 2703 int pin_number, int pin_value)
e0d3bafd
SD		 2704{
2705 int status = 0;
84b5dbf3 2706 u32 value = 0;
e0d3bafd 2707
84b5dbf3 2708 /* Check for valid pin_number - if 32 , bail out */
cde4362f 2709 if (pin_number >= 32)
84b5dbf3 2710 return -EINVAL;
e0d3bafd 2711
cde4362f
MCC		 2712 /* input */
2713 if (pin_value == 0)
84b5dbf3 2714 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
cde4362f 2715 else
84b5dbf3 2716 value = dev->gpio_dir | (1 << pin_number);
e0d3bafd 2717
6b236a37 2718 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val);
e0d3bafd 2719
84b5dbf3 2720 /* cache the value for future */
e0d3bafd
SD		 2721 dev->gpio_dir = value;
2722
84b5dbf3 2723 return status;
e0d3bafd
SD		 2724}
2725
e0d3bafd 2726/*
6e4f574b 2727* cx231xx_set_gpio_value
e0d3bafd
SD		 2728* Sets the value of the GPIO pin to Logic high or low. The Pin under
2729* reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2730*
2731* Parameters :
2732* pin_number : The GPIO Pin number to program the direction for
2733* pin_value : The value of the GPIO Pin under reference.
2734* 0 = set it to 0
2735* 1 = set it to 1
2736*/
84b5dbf3 2737int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
e0d3bafd 2738{
84b5dbf3
MCC		 2739 int status = 0;
2740 u32 value = 0;
2741
2742 /* Check for valid pin_number - if 0xFF , bail out */
2743 if (pin_number >= 32)
2744 return -EINVAL;
2745
2746 /* first do a sanity check - if the Pin is not output, make it output */
2747 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2748 /* It was in input mode */
2749 value = dev->gpio_dir | (1 << pin_number);
2750 dev->gpio_dir = value;
cde4362f 2751 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
6b236a37 2752 dev->gpio_val);
e0d3bafd 2753 value = 0;
84b5dbf3 2754 }
e0d3bafd 2755
cde4362f 2756 if (pin_value == 0)
84b5dbf3 2757 value = dev->gpio_val & (~(1 << pin_number));
cde4362f 2758 else
84b5dbf3 2759 value = dev->gpio_val | (1 << pin_number);
e0d3bafd 2760
84b5dbf3
MCC		 2761 /* store the value */
2762 dev->gpio_val = value;
e0d3bafd 2763
84b5dbf3 2764 /* toggle bit0 of GP_IO */
6b236a37 2765 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd 2766
84b5dbf3 2767 return status;
e0d3bafd
SD		 2768}
2769
cde4362f
MCC		 2770/*****************************************************************************
2771* G P I O I2C related functions *
2772******************************************************************************/
e0d3bafd
SD		 2773int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2774{
2775 int status = 0;
2776
2777 /* set SCL to output 1 ; set SDA to output 1 */
84b5dbf3
MCC		 2778 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2779 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2780 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2781 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2782
6b236a37 2783 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
cde4362f 2784 if (status < 0)
e0d3bafd 2785 return -EINVAL;
e0d3bafd
SD		 2786
2787 /* set SCL to output 1; set SDA to output 0 */
84b5dbf3
MCC		 2788 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2789 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd 2790
6b236a37 2791 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
cde4362f 2792 if (status < 0)
e0d3bafd 2793 return -EINVAL;
e0d3bafd 2794
84b5dbf3
MCC		 2795 /* set SCL to output 0; set SDA to output 0 */
2796 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2797 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd 2798
6b236a37 2799 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
cde4362f 2800 if (status < 0)
e0d3bafd 2801 return -EINVAL;
e0d3bafd
SD		 2802
2803 return status;
2804}
2805
e0d3bafd
SD		 2806int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2807{
84b5dbf3 2808 int status = 0;
e0d3bafd 2809
84b5dbf3
MCC		 2810 /* set SCL to output 0; set SDA to output 0 */
2811 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2812 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
e0d3bafd 2813
84b5dbf3
MCC		 2814 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2815 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd 2816
6b236a37 2817 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
cde4362f 2818 if (status < 0)
e0d3bafd 2819 return -EINVAL;
e0d3bafd 2820
84b5dbf3
MCC		 2821 /* set SCL to output 1; set SDA to output 0 */
2822 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2823 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd 2824
6b236a37 2825 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
cde4362f 2826 if (status < 0)
e0d3bafd 2827 return -EINVAL;
e0d3bafd
SD		 2828
2829 /* set SCL to input ,release SCL cable control
2830 set SDA to input ,release SDA cable control */
84b5dbf3
MCC		 2831 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2832 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd 2833
84b5dbf3 2834 status =
6b236a37 2835 cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
cde4362f 2836 if (status < 0)
e0d3bafd 2837 return -EINVAL;
cde4362f 2838
e0d3bafd
SD		 2839 return status;
2840}
2841
e0d3bafd
SD		 2842int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2843{
84b5dbf3
MCC		 2844 int status = 0;
2845 u8 i;
e0d3bafd
SD		 2846
2847 /* set SCL to output ; set SDA to output */
84b5dbf3
MCC		 2848 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2849 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2850
2851 for (i = 0; i < 8; i++) {
2852 if (((data << i) & 0x80) == 0) {
2853 /* set SCL to output 0; set SDA to output 0 */
2854 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2855 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
cde4362f 2856 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
6b236a37 2857 dev->gpio_val);
84b5dbf3
MCC		 2858
2859 /* set SCL to output 1; set SDA to output 0 */
2860 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
cde4362f 2861 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
6b236a37 2862 dev->gpio_val);
84b5dbf3
MCC		 2863
2864 /* set SCL to output 0; set SDA to output 0 */
2865 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f 2866 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
6b236a37 2867 dev->gpio_val);
e0d3bafd 2868 } else {
84b5dbf3
MCC		 2869 /* set SCL to output 0; set SDA to output 1 */
2870 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2871 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
cde4362f 2872 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
6b236a37 2873 dev->gpio_val);
84b5dbf3
MCC		 2874
2875 /* set SCL to output 1; set SDA to output 1 */
2876 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
cde4362f 2877 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
6b236a37 2878 dev->gpio_val);
84b5dbf3
MCC		 2879
2880 /* set SCL to output 0; set SDA to output 1 */
2881 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f 2882 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
6b236a37 2883 dev->gpio_val);
84b5dbf3 2884 }
e0d3bafd
SD		 2885 }
2886 return status;
2887}
2888
64fbf444 2889int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
e0d3bafd
SD		 2890{
2891 u8 value = 0;
84b5dbf3
MCC		 2892 int status = 0;
2893 u32 gpio_logic_value = 0;
2894 u8 i;
e0d3bafd
SD		 2895
2896 /* read byte */
84b5dbf3 2897 for (i = 0; i < 8; i++) { /* send write I2c addr */
e0d3bafd
SD		 2898
2899 /* set SCL to output 0; set SDA to input */
84b5dbf3 2900 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
cde4362f 2901 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
6b236a37 2902 dev->gpio_val);
e0d3bafd
SD		 2903
2904 /* set SCL to output 1; set SDA to input */
84b5dbf3 2905 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
cde4362f 2906 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
6b236a37 2907 dev->gpio_val);
e0d3bafd
SD		 2908
2909 /* get SDA data bit */
2910 gpio_logic_value = dev->gpio_val;
cde4362f 2911 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
6b236a37 2912 &dev->gpio_val);
cde4362f 2913 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
84b5dbf3 2914 value |= (1 << (8 - i - 1));
e0d3bafd
SD		 2915
2916 dev->gpio_val = gpio_logic_value;
2917 }
2918
2919 /* set SCL to output 0,finish the read latest SCL signal.
cde4362f
MCC		 2920 !!!set SDA to input, never to modify SDA direction at
2921 the same times */
84b5dbf3 2922 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
6b236a37 2923 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd 2924
84b5dbf3
MCC		 2925 /* store the value */
2926 *buf = value & 0xff;
e0d3bafd
SD		 2927
2928 return status;
2929}
2930
2931int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2932{
84b5dbf3 2933 int status = 0;
e0d3bafd 2934 u32 gpio_logic_value = 0;
84b5dbf3
MCC		 2935 int nCnt = 10;
2936 int nInit = nCnt;
e0d3bafd 2937
cde4362f
MCC		 2938 /* clock stretch; set SCL to input; set SDA to input;
2939 get SCL value till SCL = 1 */
84b5dbf3
MCC		 2940 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2941 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
e0d3bafd
SD		 2942
2943 gpio_logic_value = dev->gpio_val;
6b236a37 2944 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd 2945
84b5dbf3 2946 do {
e0d3bafd 2947 msleep(2);
cde4362f 2948 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
6b236a37 2949 &dev->gpio_val);
84b5dbf3 2950 nCnt--;
b9255176
SD		 2951 } while (((dev->gpio_val &
2952 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2953 (nCnt > 0));
84b5dbf3 2954
cde4362f 2955 if (nCnt == 0)
336fea92 2956 dev_dbg(dev->dev,
b7085c08
MCC		 2957 "No ACK after %d msec -GPIO I2C failed!",
2958 nInit * 10);
e0d3bafd 2959
af901ca1
AGR		 2960 /*
2961 * readAck
2962 * through clock stretch, slave has given a SCL signal,
2963 * so the SDA data can be directly read.
2964 */
6b236a37 2965 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val);
e0d3bafd 2966
84b5dbf3 2967 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
e0d3bafd 2968 dev->gpio_val = gpio_logic_value;
84b5dbf3 2969 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
e0d3bafd
SD		 2970 status = 0;
2971 } else {
2972 dev->gpio_val = gpio_logic_value;
84b5dbf3 2973 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
e0d3bafd
SD		 2974 }
2975
cde4362f
MCC		 2976 /* read SDA end, set the SCL to output 0, after this operation,
2977 SDA direction can be changed. */
e0d3bafd 2978 dev->gpio_val = gpio_logic_value;
84b5dbf3
MCC		 2979 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2980 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
6b236a37 2981 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd
SD		 2982
2983 return status;
2984}
2985
e0d3bafd
SD		 2986int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2987{
84b5dbf3 2988 int status = 0;
e0d3bafd
SD		 2989
2990 /* set SDA to ouput */
84b5dbf3 2991 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
6b236a37 2992 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd
SD		 2993
2994 /* set SCL = 0 (output); set SDA = 0 (output) */
84b5dbf3
MCC		 2995 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2996 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
6b236a37 2997 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd
SD		 2998
2999 /* set SCL = 1 (output); set SDA = 0 (output) */
84b5dbf3 3000 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
6b236a37 3001 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd
SD		 3002
3003 /* set SCL = 0 (output); set SDA = 0 (output) */
84b5dbf3 3004 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
6b236a37 3005 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd
SD		 3006
3007 /* set SDA to input,and then the slave will read data from SDA. */
84b5dbf3 3008 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
6b236a37 3009 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd
SD		 3010
3011 return status;
3012}
3013
3014int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
3015{
84b5dbf3 3016 int status = 0;
e0d3bafd
SD		 3017
3018 /* set scl to output ; set sda to input */
84b5dbf3
MCC		 3019 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
3020 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
6b236a37 3021 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd
SD		 3022
3023 /* set scl to output 0; set sda to input */
84b5dbf3 3024 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
6b236a37 3025 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd
SD		 3026
3027 /* set scl to output 1; set sda to input */
84b5dbf3 3028 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
6b236a37 3029 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
e0d3bafd
SD		 3030
3031 return status;
3032}
3033
cde4362f
MCC		 3034/*****************************************************************************
3035* G P I O I2C related functions *
3036******************************************************************************/
e0d3bafd
SD		 3037/* cx231xx_gpio_i2c_read
3038 * Function to read data from gpio based I2C interface
3039 */
64fbf444 3040int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
e0d3bafd 3041{
84b5dbf3
MCC		 3042 int status = 0;
3043 int i = 0;
e0d3bafd 3044
84b5dbf3 3045 /* get the lock */
e0d3bafd
SD		 3046 mutex_lock(&dev->gpio_i2c_lock);
3047
3048 /* start */
3049 status = cx231xx_gpio_i2c_start(dev);
3050
3051 /* write dev_addr */
84b5dbf3 3052 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
e0d3bafd
SD		 3053
3054 /* readAck */
3055 status = cx231xx_gpio_i2c_read_ack(dev);
3056
84b5dbf3
MCC		 3057 /* read data */
3058 for (i = 0; i < len; i++) {
3059 /* read data */
3060 buf[i] = 0;
3061 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
e0d3bafd 3062
84b5dbf3
MCC		 3063 if ((i + 1) != len) {
3064 /* only do write ack if we more length */
3065 status = cx231xx_gpio_i2c_write_ack(dev);
3066 }
3067 }
e0d3bafd
SD		 3068
3069 /* write NAK - inform reads are complete */
3070 status = cx231xx_gpio_i2c_write_nak(dev);
3071
3072 /* write end */
3073 status = cx231xx_gpio_i2c_end(dev);
3074
3075 /* release the lock */
3076 mutex_unlock(&dev->gpio_i2c_lock);
3077
3078 return status;
3079}
3080
e0d3bafd
SD		 3081/* cx231xx_gpio_i2c_write
3082 * Function to write data to gpio based I2C interface
3083 */
64fbf444 3084int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
e0d3bafd 3085{
84b5dbf3 3086 int i = 0;
e0d3bafd
SD		 3087
3088 /* get the lock */
3089 mutex_lock(&dev->gpio_i2c_lock);
3090
3091 /* start */
da983503 3092 cx231xx_gpio_i2c_start(dev);
e0d3bafd
SD		 3093
3094 /* write dev_addr */
da983503 3095 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
e0d3bafd
SD		 3096
3097 /* read Ack */
da983503 3098 cx231xx_gpio_i2c_read_ack(dev);
e0d3bafd 3099
84b5dbf3 3100 for (i = 0; i < len; i++) {
e0d3bafd 3101 /* Write data */
da983503 3102 cx231xx_gpio_i2c_write_byte(dev, buf[i]);
e0d3bafd 3103
84b5dbf3 3104 /* read Ack */
da983503 3105 cx231xx_gpio_i2c_read_ack(dev);
84b5dbf3 3106 }
e0d3bafd 3107
84b5dbf3 3108 /* write End */
da983503 3109 cx231xx_gpio_i2c_end(dev);
e0d3bafd
SD		 3110
3111 /* release the lock */
3112 mutex_unlock(&dev->gpio_i2c_lock);
3113
3114 return 0;
3115}
Linux kernel - Deliverables
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