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Fix common misspellings
[deliverable/linux.git] / drivers / media / video / cx23885 / cx23885.h
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/pci.h>
23#include <linux/i2c.h>
24#include <linux/i2c-algo-bit.h>
25#include <linux/kdev_t.h>
5a0e3ad6 26#include <linux/slab.h>
d19770e5 27
c0714f6c 28#include <media/v4l2-device.h>
d19770e5
ST		 29#include <media/tuner.h>
30#include <media/tveeprom.h>
409d84f8
TP		 31#include <media/videobuf-dma-sg.h>
32#include <media/videobuf-dvb.h>
6bda9644 33#include <media/rc-core.h>
d19770e5
ST		 34
35#include "btcx-risc.h"
36#include "cx23885-reg.h"
b1b81f1d 37#include "media/cx2341x.h"
d19770e5
ST		 38
39#include <linux/version.h>
40#include <linux/mutex.h>
41
3ff4ad81 42#define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)
d19770e5
ST		 43
44#define UNSET (-1U)
45
46#define CX23885_MAXBOARDS 8
47
d19770e5
ST		 48/* Max number of inputs by card */
49#define MAX_CX23885_INPUT 8
7b888014
ST		 50#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
51#define RESOURCE_OVERLAY 1
52#define RESOURCE_VIDEO 2
53#define RESOURCE_VBI 4
d19770e5 54
d19770e5
ST		 55#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
56
57#define CX23885_BOARD_NOAUTO UNSET
58#define CX23885_BOARD_UNKNOWN 0
59#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
60#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc 61#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa 62#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55 63#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835 64#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166 65#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c 66#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373 67#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7 68#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186 69#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a 70#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8 71#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c 72#define CX23885_BOARD_TBS_6920 14
579943f5 73#define CX23885_BOARD_TEVII_S470 15
c9b8b04b 74#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076 75#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
2074dffa 76#define CX23885_BOARD_HAUPPAUGE_HVR1270 18
d099becb 77#define CX23885_BOARD_HAUPPAUGE_HVR1275 19
19bc5796 78#define CX23885_BOARD_HAUPPAUGE_HVR1255 20
6b926eca 79#define CX23885_BOARD_HAUPPAUGE_HVR1210 21
493b7127 80#define CX23885_BOARD_MYGICA_X8506 22
2365b2d3 81#define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
13697380 82#define CX23885_BOARD_HAUPPAUGE_HVR1850 24
34e383dd 83#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
aee0b24c 84#define CX23885_BOARD_HAUPPAUGE_HVR1290 26
ea5697fe 85#define CX23885_BOARD_MYGICA_X8558PRO 27
0b32d65c 86#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
9028f58f 87#define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
78db8547 88#define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
d19770e5 89
6f8bee9b
ST		 90#define GPIO_0 0x00000001
91#define GPIO_1 0x00000002
92#define GPIO_2 0x00000004
93#define GPIO_3 0x00000008
94#define GPIO_4 0x00000010
95#define GPIO_5 0x00000020
96#define GPIO_6 0x00000040
97#define GPIO_7 0x00000080
98#define GPIO_8 0x00000100
99#define GPIO_9 0x00000200
f659c513
ST		 100#define GPIO_10 0x00000400
101#define GPIO_11 0x00000800
102#define GPIO_12 0x00001000
103#define GPIO_13 0x00002000
104#define GPIO_14 0x00004000
105#define GPIO_15 0x00008000
6f8bee9b 106
7b888014
ST		 107/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
108#define CX23885_NORMS (\
109 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
110 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
111 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
112 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
113
114struct cx23885_fmt {
115 char *name;
116 u32 fourcc; /* v4l2 format id */
117 int depth;
118 int flags;
119 u32 cxformat;
120};
121
122struct cx23885_ctrl {
123 struct v4l2_queryctrl v;
124 u32 off;
125 u32 reg;
126 u32 mask;
127 u32 shift;
128};
129
130struct cx23885_tvnorm {
131 char *name;
132 v4l2_std_id id;
133 u32 cxiformat;
134 u32 cxoformat;
135};
136
137struct cx23885_fh {
138 struct cx23885_dev *dev;
139 enum v4l2_buf_type type;
140 int radio;
141 u32 resources;
142
143 /* video overlay */
144 struct v4l2_window win;
145 struct v4l2_clip *clips;
146 unsigned int nclips;
147
148 /* video capture */
149 struct cx23885_fmt *fmt;
150 unsigned int width, height;
151
152 /* vbi capture */
153 struct videobuf_queue vidq;
154 struct videobuf_queue vbiq;
155
156 /* MPEG Encoder specifics ONLY */
157 struct videobuf_queue mpegq;
158 atomic_t v4l_reading;
159};
160
d19770e5
ST		 161enum cx23885_itype {
162 CX23885_VMUX_COMPOSITE1 = 1,
163 CX23885_VMUX_COMPOSITE2,
164 CX23885_VMUX_COMPOSITE3,
165 CX23885_VMUX_COMPOSITE4,
166 CX23885_VMUX_SVIDEO,
dac65fa1 167 CX23885_VMUX_COMPONENT,
d19770e5
ST		 168 CX23885_VMUX_TELEVISION,
169 CX23885_VMUX_CABLE,
170 CX23885_VMUX_DVB,
171 CX23885_VMUX_DEBUG,
172 CX23885_RADIO,
173};
174
579f1163
ST		 175enum cx23885_src_sel_type {
176 CX23885_SRC_SEL_EXT_656_VIDEO = 0,
177 CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
178};
179
d19770e5
ST		 180/* buffer for one video frame */
181struct cx23885_buffer {
182 /* common v4l buffer stuff -- must be first */
183 struct videobuf_buffer vb;
184
185 /* cx23885 specific */
186 unsigned int bpl;
187 struct btcx_riscmem risc;
188 struct cx23885_fmt *fmt;
189 u32 count;
190};
191
192struct cx23885_input {
193 enum cx23885_itype type;
194 unsigned int vmux;
195 u32 gpio0, gpio1, gpio2, gpio3;
196};
197
661c7e44
ST		 198typedef enum {
199 CX23885_MPEG_UNDEFINED = 0,
7b888014
ST		 200 CX23885_MPEG_DVB,
201 CX23885_ANALOG_VIDEO,
b1b81f1d 202 CX23885_MPEG_ENCODER,
661c7e44
ST		 203} port_t;
204
d19770e5
ST		 205struct cx23885_board {
206 char *name;
7b888014 207 port_t porta, portb, portc;
10d0dcd7 208 int num_fds_portb, num_fds_portc;
7b888014
ST		 209 unsigned int tuner_type;
210 unsigned int radio_type;
211 unsigned char tuner_addr;
212 unsigned char radio_addr;
557f48d5 213 unsigned int tuner_bus;
c7712613
ST		 214
215 /* Vendors can and do run the PCIe bridge at different
216 * clock rates, driven physically by crystals on the PCBs.
25985edc 217 * The core has to accommodate this. This allows the user
c7712613
ST		 218 * to add new boards with new frequencys. The value is
219 * expressed in Hz.
220 *
221 * The core framework will default this value based on
222 * current designs, but it can vary.
223 */
224 u32 clk_freq;
d19770e5 225 struct cx23885_input input[MAX_CX23885_INPUT];
78db8547 226 int ci_type; /* for NetUP */
d19770e5
ST		 227};
228
229struct cx23885_subid {
230 u16 subvendor;
231 u16 subdevice;
232 u32 card;
233};
234
235struct cx23885_i2c {
236 struct cx23885_dev *dev;
237
238 int nr;
239
240 /* i2c i/o */
241 struct i2c_adapter i2c_adap;
242 struct i2c_algo_bit_data i2c_algo;
243 struct i2c_client i2c_client;
244 u32 i2c_rc;
245
246 /* 885 registers used for raw addess */
247 u32 i2c_period;
248 u32 reg_ctrl;
249 u32 reg_stat;
250 u32 reg_addr;
251 u32 reg_rdata;
252 u32 reg_wdata;
253};
254
255struct cx23885_dmaqueue {
256 struct list_head active;
257 struct list_head queued;
258 struct timer_list timeout;
259 struct btcx_riscmem stopper;
260 u32 count;
261};
262
263struct cx23885_tsport {
264 struct cx23885_dev *dev;
265
266 int nr;
267 int sram_chno;
268
363c35fc 269 struct videobuf_dvb_frontends frontends;
d19770e5
ST		 270
271 /* dma queues */
272 struct cx23885_dmaqueue mpegq;
273 u32 ts_packet_size;
274 u32 ts_packet_count;
275
276 int width;
277 int height;
278
279 spinlock_t slock;
280
281 /* registers */
282 u32 reg_gpcnt;
283 u32 reg_gpcnt_ctl;
284 u32 reg_dma_ctl;
285 u32 reg_lngth;
286 u32 reg_hw_sop_ctrl;
287 u32 reg_gen_ctrl;
288 u32 reg_bd_pkt_status;
289 u32 reg_sop_status;
290 u32 reg_fifo_ovfl_stat;
291 u32 reg_vld_misc;
292 u32 reg_ts_clk_en;
293 u32 reg_ts_int_msk;
a6a3f140 294 u32 reg_ts_int_stat;
579f1163 295 u32 reg_src_sel;
d19770e5
ST		 296
297 /* Default register vals */
298 int pci_irqmask;
299 u32 dma_ctl_val;
300 u32 ts_int_msk_val;
301 u32 gen_ctrl_val;
302 u32 ts_clk_en_val;
579f1163 303 u32 src_sel_val;
b1b81f1d
ST		 304 u32 vld_misc_val;
305 u32 hw_sop_ctrl_val;
a739a7e4
ST		 306
307 /* Allow a single tsport to have multiple frontends */
308 u32 num_frontends;
78db8547 309 void (*gate_ctrl)(struct cx23885_tsport *port, int open);
5a23b076 310 void *port_priv;
d19770e5
ST		 311};
312
43c24078
AW		 313struct cx23885_kernel_ir {
314 struct cx23885_dev *cx;
eeefae53
AW		 315 char *name;
316 char *phys;
317
d8b4b582 318 struct rc_dev *rc;
eeefae53
AW		 319};
320
d19770e5 321struct cx23885_dev {
d19770e5 322 atomic_t refcount;
c0714f6c 323 struct v4l2_device v4l2_dev;
d19770e5
ST		 324
325 /* pci stuff */
326 struct pci_dev *pci;
327 unsigned char pci_rev, pci_lat;
328 int pci_bus, pci_slot;
329 u32 __iomem *lmmio;
330 u8 __iomem *bmmio;
d19770e5 331 int pci_irqmask;
dbe83a3b 332 spinlock_t pci_irqmask_lock; /* protects mask reg too */
0ac5881a 333 int hwrevision;
d19770e5 334
c7712613
ST		 335 /* This valud is board specific and is used to configure the
336 * AV core so we see nice clean and stable video and audio. */
337 u32 clk_freq;
338
44a6481d 339 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5
ST		 340 struct cx23885_i2c i2c_bus[3];
341
342 int nr;
343 struct mutex lock;
8386c27f 344 struct mutex gpio_lock;
d19770e5
ST		 345
346 /* board details */
347 unsigned int board;
348 char name[32];
349
a6a3f140 350 struct cx23885_tsport ts1, ts2;
d19770e5
ST		 351
352 /* sram configuration */
353 struct sram_channel *sram_channels;
e133be0f
ST		 354
355 enum {
356 CX23885_BRIDGE_UNDEFINED = 0,
357 CX23885_BRIDGE_885 = 885,
358 CX23885_BRIDGE_887 = 887,
25ea66e2 359 CX23885_BRIDGE_888 = 888,
e133be0f 360 } bridge;
7b888014
ST		 361
362 /* Analog video */
363 u32 resources;
364 unsigned int input;
365 u32 tvaudio;
366 v4l2_std_id tvnorm;
367 unsigned int tuner_type;
368 unsigned char tuner_addr;
557f48d5 369 unsigned int tuner_bus;
7b888014
ST		 370 unsigned int radio_type;
371 unsigned char radio_addr;
372 unsigned int has_radio;
0d5a19f1 373 struct v4l2_subdev *sd_cx25840;
e5514f10 374 struct work_struct cx25840_work;
f59ad611
AW		 375
376 /* Infrared */
377 struct v4l2_subdev *sd_ir;
378 struct work_struct ir_rx_work;
379 unsigned long ir_rx_notifications;
380 struct work_struct ir_tx_work;
381 unsigned long ir_tx_notifications;
7b888014 382
43c24078 383 struct cx23885_kernel_ir *kernel_ir;
dbda8f70
AW		 384 atomic_t ir_input_stopping;
385
7b888014
ST		 386 /* V4l */
387 u32 freq;
388 struct video_device *video_dev;
389 struct video_device *vbi_dev;
390 struct video_device *radio_dev;
391
392 struct cx23885_dmaqueue vidq;
393 struct cx23885_dmaqueue vbiq;
394 spinlock_t slock;
b1b81f1d
ST		 395
396 /* MPEG Encoder ONLY settings */
397 u32 cx23417_mailbox;
398 struct cx2341x_mpeg_params mpeg_params;
399 struct video_device *v4l_device;
400 atomic_t v4l_reader_count;
401 struct cx23885_tvnorm encodernorm;
402
d19770e5
ST		 403};
404
c0714f6c
HV		 405static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
406{
407 return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
408}
409
0d5a19f1
HV		 410#define call_all(dev, o, f, args...) \
411 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
412
d6b1850d
AW		 413#define CX23885_HW_888_IR (1 << 0)
414#define CX23885_HW_AV_CORE (1 << 1)
29f8a0a5
AW		 415
416#define call_hw(dev, grpid, o, f, args...) \
417 v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
418
419extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
420
d19770e5
ST		 421#define SRAM_CH01 0 /* Video A */
422#define SRAM_CH02 1 /* VBI A */
423#define SRAM_CH03 2 /* Video B */
424#define SRAM_CH04 3 /* Transport via B */
425#define SRAM_CH05 4 /* VBI B */
426#define SRAM_CH06 5 /* Video C */
427#define SRAM_CH07 6 /* Transport via C */
428#define SRAM_CH08 7 /* Audio Internal A */
429#define SRAM_CH09 8 /* Audio Internal B */
430#define SRAM_CH10 9 /* Audio External */
431#define SRAM_CH11 10 /* COMB_3D_N */
432#define SRAM_CH12 11 /* Comb 3D N1 */
433#define SRAM_CH13 12 /* Comb 3D N2 */
434#define SRAM_CH14 13 /* MOE Vid */
435#define SRAM_CH15 14 /* MOE RSLT */
436
437struct sram_channel {
438 char *name;
439 u32 cmds_start;
440 u32 ctrl_start;
441 u32 cdt;
1ebcad77 442 u32 fifo_start;
d19770e5
ST		 443 u32 fifo_size;
444 u32 ptr1_reg;
445 u32 ptr2_reg;
446 u32 cnt1_reg;
447 u32 cnt2_reg;
448 u32 jumponly;
449};
450
451/* ----------------------------------------------------------- */
452
453#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51 454#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5 455
9c8ced51 456#define cx_andor(reg, mask, value) \
d19770e5
ST		 457 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
458 ((value) & (mask)), dev->lmmio+((reg)>>2))
459
9c8ced51
ST		 460#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
461#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5 462
d19770e5 463/* ----------------------------------------------------------- */
7b888014
ST		 464/* cx23885-core.c */
465
466extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
467 struct sram_channel *ch,
468 unsigned int bpl, u32 risc);
469
470extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
471 struct sram_channel *ch);
d19770e5 472
7b888014
ST		 473extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
474 u32 reg, u32 mask, u32 value);
475
476extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
477 struct scatterlist *sglist,
478 unsigned int top_offset, unsigned int bottom_offset,
479 unsigned int bpl, unsigned int padding, unsigned int lines);
480
481void cx23885_cancel_buffers(struct cx23885_tsport *port);
482
483extern int cx23885_restart_queue(struct cx23885_tsport *port,
484 struct cx23885_dmaqueue *q);
485
486extern void cx23885_wakeup(struct cx23885_tsport *port,
487 struct cx23885_dmaqueue *q, u32 count);
488
6f8bee9b
ST		 489extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
490extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
09ea33e5 491extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
6f8bee9b
ST		 492extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
493 int asoutput);
494
dbe83a3b
AW		 495extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
496extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
497extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
498extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
7b888014
ST		 499
500/* ----------------------------------------------------------- */
501/* cx23885-cards.c */
d19770e5
ST		 502extern struct cx23885_board cx23885_boards[];
503extern const unsigned int cx23885_bcount;
504
505extern struct cx23885_subid cx23885_subids[];
506extern const unsigned int cx23885_idcount;
507
9c8ced51
ST		 508extern int cx23885_tuner_callback(void *priv, int component,
509 int command, int arg);
d19770e5 510extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140 511extern int cx23885_ir_init(struct cx23885_dev *dev);
f59ad611
AW		 512extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
513extern void cx23885_ir_fini(struct cx23885_dev *dev);
a6a3f140 514extern void cx23885_gpio_setup(struct cx23885_dev *dev);
d19770e5
ST		 515extern void cx23885_card_setup(struct cx23885_dev *dev);
516extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
517
518extern int cx23885_dvb_register(struct cx23885_tsport *port);
519extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
520
44a6481d
MK		 521extern int cx23885_buf_prepare(struct videobuf_queue *q,
522 struct cx23885_tsport *port,
523 struct cx23885_buffer *buf,
524 enum v4l2_field field);
44a6481d
MK		 525extern void cx23885_buf_queue(struct cx23885_tsport *port,
526 struct cx23885_buffer *buf);
527extern void cx23885_free_buffer(struct videobuf_queue *q,
528 struct cx23885_buffer *buf);
d19770e5
ST		 529
530/* ----------------------------------------------------------- */
7b888014
ST		 531/* cx23885-video.c */
532/* Video */
533extern int cx23885_video_register(struct cx23885_dev *dev);
534extern void cx23885_video_unregister(struct cx23885_dev *dev);
535extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
536
537/* ----------------------------------------------------------- */
538/* cx23885-vbi.c */
539extern int cx23885_vbi_fmt(struct file *file, void *priv,
540 struct v4l2_format *f);
541extern void cx23885_vbi_timeout(unsigned long data);
542extern struct videobuf_queue_ops cx23885_vbi_qops;
543
d19770e5
ST		 544/* cx23885-i2c.c */
545extern int cx23885_i2c_register(struct cx23885_i2c *bus);
546extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665 547extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5 548
b1b81f1d
ST		 549/* ----------------------------------------------------------- */
550/* cx23885-417.c */
551extern int cx23885_417_register(struct cx23885_dev *dev);
552extern void cx23885_417_unregister(struct cx23885_dev *dev);
553extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
554extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
555extern void cx23885_mc417_init(struct cx23885_dev *dev);
556extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
557extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
74618244
AW		 558extern int mc417_register_read(struct cx23885_dev *dev,
559 u16 address, u32 *value);
560extern int mc417_register_write(struct cx23885_dev *dev,
561 u16 address, u32 value);
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ST		 562extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
563extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
564extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
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ST		 565
566
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ST		 567/* ----------------------------------------------------------- */
568/* tv norms */
569
570static inline unsigned int norm_maxw(v4l2_std_id norm)
571{
572 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
573}
574
575static inline unsigned int norm_maxh(v4l2_std_id norm)
576{
577 return (norm & V4L2_STD_625_50) ? 576 : 480;
578}
579
580static inline unsigned int norm_swidth(v4l2_std_id norm)
581{
582 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
583}
Linux kernel - Deliverables
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