Commit | Line | Data |
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9cb2173e EG |
1 | /* |
2 | * STK1160 driver | |
3 | * | |
4 | * Copyright (C) 2012 Ezequiel Garcia | |
5 | * <elezegarcia--a.t--gmail.com> | |
6 | * | |
7 | * Based on Easycap driver by R.M. Thomas | |
8 | * Copyright (C) 2010 R.M. Thomas | |
9 | * <rmthomas--a.t--sciolus.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | */ | |
22 | ||
23 | /* GPIO Control */ | |
24 | #define STK1160_GCTRL 0x000 | |
25 | ||
26 | /* Remote Wakup Control */ | |
27 | #define STK1160_RMCTL 0x00c | |
28 | ||
29 | /* | |
30 | * Decoder Control Register: | |
31 | * This byte controls capture start/stop | |
32 | * with bit #7 (0x?? OR 0x80 to activate). | |
33 | */ | |
34 | #define STK1160_DCTRL 0x100 | |
35 | ||
36 | /* Capture Frame Start Position */ | |
37 | #define STK116_CFSPO 0x110 | |
38 | #define STK116_CFSPO_STX_L 0x110 | |
39 | #define STK116_CFSPO_STX_H 0x111 | |
40 | #define STK116_CFSPO_STY_L 0x112 | |
41 | #define STK116_CFSPO_STY_H 0x113 | |
42 | ||
43 | /* Capture Frame End Position */ | |
44 | #define STK116_CFEPO 0x114 | |
45 | #define STK116_CFEPO_ENX_L 0x114 | |
46 | #define STK116_CFEPO_ENX_H 0x115 | |
47 | #define STK116_CFEPO_ENY_L 0x116 | |
48 | #define STK116_CFEPO_ENY_H 0x117 | |
49 | ||
50 | /* Serial Interface Control */ | |
51 | #define STK1160_SICTL 0x200 | |
52 | #define STK1160_SICTL_CD 0x202 | |
53 | #define STK1160_SICTL_SDA 0x203 | |
54 | ||
55 | /* Serial Bus Write */ | |
56 | #define STK1160_SBUSW 0x204 | |
57 | #define STK1160_SBUSW_WA 0x204 | |
58 | #define STK1160_SBUSW_WD 0x205 | |
59 | ||
60 | /* Serial Bus Read */ | |
61 | #define STK1160_SBUSR 0x208 | |
62 | #define STK1160_SBUSR_RA 0x208 | |
63 | #define STK1160_SBUSR_RD 0x209 | |
64 | ||
65 | /* Alternate Serial Inteface Control */ | |
66 | #define STK1160_ASIC 0x2fc | |
67 | ||
68 | /* PLL Select Options */ | |
69 | #define STK1160_PLLSO 0x018 | |
70 | ||
71 | /* PLL Frequency Divider */ | |
72 | #define STK1160_PLLFD 0x01c | |
73 | ||
74 | /* Timing Generator */ | |
75 | #define STK1160_TIGEN 0x300 | |
76 | ||
77 | /* Timing Control Parameter */ | |
78 | #define STK1160_TICTL 0x350 | |
79 | ||
80 | /* AC97 Audio Control */ | |
81 | #define STK1160_AC97CTL_0 0x500 | |
82 | #define STK1160_AC97CTL_1 0x504 | |
83 | ||
84 | /* Use [0:6] bits of register 0x504 to set codec command address */ | |
85 | #define STK1160_AC97_ADDR 0x504 | |
86 | /* Use [16:31] bits of register 0x500 to set codec command data */ | |
87 | #define STK1160_AC97_CMD 0x502 | |
88 | ||
89 | /* Audio I2S Interface */ | |
90 | #define STK1160_I2SCTL 0x50c | |
91 | ||
92 | /* EEPROM Interface */ | |
93 | #define STK1160_EEPROM_SZ 0x5f0 |