[deliverable/linux.git] / drivers / media / video / vpx3220.c

/*
 * vpx3220a, vpx3216b & vpx3214c video decoder driver version 0.0.1
 *
 * Copyright (C) 2001 Laurent Pinchart <lpinchart@freegates.be>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <asm/uaccess.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <media/v4l2-device.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-ctrls.h>

MODULE_DESCRIPTION("vpx3220a/vpx3216b/vpx3214c video decoder driver");
MODULE_AUTHOR("Laurent Pinchart");
MODULE_LICENSE("GPL");

static int debug;
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0-1)");


#define VPX_TIMEOUT_COUNT  10

/* ----------------------------------------------------------------------- */

struct vpx3220 {
	struct v4l2_subdev sd;
	struct v4l2_ctrl_handler hdl;
	unsigned char reg[255];

	v4l2_std_id norm;
	int ident;
	int input;
	int enable;
};

static inline struct vpx3220 *to_vpx3220(struct v4l2_subdev *sd)
{
	return container_of(sd, struct vpx3220, sd);
}

static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
{
	return &container_of(ctrl->handler, struct vpx3220, hdl)->sd;
}

static char *inputs[] = { "internal", "composite", "svideo" };

/* ----------------------------------------------------------------------- */

static inline int vpx3220_write(struct v4l2_subdev *sd, u8 reg, u8 value)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	struct vpx3220 *decoder = i2c_get_clientdata(client);

	decoder->reg[reg] = value;
	return i2c_smbus_write_byte_data(client, reg, value);
}

static inline int vpx3220_read(struct v4l2_subdev *sd, u8 reg)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	return i2c_smbus_read_byte_data(client, reg);
}

static int vpx3220_fp_status(struct v4l2_subdev *sd)
{
	unsigned char status;
	unsigned int i;

	for (i = 0; i < VPX_TIMEOUT_COUNT; i++) {
		status = vpx3220_read(sd, 0x29);

		if (!(status & 4))
			return 0;

		udelay(10);

		if (need_resched())
			cond_resched();
	}

	return -1;
}

static int vpx3220_fp_write(struct v4l2_subdev *sd, u8 fpaddr, u16 data)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	/* Write the 16-bit address to the FPWR register */
	if (i2c_smbus_write_word_data(client, 0x27, swab16(fpaddr)) == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	if (vpx3220_fp_status(sd) < 0)
		return -1;

	/* Write the 16-bit data to the FPDAT register */
	if (i2c_smbus_write_word_data(client, 0x28, swab16(data)) == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	return 0;
}

static u16 vpx3220_fp_read(struct v4l2_subdev *sd, u16 fpaddr)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	s16 data;

	/* Write the 16-bit address to the FPRD register */
	if (i2c_smbus_write_word_data(client, 0x26, swab16(fpaddr)) == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	if (vpx3220_fp_status(sd) < 0)
		return -1;

	/* Read the 16-bit data from the FPDAT register */
	data = i2c_smbus_read_word_data(client, 0x28);
	if (data == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	return swab16(data);
}

static int vpx3220_write_block(struct v4l2_subdev *sd, const u8 *data, unsigned int len)
{
	u8 reg;
	int ret = -1;

	while (len >= 2) {
		reg = *data++;
		ret = vpx3220_write(sd, reg, *data++);
		if (ret < 0)
			break;
		len -= 2;
	}

	return ret;
}

static int vpx3220_write_fp_block(struct v4l2_subdev *sd,
		const u16 *data, unsigned int len)
{
	u8 reg;
	int ret = 0;

	while (len > 1) {
		reg = *data++;
		ret |= vpx3220_fp_write(sd, reg, *data++);
		len -= 2;
	}

	return ret;
}

/* ---------------------------------------------------------------------- */

static const unsigned short init_ntsc[] = {
	0x1c, 0x00,		/* NTSC tint angle */
	0x88, 17,		/* Window 1 vertical */
	0x89, 240,		/* Vertical lines in */
	0x8a, 240,		/* Vertical lines out */
	0x8b, 000,		/* Horizontal begin */
	0x8c, 640,		/* Horizontal length */
	0x8d, 640,		/* Number of pixels */
	0x8f, 0xc00,		/* Disable window 2 */
	0xf0, 0x73,		/* 13.5 MHz transport, Forced
				 * mode, latch windows */
	0xf2, 0x13,		/* NTSC M, composite input */
	0xe7, 0x1e1,		/* Enable vertical standard
				 * locking @ 240 lines */
};

static const unsigned short init_pal[] = {
	0x88, 23,		/* Window 1 vertical begin */
	0x89, 288,		/* Vertical lines in (16 lines
				 * skipped by the VFE) */
	0x8a, 288,		/* Vertical lines out (16 lines
				 * skipped by the VFE) */
	0x8b, 16,		/* Horizontal begin */
	0x8c, 768,		/* Horizontal length */
	0x8d, 784, 		/* Number of pixels
				 * Must be >= Horizontal begin + Horizontal length */
	0x8f, 0xc00,		/* Disable window 2 */
	0xf0, 0x77,		/* 13.5 MHz transport, Forced
				 * mode, latch windows */
	0xf2, 0x3d1,		/* PAL B,G,H,I, composite input */
	0xe7, 0x241,		/* PAL/SECAM set to 288 lines */
};

static const unsigned short init_secam[] = {
	0x88, 23,		/* Window 1 vertical begin */
	0x89, 288,		/* Vertical lines in (16 lines
				 * skipped by the VFE) */
	0x8a, 288,		/* Vertical lines out (16 lines
				 * skipped by the VFE) */
	0x8b, 16,		/* Horizontal begin */
	0x8c, 768,		/* Horizontal length */
	0x8d, 784,		/* Number of pixels
				 * Must be >= Horizontal begin + Horizontal length */
	0x8f, 0xc00,		/* Disable window 2 */
	0xf0, 0x77,		/* 13.5 MHz transport, Forced
				 * mode, latch windows */
	0xf2, 0x3d5,		/* SECAM, composite input */
	0xe7, 0x241,		/* PAL/SECAM set to 288 lines */
};

static const unsigned char init_common[] = {
	0xf2, 0x00,		/* Disable all outputs */
	0x33, 0x0d,		/* Luma : VIN2, Chroma : CIN
				 * (clamp off) */
	0xd8, 0xa8,		/* HREF/VREF active high, VREF
				 * pulse = 2, Odd/Even flag */
	0x20, 0x03,		/* IF compensation 0dB/oct */
	0xe0, 0xff,		/* Open up all comparators */
	0xe1, 0x00,
	0xe2, 0x7f,
	0xe3, 0x80,
	0xe4, 0x7f,
	0xe5, 0x80,
	0xe6, 0x00,		/* Brightness set to 0 */
	0xe7, 0xe0,		/* Contrast to 1.0, noise shaping
				 * 10 to 8 2-bit error diffusion */
	0xe8, 0xf8,		/* YUV422, CbCr binary offset,
				 * ... (p.32) */
	0xea, 0x18,		/* LLC2 connected, output FIFO
				 * reset with VACTintern */
	0xf0, 0x8a,		/* Half full level to 10, bus
				 * shuffler [7:0, 23:16, 15:8] */
	0xf1, 0x18,		/* Single clock, sync mode, no
				 * FE delay, no HLEN counter */
	0xf8, 0x12,		/* Port A, PIXCLK, HF# & FE#
				 * strength to 2 */
	0xf9, 0x24,		/* Port B, HREF, VREF, PREF &
				 * ALPHA strength to 4 */
};

static const unsigned short init_fp[] = {
	0x59, 0,
	0xa0, 2070,		/* ACC reference */
	0xa3, 0,
	0xa4, 0,
	0xa8, 30,
	0xb2, 768,
	0xbe, 27,
	0x58, 0,
	0x26, 0,
	0x4b, 0x298,		/* PLL gain */
};


static int vpx3220_init(struct v4l2_subdev *sd, u32 val)
{
	struct vpx3220 *decoder = to_vpx3220(sd);

	vpx3220_write_block(sd, init_common, sizeof(init_common));
	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	if (decoder->norm & V4L2_STD_NTSC)
		vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
	else if (decoder->norm & V4L2_STD_PAL)
		vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	else if (decoder->norm & V4L2_STD_SECAM)
		vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
	else
		vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	return 0;
}

static int vpx3220_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd)
{
	int res = V4L2_IN_ST_NO_SIGNAL, status;
	v4l2_std_id std = 0;

	status = vpx3220_fp_read(sd, 0x0f3);

	v4l2_dbg(1, debug, sd, "status: 0x%04x\n", status);

	if (status < 0)
		return status;

	if ((status & 0x20) == 0) {
		res = 0;

		switch (status & 0x18) {
		case 0x00:
		case 0x10:
		case 0x14:
		case 0x18:
			std = V4L2_STD_PAL;
			break;

		case 0x08:
			std = V4L2_STD_SECAM;
			break;

		case 0x04:
		case 0x0c:
		case 0x1c:
			std = V4L2_STD_NTSC;
			break;
		}
	}
	if (pstd)
		*pstd = std;
	if (pstatus)
		*pstatus = status;
	return 0;
}

static int vpx3220_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
{
	v4l2_dbg(1, debug, sd, "querystd\n");
	return vpx3220_status(sd, NULL, std);
}

static int vpx3220_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
	v4l2_dbg(1, debug, sd, "g_input_status\n");
	return vpx3220_status(sd, status, NULL);
}

static int vpx3220_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
{
	struct vpx3220 *decoder = to_vpx3220(sd);
	int temp_input;

	/* Here we back up the input selection because it gets
	   overwritten when we fill the registers with the
	   chosen video norm */
	temp_input = vpx3220_fp_read(sd, 0xf2);

	v4l2_dbg(1, debug, sd, "s_std %llx\n", (unsigned long long)std);
	if (std & V4L2_STD_NTSC) {
		vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
		v4l2_dbg(1, debug, sd, "norm switched to NTSC\n");
	} else if (std & V4L2_STD_PAL) {
		vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
		v4l2_dbg(1, debug, sd, "norm switched to PAL\n");
	} else if (std & V4L2_STD_SECAM) {
		vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
		v4l2_dbg(1, debug, sd, "norm switched to SECAM\n");
	} else {
		return -EINVAL;
	}

	decoder->norm = std;

	/* And here we set the backed up video input again */
	vpx3220_fp_write(sd, 0xf2, temp_input | 0x0010);
	udelay(10);
	return 0;
}

static int vpx3220_s_routing(struct v4l2_subdev *sd,
			     u32 input, u32 output, u32 config)
{
	int data;

	/* RJ:   input = 0: ST8 (PCTV) input
		 input = 1: COMPOSITE  input
		 input = 2: SVHS       input  */

	const int input_vals[3][2] = {
		{0x0c, 0},
		{0x0d, 0},
		{0x0e, 1}
	};

	if (input > 2)
		return -EINVAL;

	v4l2_dbg(1, debug, sd, "input switched to %s\n", inputs[input]);

	vpx3220_write(sd, 0x33, input_vals[input][0]);

	data = vpx3220_fp_read(sd, 0xf2) & ~(0x0020);
	if (data < 0)
		return data;
	/* 0x0010 is required to latch the setting */
	vpx3220_fp_write(sd, 0xf2,
			data | (input_vals[input][1] << 5) | 0x0010);

	udelay(10);
	return 0;
}

static int vpx3220_s_stream(struct v4l2_subdev *sd, int enable)
{
	v4l2_dbg(1, debug, sd, "s_stream %s\n", enable ? "on" : "off");

	vpx3220_write(sd, 0xf2, (enable ? 0x1b : 0x00));
	return 0;
}

static int vpx3220_s_ctrl(struct v4l2_ctrl *ctrl)
{
	struct v4l2_subdev *sd = to_sd(ctrl);

	switch (ctrl->id) {
	case V4L2_CID_BRIGHTNESS:
		vpx3220_write(sd, 0xe6, ctrl->val);
		return 0;
	case V4L2_CID_CONTRAST:
		/* Bit 7 and 8 is for noise shaping */
		vpx3220_write(sd, 0xe7, ctrl->val + 192);
		return 0;
	case V4L2_CID_SATURATION:
		vpx3220_fp_write(sd, 0xa0, ctrl->val);
		return 0;
	case V4L2_CID_HUE:
		vpx3220_fp_write(sd, 0x1c, ctrl->val);
		return 0;
	}
	return -EINVAL;
}

static int vpx3220_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
{
	struct vpx3220 *decoder = to_vpx3220(sd);
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	return v4l2_chip_ident_i2c_client(client, chip, decoder->ident, 0);
}

/* ----------------------------------------------------------------------- */

static const struct v4l2_ctrl_ops vpx3220_ctrl_ops = {
	.s_ctrl = vpx3220_s_ctrl,
};

static const struct v4l2_subdev_core_ops vpx3220_core_ops = {
	.g_chip_ident = vpx3220_g_chip_ident,
	.init = vpx3220_init,
	.g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
	.try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
	.s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
	.g_ctrl = v4l2_subdev_g_ctrl,
	.s_ctrl = v4l2_subdev_s_ctrl,
	.queryctrl = v4l2_subdev_queryctrl,
	.querymenu = v4l2_subdev_querymenu,
	.s_std = vpx3220_s_std,
};

static const struct v4l2_subdev_video_ops vpx3220_video_ops = {
	.s_routing = vpx3220_s_routing,
	.s_stream = vpx3220_s_stream,
	.querystd = vpx3220_querystd,
	.g_input_status = vpx3220_g_input_status,
};

static const struct v4l2_subdev_ops vpx3220_ops = {
	.core = &vpx3220_core_ops,
	.video = &vpx3220_video_ops,
};

/* -----------------------------------------------------------------------
 * Client management code
 */

static int vpx3220_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	struct vpx3220 *decoder;
	struct v4l2_subdev *sd;
	const char *name = NULL;
	u8 ver;
	u16 pn;

	/* Check if the adapter supports the needed features */
	if (!i2c_check_functionality(client->adapter,
		I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA))
		return -ENODEV;

	decoder = kzalloc(sizeof(struct vpx3220), GFP_KERNEL);
	if (decoder == NULL)
		return -ENOMEM;
	sd = &decoder->sd;
	v4l2_i2c_subdev_init(sd, client, &vpx3220_ops);
	decoder->norm = V4L2_STD_PAL;
	decoder->input = 0;
	decoder->enable = 1;
	v4l2_ctrl_handler_init(&decoder->hdl, 4);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_CONTRAST, 0, 63, 1, 32);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_SATURATION, 0, 4095, 1, 2048);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_HUE, -512, 511, 1, 0);
	sd->ctrl_handler = &decoder->hdl;
	if (decoder->hdl.error) {
		int err = decoder->hdl.error;

		v4l2_ctrl_handler_free(&decoder->hdl);
		kfree(decoder);
		return err;
	}
	v4l2_ctrl_handler_setup(&decoder->hdl);

	ver = i2c_smbus_read_byte_data(client, 0x00);
	pn = (i2c_smbus_read_byte_data(client, 0x02) << 8) +
		i2c_smbus_read_byte_data(client, 0x01);
	decoder->ident = V4L2_IDENT_VPX3220A;
	if (ver == 0xec) {
		switch (pn) {
		case 0x4680:
			name = "vpx3220a";
			break;
		case 0x4260:
			name = "vpx3216b";
			decoder->ident = V4L2_IDENT_VPX3216B;
			break;
		case 0x4280:
			name = "vpx3214c";
			decoder->ident = V4L2_IDENT_VPX3214C;
			break;
		}
	}
	if (name)
		v4l2_info(sd, "%s found @ 0x%x (%s)\n", name,
			client->addr << 1, client->adapter->name);
	else
		v4l2_info(sd, "chip (%02x:%04x) found @ 0x%x (%s)\n",
			ver, pn, client->addr << 1, client->adapter->name);

	vpx3220_write_block(sd, init_common, sizeof(init_common));
	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	/* Default to PAL */
	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	return 0;
}

static int vpx3220_remove(struct i2c_client *client)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
	struct vpx3220 *decoder = to_vpx3220(sd);

	v4l2_device_unregister_subdev(sd);
	v4l2_ctrl_handler_free(&decoder->hdl);
	kfree(decoder);
	return 0;
}

static const struct i2c_device_id vpx3220_id[] = {
	{ "vpx3220a", 0 },
	{ "vpx3216b", 0 },
	{ "vpx3214c", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, vpx3220_id);

static struct i2c_driver vpx3220_driver = {
	.driver = {
		.owner	= THIS_MODULE,
		.name	= "vpx3220",
	},
	.probe		= vpx3220_probe,
	.remove		= vpx3220_remove,
	.id_table	= vpx3220_id,
};

static __init int init_vpx3220(void)
{
	return i2c_add_driver(&vpx3220_driver);
}

static __exit void exit_vpx3220(void)
{
	i2c_del_driver(&vpx3220_driver);
}

module_init(init_vpx3220);
module_exit(exit_vpx3220);
Commit	Line	Data
d56410e0	1	/*
1da177e4 LT	2	* vpx3220a, vpx3216b & vpx3214c video decoder driver version 0.0.1
	3	*
	4	* Copyright (C) 2001 Laurent Pinchart <lpinchart@freegates.be>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#include <linux/module.h>
	22	#include <linux/init.h>
	23	#include <linux/delay.h>
	24	#include <linux/types.h>
5a0e3ad6	25	#include <linux/slab.h>
1da177e4	26	#include <asm/uaccess.h>
1da177e4	27	#include <linux/i2c.h>
107063c6	28	#include <linux/videodev2.h>
7e5eaadc HV	29	#include <media/v4l2-device.h>
7e5eaadc HV	30	#include <media/v4l2-chip-ident.h>
9a775323	31	#include <media/v4l2-ctrls.h>
1da177e4	32
23848b65 HV	33	MODULE_DESCRIPTION("vpx3220a/vpx3216b/vpx3214c video decoder driver");
	34	MODULE_AUTHOR("Laurent Pinchart");
	35	MODULE_LICENSE("GPL");
1da177e4	36
ff699e6b	37	static int debug;
1da177e4 LT	38	module_param(debug, int, 0);
	39	MODULE_PARM_DESC(debug, "Debug level (0-1)");
	40
7e5eaadc	41
1da177e4 LT	42	#define VPX_TIMEOUT_COUNT 10
	43
	44	/* ----------------------------------------------------------------------- */
	45
	46	struct vpx3220 {
7e5eaadc	47	struct v4l2_subdev sd;
9a775323	48	struct v4l2_ctrl_handler hdl;
1da177e4 LT	49	unsigned char reg[255];
1da177e4 LT	50
107063c6	51	v4l2_std_id norm;
7e5eaadc	52	int ident;
1da177e4 LT	53	int input;
1da177e4 LT	54	int enable;
1da177e4 LT	55	};
1da177e4 LT	56
7e5eaadc HV	57	static inline struct vpx3220 to_vpx3220(struct v4l2_subdev sd)
	58	{
	59	return container_of(sd, struct vpx3220, sd);
	60	}
	61
9a775323 HV	62	static inline struct v4l2_subdev to_sd(struct v4l2_ctrl ctrl)
	63	{
	64	return &container_of(ctrl->handler, struct vpx3220, hdl)->sd;
	65	}
	66
1da177e4 LT	67	static char *inputs[] = { "internal", "composite", "svideo" };
	68
	69	/* ----------------------------------------------------------------------- */
23848b65	70
7e5eaadc	71	static inline int vpx3220_write(struct v4l2_subdev *sd, u8 reg, u8 value)
1da177e4	72	{
7e5eaadc	73	struct i2c_client *client = v4l2_get_subdevdata(sd);
1da177e4 LT	74	struct vpx3220 *decoder = i2c_get_clientdata(client);
	75
	76	decoder->reg[reg] = value;
	77	return i2c_smbus_write_byte_data(client, reg, value);
	78	}
	79
7e5eaadc	80	static inline int vpx3220_read(struct v4l2_subdev *sd, u8 reg)
1da177e4	81	{
7e5eaadc HV	82	struct i2c_client *client = v4l2_get_subdevdata(sd);
7e5eaadc HV	83
1da177e4 LT	84	return i2c_smbus_read_byte_data(client, reg);
	85	}
	86
7e5eaadc	87	static int vpx3220_fp_status(struct v4l2_subdev *sd)
1da177e4 LT	88	{
	89	unsigned char status;
	90	unsigned int i;
	91
	92	for (i = 0; i < VPX_TIMEOUT_COUNT; i++) {
7e5eaadc	93	status = vpx3220_read(sd, 0x29);
1da177e4 LT	94
	95	if (!(status & 4))
	96	return 0;
	97
	98	udelay(10);
	99
	100	if (need_resched())
	101	cond_resched();
	102	}
	103
	104	return -1;
	105	}
	106
7e5eaadc	107	static int vpx3220_fp_write(struct v4l2_subdev *sd, u8 fpaddr, u16 data)
1da177e4	108	{
7e5eaadc HV	109	struct i2c_client *client = v4l2_get_subdevdata(sd);
7e5eaadc HV	110
1da177e4 LT	111	/* Write the 16-bit address to the FPWR register */
1da177e4 LT	112	if (i2c_smbus_write_word_data(client, 0x27, swab16(fpaddr)) == -1) {
7e5eaadc	113	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	114	return -1;
	115	}
	116
7e5eaadc	117	if (vpx3220_fp_status(sd) < 0)
1da177e4 LT	118	return -1;
	119
	120	/* Write the 16-bit data to the FPDAT register */
	121	if (i2c_smbus_write_word_data(client, 0x28, swab16(data)) == -1) {
7e5eaadc	122	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	123	return -1;
	124	}
	125
	126	return 0;
	127	}
	128
7e5eaadc	129	static u16 vpx3220_fp_read(struct v4l2_subdev *sd, u16 fpaddr)
1da177e4	130	{
7e5eaadc	131	struct i2c_client *client = v4l2_get_subdevdata(sd);
1da177e4 LT	132	s16 data;
	133
	134	/* Write the 16-bit address to the FPRD register */
	135	if (i2c_smbus_write_word_data(client, 0x26, swab16(fpaddr)) == -1) {
7e5eaadc	136	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	137	return -1;
	138	}
	139
7e5eaadc	140	if (vpx3220_fp_status(sd) < 0)
1da177e4 LT	141	return -1;
	142
	143	/* Read the 16-bit data from the FPDAT register */
	144	data = i2c_smbus_read_word_data(client, 0x28);
	145	if (data == -1) {
7e5eaadc	146	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	147	return -1;
	148	}
	149
	150	return swab16(data);
	151	}
	152
7e5eaadc	153	static int vpx3220_write_block(struct v4l2_subdev sd, const u8 data, unsigned int len)
1da177e4 LT	154	{
	155	u8 reg;
	156	int ret = -1;
	157
	158	while (len >= 2) {
	159	reg = *data++;
7e5eaadc	160	ret = vpx3220_write(sd, reg, *data++);
23848b65	161	if (ret < 0)
1da177e4 LT	162	break;
	163	len -= 2;
	164	}
	165
	166	return ret;
	167	}
	168
7e5eaadc	169	static int vpx3220_write_fp_block(struct v4l2_subdev *sd,
23848b65	170	const u16 *data, unsigned int len)
1da177e4 LT	171	{
	172	u8 reg;
	173	int ret = 0;
	174
	175	while (len > 1) {
	176	reg = *data++;
7e5eaadc	177	ret \|= vpx3220_fp_write(sd, reg, *data++);
1da177e4 LT	178	len -= 2;
	179	}
	180
	181	return ret;
	182	}
	183
	184	/* ---------------------------------------------------------------------- */
	185
	186	static const unsigned short init_ntsc[] = {
	187	0x1c, 0x00, /* NTSC tint angle */
	188	0x88, 17, /* Window 1 vertical */
	189	0x89, 240, /* Vertical lines in */
	190	0x8a, 240, /* Vertical lines out */
	191	0x8b, 000, /* Horizontal begin */
	192	0x8c, 640, /* Horizontal length */
	193	0x8d, 640, /* Number of pixels */
	194	0x8f, 0xc00, /* Disable window 2 */
9b3acc21	195	0xf0, 0x73, /* 13.5 MHz transport, Forced
1da177e4 LT	196	* mode, latch windows */
	197	0xf2, 0x13, /* NTSC M, composite input */
	198	0xe7, 0x1e1, /* Enable vertical standard
	199	* locking @ 240 lines */
	200	};
	201
	202	static const unsigned short init_pal[] = {
	203	0x88, 23, /* Window 1 vertical begin */
9b3acc21	204	0x89, 288, /* Vertical lines in (16 lines
1da177e4	205	* skipped by the VFE) */
9b3acc21	206	0x8a, 288, /* Vertical lines out (16 lines
1da177e4 LT	207	* skipped by the VFE) */
	208	0x8b, 16, /* Horizontal begin */
	209	0x8c, 768, /* Horizontal length */
	210	0x8d, 784, /* Number of pixels
	211	* Must be >= Horizontal begin + Horizontal length */
	212	0x8f, 0xc00, /* Disable window 2 */
9b3acc21	213	0xf0, 0x77, /* 13.5 MHz transport, Forced
1da177e4 LT	214	* mode, latch windows */
1da177e4 LT	215	0xf2, 0x3d1, /* PAL B,G,H,I, composite input */
9b3acc21	216	0xe7, 0x241, /* PAL/SECAM set to 288 lines */
1da177e4 LT	217	};
	218
	219	static const unsigned short init_secam[] = {
9b3acc21 RB	220	0x88, 23, /* Window 1 vertical begin */
9b3acc21 RB	221	0x89, 288, /* Vertical lines in (16 lines
1da177e4	222	* skipped by the VFE) */
9b3acc21	223	0x8a, 288, /* Vertical lines out (16 lines
1da177e4 LT	224	* skipped by the VFE) */
	225	0x8b, 16, /* Horizontal begin */
	226	0x8c, 768, /* Horizontal length */
	227	0x8d, 784, /* Number of pixels
	228	* Must be >= Horizontal begin + Horizontal length */
	229	0x8f, 0xc00, /* Disable window 2 */
9b3acc21	230	0xf0, 0x77, /* 13.5 MHz transport, Forced
1da177e4 LT	231	* mode, latch windows */
1da177e4 LT	232	0xf2, 0x3d5, /* SECAM, composite input */
9b3acc21	233	0xe7, 0x241, /* PAL/SECAM set to 288 lines */
1da177e4 LT	234	};
	235
	236	static const unsigned char init_common[] = {
	237	0xf2, 0x00, /* Disable all outputs */
	238	0x33, 0x0d, /* Luma : VIN2, Chroma : CIN
	239	* (clamp off) */
	240	0xd8, 0xa8, /* HREF/VREF active high, VREF
	241	* pulse = 2, Odd/Even flag */
	242	0x20, 0x03, /* IF compensation 0dB/oct */
	243	0xe0, 0xff, /* Open up all comparators */
	244	0xe1, 0x00,
	245	0xe2, 0x7f,
	246	0xe3, 0x80,
	247	0xe4, 0x7f,
	248	0xe5, 0x80,
	249	0xe6, 0x00, /* Brightness set to 0 */
	250	0xe7, 0xe0, /* Contrast to 1.0, noise shaping
	251	* 10 to 8 2-bit error diffusion */
	252	0xe8, 0xf8, /* YUV422, CbCr binary offset,
	253	* ... (p.32) */
	254	0xea, 0x18, /* LLC2 connected, output FIFO
	255	* reset with VACTintern */
	256	0xf0, 0x8a, /* Half full level to 10, bus
	257	* shuffler [7:0, 23:16, 15:8] */
	258	0xf1, 0x18, /* Single clock, sync mode, no
	259	* FE delay, no HLEN counter */
	260	0xf8, 0x12, /* Port A, PIXCLK, HF# & FE#
	261	* strength to 2 */
	262	0xf9, 0x24, /* Port B, HREF, VREF, PREF &
	263	* ALPHA strength to 4 */
	264	};
	265
	266	static const unsigned short init_fp[] = {
	267	0x59, 0,
	268	0xa0, 2070, /* ACC reference */
	269	0xa3, 0,
	270	0xa4, 0,
	271	0xa8, 30,
	272	0xb2, 768,
	273	0xbe, 27,
	274	0x58, 0,
	275	0x26, 0,
	276	0x4b, 0x298, /* PLL gain */
	277	};
	278
1da177e4	279
7e5eaadc	280	static int vpx3220_init(struct v4l2_subdev *sd, u32 val)
1da177e4	281	{
7e5eaadc HV	282	struct vpx3220 *decoder = to_vpx3220(sd);
	283
	284	vpx3220_write_block(sd, init_common, sizeof(init_common));
	285	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	286	if (decoder->norm & V4L2_STD_NTSC)
	287	vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
	288	else if (decoder->norm & V4L2_STD_PAL)
	289	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	290	else if (decoder->norm & V4L2_STD_SECAM)
	291	vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
	292	else
	293	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	294	return 0;
	295	}
1da177e4	296
7e5eaadc HV	297	static int vpx3220_status(struct v4l2_subdev sd, u32 pstatus, v4l2_std_id *pstd)
	298	{
	299	int res = V4L2_IN_ST_NO_SIGNAL, status;
	300	v4l2_std_id std = 0;
1da177e4	301
7e5eaadc	302	status = vpx3220_fp_read(sd, 0x0f3);
1da177e4	303
7e5eaadc	304	v4l2_dbg(1, debug, sd, "status: 0x%04x\n", status);
1da177e4	305
7e5eaadc HV	306	if (status < 0)
7e5eaadc HV	307	return status;
1da177e4	308
7e5eaadc HV	309	if ((status & 0x20) == 0) {
7e5eaadc HV	310	res = 0;
1da177e4	311
7e5eaadc HV	312	switch (status & 0x18) {
	313	case 0x00:
	314	case 0x10:
	315	case 0x14:
	316	case 0x18:
	317	std = V4L2_STD_PAL;
	318	break;
1da177e4	319
7e5eaadc HV	320	case 0x08:
	321	std = V4L2_STD_SECAM;
	322	break;
1da177e4	323
7e5eaadc HV	324	case 0x04:
	325	case 0x0c:
	326	case 0x1c:
	327	std = V4L2_STD_NTSC;
	328	break;
1da177e4	329	}
23848b65	330	}
7e5eaadc HV	331	if (pstd)
	332	*pstd = std;
	333	if (pstatus)
	334	*pstatus = status;
	335	return 0;
	336	}
1da177e4	337
7e5eaadc HV	338	static int vpx3220_querystd(struct v4l2_subdev sd, v4l2_std_id std)
7e5eaadc HV	339	{
bccfa449	340	v4l2_dbg(1, debug, sd, "querystd\n");
7e5eaadc HV	341	return vpx3220_status(sd, NULL, std);
7e5eaadc HV	342	}
107063c6	343
7e5eaadc HV	344	static int vpx3220_g_input_status(struct v4l2_subdev sd, u32 status)
7e5eaadc HV	345	{
bccfa449	346	v4l2_dbg(1, debug, sd, "g_input_status\n");
7e5eaadc HV	347	return vpx3220_status(sd, status, NULL);
7e5eaadc HV	348	}
de21eb63	349
7e5eaadc HV	350	static int vpx3220_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
	351	{
	352	struct vpx3220 *decoder = to_vpx3220(sd);
	353	int temp_input;
	354
	355	/* Here we back up the input selection because it gets
	356	overwritten when we fill the registers with the
25985edc	357	chosen video norm */
7e5eaadc HV	358	temp_input = vpx3220_fp_read(sd, 0xf2);
7e5eaadc HV	359
bccfa449	360	v4l2_dbg(1, debug, sd, "s_std %llx\n", (unsigned long long)std);
7e5eaadc HV	361	if (std & V4L2_STD_NTSC) {
	362	vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
	363	v4l2_dbg(1, debug, sd, "norm switched to NTSC\n");
	364	} else if (std & V4L2_STD_PAL) {
	365	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	366	v4l2_dbg(1, debug, sd, "norm switched to PAL\n");
	367	} else if (std & V4L2_STD_SECAM) {
	368	vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
	369	v4l2_dbg(1, debug, sd, "norm switched to SECAM\n");
	370	} else {
	371	return -EINVAL;
23848b65	372	}
1da177e4	373
7e5eaadc	374	decoder->norm = std;
1da177e4	375
7e5eaadc HV	376	/* And here we set the backed up video input again */
	377	vpx3220_fp_write(sd, 0xf2, temp_input \| 0x0010);
	378	udelay(10);
	379	return 0;
	380	}
1da177e4	381
5325b427 HV	382	static int vpx3220_s_routing(struct v4l2_subdev *sd,
5325b427 HV	383	u32 input, u32 output, u32 config)
7e5eaadc HV	384	{
7e5eaadc HV	385	int data;
1da177e4	386
5325b427 HV	387	/* RJ: input = 0: ST8 (PCTV) input
	388	input = 1: COMPOSITE input
	389	input = 2: SVHS input */
1da177e4	390
5325b427	391	const int input_vals[3][2] = {
7e5eaadc HV	392	{0x0c, 0},
	393	{0x0d, 0},
	394	{0x0e, 1}
	395	};
1da177e4	396
f14a2972	397	if (input > 2)
7e5eaadc	398	return -EINVAL;
1da177e4	399
5325b427	400	v4l2_dbg(1, debug, sd, "input switched to %s\n", inputs[input]);
1da177e4	401
5325b427	402	vpx3220_write(sd, 0x33, input_vals[input][0]);
1da177e4	403
7e5eaadc HV	404	data = vpx3220_fp_read(sd, 0xf2) & ~(0x0020);
	405	if (data < 0)
	406	return data;
	407	/* 0x0010 is required to latch the setting */
	408	vpx3220_fp_write(sd, 0xf2,
5325b427	409	data \| (input_vals[input][1] << 5) \| 0x0010);
1da177e4	410
7e5eaadc HV	411	udelay(10);
	412	return 0;
	413	}
1da177e4	414
7e5eaadc HV	415	static int vpx3220_s_stream(struct v4l2_subdev *sd, int enable)
7e5eaadc HV	416	{
bccfa449	417	v4l2_dbg(1, debug, sd, "s_stream %s\n", enable ? "on" : "off");
1da177e4	418
7e5eaadc HV	419	vpx3220_write(sd, 0xf2, (enable ? 0x1b : 0x00));
	420	return 0;
	421	}
107063c6	422
9a775323	423	static int vpx3220_s_ctrl(struct v4l2_ctrl *ctrl)
7e5eaadc	424	{
9a775323	425	struct v4l2_subdev *sd = to_sd(ctrl);
1da177e4	426
7e5eaadc HV	427	switch (ctrl->id) {
7e5eaadc HV	428	case V4L2_CID_BRIGHTNESS:
9a775323 HV	429	vpx3220_write(sd, 0xe6, ctrl->val);
9a775323 HV	430	return 0;
7e5eaadc	431	case V4L2_CID_CONTRAST:
9a775323 HV	432	/* Bit 7 and 8 is for noise shaping */
	433	vpx3220_write(sd, 0xe7, ctrl->val + 192);
	434	return 0;
7e5eaadc	435	case V4L2_CID_SATURATION:
9a775323 HV	436	vpx3220_fp_write(sd, 0xa0, ctrl->val);
9a775323 HV	437	return 0;
7e5eaadc	438	case V4L2_CID_HUE:
9a775323 HV	439	vpx3220_fp_write(sd, 0x1c, ctrl->val);
9a775323 HV	440	return 0;
107063c6	441	}
9a775323	442	return -EINVAL;
1da177e4 LT	443	}
1da177e4 LT	444
7e5eaadc	445	static int vpx3220_g_chip_ident(struct v4l2_subdev sd, struct v4l2_dbg_chip_ident chip)
1da177e4	446	{
7e5eaadc HV	447	struct vpx3220 *decoder = to_vpx3220(sd);
7e5eaadc HV	448	struct i2c_client *client = v4l2_get_subdevdata(sd);
1da177e4	449
7e5eaadc	450	return v4l2_chip_ident_i2c_client(client, chip, decoder->ident, 0);
1da177e4 LT	451	}
1da177e4 LT	452
7e5eaadc HV	453	/* ----------------------------------------------------------------------- */
7e5eaadc HV	454
9a775323 HV	455	static const struct v4l2_ctrl_ops vpx3220_ctrl_ops = {
	456	.s_ctrl = vpx3220_s_ctrl,
	457	};
	458
7e5eaadc HV	459	static const struct v4l2_subdev_core_ops vpx3220_core_ops = {
	460	.g_chip_ident = vpx3220_g_chip_ident,
	461	.init = vpx3220_init,
9a775323 HV	462	.g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
	463	.try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
	464	.s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
	465	.g_ctrl = v4l2_subdev_g_ctrl,
	466	.s_ctrl = v4l2_subdev_s_ctrl,
	467	.queryctrl = v4l2_subdev_queryctrl,
	468	.querymenu = v4l2_subdev_querymenu,
7e5eaadc HV	469	.s_std = vpx3220_s_std,
	470	};
	471
	472	static const struct v4l2_subdev_video_ops vpx3220_video_ops = {
	473	.s_routing = vpx3220_s_routing,
	474	.s_stream = vpx3220_s_stream,
	475	.querystd = vpx3220_querystd,
	476	.g_input_status = vpx3220_g_input_status,
	477	};
	478
	479	static const struct v4l2_subdev_ops vpx3220_ops = {
	480	.core = &vpx3220_core_ops,
7e5eaadc HV	481	.video = &vpx3220_video_ops,
	482	};
	483
1da177e4	484	/* -----------------------------------------------------------------------
c84e6036	485	* Client management code
1da177e4 LT	486	*/
1da177e4 LT	487
23848b65 HV	488	static int vpx3220_probe(struct i2c_client *client,
23848b65 HV	489	const struct i2c_device_id *id)
1da177e4	490	{
1da177e4	491	struct vpx3220 *decoder;
7e5eaadc	492	struct v4l2_subdev *sd;
23848b65 HV	493	const char *name = NULL;
	494	u8 ver;
	495	u16 pn;
1da177e4 LT	496
1da177e4 LT	497	/* Check if the adapter supports the needed features */
23848b65 HV	498	if (!i2c_check_functionality(client->adapter,
	499	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA))
	500	return -ENODEV;
1da177e4	501
7408187d	502	decoder = kzalloc(sizeof(struct vpx3220), GFP_KERNEL);
23848b65	503	if (decoder == NULL)
1da177e4	504	return -ENOMEM;
7e5eaadc HV	505	sd = &decoder->sd;
7e5eaadc HV	506	v4l2_i2c_subdev_init(sd, client, &vpx3220_ops);
107063c6	507	decoder->norm = V4L2_STD_PAL;
1da177e4 LT	508	decoder->input = 0;
1da177e4 LT	509	decoder->enable = 1;
9a775323 HV	510	v4l2_ctrl_handler_init(&decoder->hdl, 4);
	511	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	512	V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
	513	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	514	V4L2_CID_CONTRAST, 0, 63, 1, 32);
	515	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	516	V4L2_CID_SATURATION, 0, 4095, 1, 2048);
	517	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	518	V4L2_CID_HUE, -512, 511, 1, 0);
	519	sd->ctrl_handler = &decoder->hdl;
	520	if (decoder->hdl.error) {
	521	int err = decoder->hdl.error;
	522
	523	v4l2_ctrl_handler_free(&decoder->hdl);
	524	kfree(decoder);
	525	return err;
	526	}
	527	v4l2_ctrl_handler_setup(&decoder->hdl);
1da177e4	528
23848b65 HV	529	ver = i2c_smbus_read_byte_data(client, 0x00);
	530	pn = (i2c_smbus_read_byte_data(client, 0x02) << 8) +
	531	i2c_smbus_read_byte_data(client, 0x01);
7e5eaadc	532	decoder->ident = V4L2_IDENT_VPX3220A;
23848b65 HV	533	if (ver == 0xec) {
	534	switch (pn) {
	535	case 0x4680:
	536	name = "vpx3220a";
	537	break;
	538	case 0x4260:
	539	name = "vpx3216b";
7e5eaadc	540	decoder->ident = V4L2_IDENT_VPX3216B;
23848b65 HV	541	break;
	542	case 0x4280:
	543	name = "vpx3214c";
7e5eaadc	544	decoder->ident = V4L2_IDENT_VPX3214C;
23848b65 HV	545	break;
23848b65 HV	546	}
1da177e4	547	}
23848b65	548	if (name)
7e5eaadc	549	v4l2_info(sd, "%s found @ 0x%x (%s)\n", name,
23848b65 HV	550	client->addr << 1, client->adapter->name);
23848b65 HV	551	else
7e5eaadc	552	v4l2_info(sd, "chip (%02x:%04x) found @ 0x%x (%s)\n",
23848b65	553	ver, pn, client->addr << 1, client->adapter->name);
1da177e4	554
7e5eaadc HV	555	vpx3220_write_block(sd, init_common, sizeof(init_common));
	556	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	557	/* Default to PAL */
	558	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
1da177e4 LT	559	return 0;
	560	}
	561
23848b65	562	static int vpx3220_remove(struct i2c_client *client)
1da177e4	563	{
7e5eaadc	564	struct v4l2_subdev *sd = i2c_get_clientdata(client);
9a775323	565	struct vpx3220 *decoder = to_vpx3220(sd);
7e5eaadc HV	566
7e5eaadc HV	567	v4l2_device_unregister_subdev(sd);
9a775323 HV	568	v4l2_ctrl_handler_free(&decoder->hdl);
9a775323 HV	569	kfree(decoder);
23848b65	570	return 0;
1da177e4 LT	571	}
1da177e4 LT	572
23848b65 HV	573	static const struct i2c_device_id vpx3220_id[] = {
	574	{ "vpx3220a", 0 },
	575	{ "vpx3216b", 0 },
	576	{ "vpx3214c", 0 },
	577	{ }
	578	};
	579	MODULE_DEVICE_TABLE(i2c, vpx3220_id);
1da177e4	580
c2d999f3 HV	581	static struct i2c_driver vpx3220_driver = {
	582	.driver = {
	583	.owner = THIS_MODULE,
	584	.name = "vpx3220",
	585	},
	586	.probe = vpx3220_probe,
	587	.remove = vpx3220_remove,
	588	.id_table = vpx3220_id,
1da177e4	589	};
c2d999f3 HV	590
	591	static __init int init_vpx3220(void)
	592	{
	593	return i2c_add_driver(&vpx3220_driver);
	594	}
	595
	596	static __exit void exit_vpx3220(void)
	597	{
	598	i2c_del_driver(&vpx3220_driver);
	599	}
	600
	601	module_init(init_vpx3220);
	602	module_exit(exit_vpx3220);