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e3ec3a3d SB |
1 | /* |
2 | * Arasan Secure Digital Host Controller Interface. | |
3 | * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> | |
4 | * Copyright (c) 2012 Wind River Systems, Inc. | |
5 | * Copyright (C) 2013 Pengutronix e.K. | |
6 | * Copyright (C) 2013 Xilinx Inc. | |
7 | * | |
8 | * Based on sdhci-of-esdhc.c | |
9 | * | |
10 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | |
11 | * Copyright (c) 2009 MontaVista Software, Inc. | |
12 | * | |
13 | * Authors: Xiaobo Xie <X.Xie@freescale.com> | |
14 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or (at | |
19 | * your option) any later version. | |
20 | */ | |
21 | ||
c390f211 | 22 | #include <linux/clk-provider.h> |
3ea4666e | 23 | #include <linux/mfd/syscon.h> |
e3ec3a3d | 24 | #include <linux/module.h> |
308f3f8d | 25 | #include <linux/of_device.h> |
91aa3661 | 26 | #include <linux/phy/phy.h> |
3ea4666e | 27 | #include <linux/regmap.h> |
e3ec3a3d SB |
28 | #include "sdhci-pltfm.h" |
29 | ||
30 | #define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c | |
a05c8465 | 31 | #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 |
e3ec3a3d | 32 | |
a05c8465 | 33 | #define VENDOR_ENHANCED_STROBE BIT(0) |
e3ec3a3d SB |
34 | #define CLK_CTRL_TIMEOUT_SHIFT 16 |
35 | #define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT) | |
36 | #define CLK_CTRL_TIMEOUT_MIN_EXP 13 | |
37 | ||
7b6be966 DA |
38 | #define PHY_CLK_TOO_SLOW_HZ 400000 |
39 | ||
3ea4666e DA |
40 | /* |
41 | * On some SoCs the syscon area has a feature where the upper 16-bits of | |
42 | * each 32-bit register act as a write mask for the lower 16-bits. This allows | |
43 | * atomic updates of the register without locking. This macro is used on SoCs | |
44 | * that have that feature. | |
45 | */ | |
46 | #define HIWORD_UPDATE(val, mask, shift) \ | |
47 | ((val) << (shift) | (mask) << ((shift) + 16)) | |
48 | ||
49 | /** | |
50 | * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map | |
51 | * | |
52 | * @reg: Offset within the syscon of the register containing this field | |
53 | * @width: Number of bits for this field | |
54 | * @shift: Bit offset within @reg of this field (or -1 if not avail) | |
55 | */ | |
56 | struct sdhci_arasan_soc_ctl_field { | |
57 | u32 reg; | |
58 | u16 width; | |
59 | s16 shift; | |
60 | }; | |
61 | ||
62 | /** | |
63 | * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers | |
64 | * | |
65 | * It's up to the licensee of the Arsan IP block to make these available | |
66 | * somewhere if needed. Presumably these will be scattered somewhere that's | |
67 | * accessible via the syscon API. | |
68 | * | |
69 | * @baseclkfreq: Where to find corecfg_baseclkfreq | |
f78f9374 | 70 | * @clockmultiplier: Where to find corecfg_clockmultiplier |
3ea4666e DA |
71 | * @hiword_update: If true, use HIWORD_UPDATE to access the syscon |
72 | */ | |
73 | struct sdhci_arasan_soc_ctl_map { | |
74 | struct sdhci_arasan_soc_ctl_field baseclkfreq; | |
f78f9374 | 75 | struct sdhci_arasan_soc_ctl_field clockmultiplier; |
3ea4666e DA |
76 | bool hiword_update; |
77 | }; | |
78 | ||
e3ec3a3d SB |
79 | /** |
80 | * struct sdhci_arasan_data | |
c390f211 | 81 | * @host: Pointer to the main SDHCI host structure. |
3ea4666e DA |
82 | * @clk_ahb: Pointer to the AHB clock |
83 | * @phy: Pointer to the generic phy | |
7b6be966 | 84 | * @is_phy_on: True if the PHY is on; false if not. |
c390f211 DA |
85 | * @sdcardclk_hw: Struct for the clock we might provide to a PHY. |
86 | * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. | |
3ea4666e DA |
87 | * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. |
88 | * @soc_ctl_map: Map to get offsets into soc_ctl registers. | |
e3ec3a3d SB |
89 | */ |
90 | struct sdhci_arasan_data { | |
c390f211 | 91 | struct sdhci_host *host; |
e3ec3a3d | 92 | struct clk *clk_ahb; |
91aa3661 | 93 | struct phy *phy; |
7b6be966 | 94 | bool is_phy_on; |
3ea4666e | 95 | |
c390f211 DA |
96 | struct clk_hw sdcardclk_hw; |
97 | struct clk *sdcardclk; | |
98 | ||
3ea4666e DA |
99 | struct regmap *soc_ctl_base; |
100 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; | |
101 | }; | |
102 | ||
103 | static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = { | |
104 | .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, | |
f78f9374 | 105 | .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, |
3ea4666e | 106 | .hiword_update = true, |
e3ec3a3d SB |
107 | }; |
108 | ||
3ea4666e DA |
109 | /** |
110 | * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers | |
111 | * | |
112 | * This function allows writing to fields in sdhci_arasan_soc_ctl_map. | |
113 | * Note that if a field is specified as not available (shift < 0) then | |
114 | * this function will silently return an error code. It will be noisy | |
115 | * and print errors for any other (unexpected) errors. | |
116 | * | |
117 | * @host: The sdhci_host | |
118 | * @fld: The field to write to | |
119 | * @val: The value to write | |
120 | */ | |
121 | static int sdhci_arasan_syscon_write(struct sdhci_host *host, | |
122 | const struct sdhci_arasan_soc_ctl_field *fld, | |
123 | u32 val) | |
124 | { | |
125 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
126 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
127 | struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; | |
128 | u32 reg = fld->reg; | |
129 | u16 width = fld->width; | |
130 | s16 shift = fld->shift; | |
131 | int ret; | |
132 | ||
133 | /* | |
134 | * Silently return errors for shift < 0 so caller doesn't have | |
135 | * to check for fields which are optional. For fields that | |
136 | * are required then caller needs to do something special | |
137 | * anyway. | |
138 | */ | |
139 | if (shift < 0) | |
140 | return -EINVAL; | |
141 | ||
142 | if (sdhci_arasan->soc_ctl_map->hiword_update) | |
143 | ret = regmap_write(soc_ctl_base, reg, | |
144 | HIWORD_UPDATE(val, GENMASK(width, 0), | |
145 | shift)); | |
146 | else | |
147 | ret = regmap_update_bits(soc_ctl_base, reg, | |
148 | GENMASK(shift + width, shift), | |
149 | val << shift); | |
150 | ||
151 | /* Yell about (unexpected) regmap errors */ | |
152 | if (ret) | |
153 | pr_warn("%s: Regmap write fail: %d\n", | |
154 | mmc_hostname(host->mmc), ret); | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
e3ec3a3d SB |
159 | static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host) |
160 | { | |
161 | u32 div; | |
162 | unsigned long freq; | |
163 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
164 | ||
165 | div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET); | |
166 | div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT; | |
167 | ||
168 | freq = clk_get_rate(pltfm_host->clk); | |
169 | freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div); | |
170 | ||
171 | return freq; | |
172 | } | |
173 | ||
802ac39a SL |
174 | static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) |
175 | { | |
176 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
177 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
6fc09244 | 178 | bool ctrl_phy = false; |
802ac39a | 179 | |
7b6be966 DA |
180 | if (!IS_ERR(sdhci_arasan->phy)) { |
181 | if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { | |
182 | /* | |
183 | * If PHY off, set clock to max speed and power PHY on. | |
184 | * | |
185 | * Although PHY docs apparently suggest power cycling | |
186 | * when changing the clock the PHY doesn't like to be | |
187 | * powered on while at low speeds like those used in ID | |
188 | * mode. Even worse is powering the PHY on while the | |
189 | * clock is off. | |
190 | * | |
191 | * To workaround the PHY limitations, the best we can | |
192 | * do is to power it on at a faster speed and then slam | |
193 | * through low speeds without power cycling. | |
194 | */ | |
195 | sdhci_set_clock(host, host->max_clk); | |
196 | spin_unlock_irq(&host->lock); | |
197 | phy_power_on(sdhci_arasan->phy); | |
198 | spin_lock_irq(&host->lock); | |
199 | sdhci_arasan->is_phy_on = true; | |
200 | ||
201 | /* | |
202 | * We'll now fall through to the below case with | |
203 | * ctrl_phy = false (so we won't turn off/on). The | |
204 | * sdhci_set_clock() will set the real clock. | |
205 | */ | |
206 | } else if (clock > PHY_CLK_TOO_SLOW_HZ) { | |
207 | /* | |
208 | * At higher clock speeds the PHY is fine being power | |
209 | * cycled and docs say you _should_ power cycle when | |
210 | * changing clock speeds. | |
211 | */ | |
212 | ctrl_phy = true; | |
213 | } | |
214 | } | |
802ac39a | 215 | |
7b6be966 | 216 | if (ctrl_phy && sdhci_arasan->is_phy_on) { |
802ac39a SL |
217 | spin_unlock_irq(&host->lock); |
218 | phy_power_off(sdhci_arasan->phy); | |
219 | spin_lock_irq(&host->lock); | |
7b6be966 | 220 | sdhci_arasan->is_phy_on = false; |
802ac39a SL |
221 | } |
222 | ||
223 | sdhci_set_clock(host, clock); | |
224 | ||
6fc09244 | 225 | if (ctrl_phy) { |
802ac39a SL |
226 | spin_unlock_irq(&host->lock); |
227 | phy_power_on(sdhci_arasan->phy); | |
228 | spin_lock_irq(&host->lock); | |
7b6be966 | 229 | sdhci_arasan->is_phy_on = true; |
802ac39a SL |
230 | } |
231 | } | |
232 | ||
a05c8465 SL |
233 | static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc, |
234 | struct mmc_ios *ios) | |
235 | { | |
236 | u32 vendor; | |
237 | struct sdhci_host *host = mmc_priv(mmc); | |
238 | ||
239 | vendor = readl(host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER); | |
240 | if (ios->enhanced_strobe) | |
241 | vendor |= VENDOR_ENHANCED_STROBE; | |
242 | else | |
243 | vendor &= ~VENDOR_ENHANCED_STROBE; | |
244 | ||
245 | writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER); | |
246 | } | |
247 | ||
e3ec3a3d | 248 | static struct sdhci_ops sdhci_arasan_ops = { |
802ac39a | 249 | .set_clock = sdhci_arasan_set_clock, |
e3ec3a3d SB |
250 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
251 | .get_timeout_clock = sdhci_arasan_get_timeout_clock, | |
2317f56c | 252 | .set_bus_width = sdhci_set_bus_width, |
03231f9b | 253 | .reset = sdhci_reset, |
96d7b78c | 254 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
e3ec3a3d SB |
255 | }; |
256 | ||
257 | static struct sdhci_pltfm_data sdhci_arasan_pdata = { | |
258 | .ops = &sdhci_arasan_ops, | |
2d532d45 SG |
259 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
260 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
261 | SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, | |
e3ec3a3d SB |
262 | }; |
263 | ||
264 | #ifdef CONFIG_PM_SLEEP | |
265 | /** | |
266 | * sdhci_arasan_suspend - Suspend method for the driver | |
267 | * @dev: Address of the device structure | |
268 | * Returns 0 on success and error value on error | |
269 | * | |
270 | * Put the device in a low power state. | |
271 | */ | |
272 | static int sdhci_arasan_suspend(struct device *dev) | |
273 | { | |
274 | struct platform_device *pdev = to_platform_device(dev); | |
275 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
276 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
89211418 | 277 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
278 | int ret; |
279 | ||
280 | ret = sdhci_suspend_host(host); | |
281 | if (ret) | |
282 | return ret; | |
283 | ||
7b6be966 | 284 | if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { |
91aa3661 SL |
285 | ret = phy_power_off(sdhci_arasan->phy); |
286 | if (ret) { | |
287 | dev_err(dev, "Cannot power off phy.\n"); | |
288 | sdhci_resume_host(host); | |
289 | return ret; | |
290 | } | |
7b6be966 | 291 | sdhci_arasan->is_phy_on = false; |
91aa3661 SL |
292 | } |
293 | ||
e3ec3a3d SB |
294 | clk_disable(pltfm_host->clk); |
295 | clk_disable(sdhci_arasan->clk_ahb); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | /** | |
301 | * sdhci_arasan_resume - Resume method for the driver | |
302 | * @dev: Address of the device structure | |
303 | * Returns 0 on success and error value on error | |
304 | * | |
305 | * Resume operation after suspend | |
306 | */ | |
307 | static int sdhci_arasan_resume(struct device *dev) | |
308 | { | |
309 | struct platform_device *pdev = to_platform_device(dev); | |
310 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
311 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
89211418 | 312 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
e3ec3a3d SB |
313 | int ret; |
314 | ||
315 | ret = clk_enable(sdhci_arasan->clk_ahb); | |
316 | if (ret) { | |
317 | dev_err(dev, "Cannot enable AHB clock.\n"); | |
318 | return ret; | |
319 | } | |
320 | ||
321 | ret = clk_enable(pltfm_host->clk); | |
322 | if (ret) { | |
323 | dev_err(dev, "Cannot enable SD clock.\n"); | |
e3ec3a3d SB |
324 | return ret; |
325 | } | |
326 | ||
7b6be966 | 327 | if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { |
91aa3661 SL |
328 | ret = phy_power_on(sdhci_arasan->phy); |
329 | if (ret) { | |
330 | dev_err(dev, "Cannot power on phy.\n"); | |
331 | return ret; | |
332 | } | |
7b6be966 | 333 | sdhci_arasan->is_phy_on = true; |
91aa3661 SL |
334 | } |
335 | ||
e3ec3a3d SB |
336 | return sdhci_resume_host(host); |
337 | } | |
338 | #endif /* ! CONFIG_PM_SLEEP */ | |
339 | ||
340 | static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend, | |
341 | sdhci_arasan_resume); | |
342 | ||
3ea4666e DA |
343 | static const struct of_device_id sdhci_arasan_of_match[] = { |
344 | /* SoC-specific compatible strings w/ soc_ctl_map */ | |
345 | { | |
346 | .compatible = "rockchip,rk3399-sdhci-5.1", | |
347 | .data = &rk3399_soc_ctl_map, | |
348 | }, | |
349 | ||
350 | /* Generic compatible below here */ | |
351 | { .compatible = "arasan,sdhci-8.9a" }, | |
352 | { .compatible = "arasan,sdhci-5.1" }, | |
353 | { .compatible = "arasan,sdhci-4.9a" }, | |
354 | ||
355 | { /* sentinel */ } | |
356 | }; | |
357 | MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); | |
358 | ||
c390f211 DA |
359 | /** |
360 | * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate | |
361 | * | |
362 | * Return the current actual rate of the SD card clock. This can be used | |
363 | * to communicate with out PHY. | |
364 | * | |
365 | * @hw: Pointer to the hardware clock structure. | |
366 | * @parent_rate The parent rate (should be rate of clk_xin). | |
367 | * Returns the card clock rate. | |
368 | */ | |
369 | static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, | |
370 | unsigned long parent_rate) | |
371 | ||
372 | { | |
373 | struct sdhci_arasan_data *sdhci_arasan = | |
374 | container_of(hw, struct sdhci_arasan_data, sdcardclk_hw); | |
375 | struct sdhci_host *host = sdhci_arasan->host; | |
376 | ||
377 | return host->mmc->actual_clock; | |
378 | } | |
379 | ||
380 | static const struct clk_ops arasan_sdcardclk_ops = { | |
381 | .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, | |
382 | }; | |
383 | ||
f78f9374 SL |
384 | /** |
385 | * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier | |
386 | * | |
387 | * The corecfg_clockmultiplier is supposed to contain clock multiplier | |
388 | * value of programmable clock generator. | |
389 | * | |
390 | * NOTES: | |
391 | * - Many existing devices don't seem to do this and work fine. To keep | |
392 | * compatibility for old hardware where the device tree doesn't provide a | |
393 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
394 | * for this platform. | |
395 | * - The value of corecfg_clockmultiplier should sync with that of corresponding | |
396 | * value reading from sdhci_capability_register. So this function is called | |
397 | * once at probe time and never called again. | |
398 | * | |
399 | * @host: The sdhci_host | |
400 | */ | |
401 | static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host, | |
402 | u32 value) | |
403 | { | |
404 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
405 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
406 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
407 | sdhci_arasan->soc_ctl_map; | |
408 | ||
409 | /* Having a map is optional */ | |
410 | if (!soc_ctl_map) | |
411 | return; | |
412 | ||
413 | /* If we have a map, we expect to have a syscon */ | |
414 | if (!sdhci_arasan->soc_ctl_base) { | |
415 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
416 | mmc_hostname(host->mmc)); | |
417 | return; | |
418 | } | |
419 | ||
420 | sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); | |
421 | } | |
422 | ||
3ea4666e DA |
423 | /** |
424 | * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq | |
425 | * | |
426 | * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This | |
427 | * function can be used to make that happen. | |
428 | * | |
429 | * NOTES: | |
430 | * - Many existing devices don't seem to do this and work fine. To keep | |
431 | * compatibility for old hardware where the device tree doesn't provide a | |
432 | * register map, this function is a noop if a soc_ctl_map hasn't been provided | |
433 | * for this platform. | |
434 | * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider | |
435 | * to achieve lower clock rates. That means that this function is called once | |
436 | * at probe time and never called again. | |
437 | * | |
438 | * @host: The sdhci_host | |
439 | */ | |
440 | static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) | |
441 | { | |
442 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
443 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
444 | const struct sdhci_arasan_soc_ctl_map *soc_ctl_map = | |
445 | sdhci_arasan->soc_ctl_map; | |
446 | u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); | |
447 | ||
448 | /* Having a map is optional */ | |
449 | if (!soc_ctl_map) | |
450 | return; | |
451 | ||
452 | /* If we have a map, we expect to have a syscon */ | |
453 | if (!sdhci_arasan->soc_ctl_base) { | |
454 | pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", | |
455 | mmc_hostname(host->mmc)); | |
456 | return; | |
457 | } | |
458 | ||
459 | sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); | |
460 | } | |
461 | ||
c390f211 DA |
462 | /** |
463 | * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use | |
464 | * | |
465 | * Some PHY devices need to know what the actual card clock is. In order for | |
466 | * them to find out, we'll provide a clock through the common clock framework | |
467 | * for them to query. | |
468 | * | |
469 | * Note: without seriously re-architecting SDHCI's clock code and testing on | |
470 | * all platforms, there's no way to create a totally beautiful clock here | |
471 | * with all clock ops implemented. Instead, we'll just create a clock that can | |
472 | * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock | |
473 | * framework that we're doing things behind its back. This should be sufficient | |
474 | * to create nice clean device tree bindings and later (if needed) we can try | |
475 | * re-architecting SDHCI if we see some benefit to it. | |
476 | * | |
477 | * @sdhci_arasan: Our private data structure. | |
478 | * @clk_xin: Pointer to the functional clock | |
479 | * @dev: Pointer to our struct device. | |
480 | * Returns 0 on success and error value on error | |
481 | */ | |
482 | static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, | |
483 | struct clk *clk_xin, | |
484 | struct device *dev) | |
485 | { | |
486 | struct device_node *np = dev->of_node; | |
487 | struct clk_init_data sdcardclk_init; | |
488 | const char *parent_clk_name; | |
489 | int ret; | |
490 | ||
491 | /* Providing a clock to the PHY is optional; no error if missing */ | |
492 | if (!of_find_property(np, "#clock-cells", NULL)) | |
493 | return 0; | |
494 | ||
495 | ret = of_property_read_string_index(np, "clock-output-names", 0, | |
496 | &sdcardclk_init.name); | |
497 | if (ret) { | |
498 | dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); | |
499 | return ret; | |
500 | } | |
501 | ||
502 | parent_clk_name = __clk_get_name(clk_xin); | |
503 | sdcardclk_init.parent_names = &parent_clk_name; | |
504 | sdcardclk_init.num_parents = 1; | |
505 | sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; | |
506 | sdcardclk_init.ops = &arasan_sdcardclk_ops; | |
507 | ||
508 | sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init; | |
509 | sdhci_arasan->sdcardclk = | |
510 | devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw); | |
511 | sdhci_arasan->sdcardclk_hw.init = NULL; | |
512 | ||
513 | ret = of_clk_add_provider(np, of_clk_src_simple_get, | |
514 | sdhci_arasan->sdcardclk); | |
515 | if (ret) | |
516 | dev_err(dev, "Failed to add clock provider\n"); | |
517 | ||
518 | return ret; | |
519 | } | |
520 | ||
521 | /** | |
522 | * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() | |
523 | * | |
524 | * Should be called any time we're exiting and sdhci_arasan_register_sdclk() | |
525 | * returned success. | |
526 | * | |
527 | * @dev: Pointer to our struct device. | |
528 | */ | |
529 | static void sdhci_arasan_unregister_sdclk(struct device *dev) | |
530 | { | |
531 | struct device_node *np = dev->of_node; | |
532 | ||
533 | if (!of_find_property(np, "#clock-cells", NULL)) | |
534 | return; | |
535 | ||
536 | of_clk_del_provider(dev->of_node); | |
537 | } | |
538 | ||
e3ec3a3d SB |
539 | static int sdhci_arasan_probe(struct platform_device *pdev) |
540 | { | |
541 | int ret; | |
3ea4666e DA |
542 | const struct of_device_id *match; |
543 | struct device_node *node; | |
e3ec3a3d SB |
544 | struct clk *clk_xin; |
545 | struct sdhci_host *host; | |
546 | struct sdhci_pltfm_host *pltfm_host; | |
547 | struct sdhci_arasan_data *sdhci_arasan; | |
548 | ||
89211418 JZ |
549 | host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata, |
550 | sizeof(*sdhci_arasan)); | |
551 | if (IS_ERR(host)) | |
552 | return PTR_ERR(host); | |
553 | ||
554 | pltfm_host = sdhci_priv(host); | |
555 | sdhci_arasan = sdhci_pltfm_priv(pltfm_host); | |
c390f211 | 556 | sdhci_arasan->host = host; |
e3ec3a3d | 557 | |
3ea4666e DA |
558 | match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); |
559 | sdhci_arasan->soc_ctl_map = match->data; | |
560 | ||
561 | node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); | |
562 | if (node) { | |
563 | sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); | |
564 | of_node_put(node); | |
565 | ||
566 | if (IS_ERR(sdhci_arasan->soc_ctl_base)) { | |
567 | ret = PTR_ERR(sdhci_arasan->soc_ctl_base); | |
568 | if (ret != -EPROBE_DEFER) | |
569 | dev_err(&pdev->dev, "Can't get syscon: %d\n", | |
570 | ret); | |
571 | goto err_pltfm_free; | |
572 | } | |
573 | } | |
574 | ||
e3ec3a3d SB |
575 | sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); |
576 | if (IS_ERR(sdhci_arasan->clk_ahb)) { | |
577 | dev_err(&pdev->dev, "clk_ahb clock not found.\n"); | |
278d0962 SL |
578 | ret = PTR_ERR(sdhci_arasan->clk_ahb); |
579 | goto err_pltfm_free; | |
e3ec3a3d SB |
580 | } |
581 | ||
582 | clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); | |
583 | if (IS_ERR(clk_xin)) { | |
584 | dev_err(&pdev->dev, "clk_xin clock not found.\n"); | |
278d0962 SL |
585 | ret = PTR_ERR(clk_xin); |
586 | goto err_pltfm_free; | |
e3ec3a3d SB |
587 | } |
588 | ||
589 | ret = clk_prepare_enable(sdhci_arasan->clk_ahb); | |
590 | if (ret) { | |
591 | dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); | |
278d0962 | 592 | goto err_pltfm_free; |
e3ec3a3d SB |
593 | } |
594 | ||
595 | ret = clk_prepare_enable(clk_xin); | |
596 | if (ret) { | |
597 | dev_err(&pdev->dev, "Unable to enable SD clock.\n"); | |
598 | goto clk_dis_ahb; | |
599 | } | |
600 | ||
e3ec3a3d | 601 | sdhci_get_of_property(pdev); |
e3ec3a3d SB |
602 | pltfm_host->clk = clk_xin; |
603 | ||
f78f9374 SL |
604 | if (of_device_is_compatible(pdev->dev.of_node, |
605 | "rockchip,rk3399-sdhci-5.1")) | |
606 | sdhci_arasan_update_clockmultiplier(host, 0x0); | |
607 | ||
3ea4666e DA |
608 | sdhci_arasan_update_baseclkfreq(host); |
609 | ||
c390f211 DA |
610 | ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); |
611 | if (ret) | |
612 | goto clk_disable_all; | |
613 | ||
16b23787 MS |
614 | ret = mmc_of_parse(host->mmc); |
615 | if (ret) { | |
616 | dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret); | |
c390f211 | 617 | goto unreg_clk; |
16b23787 MS |
618 | } |
619 | ||
91aa3661 SL |
620 | sdhci_arasan->phy = ERR_PTR(-ENODEV); |
621 | if (of_device_is_compatible(pdev->dev.of_node, | |
622 | "arasan,sdhci-5.1")) { | |
623 | sdhci_arasan->phy = devm_phy_get(&pdev->dev, | |
624 | "phy_arasan"); | |
625 | if (IS_ERR(sdhci_arasan->phy)) { | |
626 | ret = PTR_ERR(sdhci_arasan->phy); | |
627 | dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); | |
c390f211 | 628 | goto unreg_clk; |
91aa3661 SL |
629 | } |
630 | ||
631 | ret = phy_init(sdhci_arasan->phy); | |
632 | if (ret < 0) { | |
633 | dev_err(&pdev->dev, "phy_init err.\n"); | |
c390f211 | 634 | goto unreg_clk; |
91aa3661 SL |
635 | } |
636 | ||
a05c8465 SL |
637 | host->mmc_host_ops.hs400_enhanced_strobe = |
638 | sdhci_arasan_hs400_enhanced_strobe; | |
91aa3661 SL |
639 | } |
640 | ||
e3ec3a3d | 641 | ret = sdhci_add_host(host); |
b1df9de7 | 642 | if (ret) |
91aa3661 | 643 | goto err_add_host; |
e3ec3a3d SB |
644 | |
645 | return 0; | |
646 | ||
91aa3661 | 647 | err_add_host: |
91aa3661 SL |
648 | if (!IS_ERR(sdhci_arasan->phy)) |
649 | phy_exit(sdhci_arasan->phy); | |
c390f211 DA |
650 | unreg_clk: |
651 | sdhci_arasan_unregister_sdclk(&pdev->dev); | |
e3ec3a3d SB |
652 | clk_disable_all: |
653 | clk_disable_unprepare(clk_xin); | |
654 | clk_dis_ahb: | |
655 | clk_disable_unprepare(sdhci_arasan->clk_ahb); | |
278d0962 SL |
656 | err_pltfm_free: |
657 | sdhci_pltfm_free(pdev); | |
e3ec3a3d SB |
658 | return ret; |
659 | } | |
660 | ||
661 | static int sdhci_arasan_remove(struct platform_device *pdev) | |
662 | { | |
0c7fe32e | 663 | int ret; |
e3ec3a3d SB |
664 | struct sdhci_host *host = platform_get_drvdata(pdev); |
665 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
89211418 JZ |
666 | struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); |
667 | struct clk *clk_ahb = sdhci_arasan->clk_ahb; | |
e3ec3a3d | 668 | |
91aa3661 | 669 | if (!IS_ERR(sdhci_arasan->phy)) { |
7b6be966 DA |
670 | if (sdhci_arasan->is_phy_on) |
671 | phy_power_off(sdhci_arasan->phy); | |
91aa3661 SL |
672 | phy_exit(sdhci_arasan->phy); |
673 | } | |
674 | ||
c390f211 DA |
675 | sdhci_arasan_unregister_sdclk(&pdev->dev); |
676 | ||
0c7fe32e JZ |
677 | ret = sdhci_pltfm_unregister(pdev); |
678 | ||
89211418 | 679 | clk_disable_unprepare(clk_ahb); |
e3ec3a3d | 680 | |
0c7fe32e | 681 | return ret; |
e3ec3a3d SB |
682 | } |
683 | ||
e3ec3a3d SB |
684 | static struct platform_driver sdhci_arasan_driver = { |
685 | .driver = { | |
686 | .name = "sdhci-arasan", | |
e3ec3a3d SB |
687 | .of_match_table = sdhci_arasan_of_match, |
688 | .pm = &sdhci_arasan_dev_pm_ops, | |
689 | }, | |
690 | .probe = sdhci_arasan_probe, | |
691 | .remove = sdhci_arasan_remove, | |
692 | }; | |
693 | ||
694 | module_platform_driver(sdhci_arasan_driver); | |
695 | ||
696 | MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller"); | |
697 | MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>"); | |
698 | MODULE_LICENSE("GPL"); |