[deliverable/linux.git] / drivers / mmc / host / sdhci-tegra.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/delay.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/gpio/consumer.h>

#include "sdhci-pltfm.h"

/* Tegra SDHOST controller vendor register definitions */
#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL			0x100
#define SDHCI_CLOCK_CTRL_TAP_MASK			0x00ff0000
#define SDHCI_CLOCK_CTRL_TAP_SHIFT			16
#define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE		BIT(5)
#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE		BIT(3)
#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE	BIT(2)

#define SDHCI_TEGRA_VENDOR_MISC_CTRL		0x120
#define SDHCI_MISC_CTRL_ENABLE_SDR104		0x8
#define SDHCI_MISC_CTRL_ENABLE_SDR50		0x10
#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300	0x20
#define SDHCI_MISC_CTRL_ENABLE_DDR50		0x200

#define SDHCI_TEGRA_AUTO_CAL_CONFIG		0x1e4
#define SDHCI_AUTO_CAL_START			BIT(31)
#define SDHCI_AUTO_CAL_ENABLE			BIT(29)

#define NVQUIRK_FORCE_SDHCI_SPEC_200	BIT(0)
#define NVQUIRK_ENABLE_BLOCK_GAP_DET	BIT(1)
#define NVQUIRK_ENABLE_SDHCI_SPEC_300	BIT(2)
#define NVQUIRK_ENABLE_SDR50		BIT(3)
#define NVQUIRK_ENABLE_SDR104		BIT(4)
#define NVQUIRK_ENABLE_DDR50		BIT(5)
#define NVQUIRK_HAS_PADCALIB		BIT(6)

struct sdhci_tegra_soc_data {
	const struct sdhci_pltfm_data *pdata;
	u32 nvquirks;
};

struct sdhci_tegra {
	const struct sdhci_tegra_soc_data *soc_data;
	struct gpio_desc *power_gpio;
	bool ddr_signaling;
	bool pad_calib_required;
};

static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
			(reg == SDHCI_HOST_VERSION))) {
		/* Erratum: Version register is invalid in HW. */
		return SDHCI_SPEC_200;
	}

	return readw(host->ioaddr + reg);
}

static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	switch (reg) {
	case SDHCI_TRANSFER_MODE:
		/*
		 * Postpone this write, we must do it together with a
		 * command write that is down below.
		 */
		pltfm_host->xfer_mode_shadow = val;
		return;
	case SDHCI_COMMAND:
		writel((val << 16) | pltfm_host->xfer_mode_shadow,
			host->ioaddr + SDHCI_TRANSFER_MODE);
		return;
	}

	writew(val, host->ioaddr + reg);
}

static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	/* Seems like we're getting spurious timeout and crc errors, so
	 * disable signalling of them. In case of real errors software
	 * timers should take care of eventually detecting them.
	 */
	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
		val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);

	writel(val, host->ioaddr + reg);

	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
			(reg == SDHCI_INT_ENABLE))) {
		/* Erratum: Must enable block gap interrupt detection */
		u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
		if (val & SDHCI_INT_CARD_INT)
			gap_ctrl |= 0x8;
		else
			gap_ctrl &= ~0x8;
		writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	}
}

static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
{
	return mmc_gpio_get_ro(host->mmc);
}

static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	u32 misc_ctrl, clk_ctrl;

	sdhci_reset(host, mask);

	if (!(mask & SDHCI_RESET_ALL))
		return;

	misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
	clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);

	misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
		       SDHCI_MISC_CTRL_ENABLE_SDR50 |
		       SDHCI_MISC_CTRL_ENABLE_DDR50 |
		       SDHCI_MISC_CTRL_ENABLE_SDR104);

	clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;

	/*
	 * If the board does not define a regulator for the SDHCI
	 * IO voltage, then don't advertise support for UHS modes
	 * even if the device supports it because the IO voltage
	 * cannot be configured.
	 */
	if (!IS_ERR(host->mmc->supply.vqmmc)) {
		/* Erratum: Enable SDHCI spec v3.00 support */
		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
			misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
		/* Advertise UHS modes as supported by host */
		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
			misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
		if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
			misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
			misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
		if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
			clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
	}

	sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
	sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);

	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
		tegra_host->pad_calib_required = true;

	tegra_host->ddr_signaling = false;
}

static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
{
	u32 ctrl;

	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
	    (bus_width == MMC_BUS_WIDTH_8)) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (bus_width == MMC_BUS_WIDTH_4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}

static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
{
	u32 val;

	mdelay(1);

	val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
	val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
	sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
}

static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	unsigned long host_clk;

	if (!clock)
		return sdhci_set_clock(host, clock);

	host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
	clk_set_rate(pltfm_host->clk, host_clk);
	host->max_clk = clk_get_rate(pltfm_host->clk);

	sdhci_set_clock(host, clock);

	if (tegra_host->pad_calib_required) {
		tegra_sdhci_pad_autocalib(host);
		tegra_host->pad_calib_required = false;
	}
}

static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
					  unsigned timing)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);

	if (timing == MMC_TIMING_UHS_DDR50)
		tegra_host->ddr_signaling = true;

	return sdhci_set_uhs_signaling(host, timing);
}

static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	/*
	 * DDR modes require the host to run at double the card frequency, so
	 * the maximum rate we can support is half of the module input clock.
	 */
	return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2;
}

static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
{
	u32 reg;

	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
	reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
	reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
	sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
}

static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
{
	unsigned int min, max;

	/*
	 * Start search for minimum tap value at 10, as smaller values are
	 * may wrongly be reported as working but fail at higher speeds,
	 * according to the TRM.
	 */
	min = 10;
	while (min < 255) {
		tegra_sdhci_set_tap(host, min);
		if (!mmc_send_tuning(host->mmc, opcode, NULL))
			break;
		min++;
	}

	/* Find the maximum tap value that still passes. */
	max = min + 1;
	while (max < 255) {
		tegra_sdhci_set_tap(host, max);
		if (mmc_send_tuning(host->mmc, opcode, NULL)) {
			max--;
			break;
		}
		max++;
	}

	/* The TRM states the ideal tap value is at 75% in the passing range. */
	tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));

	return mmc_send_tuning(host->mmc, opcode, NULL);
}

static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
		tegra_host->pad_calib_required = true;
}

static const struct sdhci_ops tegra_sdhci_ops = {
	.get_ro     = tegra_sdhci_get_ro,
	.read_w     = tegra_sdhci_readw,
	.write_l    = tegra_sdhci_writel,
	.set_clock  = tegra_sdhci_set_clock,
	.set_bus_width = tegra_sdhci_set_bus_width,
	.reset      = tegra_sdhci_reset,
	.platform_execute_tuning = tegra_sdhci_execute_tuning,
	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
	.voltage_switch = tegra_sdhci_voltage_switch,
	.get_max_clock = tegra_sdhci_get_max_clock,
};

static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
	.pdata = &sdhci_tegra20_pdata,
	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
		    NVQUIRK_ENABLE_BLOCK_GAP_DET,
};

static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
	.pdata = &sdhci_tegra30_pdata,
	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
		    NVQUIRK_ENABLE_SDR50 |
		    NVQUIRK_ENABLE_SDR104 |
		    NVQUIRK_HAS_PADCALIB,
};

static const struct sdhci_ops tegra114_sdhci_ops = {
	.get_ro     = tegra_sdhci_get_ro,
	.read_w     = tegra_sdhci_readw,
	.write_w    = tegra_sdhci_writew,
	.write_l    = tegra_sdhci_writel,
	.set_clock  = tegra_sdhci_set_clock,
	.set_bus_width = tegra_sdhci_set_bus_width,
	.reset      = tegra_sdhci_reset,
	.platform_execute_tuning = tegra_sdhci_execute_tuning,
	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
	.voltage_switch = tegra_sdhci_voltage_switch,
	.get_max_clock = tegra_sdhci_get_max_clock,
};

static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.ops  = &tegra114_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
	.pdata = &sdhci_tegra114_pdata,
};

static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
		   /*
		    * The TRM states that the SD/MMC controller found on
		    * Tegra124 can address 34 bits (the maximum supported by
		    * the Tegra memory controller), but tests show that DMA
		    * to or from above 4 GiB doesn't work. This is possibly
		    * caused by missing programming, though it's not obvious
		    * what sequence is required. Mark 64-bit DMA broken for
		    * now to fix this for existing users (e.g. Nyan boards).
		    */
		   SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
	.ops  = &tegra114_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
	.pdata = &sdhci_tegra124_pdata,
};

static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.ops  = &tegra114_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
	.pdata = &sdhci_tegra210_pdata,
};

static const struct of_device_id sdhci_tegra_dt_match[] = {
	{ .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
	{}
};
MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);

static int sdhci_tegra_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	const struct sdhci_tegra_soc_data *soc_data;
	struct sdhci_host *host;
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_tegra *tegra_host;
	struct clk *clk;
	int rc;

	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
	if (!match)
		return -EINVAL;
	soc_data = match->data;

	host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
	if (IS_ERR(host))
		return PTR_ERR(host);
	pltfm_host = sdhci_priv(host);

	tegra_host = sdhci_pltfm_priv(pltfm_host);
	tegra_host->ddr_signaling = false;
	tegra_host->pad_calib_required = false;
	tegra_host->soc_data = soc_data;

	rc = mmc_of_parse(host->mmc);
	if (rc)
		goto err_parse_dt;

	if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
		host->mmc->caps |= MMC_CAP_1_8V_DDR;

	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
							 GPIOD_OUT_HIGH);
	if (IS_ERR(tegra_host->power_gpio)) {
		rc = PTR_ERR(tegra_host->power_gpio);
		goto err_power_req;
	}

	clk = devm_clk_get(mmc_dev(host->mmc), NULL);
	if (IS_ERR(clk)) {
		dev_err(mmc_dev(host->mmc), "clk err\n");
		rc = PTR_ERR(clk);
		goto err_clk_get;
	}
	clk_prepare_enable(clk);
	pltfm_host->clk = clk;

	rc = sdhci_add_host(host);
	if (rc)
		goto err_add_host;

	return 0;

err_add_host:
	clk_disable_unprepare(pltfm_host->clk);
err_clk_get:
err_power_req:
err_parse_dt:
	sdhci_pltfm_free(pdev);
	return rc;
}

static struct platform_driver sdhci_tegra_driver = {
	.driver		= {
		.name	= "sdhci-tegra",
		.of_match_table = sdhci_tegra_dt_match,
		.pm	= &sdhci_pltfm_pmops,
	},
	.probe		= sdhci_tegra_probe,
	.remove		= sdhci_pltfm_unregister,
};

module_platform_driver(sdhci_tegra_driver);

MODULE_DESCRIPTION("SDHCI driver for Tegra");
MODULE_AUTHOR("Google, Inc.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
03d2bfc8 OJ	1	/*
	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	*/
	14
e5c63d91	15	#include <linux/delay.h>
03d2bfc8	16	#include <linux/err.h>
96547f5d	17	#include <linux/module.h>
03d2bfc8 OJ	18	#include <linux/init.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/clk.h>
	21	#include <linux/io.h>
55cd65e4	22	#include <linux/of.h>
3e44a1a7	23	#include <linux/of_device.h>
03d2bfc8 OJ	24	#include <linux/mmc/card.h>
03d2bfc8 OJ	25	#include <linux/mmc/host.h>
c3c2384c	26	#include <linux/mmc/mmc.h>
0aacd23f	27	#include <linux/mmc/slot-gpio.h>
2391b340	28	#include <linux/gpio/consumer.h>
03d2bfc8	29
03d2bfc8 OJ	30	#include "sdhci-pltfm.h"
03d2bfc8 OJ	31
ca5879d3	32	/* Tegra SDHOST controller vendor register definitions */
74cd42bc	33	#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
c3c2384c LS	34	#define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
	35	#define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
	36	#define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
74cd42bc LS	37	#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
	38	#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
	39
ca5879d3	40	#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
3145351a AB	41	#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
3145351a AB	42	#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
ca5879d3	43	#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
3145351a	44	#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
ca5879d3	45
e5c63d91 LS	46	#define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
	47	#define SDHCI_AUTO_CAL_START BIT(31)
	48	#define SDHCI_AUTO_CAL_ENABLE BIT(29)
	49
3e44a1a7 SW	50	#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
3e44a1a7 SW	51	#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
ca5879d3	52	#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
7ad2ed1d LS	53	#define NVQUIRK_ENABLE_SDR50 BIT(3)
	54	#define NVQUIRK_ENABLE_SDR104 BIT(4)
	55	#define NVQUIRK_ENABLE_DDR50 BIT(5)
e5c63d91	56	#define NVQUIRK_HAS_PADCALIB BIT(6)
3e44a1a7 SW	57
3e44a1a7 SW	58	struct sdhci_tegra_soc_data {
1db5eebf	59	const struct sdhci_pltfm_data *pdata;
3e44a1a7 SW	60	u32 nvquirks;
	61	};
	62
	63	struct sdhci_tegra {
3e44a1a7	64	const struct sdhci_tegra_soc_data *soc_data;
2391b340	65	struct gpio_desc *power_gpio;
a8e326a9	66	bool ddr_signaling;
e5c63d91	67	bool pad_calib_required;
3e44a1a7 SW	68	};
3e44a1a7 SW	69
03d2bfc8 OJ	70	static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
03d2bfc8 OJ	71	{
3e44a1a7	72	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0734e79c	73	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
3e44a1a7 SW	74	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	75
	76	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
	77	(reg == SDHCI_HOST_VERSION))) {
03d2bfc8 OJ	78	/* Erratum: Version register is invalid in HW. */
	79	return SDHCI_SPEC_200;
	80	}
	81
	82	return readw(host->ioaddr + reg);
	83	}
	84
352ee868 PK	85	static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	86	{
	87	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
352ee868	88
01df7ecd RK	89	switch (reg) {
	90	case SDHCI_TRANSFER_MODE:
	91	/*
	92	* Postpone this write, we must do it together with a
	93	* command write that is down below.
	94	*/
	95	pltfm_host->xfer_mode_shadow = val;
	96	return;
	97	case SDHCI_COMMAND:
	98	writel((val << 16) \| pltfm_host->xfer_mode_shadow,
	99	host->ioaddr + SDHCI_TRANSFER_MODE);
	100	return;
352ee868 PK	101	}
	102
	103	writew(val, host->ioaddr + reg);
	104	}
	105
03d2bfc8 OJ	106	static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
03d2bfc8 OJ	107	{
3e44a1a7	108	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0734e79c	109	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
3e44a1a7 SW	110	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
3e44a1a7 SW	111
03d2bfc8 OJ	112	/* Seems like we're getting spurious timeout and crc errors, so
	113	* disable signalling of them. In case of real errors software
	114	* timers should take care of eventually detecting them.
	115	*/
	116	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
	117	val &= ~(SDHCI_INT_TIMEOUT\|SDHCI_INT_CRC);
	118
	119	writel(val, host->ioaddr + reg);
	120
3e44a1a7 SW	121	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
3e44a1a7 SW	122	(reg == SDHCI_INT_ENABLE))) {
03d2bfc8 OJ	123	/* Erratum: Must enable block gap interrupt detection */
	124	u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	125	if (val & SDHCI_INT_CARD_INT)
	126	gap_ctrl \|= 0x8;
	127	else
	128	gap_ctrl &= ~0x8;
	129	writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	130	}
	131	}
	132
3e44a1a7	133	static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
03d2bfc8	134	{
0aacd23f	135	return mmc_gpio_get_ro(host->mmc);
03d2bfc8 OJ	136	}
03d2bfc8 OJ	137
03231f9b	138	static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
ca5879d3 PK	139	{
ca5879d3 PK	140	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0734e79c	141	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
ca5879d3	142	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
74cd42bc	143	u32 misc_ctrl, clk_ctrl;
ca5879d3	144
03231f9b RK	145	sdhci_reset(host, mask);
03231f9b RK	146
ca5879d3 PK	147	if (!(mask & SDHCI_RESET_ALL))
	148	return;
	149
1b84def8	150	misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
74cd42bc	151	clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
4f6aa326 JH	152
	153	misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 \|
	154	SDHCI_MISC_CTRL_ENABLE_SDR50 \|
	155	SDHCI_MISC_CTRL_ENABLE_DDR50 \|
	156	SDHCI_MISC_CTRL_ENABLE_SDR104);
	157
74cd42bc	158	clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
4f6aa326 JH	159
	160	/*
	161	* If the board does not define a regulator for the SDHCI
	162	* IO voltage, then don't advertise support for UHS modes
	163	* even if the device supports it because the IO voltage
	164	* cannot be configured.
	165	*/
	166	if (!IS_ERR(host->mmc->supply.vqmmc)) {
	167	/* Erratum: Enable SDHCI spec v3.00 support */
	168	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
	169	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
	170	/* Advertise UHS modes as supported by host */
	171	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
	172	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_SDR50;
	173	if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
	174	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_DDR50;
	175	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
	176	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_SDR104;
	177	if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
	178	clk_ctrl \|= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
	179	}
	180
	181	sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
74cd42bc LS	182	sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
74cd42bc LS	183
e5c63d91 LS	184	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
	185	tegra_host->pad_calib_required = true;
	186
a8e326a9	187	tegra_host->ddr_signaling = false;
ca5879d3 PK	188	}
ca5879d3 PK	189
2317f56c	190	static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
03d2bfc8	191	{
03d2bfc8 OJ	192	u32 ctrl;
03d2bfc8 OJ	193
03d2bfc8	194	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
0aacd23f JL	195	if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
0aacd23f JL	196	(bus_width == MMC_BUS_WIDTH_8)) {
03d2bfc8 OJ	197	ctrl &= ~SDHCI_CTRL_4BITBUS;
	198	ctrl \|= SDHCI_CTRL_8BITBUS;
	199	} else {
	200	ctrl &= ~SDHCI_CTRL_8BITBUS;
	201	if (bus_width == MMC_BUS_WIDTH_4)
	202	ctrl \|= SDHCI_CTRL_4BITBUS;
	203	else
	204	ctrl &= ~SDHCI_CTRL_4BITBUS;
	205	}
	206	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
03d2bfc8 OJ	207	}
03d2bfc8 OJ	208
e5c63d91 LS	209	static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
	210	{
	211	u32 val;
	212
	213	mdelay(1);
	214
	215	val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
	216	val \|= SDHCI_AUTO_CAL_ENABLE \| SDHCI_AUTO_CAL_START;
	217	sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
	218	}
	219
a8e326a9 LS	220	static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
	221	{
	222	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0734e79c	223	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
a8e326a9 LS	224	unsigned long host_clk;
	225
	226	if (!clock)
3491b690	227	return sdhci_set_clock(host, clock);
a8e326a9 LS	228
	229	host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
	230	clk_set_rate(pltfm_host->clk, host_clk);
	231	host->max_clk = clk_get_rate(pltfm_host->clk);
	232
e5c63d91 LS	233	sdhci_set_clock(host, clock);
	234
	235	if (tegra_host->pad_calib_required) {
	236	tegra_sdhci_pad_autocalib(host);
	237	tegra_host->pad_calib_required = false;
	238	}
a8e326a9 LS	239	}
	240
	241	static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
	242	unsigned timing)
	243	{
	244	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0734e79c	245	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
a8e326a9 LS	246
	247	if (timing == MMC_TIMING_UHS_DDR50)
	248	tegra_host->ddr_signaling = true;
	249
	250	return sdhci_set_uhs_signaling(host, timing);
	251	}
	252
	253	static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
	254	{
	255	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	256
	257	/*
	258	* DDR modes require the host to run at double the card frequency, so
	259	* the maximum rate we can support is half of the module input clock.
	260	*/
	261	return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2;
	262	}
	263
c3c2384c LS	264	static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
	265	{
	266	u32 reg;
	267
	268	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
	269	reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
	270	reg \|= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
	271	sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
	272	}
	273
	274	static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
	275	{
	276	unsigned int min, max;
	277
	278	/*
	279	* Start search for minimum tap value at 10, as smaller values are
	280	* may wrongly be reported as working but fail at higher speeds,
	281	* according to the TRM.
	282	*/
	283	min = 10;
	284	while (min < 255) {
	285	tegra_sdhci_set_tap(host, min);
	286	if (!mmc_send_tuning(host->mmc, opcode, NULL))
	287	break;
	288	min++;
	289	}
	290
	291	/* Find the maximum tap value that still passes. */
	292	max = min + 1;
	293	while (max < 255) {
	294	tegra_sdhci_set_tap(host, max);
	295	if (mmc_send_tuning(host->mmc, opcode, NULL)) {
	296	max--;
	297	break;
	298	}
	299	max++;
	300	}
	301
	302	/* The TRM states the ideal tap value is at 75% in the passing range. */
	303	tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
	304
	305	return mmc_send_tuning(host->mmc, opcode, NULL);
	306	}
	307
e5c63d91 LS	308	static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
	309	{
	310	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	311	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	312	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	313
	314	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
	315	tegra_host->pad_calib_required = true;
	316	}
	317
c915568d	318	static const struct sdhci_ops tegra_sdhci_ops = {
85d6509d	319	.get_ro = tegra_sdhci_get_ro,
85d6509d SG	320	.read_w = tegra_sdhci_readw,
85d6509d SG	321	.write_l = tegra_sdhci_writel,
a8e326a9	322	.set_clock = tegra_sdhci_set_clock,
2317f56c	323	.set_bus_width = tegra_sdhci_set_bus_width,
03231f9b	324	.reset = tegra_sdhci_reset,
c3c2384c	325	.platform_execute_tuning = tegra_sdhci_execute_tuning,
a8e326a9	326	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
e5c63d91	327	.voltage_switch = tegra_sdhci_voltage_switch,
a8e326a9	328	.get_max_clock = tegra_sdhci_get_max_clock,
85d6509d SG	329	};
85d6509d SG	330
1db5eebf	331	static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
3e44a1a7 SW	332	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	333	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	334	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	335	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	336	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
3e44a1a7 SW	337	.ops = &tegra_sdhci_ops,
	338	};
	339
d49d19c2	340	static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
3e44a1a7 SW	341	.pdata = &sdhci_tegra20_pdata,
	342	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 \|
	343	NVQUIRK_ENABLE_BLOCK_GAP_DET,
	344	};
3e44a1a7	345
1db5eebf	346	static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
85d6509d	347	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
3e44a1a7	348	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
85d6509d SG	349	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
85d6509d SG	350	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	351	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	352	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
a8e326a9	353	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
85d6509d SG	354	.ops = &tegra_sdhci_ops,
85d6509d SG	355	};
03d2bfc8	356
d49d19c2	357	static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
3e44a1a7	358	.pdata = &sdhci_tegra30_pdata,
3145351a	359	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 \|
7ad2ed1d	360	NVQUIRK_ENABLE_SDR50 \|
e5c63d91 LS	361	NVQUIRK_ENABLE_SDR104 \|
e5c63d91 LS	362	NVQUIRK_HAS_PADCALIB,
3e44a1a7	363	};
3e44a1a7	364
01df7ecd RK	365	static const struct sdhci_ops tegra114_sdhci_ops = {
	366	.get_ro = tegra_sdhci_get_ro,
	367	.read_w = tegra_sdhci_readw,
	368	.write_w = tegra_sdhci_writew,
	369	.write_l = tegra_sdhci_writel,
a8e326a9	370	.set_clock = tegra_sdhci_set_clock,
01df7ecd RK	371	.set_bus_width = tegra_sdhci_set_bus_width,
01df7ecd RK	372	.reset = tegra_sdhci_reset,
c3c2384c	373	.platform_execute_tuning = tegra_sdhci_execute_tuning,
a8e326a9	374	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
e5c63d91	375	.voltage_switch = tegra_sdhci_voltage_switch,
a8e326a9	376	.get_max_clock = tegra_sdhci_get_max_clock,
01df7ecd RK	377	};
01df7ecd RK	378
1db5eebf	379	static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
5ebf2552 RK	380	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	381	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	382	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	383	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	384	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	385	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
a8e326a9	386	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
01df7ecd	387	.ops = &tegra114_sdhci_ops,
5ebf2552 RK	388	};
5ebf2552 RK	389
d49d19c2	390	static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
5ebf2552	391	.pdata = &sdhci_tegra114_pdata,
7bf037d6 JH	392	};
7bf037d6 JH	393
a0a2f1d8 TR	394	static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
	395	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	396	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	397	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	398	SDHCI_QUIRK_NO_HISPD_BIT \|
	399	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
	400	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	401	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN \|
	402	/*
	403	* The TRM states that the SD/MMC controller found on
	404	* Tegra124 can address 34 bits (the maximum supported by
	405	* the Tegra memory controller), but tests show that DMA
	406	* to or from above 4 GiB doesn't work. This is possibly
	407	* caused by missing programming, though it's not obvious
	408	* what sequence is required. Mark 64-bit DMA broken for
	409	* now to fix this for existing users (e.g. Nyan boards).
	410	*/
	411	SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
	412	.ops = &tegra114_sdhci_ops,
	413	};
	414
	415	static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
	416	.pdata = &sdhci_tegra124_pdata,
	417	};
	418
b5a84ecf TR	419	static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
	420	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	421	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	422	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	423	SDHCI_QUIRK_NO_HISPD_BIT \|
a8e326a9 LS	424	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
	425	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	426	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
b5a84ecf TR	427	.ops = &tegra114_sdhci_ops,
	428	};
	429
	430	static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
	431	.pdata = &sdhci_tegra210_pdata,
b5a84ecf TR	432	};
b5a84ecf TR	433
498d83e7	434	static const struct of_device_id sdhci_tegra_dt_match[] = {
b5a84ecf	435	{ .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
a0a2f1d8	436	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
5ebf2552	437	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
3e44a1a7	438	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
3e44a1a7	439	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
275173b2 GL	440	{}
275173b2 GL	441	};
e4404fab	442	MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
275173b2	443
c3be1efd	444	static int sdhci_tegra_probe(struct platform_device *pdev)
03d2bfc8	445	{
3e44a1a7 SW	446	const struct of_device_id *match;
	447	const struct sdhci_tegra_soc_data *soc_data;
	448	struct sdhci_host *host;
85d6509d	449	struct sdhci_pltfm_host *pltfm_host;
3e44a1a7	450	struct sdhci_tegra *tegra_host;
03d2bfc8 OJ	451	struct clk *clk;
	452	int rc;
	453
3e44a1a7	454	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
b37f9d98 JL	455	if (!match)
	456	return -EINVAL;
	457	soc_data = match->data;
3e44a1a7	458
0734e79c	459	host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
85d6509d SG	460	if (IS_ERR(host))
85d6509d SG	461	return PTR_ERR(host);
85d6509d SG	462	pltfm_host = sdhci_priv(host);
85d6509d SG	463
0734e79c	464	tegra_host = sdhci_pltfm_priv(pltfm_host);
a8e326a9	465	tegra_host->ddr_signaling = false;
e5c63d91	466	tegra_host->pad_calib_required = false;
3e44a1a7	467	tegra_host->soc_data = soc_data;
275173b2	468
2391b340	469	rc = mmc_of_parse(host->mmc);
47caa84f SB	470	if (rc)
47caa84f SB	471	goto err_parse_dt;
0e786102	472
7ad2ed1d	473	if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
c3c2384c LS	474	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
c3c2384c LS	475
2391b340 MJ	476	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
	477	GPIOD_OUT_HIGH);
	478	if (IS_ERR(tegra_host->power_gpio)) {
	479	rc = PTR_ERR(tegra_host->power_gpio);
	480	goto err_power_req;
03d2bfc8 OJ	481	}
03d2bfc8 OJ	482
e4f79d9c	483	clk = devm_clk_get(mmc_dev(host->mmc), NULL);
03d2bfc8 OJ	484	if (IS_ERR(clk)) {
	485	dev_err(mmc_dev(host->mmc), "clk err\n");
	486	rc = PTR_ERR(clk);
85d6509d	487	goto err_clk_get;
03d2bfc8	488	}
1e674bc6	489	clk_prepare_enable(clk);
03d2bfc8 OJ	490	pltfm_host->clk = clk;
03d2bfc8 OJ	491
85d6509d SG	492	rc = sdhci_add_host(host);
	493	if (rc)
	494	goto err_add_host;
	495
03d2bfc8 OJ	496	return 0;
03d2bfc8 OJ	497
85d6509d	498	err_add_host:
1e674bc6	499	clk_disable_unprepare(pltfm_host->clk);
85d6509d	500	err_clk_get:
85d6509d	501	err_power_req:
47caa84f	502	err_parse_dt:
85d6509d	503	sdhci_pltfm_free(pdev);
03d2bfc8 OJ	504	return rc;
	505	}
	506
85d6509d SG	507	static struct platform_driver sdhci_tegra_driver = {
	508	.driver = {
	509	.name = "sdhci-tegra",
275173b2	510	.of_match_table = sdhci_tegra_dt_match,
fa243f64	511	.pm = &sdhci_pltfm_pmops,
85d6509d SG	512	},
85d6509d SG	513	.probe = sdhci_tegra_probe,
caebcae9	514	.remove = sdhci_pltfm_unregister,
03d2bfc8 OJ	515	};
03d2bfc8 OJ	516
d1f81a64	517	module_platform_driver(sdhci_tegra_driver);
85d6509d SG	518
85d6509d SG	519	MODULE_DESCRIPTION("SDHCI driver for Tegra");
3e44a1a7	520	MODULE_AUTHOR("Google, Inc.");
85d6509d	521	MODULE_LICENSE("GPL v2");