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Merge remote-tracking branch 'iommu/next'
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
66fd8ad5 44static unsigned int debug_quirks2;
67435274 45
d129bceb
PO		 46static void sdhci_finish_data(struct sdhci_host *);
47
52983382 48static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb
PO		 49
50static void sdhci_dumpregs(struct sdhci_host *host)
51{
a7c53671
CD		 52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host->mmc));
d129bceb 54
a7c53671
CD		 55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
57 sdhci_readw(host, SDHCI_HOST_VERSION));
58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
62 sdhci_readl(host, SDHCI_ARGUMENT),
63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
65 sdhci_readl(host, SDHCI_PRESENT_STATE),
66 sdhci_readb(host, SDHCI_HOST_CONTROL));
67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
68 sdhci_readb(host, SDHCI_POWER_CONTROL),
69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
75 sdhci_readl(host, SDHCI_INT_STATUS));
76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
77 sdhci_readl(host, SDHCI_INT_ENABLE),
78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
80 sdhci_readw(host, SDHCI_ACMD12_ERR),
81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
83 sdhci_readl(host, SDHCI_CAPABILITIES),
84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host, SDHCI_COMMAND),
87 sdhci_readl(host, SDHCI_MAX_CURRENT));
88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 90
e57a5f61
AH		 91 if (host->flags & SDHCI_USE_ADMA) {
92 if (host->flags & SDHCI_USE_64_BIT_DMA)
a7c53671
CD		 93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
94 readl(host->ioaddr + SDHCI_ADMA_ERROR),
95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 97 else
a7c53671
CD		 98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
99 readl(host->ioaddr + SDHCI_ADMA_ERROR),
100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 101 }
be3f4ae0 102
a7c53671 103 pr_err(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 104}
105
106/*****************************************************************************\
107 * *
108 * Low level functions *
109 * *
110\*****************************************************************************/
111
56a590dc
AH		 112static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
113{
114 return cmd->data || cmd->flags & MMC_RSP_BUSY;
115}
116
7260cf5e
AV		 117static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
118{
5b4f1f6c 119 u32 present;
7260cf5e 120
c79396c1 121 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
860951c5 122 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 123 return;
124
5b4f1f6c
RK		 125 if (enable) {
126 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
127 SDHCI_CARD_PRESENT;
d25928d1 128
5b4f1f6c
RK		 129 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
130 SDHCI_INT_CARD_INSERT;
131 } else {
132 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
133 }
b537f94c
RK		 134
135 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
136 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 137}
138
139static void sdhci_enable_card_detection(struct sdhci_host *host)
140{
141 sdhci_set_card_detection(host, true);
142}
143
144static void sdhci_disable_card_detection(struct sdhci_host *host)
145{
146 sdhci_set_card_detection(host, false);
147}
148
02d0b685
UH		 149static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
150{
151 if (host->bus_on)
152 return;
153 host->bus_on = true;
154 pm_runtime_get_noresume(host->mmc->parent);
155}
156
157static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
158{
159 if (!host->bus_on)
160 return;
161 host->bus_on = false;
162 pm_runtime_put_noidle(host->mmc->parent);
163}
164
03231f9b 165void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 166{
e16514d8 167 unsigned long timeout;
393c1a34 168
4e4141a5 169 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 170
f0710a55 171 if (mask & SDHCI_RESET_ALL) {
d129bceb 172 host->clock = 0;
f0710a55
AH		 173 /* Reset-all turns off SD Bus Power */
174 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
175 sdhci_runtime_pm_bus_off(host);
176 }
d129bceb 177
e16514d8
PO		 178 /* Wait max 100 ms */
179 timeout = 100;
180
181 /* hw clears the bit when it's done */
4e4141a5 182 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 183 if (timeout == 0) {
a3c76eb9 184 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 185 mmc_hostname(host->mmc), (int)mask);
186 sdhci_dumpregs(host);
187 return;
188 }
189 timeout--;
190 mdelay(1);
d129bceb 191 }
03231f9b
RK		 192}
193EXPORT_SYMBOL_GPL(sdhci_reset);
194
195static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
196{
197 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 198 struct mmc_host *mmc = host->mmc;
199
200 if (!mmc->ops->get_cd(mmc))
03231f9b
RK		 201 return;
202 }
063a9dbb 203
03231f9b 204 host->ops->reset(host, mask);
393c1a34 205
da91a8f9
RK		 206 if (mask & SDHCI_RESET_ALL) {
207 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
208 if (host->ops->enable_dma)
209 host->ops->enable_dma(host);
210 }
211
212 /* Resetting the controller clears many */
213 host->preset_enabled = false;
3abc1e80 214 }
d129bceb
PO		 215}
216
2f4cbb3d 217static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 218{
d3940f27
AH		 219 struct mmc_host *mmc = host->mmc;
220
2f4cbb3d 221 if (soft)
03231f9b 222 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 223 else
03231f9b 224 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 225
b537f94c
RK		 226 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
227 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
228 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
229 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
230 SDHCI_INT_RESPONSE;
231
f37b20eb
DA		 232 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
233 host->tuning_mode == SDHCI_TUNING_MODE_3)
234 host->ier |= SDHCI_INT_RETUNE;
235
b537f94c
RK		 236 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
237 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 238
239 if (soft) {
240 /* force clock reconfiguration */
241 host->clock = 0;
d3940f27 242 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 243 }
7260cf5e 244}
d129bceb 245
7260cf5e
AV		 246static void sdhci_reinit(struct sdhci_host *host)
247{
2f4cbb3d 248 sdhci_init(host, 0);
7260cf5e 249 sdhci_enable_card_detection(host);
d129bceb
PO		 250}
251
061d17a6 252static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 253{
254 u8 ctrl;
255
4e4141a5 256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 257 ctrl |= SDHCI_CTRL_LED;
4e4141a5 258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 259}
260
061d17a6 261static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 262{
263 u8 ctrl;
264
4e4141a5 265 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 266 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 267 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 268}
269
4f78230f 270#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 271static void sdhci_led_control(struct led_classdev *led,
061d17a6 272 enum led_brightness brightness)
2f730fec
PO		 273{
274 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
275 unsigned long flags;
276
277 spin_lock_irqsave(&host->lock, flags);
278
66fd8ad5
AH		 279 if (host->runtime_suspended)
280 goto out;
281
2f730fec 282 if (brightness == LED_OFF)
061d17a6 283 __sdhci_led_deactivate(host);
2f730fec 284 else
061d17a6 285 __sdhci_led_activate(host);
66fd8ad5 286out:
2f730fec
PO		 287 spin_unlock_irqrestore(&host->lock, flags);
288}
061d17a6
AH		 289
290static int sdhci_led_register(struct sdhci_host *host)
291{
292 struct mmc_host *mmc = host->mmc;
293
294 snprintf(host->led_name, sizeof(host->led_name),
295 "%s::", mmc_hostname(mmc));
296
297 host->led.name = host->led_name;
298 host->led.brightness = LED_OFF;
299 host->led.default_trigger = mmc_hostname(mmc);
300 host->led.brightness_set = sdhci_led_control;
301
302 return led_classdev_register(mmc_dev(mmc), &host->led);
303}
304
305static void sdhci_led_unregister(struct sdhci_host *host)
306{
307 led_classdev_unregister(&host->led);
308}
309
310static inline void sdhci_led_activate(struct sdhci_host *host)
311{
312}
313
314static inline void sdhci_led_deactivate(struct sdhci_host *host)
315{
316}
317
318#else
319
320static inline int sdhci_led_register(struct sdhci_host *host)
321{
322 return 0;
323}
324
325static inline void sdhci_led_unregister(struct sdhci_host *host)
326{
327}
328
329static inline void sdhci_led_activate(struct sdhci_host *host)
330{
331 __sdhci_led_activate(host);
332}
333
334static inline void sdhci_led_deactivate(struct sdhci_host *host)
335{
336 __sdhci_led_deactivate(host);
337}
338
2f730fec
PO		 339#endif
340
d129bceb
PO		 341/*****************************************************************************\
342 * *
343 * Core functions *
344 * *
345\*****************************************************************************/
346
a406f5a3 347static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 348{
7659150c
PO		 349 unsigned long flags;
350 size_t blksize, len, chunk;
7244b85b 351 u32 uninitialized_var(scratch);
7659150c 352 u8 *buf;
d129bceb 353
a406f5a3 354 DBG("PIO reading\n");
d129bceb 355
a406f5a3 356 blksize = host->data->blksz;
7659150c 357 chunk = 0;
d129bceb 358
7659150c 359 local_irq_save(flags);
d129bceb 360
a406f5a3 361 while (blksize) {
bf3a35ac 362 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 363
7659150c 364 len = min(host->sg_miter.length, blksize);
d129bceb 365
7659150c
PO		 366 blksize -= len;
367 host->sg_miter.consumed = len;
14d836e7 368
7659150c 369 buf = host->sg_miter.addr;
d129bceb 370
7659150c
PO		 371 while (len) {
372 if (chunk == 0) {
4e4141a5 373 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 374 chunk = 4;
a406f5a3 375 }
7659150c
PO		 376
377 *buf = scratch & 0xFF;
378
379 buf++;
380 scratch >>= 8;
381 chunk--;
382 len--;
d129bceb 383 }
a406f5a3 384 }
7659150c
PO		 385
386 sg_miter_stop(&host->sg_miter);
387
388 local_irq_restore(flags);
a406f5a3 389}
d129bceb 390
a406f5a3
PO		 391static void sdhci_write_block_pio(struct sdhci_host *host)
392{
7659150c
PO		 393 unsigned long flags;
394 size_t blksize, len, chunk;
395 u32 scratch;
396 u8 *buf;
d129bceb 397
a406f5a3
PO		 398 DBG("PIO writing\n");
399
400 blksize = host->data->blksz;
7659150c
PO		 401 chunk = 0;
402 scratch = 0;
d129bceb 403
7659150c 404 local_irq_save(flags);
d129bceb 405
a406f5a3 406 while (blksize) {
bf3a35ac 407 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 408
7659150c
PO		 409 len = min(host->sg_miter.length, blksize);
410
411 blksize -= len;
412 host->sg_miter.consumed = len;
413
414 buf = host->sg_miter.addr;
d129bceb 415
7659150c
PO		 416 while (len) {
417 scratch |= (u32)*buf << (chunk * 8);
418
419 buf++;
420 chunk++;
421 len--;
422
423 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 424 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 425 chunk = 0;
426 scratch = 0;
d129bceb 427 }
d129bceb
PO		 428 }
429 }
7659150c
PO		 430
431 sg_miter_stop(&host->sg_miter);
432
433 local_irq_restore(flags);
a406f5a3
PO		 434}
435
436static void sdhci_transfer_pio(struct sdhci_host *host)
437{
438 u32 mask;
439
7659150c 440 if (host->blocks == 0)
a406f5a3
PO		 441 return;
442
443 if (host->data->flags & MMC_DATA_READ)
444 mask = SDHCI_DATA_AVAILABLE;
445 else
446 mask = SDHCI_SPACE_AVAILABLE;
447
4a3cba32
PO		 448 /*
449 * Some controllers (JMicron JMB38x) mess up the buffer bits
450 * for transfers < 4 bytes. As long as it is just one block,
451 * we can ignore the bits.
452 */
453 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
454 (host->data->blocks == 1))
455 mask = ~0;
456
4e4141a5 457 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 458 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
459 udelay(100);
460
a406f5a3
PO		 461 if (host->data->flags & MMC_DATA_READ)
462 sdhci_read_block_pio(host);
463 else
464 sdhci_write_block_pio(host);
d129bceb 465
7659150c
PO		 466 host->blocks--;
467 if (host->blocks == 0)
a406f5a3 468 break;
a406f5a3 469 }
d129bceb 470
a406f5a3 471 DBG("PIO transfer complete.\n");
d129bceb
PO		 472}
473
48857d9b 474static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 475 struct mmc_data *data, int cookie)
48857d9b
RK		 476{
477 int sg_count;
478
94538e51
RK		 479 /*
480 * If the data buffers are already mapped, return the previous
481 * dma_map_sg() result.
482 */
483 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 484 return data->sg_count;
48857d9b
RK		 485
486 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
487 data->flags & MMC_DATA_WRITE ?
488 DMA_TO_DEVICE : DMA_FROM_DEVICE);
489
490 if (sg_count == 0)
491 return -ENOSPC;
492
493 data->sg_count = sg_count;
c0999b72 494 data->host_cookie = cookie;
48857d9b
RK		 495
496 return sg_count;
497}
498
2134a922
PO		 499static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
500{
501 local_irq_save(*flags);
482fce99 502 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 503}
504
505static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
506{
482fce99 507 kunmap_atomic(buffer);
2134a922
PO		 508 local_irq_restore(*flags);
509}
510
e57a5f61
AH		 511static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
512 dma_addr_t addr, int len, unsigned cmd)
118cd17d 513{
e57a5f61 514 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 515
e57a5f61 516 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 517 dma_desc->cmd = cpu_to_le16(cmd);
518 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 519 dma_desc->addr_lo = cpu_to_le32((u32)addr);
520
521 if (host->flags & SDHCI_USE_64_BIT_DMA)
522 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 523}
524
b5ffa674
AH		 525static void sdhci_adma_mark_end(void *desc)
526{
e57a5f61 527 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 528
e57a5f61 529 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 530 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 531}
532
60c64762
RK		 533static void sdhci_adma_table_pre(struct sdhci_host *host,
534 struct mmc_data *data, int sg_count)
2134a922 535{
2134a922 536 struct scatterlist *sg;
2134a922 537 unsigned long flags;
acc3ad13
RK		 538 dma_addr_t addr, align_addr;
539 void *desc, *align;
540 char *buffer;
541 int len, offset, i;
2134a922
PO		 542
543 /*
544 * The spec does not specify endianness of descriptor table.
545 * We currently guess that it is LE.
546 */
547
60c64762 548 host->sg_count = sg_count;
2134a922 549
4efaa6fb 550 desc = host->adma_table;
2134a922
PO		 551 align = host->align_buffer;
552
553 align_addr = host->align_addr;
554
555 for_each_sg(data->sg, sg, host->sg_count, i) {
556 addr = sg_dma_address(sg);
557 len = sg_dma_len(sg);
558
559 /*
acc3ad13
RK		 560 * The SDHCI specification states that ADMA addresses must
561 * be 32-bit aligned. If they aren't, then we use a bounce
562 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 563 * alignment.
564 */
04a5ae6f
AH		 565 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
566 SDHCI_ADMA2_MASK;
2134a922
PO		 567 if (offset) {
568 if (data->flags & MMC_DATA_WRITE) {
569 buffer = sdhci_kmap_atomic(sg, &flags);
570 memcpy(align, buffer, offset);
571 sdhci_kunmap_atomic(buffer, &flags);
572 }
573
118cd17d 574 /* tran, valid */
e57a5f61 575 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 576 ADMA2_TRAN_VALID);
2134a922
PO		 577
578 BUG_ON(offset > 65536);
579
04a5ae6f
AH		 580 align += SDHCI_ADMA2_ALIGN;
581 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 582
76fe379a 583 desc += host->desc_sz;
2134a922
PO		 584
585 addr += offset;
586 len -= offset;
587 }
588
2134a922
PO		 589 BUG_ON(len > 65536);
590
347ea32d
AH		 591 if (len) {
592 /* tran, valid */
593 sdhci_adma_write_desc(host, desc, addr, len,
594 ADMA2_TRAN_VALID);
595 desc += host->desc_sz;
596 }
2134a922
PO		 597
598 /*
599 * If this triggers then we have a calculation bug
600 * somewhere. :/
601 */
76fe379a 602 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 603 }
604
70764a90 605 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 606 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 607 if (desc != host->adma_table) {
76fe379a 608 desc -= host->desc_sz;
b5ffa674 609 sdhci_adma_mark_end(desc);
70764a90
TA		 610 }
611 } else {
acc3ad13 612 /* Add a terminating entry - nop, end, valid */
e57a5f61 613 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 614 }
2134a922
PO		 615}
616
617static void sdhci_adma_table_post(struct sdhci_host *host,
618 struct mmc_data *data)
619{
2134a922
PO		 620 struct scatterlist *sg;
621 int i, size;
1c3d5f6d 622 void *align;
2134a922
PO		 623 char *buffer;
624 unsigned long flags;
625
47fa9613
RK		 626 if (data->flags & MMC_DATA_READ) {
627 bool has_unaligned = false;
de0b65a7 628
47fa9613
RK		 629 /* Do a quick scan of the SG list for any unaligned mappings */
630 for_each_sg(data->sg, sg, host->sg_count, i)
631 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
632 has_unaligned = true;
633 break;
634 }
2134a922 635
47fa9613
RK		 636 if (has_unaligned) {
637 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 638 data->sg_len, DMA_FROM_DEVICE);
2134a922 639
47fa9613 640 align = host->align_buffer;
2134a922 641
47fa9613
RK		 642 for_each_sg(data->sg, sg, host->sg_count, i) {
643 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
644 size = SDHCI_ADMA2_ALIGN -
645 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
646
647 buffer = sdhci_kmap_atomic(sg, &flags);
648 memcpy(buffer, align, size);
649 sdhci_kunmap_atomic(buffer, &flags);
2134a922 650
47fa9613
RK		 651 align += SDHCI_ADMA2_ALIGN;
652 }
2134a922
PO		 653 }
654 }
655 }
2134a922
PO		 656}
657
a3c7778f 658static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 659{
1c8cde92 660 u8 count;
a3c7778f 661 struct mmc_data *data = cmd->data;
1c8cde92 662 unsigned target_timeout, current_timeout;
d129bceb 663
ee53ab5d
PO		 664 /*
665 * If the host controller provides us with an incorrect timeout
666 * value, just skip the check and use 0xE. The hardware may take
667 * longer to time out, but that's much better than having a too-short
668 * timeout value.
669 */
11a2f1b7 670 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 671 return 0xE;
e538fbe8 672
a3c7778f 673 /* Unspecified timeout, assume max */
1d4d7744 674 if (!data && !cmd->busy_timeout)
a3c7778f 675 return 0xE;
d129bceb 676
a3c7778f
AW		 677 /* timeout in us */
678 if (!data)
1d4d7744 679 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 680 else {
fafcfda9 681 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 682 if (host->clock && data->timeout_clks) {
683 unsigned long long val;
684
685 /*
686 * data->timeout_clks is in units of clock cycles.
687 * host->clock is in Hz. target_timeout is in us.
688 * Hence, us = 1000000 * cycles / Hz. Round up.
689 */
690 val = 1000000 * data->timeout_clks;
691 if (do_div(val, host->clock))
692 target_timeout++;
693 target_timeout += val;
694 }
78a2ca27 695 }
81b39802 696
1c8cde92
PO		 697 /*
698 * Figure out needed cycles.
699 * We do this in steps in order to fit inside a 32 bit int.
700 * The first step is the minimum timeout, which will have a
701 * minimum resolution of 6 bits:
702 * (1) 2^13*1000 > 2^22,
703 * (2) host->timeout_clk < 2^16
704 * =>
705 * (1) / (2) > 2^6
706 */
707 count = 0;
708 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
709 while (current_timeout < target_timeout) {
710 count++;
711 current_timeout <<= 1;
712 if (count >= 0xF)
713 break;
714 }
715
716 if (count >= 0xF) {
09eeff52
CB		 717 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
718 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 719 count = 0xE;
720 }
721
ee53ab5d
PO		 722 return count;
723}
724
6aa943ab
AV		 725static void sdhci_set_transfer_irqs(struct sdhci_host *host)
726{
727 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
728 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
729
730 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 731 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 732 else
b537f94c
RK		 733 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
734
735 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
736 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 737}
738
b45e668a 739static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 740{
741 u8 count;
b45e668a
AD		 742
743 if (host->ops->set_timeout) {
744 host->ops->set_timeout(host, cmd);
745 } else {
746 count = sdhci_calc_timeout(host, cmd);
747 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
748 }
749}
750
751static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
752{
2134a922 753 u8 ctrl;
a3c7778f 754 struct mmc_data *data = cmd->data;
ee53ab5d 755
56a590dc 756 if (sdhci_data_line_cmd(cmd))
b45e668a 757 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 758
759 if (!data)
ee53ab5d
PO		 760 return;
761
43dea098
AH		 762 WARN_ON(host->data);
763
ee53ab5d
PO		 764 /* Sanity checks */
765 BUG_ON(data->blksz * data->blocks > 524288);
766 BUG_ON(data->blksz > host->mmc->max_blk_size);
767 BUG_ON(data->blocks > 65535);
768
769 host->data = data;
770 host->data_early = 0;
f6a03cbf 771 host->data->bytes_xfered = 0;
ee53ab5d 772
fce14421 773 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 774 struct scatterlist *sg;
df953925 775 unsigned int length_mask, offset_mask;
a0eaf0f9 776 int i;
2134a922 777
fce14421
RK		 778 host->flags |= SDHCI_REQ_USE_DMA;
779
780 /*
781 * FIXME: This doesn't account for merging when mapping the
782 * scatterlist.
783 *
784 * The assumption here being that alignment and lengths are
785 * the same after DMA mapping to device address space.
786 */
a0eaf0f9 787 length_mask = 0;
df953925 788 offset_mask = 0;
2134a922 789 if (host->flags & SDHCI_USE_ADMA) {
df953925 790 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 791 length_mask = 3;
df953925
RK		 792 /*
793 * As we use up to 3 byte chunks to work
794 * around alignment problems, we need to
795 * check the offset as well.
796 */
797 offset_mask = 3;
798 }
2134a922
PO		 799 } else {
800 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 801 length_mask = 3;
df953925
RK		 802 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
803 offset_mask = 3;
2134a922
PO		 804 }
805
df953925 806 if (unlikely(length_mask | offset_mask)) {
2134a922 807 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 808 if (sg->length & length_mask) {
2e4456f0 809 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 810 sg->length);
2134a922
PO		 811 host->flags &= ~SDHCI_REQ_USE_DMA;
812 break;
813 }
a0eaf0f9 814 if (sg->offset & offset_mask) {
2e4456f0 815 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 816 host->flags &= ~SDHCI_REQ_USE_DMA;
817 break;
818 }
819 }
820 }
821 }
822
8f1934ce 823 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 824 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 825
826 if (sg_cnt <= 0) {
827 /*
828 * This only happens when someone fed
829 * us an invalid request.
830 */
831 WARN_ON(1);
832 host->flags &= ~SDHCI_REQ_USE_DMA;
833 } else if (host->flags & SDHCI_USE_ADMA) {
834 sdhci_adma_table_pre(host, data, sg_cnt);
835
836 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
837 if (host->flags & SDHCI_USE_64_BIT_DMA)
838 sdhci_writel(host,
839 (u64)host->adma_addr >> 32,
840 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 841 } else {
60c64762
RK		 842 WARN_ON(sg_cnt != 1);
843 sdhci_writel(host, sg_dma_address(data->sg),
844 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 845 }
846 }
847
2134a922
PO		 848 /*
849 * Always adjust the DMA selection as some controllers
850 * (e.g. JMicron) can't do PIO properly when the selection
851 * is ADMA.
852 */
853 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 854 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 855 ctrl &= ~SDHCI_CTRL_DMA_MASK;
856 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 857 (host->flags & SDHCI_USE_ADMA)) {
858 if (host->flags & SDHCI_USE_64_BIT_DMA)
859 ctrl |= SDHCI_CTRL_ADMA64;
860 else
861 ctrl |= SDHCI_CTRL_ADMA32;
862 } else {
2134a922 863 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 864 }
4e4141a5 865 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 866 }
867
8f1934ce 868 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 869 int flags;
870
871 flags = SG_MITER_ATOMIC;
872 if (host->data->flags & MMC_DATA_READ)
873 flags |= SG_MITER_TO_SG;
874 else
875 flags |= SG_MITER_FROM_SG;
876 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 877 host->blocks = data->blocks;
d129bceb 878 }
c7fa9963 879
6aa943ab
AV		 880 sdhci_set_transfer_irqs(host);
881
f6a03cbf
MV		 882 /* Set the DMA boundary value and block size */
883 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
884 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 885 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 886}
887
0293d501
AH		 888static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
889 struct mmc_request *mrq)
890{
e466cd92
AH		 891 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
892 !mrq->cap_cmd_during_tfr;
0293d501
AH		 893}
894
c7fa9963 895static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 896 struct mmc_command *cmd)
c7fa9963 897{
d3fc5d71 898 u16 mode = 0;
e89d456f 899 struct mmc_data *data = cmd->data;
c7fa9963 900
2b558c13 901 if (data == NULL) {
9b8ffea6
VW		 902 if (host->quirks2 &
903 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
904 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
905 } else {
2b558c13 906 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 907 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
908 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 909 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 910 }
c7fa9963 911 return;
2b558c13 912 }
c7fa9963 913
e538fbe8
PO		 914 WARN_ON(!host->data);
915
d3fc5d71
VY		 916 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
917 mode = SDHCI_TRNS_BLK_CNT_EN;
918
e89d456f 919 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 920 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 921 /*
922 * If we are sending CMD23, CMD12 never gets sent
923 * on successful completion (so no Auto-CMD12).
924 */
0293d501 925 if (sdhci_auto_cmd12(host, cmd->mrq) &&
85cc1c33 926 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 927 mode |= SDHCI_TRNS_AUTO_CMD12;
a4c73aba 928 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
8edf6371 929 mode |= SDHCI_TRNS_AUTO_CMD23;
a4c73aba 930 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
8edf6371 931 }
c4512f79 932 }
8edf6371 933
c7fa9963
PO		 934 if (data->flags & MMC_DATA_READ)
935 mode |= SDHCI_TRNS_READ;
c9fddbc4 936 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 937 mode |= SDHCI_TRNS_DMA;
938
4e4141a5 939 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 940}
941
0cc563ce
AH		 942static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
943{
944 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
945 ((mrq->cmd && mrq->cmd->error) ||
946 (mrq->sbc && mrq->sbc->error) ||
947 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
948 (mrq->data->stop && mrq->data->stop->error))) ||
949 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
950}
951
4e9f8fe5
AH		 952static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
953{
954 int i;
955
956 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
957 if (host->mrqs_done[i] == mrq) {
958 WARN_ON(1);
959 return;
960 }
961 }
962
963 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
964 if (!host->mrqs_done[i]) {
965 host->mrqs_done[i] = mrq;
966 break;
967 }
968 }
969
970 WARN_ON(i >= SDHCI_MAX_MRQS);
971
972 tasklet_schedule(&host->finish_tasklet);
973}
974
a6d3bdd5
AH		 975static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
976{
5a8a3fef
AH		 977 if (host->cmd && host->cmd->mrq == mrq)
978 host->cmd = NULL;
979
980 if (host->data_cmd && host->data_cmd->mrq == mrq)
981 host->data_cmd = NULL;
982
983 if (host->data && host->data->mrq == mrq)
984 host->data = NULL;
985
ed1563de
AH		 986 if (sdhci_needs_reset(host, mrq))
987 host->pending_reset = true;
988
4e9f8fe5 989 __sdhci_finish_mrq(host, mrq);
a6d3bdd5
AH		 990}
991
d129bceb
PO		 992static void sdhci_finish_data(struct sdhci_host *host)
993{
33a57adb
AH		 994 struct mmc_command *data_cmd = host->data_cmd;
995 struct mmc_data *data = host->data;
d129bceb 996
d129bceb 997 host->data = NULL;
7c89a3d9 998 host->data_cmd = NULL;
d129bceb 999
add8913d
RK		 1000 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1001 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1002 sdhci_adma_table_post(host, data);
d129bceb
PO		 1003
1004 /*
c9b74c5b
PO		 1005 * The specification states that the block count register must
1006 * be updated, but it does not specify at what point in the
1007 * data flow. That makes the register entirely useless to read
1008 * back so we have to assume that nothing made it to the card
1009 * in the event of an error.
d129bceb 1010 */
c9b74c5b
PO		 1011 if (data->error)
1012 data->bytes_xfered = 0;
d129bceb 1013 else
c9b74c5b 1014 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 1015
e89d456f
AW		 1016 /*
1017 * Need to send CMD12 if -
1018 * a) open-ended multiblock transfer (no CMD23)
1019 * b) error in multiblock transfer
1020 */
1021 if (data->stop &&
1022 (data->error ||
a4c73aba 1023 !data->mrq->sbc)) {
e89d456f 1024
d129bceb
PO		 1025 /*
1026 * The controller needs a reset of internal state machines
1027 * upon error conditions.
1028 */
17b0429d 1029 if (data->error) {
33a57adb
AH		 1030 if (!host->cmd || host->cmd == data_cmd)
1031 sdhci_do_reset(host, SDHCI_RESET_CMD);
03231f9b 1032 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 1033 }
1034
e466cd92
AH		 1035 /*
1036 * 'cap_cmd_during_tfr' request must not use the command line
1037 * after mmc_command_done() has been called. It is upper layer's
1038 * responsibility to send the stop command if required.
1039 */
1040 if (data->mrq->cap_cmd_during_tfr) {
1041 sdhci_finish_mrq(host, data->mrq);
1042 } else {
1043 /* Avoid triggering warning in sdhci_send_command() */
1044 host->cmd = NULL;
1045 sdhci_send_command(host, data->stop);
1046 }
a6d3bdd5
AH		 1047 } else {
1048 sdhci_finish_mrq(host, data->mrq);
1049 }
d129bceb
PO		 1050}
1051
d7422fb4
AH		 1052static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1053 unsigned long timeout)
1054{
1055 if (sdhci_data_line_cmd(mrq->cmd))
1056 mod_timer(&host->data_timer, timeout);
1057 else
1058 mod_timer(&host->timer, timeout);
1059}
1060
1061static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1062{
1063 if (sdhci_data_line_cmd(mrq->cmd))
1064 del_timer(&host->data_timer);
1065 else
1066 del_timer(&host->timer);
1067}
1068
c0e55129 1069void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1070{
1071 int flags;
fd2208d7 1072 u32 mask;
7cb2c76f 1073 unsigned long timeout;
d129bceb
PO		 1074
1075 WARN_ON(host->cmd);
1076
96776200
RK		 1077 /* Initially, a command has no error */
1078 cmd->error = 0;
1079
d129bceb 1080 /* Wait max 10 ms */
7cb2c76f 1081 timeout = 10;
fd2208d7
PO		 1082
1083 mask = SDHCI_CMD_INHIBIT;
56a590dc 1084 if (sdhci_data_line_cmd(cmd))
fd2208d7
PO		 1085 mask |= SDHCI_DATA_INHIBIT;
1086
1087 /* We shouldn't wait for data inihibit for stop commands, even
1088 though they might use busy signaling */
a4c73aba 1089 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
fd2208d7
PO		 1090 mask &= ~SDHCI_DATA_INHIBIT;
1091
4e4141a5 1092 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1093 if (timeout == 0) {
2e4456f0
MV		 1094 pr_err("%s: Controller never released inhibit bit(s).\n",
1095 mmc_hostname(host->mmc));
d129bceb 1096 sdhci_dumpregs(host);
17b0429d 1097 cmd->error = -EIO;
a6d3bdd5 1098 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1099 return;
1100 }
7cb2c76f
PO		 1101 timeout--;
1102 mdelay(1);
1103 }
d129bceb 1104
3e1a6892 1105 timeout = jiffies;
1d4d7744
UH		 1106 if (!cmd->data && cmd->busy_timeout > 9000)
1107 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1108 else
1109 timeout += 10 * HZ;
d7422fb4 1110 sdhci_mod_timer(host, cmd->mrq, timeout);
d129bceb
PO		 1111
1112 host->cmd = cmd;
56a590dc 1113 if (sdhci_data_line_cmd(cmd)) {
7c89a3d9
AH		 1114 WARN_ON(host->data_cmd);
1115 host->data_cmd = cmd;
1116 }
d129bceb 1117
a3c7778f 1118 sdhci_prepare_data(host, cmd);
d129bceb 1119
4e4141a5 1120 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1121
e89d456f 1122 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1123
d129bceb 1124 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1125 pr_err("%s: Unsupported response type!\n",
d129bceb 1126 mmc_hostname(host->mmc));
17b0429d 1127 cmd->error = -EINVAL;
a6d3bdd5 1128 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1129 return;
1130 }
1131
1132 if (!(cmd->flags & MMC_RSP_PRESENT))
1133 flags = SDHCI_CMD_RESP_NONE;
1134 else if (cmd->flags & MMC_RSP_136)
1135 flags = SDHCI_CMD_RESP_LONG;
1136 else if (cmd->flags & MMC_RSP_BUSY)
1137 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1138 else
1139 flags = SDHCI_CMD_RESP_SHORT;
1140
1141 if (cmd->flags & MMC_RSP_CRC)
1142 flags |= SDHCI_CMD_CRC;
1143 if (cmd->flags & MMC_RSP_OPCODE)
1144 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1145
1146 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1147 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1148 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1149 flags |= SDHCI_CMD_DATA;
1150
4e4141a5 1151 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1152}
c0e55129 1153EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1154
1155static void sdhci_finish_command(struct sdhci_host *host)
1156{
e0a5640a 1157 struct mmc_command *cmd = host->cmd;
d129bceb
PO		 1158 int i;
1159
e0a5640a
AH		 1160 host->cmd = NULL;
1161
1162 if (cmd->flags & MMC_RSP_PRESENT) {
1163 if (cmd->flags & MMC_RSP_136) {
d129bceb
PO		 1164 /* CRC is stripped so we need to do some shifting. */
1165 for (i = 0;i < 4;i++) {
e0a5640a 1166 cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1167 SDHCI_RESPONSE + (3-i)*4) << 8;
1168 if (i != 3)
e0a5640a 1169 cmd->resp[i] |=
4e4141a5 1170 sdhci_readb(host,
d129bceb
PO		 1171 SDHCI_RESPONSE + (3-i)*4-1);
1172 }
1173 } else {
e0a5640a 1174 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1175 }
1176 }
1177
e466cd92
AH		 1178 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1179 mmc_command_done(host->mmc, cmd->mrq);
1180
6bde8681
AH		 1181 /*
1182 * The host can send and interrupt when the busy state has
1183 * ended, allowing us to wait without wasting CPU cycles.
1184 * The busy signal uses DAT0 so this is similar to waiting
1185 * for data to complete.
1186 *
1187 * Note: The 1.0 specification is a bit ambiguous about this
1188 * feature so there might be some problems with older
1189 * controllers.
1190 */
e0a5640a
AH		 1191 if (cmd->flags & MMC_RSP_BUSY) {
1192 if (cmd->data) {
6bde8681
AH		 1193 DBG("Cannot wait for busy signal when also doing a data transfer");
1194 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
ea968023
AH		 1195 cmd == host->data_cmd) {
1196 /* Command complete before busy is ended */
6bde8681
AH		 1197 return;
1198 }
1199 }
1200
e89d456f 1201 /* Finished CMD23, now send actual command. */
a4c73aba
AH		 1202 if (cmd == cmd->mrq->sbc) {
1203 sdhci_send_command(host, cmd->mrq->cmd);
e89d456f 1204 } else {
e538fbe8 1205
e89d456f
AW		 1206 /* Processed actual command. */
1207 if (host->data && host->data_early)
1208 sdhci_finish_data(host);
d129bceb 1209
e0a5640a 1210 if (!cmd->data)
a6d3bdd5 1211 sdhci_finish_mrq(host, cmd->mrq);
e89d456f 1212 }
d129bceb
PO		 1213}
1214
52983382
KL		 1215static u16 sdhci_get_preset_value(struct sdhci_host *host)
1216{
d975f121 1217 u16 preset = 0;
52983382 1218
d975f121
RK		 1219 switch (host->timing) {
1220 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1221 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1222 break;
d975f121 1223 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1224 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1225 break;
d975f121 1226 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1227 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1228 break;
d975f121
RK		 1229 case MMC_TIMING_UHS_SDR104:
1230 case MMC_TIMING_MMC_HS200:
52983382
KL		 1231 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1232 break;
d975f121 1233 case MMC_TIMING_UHS_DDR50:
0dafa60e 1234 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1235 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1236 break;
e9fb05d5
AH		 1237 case MMC_TIMING_MMC_HS400:
1238 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1239 break;
52983382
KL		 1240 default:
1241 pr_warn("%s: Invalid UHS-I mode selected\n",
1242 mmc_hostname(host->mmc));
1243 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1244 break;
1245 }
1246 return preset;
1247}
1248
fb9ee047
LD		 1249u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1250 unsigned int *actual_clock)
d129bceb 1251{
c3ed3877 1252 int div = 0; /* Initialized for compiler warning */
df16219f 1253 int real_div = div, clk_mul = 1;
c3ed3877 1254 u16 clk = 0;
5497159c 1255 bool switch_base_clk = false;
d129bceb 1256
85105c53 1257 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1258 if (host->preset_enabled) {
52983382
KL		 1259 u16 pre_val;
1260
1261 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1262 pre_val = sdhci_get_preset_value(host);
1263 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1264 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1265 if (host->clk_mul &&
1266 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1267 clk = SDHCI_PROG_CLOCK_MODE;
1268 real_div = div + 1;
1269 clk_mul = host->clk_mul;
1270 } else {
1271 real_div = max_t(int, 1, div << 1);
1272 }
1273 goto clock_set;
1274 }
1275
c3ed3877
AN		 1276 /*
1277 * Check if the Host Controller supports Programmable Clock
1278 * Mode.
1279 */
1280 if (host->clk_mul) {
52983382
KL		 1281 for (div = 1; div <= 1024; div++) {
1282 if ((host->max_clk * host->clk_mul / div)
1283 <= clock)
1284 break;
1285 }
5497159c 1286 if ((host->max_clk * host->clk_mul / div) <= clock) {
1287 /*
1288 * Set Programmable Clock Mode in the Clock
1289 * Control register.
1290 */
1291 clk = SDHCI_PROG_CLOCK_MODE;
1292 real_div = div;
1293 clk_mul = host->clk_mul;
1294 div--;
1295 } else {
1296 /*
1297 * Divisor can be too small to reach clock
1298 * speed requirement. Then use the base clock.
1299 */
1300 switch_base_clk = true;
1301 }
1302 }
1303
1304 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1305 /* Version 3.00 divisors must be a multiple of 2. */
1306 if (host->max_clk <= clock)
1307 div = 1;
1308 else {
1309 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1310 div += 2) {
1311 if ((host->max_clk / div) <= clock)
1312 break;
1313 }
85105c53 1314 }
df16219f 1315 real_div = div;
c3ed3877 1316 div >>= 1;
d1955c3a
SG		 1317 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1318 && !div && host->max_clk <= 25000000)
1319 div = 1;
85105c53
ZG		 1320 }
1321 } else {
1322 /* Version 2.00 divisors must be a power of 2. */
0397526d 1323 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1324 if ((host->max_clk / div) <= clock)
1325 break;
1326 }
df16219f 1327 real_div = div;
c3ed3877 1328 div >>= 1;
d129bceb 1329 }
d129bceb 1330
52983382 1331clock_set:
03d6f5ff 1332 if (real_div)
fb9ee047 1333 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1334 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1335 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1336 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 1337
1338 return clk;
1339}
1340EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1341
1342void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1343{
1344 u16 clk;
1345 unsigned long timeout;
1346
1347 host->mmc->actual_clock = 0;
1348
1349 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
fb9ee047
LD		 1350
1351 if (clock == 0)
1352 return;
1353
1354 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1355
d129bceb 1356 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1357 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1358
27f6cb16
CB		 1359 /* Wait max 20 ms */
1360 timeout = 20;
4e4141a5 1361 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1362 & SDHCI_CLOCK_INT_STABLE)) {
1363 if (timeout == 0) {
2e4456f0
MV		 1364 pr_err("%s: Internal clock never stabilised.\n",
1365 mmc_hostname(host->mmc));
d129bceb
PO		 1366 sdhci_dumpregs(host);
1367 return;
1368 }
7cb2c76f
PO		 1369 timeout--;
1370 mdelay(1);
1371 }
d129bceb
PO		 1372
1373 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1374 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1375}
1771059c 1376EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1377
1dceb041
AH		 1378static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1379 unsigned short vdd)
146ad66e 1380{
3a48edc4 1381 struct mmc_host *mmc = host->mmc;
1dceb041
AH		 1382
1383 spin_unlock_irq(&host->lock);
1384 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1385 spin_lock_irq(&host->lock);
1386
1387 if (mode != MMC_POWER_OFF)
1388 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1389 else
1390 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1391}
1392
1393void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1394 unsigned short vdd)
1395{
8364248a 1396 u8 pwr = 0;
146ad66e 1397
24fbb3ca
RK		 1398 if (mode != MMC_POWER_OFF) {
1399 switch (1 << vdd) {
ae628903
PO		 1400 case MMC_VDD_165_195:
1401 pwr = SDHCI_POWER_180;
1402 break;
1403 case MMC_VDD_29_30:
1404 case MMC_VDD_30_31:
1405 pwr = SDHCI_POWER_300;
1406 break;
1407 case MMC_VDD_32_33:
1408 case MMC_VDD_33_34:
1409 pwr = SDHCI_POWER_330;
1410 break;
1411 default:
9d5de93f
AH		 1412 WARN(1, "%s: Invalid vdd %#x\n",
1413 mmc_hostname(host->mmc), vdd);
1414 break;
ae628903
PO		 1415 }
1416 }
1417
1418 if (host->pwr == pwr)
e921a8b6 1419 return;
146ad66e 1420
ae628903
PO		 1421 host->pwr = pwr;
1422
1423 if (pwr == 0) {
4e4141a5 1424 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1425 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1426 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1427 } else {
1428 /*
1429 * Spec says that we should clear the power reg before setting
1430 * a new value. Some controllers don't seem to like this though.
1431 */
1432 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1433 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1434
e921a8b6
RK		 1435 /*
1436 * At least the Marvell CaFe chip gets confused if we set the
1437 * voltage and set turn on power at the same time, so set the
1438 * voltage first.
1439 */
1440 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1441 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1442
e921a8b6 1443 pwr |= SDHCI_POWER_ON;
146ad66e 1444
e921a8b6 1445 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1446
e921a8b6
RK		 1447 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1448 sdhci_runtime_pm_bus_on(host);
f0710a55 1449
e921a8b6
RK		 1450 /*
1451 * Some controllers need an extra 10ms delay of 10ms before
1452 * they can apply clock after applying power
1453 */
1454 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1455 mdelay(10);
1456 }
1dceb041
AH		 1457}
1458EXPORT_SYMBOL_GPL(sdhci_set_power);
918f4cbd 1459
1dceb041
AH		 1460static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1461 unsigned short vdd)
1462{
1463 struct mmc_host *mmc = host->mmc;
1464
1465 if (host->ops->set_power)
1466 host->ops->set_power(host, mode, vdd);
1467 else if (!IS_ERR(mmc->supply.vmmc))
1468 sdhci_set_power_reg(host, mode, vdd);
1469 else
1470 sdhci_set_power(host, mode, vdd);
146ad66e
PO		 1471}
1472
d129bceb
PO		 1473/*****************************************************************************\
1474 * *
1475 * MMC callbacks *
1476 * *
1477\*****************************************************************************/
1478
1479static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1480{
1481 struct sdhci_host *host;
505a8680 1482 int present;
d129bceb
PO		 1483 unsigned long flags;
1484
1485 host = mmc_priv(mmc);
1486
04e079cf 1487 /* Firstly check card presence */
8d28b7a7 1488 present = mmc->ops->get_cd(mmc);
2836766a 1489
d129bceb
PO		 1490 spin_lock_irqsave(&host->lock, flags);
1491
061d17a6 1492 sdhci_led_activate(host);
e89d456f
AW		 1493
1494 /*
1495 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1496 * requests if Auto-CMD12 is enabled.
1497 */
0293d501 1498 if (sdhci_auto_cmd12(host, mrq)) {
c4512f79
JH		 1499 if (mrq->stop) {
1500 mrq->data->stop = NULL;
1501 mrq->stop = NULL;
1502 }
1503 }
d129bceb 1504
68d1fb7e 1505 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
a4c73aba 1506 mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 1507 sdhci_finish_mrq(host, mrq);
cf2b5eea 1508 } else {
8edf6371 1509 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1510 sdhci_send_command(host, mrq->sbc);
1511 else
1512 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1513 }
d129bceb 1514
5f25a66f 1515 mmiowb();
d129bceb
PO		 1516 spin_unlock_irqrestore(&host->lock, flags);
1517}
1518
2317f56c
RK		 1519void sdhci_set_bus_width(struct sdhci_host *host, int width)
1520{
1521 u8 ctrl;
1522
1523 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1524 if (width == MMC_BUS_WIDTH_8) {
1525 ctrl &= ~SDHCI_CTRL_4BITBUS;
1526 if (host->version >= SDHCI_SPEC_300)
1527 ctrl |= SDHCI_CTRL_8BITBUS;
1528 } else {
1529 if (host->version >= SDHCI_SPEC_300)
1530 ctrl &= ~SDHCI_CTRL_8BITBUS;
1531 if (width == MMC_BUS_WIDTH_4)
1532 ctrl |= SDHCI_CTRL_4BITBUS;
1533 else
1534 ctrl &= ~SDHCI_CTRL_4BITBUS;
1535 }
1536 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1537}
1538EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1539
96d7b78c
RK		 1540void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1541{
1542 u16 ctrl_2;
1543
1544 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1545 /* Select Bus Speed Mode for host */
1546 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1547 if ((timing == MMC_TIMING_MMC_HS200) ||
1548 (timing == MMC_TIMING_UHS_SDR104))
1549 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1550 else if (timing == MMC_TIMING_UHS_SDR12)
1551 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1552 else if (timing == MMC_TIMING_UHS_SDR25)
1553 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1554 else if (timing == MMC_TIMING_UHS_SDR50)
1555 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1556 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1557 (timing == MMC_TIMING_MMC_DDR52))
1558 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1559 else if (timing == MMC_TIMING_MMC_HS400)
1560 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1561 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1562}
1563EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1564
ded97e0b 1565static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 1566{
ded97e0b 1567 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 1568 unsigned long flags;
1569 u8 ctrl;
1570
d129bceb
PO		 1571 spin_lock_irqsave(&host->lock, flags);
1572
ceb6143b
AH		 1573 if (host->flags & SDHCI_DEVICE_DEAD) {
1574 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1575 if (!IS_ERR(mmc->supply.vmmc) &&
1576 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1577 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1578 return;
1579 }
1e72859e 1580
d129bceb
PO		 1581 /*
1582 * Reset the chip on each power off.
1583 * Should clear out any weird states.
1584 */
1585 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1586 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1587 sdhci_reinit(host);
d129bceb
PO		 1588 }
1589
52983382 1590 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1591 (ios->power_mode == MMC_POWER_UP) &&
1592 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1593 sdhci_enable_preset_value(host, false);
1594
373073ef 1595 if (!ios->clock || ios->clock != host->clock) {
1771059c 1596 host->ops->set_clock(host, ios->clock);
373073ef 1597 host->clock = ios->clock;
03d6f5ff
AD		 1598
1599 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1600 host->clock) {
1601 host->timeout_clk = host->mmc->actual_clock ?
1602 host->mmc->actual_clock / 1000 :
1603 host->clock / 1000;
1604 host->mmc->max_busy_timeout =
1605 host->ops->get_max_timeout_count ?
1606 host->ops->get_max_timeout_count(host) :
1607 1 << 27;
1608 host->mmc->max_busy_timeout /= host->timeout_clk;
1609 }
373073ef 1610 }
d129bceb 1611
1dceb041 1612 __sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1613
643a81ff
PR		 1614 if (host->ops->platform_send_init_74_clocks)
1615 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1616
2317f56c 1617 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1618
15ec4461 1619 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1620
3ab9c8da
PR		 1621 if ((ios->timing == MMC_TIMING_SD_HS ||
1622 ios->timing == MMC_TIMING_MMC_HS)
1623 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1624 ctrl |= SDHCI_CTRL_HISPD;
1625 else
1626 ctrl &= ~SDHCI_CTRL_HISPD;
1627
d6d50a15 1628 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1629 u16 clk, ctrl_2;
49c468fc
AN		 1630
1631 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1632 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1633 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1634 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1635 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1636 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1637 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1638 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1639 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1640
da91a8f9 1641 if (!host->preset_enabled) {
758535c4 1642 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1643 /*
1644 * We only need to set Driver Strength if the
1645 * preset value enable is not set.
1646 */
da91a8f9 1647 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1648 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1649 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1650 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1651 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1652 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1653 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1654 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1655 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1656 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1657 else {
2e4456f0
MV		 1658 pr_warn("%s: invalid driver type, default to driver type B\n",
1659 mmc_hostname(mmc));
43e943a0
PG		 1660 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1661 }
d6d50a15
AN		 1662
1663 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1664 } else {
1665 /*
1666 * According to SDHC Spec v3.00, if the Preset Value
1667 * Enable in the Host Control 2 register is set, we
1668 * need to reset SD Clock Enable before changing High
1669 * Speed Enable to avoid generating clock gliches.
1670 */
758535c4
AN		 1671
1672 /* Reset SD Clock Enable */
1673 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1674 clk &= ~SDHCI_CLOCK_CARD_EN;
1675 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1676
1677 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1678
1679 /* Re-enable SD Clock */
1771059c 1680 host->ops->set_clock(host, host->clock);
d6d50a15 1681 }
49c468fc 1682
49c468fc
AN		 1683 /* Reset SD Clock Enable */
1684 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1685 clk &= ~SDHCI_CLOCK_CARD_EN;
1686 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1687
96d7b78c 1688 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1689 host->timing = ios->timing;
49c468fc 1690
52983382
KL		 1691 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1692 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1693 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1694 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1695 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1696 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1697 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1698 u16 preset;
1699
1700 sdhci_enable_preset_value(host, true);
1701 preset = sdhci_get_preset_value(host);
1702 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1703 >> SDHCI_PRESET_DRV_SHIFT;
1704 }
1705
49c468fc 1706 /* Re-enable SD Clock */
1771059c 1707 host->ops->set_clock(host, host->clock);
758535c4
AN		 1708 } else
1709 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1710
b8352260
LD		 1711 /*
1712 * Some (ENE) controllers go apeshit on some ios operation,
1713 * signalling timeout and CRC errors even on CMD0. Resetting
1714 * it on each ios seems to solve the problem.
1715 */
c63705e1 1716 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1717 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1718
5f25a66f 1719 mmiowb();
d129bceb
PO		 1720 spin_unlock_irqrestore(&host->lock, flags);
1721}
1722
ded97e0b 1723static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 1724{
1725 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 1726 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 1727
1728 if (host->flags & SDHCI_DEVICE_DEAD)
1729 return 0;
1730
88af5655 1731 /* If nonremovable, assume that the card is always present. */
860951c5 1732 if (!mmc_card_is_removable(host->mmc))
94144a46
KL		 1733 return 1;
1734
88af5655
II		 1735 /*
1736 * Try slot gpio detect, if defined it take precedence
1737 * over build in controller functionality
1738 */
287980e4 1739 if (gpio_cd >= 0)
94144a46
KL		 1740 return !!gpio_cd;
1741
88af5655
II		 1742 /* If polling, assume that the card is always present. */
1743 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1744 return 1;
1745
94144a46
KL		 1746 /* Host native card detect */
1747 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1748}
1749
66fd8ad5 1750static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1751{
d129bceb 1752 unsigned long flags;
2dfb579c 1753 int is_readonly;
d129bceb 1754
d129bceb
PO		 1755 spin_lock_irqsave(&host->lock, flags);
1756
1e72859e 1757 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1758 is_readonly = 0;
1759 else if (host->ops->get_ro)
1760 is_readonly = host->ops->get_ro(host);
1e72859e 1761 else
2dfb579c
WS		 1762 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1763 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1764
1765 spin_unlock_irqrestore(&host->lock, flags);
1766
2dfb579c
WS		 1767 /* This quirk needs to be replaced by a callback-function later */
1768 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1769 !is_readonly : is_readonly;
d129bceb
PO		 1770}
1771
82b0e23a
TI		 1772#define SAMPLE_COUNT 5
1773
ded97e0b 1774static int sdhci_get_ro(struct mmc_host *mmc)
82b0e23a 1775{
ded97e0b 1776 struct sdhci_host *host = mmc_priv(mmc);
82b0e23a
TI		 1777 int i, ro_count;
1778
82b0e23a 1779 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1780 return sdhci_check_ro(host);
82b0e23a
TI		 1781
1782 ro_count = 0;
1783 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1784 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1785 if (++ro_count > SAMPLE_COUNT / 2)
1786 return 1;
1787 }
1788 msleep(30);
1789 }
1790 return 0;
1791}
1792
20758b66
AH		 1793static void sdhci_hw_reset(struct mmc_host *mmc)
1794{
1795 struct sdhci_host *host = mmc_priv(mmc);
1796
1797 if (host->ops && host->ops->hw_reset)
1798 host->ops->hw_reset(host);
1799}
1800
66fd8ad5
AH		 1801static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1802{
be138554 1803 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1804 if (enable)
b537f94c 1805 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1806 else
b537f94c
RK		 1807 host->ier &= ~SDHCI_INT_CARD_INT;
1808
1809 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1810 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1811 mmiowb();
1812 }
66fd8ad5
AH		 1813}
1814
1815static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1816{
1817 struct sdhci_host *host = mmc_priv(mmc);
1818 unsigned long flags;
f75979b7 1819
66fd8ad5 1820 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1821 if (enable)
1822 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1823 else
1824 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1825
66fd8ad5 1826 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1827 spin_unlock_irqrestore(&host->lock, flags);
1828}
1829
ded97e0b
DA		 1830static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1831 struct mmc_ios *ios)
f2119df6 1832{
ded97e0b 1833 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 1834 u16 ctrl;
6231f3de 1835 int ret;
f2119df6 1836
20b92a30
KL		 1837 /*
1838 * Signal Voltage Switching is only applicable for Host Controllers
1839 * v3.00 and above.
1840 */
1841 if (host->version < SDHCI_SPEC_300)
1842 return 0;
6231f3de 1843
f2119df6 1844 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1845
21f5998f 1846 switch (ios->signal_voltage) {
20b92a30 1847 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 1848 if (!(host->flags & SDHCI_SIGNALING_330))
1849 return -EINVAL;
20b92a30
KL		 1850 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1851 ctrl &= ~SDHCI_CTRL_VDD_180;
1852 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1853
3a48edc4 1854 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1855 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1856 if (ret) {
6606110d
JP		 1857 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1858 mmc_hostname(mmc));
20b92a30
KL		 1859 return -EIO;
1860 }
1861 }
1862 /* Wait for 5ms */
1863 usleep_range(5000, 5500);
f2119df6 1864
20b92a30
KL		 1865 /* 3.3V regulator output should be stable within 5 ms */
1866 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1867 if (!(ctrl & SDHCI_CTRL_VDD_180))
1868 return 0;
6231f3de 1869
6606110d
JP		 1870 pr_warn("%s: 3.3V regulator output did not became stable\n",
1871 mmc_hostname(mmc));
20b92a30
KL		 1872
1873 return -EAGAIN;
1874 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 1875 if (!(host->flags & SDHCI_SIGNALING_180))
1876 return -EINVAL;
3a48edc4 1877 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1878 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1879 if (ret) {
6606110d
JP		 1880 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1881 mmc_hostname(mmc));
20b92a30
KL		 1882 return -EIO;
1883 }
1884 }
6231f3de 1885
6231f3de
PR		 1886 /*
1887 * Enable 1.8V Signal Enable in the Host Control2
1888 * register
1889 */
20b92a30
KL		 1890 ctrl |= SDHCI_CTRL_VDD_180;
1891 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1892
9d967a61
VY		 1893 /* Some controller need to do more when switching */
1894 if (host->ops->voltage_switch)
1895 host->ops->voltage_switch(host);
1896
20b92a30
KL		 1897 /* 1.8V regulator output should be stable within 5 ms */
1898 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1899 if (ctrl & SDHCI_CTRL_VDD_180)
1900 return 0;
f2119df6 1901
6606110d
JP		 1902 pr_warn("%s: 1.8V regulator output did not became stable\n",
1903 mmc_hostname(mmc));
f2119df6 1904
20b92a30
KL		 1905 return -EAGAIN;
1906 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 1907 if (!(host->flags & SDHCI_SIGNALING_120))
1908 return -EINVAL;
3a48edc4 1909 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1910 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1911 if (ret) {
6606110d
JP		 1912 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1913 mmc_hostname(mmc));
20b92a30 1914 return -EIO;
f2119df6
AN		 1915 }
1916 }
6231f3de 1917 return 0;
20b92a30 1918 default:
f2119df6
AN		 1919 /* No signal voltage switch required */
1920 return 0;
20b92a30 1921 }
f2119df6
AN		 1922}
1923
20b92a30
KL		 1924static int sdhci_card_busy(struct mmc_host *mmc)
1925{
1926 struct sdhci_host *host = mmc_priv(mmc);
1927 u32 present_state;
1928
e613cc47 1929 /* Check whether DAT[0] is 0 */
20b92a30 1930 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 1931
e613cc47 1932 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 1933}
1934
b5540ce1
AH		 1935static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1936{
1937 struct sdhci_host *host = mmc_priv(mmc);
1938 unsigned long flags;
1939
1940 spin_lock_irqsave(&host->lock, flags);
1941 host->flags |= SDHCI_HS400_TUNING;
1942 spin_unlock_irqrestore(&host->lock, flags);
1943
1944 return 0;
1945}
1946
069c9f14 1947static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1948{
4b6f37d3 1949 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1950 u16 ctrl;
b513ea25 1951 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1952 int err = 0;
2b35bd83 1953 unsigned long flags;
38e40bf5 1954 unsigned int tuning_count = 0;
b5540ce1 1955 bool hs400_tuning;
b513ea25 1956
2b35bd83 1957 spin_lock_irqsave(&host->lock, flags);
b513ea25 1958
b5540ce1
AH		 1959 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1960 host->flags &= ~SDHCI_HS400_TUNING;
1961
38e40bf5
AH		 1962 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1963 tuning_count = host->tuning_count;
1964
b513ea25 1965 /*
9faac7b9
WY		 1966 * The Host Controller needs tuning in case of SDR104 and DDR50
1967 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1968 * the Capabilities register.
069c9f14
G		 1969 * If the Host Controller supports the HS200 mode then the
1970 * tuning function has to be executed.
b513ea25 1971 */
4b6f37d3 1972 switch (host->timing) {
b5540ce1 1973 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1974 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1975 err = -EINVAL;
1976 goto out_unlock;
1977
4b6f37d3 1978 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1979 /*
1980 * Periodic re-tuning for HS400 is not expected to be needed, so
1981 * disable it here.
1982 */
1983 if (hs400_tuning)
1984 tuning_count = 0;
1985 break;
1986
4b6f37d3 1987 case MMC_TIMING_UHS_SDR104:
9faac7b9 1988 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1989 break;
1990
1991 case MMC_TIMING_UHS_SDR50:
4228b213 1992 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3
RK		 1993 break;
1994 /* FALLTHROUGH */
1995
1996 default:
d519c863 1997 goto out_unlock;
b513ea25
AN		 1998 }
1999
45251812 2000 if (host->ops->platform_execute_tuning) {
2b35bd83 2001 spin_unlock_irqrestore(&host->lock, flags);
45251812 2002 err = host->ops->platform_execute_tuning(host, opcode);
45251812
DA		 2003 return err;
2004 }
2005
4b6f37d3
RK		 2006 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2007 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 2008 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2009 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 2010 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2011
2012 /*
2013 * As per the Host Controller spec v3.00, tuning command
2014 * generates Buffer Read Ready interrupt, so enable that.
2015 *
2016 * Note: The spec clearly says that when tuning sequence
2017 * is being performed, the controller does not generate
2018 * interrupts other than Buffer Read Ready interrupt. But
2019 * to make sure we don't hit a controller bug, we _only_
2020 * enable Buffer Read Ready interrupt here.
2021 */
b537f94c
RK		 2022 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2023 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 2024
2025 /*
2026 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1473bdd5 2027 * of loops reaches 40 times.
b513ea25 2028 */
b513ea25
AN		 2029 do {
2030 struct mmc_command cmd = {0};
66fd8ad5 2031 struct mmc_request mrq = {NULL};
b513ea25 2032
069c9f14 2033 cmd.opcode = opcode;
b513ea25
AN		 2034 cmd.arg = 0;
2035 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2036 cmd.retries = 0;
2037 cmd.data = NULL;
4e9f8fe5 2038 cmd.mrq = &mrq;
b513ea25
AN		 2039 cmd.error = 0;
2040
7ce45e95
AC		 2041 if (tuning_loop_counter-- == 0)
2042 break;
2043
b513ea25 2044 mrq.cmd = &cmd;
b513ea25
AN		 2045
2046 /*
2047 * In response to CMD19, the card sends 64 bytes of tuning
2048 * block to the Host Controller. So we set the block size
2049 * to 64 here.
2050 */
069c9f14
G		 2051 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2052 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2053 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2054 SDHCI_BLOCK_SIZE);
2055 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2056 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2057 SDHCI_BLOCK_SIZE);
2058 } else {
2059 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2060 SDHCI_BLOCK_SIZE);
2061 }
b513ea25
AN		 2062
2063 /*
2064 * The tuning block is sent by the card to the host controller.
2065 * So we set the TRNS_READ bit in the Transfer Mode register.
2066 * This also takes care of setting DMA Enable and Multi Block
2067 * Select in the same register to 0.
2068 */
2069 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2070
2071 sdhci_send_command(host, &cmd);
2072
2073 host->cmd = NULL;
07c161bc 2074 sdhci_del_timer(host, &mrq);
b513ea25 2075
2b35bd83 2076 spin_unlock_irqrestore(&host->lock, flags);
b513ea25 2077 /* Wait for Buffer Read Ready interrupt */
0c293c4e 2078 wait_event_timeout(host->buf_ready_int,
b513ea25
AN		 2079 (host->tuning_done == 1),
2080 msecs_to_jiffies(50));
2b35bd83 2081 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 2082
2083 if (!host->tuning_done) {
2e4456f0 2084 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 2085 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2086 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2087 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2088 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2089
2090 err = -EIO;
2091 goto out;
2092 }
2093
2094 host->tuning_done = 0;
2095
2096 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2097
2098 /* eMMC spec does not require a delay between tuning cycles */
2099 if (opcode == MMC_SEND_TUNING_BLOCK)
2100 mdelay(1);
b513ea25
AN		 2101 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2102
2103 /*
2104 * The Host Driver has exhausted the maximum number of loops allowed,
2105 * so use fixed sampling frequency.
2106 */
7ce45e95 2107 if (tuning_loop_counter < 0) {
b513ea25
AN		 2108 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2109 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2110 }
2111 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2112 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2113 err = -EIO;
b513ea25
AN		 2114 }
2115
2116out:
38e40bf5 2117 if (tuning_count) {
66c39dfc
AH		 2118 /*
2119 * In case tuning fails, host controllers which support
2120 * re-tuning can try tuning again at a later time, when the
2121 * re-tuning timer expires. So for these controllers, we
2122 * return 0. Since there might be other controllers who do not
2123 * have this capability, we return error for them.
2124 */
2125 err = 0;
cf2b5eea
AN		 2126 }
2127
66c39dfc 2128 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2129
b537f94c
RK		 2130 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2131 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2132out_unlock:
2b35bd83 2133 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2134 return err;
2135}
2136
cb849648
AH		 2137static int sdhci_select_drive_strength(struct mmc_card *card,
2138 unsigned int max_dtr, int host_drv,
2139 int card_drv, int *drv_type)
2140{
2141 struct sdhci_host *host = mmc_priv(card->host);
2142
2143 if (!host->ops->select_drive_strength)
2144 return 0;
2145
2146 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2147 card_drv, drv_type);
2148}
52983382
KL		 2149
2150static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2151{
4d55c5a1
AN		 2152 /* Host Controller v3.00 defines preset value registers */
2153 if (host->version < SDHCI_SPEC_300)
2154 return;
2155
4d55c5a1
AN		 2156 /*
2157 * We only enable or disable Preset Value if they are not already
2158 * enabled or disabled respectively. Otherwise, we bail out.
2159 */
da91a8f9
RK		 2160 if (host->preset_enabled != enable) {
2161 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2162
2163 if (enable)
2164 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2165 else
2166 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2167
4d55c5a1 2168 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2169
2170 if (enable)
2171 host->flags |= SDHCI_PV_ENABLED;
2172 else
2173 host->flags &= ~SDHCI_PV_ENABLED;
2174
2175 host->preset_enabled = enable;
4d55c5a1 2176 }
66fd8ad5
AH		 2177}
2178
348487cb
HC		 2179static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2180 int err)
2181{
2182 struct sdhci_host *host = mmc_priv(mmc);
2183 struct mmc_data *data = mrq->data;
2184
f48f039c 2185 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2186 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2187 data->flags & MMC_DATA_WRITE ?
2188 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2189
2190 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2191}
2192
348487cb
HC		 2193static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2194 bool is_first_req)
2195{
2196 struct sdhci_host *host = mmc_priv(mmc);
2197
d31911b9 2198 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2199
2200 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2201 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2202}
2203
5d0d11c5
AH		 2204static inline bool sdhci_has_requests(struct sdhci_host *host)
2205{
2206 return host->cmd || host->data_cmd;
2207}
2208
2209static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2210{
2211 if (host->data_cmd) {
2212 host->data_cmd->error = err;
2213 sdhci_finish_mrq(host, host->data_cmd->mrq);
2214 }
2215
2216 if (host->cmd) {
2217 host->cmd->error = err;
2218 sdhci_finish_mrq(host, host->cmd->mrq);
2219 }
2220}
2221
71e69211 2222static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2223{
71e69211 2224 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2225 unsigned long flags;
2836766a 2226 int present;
d129bceb 2227
722e1280
CD		 2228 /* First check if client has provided their own card event */
2229 if (host->ops->card_event)
2230 host->ops->card_event(host);
2231
d3940f27 2232 present = mmc->ops->get_cd(mmc);
2836766a 2233
d129bceb
PO		 2234 spin_lock_irqsave(&host->lock, flags);
2235
5d0d11c5
AH		 2236 /* Check sdhci_has_requests() first in case we are runtime suspended */
2237 if (sdhci_has_requests(host) && !present) {
a3c76eb9 2238 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2239 mmc_hostname(host->mmc));
a3c76eb9 2240 pr_err("%s: Resetting controller.\n",
66fd8ad5 2241 mmc_hostname(host->mmc));
d129bceb 2242
03231f9b
RK		 2243 sdhci_do_reset(host, SDHCI_RESET_CMD);
2244 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2245
5d0d11c5 2246 sdhci_error_out_mrqs(host, -ENOMEDIUM);
d129bceb
PO		 2247 }
2248
2249 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2250}
2251
2252static const struct mmc_host_ops sdhci_ops = {
2253 .request = sdhci_request,
348487cb
HC		 2254 .post_req = sdhci_post_req,
2255 .pre_req = sdhci_pre_req,
71e69211 2256 .set_ios = sdhci_set_ios,
94144a46 2257 .get_cd = sdhci_get_cd,
71e69211
GL		 2258 .get_ro = sdhci_get_ro,
2259 .hw_reset = sdhci_hw_reset,
2260 .enable_sdio_irq = sdhci_enable_sdio_irq,
2261 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2262 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2263 .execute_tuning = sdhci_execute_tuning,
cb849648 2264 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2265 .card_event = sdhci_card_event,
20b92a30 2266 .card_busy = sdhci_card_busy,
71e69211
GL		 2267};
2268
2269/*****************************************************************************\
2270 * *
2271 * Tasklets *
2272 * *
2273\*****************************************************************************/
2274
4e9f8fe5 2275static bool sdhci_request_done(struct sdhci_host *host)
d129bceb 2276{
d129bceb
PO		 2277 unsigned long flags;
2278 struct mmc_request *mrq;
4e9f8fe5 2279 int i;
d129bceb 2280
66fd8ad5
AH		 2281 spin_lock_irqsave(&host->lock, flags);
2282
4e9f8fe5
AH		 2283 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2284 mrq = host->mrqs_done[i];
2285 if (mrq) {
2286 host->mrqs_done[i] = NULL;
2287 break;
2288 }
66fd8ad5 2289 }
d129bceb 2290
4e9f8fe5
AH		 2291 if (!mrq) {
2292 spin_unlock_irqrestore(&host->lock, flags);
2293 return true;
2294 }
d129bceb 2295
d7422fb4
AH		 2296 sdhci_del_timer(host, mrq);
2297
054cedff
RK		 2298 /*
2299 * Always unmap the data buffers if they were mapped by
2300 * sdhci_prepare_data() whenever we finish with a request.
2301 * This avoids leaking DMA mappings on error.
2302 */
2303 if (host->flags & SDHCI_REQ_USE_DMA) {
2304 struct mmc_data *data = mrq->data;
2305
2306 if (data && data->host_cookie == COOKIE_MAPPED) {
2307 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2308 (data->flags & MMC_DATA_READ) ?
2309 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2310 data->host_cookie = COOKIE_UNMAPPED;
2311 }
2312 }
2313
d129bceb
PO		 2314 /*
2315 * The controller needs a reset of internal state machines
2316 * upon error conditions.
2317 */
0cc563ce 2318 if (sdhci_needs_reset(host, mrq)) {
645289dc 2319 /* Some controllers need this kick or reset won't work here */
8213af3b 2320 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2321 /* This is to force an update */
1771059c 2322 host->ops->set_clock(host, host->clock);
645289dc
PO		 2323
2324 /* Spec says we should do both at the same time, but Ricoh
2325 controllers do not like that. */
33a57adb
AH		 2326 if (!host->cmd)
2327 sdhci_do_reset(host, SDHCI_RESET_CMD);
2328 if (!host->data_cmd)
2329 sdhci_do_reset(host, SDHCI_RESET_DATA);
ed1563de
AH		 2330
2331 host->pending_reset = false;
d129bceb
PO		 2332 }
2333
4e9f8fe5
AH		 2334 if (!sdhci_has_requests(host))
2335 sdhci_led_deactivate(host);
d129bceb 2336
5f25a66f 2337 mmiowb();
d129bceb
PO		 2338 spin_unlock_irqrestore(&host->lock, flags);
2339
2340 mmc_request_done(host->mmc, mrq);
4e9f8fe5
AH		 2341
2342 return false;
2343}
2344
2345static void sdhci_tasklet_finish(unsigned long param)
2346{
2347 struct sdhci_host *host = (struct sdhci_host *)param;
2348
2349 while (!sdhci_request_done(host))
2350 ;
d129bceb
PO		 2351}
2352
2353static void sdhci_timeout_timer(unsigned long data)
2354{
2355 struct sdhci_host *host;
2356 unsigned long flags;
2357
2358 host = (struct sdhci_host*)data;
2359
2360 spin_lock_irqsave(&host->lock, flags);
2361
d7422fb4
AH		 2362 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2363 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2364 mmc_hostname(host->mmc));
2365 sdhci_dumpregs(host);
2366
2367 host->cmd->error = -ETIMEDOUT;
2368 sdhci_finish_mrq(host, host->cmd->mrq);
2369 }
2370
2371 mmiowb();
2372 spin_unlock_irqrestore(&host->lock, flags);
2373}
2374
2375static void sdhci_timeout_data_timer(unsigned long data)
2376{
2377 struct sdhci_host *host;
2378 unsigned long flags;
2379
2380 host = (struct sdhci_host *)data;
2381
2382 spin_lock_irqsave(&host->lock, flags);
2383
2384 if (host->data || host->data_cmd ||
2385 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2e4456f0
MV		 2386 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2387 mmc_hostname(host->mmc));
d129bceb
PO		 2388 sdhci_dumpregs(host);
2389
2390 if (host->data) {
17b0429d 2391 host->data->error = -ETIMEDOUT;
d129bceb 2392 sdhci_finish_data(host);
d7422fb4
AH		 2393 } else if (host->data_cmd) {
2394 host->data_cmd->error = -ETIMEDOUT;
2395 sdhci_finish_mrq(host, host->data_cmd->mrq);
d129bceb 2396 } else {
d7422fb4
AH		 2397 host->cmd->error = -ETIMEDOUT;
2398 sdhci_finish_mrq(host, host->cmd->mrq);
d129bceb
PO		 2399 }
2400 }
2401
5f25a66f 2402 mmiowb();
d129bceb
PO		 2403 spin_unlock_irqrestore(&host->lock, flags);
2404}
2405
2406/*****************************************************************************\
2407 * *
2408 * Interrupt handling *
2409 * *
2410\*****************************************************************************/
2411
61541397 2412static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb 2413{
d129bceb 2414 if (!host->cmd) {
ed1563de
AH		 2415 /*
2416 * SDHCI recovers from errors by resetting the cmd and data
2417 * circuits. Until that is done, there very well might be more
2418 * interrupts, so ignore them in that case.
2419 */
2420 if (host->pending_reset)
2421 return;
2e4456f0
MV		 2422 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2423 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2424 sdhci_dumpregs(host);
2425 return;
2426 }
2427
ec014cba
RK		 2428 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2429 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2430 if (intmask & SDHCI_INT_TIMEOUT)
2431 host->cmd->error = -ETIMEDOUT;
2432 else
2433 host->cmd->error = -EILSEQ;
43b58b36 2434
71fcbda0
RK		 2435 /*
2436 * If this command initiates a data phase and a response
2437 * CRC error is signalled, the card can start transferring
2438 * data - the card may have received the command without
2439 * error. We must not terminate the mmc_request early.
2440 *
2441 * If the card did not receive the command or returned an
2442 * error which prevented it sending data, the data phase
2443 * will time out.
2444 */
2445 if (host->cmd->data &&
2446 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2447 SDHCI_INT_CRC) {
2448 host->cmd = NULL;
2449 return;
2450 }
2451
a6d3bdd5 2452 sdhci_finish_mrq(host, host->cmd->mrq);
e809517f
PO		 2453 return;
2454 }
2455
6bde8681
AH		 2456 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2457 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data &&
2458 host->cmd->opcode == MMC_STOP_TRANSMISSION)
61541397 2459 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2460
2461 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2462 sdhci_finish_command(host);
d129bceb
PO		 2463}
2464
0957c333 2465#ifdef CONFIG_MMC_DEBUG
08621b18 2466static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2467{
2468 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2469 void *desc = host->adma_table;
6882a8c0
BD		 2470
2471 sdhci_dumpregs(host);
2472
2473 while (true) {
e57a5f61
AH		 2474 struct sdhci_adma2_64_desc *dma_desc = desc;
2475
2476 if (host->flags & SDHCI_USE_64_BIT_DMA)
2477 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2478 name, desc, le32_to_cpu(dma_desc->addr_hi),
2479 le32_to_cpu(dma_desc->addr_lo),
2480 le16_to_cpu(dma_desc->len),
2481 le16_to_cpu(dma_desc->cmd));
2482 else
2483 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2484 name, desc, le32_to_cpu(dma_desc->addr_lo),
2485 le16_to_cpu(dma_desc->len),
2486 le16_to_cpu(dma_desc->cmd));
6882a8c0 2487
76fe379a 2488 desc += host->desc_sz;
6882a8c0 2489
0545230f 2490 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2491 break;
2492 }
2493}
2494#else
08621b18 2495static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2496#endif
2497
d129bceb
PO		 2498static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2499{
069c9f14 2500 u32 command;
d129bceb 2501
b513ea25
AN		 2502 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2503 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2504 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2505 if (command == MMC_SEND_TUNING_BLOCK ||
2506 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2507 host->tuning_done = 1;
2508 wake_up(&host->buf_ready_int);
2509 return;
2510 }
2511 }
2512
d129bceb 2513 if (!host->data) {
7c89a3d9
AH		 2514 struct mmc_command *data_cmd = host->data_cmd;
2515
2516 if (data_cmd)
2517 host->data_cmd = NULL;
2518
d129bceb 2519 /*
e809517f
PO		 2520 * The "data complete" interrupt is also used to
2521 * indicate that a busy state has ended. See comment
2522 * above in sdhci_cmd_irq().
d129bceb 2523 */
7c89a3d9 2524 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8 2525 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
7c89a3d9 2526 data_cmd->error = -ETIMEDOUT;
a6d3bdd5 2527 sdhci_finish_mrq(host, data_cmd->mrq);
c5abd5e8
MC		 2528 return;
2529 }
e809517f 2530 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2531 /*
2532 * Some cards handle busy-end interrupt
2533 * before the command completed, so make
2534 * sure we do things in the proper order.
2535 */
ea968023
AH		 2536 if (host->cmd == data_cmd)
2537 return;
2538
a6d3bdd5 2539 sdhci_finish_mrq(host, data_cmd->mrq);
e809517f
PO		 2540 return;
2541 }
2542 }
d129bceb 2543
ed1563de
AH		 2544 /*
2545 * SDHCI recovers from errors by resetting the cmd and data
2546 * circuits. Until that is done, there very well might be more
2547 * interrupts, so ignore them in that case.
2548 */
2549 if (host->pending_reset)
2550 return;
2551
2e4456f0
MV		 2552 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2553 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2554 sdhci_dumpregs(host);
2555
2556 return;
2557 }
2558
2559 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2560 host->data->error = -ETIMEDOUT;
22113efd
AL		 2561 else if (intmask & SDHCI_INT_DATA_END_BIT)
2562 host->data->error = -EILSEQ;
2563 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2564 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2565 != MMC_BUS_TEST_R)
17b0429d 2566 host->data->error = -EILSEQ;
6882a8c0 2567 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2568 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2569 sdhci_adma_show_error(host);
2134a922 2570 host->data->error = -EIO;
a4071fbb
HZ		 2571 if (host->ops->adma_workaround)
2572 host->ops->adma_workaround(host, intmask);
6882a8c0 2573 }
d129bceb 2574
17b0429d 2575 if (host->data->error)
d129bceb
PO		 2576 sdhci_finish_data(host);
2577 else {
a406f5a3 2578 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2579 sdhci_transfer_pio(host);
2580
6ba736a1
PO		 2581 /*
2582 * We currently don't do anything fancy with DMA
2583 * boundaries, but as we can't disable the feature
2584 * we need to at least restart the transfer.
f6a03cbf
MV		 2585 *
2586 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2587 * should return a valid address to continue from, but as
2588 * some controllers are faulty, don't trust them.
6ba736a1 2589 */
f6a03cbf
MV		 2590 if (intmask & SDHCI_INT_DMA_END) {
2591 u32 dmastart, dmanow;
2592 dmastart = sg_dma_address(host->data->sg);
2593 dmanow = dmastart + host->data->bytes_xfered;
2594 /*
2595 * Force update to the next DMA block boundary.
2596 */
2597 dmanow = (dmanow &
2598 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2599 SDHCI_DEFAULT_BOUNDARY_SIZE;
2600 host->data->bytes_xfered = dmanow - dmastart;
2601 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2602 " next 0x%08x\n",
2603 mmc_hostname(host->mmc), dmastart,
2604 host->data->bytes_xfered, dmanow);
2605 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2606 }
6ba736a1 2607
e538fbe8 2608 if (intmask & SDHCI_INT_DATA_END) {
7c89a3d9 2609 if (host->cmd == host->data_cmd) {
e538fbe8
PO		 2610 /*
2611 * Data managed to finish before the
2612 * command completed. Make sure we do
2613 * things in the proper order.
2614 */
2615 host->data_early = 1;
2616 } else {
2617 sdhci_finish_data(host);
2618 }
2619 }
d129bceb
PO		 2620 }
2621}
2622
7d12e780 2623static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2624{
781e989c 2625 irqreturn_t result = IRQ_NONE;
66fd8ad5 2626 struct sdhci_host *host = dev_id;
41005003 2627 u32 intmask, mask, unexpected = 0;
781e989c 2628 int max_loops = 16;
d129bceb
PO		 2629
2630 spin_lock(&host->lock);
2631
be138554 2632 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2633 spin_unlock(&host->lock);
655bca76 2634 return IRQ_NONE;
66fd8ad5
AH		 2635 }
2636
4e4141a5 2637 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2638 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2639 result = IRQ_NONE;
2640 goto out;
2641 }
2642
41005003
RK		 2643 do {
2644 /* Clear selected interrupts. */
2645 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2646 SDHCI_INT_BUS_POWER);
2647 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2648
41005003
RK		 2649 DBG("*** %s got interrupt: 0x%08x\n",
2650 mmc_hostname(host->mmc), intmask);
d129bceb 2651
41005003
RK		 2652 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2653 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2654 SDHCI_CARD_PRESENT;
d129bceb 2655
41005003
RK		 2656 /*
2657 * There is a observation on i.mx esdhc. INSERT
2658 * bit will be immediately set again when it gets
2659 * cleared, if a card is inserted. We have to mask
2660 * the irq to prevent interrupt storm which will
2661 * freeze the system. And the REMOVE gets the
2662 * same situation.
2663 *
2664 * More testing are needed here to ensure it works
2665 * for other platforms though.
2666 */
b537f94c
RK		 2667 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2668 SDHCI_INT_CARD_REMOVE);
2669 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2670 SDHCI_INT_CARD_INSERT;
2671 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2672 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2673
2674 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2675 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2676
2677 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2678 SDHCI_INT_CARD_REMOVE);
2679 result = IRQ_WAKE_THREAD;
41005003 2680 }
d129bceb 2681
41005003 2682 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2683 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2684 &intmask);
964f9ce2 2685
41005003
RK		 2686 if (intmask & SDHCI_INT_DATA_MASK)
2687 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2688
41005003
RK		 2689 if (intmask & SDHCI_INT_BUS_POWER)
2690 pr_err("%s: Card is consuming too much power!\n",
2691 mmc_hostname(host->mmc));
3192a28f 2692
f37b20eb
DA		 2693 if (intmask & SDHCI_INT_RETUNE)
2694 mmc_retune_needed(host->mmc);
2695
781e989c
RK		 2696 if (intmask & SDHCI_INT_CARD_INT) {
2697 sdhci_enable_sdio_irq_nolock(host, false);
2698 host->thread_isr |= SDHCI_INT_CARD_INT;
2699 result = IRQ_WAKE_THREAD;
2700 }
f75979b7 2701
41005003
RK		 2702 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2703 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2704 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
f37b20eb 2705 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
f75979b7 2706
41005003
RK		 2707 if (intmask) {
2708 unexpected |= intmask;
2709 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2710 }
d129bceb 2711
781e989c
RK		 2712 if (result == IRQ_NONE)
2713 result = IRQ_HANDLED;
d129bceb 2714
41005003 2715 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2716 } while (intmask && --max_loops);
d129bceb
PO		 2717out:
2718 spin_unlock(&host->lock);
2719
6379b237
AS		 2720 if (unexpected) {
2721 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2722 mmc_hostname(host->mmc), unexpected);
2723 sdhci_dumpregs(host);
2724 }
f75979b7 2725
d129bceb
PO		 2726 return result;
2727}
2728
781e989c
RK		 2729static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2730{
2731 struct sdhci_host *host = dev_id;
2732 unsigned long flags;
2733 u32 isr;
2734
2735 spin_lock_irqsave(&host->lock, flags);
2736 isr = host->thread_isr;
2737 host->thread_isr = 0;
2738 spin_unlock_irqrestore(&host->lock, flags);
2739
3560db8e 2740 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 2741 struct mmc_host *mmc = host->mmc;
2742
2743 mmc->ops->card_event(mmc);
2744 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 2745 }
2746
781e989c
RK		 2747 if (isr & SDHCI_INT_CARD_INT) {
2748 sdio_run_irqs(host->mmc);
2749
2750 spin_lock_irqsave(&host->lock, flags);
2751 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2752 sdhci_enable_sdio_irq_nolock(host, true);
2753 spin_unlock_irqrestore(&host->lock, flags);
2754 }
2755
2756 return isr ? IRQ_HANDLED : IRQ_NONE;
2757}
2758
d129bceb
PO		 2759/*****************************************************************************\
2760 * *
2761 * Suspend/resume *
2762 * *
2763\*****************************************************************************/
2764
2765#ifdef CONFIG_PM
84d62605
LD		 2766/*
2767 * To enable wakeup events, the corresponding events have to be enabled in
2768 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2769 * Table' in the SD Host Controller Standard Specification.
2770 * It is useless to restore SDHCI_INT_ENABLE state in
2771 * sdhci_disable_irq_wakeups() since it will be set by
2772 * sdhci_enable_card_detection() or sdhci_init().
2773 */
ad080d79
KL		 2774void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2775{
2776 u8 val;
2777 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2778 | SDHCI_WAKE_ON_INT;
84d62605
LD		 2779 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2780 SDHCI_INT_CARD_INT;
ad080d79
KL		 2781
2782 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2783 val |= mask ;
2784 /* Avoid fake wake up */
84d62605 2785 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
ad080d79 2786 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
84d62605
LD		 2787 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2788 }
ad080d79 2789 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
84d62605 2790 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
ad080d79
KL		 2791}
2792EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2793
0b10f478 2794static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2795{
2796 u8 val;
2797 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2798 | SDHCI_WAKE_ON_INT;
2799
2800 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2801 val &= ~mask;
2802 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2803}
d129bceb 2804
29495aa0 2805int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2806{
7260cf5e
AV		 2807 sdhci_disable_card_detection(host);
2808
66c39dfc 2809 mmc_retune_timer_stop(host->mmc);
f37b20eb
DA		 2810 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2811 mmc_retune_needed(host->mmc);
cf2b5eea 2812
ad080d79 2813 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2814 host->ier = 0;
2815 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2816 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2817 free_irq(host->irq, host);
2818 } else {
2819 sdhci_enable_irq_wakeups(host);
2820 enable_irq_wake(host->irq);
2821 }
4ee14ec6 2822 return 0;
d129bceb
PO		 2823}
2824
b8c86fc5 2825EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2826
b8c86fc5
PO		 2827int sdhci_resume_host(struct sdhci_host *host)
2828{
d3940f27 2829 struct mmc_host *mmc = host->mmc;
4ee14ec6 2830 int ret = 0;
d129bceb 2831
a13abc7b 2832 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2833 if (host->ops->enable_dma)
2834 host->ops->enable_dma(host);
2835 }
d129bceb 2836
6308d290
AH		 2837 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2838 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2839 /* Card keeps power but host controller does not */
2840 sdhci_init(host, 0);
2841 host->pwr = 0;
2842 host->clock = 0;
d3940f27 2843 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290
AH		 2844 } else {
2845 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2846 mmiowb();
2847 }
b8c86fc5 2848
14a7b416
HC		 2849 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2850 ret = request_threaded_irq(host->irq, sdhci_irq,
2851 sdhci_thread_irq, IRQF_SHARED,
2852 mmc_hostname(host->mmc), host);
2853 if (ret)
2854 return ret;
2855 } else {
2856 sdhci_disable_irq_wakeups(host);
2857 disable_irq_wake(host->irq);
2858 }
2859
7260cf5e
AV		 2860 sdhci_enable_card_detection(host);
2861
2f4cbb3d 2862 return ret;
d129bceb
PO		 2863}
2864
b8c86fc5 2865EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 2866
66fd8ad5
AH		 2867int sdhci_runtime_suspend_host(struct sdhci_host *host)
2868{
2869 unsigned long flags;
66fd8ad5 2870
66c39dfc 2871 mmc_retune_timer_stop(host->mmc);
f37b20eb
DA		 2872 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2873 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2874
2875 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2876 host->ier &= SDHCI_INT_CARD_INT;
2877 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2878 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2879 spin_unlock_irqrestore(&host->lock, flags);
2880
781e989c 2881 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2882
2883 spin_lock_irqsave(&host->lock, flags);
2884 host->runtime_suspended = true;
2885 spin_unlock_irqrestore(&host->lock, flags);
2886
8a125bad 2887 return 0;
66fd8ad5
AH		 2888}
2889EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2890
2891int sdhci_runtime_resume_host(struct sdhci_host *host)
2892{
d3940f27 2893 struct mmc_host *mmc = host->mmc;
66fd8ad5 2894 unsigned long flags;
8a125bad 2895 int host_flags = host->flags;
66fd8ad5
AH		 2896
2897 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2898 if (host->ops->enable_dma)
2899 host->ops->enable_dma(host);
2900 }
2901
2902 sdhci_init(host, 0);
2903
2904 /* Force clock and power re-program */
2905 host->pwr = 0;
2906 host->clock = 0;
d3940f27
AH		 2907 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2908 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 2909
52983382
KL		 2910 if ((host_flags & SDHCI_PV_ENABLED) &&
2911 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2912 spin_lock_irqsave(&host->lock, flags);
2913 sdhci_enable_preset_value(host, true);
2914 spin_unlock_irqrestore(&host->lock, flags);
2915 }
66fd8ad5 2916
66fd8ad5
AH		 2917 spin_lock_irqsave(&host->lock, flags);
2918
2919 host->runtime_suspended = false;
2920
2921 /* Enable SDIO IRQ */
ef104333 2922 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2923 sdhci_enable_sdio_irq_nolock(host, true);
2924
2925 /* Enable Card Detection */
2926 sdhci_enable_card_detection(host);
2927
2928 spin_unlock_irqrestore(&host->lock, flags);
2929
8a125bad 2930 return 0;
66fd8ad5
AH		 2931}
2932EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2933
162d6f98 2934#endif /* CONFIG_PM */
66fd8ad5 2935
d129bceb
PO		 2936/*****************************************************************************\
2937 * *
b8c86fc5 2938 * Device allocation/registration *
d129bceb
PO		 2939 * *
2940\*****************************************************************************/
2941
b8c86fc5
PO		 2942struct sdhci_host *sdhci_alloc_host(struct device *dev,
2943 size_t priv_size)
d129bceb 2944{
d129bceb
PO		 2945 struct mmc_host *mmc;
2946 struct sdhci_host *host;
2947
b8c86fc5 2948 WARN_ON(dev == NULL);
d129bceb 2949
b8c86fc5 2950 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2951 if (!mmc)
b8c86fc5 2952 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2953
2954 host = mmc_priv(mmc);
2955 host->mmc = mmc;
bf60e592
AH		 2956 host->mmc_host_ops = sdhci_ops;
2957 mmc->ops = &host->mmc_host_ops;
d129bceb 2958
8cb851a4
AH		 2959 host->flags = SDHCI_SIGNALING_330;
2960
b8c86fc5
PO		 2961 return host;
2962}
8a4da143 2963
b8c86fc5 2964EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2965
7b91369b
AC		 2966static int sdhci_set_dma_mask(struct sdhci_host *host)
2967{
2968 struct mmc_host *mmc = host->mmc;
2969 struct device *dev = mmc_dev(mmc);
2970 int ret = -EINVAL;
2971
2972 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2973 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2974
2975 /* Try 64-bit mask if hardware is capable of it */
2976 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2977 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2978 if (ret) {
2979 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2980 mmc_hostname(mmc));
2981 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2982 }
2983 }
2984
2985 /* 32-bit mask as default & fallback */
2986 if (ret) {
2987 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2988 if (ret)
2989 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2990 mmc_hostname(mmc));
2991 }
2992
2993 return ret;
2994}
2995
6132a3bf
AH		 2996void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
2997{
2998 u16 v;
2999
3000 if (host->read_caps)
3001 return;
3002
3003 host->read_caps = true;
3004
3005 if (debug_quirks)
3006 host->quirks = debug_quirks;
3007
3008 if (debug_quirks2)
3009 host->quirks2 = debug_quirks2;
3010
3011 sdhci_do_reset(host, SDHCI_RESET_ALL);
3012
3013 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3014 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3015
3016 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3017 return;
3018
3019 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
3020
3021 if (host->version < SDHCI_SPEC_300)
3022 return;
3023
3024 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
3025}
3026EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3027
52f5336d 3028int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 3029{
3030 struct mmc_host *mmc;
f2119df6
AN		 3031 u32 max_current_caps;
3032 unsigned int ocr_avail;
f5fa92e5 3033 unsigned int override_timeout_clk;
59241757 3034 u32 max_clk;
b8c86fc5 3035 int ret;
d129bceb 3036
b8c86fc5
PO		 3037 WARN_ON(host == NULL);
3038 if (host == NULL)
3039 return -EINVAL;
d129bceb 3040
b8c86fc5 3041 mmc = host->mmc;
d129bceb 3042
efba142b
JH		 3043 /*
3044 * If there are external regulators, get them. Note this must be done
3045 * early before resetting the host and reading the capabilities so that
3046 * the host can take the appropriate action if regulators are not
3047 * available.
3048 */
3049 ret = mmc_regulator_get_supply(mmc);
3050 if (ret == -EPROBE_DEFER)
3051 return ret;
3052
6132a3bf 3053 sdhci_read_caps(host);
d129bceb 3054
f5fa92e5
AH		 3055 override_timeout_clk = host->timeout_clk;
3056
85105c53 3057 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 3058 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3059 mmc_hostname(mmc), host->version);
4a965505
PO		 3060 }
3061
b8c86fc5 3062 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 3063 host->flags |= SDHCI_USE_SDMA;
28da3589 3064 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 3065 DBG("Controller doesn't have SDMA capability\n");
67435274 3066 else
a13abc7b 3067 host->flags |= SDHCI_USE_SDMA;
d129bceb 3068
b8c86fc5 3069 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 3070 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 3071 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 3072 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 3073 }
3074
f2119df6 3075 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 3076 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 3077 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 3078
3079 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3080 (host->flags & SDHCI_USE_ADMA)) {
3081 DBG("Disabling ADMA as it is marked broken\n");
3082 host->flags &= ~SDHCI_USE_ADMA;
3083 }
3084
e57a5f61
AH		 3085 /*
3086 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3087 * and *must* do 64-bit DMA. A driver has the opportunity to change
3088 * that during the first call to ->enable_dma(). Similarly
3089 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3090 * implement.
3091 */
28da3589 3092 if (host->caps & SDHCI_CAN_64BIT)
e57a5f61
AH		 3093 host->flags |= SDHCI_USE_64_BIT_DMA;
3094
a13abc7b 3095 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 3096 ret = sdhci_set_dma_mask(host);
3097
3098 if (!ret && host->ops->enable_dma)
3099 ret = host->ops->enable_dma(host);
3100
3101 if (ret) {
3102 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3103 mmc_hostname(mmc));
3104 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3105
3106 ret = 0;
d129bceb
PO		 3107 }
3108 }
3109
e57a5f61
AH		 3110 /* SDMA does not support 64-bit DMA */
3111 if (host->flags & SDHCI_USE_64_BIT_DMA)
3112 host->flags &= ~SDHCI_USE_SDMA;
3113
2134a922 3114 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 3115 dma_addr_t dma;
3116 void *buf;
3117
2134a922 3118 /*
76fe379a
AH		 3119 * The DMA descriptor table size is calculated as the maximum
3120 * number of segments times 2, to allow for an alignment
3121 * descriptor for each segment, plus 1 for a nop end descriptor,
3122 * all multipled by the descriptor size.
2134a922 3123 */
e57a5f61
AH		 3124 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3125 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3126 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 3127 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 3128 } else {
3129 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3130 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3131 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3132 }
e66e61cb 3133
04a5ae6f 3134 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 3135 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3136 host->adma_table_sz, &dma, GFP_KERNEL);
3137 if (!buf) {
6606110d 3138 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 3139 mmc_hostname(mmc));
3140 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3141 } else if ((dma + host->align_buffer_sz) &
3142 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 3143 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3144 mmc_hostname(mmc));
d1e49f77 3145 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3146 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3147 host->adma_table_sz, buf, dma);
3148 } else {
3149 host->align_buffer = buf;
3150 host->align_addr = dma;
edd63fcc 3151
e66e61cb
RK		 3152 host->adma_table = buf + host->align_buffer_sz;
3153 host->adma_addr = dma + host->align_buffer_sz;
3154 }
2134a922
PO		 3155 }
3156
7659150c
PO		 3157 /*
3158 * If we use DMA, then it's up to the caller to set the DMA
3159 * mask, but PIO does not need the hw shim so we set a new
3160 * mask here in that case.
3161 */
a13abc7b 3162 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3163 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3164 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3165 }
d129bceb 3166
c4687d5f 3167 if (host->version >= SDHCI_SPEC_300)
28da3589 3168 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3169 >> SDHCI_CLOCK_BASE_SHIFT;
3170 else
28da3589 3171 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3172 >> SDHCI_CLOCK_BASE_SHIFT;
3173
4240ff0a 3174 host->max_clk *= 1000000;
f27f47ef
AV		 3175 if (host->max_clk == 0 || host->quirks &
3176 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3177 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3178 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3179 mmc_hostname(mmc));
eb5c20de
AH		 3180 ret = -ENODEV;
3181 goto undma;
4240ff0a
BD		 3182 }
3183 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3184 }
d129bceb 3185
c3ed3877
AN		 3186 /*
3187 * In case of Host Controller v3.00, find out whether clock
3188 * multiplier is supported.
3189 */
28da3589 3190 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
c3ed3877
AN		 3191 SDHCI_CLOCK_MUL_SHIFT;
3192
3193 /*
3194 * In case the value in Clock Multiplier is 0, then programmable
3195 * clock mode is not supported, otherwise the actual clock
3196 * multiplier is one more than the value of Clock Multiplier
3197 * in the Capabilities Register.
3198 */
3199 if (host->clk_mul)
3200 host->clk_mul += 1;
3201
d129bceb
PO		 3202 /*
3203 * Set host parameters.
3204 */
59241757
DA		 3205 max_clk = host->max_clk;
3206
ce5f036b 3207 if (host->ops->get_min_clock)
a9e58f25 3208 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3209 else if (host->version >= SDHCI_SPEC_300) {
3210 if (host->clk_mul) {
3211 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3212 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3213 } else
3214 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3215 } else
0397526d 3216 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3217
d310ae49 3218 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 3219 mmc->f_max = max_clk;
3220
28aab053 3221 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
28da3589 3222 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
28aab053
AD		 3223 SDHCI_TIMEOUT_CLK_SHIFT;
3224 if (host->timeout_clk == 0) {
3225 if (host->ops->get_timeout_clock) {
3226 host->timeout_clk =
3227 host->ops->get_timeout_clock(host);
3228 } else {
3229 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3230 mmc_hostname(mmc));
eb5c20de
AH		 3231 ret = -ENODEV;
3232 goto undma;
28aab053 3233 }
272308ca 3234 }
272308ca 3235
28da3589 3236 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
28aab053 3237 host->timeout_clk *= 1000;
272308ca 3238
99513624
AH		 3239 if (override_timeout_clk)
3240 host->timeout_clk = override_timeout_clk;
3241
28aab053 3242 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3243 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3244 mmc->max_busy_timeout /= host->timeout_clk;
3245 }
58d1246d 3246
e89d456f 3247 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3248 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3249
3250 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3251 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3252
8edf6371 3253 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3254 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3255 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3256 !(host->flags & SDHCI_USE_SDMA)) &&
3257 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3258 host->flags |= SDHCI_AUTO_CMD23;
3259 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3260 } else {
3261 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3262 }
3263
15ec4461
PR		 3264 /*
3265 * A controller may support 8-bit width, but the board itself
3266 * might not have the pins brought out. Boards that support
3267 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3268 * their platform code before calling sdhci_add_host(), and we
3269 * won't assume 8-bit width for hosts without that CAP.
3270 */
5fe23c7f 3271 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3272 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3273
63ef5d8c
JH		 3274 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3275 mmc->caps &= ~MMC_CAP_CMD23;
3276
28da3589 3277 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 3278 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3279
176d1ed4 3280 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 3281 mmc_card_is_removable(mmc) &&
287980e4 3282 mmc_gpio_get_cd(host->mmc) < 0)
68d1fb7e
AV		 3283 mmc->caps |= MMC_CAP_NEEDS_POLL;
3284
6231f3de 3285 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3286 if (!IS_ERR(mmc->supply.vqmmc)) {
3287 ret = regulator_enable(mmc->supply.vqmmc);
3288 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3289 1950000))
28da3589
AH		 3290 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3291 SDHCI_SUPPORT_SDR50 |
3292 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3293 if (ret) {
3294 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3295 mmc_hostname(mmc), ret);
4bb74313 3296 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3297 }
8363c374 3298 }
6231f3de 3299
28da3589
AH		 3300 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3301 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3302 SDHCI_SUPPORT_DDR50);
3303 }
6a66180a 3304
4188bba0 3305 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 3306 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3307 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3308 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3309
3310 /* SDR104 supports also implies SDR50 support */
28da3589 3311 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 3312 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3313 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3314 * field can be promoted to support HS200.
3315 */
549c0b18 3316 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3317 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 3318 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 3319 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 3320 }
f2119df6 3321
e9fb05d5 3322 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 3323 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 3324 mmc->caps2 |= MMC_CAP2_HS400;
3325
549c0b18
AH		 3326 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3327 (IS_ERR(mmc->supply.vqmmc) ||
3328 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3329 1300000)))
3330 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3331
28da3589
AH		 3332 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3333 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3334 mmc->caps |= MMC_CAP_UHS_DDR50;
3335
069c9f14 3336 /* Does the host need tuning for SDR50? */
28da3589 3337 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 3338 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3339
d6d50a15 3340 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 3341 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 3342 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 3343 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 3344 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 3345 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 3346 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3347
cf2b5eea 3348 /* Initial value for re-tuning timer count */
28da3589
AH		 3349 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3350 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
cf2b5eea
AN		 3351
3352 /*
3353 * In case Re-tuning Timer is not disabled, the actual value of
3354 * re-tuning timer will be 2 ^ (n - 1).
3355 */
3356 if (host->tuning_count)
3357 host->tuning_count = 1 << (host->tuning_count - 1);
3358
3359 /* Re-tuning mode supported by the Host Controller */
28da3589 3360 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
cf2b5eea
AN		 3361 SDHCI_RETUNING_MODE_SHIFT;
3362
8f230f45 3363 ocr_avail = 0;
bad37e1a 3364
f2119df6
AN		 3365 /*
3366 * According to SD Host Controller spec v3.00, if the Host System
3367 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3368 * the value is meaningful only if Voltage Support in the Capabilities
3369 * register is set. The actual current value is 4 times the register
3370 * value.
3371 */
3372 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3373 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3374 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3375 if (curr > 0) {
3376
3377 /* convert to SDHCI_MAX_CURRENT format */
3378 curr = curr/1000; /* convert to mA */
3379 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3380
3381 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3382 max_current_caps =
3383 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3384 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3385 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3386 }
3387 }
f2119df6 3388
28da3589 3389 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 3390 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3391
55c4665e 3392 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3393 SDHCI_MAX_CURRENT_330_MASK) >>
3394 SDHCI_MAX_CURRENT_330_SHIFT) *
3395 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3396 }
28da3589 3397 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 3398 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3399
55c4665e 3400 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3401 SDHCI_MAX_CURRENT_300_MASK) >>
3402 SDHCI_MAX_CURRENT_300_SHIFT) *
3403 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3404 }
28da3589 3405 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3406 ocr_avail |= MMC_VDD_165_195;
3407
55c4665e 3408 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3409 SDHCI_MAX_CURRENT_180_MASK) >>
3410 SDHCI_MAX_CURRENT_180_SHIFT) *
3411 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3412 }
3413
5fd26c7e
UH		 3414 /* If OCR set by host, use it instead. */
3415 if (host->ocr_mask)
3416 ocr_avail = host->ocr_mask;
3417
3418 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3419 if (mmc->ocr_avail)
52221610 3420 ocr_avail = mmc->ocr_avail;
3a48edc4 3421
8f230f45
TI		 3422 mmc->ocr_avail = ocr_avail;
3423 mmc->ocr_avail_sdio = ocr_avail;
3424 if (host->ocr_avail_sdio)
3425 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3426 mmc->ocr_avail_sd = ocr_avail;
3427 if (host->ocr_avail_sd)
3428 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3429 else /* normal SD controllers don't support 1.8V */
3430 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3431 mmc->ocr_avail_mmc = ocr_avail;
3432 if (host->ocr_avail_mmc)
3433 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3434
3435 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3436 pr_err("%s: Hardware doesn't report any support voltages.\n",
3437 mmc_hostname(mmc));
eb5c20de
AH		 3438 ret = -ENODEV;
3439 goto unreg;
146ad66e
PO		 3440 }
3441
8cb851a4
AH		 3442 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3443 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3444 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3445 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3446 host->flags |= SDHCI_SIGNALING_180;
3447
3448 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3449 host->flags |= SDHCI_SIGNALING_120;
3450
d129bceb
PO		 3451 spin_lock_init(&host->lock);
3452
3453 /*
2134a922
PO		 3454 * Maximum number of segments. Depends on if the hardware
3455 * can do scatter/gather or not.
d129bceb 3456 */
2134a922 3457 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3458 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3459 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3460 mmc->max_segs = 1;
2134a922 3461 else /* PIO */
4fb213f8 3462 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3463
3464 /*
ac00531d
AH		 3465 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3466 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3467 * is less anyway.
d129bceb 3468 */
55db890a 3469 mmc->max_req_size = 524288;
d129bceb
PO		 3470
3471 /*
3472 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3473 * of bytes. When doing hardware scatter/gather, each entry cannot
3474 * be larger than 64 KiB though.
d129bceb 3475 */
30652aa3
OJ		 3476 if (host->flags & SDHCI_USE_ADMA) {
3477 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3478 mmc->max_seg_size = 65535;
3479 else
3480 mmc->max_seg_size = 65536;
3481 } else {
2134a922 3482 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3483 }
d129bceb 3484
fe4a3c7a
PO		 3485 /*
3486 * Maximum block size. This varies from controller to controller and
3487 * is specified in the capabilities register.
3488 */
0633f654
AV		 3489 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3490 mmc->max_blk_size = 2;
3491 } else {
28da3589 3492 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3493 SDHCI_MAX_BLOCK_SHIFT;
3494 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3495 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3496 mmc_hostname(mmc));
0633f654
AV		 3497 mmc->max_blk_size = 0;
3498 }
3499 }
3500
3501 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3502
55db890a
PO		 3503 /*
3504 * Maximum block count.
3505 */
1388eefd 3506 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3507
52f5336d
AH		 3508 return 0;
3509
3510unreg:
3511 if (!IS_ERR(mmc->supply.vqmmc))
3512 regulator_disable(mmc->supply.vqmmc);
3513undma:
3514 if (host->align_buffer)
3515 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3516 host->adma_table_sz, host->align_buffer,
3517 host->align_addr);
3518 host->adma_table = NULL;
3519 host->align_buffer = NULL;
3520
3521 return ret;
3522}
3523EXPORT_SYMBOL_GPL(sdhci_setup_host);
3524
3525int __sdhci_add_host(struct sdhci_host *host)
3526{
3527 struct mmc_host *mmc = host->mmc;
3528 int ret;
3529
d129bceb
PO		 3530 /*
3531 * Init tasklets.
3532 */
d129bceb
PO		 3533 tasklet_init(&host->finish_tasklet,
3534 sdhci_tasklet_finish, (unsigned long)host);
3535
e4cad1b5 3536 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d7422fb4
AH		 3537 setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3538 (unsigned long)host);
d129bceb 3539
250fb7b4 3540 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3541
2af502ca
SG		 3542 sdhci_init(host, 0);
3543
781e989c
RK		 3544 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3545 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3546 if (ret) {
3547 pr_err("%s: Failed to request IRQ %d: %d\n",
3548 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3549 goto untasklet;
0fc81ee3 3550 }
d129bceb 3551
d129bceb
PO		 3552#ifdef CONFIG_MMC_DEBUG
3553 sdhci_dumpregs(host);
3554#endif
3555
061d17a6 3556 ret = sdhci_led_register(host);
0fc81ee3
MB		 3557 if (ret) {
3558 pr_err("%s: Failed to register LED device: %d\n",
3559 mmc_hostname(mmc), ret);
eb5c20de 3560 goto unirq;
0fc81ee3 3561 }
2f730fec 3562
5f25a66f
PO		 3563 mmiowb();
3564
eb5c20de
AH		 3565 ret = mmc_add_host(mmc);
3566 if (ret)
3567 goto unled;
d129bceb 3568
a3c76eb9 3569 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3570 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3571 (host->flags & SDHCI_USE_ADMA) ?
3572 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3573 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3574
7260cf5e
AV		 3575 sdhci_enable_card_detection(host);
3576
d129bceb
PO		 3577 return 0;
3578
eb5c20de 3579unled:
061d17a6 3580 sdhci_led_unregister(host);
eb5c20de 3581unirq:
03231f9b 3582 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3583 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3584 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 3585 free_irq(host->irq, host);
8ef1a143 3586untasklet:
d129bceb 3587 tasklet_kill(&host->finish_tasklet);
52f5336d 3588
eb5c20de
AH		 3589 if (!IS_ERR(mmc->supply.vqmmc))
3590 regulator_disable(mmc->supply.vqmmc);
52f5336d 3591
eb5c20de
AH		 3592 if (host->align_buffer)
3593 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3594 host->adma_table_sz, host->align_buffer,
3595 host->align_addr);
3596 host->adma_table = NULL;
3597 host->align_buffer = NULL;
d129bceb
PO		 3598
3599 return ret;
3600}
52f5336d
AH		 3601EXPORT_SYMBOL_GPL(__sdhci_add_host);
3602
3603int sdhci_add_host(struct sdhci_host *host)
3604{
3605 int ret;
3606
3607 ret = sdhci_setup_host(host);
3608 if (ret)
3609 return ret;
d129bceb 3610
52f5336d
AH		 3611 return __sdhci_add_host(host);
3612}
b8c86fc5 3613EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3614
1e72859e 3615void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3616{
3a48edc4 3617 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3618 unsigned long flags;
3619
3620 if (dead) {
3621 spin_lock_irqsave(&host->lock, flags);
3622
3623 host->flags |= SDHCI_DEVICE_DEAD;
3624
5d0d11c5 3625 if (sdhci_has_requests(host)) {
a3c76eb9 3626 pr_err("%s: Controller removed during "
4e743f1f 3627 " transfer!\n", mmc_hostname(mmc));
5d0d11c5 3628 sdhci_error_out_mrqs(host, -ENOMEDIUM);
1e72859e
PO		 3629 }
3630
3631 spin_unlock_irqrestore(&host->lock, flags);
3632 }
3633
7260cf5e
AV		 3634 sdhci_disable_card_detection(host);
3635
4e743f1f 3636 mmc_remove_host(mmc);
d129bceb 3637
061d17a6 3638 sdhci_led_unregister(host);
2f730fec 3639
1e72859e 3640 if (!dead)
03231f9b 3641 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3642
b537f94c
RK		 3643 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3644 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3645 free_irq(host->irq, host);
3646
3647 del_timer_sync(&host->timer);
d7422fb4 3648 del_timer_sync(&host->data_timer);
d129bceb 3649
d129bceb 3650 tasklet_kill(&host->finish_tasklet);
2134a922 3651
3a48edc4
TK		 3652 if (!IS_ERR(mmc->supply.vqmmc))
3653 regulator_disable(mmc->supply.vqmmc);
6231f3de 3654
edd63fcc 3655 if (host->align_buffer)
e66e61cb
RK		 3656 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3657 host->adma_table_sz, host->align_buffer,
3658 host->align_addr);
2134a922 3659
4efaa6fb 3660 host->adma_table = NULL;
2134a922 3661 host->align_buffer = NULL;
d129bceb
PO		 3662}
3663
b8c86fc5 3664EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3665
b8c86fc5 3666void sdhci_free_host(struct sdhci_host *host)
d129bceb 3667{
b8c86fc5 3668 mmc_free_host(host->mmc);
d129bceb
PO		 3669}
3670
b8c86fc5 3671EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3672
3673/*****************************************************************************\
3674 * *
3675 * Driver init/exit *
3676 * *
3677\*****************************************************************************/
3678
3679static int __init sdhci_drv_init(void)
3680{
a3c76eb9 3681 pr_info(DRIVER_NAME
52fbf9c9 3682 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3683 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3684
b8c86fc5 3685 return 0;
d129bceb
PO		 3686}
3687
3688static void __exit sdhci_drv_exit(void)
3689{
d129bceb
PO		 3690}
3691
3692module_init(sdhci_drv_init);
3693module_exit(sdhci_drv_exit);
3694
df673b22 3695module_param(debug_quirks, uint, 0444);
66fd8ad5 3696module_param(debug_quirks2, uint, 0444);
67435274 3697
32710e8f 3698MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3699MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3700MODULE_LICENSE("GPL");
67435274 3701
df673b22 3702MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3703MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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