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Merge remote-tracking branch 'omap_dss2/for-next'
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Overview:
3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
61b03bd7 5 *
1da177e4 6 * Additional technical information is available on
8b2b403c 7 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 8 *
1da177e4 9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 11 *
ace4dfee 12 * Credits:
61b03bd7
TG		 13 * David Woodhouse for adding multichip support
14 *
1da177e4
LT		 15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
17 *
ace4dfee 18 * TODO:
1da177e4
LT		 19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 21 * if we have HW ECC support.
c0b8ba7b 22 * BBT table is not serialized, has to be fixed
1da177e4 23 *
1da177e4
LT		 24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
20171642
EG		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
552d9205 32#include <linux/module.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/errno.h>
7aa65bfd 35#include <linux/err.h>
1da177e4
LT		 36#include <linux/sched.h>
37#include <linux/slab.h>
66507c7b 38#include <linux/mm.h>
1da177e4
LT		 39#include <linux/types.h>
40#include <linux/mtd/mtd.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/nand_ecc.h>
193bd400 43#include <linux/mtd/nand_bch.h>
1da177e4
LT		 44#include <linux/interrupt.h>
45#include <linux/bitops.h>
7351d3a5 46#include <linux/io.h>
1da177e4 47#include <linux/mtd/partitions.h>
d48f62b9 48#include <linux/of.h>
1da177e4 49
41b207a7
BB		 50static int nand_get_device(struct mtd_info *mtd, int new_state);
51
52static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
53 struct mtd_oob_ops *ops);
1da177e4
LT		 54
55/* Define default oob placement schemes for large and small page devices */
41b207a7
BB		 56static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
57 struct mtd_oob_region *oobregion)
58{
59 struct nand_chip *chip = mtd_to_nand(mtd);
60 struct nand_ecc_ctrl *ecc = &chip->ecc;
1da177e4 61
41b207a7
BB		 62 if (section > 1)
63 return -ERANGE;
1da177e4 64
41b207a7
BB		 65 if (!section) {
66 oobregion->offset = 0;
67 oobregion->length = 4;
68 } else {
69 oobregion->offset = 6;
70 oobregion->length = ecc->total - 4;
71 }
1da177e4 72
41b207a7
BB		 73 return 0;
74}
75
76static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
77 struct mtd_oob_region *oobregion)
78{
79 if (section > 1)
80 return -ERANGE;
1da177e4 81
41b207a7
BB		 82 if (mtd->oobsize == 16) {
83 if (section)
84 return -ERANGE;
85
86 oobregion->length = 8;
87 oobregion->offset = 8;
88 } else {
89 oobregion->length = 2;
90 if (!section)
91 oobregion->offset = 3;
92 else
93 oobregion->offset = 6;
94 }
95
96 return 0;
97}
98
99const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
100 .ecc = nand_ooblayout_ecc_sp,
101 .free = nand_ooblayout_free_sp,
81ec5364 102};
41b207a7 103EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops);
81ec5364 104
41b207a7
BB		 105static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
106 struct mtd_oob_region *oobregion)
107{
108 struct nand_chip *chip = mtd_to_nand(mtd);
109 struct nand_ecc_ctrl *ecc = &chip->ecc;
1da177e4 110
41b207a7
BB		 111 if (section)
112 return -ERANGE;
8593fbc6 113
41b207a7
BB		 114 oobregion->length = ecc->total;
115 oobregion->offset = mtd->oobsize - oobregion->length;
116
117 return 0;
118}
119
120static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
121 struct mtd_oob_region *oobregion)
122{
123 struct nand_chip *chip = mtd_to_nand(mtd);
124 struct nand_ecc_ctrl *ecc = &chip->ecc;
125
126 if (section)
127 return -ERANGE;
128
129 oobregion->length = mtd->oobsize - ecc->total - 2;
130 oobregion->offset = 2;
131
132 return 0;
133}
134
135const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
136 .ecc = nand_ooblayout_ecc_lp,
137 .free = nand_ooblayout_free_lp,
138};
139EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops);
d470a97c 140
6fe5a6ac
VS		 141static int check_offs_len(struct mtd_info *mtd,
142 loff_t ofs, uint64_t len)
143{
862eba51 144 struct nand_chip *chip = mtd_to_nand(mtd);
6fe5a6ac
VS		 145 int ret = 0;
146
147 /* Start address must align on block boundary */
daae74ca 148 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 149 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 150 ret = -EINVAL;
151 }
152
153 /* Length must align on block boundary */
daae74ca 154 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 155 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 156 ret = -EINVAL;
157 }
158
6fe5a6ac
VS		 159 return ret;
160}
161
1da177e4
LT		 162/**
163 * nand_release_device - [GENERIC] release chip
8b6e50c9 164 * @mtd: MTD device structure
61b03bd7 165 *
b0bb6903 166 * Release chip lock and wake up anyone waiting on the device.
1da177e4 167 */
e0c7d767 168static void nand_release_device(struct mtd_info *mtd)
1da177e4 169{
862eba51 170 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 171
a36ed299 172 /* Release the controller and the chip */
ace4dfee
TG		 173 spin_lock(&chip->controller->lock);
174 chip->controller->active = NULL;
175 chip->state = FL_READY;
176 wake_up(&chip->controller->wq);
177 spin_unlock(&chip->controller->lock);
1da177e4
LT		 178}
179
180/**
181 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 182 * @mtd: MTD device structure
1da177e4 183 *
7854d3f7 184 * Default read function for 8bit buswidth
1da177e4 185 */
58dd8f2b 186static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 187{
862eba51 188 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 189 return readb(chip->IO_ADDR_R);
1da177e4
LT		 190}
191
1da177e4 192/**
7854d3f7 193 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 194 * @mtd: MTD device structure
1da177e4 195 *
7854d3f7
BN		 196 * Default read function for 16bit buswidth with endianness conversion.
197 *
1da177e4 198 */
58dd8f2b 199static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 200{
862eba51 201 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 202 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 203}
204
1da177e4
LT		 205/**
206 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 207 * @mtd: MTD device structure
1da177e4 208 *
7854d3f7 209 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 210 */
211static u16 nand_read_word(struct mtd_info *mtd)
212{
862eba51 213 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 214 return readw(chip->IO_ADDR_R);
1da177e4
LT		 215}
216
1da177e4
LT		 217/**
218 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 219 * @mtd: MTD device structure
220 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 221 *
222 * Default select function for 1 chip devices.
223 */
ace4dfee 224static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 225{
862eba51 226 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee
TG		 227
228 switch (chipnr) {
1da177e4 229 case -1:
ace4dfee 230 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 231 break;
232 case 0:
1da177e4
LT		 233 break;
234
235 default:
236 BUG();
237 }
238}
239
05f78359
UKK		 240/**
241 * nand_write_byte - [DEFAULT] write single byte to chip
242 * @mtd: MTD device structure
243 * @byte: value to write
244 *
245 * Default function to write a byte to I/O[7:0]
246 */
247static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
248{
862eba51 249 struct nand_chip *chip = mtd_to_nand(mtd);
05f78359
UKK		 250
251 chip->write_buf(mtd, &byte, 1);
252}
253
254/**
255 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
256 * @mtd: MTD device structure
257 * @byte: value to write
258 *
259 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
260 */
261static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
262{
862eba51 263 struct nand_chip *chip = mtd_to_nand(mtd);
05f78359
UKK		 264 uint16_t word = byte;
265
266 /*
267 * It's not entirely clear what should happen to I/O[15:8] when writing
268 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
269 *
270 * When the host supports a 16-bit bus width, only data is
271 * transferred at the 16-bit width. All address and command line
272 * transfers shall use only the lower 8-bits of the data bus. During
273 * command transfers, the host may place any value on the upper
274 * 8-bits of the data bus. During address transfers, the host shall
275 * set the upper 8-bits of the data bus to 00h.
276 *
277 * One user of the write_byte callback is nand_onfi_set_features. The
278 * four parameters are specified to be written to I/O[7:0], but this is
279 * neither an address nor a command transfer. Let's assume a 0 on the
280 * upper I/O lines is OK.
281 */
282 chip->write_buf(mtd, (uint8_t *)&word, 2);
283}
284
1da177e4
LT		 285/**
286 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 287 * @mtd: MTD device structure
288 * @buf: data buffer
289 * @len: number of bytes to write
1da177e4 290 *
7854d3f7 291 * Default write function for 8bit buswidth.
1da177e4 292 */
58dd8f2b 293static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 294{
862eba51 295 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 296
76413839 297 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 298}
299
300/**
61b03bd7 301 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 302 * @mtd: MTD device structure
303 * @buf: buffer to store date
304 * @len: number of bytes to read
1da177e4 305 *
7854d3f7 306 * Default read function for 8bit buswidth.
1da177e4 307 */
58dd8f2b 308static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 309{
862eba51 310 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 311
76413839 312 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 313}
314
1da177e4
LT		 315/**
316 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 317 * @mtd: MTD device structure
318 * @buf: data buffer
319 * @len: number of bytes to write
1da177e4 320 *
7854d3f7 321 * Default write function for 16bit buswidth.
1da177e4 322 */
58dd8f2b 323static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 324{
862eba51 325 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 326 u16 *p = (u16 *) buf;
61b03bd7 327
76413839 328 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 329}
330
331/**
61b03bd7 332 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 333 * @mtd: MTD device structure
334 * @buf: buffer to store date
335 * @len: number of bytes to read
1da177e4 336 *
7854d3f7 337 * Default read function for 16bit buswidth.
1da177e4 338 */
58dd8f2b 339static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 340{
862eba51 341 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 342 u16 *p = (u16 *) buf;
1da177e4 343
76413839 344 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 345}
346
1da177e4
LT		 347/**
348 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 349 * @mtd: MTD device structure
350 * @ofs: offset from device start
1da177e4 351 *
61b03bd7 352 * Check, if the block is bad.
1da177e4 353 */
9f3e0429 354static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
1da177e4 355{
9f3e0429 356 int page, res = 0, i = 0;
862eba51 357 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4
LT		 358 u16 bad;
359
5fb1549d 360 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 361 ofs += mtd->erasesize - mtd->writesize;
362
1a12f46a
TK		 363 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
364
cdbec050
BN		 365 do {
366 if (chip->options & NAND_BUSWIDTH_16) {
367 chip->cmdfunc(mtd, NAND_CMD_READOOB,
368 chip->badblockpos & 0xFE, page);
369 bad = cpu_to_le16(chip->read_word(mtd));
370 if (chip->badblockpos & 0x1)
371 bad >>= 8;
372 else
373 bad &= 0xFF;
374 } else {
375 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
376 page);
377 bad = chip->read_byte(mtd);
378 }
379
380 if (likely(chip->badblockbits == 8))
381 res = bad != 0xFF;
e0b58d0a 382 else
cdbec050
BN		 383 res = hweight8(bad) < chip->badblockbits;
384 ofs += mtd->writesize;
385 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
386 i++;
387 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 388
1da177e4
LT		 389 return res;
390}
391
392/**
5a0edb25 393 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
8b6e50c9
BN		 394 * @mtd: MTD device structure
395 * @ofs: offset from device start
1da177e4 396 *
8b6e50c9 397 * This is the default implementation, which can be overridden by a hardware
5a0edb25
BN		 398 * specific driver. It provides the details for writing a bad block marker to a
399 * block.
400 */
401static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
402{
862eba51 403 struct nand_chip *chip = mtd_to_nand(mtd);
5a0edb25
BN		 404 struct mtd_oob_ops ops;
405 uint8_t buf[2] = { 0, 0 };
406 int ret = 0, res, i = 0;
407
0ec56dc4 408 memset(&ops, 0, sizeof(ops));
5a0edb25
BN		 409 ops.oobbuf = buf;
410 ops.ooboffs = chip->badblockpos;
411 if (chip->options & NAND_BUSWIDTH_16) {
412 ops.ooboffs &= ~0x01;
413 ops.len = ops.ooblen = 2;
414 } else {
415 ops.len = ops.ooblen = 1;
416 }
417 ops.mode = MTD_OPS_PLACE_OOB;
418
419 /* Write to first/last page(s) if necessary */
420 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
421 ofs += mtd->erasesize - mtd->writesize;
422 do {
423 res = nand_do_write_oob(mtd, ofs, &ops);
424 if (!ret)
425 ret = res;
426
427 i++;
428 ofs += mtd->writesize;
429 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
430
431 return ret;
432}
433
434/**
435 * nand_block_markbad_lowlevel - mark a block bad
436 * @mtd: MTD device structure
437 * @ofs: offset from device start
438 *
439 * This function performs the generic NAND bad block marking steps (i.e., bad
440 * block table(s) and/or marker(s)). We only allow the hardware driver to
441 * specify how to write bad block markers to OOB (chip->block_markbad).
442 *
b32843b7 443 * We try operations in the following order:
e2414f4c 444 * (1) erase the affected block, to allow OOB marker to be written cleanly
b32843b7
BN		 445 * (2) write bad block marker to OOB area of affected block (unless flag
446 * NAND_BBT_NO_OOB_BBM is present)
447 * (3) update the BBT
448 * Note that we retain the first error encountered in (2) or (3), finish the
e2414f4c 449 * procedures, and dump the error in the end.
1da177e4 450*/
5a0edb25 451static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
1da177e4 452{
862eba51 453 struct nand_chip *chip = mtd_to_nand(mtd);
b32843b7 454 int res, ret = 0;
61b03bd7 455
b32843b7 456 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
00918429
BN		 457 struct erase_info einfo;
458
459 /* Attempt erase before marking OOB */
460 memset(&einfo, 0, sizeof(einfo));
461 einfo.mtd = mtd;
462 einfo.addr = ofs;
daae74ca 463 einfo.len = 1ULL << chip->phys_erase_shift;
00918429 464 nand_erase_nand(mtd, &einfo, 0);
1da177e4 465
b32843b7 466 /* Write bad block marker to OOB */
6a8214aa 467 nand_get_device(mtd, FL_WRITING);
5a0edb25 468 ret = chip->block_markbad(mtd, ofs);
c0b8ba7b 469 nand_release_device(mtd);
f1a28c02 470 }
e2414f4c 471
b32843b7
BN		 472 /* Mark block bad in BBT */
473 if (chip->bbt) {
474 res = nand_markbad_bbt(mtd, ofs);
e2414f4c
BN		 475 if (!ret)
476 ret = res;
477 }
478
f1a28c02
TG		 479 if (!ret)
480 mtd->ecc_stats.badblocks++;
c0b8ba7b 481
f1a28c02 482 return ret;
1da177e4
LT		 483}
484
61b03bd7 485/**
1da177e4 486 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 487 * @mtd: MTD device structure
1da177e4 488 *
8b6e50c9
BN		 489 * Check, if the device is write protected. The function expects, that the
490 * device is already selected.
1da177e4 491 */
e0c7d767 492static int nand_check_wp(struct mtd_info *mtd)
1da177e4 493{
862eba51 494 struct nand_chip *chip = mtd_to_nand(mtd);
93edbad6 495
8b6e50c9 496 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 497 if (chip->options & NAND_BROKEN_XD)
498 return 0;
499
1da177e4 500 /* Check the WP bit */
ace4dfee
TG		 501 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
502 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 503}
504
8471bb73 505/**
c30e1f79 506 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
8471bb73
EG		 507 * @mtd: MTD device structure
508 * @ofs: offset from device start
509 *
c30e1f79 510 * Check if the block is marked as reserved.
8471bb73
EG		 511 */
512static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
513{
862eba51 514 struct nand_chip *chip = mtd_to_nand(mtd);
8471bb73
EG		 515
516 if (!chip->bbt)
517 return 0;
518 /* Return info from the table */
519 return nand_isreserved_bbt(mtd, ofs);
520}
521
1da177e4
LT		 522/**
523 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 524 * @mtd: MTD device structure
525 * @ofs: offset from device start
8b6e50c9 526 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 527 *
528 * Check, if the block is bad. Either by reading the bad block table or
529 * calling of the scan function.
530 */
9f3e0429 531static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
1da177e4 532{
862eba51 533 struct nand_chip *chip = mtd_to_nand(mtd);
61b03bd7 534
ace4dfee 535 if (!chip->bbt)
9f3e0429 536 return chip->block_bad(mtd, ofs);
61b03bd7 537
1da177e4 538 /* Return info from the table */
e0c7d767 539 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 540}
541
2af7c653
SK		 542/**
543 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 544 * @mtd: MTD device structure
545 * @timeo: Timeout
2af7c653
SK		 546 *
547 * Helper function for nand_wait_ready used when needing to wait in interrupt
548 * context.
549 */
550static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
551{
862eba51 552 struct nand_chip *chip = mtd_to_nand(mtd);
2af7c653
SK		 553 int i;
554
555 /* Wait for the device to get ready */
556 for (i = 0; i < timeo; i++) {
557 if (chip->dev_ready(mtd))
558 break;
559 touch_softlockup_watchdog();
560 mdelay(1);
561 }
562}
563
b70af9be
AS		 564/**
565 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
566 * @mtd: MTD device structure
567 *
568 * Wait for the ready pin after a command, and warn if a timeout occurs.
569 */
4b648b02 570void nand_wait_ready(struct mtd_info *mtd)
3b88775c 571{
862eba51 572 struct nand_chip *chip = mtd_to_nand(mtd);
b70af9be 573 unsigned long timeo = 400;
3b88775c 574
2af7c653 575 if (in_interrupt() || oops_in_progress)
b70af9be 576 return panic_nand_wait_ready(mtd, timeo);
2af7c653 577
7854d3f7 578 /* Wait until command is processed or timeout occurs */
b70af9be 579 timeo = jiffies + msecs_to_jiffies(timeo);
3b88775c 580 do {
ace4dfee 581 if (chip->dev_ready(mtd))
4c7e054f 582 return;
b70af9be 583 cond_resched();
61b03bd7 584 } while (time_before(jiffies, timeo));
b70af9be 585
9ebfdf5b
BN		 586 if (!chip->dev_ready(mtd))
587 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
3b88775c 588}
4b648b02 589EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 590
60c70d66
RQ		 591/**
592 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
593 * @mtd: MTD device structure
594 * @timeo: Timeout in ms
595 *
596 * Wait for status ready (i.e. command done) or timeout.
597 */
598static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
599{
862eba51 600 register struct nand_chip *chip = mtd_to_nand(mtd);
60c70d66
RQ		 601
602 timeo = jiffies + msecs_to_jiffies(timeo);
603 do {
604 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
605 break;
606 touch_softlockup_watchdog();
607 } while (time_before(jiffies, timeo));
608};
609
1da177e4
LT		 610/**
611 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 612 * @mtd: MTD device structure
613 * @command: the command to be sent
614 * @column: the column address for this command, -1 if none
615 * @page_addr: the page address for this command, -1 if none
1da177e4 616 *
8b6e50c9 617 * Send command to NAND device. This function is used for small page devices
51148f1f 618 * (512 Bytes per page).
1da177e4 619 */
7abd3ef9
TG		 620static void nand_command(struct mtd_info *mtd, unsigned int command,
621 int column, int page_addr)
1da177e4 622{
862eba51 623 register struct nand_chip *chip = mtd_to_nand(mtd);
7abd3ef9 624 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 625
8b6e50c9 626 /* Write out the command to the device */
1da177e4
LT		 627 if (command == NAND_CMD_SEQIN) {
628 int readcmd;
629
28318776 630 if (column >= mtd->writesize) {
1da177e4 631 /* OOB area */
28318776 632 column -= mtd->writesize;
1da177e4
LT		 633 readcmd = NAND_CMD_READOOB;
634 } else if (column < 256) {
635 /* First 256 bytes --> READ0 */
636 readcmd = NAND_CMD_READ0;
637 } else {
638 column -= 256;
639 readcmd = NAND_CMD_READ1;
640 }
ace4dfee 641 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 642 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 643 }
ace4dfee 644 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 645
8b6e50c9 646 /* Address cycle, when necessary */
7abd3ef9
TG		 647 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
648 /* Serially input address */
649 if (column != -1) {
650 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 651 if (chip->options & NAND_BUSWIDTH_16 &&
652 !nand_opcode_8bits(command))
7abd3ef9 653 column >>= 1;
ace4dfee 654 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 655 ctrl &= ~NAND_CTRL_CHANGE;
656 }
657 if (page_addr != -1) {
ace4dfee 658 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 659 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 660 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 661 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 662 if (chip->chipsize > (32 << 20))
663 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 664 }
ace4dfee 665 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 666
667 /*
8b6e50c9
BN		 668 * Program and erase have their own busy handlers status and sequential
669 * in needs no delay
e0c7d767 670 */
1da177e4 671 switch (command) {
61b03bd7 672
1da177e4
LT		 673 case NAND_CMD_PAGEPROG:
674 case NAND_CMD_ERASE1:
675 case NAND_CMD_ERASE2:
676 case NAND_CMD_SEQIN:
677 case NAND_CMD_STATUS:
678 return;
679
680 case NAND_CMD_RESET:
ace4dfee 681 if (chip->dev_ready)
1da177e4 682 break;
ace4dfee
TG		 683 udelay(chip->chip_delay);
684 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 685 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 686 chip->cmd_ctrl(mtd,
687 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 688 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
689 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 690 return;
691
e0c7d767 692 /* This applies to read commands */
1da177e4 693 default:
61b03bd7 694 /*
1da177e4
LT		 695 * If we don't have access to the busy pin, we apply the given
696 * command delay
e0c7d767 697 */
ace4dfee
TG		 698 if (!chip->dev_ready) {
699 udelay(chip->chip_delay);
1da177e4 700 return;
61b03bd7 701 }
1da177e4 702 }
8b6e50c9
BN		 703 /*
704 * Apply this short delay always to ensure that we do wait tWB in
705 * any case on any machine.
706 */
e0c7d767 707 ndelay(100);
3b88775c
TG		 708
709 nand_wait_ready(mtd);
1da177e4
LT		 710}
711
712/**
713 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 714 * @mtd: MTD device structure
715 * @command: the command to be sent
716 * @column: the column address for this command, -1 if none
717 * @page_addr: the page address for this command, -1 if none
1da177e4 718 *
7abd3ef9 719 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 720 * devices. We don't have the separate regions as we have in the small page
721 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 722 */
7abd3ef9
TG		 723static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
724 int column, int page_addr)
1da177e4 725{
862eba51 726 register struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4
LT		 727
728 /* Emulate NAND_CMD_READOOB */
729 if (command == NAND_CMD_READOOB) {
28318776 730 column += mtd->writesize;
1da177e4
LT		 731 command = NAND_CMD_READ0;
732 }
61b03bd7 733
7abd3ef9 734 /* Command latch cycle */
fb066ada 735 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 736
737 if (column != -1 || page_addr != -1) {
7abd3ef9 738 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 739
740 /* Serially input address */
741 if (column != -1) {
742 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 743 if (chip->options & NAND_BUSWIDTH_16 &&
744 !nand_opcode_8bits(command))
1da177e4 745 column >>= 1;
ace4dfee 746 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 747 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 748 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 749 }
1da177e4 750 if (page_addr != -1) {
ace4dfee
TG		 751 chip->cmd_ctrl(mtd, page_addr, ctrl);
752 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 753 NAND_NCE | NAND_ALE);
1da177e4 754 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 755 if (chip->chipsize > (128 << 20))
756 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 757 NAND_NCE | NAND_ALE);
1da177e4 758 }
1da177e4 759 }
ace4dfee 760 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 761
762 /*
8b6e50c9 763 * Program and erase have their own busy handlers status, sequential
7a442f17 764 * in and status need no delay.
30f464b7 765 */
1da177e4 766 switch (command) {
61b03bd7 767
1da177e4
LT		 768 case NAND_CMD_CACHEDPROG:
769 case NAND_CMD_PAGEPROG:
770 case NAND_CMD_ERASE1:
771 case NAND_CMD_ERASE2:
772 case NAND_CMD_SEQIN:
7bc3312b 773 case NAND_CMD_RNDIN:
1da177e4 774 case NAND_CMD_STATUS:
30f464b7 775 return;
1da177e4
LT		 776
777 case NAND_CMD_RESET:
ace4dfee 778 if (chip->dev_ready)
1da177e4 779 break;
ace4dfee 780 udelay(chip->chip_delay);
12efdde3
TG		 781 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
782 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
783 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
784 NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 785 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
786 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 787 return;
788
7bc3312b
TG		 789 case NAND_CMD_RNDOUT:
790 /* No ready / busy check necessary */
791 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
792 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
793 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
794 NAND_NCE | NAND_CTRL_CHANGE);
795 return;
796
1da177e4 797 case NAND_CMD_READ0:
12efdde3
TG		 798 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
799 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
800 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
801 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 802
e0c7d767 803 /* This applies to read commands */
1da177e4 804 default:
61b03bd7 805 /*
1da177e4 806 * If we don't have access to the busy pin, we apply the given
8b6e50c9 807 * command delay.
e0c7d767 808 */
ace4dfee
TG		 809 if (!chip->dev_ready) {
810 udelay(chip->chip_delay);
1da177e4 811 return;
61b03bd7 812 }
1da177e4 813 }
3b88775c 814
8b6e50c9
BN		 815 /*
816 * Apply this short delay always to ensure that we do wait tWB in
817 * any case on any machine.
818 */
e0c7d767 819 ndelay(100);
3b88775c
TG		 820
821 nand_wait_ready(mtd);
1da177e4
LT		 822}
823
2af7c653
SK		 824/**
825 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 826 * @chip: the nand chip descriptor
827 * @mtd: MTD device structure
828 * @new_state: the state which is requested
2af7c653
SK		 829 *
830 * Used when in panic, no locks are taken.
831 */
832static void panic_nand_get_device(struct nand_chip *chip,
833 struct mtd_info *mtd, int new_state)
834{
7854d3f7 835 /* Hardware controller shared among independent devices */
2af7c653
SK		 836 chip->controller->active = chip;
837 chip->state = new_state;
838}
839
1da177e4
LT		 840/**
841 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 842 * @mtd: MTD device structure
843 * @new_state: the state which is requested
1da177e4
LT		 844 *
845 * Get the device and lock it for exclusive access
846 */
2c0a2bed 847static int
6a8214aa 848nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 849{
862eba51 850 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee
TG		 851 spinlock_t *lock = &chip->controller->lock;
852 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 853 DECLARE_WAITQUEUE(wait, current);
7351d3a5 854retry:
0dfc6246
TG		 855 spin_lock(lock);
856
b8b3ee9a 857 /* Hardware controller shared among independent devices */
ace4dfee
TG		 858 if (!chip->controller->active)
859 chip->controller->active = chip;
a36ed299 860
ace4dfee
TG		 861 if (chip->controller->active == chip && chip->state == FL_READY) {
862 chip->state = new_state;
0dfc6246 863 spin_unlock(lock);
962034f4
VW		 864 return 0;
865 }
866 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 867 if (chip->controller->active->state == FL_PM_SUSPENDED) {
868 chip->state = FL_PM_SUSPENDED;
869 spin_unlock(lock);
870 return 0;
6b0d9a84 871 }
0dfc6246
TG		 872 }
873 set_current_state(TASK_UNINTERRUPTIBLE);
874 add_wait_queue(wq, &wait);
875 spin_unlock(lock);
876 schedule();
877 remove_wait_queue(wq, &wait);
1da177e4
LT		 878 goto retry;
879}
880
2af7c653 881/**
8b6e50c9
BN		 882 * panic_nand_wait - [GENERIC] wait until the command is done
883 * @mtd: MTD device structure
884 * @chip: NAND chip structure
885 * @timeo: timeout
2af7c653
SK		 886 *
887 * Wait for command done. This is a helper function for nand_wait used when
888 * we are in interrupt context. May happen when in panic and trying to write
b595076a 889 * an oops through mtdoops.
2af7c653
SK		 890 */
891static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
892 unsigned long timeo)
893{
894 int i;
895 for (i = 0; i < timeo; i++) {
896 if (chip->dev_ready) {
897 if (chip->dev_ready(mtd))
898 break;
899 } else {
900 if (chip->read_byte(mtd) & NAND_STATUS_READY)
901 break;
902 }
903 mdelay(1);
f8ac0414 904 }
2af7c653
SK		 905}
906
1da177e4 907/**
8b6e50c9
BN		 908 * nand_wait - [DEFAULT] wait until the command is done
909 * @mtd: MTD device structure
910 * @chip: NAND chip structure
1da177e4 911 *
b70af9be 912 * Wait for command done. This applies to erase and program only.
844d3b42 913 */
7bc3312b 914static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 915{
916
b70af9be
AS		 917 int status;
918 unsigned long timeo = 400;
1da177e4 919
8b6e50c9
BN		 920 /*
921 * Apply this short delay always to ensure that we do wait tWB in any
922 * case on any machine.
923 */
e0c7d767 924 ndelay(100);
1da177e4 925
14c65786 926 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 927
2af7c653
SK		 928 if (in_interrupt() || oops_in_progress)
929 panic_nand_wait(mtd, chip, timeo);
930 else {
6d2559f8 931 timeo = jiffies + msecs_to_jiffies(timeo);
b70af9be 932 do {
2af7c653
SK		 933 if (chip->dev_ready) {
934 if (chip->dev_ready(mtd))
935 break;
936 } else {
937 if (chip->read_byte(mtd) & NAND_STATUS_READY)
938 break;
939 }
940 cond_resched();
b70af9be 941 } while (time_before(jiffies, timeo));
1da177e4 942 }
8fe833c1 943
ace4dfee 944 status = (int)chip->read_byte(mtd);
f251b8df
MC		 945 /* This can happen if in case of timeout or buggy dev_ready */
946 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 947 return status;
948}
949
7d70f334 950/**
b6d676db 951 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 952 * @mtd: mtd info
953 * @ofs: offset to start unlock from
954 * @len: length to unlock
8b6e50c9
BN		 955 * @invert: when = 0, unlock the range of blocks within the lower and
956 * upper boundary address
957 * when = 1, unlock the range of blocks outside the boundaries
958 * of the lower and upper boundary address
7d70f334 959 *
8b6e50c9 960 * Returs unlock status.
7d70f334
VS		 961 */
962static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
963 uint64_t len, int invert)
964{
965 int ret = 0;
966 int status, page;
862eba51 967 struct nand_chip *chip = mtd_to_nand(mtd);
7d70f334
VS		 968
969 /* Submit address of first page to unlock */
970 page = ofs >> chip->page_shift;
971 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
972
973 /* Submit address of last page to unlock */
974 page = (ofs + len) >> chip->page_shift;
975 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
976 (page | invert) & chip->pagemask);
977
978 /* Call wait ready function */
979 status = chip->waitfunc(mtd, chip);
7d70f334 980 /* See if device thinks it succeeded */
74830966 981 if (status & NAND_STATUS_FAIL) {
289c0522 982 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 983 __func__, status);
984 ret = -EIO;
985 }
986
987 return ret;
988}
989
990/**
b6d676db 991 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 992 * @mtd: mtd info
993 * @ofs: offset to start unlock from
994 * @len: length to unlock
7d70f334 995 *
8b6e50c9 996 * Returns unlock status.
7d70f334
VS		 997 */
998int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
999{
1000 int ret = 0;
1001 int chipnr;
862eba51 1002 struct nand_chip *chip = mtd_to_nand(mtd);
7d70f334 1003
289c0522 1004 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1005 __func__, (unsigned long long)ofs, len);
1006
1007 if (check_offs_len(mtd, ofs, len))
b1a2348a 1008 return -EINVAL;
7d70f334
VS		 1009
1010 /* Align to last block address if size addresses end of the device */
1011 if (ofs + len == mtd->size)
1012 len -= mtd->erasesize;
1013
6a8214aa 1014 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 1015
1016 /* Shift to get chip number */
1017 chipnr = ofs >> chip->chip_shift;
1018
1019 chip->select_chip(mtd, chipnr);
1020
57d3a9a8
WD		 1021 /*
1022 * Reset the chip.
1023 * If we want to check the WP through READ STATUS and check the bit 7
1024 * we must reset the chip
1025 * some operation can also clear the bit 7 of status register
1026 * eg. erase/program a locked block
1027 */
1028 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1029
7d70f334
VS		 1030 /* Check, if it is write protected */
1031 if (nand_check_wp(mtd)) {
289c0522 1032 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1033 __func__);
1034 ret = -EIO;
1035 goto out;
1036 }
1037
1038 ret = __nand_unlock(mtd, ofs, len, 0);
1039
1040out:
b0bb6903 1041 chip->select_chip(mtd, -1);
7d70f334
VS		 1042 nand_release_device(mtd);
1043
1044 return ret;
1045}
7351d3a5 1046EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 1047
1048/**
b6d676db 1049 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 1050 * @mtd: mtd info
1051 * @ofs: offset to start unlock from
1052 * @len: length to unlock
7d70f334 1053 *
8b6e50c9
BN		 1054 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1055 * have this feature, but it allows only to lock all blocks, not for specified
1056 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1057 * now.
7d70f334 1058 *
8b6e50c9 1059 * Returns lock status.
7d70f334
VS		 1060 */
1061int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1062{
1063 int ret = 0;
1064 int chipnr, status, page;
862eba51 1065 struct nand_chip *chip = mtd_to_nand(mtd);
7d70f334 1066
289c0522 1067 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1068 __func__, (unsigned long long)ofs, len);
1069
1070 if (check_offs_len(mtd, ofs, len))
b1a2348a 1071 return -EINVAL;
7d70f334 1072
6a8214aa 1073 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 1074
1075 /* Shift to get chip number */
1076 chipnr = ofs >> chip->chip_shift;
1077
1078 chip->select_chip(mtd, chipnr);
1079
57d3a9a8
WD		 1080 /*
1081 * Reset the chip.
1082 * If we want to check the WP through READ STATUS and check the bit 7
1083 * we must reset the chip
1084 * some operation can also clear the bit 7 of status register
1085 * eg. erase/program a locked block
1086 */
1087 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1088
7d70f334
VS		 1089 /* Check, if it is write protected */
1090 if (nand_check_wp(mtd)) {
289c0522 1091 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1092 __func__);
1093 status = MTD_ERASE_FAILED;
1094 ret = -EIO;
1095 goto out;
1096 }
1097
1098 /* Submit address of first page to lock */
1099 page = ofs >> chip->page_shift;
1100 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1101
1102 /* Call wait ready function */
1103 status = chip->waitfunc(mtd, chip);
7d70f334 1104 /* See if device thinks it succeeded */
74830966 1105 if (status & NAND_STATUS_FAIL) {
289c0522 1106 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1107 __func__, status);
1108 ret = -EIO;
1109 goto out;
1110 }
1111
1112 ret = __nand_unlock(mtd, ofs, len, 0x1);
1113
1114out:
b0bb6903 1115 chip->select_chip(mtd, -1);
7d70f334
VS		 1116 nand_release_device(mtd);
1117
1118 return ret;
1119}
7351d3a5 1120EXPORT_SYMBOL(nand_lock);
7d70f334 1121
730a43fb
BB		 1122/**
1123 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1124 * @buf: buffer to test
1125 * @len: buffer length
1126 * @bitflips_threshold: maximum number of bitflips
1127 *
1128 * Check if a buffer contains only 0xff, which means the underlying region
1129 * has been erased and is ready to be programmed.
1130 * The bitflips_threshold specify the maximum number of bitflips before
1131 * considering the region is not erased.
1132 * Note: The logic of this function has been extracted from the memweight
1133 * implementation, except that nand_check_erased_buf function exit before
1134 * testing the whole buffer if the number of bitflips exceed the
1135 * bitflips_threshold value.
1136 *
1137 * Returns a positive number of bitflips less than or equal to
1138 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1139 * threshold.
1140 */
1141static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1142{
1143 const unsigned char *bitmap = buf;
1144 int bitflips = 0;
1145 int weight;
1146
1147 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1148 len--, bitmap++) {
1149 weight = hweight8(*bitmap);
1150 bitflips += BITS_PER_BYTE - weight;
1151 if (unlikely(bitflips > bitflips_threshold))
1152 return -EBADMSG;
1153 }
1154
1155 for (; len >= sizeof(long);
1156 len -= sizeof(long), bitmap += sizeof(long)) {
1157 weight = hweight_long(*((unsigned long *)bitmap));
1158 bitflips += BITS_PER_LONG - weight;
1159 if (unlikely(bitflips > bitflips_threshold))
1160 return -EBADMSG;
1161 }
1162
1163 for (; len > 0; len--, bitmap++) {
1164 weight = hweight8(*bitmap);
1165 bitflips += BITS_PER_BYTE - weight;
1166 if (unlikely(bitflips > bitflips_threshold))
1167 return -EBADMSG;
1168 }
1169
1170 return bitflips;
1171}
1172
1173/**
1174 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1175 * 0xff data
1176 * @data: data buffer to test
1177 * @datalen: data length
1178 * @ecc: ECC buffer
1179 * @ecclen: ECC length
1180 * @extraoob: extra OOB buffer
1181 * @extraooblen: extra OOB length
1182 * @bitflips_threshold: maximum number of bitflips
1183 *
1184 * Check if a data buffer and its associated ECC and OOB data contains only
1185 * 0xff pattern, which means the underlying region has been erased and is
1186 * ready to be programmed.
1187 * The bitflips_threshold specify the maximum number of bitflips before
1188 * considering the region as not erased.
1189 *
1190 * Note:
1191 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1192 * different from the NAND page size. When fixing bitflips, ECC engines will
1193 * report the number of errors per chunk, and the NAND core infrastructure
1194 * expect you to return the maximum number of bitflips for the whole page.
1195 * This is why you should always use this function on a single chunk and
1196 * not on the whole page. After checking each chunk you should update your
1197 * max_bitflips value accordingly.
1198 * 2/ When checking for bitflips in erased pages you should not only check
1199 * the payload data but also their associated ECC data, because a user might
1200 * have programmed almost all bits to 1 but a few. In this case, we
1201 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1202 * this case.
1203 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1204 * data are protected by the ECC engine.
1205 * It could also be used if you support subpages and want to attach some
1206 * extra OOB data to an ECC chunk.
1207 *
1208 * Returns a positive number of bitflips less than or equal to
1209 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1210 * threshold. In case of success, the passed buffers are filled with 0xff.
1211 */
1212int nand_check_erased_ecc_chunk(void *data, int datalen,
1213 void *ecc, int ecclen,
1214 void *extraoob, int extraooblen,
1215 int bitflips_threshold)
1216{
1217 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1218
1219 data_bitflips = nand_check_erased_buf(data, datalen,
1220 bitflips_threshold);
1221 if (data_bitflips < 0)
1222 return data_bitflips;
1223
1224 bitflips_threshold -= data_bitflips;
1225
1226 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1227 if (ecc_bitflips < 0)
1228 return ecc_bitflips;
1229
1230 bitflips_threshold -= ecc_bitflips;
1231
1232 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1233 bitflips_threshold);
1234 if (extraoob_bitflips < 0)
1235 return extraoob_bitflips;
1236
1237 if (data_bitflips)
1238 memset(data, 0xff, datalen);
1239
1240 if (ecc_bitflips)
1241 memset(ecc, 0xff, ecclen);
1242
1243 if (extraoob_bitflips)
1244 memset(extraoob, 0xff, extraooblen);
1245
1246 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1247}
1248EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1249
8593fbc6 1250/**
7854d3f7 1251 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1252 * @mtd: mtd info structure
1253 * @chip: nand chip info structure
1254 * @buf: buffer to store read data
1fbb938d 1255 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1256 * @page: page number to read
52ff49df 1257 *
7854d3f7 1258 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1259 */
1260static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1261 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1262{
1263 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1264 if (oob_required)
1265 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1266 return 0;
1267}
1268
52ff49df 1269/**
7854d3f7 1270 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1271 * @mtd: mtd info structure
1272 * @chip: nand chip info structure
1273 * @buf: buffer to store read data
1fbb938d 1274 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1275 * @page: page number to read
52ff49df
DB		 1276 *
1277 * We need a special oob layout and handling even when OOB isn't used.
1278 */
7351d3a5 1279static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1280 struct nand_chip *chip, uint8_t *buf,
1281 int oob_required, int page)
52ff49df
DB		 1282{
1283 int eccsize = chip->ecc.size;
1284 int eccbytes = chip->ecc.bytes;
1285 uint8_t *oob = chip->oob_poi;
1286 int steps, size;
1287
1288 for (steps = chip->ecc.steps; steps > 0; steps--) {
1289 chip->read_buf(mtd, buf, eccsize);
1290 buf += eccsize;
1291
1292 if (chip->ecc.prepad) {
1293 chip->read_buf(mtd, oob, chip->ecc.prepad);
1294 oob += chip->ecc.prepad;
1295 }
1296
1297 chip->read_buf(mtd, oob, eccbytes);
1298 oob += eccbytes;
1299
1300 if (chip->ecc.postpad) {
1301 chip->read_buf(mtd, oob, chip->ecc.postpad);
1302 oob += chip->ecc.postpad;
1303 }
1304 }
1305
1306 size = mtd->oobsize - (oob - chip->oob_poi);
1307 if (size)
1308 chip->read_buf(mtd, oob, size);
1309
1310 return 0;
1311}
1312
1da177e4 1313/**
7854d3f7 1314 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1315 * @mtd: mtd info structure
1316 * @chip: nand chip info structure
1317 * @buf: buffer to store read data
1fbb938d 1318 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1319 * @page: page number to read
068e3c0a 1320 */
f5bbdacc 1321static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1322 uint8_t *buf, int oob_required, int page)
1da177e4 1323{
846031d3 1324 int i, eccsize = chip->ecc.size, ret;
f5bbdacc
TG		 1325 int eccbytes = chip->ecc.bytes;
1326 int eccsteps = chip->ecc.steps;
1327 uint8_t *p = buf;
4bf63fcb
DW		 1328 uint8_t *ecc_calc = chip->buffers->ecccalc;
1329 uint8_t *ecc_code = chip->buffers->ecccode;
3f91e94f 1330 unsigned int max_bitflips = 0;
f5bbdacc 1331
1fbb938d 1332 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1333
1334 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1335 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1336
846031d3
BB		 1337 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1338 chip->ecc.total);
1339 if (ret)
1340 return ret;
f5bbdacc
TG		 1341
1342 eccsteps = chip->ecc.steps;
1343 p = buf;
1344
1345 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1346 int stat;
1347
1348 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1349 if (stat < 0) {
f5bbdacc 1350 mtd->ecc_stats.failed++;
3f91e94f 1351 } else {
f5bbdacc 1352 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1353 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1354 }
f5bbdacc 1355 }
3f91e94f 1356 return max_bitflips;
22c60f5f 1357}
1da177e4 1358
3d459559 1359/**
837a6ba4 1360 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1361 * @mtd: mtd info structure
1362 * @chip: nand chip info structure
1363 * @data_offs: offset of requested data within the page
1364 * @readlen: data length
1365 * @bufpoi: buffer to store read data
e004debd 1366 * @page: page number to read
3d459559 1367 */
7351d3a5 1368static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
e004debd
HS		 1369 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1370 int page)
3d459559 1371{
846031d3 1372 int start_step, end_step, num_steps, ret;
3d459559
AK		 1373 uint8_t *p;
1374 int data_col_addr, i, gaps = 0;
1375 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1376 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
846031d3 1377 int index, section = 0;
3f91e94f 1378 unsigned int max_bitflips = 0;
846031d3 1379 struct mtd_oob_region oobregion = { };
3d459559 1380
7854d3f7 1381 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1382 start_step = data_offs / chip->ecc.size;
1383 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1384 num_steps = end_step - start_step + 1;
4a4163ca 1385 index = start_step * chip->ecc.bytes;
3d459559 1386
8b6e50c9 1387 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1388 datafrag_len = num_steps * chip->ecc.size;
1389 eccfrag_len = num_steps * chip->ecc.bytes;
1390
1391 data_col_addr = start_step * chip->ecc.size;
1392 /* If we read not a page aligned data */
1393 if (data_col_addr != 0)
1394 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1395
1396 p = bufpoi + data_col_addr;
1397 chip->read_buf(mtd, p, datafrag_len);
1398
8b6e50c9 1399 /* Calculate ECC */
3d459559
AK		 1400 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1401 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1402
8b6e50c9
BN		 1403 /*
1404 * The performance is faster if we position offsets according to
7854d3f7 1405 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1406 */
846031d3
BB		 1407 ret = mtd_ooblayout_find_eccregion(mtd, index, &section, &oobregion);
1408 if (ret)
1409 return ret;
1410
1411 if (oobregion.length < eccfrag_len)
1412 gaps = 1;
1413
3d459559
AK		 1414 if (gaps) {
1415 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1416 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1417 } else {
8b6e50c9 1418 /*
7854d3f7 1419 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1420 * about buswidth alignment in read_buf.
1421 */
846031d3 1422 aligned_pos = oobregion.offset & ~(busw - 1);
3d459559 1423 aligned_len = eccfrag_len;
846031d3 1424 if (oobregion.offset & (busw - 1))
3d459559 1425 aligned_len++;
846031d3
BB		 1426 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
1427 (busw - 1))
3d459559
AK		 1428 aligned_len++;
1429
7351d3a5 1430 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
846031d3 1431 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1432 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1433 }
1434
846031d3
BB		 1435 ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode,
1436 chip->oob_poi, index, eccfrag_len);
1437 if (ret)
1438 return ret;
3d459559
AK		 1439
1440 p = bufpoi + data_col_addr;
1441 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1442 int stat;
1443
7351d3a5
FF		 1444 stat = chip->ecc.correct(mtd, p,
1445 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
40cbe6ee
BB		 1446 if (stat == -EBADMSG &&
1447 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1448 /* check for empty pages with bitflips */
1449 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1450 &chip->buffers->ecccode[i],
1451 chip->ecc.bytes,
1452 NULL, 0,
1453 chip->ecc.strength);
1454 }
1455
3f91e94f 1456 if (stat < 0) {
3d459559 1457 mtd->ecc_stats.failed++;
3f91e94f 1458 } else {
3d459559 1459 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1460 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1461 }
3d459559 1462 }
3f91e94f 1463 return max_bitflips;
3d459559
AK		 1464}
1465
068e3c0a 1466/**
7854d3f7 1467 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1468 * @mtd: mtd info structure
1469 * @chip: nand chip info structure
1470 * @buf: buffer to store read data
1fbb938d 1471 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1472 * @page: page number to read
068e3c0a 1473 *
7854d3f7 1474 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1475 */
f5bbdacc 1476static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1477 uint8_t *buf, int oob_required, int page)
1da177e4 1478{
846031d3 1479 int i, eccsize = chip->ecc.size, ret;
f5bbdacc
TG		 1480 int eccbytes = chip->ecc.bytes;
1481 int eccsteps = chip->ecc.steps;
1482 uint8_t *p = buf;
4bf63fcb
DW		 1483 uint8_t *ecc_calc = chip->buffers->ecccalc;
1484 uint8_t *ecc_code = chip->buffers->ecccode;
3f91e94f 1485 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1486
1487 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1488 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1489 chip->read_buf(mtd, p, eccsize);
1490 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1491 }
f75e5097 1492 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1493
846031d3
BB		 1494 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1495 chip->ecc.total);
1496 if (ret)
1497 return ret;
1da177e4 1498
f5bbdacc
TG		 1499 eccsteps = chip->ecc.steps;
1500 p = buf;
61b03bd7 1501
f5bbdacc
TG		 1502 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1503 int stat;
1da177e4 1504
f5bbdacc 1505 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
40cbe6ee
BB		 1506 if (stat == -EBADMSG &&
1507 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1508 /* check for empty pages with bitflips */
1509 stat = nand_check_erased_ecc_chunk(p, eccsize,
1510 &ecc_code[i], eccbytes,
1511 NULL, 0,
1512 chip->ecc.strength);
1513 }
1514
3f91e94f 1515 if (stat < 0) {
f5bbdacc 1516 mtd->ecc_stats.failed++;
3f91e94f 1517 } else {
f5bbdacc 1518 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1519 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1520 }
f5bbdacc 1521 }
3f91e94f 1522 return max_bitflips;
f5bbdacc 1523}
1da177e4 1524
6e0cb135 1525/**
7854d3f7 1526 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1527 * @mtd: mtd info structure
1528 * @chip: nand chip info structure
1529 * @buf: buffer to store read data
1fbb938d 1530 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1531 * @page: page number to read
6e0cb135 1532 *
8b6e50c9
BN		 1533 * Hardware ECC for large page chips, require OOB to be read first. For this
1534 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1535 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1536 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1537 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1538 */
1539static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1540 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135 1541{
846031d3 1542 int i, eccsize = chip->ecc.size, ret;
6e0cb135
SN		 1543 int eccbytes = chip->ecc.bytes;
1544 int eccsteps = chip->ecc.steps;
1545 uint8_t *p = buf;
1546 uint8_t *ecc_code = chip->buffers->ecccode;
6e0cb135 1547 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1548 unsigned int max_bitflips = 0;
6e0cb135
SN		 1549
1550 /* Read the OOB area first */
1551 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1552 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1553 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1554
846031d3
BB		 1555 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1556 chip->ecc.total);
1557 if (ret)
1558 return ret;
6e0cb135
SN		 1559
1560 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1561 int stat;
1562
1563 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1564 chip->read_buf(mtd, p, eccsize);
1565 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1566
1567 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
40cbe6ee
BB		 1568 if (stat == -EBADMSG &&
1569 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1570 /* check for empty pages with bitflips */
1571 stat = nand_check_erased_ecc_chunk(p, eccsize,
1572 &ecc_code[i], eccbytes,
1573 NULL, 0,
1574 chip->ecc.strength);
1575 }
1576
3f91e94f 1577 if (stat < 0) {
6e0cb135 1578 mtd->ecc_stats.failed++;
3f91e94f 1579 } else {
6e0cb135 1580 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1581 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1582 }
6e0cb135 1583 }
3f91e94f 1584 return max_bitflips;
6e0cb135
SN		 1585}
1586
f5bbdacc 1587/**
7854d3f7 1588 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1589 * @mtd: mtd info structure
1590 * @chip: nand chip info structure
1591 * @buf: buffer to store read data
1fbb938d 1592 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1593 * @page: page number to read
f5bbdacc 1594 *
8b6e50c9
BN		 1595 * The hw generator calculates the error syndrome automatically. Therefore we
1596 * need a special oob layout and handling.
f5bbdacc
TG		 1597 */
1598static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1599 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1600{
1601 int i, eccsize = chip->ecc.size;
1602 int eccbytes = chip->ecc.bytes;
1603 int eccsteps = chip->ecc.steps;
40cbe6ee 1604 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
f5bbdacc 1605 uint8_t *p = buf;
f75e5097 1606 uint8_t *oob = chip->oob_poi;
3f91e94f 1607 unsigned int max_bitflips = 0;
1da177e4 1608
f5bbdacc
TG		 1609 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1610 int stat;
61b03bd7 1611
f5bbdacc
TG		 1612 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1613 chip->read_buf(mtd, p, eccsize);
1da177e4 1614
f5bbdacc
TG		 1615 if (chip->ecc.prepad) {
1616 chip->read_buf(mtd, oob, chip->ecc.prepad);
1617 oob += chip->ecc.prepad;
1618 }
1da177e4 1619
f5bbdacc
TG		 1620 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1621 chip->read_buf(mtd, oob, eccbytes);
1622 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1623
f5bbdacc 1624 oob += eccbytes;
1da177e4 1625
f5bbdacc
TG		 1626 if (chip->ecc.postpad) {
1627 chip->read_buf(mtd, oob, chip->ecc.postpad);
1628 oob += chip->ecc.postpad;
61b03bd7 1629 }
40cbe6ee
BB		 1630
1631 if (stat == -EBADMSG &&
1632 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1633 /* check for empty pages with bitflips */
1634 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1635 oob - eccpadbytes,
1636 eccpadbytes,
1637 NULL, 0,
1638 chip->ecc.strength);
1639 }
1640
1641 if (stat < 0) {
1642 mtd->ecc_stats.failed++;
1643 } else {
1644 mtd->ecc_stats.corrected += stat;
1645 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1646 }
f5bbdacc 1647 }
1da177e4 1648
f5bbdacc 1649 /* Calculate remaining oob bytes */
7e4178f9 1650 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1651 if (i)
1652 chip->read_buf(mtd, oob, i);
61b03bd7 1653
3f91e94f 1654 return max_bitflips;
f5bbdacc 1655}
1da177e4 1656
f5bbdacc 1657/**
7854d3f7 1658 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
846031d3 1659 * @mtd: mtd info structure
8b6e50c9
BN		 1660 * @oob: oob destination address
1661 * @ops: oob ops structure
1662 * @len: size of oob to transfer
8593fbc6 1663 */
846031d3 1664static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob,
7014568b 1665 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1666{
846031d3
BB		 1667 struct nand_chip *chip = mtd_to_nand(mtd);
1668 int ret;
1669
f8ac0414 1670 switch (ops->mode) {
8593fbc6 1671
0612b9dd
BN		 1672 case MTD_OPS_PLACE_OOB:
1673 case MTD_OPS_RAW:
8593fbc6
TG		 1674 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1675 return oob + len;
1676
846031d3
BB		 1677 case MTD_OPS_AUTO_OOB:
1678 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
1679 ops->ooboffs, len);
1680 BUG_ON(ret);
1681 return oob + len;
1682
8593fbc6
TG		 1683 default:
1684 BUG();
1685 }
1686 return NULL;
1687}
1688
ba84fb59
BN		 1689/**
1690 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1691 * @mtd: MTD device structure
1692 * @retry_mode: the retry mode to use
1693 *
1694 * Some vendors supply a special command to shift the Vt threshold, to be used
1695 * when there are too many bitflips in a page (i.e., ECC error). After setting
1696 * a new threshold, the host should retry reading the page.
1697 */
1698static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1699{
862eba51 1700 struct nand_chip *chip = mtd_to_nand(mtd);
ba84fb59
BN		 1701
1702 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1703
1704 if (retry_mode >= chip->read_retries)
1705 return -EINVAL;
1706
1707 if (!chip->setup_read_retry)
1708 return -EOPNOTSUPP;
1709
1710 return chip->setup_read_retry(mtd, retry_mode);
1711}
1712
8593fbc6 1713/**
7854d3f7 1714 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1715 * @mtd: MTD device structure
1716 * @from: offset to read from
1717 * @ops: oob ops structure
f5bbdacc
TG		 1718 *
1719 * Internal function. Called with chip held.
1720 */
8593fbc6
TG		 1721static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1722 struct mtd_oob_ops *ops)
f5bbdacc 1723{
e47f3db4 1724 int chipnr, page, realpage, col, bytes, aligned, oob_required;
862eba51 1725 struct nand_chip *chip = mtd_to_nand(mtd);
f5bbdacc 1726 int ret = 0;
8593fbc6 1727 uint32_t readlen = ops->len;
7014568b 1728 uint32_t oobreadlen = ops->ooblen;
29f1058a 1729 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
9aca334e 1730
8593fbc6 1731 uint8_t *bufpoi, *oob, *buf;
66507c7b 1732 int use_bufpoi;
edbc4540 1733 unsigned int max_bitflips = 0;
ba84fb59 1734 int retry_mode = 0;
b72f3dfb 1735 bool ecc_fail = false;
1da177e4 1736
f5bbdacc
TG		 1737 chipnr = (int)(from >> chip->chip_shift);
1738 chip->select_chip(mtd, chipnr);
61b03bd7 1739
f5bbdacc
TG		 1740 realpage = (int)(from >> chip->page_shift);
1741 page = realpage & chip->pagemask;
1da177e4 1742
f5bbdacc 1743 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1744
8593fbc6
TG		 1745 buf = ops->datbuf;
1746 oob = ops->oobbuf;
e47f3db4 1747 oob_required = oob ? 1 : 0;
8593fbc6 1748
f8ac0414 1749 while (1) {
b72f3dfb
BN		 1750 unsigned int ecc_failures = mtd->ecc_stats.failed;
1751
f5bbdacc
TG		 1752 bytes = min(mtd->writesize - col, readlen);
1753 aligned = (bytes == mtd->writesize);
61b03bd7 1754
66507c7b
KD		 1755 if (!aligned)
1756 use_bufpoi = 1;
1757 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1758 use_bufpoi = !virt_addr_valid(buf);
1759 else
1760 use_bufpoi = 0;
1761
8b6e50c9 1762 /* Is the current page in the buffer? */
8593fbc6 1763 if (realpage != chip->pagebuf || oob) {
66507c7b
KD		 1764 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1765
1766 if (use_bufpoi && aligned)
1767 pr_debug("%s: using read bounce buffer for buf@%p\n",
1768 __func__, buf);
61b03bd7 1769
ba84fb59 1770read_retry:
c00a0991 1771 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1772
edbc4540
MD		 1773 /*
1774 * Now read the page into the buffer. Absent an error,
1775 * the read methods return max bitflips per ecc step.
1776 */
0612b9dd 1777 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1778 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1779 oob_required,
1780 page);
a5ff4f10
JW		 1781 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1782 !oob)
7351d3a5 1783 ret = chip->ecc.read_subpage(mtd, chip,
e004debd
HS		 1784 col, bytes, bufpoi,
1785 page);
956e944c 1786 else
46a8cf2d 1787 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1788 oob_required, page);
6d77b9d0 1789 if (ret < 0) {
66507c7b 1790 if (use_bufpoi)
6d77b9d0
BN		 1791 /* Invalidate page cache */
1792 chip->pagebuf = -1;
1da177e4 1793 break;
6d77b9d0 1794 }
f5bbdacc 1795
edbc4540
MD		 1796 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1797
f5bbdacc 1798 /* Transfer not aligned data */
66507c7b 1799 if (use_bufpoi) {
a5ff4f10 1800 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
b72f3dfb 1801 !(mtd->ecc_stats.failed - ecc_failures) &&
edbc4540 1802 (ops->mode != MTD_OPS_RAW)) {
3d459559 1803 chip->pagebuf = realpage;
edbc4540
MD		 1804 chip->pagebuf_bitflips = ret;
1805 } else {
6d77b9d0
BN		 1806 /* Invalidate page cache */
1807 chip->pagebuf = -1;
edbc4540 1808 }
4bf63fcb 1809 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1810 }
1811
8593fbc6 1812 if (unlikely(oob)) {
b64d39d8
ML		 1813 int toread = min(oobreadlen, max_oobsize);
1814
1815 if (toread) {
846031d3 1816 oob = nand_transfer_oob(mtd,
b64d39d8
ML		 1817 oob, ops, toread);
1818 oobreadlen -= toread;
1819 }
8593fbc6 1820 }
5bc7c33c
BN		 1821
1822 if (chip->options & NAND_NEED_READRDY) {
1823 /* Apply delay or wait for ready/busy pin */
1824 if (!chip->dev_ready)
1825 udelay(chip->chip_delay);
1826 else
1827 nand_wait_ready(mtd);
1828 }
b72f3dfb 1829
ba84fb59 1830 if (mtd->ecc_stats.failed - ecc_failures) {
28fa65e6 1831 if (retry_mode + 1 < chip->read_retries) {
ba84fb59
BN		 1832 retry_mode++;
1833 ret = nand_setup_read_retry(mtd,
1834 retry_mode);
1835 if (ret < 0)
1836 break;
1837
1838 /* Reset failures; retry */
1839 mtd->ecc_stats.failed = ecc_failures;
1840 goto read_retry;
1841 } else {
1842 /* No more retry modes; real failure */
1843 ecc_fail = true;
1844 }
1845 }
1846
1847 buf += bytes;
8593fbc6 1848 } else {
4bf63fcb 1849 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1850 buf += bytes;
edbc4540
MD		 1851 max_bitflips = max_t(unsigned int, max_bitflips,
1852 chip->pagebuf_bitflips);
8593fbc6 1853 }
1da177e4 1854
f5bbdacc 1855 readlen -= bytes;
61b03bd7 1856
ba84fb59
BN		 1857 /* Reset to retry mode 0 */
1858 if (retry_mode) {
1859 ret = nand_setup_read_retry(mtd, 0);
1860 if (ret < 0)
1861 break;
1862 retry_mode = 0;
1863 }
1864
f5bbdacc 1865 if (!readlen)
61b03bd7 1866 break;
1da177e4 1867
8b6e50c9 1868 /* For subsequent reads align to page boundary */
1da177e4
LT		 1869 col = 0;
1870 /* Increment page address */
1871 realpage++;
1872
ace4dfee 1873 page = realpage & chip->pagemask;
1da177e4
LT		 1874 /* Check, if we cross a chip boundary */
1875 if (!page) {
1876 chipnr++;
ace4dfee
TG		 1877 chip->select_chip(mtd, -1);
1878 chip->select_chip(mtd, chipnr);
1da177e4 1879 }
1da177e4 1880 }
b0bb6903 1881 chip->select_chip(mtd, -1);
1da177e4 1882
8593fbc6 1883 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1884 if (oob)
1885 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1886
3f91e94f 1887 if (ret < 0)
f5bbdacc
TG		 1888 return ret;
1889
b72f3dfb 1890 if (ecc_fail)
9a1fcdfd
TG		 1891 return -EBADMSG;
1892
edbc4540 1893 return max_bitflips;
f5bbdacc
TG		 1894}
1895
1896/**
25985edc 1897 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1898 * @mtd: MTD device structure
1899 * @from: offset to read from
1900 * @len: number of bytes to read
1901 * @retlen: pointer to variable to store the number of read bytes
1902 * @buf: the databuffer to put data
f5bbdacc 1903 *
8b6e50c9 1904 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1905 */
1906static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1907 size_t *retlen, uint8_t *buf)
1908{
4a89ff88 1909 struct mtd_oob_ops ops;
f5bbdacc
TG		 1910 int ret;
1911
6a8214aa 1912 nand_get_device(mtd, FL_READING);
0ec56dc4 1913 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 1914 ops.len = len;
1915 ops.datbuf = buf;
11041ae6 1916 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1917 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1918 *retlen = ops.retlen;
f5bbdacc 1919 nand_release_device(mtd);
f5bbdacc 1920 return ret;
1da177e4
LT		 1921}
1922
7bc3312b 1923/**
7854d3f7 1924 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1925 * @mtd: mtd info structure
1926 * @chip: nand chip info structure
1927 * @page: page number to read
7bc3312b 1928 */
9d02fc2a 1929int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
7bc3312b 1930{
5c2ffb11 1931 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1932 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1933 return 0;
7bc3312b 1934}
9d02fc2a 1935EXPORT_SYMBOL(nand_read_oob_std);
7bc3312b
TG		 1936
1937/**
7854d3f7 1938 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1939 * with syndromes
8b6e50c9
BN		 1940 * @mtd: mtd info structure
1941 * @chip: nand chip info structure
1942 * @page: page number to read
7bc3312b 1943 */
9d02fc2a
BB		 1944int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1945 int page)
7bc3312b 1946{
7bc3312b
TG		 1947 int length = mtd->oobsize;
1948 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1949 int eccsize = chip->ecc.size;
2ea69d21 1950 uint8_t *bufpoi = chip->oob_poi;
7bc3312b
TG		 1951 int i, toread, sndrnd = 0, pos;
1952
1953 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1954 for (i = 0; i < chip->ecc.steps; i++) {
1955 if (sndrnd) {
1956 pos = eccsize + i * (eccsize + chunk);
1957 if (mtd->writesize > 512)
1958 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1959 else
1960 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1961 } else
1962 sndrnd = 1;
1963 toread = min_t(int, length, chunk);
1964 chip->read_buf(mtd, bufpoi, toread);
1965 bufpoi += toread;
1966 length -= toread;
1967 }
1968 if (length > 0)
1969 chip->read_buf(mtd, bufpoi, length);
1970
5c2ffb11 1971 return 0;
7bc3312b 1972}
9d02fc2a 1973EXPORT_SYMBOL(nand_read_oob_syndrome);
7bc3312b
TG		 1974
1975/**
7854d3f7 1976 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1977 * @mtd: mtd info structure
1978 * @chip: nand chip info structure
1979 * @page: page number to write
7bc3312b 1980 */
9d02fc2a 1981int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
7bc3312b
TG		 1982{
1983 int status = 0;
1984 const uint8_t *buf = chip->oob_poi;
1985 int length = mtd->oobsize;
1986
1987 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1988 chip->write_buf(mtd, buf, length);
1989 /* Send command to program the OOB data */
1990 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1991
1992 status = chip->waitfunc(mtd, chip);
1993
0d420f9d 1994 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b 1995}
9d02fc2a 1996EXPORT_SYMBOL(nand_write_oob_std);
7bc3312b
TG		 1997
1998/**
7854d3f7 1999 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 2000 * with syndrome - only for large page flash
2001 * @mtd: mtd info structure
2002 * @chip: nand chip info structure
2003 * @page: page number to write
7bc3312b 2004 */
9d02fc2a
BB		 2005int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2006 int page)
7bc3312b
TG		 2007{
2008 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2009 int eccsize = chip->ecc.size, length = mtd->oobsize;
2010 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
2011 const uint8_t *bufpoi = chip->oob_poi;
2012
2013 /*
2014 * data-ecc-data-ecc ... ecc-oob
2015 * or
2016 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2017 */
2018 if (!chip->ecc.prepad && !chip->ecc.postpad) {
2019 pos = steps * (eccsize + chunk);
2020 steps = 0;
2021 } else
8b0036ee 2022 pos = eccsize;
7bc3312b
TG		 2023
2024 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
2025 for (i = 0; i < steps; i++) {
2026 if (sndcmd) {
2027 if (mtd->writesize <= 512) {
2028 uint32_t fill = 0xFFFFFFFF;
2029
2030 len = eccsize;
2031 while (len > 0) {
2032 int num = min_t(int, len, 4);
2033 chip->write_buf(mtd, (uint8_t *)&fill,
2034 num);
2035 len -= num;
2036 }
2037 } else {
2038 pos = eccsize + i * (eccsize + chunk);
2039 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2040 }
2041 } else
2042 sndcmd = 1;
2043 len = min_t(int, length, chunk);
2044 chip->write_buf(mtd, bufpoi, len);
2045 bufpoi += len;
2046 length -= len;
2047 }
2048 if (length > 0)
2049 chip->write_buf(mtd, bufpoi, length);
2050
2051 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2052 status = chip->waitfunc(mtd, chip);
2053
2054 return status & NAND_STATUS_FAIL ? -EIO : 0;
2055}
9d02fc2a 2056EXPORT_SYMBOL(nand_write_oob_syndrome);
7bc3312b 2057
1da177e4 2058/**
7854d3f7 2059 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 2060 * @mtd: MTD device structure
2061 * @from: offset to read from
2062 * @ops: oob operations description structure
1da177e4 2063 *
8b6e50c9 2064 * NAND read out-of-band data from the spare area.
1da177e4 2065 */
8593fbc6
TG		 2066static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2067 struct mtd_oob_ops *ops)
1da177e4 2068{
c00a0991 2069 int page, realpage, chipnr;
862eba51 2070 struct nand_chip *chip = mtd_to_nand(mtd);
041e4575 2071 struct mtd_ecc_stats stats;
7014568b
VW		 2072 int readlen = ops->ooblen;
2073 int len;
7bc3312b 2074 uint8_t *buf = ops->oobbuf;
1951f2f7 2075 int ret = 0;
61b03bd7 2076
289c0522 2077 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 2078 __func__, (unsigned long long)from, readlen);
1da177e4 2079
041e4575
BN		 2080 stats = mtd->ecc_stats;
2081
29f1058a 2082 len = mtd_oobavail(mtd, ops);
03736155
AH		 2083
2084 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2085 pr_debug("%s: attempt to start read outside oob\n",
2086 __func__);
03736155
AH		 2087 return -EINVAL;
2088 }
2089
2090 /* Do not allow reads past end of device */
2091 if (unlikely(from >= mtd->size ||
2092 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2093 (from >> chip->page_shift)) * len)) {
289c0522
BN		 2094 pr_debug("%s: attempt to read beyond end of device\n",
2095 __func__);
03736155
AH		 2096 return -EINVAL;
2097 }
7014568b 2098
7314e9e7 2099 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 2100 chip->select_chip(mtd, chipnr);
1da177e4 2101
7314e9e7
TG		 2102 /* Shift to get page */
2103 realpage = (int)(from >> chip->page_shift);
2104 page = realpage & chip->pagemask;
1da177e4 2105
f8ac0414 2106 while (1) {
0612b9dd 2107 if (ops->mode == MTD_OPS_RAW)
1951f2f7 2108 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 2109 else
1951f2f7
SL		 2110 ret = chip->ecc.read_oob(mtd, chip, page);
2111
2112 if (ret < 0)
2113 break;
7014568b
VW		 2114
2115 len = min(len, readlen);
846031d3 2116 buf = nand_transfer_oob(mtd, buf, ops, len);
8593fbc6 2117
5bc7c33c
BN		 2118 if (chip->options & NAND_NEED_READRDY) {
2119 /* Apply delay or wait for ready/busy pin */
2120 if (!chip->dev_ready)
2121 udelay(chip->chip_delay);
2122 else
2123 nand_wait_ready(mtd);
2124 }
2125
7014568b 2126 readlen -= len;
0d420f9d
SZ		 2127 if (!readlen)
2128 break;
2129
7314e9e7
TG		 2130 /* Increment page address */
2131 realpage++;
2132
2133 page = realpage & chip->pagemask;
2134 /* Check, if we cross a chip boundary */
2135 if (!page) {
2136 chipnr++;
2137 chip->select_chip(mtd, -1);
2138 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2139 }
2140 }
b0bb6903 2141 chip->select_chip(mtd, -1);
1da177e4 2142
1951f2f7
SL		 2143 ops->oobretlen = ops->ooblen - readlen;
2144
2145 if (ret < 0)
2146 return ret;
041e4575
BN		 2147
2148 if (mtd->ecc_stats.failed - stats.failed)
2149 return -EBADMSG;
2150
2151 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 2152}
2153
2154/**
8593fbc6 2155 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 2156 * @mtd: MTD device structure
2157 * @from: offset to read from
2158 * @ops: oob operation description structure
1da177e4 2159 *
8b6e50c9 2160 * NAND read data and/or out-of-band data.
1da177e4 2161 */
8593fbc6
TG		 2162static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2163 struct mtd_oob_ops *ops)
1da177e4 2164{
4ae1f3a6 2165 int ret;
8593fbc6
TG		 2166
2167 ops->retlen = 0;
1da177e4
LT		 2168
2169 /* Do not allow reads past end of device */
7014568b 2170 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 2171 pr_debug("%s: attempt to read beyond end of device\n",
2172 __func__);
1da177e4
LT		 2173 return -EINVAL;
2174 }
2175
4ae1f3a6
AS		 2176 if (ops->mode != MTD_OPS_PLACE_OOB &&
2177 ops->mode != MTD_OPS_AUTO_OOB &&
2178 ops->mode != MTD_OPS_RAW)
2179 return -ENOTSUPP;
1da177e4 2180
4ae1f3a6 2181 nand_get_device(mtd, FL_READING);
1da177e4 2182
8593fbc6
TG		 2183 if (!ops->datbuf)
2184 ret = nand_do_read_oob(mtd, from, ops);
2185 else
2186 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 2187
8593fbc6
TG		 2188 nand_release_device(mtd);
2189 return ret;
2190}
61b03bd7 2191
1da177e4 2192
8593fbc6 2193/**
7854d3f7 2194 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 2195 * @mtd: mtd info structure
2196 * @chip: nand chip info structure
2197 * @buf: data buffer
1fbb938d 2198 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2199 * @page: page number to write
52ff49df 2200 *
7854d3f7 2201 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 2202 */
fdbad98d 2203static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9 2204 const uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 2205{
2206 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 2207 if (oob_required)
2208 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2209
2210 return 0;
1da177e4
LT		 2211}
2212
52ff49df 2213/**
7854d3f7 2214 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 2215 * @mtd: mtd info structure
2216 * @chip: nand chip info structure
2217 * @buf: data buffer
1fbb938d 2218 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2219 * @page: page number to write
52ff49df
DB		 2220 *
2221 * We need a special oob layout and handling even when ECC isn't checked.
2222 */
fdbad98d 2223static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 2224 struct nand_chip *chip,
45aaeff9
BB		 2225 const uint8_t *buf, int oob_required,
2226 int page)
52ff49df
DB		 2227{
2228 int eccsize = chip->ecc.size;
2229 int eccbytes = chip->ecc.bytes;
2230 uint8_t *oob = chip->oob_poi;
2231 int steps, size;
2232
2233 for (steps = chip->ecc.steps; steps > 0; steps--) {
2234 chip->write_buf(mtd, buf, eccsize);
2235 buf += eccsize;
2236
2237 if (chip->ecc.prepad) {
2238 chip->write_buf(mtd, oob, chip->ecc.prepad);
2239 oob += chip->ecc.prepad;
2240 }
2241
60c3bc1f 2242 chip->write_buf(mtd, oob, eccbytes);
52ff49df
DB		 2243 oob += eccbytes;
2244
2245 if (chip->ecc.postpad) {
2246 chip->write_buf(mtd, oob, chip->ecc.postpad);
2247 oob += chip->ecc.postpad;
2248 }
2249 }
2250
2251 size = mtd->oobsize - (oob - chip->oob_poi);
2252 if (size)
2253 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 2254
2255 return 0;
52ff49df 2256}
9223a456 2257/**
7854d3f7 2258 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 2259 * @mtd: mtd info structure
2260 * @chip: nand chip info structure
2261 * @buf: data buffer
1fbb938d 2262 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2263 * @page: page number to write
9223a456 2264 */
fdbad98d 2265static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9
BB		 2266 const uint8_t *buf, int oob_required,
2267 int page)
9223a456 2268{
846031d3 2269 int i, eccsize = chip->ecc.size, ret;
f75e5097
TG		 2270 int eccbytes = chip->ecc.bytes;
2271 int eccsteps = chip->ecc.steps;
4bf63fcb 2272 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2273 const uint8_t *p = buf;
9223a456 2274
7854d3f7 2275 /* Software ECC calculation */
8593fbc6
TG		 2276 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2277 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 2278
846031d3
BB		 2279 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2280 chip->ecc.total);
2281 if (ret)
2282 return ret;
9223a456 2283
45aaeff9 2284 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
f75e5097 2285}
9223a456 2286
f75e5097 2287/**
7854d3f7 2288 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2289 * @mtd: mtd info structure
2290 * @chip: nand chip info structure
2291 * @buf: data buffer
1fbb938d 2292 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2293 * @page: page number to write
f75e5097 2294 */
fdbad98d 2295static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9
BB		 2296 const uint8_t *buf, int oob_required,
2297 int page)
f75e5097 2298{
846031d3 2299 int i, eccsize = chip->ecc.size, ret;
f75e5097
TG		 2300 int eccbytes = chip->ecc.bytes;
2301 int eccsteps = chip->ecc.steps;
4bf63fcb 2302 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2303 const uint8_t *p = buf;
9223a456 2304
f75e5097
TG		 2305 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2306 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2307 chip->write_buf(mtd, p, eccsize);
f75e5097 2308 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2309 }
2310
846031d3
BB		 2311 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2312 chip->ecc.total);
2313 if (ret)
2314 return ret;
f75e5097
TG		 2315
2316 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2317
2318 return 0;
9223a456
TG		 2319}
2320
837a6ba4
GP		 2321
2322/**
73c8aaf4 2323 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
837a6ba4
GP		 2324 * @mtd: mtd info structure
2325 * @chip: nand chip info structure
d6a95080 2326 * @offset: column address of subpage within the page
837a6ba4 2327 * @data_len: data length
d6a95080 2328 * @buf: data buffer
837a6ba4 2329 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2330 * @page: page number to write
837a6ba4
GP		 2331 */
2332static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2333 struct nand_chip *chip, uint32_t offset,
d6a95080 2334 uint32_t data_len, const uint8_t *buf,
45aaeff9 2335 int oob_required, int page)
837a6ba4
GP		 2336{
2337 uint8_t *oob_buf = chip->oob_poi;
2338 uint8_t *ecc_calc = chip->buffers->ecccalc;
2339 int ecc_size = chip->ecc.size;
2340 int ecc_bytes = chip->ecc.bytes;
2341 int ecc_steps = chip->ecc.steps;
837a6ba4
GP		 2342 uint32_t start_step = offset / ecc_size;
2343 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2344 int oob_bytes = mtd->oobsize / ecc_steps;
846031d3 2345 int step, ret;
837a6ba4
GP		 2346
2347 for (step = 0; step < ecc_steps; step++) {
2348 /* configure controller for WRITE access */
2349 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2350
2351 /* write data (untouched subpages already masked by 0xFF) */
d6a95080 2352 chip->write_buf(mtd, buf, ecc_size);
837a6ba4
GP		 2353
2354 /* mask ECC of un-touched subpages by padding 0xFF */
2355 if ((step < start_step) || (step > end_step))
2356 memset(ecc_calc, 0xff, ecc_bytes);
2357 else
d6a95080 2358 chip->ecc.calculate(mtd, buf, ecc_calc);
837a6ba4
GP		 2359
2360 /* mask OOB of un-touched subpages by padding 0xFF */
2361 /* if oob_required, preserve OOB metadata of written subpage */
2362 if (!oob_required || (step < start_step) || (step > end_step))
2363 memset(oob_buf, 0xff, oob_bytes);
2364
d6a95080 2365 buf += ecc_size;
837a6ba4
GP		 2366 ecc_calc += ecc_bytes;
2367 oob_buf += oob_bytes;
2368 }
2369
2370 /* copy calculated ECC for whole page to chip->buffer->oob */
2371 /* this include masked-value(0xFF) for unwritten subpages */
2372 ecc_calc = chip->buffers->ecccalc;
846031d3
BB		 2373 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2374 chip->ecc.total);
2375 if (ret)
2376 return ret;
837a6ba4
GP		 2377
2378 /* write OOB buffer to NAND device */
2379 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2380
2381 return 0;
2382}
2383
2384
61b03bd7 2385/**
7854d3f7 2386 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2387 * @mtd: mtd info structure
2388 * @chip: nand chip info structure
2389 * @buf: data buffer
1fbb938d 2390 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2391 * @page: page number to write
1da177e4 2392 *
8b6e50c9
BN		 2393 * The hw generator calculates the error syndrome automatically. Therefore we
2394 * need a special oob layout and handling.
f75e5097 2395 */
fdbad98d 2396static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d 2397 struct nand_chip *chip,
45aaeff9
BB		 2398 const uint8_t *buf, int oob_required,
2399 int page)
1da177e4 2400{
f75e5097
TG		 2401 int i, eccsize = chip->ecc.size;
2402 int eccbytes = chip->ecc.bytes;
2403 int eccsteps = chip->ecc.steps;
2404 const uint8_t *p = buf;
2405 uint8_t *oob = chip->oob_poi;
1da177e4 2406
f75e5097 2407 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2408
f75e5097
TG		 2409 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2410 chip->write_buf(mtd, p, eccsize);
61b03bd7 2411
f75e5097
TG		 2412 if (chip->ecc.prepad) {
2413 chip->write_buf(mtd, oob, chip->ecc.prepad);
2414 oob += chip->ecc.prepad;
2415 }
2416
2417 chip->ecc.calculate(mtd, p, oob);
2418 chip->write_buf(mtd, oob, eccbytes);
2419 oob += eccbytes;
2420
2421 if (chip->ecc.postpad) {
2422 chip->write_buf(mtd, oob, chip->ecc.postpad);
2423 oob += chip->ecc.postpad;
1da177e4 2424 }
1da177e4 2425 }
f75e5097
TG		 2426
2427 /* Calculate remaining oob bytes */
7e4178f9 2428 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2429 if (i)
2430 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2431
2432 return 0;
f75e5097
TG		 2433}
2434
2435/**
956e944c 2436 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2437 * @mtd: MTD device structure
2438 * @chip: NAND chip descriptor
837a6ba4
GP		 2439 * @offset: address offset within the page
2440 * @data_len: length of actual data to be written
8b6e50c9 2441 * @buf: the data to write
1fbb938d 2442 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2443 * @page: page number to write
2444 * @cached: cached programming
2445 * @raw: use _raw version of write_page
f75e5097
TG		 2446 */
2447static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4
GP		 2448 uint32_t offset, int data_len, const uint8_t *buf,
2449 int oob_required, int page, int cached, int raw)
f75e5097 2450{
837a6ba4
GP		 2451 int status, subpage;
2452
2453 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2454 chip->ecc.write_subpage)
2455 subpage = offset || (data_len < mtd->writesize);
2456 else
2457 subpage = 0;
f75e5097
TG		 2458
2459 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2460
956e944c 2461 if (unlikely(raw))
837a6ba4 2462 status = chip->ecc.write_page_raw(mtd, chip, buf,
45aaeff9 2463 oob_required, page);
837a6ba4
GP		 2464 else if (subpage)
2465 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
45aaeff9 2466 buf, oob_required, page);
956e944c 2467 else
45aaeff9
BB		 2468 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2469 page);
fdbad98d
JW		 2470
2471 if (status < 0)
2472 return status;
f75e5097
TG		 2473
2474 /*
7854d3f7 2475 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2476 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2477 */
2478 cached = 0;
2479
3239a6cd 2480 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2481
2482 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2483 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2484 /*
2485 * See if operation failed and additional status checks are
8b6e50c9 2486 * available.
f75e5097
TG		 2487 */
2488 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2489 status = chip->errstat(mtd, chip, FL_WRITING, status,
2490 page);
2491
2492 if (status & NAND_STATUS_FAIL)
2493 return -EIO;
2494 } else {
2495 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2496 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2497 }
2498
f75e5097 2499 return 0;
1da177e4
LT		 2500}
2501
8593fbc6 2502/**
7854d3f7 2503 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2504 * @mtd: MTD device structure
8b6e50c9
BN		 2505 * @oob: oob data buffer
2506 * @len: oob data write length
2507 * @ops: oob ops structure
8593fbc6 2508 */
f722013e
TAA		 2509static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2510 struct mtd_oob_ops *ops)
8593fbc6 2511{
862eba51 2512 struct nand_chip *chip = mtd_to_nand(mtd);
846031d3 2513 int ret;
f722013e
TAA		 2514
2515 /*
2516 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2517 * data from a previous OOB read.
2518 */
2519 memset(chip->oob_poi, 0xff, mtd->oobsize);
2520
f8ac0414 2521 switch (ops->mode) {
8593fbc6 2522
0612b9dd
BN		 2523 case MTD_OPS_PLACE_OOB:
2524 case MTD_OPS_RAW:
8593fbc6
TG		 2525 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2526 return oob + len;
2527
846031d3
BB		 2528 case MTD_OPS_AUTO_OOB:
2529 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
2530 ops->ooboffs, len);
2531 BUG_ON(ret);
2532 return oob + len;
2533
8593fbc6
TG		 2534 default:
2535 BUG();
2536 }
2537 return NULL;
2538}
2539
f8ac0414 2540#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2541
2542/**
7854d3f7 2543 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2544 * @mtd: MTD device structure
2545 * @to: offset to write to
2546 * @ops: oob operations description structure
1da177e4 2547 *
8b6e50c9 2548 * NAND write with ECC.
1da177e4 2549 */
8593fbc6
TG		 2550static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2551 struct mtd_oob_ops *ops)
1da177e4 2552{
29072b96 2553 int chipnr, realpage, page, blockmask, column;
862eba51 2554 struct nand_chip *chip = mtd_to_nand(mtd);
8593fbc6 2555 uint32_t writelen = ops->len;
782ce79a
ML		 2556
2557 uint32_t oobwritelen = ops->ooblen;
29f1058a 2558 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
782ce79a 2559
8593fbc6
TG		 2560 uint8_t *oob = ops->oobbuf;
2561 uint8_t *buf = ops->datbuf;
837a6ba4 2562 int ret;
e47f3db4 2563 int oob_required = oob ? 1 : 0;
1da177e4 2564
8593fbc6 2565 ops->retlen = 0;
29072b96
TG		 2566 if (!writelen)
2567 return 0;
1da177e4 2568
8b6e50c9 2569 /* Reject writes, which are not page aligned */
8593fbc6 2570 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2571 pr_notice("%s: attempt to write non page aligned data\n",
2572 __func__);
1da177e4
LT		 2573 return -EINVAL;
2574 }
2575
29072b96 2576 column = to & (mtd->writesize - 1);
1da177e4 2577
6a930961
TG		 2578 chipnr = (int)(to >> chip->chip_shift);
2579 chip->select_chip(mtd, chipnr);
2580
1da177e4 2581 /* Check, if it is write protected */
b0bb6903
HS		 2582 if (nand_check_wp(mtd)) {
2583 ret = -EIO;
2584 goto err_out;
2585 }
1da177e4 2586
f75e5097
TG		 2587 realpage = (int)(to >> chip->page_shift);
2588 page = realpage & chip->pagemask;
2589 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2590
2591 /* Invalidate the page cache, when we write to the cached page */
537ab1bd
BN		 2592 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2593 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2594 chip->pagebuf = -1;
61b03bd7 2595
782ce79a 2596 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2597 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2598 ret = -EINVAL;
2599 goto err_out;
2600 }
782ce79a 2601
f8ac0414 2602 while (1) {
29072b96 2603 int bytes = mtd->writesize;
f75e5097 2604 int cached = writelen > bytes && page != blockmask;
29072b96 2605 uint8_t *wbuf = buf;
66507c7b 2606 int use_bufpoi;
144f4c98 2607 int part_pagewr = (column || writelen < mtd->writesize);
66507c7b
KD		 2608
2609 if (part_pagewr)
2610 use_bufpoi = 1;
2611 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2612 use_bufpoi = !virt_addr_valid(buf);
2613 else
2614 use_bufpoi = 0;
29072b96 2615
66507c7b
KD		 2616 /* Partial page write?, or need to use bounce buffer */
2617 if (use_bufpoi) {
2618 pr_debug("%s: using write bounce buffer for buf@%p\n",
2619 __func__, buf);
29072b96 2620 cached = 0;
66507c7b
KD		 2621 if (part_pagewr)
2622 bytes = min_t(int, bytes - column, writelen);
29072b96
TG		 2623 chip->pagebuf = -1;
2624 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2625 memcpy(&chip->buffers->databuf[column], buf, bytes);
2626 wbuf = chip->buffers->databuf;
2627 }
1da177e4 2628
782ce79a
ML		 2629 if (unlikely(oob)) {
2630 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2631 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2632 oobwritelen -= len;
f722013e
TAA		 2633 } else {
2634 /* We still need to erase leftover OOB data */
2635 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2636 }
837a6ba4
GP		 2637 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2638 oob_required, page, cached,
2639 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2640 if (ret)
2641 break;
2642
2643 writelen -= bytes;
2644 if (!writelen)
2645 break;
2646
29072b96 2647 column = 0;
f75e5097
TG		 2648 buf += bytes;
2649 realpage++;
2650
2651 page = realpage & chip->pagemask;
2652 /* Check, if we cross a chip boundary */
2653 if (!page) {
2654 chipnr++;
2655 chip->select_chip(mtd, -1);
2656 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2657 }
2658 }
8593fbc6 2659
8593fbc6 2660 ops->retlen = ops->len - writelen;
7014568b
VW		 2661 if (unlikely(oob))
2662 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2663
2664err_out:
2665 chip->select_chip(mtd, -1);
1da177e4
LT		 2666 return ret;
2667}
2668
2af7c653
SK		 2669/**
2670 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2671 * @mtd: MTD device structure
2672 * @to: offset to write to
2673 * @len: number of bytes to write
2674 * @retlen: pointer to variable to store the number of written bytes
2675 * @buf: the data to write
2af7c653
SK		 2676 *
2677 * NAND write with ECC. Used when performing writes in interrupt context, this
2678 * may for example be called by mtdoops when writing an oops while in panic.
2679 */
2680static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2681 size_t *retlen, const uint8_t *buf)
2682{
862eba51 2683 struct nand_chip *chip = mtd_to_nand(mtd);
4a89ff88 2684 struct mtd_oob_ops ops;
2af7c653
SK		 2685 int ret;
2686
8b6e50c9 2687 /* Wait for the device to get ready */
2af7c653
SK		 2688 panic_nand_wait(mtd, chip, 400);
2689
8b6e50c9 2690 /* Grab the device */
2af7c653
SK		 2691 panic_nand_get_device(chip, mtd, FL_WRITING);
2692
0ec56dc4 2693 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2694 ops.len = len;
2695 ops.datbuf = (uint8_t *)buf;
11041ae6 2696 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2697
4a89ff88 2698 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2699
4a89ff88 2700 *retlen = ops.retlen;
2af7c653
SK		 2701 return ret;
2702}
2703
f75e5097 2704/**
8593fbc6 2705 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2706 * @mtd: MTD device structure
2707 * @to: offset to write to
2708 * @len: number of bytes to write
2709 * @retlen: pointer to variable to store the number of written bytes
2710 * @buf: the data to write
f75e5097 2711 *
8b6e50c9 2712 * NAND write with ECC.
f75e5097 2713 */
8593fbc6
TG		 2714static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2715 size_t *retlen, const uint8_t *buf)
f75e5097 2716{
4a89ff88 2717 struct mtd_oob_ops ops;
f75e5097
TG		 2718 int ret;
2719
6a8214aa 2720 nand_get_device(mtd, FL_WRITING);
0ec56dc4 2721 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2722 ops.len = len;
2723 ops.datbuf = (uint8_t *)buf;
11041ae6 2724 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2725 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2726 *retlen = ops.retlen;
f75e5097 2727 nand_release_device(mtd);
8593fbc6 2728 return ret;
f75e5097 2729}
7314e9e7 2730
1da177e4 2731/**
8593fbc6 2732 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2733 * @mtd: MTD device structure
2734 * @to: offset to write to
2735 * @ops: oob operation description structure
1da177e4 2736 *
8b6e50c9 2737 * NAND write out-of-band.
1da177e4 2738 */
8593fbc6
TG		 2739static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2740 struct mtd_oob_ops *ops)
1da177e4 2741{
03736155 2742 int chipnr, page, status, len;
862eba51 2743 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 2744
289c0522 2745 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2746 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2747
29f1058a 2748 len = mtd_oobavail(mtd, ops);
03736155 2749
1da177e4 2750 /* Do not allow write past end of page */
03736155 2751 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2752 pr_debug("%s: attempt to write past end of page\n",
2753 __func__);
1da177e4
LT		 2754 return -EINVAL;
2755 }
2756
03736155 2757 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2758 pr_debug("%s: attempt to start write outside oob\n",
2759 __func__);
03736155
AH		 2760 return -EINVAL;
2761 }
2762
775adc3d 2763 /* Do not allow write past end of device */
03736155
AH		 2764 if (unlikely(to >= mtd->size ||
2765 ops->ooboffs + ops->ooblen >
2766 ((mtd->size >> chip->page_shift) -
2767 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2768 pr_debug("%s: attempt to write beyond end of device\n",
2769 __func__);
03736155
AH		 2770 return -EINVAL;
2771 }
2772
7314e9e7 2773 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2774 chip->select_chip(mtd, chipnr);
1da177e4 2775
7314e9e7
TG		 2776 /* Shift to get page */
2777 page = (int)(to >> chip->page_shift);
2778
2779 /*
2780 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2781 * of my DiskOnChip 2000 test units) will clear the whole data page too
2782 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2783 * it in the doc2000 driver in August 1999. dwmw2.
2784 */
ace4dfee 2785 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2786
2787 /* Check, if it is write protected */
b0bb6903
HS		 2788 if (nand_check_wp(mtd)) {
2789 chip->select_chip(mtd, -1);
8593fbc6 2790 return -EROFS;
b0bb6903 2791 }
61b03bd7 2792
1da177e4 2793 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2794 if (page == chip->pagebuf)
2795 chip->pagebuf = -1;
1da177e4 2796
f722013e 2797 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2798
0612b9dd 2799 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2800 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2801 else
2802 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2803
b0bb6903
HS		 2804 chip->select_chip(mtd, -1);
2805
7bc3312b
TG		 2806 if (status)
2807 return status;
1da177e4 2808
7014568b 2809 ops->oobretlen = ops->ooblen;
1da177e4 2810
7bc3312b 2811 return 0;
8593fbc6
TG		 2812}
2813
2814/**
2815 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2816 * @mtd: MTD device structure
2817 * @to: offset to write to
2818 * @ops: oob operation description structure
8593fbc6
TG		 2819 */
2820static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2821 struct mtd_oob_ops *ops)
2822{
8593fbc6
TG		 2823 int ret = -ENOTSUPP;
2824
2825 ops->retlen = 0;
2826
2827 /* Do not allow writes past end of device */
7014568b 2828 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2829 pr_debug("%s: attempt to write beyond end of device\n",
2830 __func__);
8593fbc6
TG		 2831 return -EINVAL;
2832 }
2833
6a8214aa 2834 nand_get_device(mtd, FL_WRITING);
8593fbc6 2835
f8ac0414 2836 switch (ops->mode) {
0612b9dd
BN		 2837 case MTD_OPS_PLACE_OOB:
2838 case MTD_OPS_AUTO_OOB:
2839 case MTD_OPS_RAW:
8593fbc6
TG		 2840 break;
2841
2842 default:
2843 goto out;
2844 }
2845
2846 if (!ops->datbuf)
2847 ret = nand_do_write_oob(mtd, to, ops);
2848 else
2849 ret = nand_do_write_ops(mtd, to, ops);
2850
7351d3a5 2851out:
1da177e4 2852 nand_release_device(mtd);
1da177e4
LT		 2853 return ret;
2854}
2855
1da177e4 2856/**
49c50b97 2857 * single_erase - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2858 * @mtd: MTD device structure
2859 * @page: the page address of the block which will be erased
1da177e4 2860 *
49c50b97 2861 * Standard erase command for NAND chips. Returns NAND status.
1da177e4 2862 */
49c50b97 2863static int single_erase(struct mtd_info *mtd, int page)
1da177e4 2864{
862eba51 2865 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 2866 /* Send commands to erase a block */
ace4dfee
TG		 2867 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2868 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
49c50b97
BN		 2869
2870 return chip->waitfunc(mtd, chip);
1da177e4
LT		 2871}
2872
1da177e4
LT		 2873/**
2874 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2875 * @mtd: MTD device structure
2876 * @instr: erase instruction
1da177e4 2877 *
8b6e50c9 2878 * Erase one ore more blocks.
1da177e4 2879 */
e0c7d767 2880static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2881{
e0c7d767 2882 return nand_erase_nand(mtd, instr, 0);
1da177e4 2883}
61b03bd7 2884
1da177e4 2885/**
7854d3f7 2886 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2887 * @mtd: MTD device structure
2888 * @instr: erase instruction
2889 * @allowbbt: allow erasing the bbt area
1da177e4 2890 *
8b6e50c9 2891 * Erase one ore more blocks.
1da177e4 2892 */
ace4dfee
TG		 2893int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2894 int allowbbt)
1da177e4 2895{
69423d99 2896 int page, status, pages_per_block, ret, chipnr;
862eba51 2897 struct nand_chip *chip = mtd_to_nand(mtd);
69423d99 2898 loff_t len;
1da177e4 2899
289c0522
BN		 2900 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2901 __func__, (unsigned long long)instr->addr,
2902 (unsigned long long)instr->len);
1da177e4 2903
6fe5a6ac 2904 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2905 return -EINVAL;
1da177e4 2906
1da177e4 2907 /* Grab the lock and see if the device is available */
6a8214aa 2908 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 2909
2910 /* Shift to get first page */
ace4dfee
TG		 2911 page = (int)(instr->addr >> chip->page_shift);
2912 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2913
2914 /* Calculate pages in each block */
ace4dfee 2915 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2916
2917 /* Select the NAND device */
ace4dfee 2918 chip->select_chip(mtd, chipnr);
1da177e4 2919
1da177e4
LT		 2920 /* Check, if it is write protected */
2921 if (nand_check_wp(mtd)) {
289c0522
BN		 2922 pr_debug("%s: device is write protected!\n",
2923 __func__);
1da177e4
LT		 2924 instr->state = MTD_ERASE_FAILED;
2925 goto erase_exit;
2926 }
2927
2928 /* Loop through the pages */
2929 len = instr->len;
2930
2931 instr->state = MTD_ERASING;
2932
2933 while (len) {
12183a20 2934 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee 2935 if (nand_block_checkbad(mtd, ((loff_t) page) <<
9f3e0429 2936 chip->page_shift, allowbbt)) {
d0370219
BN		 2937 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2938 __func__, page);
1da177e4
LT		 2939 instr->state = MTD_ERASE_FAILED;
2940 goto erase_exit;
2941 }
61b03bd7 2942
ace4dfee
TG		 2943 /*
2944 * Invalidate the page cache, if we erase the block which
8b6e50c9 2945 * contains the current cached page.
ace4dfee
TG		 2946 */
2947 if (page <= chip->pagebuf && chip->pagebuf <
2948 (page + pages_per_block))
2949 chip->pagebuf = -1;
1da177e4 2950
49c50b97 2951 status = chip->erase(mtd, page & chip->pagemask);
1da177e4 2952
ace4dfee
TG		 2953 /*
2954 * See if operation failed and additional status checks are
2955 * available
2956 */
2957 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2958 status = chip->errstat(mtd, chip, FL_ERASING,
2959 status, page);
068e3c0a 2960
1da177e4 2961 /* See if block erase succeeded */
a4ab4c5d 2962 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2963 pr_debug("%s: failed erase, page 0x%08x\n",
2964 __func__, page);
1da177e4 2965 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2966 instr->fail_addr =
2967 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2968 goto erase_exit;
2969 }
30f464b7 2970
1da177e4 2971 /* Increment page address and decrement length */
daae74ca 2972 len -= (1ULL << chip->phys_erase_shift);
1da177e4
LT		 2973 page += pages_per_block;
2974
2975 /* Check, if we cross a chip boundary */
ace4dfee 2976 if (len && !(page & chip->pagemask)) {
1da177e4 2977 chipnr++;
ace4dfee
TG		 2978 chip->select_chip(mtd, -1);
2979 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2980 }
2981 }
2982 instr->state = MTD_ERASE_DONE;
2983
7351d3a5 2984erase_exit:
1da177e4
LT		 2985
2986 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2987
2988 /* Deselect and wake up anyone waiting on the device */
b0bb6903 2989 chip->select_chip(mtd, -1);
1da177e4
LT		 2990 nand_release_device(mtd);
2991
49defc01
DW		 2992 /* Do call back function */
2993 if (!ret)
2994 mtd_erase_callback(instr);
2995
1da177e4
LT		 2996 /* Return more or less happy */
2997 return ret;
2998}
2999
3000/**
3001 * nand_sync - [MTD Interface] sync
8b6e50c9 3002 * @mtd: MTD device structure
1da177e4 3003 *
8b6e50c9 3004 * Sync is actually a wait for chip ready function.
1da177e4 3005 */
e0c7d767 3006static void nand_sync(struct mtd_info *mtd)
1da177e4 3007{
289c0522 3008 pr_debug("%s: called\n", __func__);
1da177e4
LT		 3009
3010 /* Grab the lock and see if the device is available */
6a8214aa 3011 nand_get_device(mtd, FL_SYNCING);
1da177e4 3012 /* Release it and go back */
e0c7d767 3013 nand_release_device(mtd);
1da177e4
LT		 3014}
3015
1da177e4 3016/**
ace4dfee 3017 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 3018 * @mtd: MTD device structure
3019 * @offs: offset relative to mtd start
1da177e4 3020 */
ace4dfee 3021static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 3022{
9f3e0429
AT		 3023 struct nand_chip *chip = mtd_to_nand(mtd);
3024 int chipnr = (int)(offs >> chip->chip_shift);
3025 int ret;
3026
3027 /* Select the NAND device */
3028 nand_get_device(mtd, FL_READING);
3029 chip->select_chip(mtd, chipnr);
3030
3031 ret = nand_block_checkbad(mtd, offs, 0);
3032
3033 chip->select_chip(mtd, -1);
3034 nand_release_device(mtd);
3035
3036 return ret;
1da177e4
LT		 3037}
3038
3039/**
ace4dfee 3040 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 3041 * @mtd: MTD device structure
3042 * @ofs: offset relative to mtd start
1da177e4 3043 */
e0c7d767 3044static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 3045{
1da177e4
LT		 3046 int ret;
3047
f8ac0414
FF		 3048 ret = nand_block_isbad(mtd, ofs);
3049 if (ret) {
8b6e50c9 3050 /* If it was bad already, return success and do nothing */
1da177e4
LT		 3051 if (ret > 0)
3052 return 0;
e0c7d767
DW		 3053 return ret;
3054 }
1da177e4 3055
5a0edb25 3056 return nand_block_markbad_lowlevel(mtd, ofs);
1da177e4
LT		 3057}
3058
7db03ecc
HS		 3059/**
3060 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3061 * @mtd: MTD device structure
3062 * @chip: nand chip info structure
3063 * @addr: feature address.
3064 * @subfeature_param: the subfeature parameters, a four bytes array.
3065 */
3066static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3067 int addr, uint8_t *subfeature_param)
3068{
3069 int status;
05f78359 3070 int i;
7db03ecc 3071
d914c932
DM		 3072 if (!chip->onfi_version ||
3073 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3074 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 3075 return -EINVAL;
3076
3077 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
05f78359
UKK		 3078 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3079 chip->write_byte(mtd, subfeature_param[i]);
3080
7db03ecc
HS		 3081 status = chip->waitfunc(mtd, chip);
3082 if (status & NAND_STATUS_FAIL)
3083 return -EIO;
3084 return 0;
3085}
3086
3087/**
3088 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3089 * @mtd: MTD device structure
3090 * @chip: nand chip info structure
3091 * @addr: feature address.
3092 * @subfeature_param: the subfeature parameters, a four bytes array.
3093 */
3094static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3095 int addr, uint8_t *subfeature_param)
3096{
05f78359
UKK		 3097 int i;
3098
d914c932
DM		 3099 if (!chip->onfi_version ||
3100 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3101 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 3102 return -EINVAL;
3103
7db03ecc 3104 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
05f78359
UKK		 3105 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3106 *subfeature_param++ = chip->read_byte(mtd);
7db03ecc
HS		 3107 return 0;
3108}
3109
962034f4
VW		 3110/**
3111 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 3112 * @mtd: MTD device structure
962034f4
VW		 3113 */
3114static int nand_suspend(struct mtd_info *mtd)
3115{
6a8214aa 3116 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 3117}
3118
3119/**
3120 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 3121 * @mtd: MTD device structure
962034f4
VW		 3122 */
3123static void nand_resume(struct mtd_info *mtd)
3124{
862eba51 3125 struct nand_chip *chip = mtd_to_nand(mtd);
962034f4 3126
ace4dfee 3127 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 3128 nand_release_device(mtd);
3129 else
d0370219
BN		 3130 pr_err("%s called for a chip which is not in suspended state\n",
3131 __func__);
962034f4
VW		 3132}
3133
72ea4036
SB		 3134/**
3135 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3136 * prevent further operations
3137 * @mtd: MTD device structure
3138 */
3139static void nand_shutdown(struct mtd_info *mtd)
3140{
9ca641b0 3141 nand_get_device(mtd, FL_PM_SUSPENDED);
72ea4036
SB		 3142}
3143
8b6e50c9 3144/* Set default functions */
ace4dfee 3145static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 3146{
1da177e4 3147 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 3148 if (!chip->chip_delay)
3149 chip->chip_delay = 20;
1da177e4
LT		 3150
3151 /* check, if a user supplied command function given */
ace4dfee
TG		 3152 if (chip->cmdfunc == NULL)
3153 chip->cmdfunc = nand_command;
1da177e4
LT		 3154
3155 /* check, if a user supplied wait function given */
ace4dfee
TG		 3156 if (chip->waitfunc == NULL)
3157 chip->waitfunc = nand_wait;
3158
3159 if (!chip->select_chip)
3160 chip->select_chip = nand_select_chip;
68e80780 3161
4204cccd
HS		 3162 /* set for ONFI nand */
3163 if (!chip->onfi_set_features)
3164 chip->onfi_set_features = nand_onfi_set_features;
3165 if (!chip->onfi_get_features)
3166 chip->onfi_get_features = nand_onfi_get_features;
3167
68e80780
BN		 3168 /* If called twice, pointers that depend on busw may need to be reset */
3169 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 3170 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3171 if (!chip->read_word)
3172 chip->read_word = nand_read_word;
3173 if (!chip->block_bad)
3174 chip->block_bad = nand_block_bad;
3175 if (!chip->block_markbad)
3176 chip->block_markbad = nand_default_block_markbad;
68e80780 3177 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 3178 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
05f78359
UKK		 3179 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3180 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
68e80780 3181 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 3182 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 3183 if (!chip->scan_bbt)
3184 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 3185
3186 if (!chip->controller) {
3187 chip->controller = &chip->hwcontrol;
fe18266a 3188 nand_hw_control_init(chip->controller);
f75e5097
TG		 3189 }
3190
7aa65bfd
TG		 3191}
3192
8b6e50c9 3193/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 3194static void sanitize_string(uint8_t *s, size_t len)
3195{
3196 ssize_t i;
3197
8b6e50c9 3198 /* Null terminate */
d1e1f4e4
FF		 3199 s[len - 1] = 0;
3200
8b6e50c9 3201 /* Remove non printable chars */
d1e1f4e4
FF		 3202 for (i = 0; i < len - 1; i++) {
3203 if (s[i] < ' ' || s[i] > 127)
3204 s[i] = '?';
3205 }
3206
8b6e50c9 3207 /* Remove trailing spaces */
d1e1f4e4
FF		 3208 strim(s);
3209}
3210
3211static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3212{
3213 int i;
3214 while (len--) {
3215 crc ^= *p++ << 8;
3216 for (i = 0; i < 8; i++)
3217 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3218 }
3219
3220 return crc;
3221}
3222
6dcbe0cd
HS		 3223/* Parse the Extended Parameter Page. */
3224static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3225 struct nand_chip *chip, struct nand_onfi_params *p)
3226{
3227 struct onfi_ext_param_page *ep;
3228 struct onfi_ext_section *s;
3229 struct onfi_ext_ecc_info *ecc;
3230 uint8_t *cursor;
3231 int ret = -EINVAL;
3232 int len;
3233 int i;
3234
3235 len = le16_to_cpu(p->ext_param_page_length) * 16;
3236 ep = kmalloc(len, GFP_KERNEL);
5cb13271
BN		 3237 if (!ep)
3238 return -ENOMEM;
6dcbe0cd
HS		 3239
3240 /* Send our own NAND_CMD_PARAM. */
3241 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3242
3243 /* Use the Change Read Column command to skip the ONFI param pages. */
3244 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3245 sizeof(*p) * p->num_of_param_pages , -1);
3246
3247 /* Read out the Extended Parameter Page. */
3248 chip->read_buf(mtd, (uint8_t *)ep, len);
3249 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3250 != le16_to_cpu(ep->crc))) {
3251 pr_debug("fail in the CRC.\n");
3252 goto ext_out;
3253 }
3254
3255 /*
3256 * Check the signature.
3257 * Do not strictly follow the ONFI spec, maybe changed in future.
3258 */
3259 if (strncmp(ep->sig, "EPPS", 4)) {
3260 pr_debug("The signature is invalid.\n");
3261 goto ext_out;
3262 }
3263
3264 /* find the ECC section. */
3265 cursor = (uint8_t *)(ep + 1);
3266 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3267 s = ep->sections + i;
3268 if (s->type == ONFI_SECTION_TYPE_2)
3269 break;
3270 cursor += s->length * 16;
3271 }
3272 if (i == ONFI_EXT_SECTION_MAX) {
3273 pr_debug("We can not find the ECC section.\n");
3274 goto ext_out;
3275 }
3276
3277 /* get the info we want. */
3278 ecc = (struct onfi_ext_ecc_info *)cursor;
3279
4ae7d228
BN		 3280 if (!ecc->codeword_size) {
3281 pr_debug("Invalid codeword size\n");
3282 goto ext_out;
6dcbe0cd
HS		 3283 }
3284
4ae7d228
BN		 3285 chip->ecc_strength_ds = ecc->ecc_bits;
3286 chip->ecc_step_ds = 1 << ecc->codeword_size;
5cb13271 3287 ret = 0;
6dcbe0cd
HS		 3288
3289ext_out:
3290 kfree(ep);
3291 return ret;
3292}
3293
8429bb39
BN		 3294static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3295{
862eba51 3296 struct nand_chip *chip = mtd_to_nand(mtd);
8429bb39
BN		 3297 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3298
3299 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3300 feature);
3301}
3302
3303/*
3304 * Configure chip properties from Micron vendor-specific ONFI table
3305 */
3306static void nand_onfi_detect_micron(struct nand_chip *chip,
3307 struct nand_onfi_params *p)
3308{
3309 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3310
3311 if (le16_to_cpu(p->vendor_revision) < 1)
3312 return;
3313
3314 chip->read_retries = micron->read_retry_options;
3315 chip->setup_read_retry = nand_setup_read_retry_micron;
3316}
3317
6fb277ba 3318/*
8b6e50c9 3319 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 3320 */
3321static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 3322 int *busw)
6fb277ba
FF		 3323{
3324 struct nand_onfi_params *p = &chip->onfi_params;
bd9c6e99 3325 int i, j;
6fb277ba
FF		 3326 int val;
3327
7854d3f7 3328 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 3329 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3330 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3331 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3332 return 0;
3333
6fb277ba
FF		 3334 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3335 for (i = 0; i < 3; i++) {
bd9c6e99
BN		 3336 for (j = 0; j < sizeof(*p); j++)
3337 ((uint8_t *)p)[j] = chip->read_byte(mtd);
6fb277ba
FF		 3338 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3339 le16_to_cpu(p->crc)) {
6fb277ba
FF		 3340 break;
3341 }
3342 }
3343
c7f23a70
BN		 3344 if (i == 3) {
3345 pr_err("Could not find valid ONFI parameter page; aborting\n");
6fb277ba 3346 return 0;
c7f23a70 3347 }
6fb277ba 3348
8b6e50c9 3349 /* Check version */
6fb277ba 3350 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 3351 if (val & (1 << 5))
3352 chip->onfi_version = 23;
3353 else if (val & (1 << 4))
6fb277ba
FF		 3354 chip->onfi_version = 22;
3355 else if (val & (1 << 3))
3356 chip->onfi_version = 21;
3357 else if (val & (1 << 2))
3358 chip->onfi_version = 20;
b7b1a29d 3359 else if (val & (1 << 1))
6fb277ba 3360 chip->onfi_version = 10;
b7b1a29d
BN		 3361
3362 if (!chip->onfi_version) {
20171642 3363 pr_info("unsupported ONFI version: %d\n", val);
b7b1a29d
BN		 3364 return 0;
3365 }
6fb277ba
FF		 3366
3367 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3368 sanitize_string(p->model, sizeof(p->model));
3369 if (!mtd->name)
3370 mtd->name = p->model;
4355b70c 3371
6fb277ba 3372 mtd->writesize = le32_to_cpu(p->byte_per_page);
4355b70c
BN		 3373
3374 /*
3375 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3376 * (don't ask me who thought of this...). MTD assumes that these
3377 * dimensions will be power-of-2, so just truncate the remaining area.
3378 */
3379 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3380 mtd->erasesize *= mtd->writesize;
3381
6fb277ba 3382 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4355b70c
BN		 3383
3384 /* See erasesize comment */
3385 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3386 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
13fbd179 3387 chip->bits_per_cell = p->bits_per_cell;
e2985fc1
HS		 3388
3389 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
08c248fb 3390 *busw = NAND_BUSWIDTH_16;
e2985fc1
HS		 3391 else
3392 *busw = 0;
6fb277ba 3393
10c86bab
HS		 3394 if (p->ecc_bits != 0xff) {
3395 chip->ecc_strength_ds = p->ecc_bits;
3396 chip->ecc_step_ds = 512;
6dcbe0cd
HS		 3397 } else if (chip->onfi_version >= 21 &&
3398 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3399
3400 /*
3401 * The nand_flash_detect_ext_param_page() uses the
3402 * Change Read Column command which maybe not supported
3403 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3404 * now. We do not replace user supplied command function.
3405 */
3406 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3407 chip->cmdfunc = nand_command_lp;
3408
3409 /* The Extended Parameter Page is supported since ONFI 2.1. */
3410 if (nand_flash_detect_ext_param_page(mtd, chip, p))
c7f23a70
BN		 3411 pr_warn("Failed to detect ONFI extended param page\n");
3412 } else {
3413 pr_warn("Could not retrieve ONFI ECC requirements\n");
10c86bab
HS		 3414 }
3415
8429bb39
BN		 3416 if (p->jedec_id == NAND_MFR_MICRON)
3417 nand_onfi_detect_micron(chip, p);
3418
6fb277ba
FF		 3419 return 1;
3420}
3421
91361818
HS		 3422/*
3423 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3424 */
3425static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3426 int *busw)
3427{
3428 struct nand_jedec_params *p = &chip->jedec_params;
3429 struct jedec_ecc_info *ecc;
3430 int val;
3431 int i, j;
3432
3433 /* Try JEDEC for unknown chip or LP */
3434 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3435 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3436 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3437 chip->read_byte(mtd) != 'C')
3438 return 0;
3439
3440 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3441 for (i = 0; i < 3; i++) {
3442 for (j = 0; j < sizeof(*p); j++)
3443 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3444
3445 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3446 le16_to_cpu(p->crc))
3447 break;
3448 }
3449
3450 if (i == 3) {
3451 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3452 return 0;
3453 }
3454
3455 /* Check version */
3456 val = le16_to_cpu(p->revision);
3457 if (val & (1 << 2))
3458 chip->jedec_version = 10;
3459 else if (val & (1 << 1))
3460 chip->jedec_version = 1; /* vendor specific version */
3461
3462 if (!chip->jedec_version) {
3463 pr_info("unsupported JEDEC version: %d\n", val);
3464 return 0;
3465 }
3466
3467 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3468 sanitize_string(p->model, sizeof(p->model));
3469 if (!mtd->name)
3470 mtd->name = p->model;
3471
3472 mtd->writesize = le32_to_cpu(p->byte_per_page);
3473
3474 /* Please reference to the comment for nand_flash_detect_onfi. */
3475 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3476 mtd->erasesize *= mtd->writesize;
3477
3478 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3479
3480 /* Please reference to the comment for nand_flash_detect_onfi. */
3481 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3482 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3483 chip->bits_per_cell = p->bits_per_cell;
3484
3485 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3486 *busw = NAND_BUSWIDTH_16;
3487 else
3488 *busw = 0;
3489
3490 /* ECC info */
3491 ecc = &p->ecc_info[0];
3492
3493 if (ecc->codeword_size >= 9) {
3494 chip->ecc_strength_ds = ecc->ecc_bits;
3495 chip->ecc_step_ds = 1 << ecc->codeword_size;
3496 } else {
3497 pr_warn("Invalid codeword size\n");
3498 }
3499
3500 return 1;
3501}
3502
e3b88bd6
BN		 3503/*
3504 * nand_id_has_period - Check if an ID string has a given wraparound period
3505 * @id_data: the ID string
3506 * @arrlen: the length of the @id_data array
3507 * @period: the period of repitition
3508 *
3509 * Check if an ID string is repeated within a given sequence of bytes at
3510 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3511 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3512 * if the repetition has a period of @period; otherwise, returns zero.
3513 */
3514static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3515{
3516 int i, j;
3517 for (i = 0; i < period; i++)
3518 for (j = i + period; j < arrlen; j += period)
3519 if (id_data[i] != id_data[j])
3520 return 0;
3521 return 1;
3522}
3523
3524/*
3525 * nand_id_len - Get the length of an ID string returned by CMD_READID
3526 * @id_data: the ID string
3527 * @arrlen: the length of the @id_data array
3528
3529 * Returns the length of the ID string, according to known wraparound/trailing
3530 * zero patterns. If no pattern exists, returns the length of the array.
3531 */
3532static int nand_id_len(u8 *id_data, int arrlen)
3533{
3534 int last_nonzero, period;
3535
3536 /* Find last non-zero byte */
3537 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3538 if (id_data[last_nonzero])
3539 break;
3540
3541 /* All zeros */
3542 if (last_nonzero < 0)
3543 return 0;
3544
3545 /* Calculate wraparound period */
3546 for (period = 1; period < arrlen; period++)
3547 if (nand_id_has_period(id_data, arrlen, period))
3548 break;
3549
3550 /* There's a repeated pattern */
3551 if (period < arrlen)
3552 return period;
3553
3554 /* There are trailing zeros */
3555 if (last_nonzero < arrlen - 1)
3556 return last_nonzero + 1;
3557
3558 /* No pattern detected */
3559 return arrlen;
3560}
3561
7db906b7
HS		 3562/* Extract the bits of per cell from the 3rd byte of the extended ID */
3563static int nand_get_bits_per_cell(u8 cellinfo)
3564{
3565 int bits;
3566
3567 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3568 bits >>= NAND_CI_CELLTYPE_SHIFT;
3569 return bits + 1;
3570}
3571
fc09bbc0
BN		 3572/*
3573 * Many new NAND share similar device ID codes, which represent the size of the
3574 * chip. The rest of the parameters must be decoded according to generic or
3575 * manufacturer-specific "extended ID" decoding patterns.
3576 */
3577static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3578 u8 id_data[8], int *busw)
3579{
e3b88bd6 3580 int extid, id_len;
fc09bbc0 3581 /* The 3rd id byte holds MLC / multichip data */
7db906b7 3582 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
fc09bbc0
BN		 3583 /* The 4th id byte is the important one */
3584 extid = id_data[3];
3585
e3b88bd6
BN		 3586 id_len = nand_id_len(id_data, 8);
3587
fc09bbc0
BN		 3588 /*
3589 * Field definitions are in the following datasheets:
3590 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 3591 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 3592 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 3593 *
af451af4
BN		 3594 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3595 * ID to decide what to do.
fc09bbc0 3596 */
af451af4 3597 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
1d0ed69d 3598 !nand_is_slc(chip) && id_data[5] != 0x00) {
fc09bbc0
BN		 3599 /* Calc pagesize */
3600 mtd->writesize = 2048 << (extid & 0x03);
3601 extid >>= 2;
3602 /* Calc oobsize */
e2d3a35e 3603 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 3604 case 1:
3605 mtd->oobsize = 128;
3606 break;
3607 case 2:
3608 mtd->oobsize = 218;
3609 break;
3610 case 3:
3611 mtd->oobsize = 400;
3612 break;
e2d3a35e 3613 case 4:
fc09bbc0
BN		 3614 mtd->oobsize = 436;
3615 break;
e2d3a35e
BN		 3616 case 5:
3617 mtd->oobsize = 512;
3618 break;
3619 case 6:
e2d3a35e
BN		 3620 mtd->oobsize = 640;
3621 break;
94d04e82
HS		 3622 case 7:
3623 default: /* Other cases are "reserved" (unknown) */
3624 mtd->oobsize = 1024;
3625 break;
fc09bbc0
BN		 3626 }
3627 extid >>= 2;
3628 /* Calc blocksize */
3629 mtd->erasesize = (128 * 1024) <<
3630 (((extid >> 1) & 0x04) | (extid & 0x03));
3631 *busw = 0;
73ca392f 3632 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
1d0ed69d 3633 !nand_is_slc(chip)) {
73ca392f
BN		 3634 unsigned int tmp;
3635
3636 /* Calc pagesize */
3637 mtd->writesize = 2048 << (extid & 0x03);
3638 extid >>= 2;
3639 /* Calc oobsize */
3640 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3641 case 0:
3642 mtd->oobsize = 128;
3643 break;
3644 case 1:
3645 mtd->oobsize = 224;
3646 break;
3647 case 2:
3648 mtd->oobsize = 448;
3649 break;
3650 case 3:
3651 mtd->oobsize = 64;
3652 break;
3653 case 4:
3654 mtd->oobsize = 32;
3655 break;
3656 case 5:
3657 mtd->oobsize = 16;
3658 break;
3659 default:
3660 mtd->oobsize = 640;
3661 break;
3662 }
3663 extid >>= 2;
3664 /* Calc blocksize */
3665 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3666 if (tmp < 0x03)
3667 mtd->erasesize = (128 * 1024) << tmp;
3668 else if (tmp == 0x03)
3669 mtd->erasesize = 768 * 1024;
3670 else
3671 mtd->erasesize = (64 * 1024) << tmp;
3672 *busw = 0;
fc09bbc0
BN		 3673 } else {
3674 /* Calc pagesize */
3675 mtd->writesize = 1024 << (extid & 0x03);
3676 extid >>= 2;
3677 /* Calc oobsize */
3678 mtd->oobsize = (8 << (extid & 0x01)) *
3679 (mtd->writesize >> 9);
3680 extid >>= 2;
3681 /* Calc blocksize. Blocksize is multiples of 64KiB */
3682 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3683 extid >>= 2;
3684 /* Get buswidth information */
3685 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
60c67382
BN		 3686
3687 /*
3688 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3689 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3690 * follows:
3691 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3692 * 110b -> 24nm
3693 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3694 */
3695 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
1d0ed69d 3696 nand_is_slc(chip) &&
60c67382
BN		 3697 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3698 !(id_data[4] & 0x80) /* !BENAND */) {
3699 mtd->oobsize = 32 * mtd->writesize >> 9;
3700 }
3701
fc09bbc0
BN		 3702 }
3703}
3704
f23a481c
BN		 3705/*
3706 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3707 * decodes a matching ID table entry and assigns the MTD size parameters for
3708 * the chip.
3709 */
3710static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3711 struct nand_flash_dev *type, u8 id_data[8],
3712 int *busw)
3713{
3714 int maf_id = id_data[0];
3715
3716 mtd->erasesize = type->erasesize;
3717 mtd->writesize = type->pagesize;
3718 mtd->oobsize = mtd->writesize / 32;
3719 *busw = type->options & NAND_BUSWIDTH_16;
3720
1c195e90
HS		 3721 /* All legacy ID NAND are small-page, SLC */
3722 chip->bits_per_cell = 1;
3723
f23a481c
BN		 3724 /*
3725 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3726 * some Spansion chips have erasesize that conflicts with size
3727 * listed in nand_ids table.
3728 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3729 */
3730 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3731 && id_data[6] == 0x00 && id_data[7] == 0x00
3732 && mtd->writesize == 512) {
3733 mtd->erasesize = 128 * 1024;
3734 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3735 }
3736}
3737
7e74c2d7
BN		 3738/*
3739 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3740 * heuristic patterns using various detected parameters (e.g., manufacturer,
3741 * page size, cell-type information).
3742 */
3743static void nand_decode_bbm_options(struct mtd_info *mtd,
3744 struct nand_chip *chip, u8 id_data[8])
3745{
3746 int maf_id = id_data[0];
3747
3748 /* Set the bad block position */
3749 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3750 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3751 else
3752 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3753
3754 /*
3755 * Bad block marker is stored in the last page of each block on Samsung
3756 * and Hynix MLC devices; stored in first two pages of each block on
3757 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3758 * AMD/Spansion, and Macronix. All others scan only the first page.
3759 */
1d0ed69d 3760 if (!nand_is_slc(chip) &&
7e74c2d7
BN		 3761 (maf_id == NAND_MFR_SAMSUNG ||
3762 maf_id == NAND_MFR_HYNIX))
3763 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
1d0ed69d 3764 else if ((nand_is_slc(chip) &&
7e74c2d7
BN		 3765 (maf_id == NAND_MFR_SAMSUNG ||
3766 maf_id == NAND_MFR_HYNIX ||
3767 maf_id == NAND_MFR_TOSHIBA ||
3768 maf_id == NAND_MFR_AMD ||
3769 maf_id == NAND_MFR_MACRONIX)) ||
3770 (mtd->writesize == 2048 &&
3771 maf_id == NAND_MFR_MICRON))
3772 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3773}
3774
ec6e87e3
HS		 3775static inline bool is_full_id_nand(struct nand_flash_dev *type)
3776{
3777 return type->id_len;
3778}
3779
3780static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3781 struct nand_flash_dev *type, u8 *id_data, int *busw)
3782{
3783 if (!strncmp(type->id, id_data, type->id_len)) {
3784 mtd->writesize = type->pagesize;
3785 mtd->erasesize = type->erasesize;
3786 mtd->oobsize = type->oobsize;
3787
7db906b7 3788 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
ec6e87e3
HS		 3789 chip->chipsize = (uint64_t)type->chipsize << 20;
3790 chip->options |= type->options;
57219342
HS		 3791 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3792 chip->ecc_step_ds = NAND_ECC_STEP(type);
57a94e24
BB		 3793 chip->onfi_timing_mode_default =
3794 type->onfi_timing_mode_default;
ec6e87e3
HS		 3795
3796 *busw = type->options & NAND_BUSWIDTH_16;
3797
092b6a1d
CZ		 3798 if (!mtd->name)
3799 mtd->name = type->name;
3800
ec6e87e3
HS		 3801 return true;
3802 }
3803 return false;
3804}
3805
7aa65bfd 3806/*
8b6e50c9 3807 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3808 */
3809static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3810 struct nand_chip *chip,
7351d3a5 3811 int *maf_id, int *dev_id,
5e81e88a 3812 struct nand_flash_dev *type)
7aa65bfd 3813{
bb77082f 3814 int busw;
d1e1f4e4 3815 int i, maf_idx;
426c457a 3816 u8 id_data[8];
1da177e4
LT		 3817
3818 /* Select the device */
ace4dfee 3819 chip->select_chip(mtd, 0);
1da177e4 3820
ef89a880
KB		 3821 /*
3822 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3823 * after power-up.
ef89a880
KB		 3824 */
3825 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3826
1da177e4 3827 /* Send the command for reading device ID */
ace4dfee 3828 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3829
3830 /* Read manufacturer and device IDs */
ace4dfee 3831 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3832 *dev_id = chip->read_byte(mtd);
1da177e4 3833
8b6e50c9
BN		 3834 /*
3835 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3836 * interface concerns can cause random data which looks like a
3837 * possibly credible NAND flash to appear. If the two results do
3838 * not match, ignore the device completely.
3839 */
3840
3841 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3842
4aef9b78
BN		 3843 /* Read entire ID string */
3844 for (i = 0; i < 8; i++)
426c457a 3845 id_data[i] = chip->read_byte(mtd);
ed8165c7 3846
d1e1f4e4 3847 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
20171642 3848 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
d0370219 3849 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3850 return ERR_PTR(-ENODEV);
3851 }
3852
7aa65bfd 3853 if (!type)
5e81e88a
DW		 3854 type = nand_flash_ids;
3855
ec6e87e3
HS		 3856 for (; type->name != NULL; type++) {
3857 if (is_full_id_nand(type)) {
3858 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3859 goto ident_done;
3860 } else if (*dev_id == type->dev_id) {
db5b09f6 3861 break;
ec6e87e3
HS		 3862 }
3863 }
5e81e88a 3864
d1e1f4e4
FF		 3865 chip->onfi_version = 0;
3866 if (!type->name || !type->pagesize) {
35fc5195 3867 /* Check if the chip is ONFI compliant */
47450b35 3868 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3869 goto ident_done;
91361818
HS		 3870
3871 /* Check if the chip is JEDEC compliant */
3872 if (nand_flash_detect_jedec(mtd, chip, &busw))
3873 goto ident_done;
d1e1f4e4
FF		 3874 }
3875
5e81e88a 3876 if (!type->name)
7aa65bfd
TG		 3877 return ERR_PTR(-ENODEV);
3878
ba0251fe
TG		 3879 if (!mtd->name)
3880 mtd->name = type->name;
3881
69423d99 3882 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3883
a7f5ba40 3884 if (!type->pagesize) {
fc09bbc0
BN		 3885 /* Decode parameters from extended ID */
3886 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3887 } else {
f23a481c 3888 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3889 }
bf7a01bf
BN		 3890 /* Get chip options */
3891 chip->options |= type->options;
d1e1f4e4 3892
8b6e50c9
BN		 3893 /*
3894 * Check if chip is not a Samsung device. Do not clear the
3895 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3896 */
3897 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3898 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3899ident_done:
3900
7aa65bfd 3901 /* Try to identify manufacturer */
9a909867 3902 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3903 if (nand_manuf_ids[maf_idx].id == *maf_id)
3904 break;
3905 }
0ea4a755 3906
64b37b2a
MC		 3907 if (chip->options & NAND_BUSWIDTH_AUTO) {
3908 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3909 chip->options |= busw;
3910 nand_set_defaults(chip, busw);
3911 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3912 /*
3913 * Check, if buswidth is correct. Hardware drivers should set
3914 * chip correct!
3915 */
20171642
EG		 3916 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3917 *maf_id, *dev_id);
3918 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3919 pr_warn("bus width %d instead %d bit\n",
d0370219
BN		 3920 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3921 busw ? 16 : 8);
7aa65bfd
TG		 3922 return ERR_PTR(-EINVAL);
3923 }
61b03bd7 3924
7e74c2d7
BN		 3925 nand_decode_bbm_options(mtd, chip, id_data);
3926
7aa65bfd 3927 /* Calculate the address shift from the page size */
ace4dfee 3928 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3929 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3930 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3931
ace4dfee 3932 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3933 ffs(mtd->erasesize) - 1;
69423d99
AH		 3934 if (chip->chipsize & 0xffffffff)
3935 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3936 else {
3937 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3938 chip->chip_shift += 32 - 1;
3939 }
1da177e4 3940
26d9be11 3941 chip->badblockbits = 8;
49c50b97 3942 chip->erase = single_erase;
7aa65bfd 3943
8b6e50c9 3944 /* Do not replace user supplied command function! */
ace4dfee
TG		 3945 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3946 chip->cmdfunc = nand_command_lp;
7aa65bfd 3947
20171642
EG		 3948 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3949 *maf_id, *dev_id);
ffdac6cd
HS		 3950
3951 if (chip->onfi_version)
3952 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3953 chip->onfi_params.model);
3954 else if (chip->jedec_version)
3955 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3956 chip->jedec_params.model);
3957 else
3958 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3959 type->name);
3960
3755a991 3961 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3723e93c 3962 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3755a991 3963 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3964 return type;
3965}
3966
d48f62b9
BB		 3967static const char * const nand_ecc_modes[] = {
3968 [NAND_ECC_NONE] = "none",
3969 [NAND_ECC_SOFT] = "soft",
3970 [NAND_ECC_HW] = "hw",
3971 [NAND_ECC_HW_SYNDROME] = "hw_syndrome",
3972 [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first",
d48f62b9
BB		 3973};
3974
3975static int of_get_nand_ecc_mode(struct device_node *np)
3976{
3977 const char *pm;
3978 int err, i;
3979
3980 err = of_property_read_string(np, "nand-ecc-mode", &pm);
3981 if (err < 0)
3982 return err;
3983
3984 for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++)
3985 if (!strcasecmp(pm, nand_ecc_modes[i]))
3986 return i;
3987
ae211bcf
RM		 3988 /*
3989 * For backward compatibility we support few obsoleted values that don't
3990 * have their mappings into nand_ecc_modes_t anymore (they were merged
3991 * with other enums).
3992 */
3993 if (!strcasecmp(pm, "soft_bch"))
3994 return NAND_ECC_SOFT;
3995
d48f62b9
BB		 3996 return -ENODEV;
3997}
3998
ba4f46b2
RM		 3999static const char * const nand_ecc_algos[] = {
4000 [NAND_ECC_HAMMING] = "hamming",
4001 [NAND_ECC_BCH] = "bch",
4002};
4003
d48f62b9
BB		 4004static int of_get_nand_ecc_algo(struct device_node *np)
4005{
4006 const char *pm;
ba4f46b2 4007 int err, i;
d48f62b9 4008
ba4f46b2
RM		 4009 err = of_property_read_string(np, "nand-ecc-algo", &pm);
4010 if (!err) {
4011 for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++)
4012 if (!strcasecmp(pm, nand_ecc_algos[i]))
4013 return i;
4014 return -ENODEV;
4015 }
d48f62b9
BB		 4016
4017 /*
4018 * For backward compatibility we also read "nand-ecc-mode" checking
4019 * for some obsoleted values that were specifying ECC algorithm.
4020 */
4021 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4022 if (err < 0)
4023 return err;
4024
4025 if (!strcasecmp(pm, "soft"))
4026 return NAND_ECC_HAMMING;
4027 else if (!strcasecmp(pm, "soft_bch"))
4028 return NAND_ECC_BCH;
4029
4030 return -ENODEV;
4031}
4032
4033static int of_get_nand_ecc_step_size(struct device_node *np)
4034{
4035 int ret;
4036 u32 val;
4037
4038 ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
4039 return ret ? ret : val;
4040}
4041
4042static int of_get_nand_ecc_strength(struct device_node *np)
4043{
4044 int ret;
4045 u32 val;
4046
4047 ret = of_property_read_u32(np, "nand-ecc-strength", &val);
4048 return ret ? ret : val;
4049}
4050
4051static int of_get_nand_bus_width(struct device_node *np)
4052{
4053 u32 val;
4054
4055 if (of_property_read_u32(np, "nand-bus-width", &val))
4056 return 8;
4057
4058 switch (val) {
4059 case 8:
4060 case 16:
4061 return val;
4062 default:
4063 return -EIO;
4064 }
4065}
4066
4067static bool of_get_nand_on_flash_bbt(struct device_node *np)
4068{
4069 return of_property_read_bool(np, "nand-on-flash-bbt");
4070}
4071
7194a29a 4072static int nand_dt_init(struct nand_chip *chip)
5844feea 4073{
7194a29a 4074 struct device_node *dn = nand_get_flash_node(chip);
79082457 4075 int ecc_mode, ecc_algo, ecc_strength, ecc_step;
5844feea 4076
7194a29a
BB		 4077 if (!dn)
4078 return 0;
4079
5844feea
BN		 4080 if (of_get_nand_bus_width(dn) == 16)
4081 chip->options |= NAND_BUSWIDTH_16;
4082
4083 if (of_get_nand_on_flash_bbt(dn))
4084 chip->bbt_options |= NAND_BBT_USE_FLASH;
4085
4086 ecc_mode = of_get_nand_ecc_mode(dn);
79082457 4087 ecc_algo = of_get_nand_ecc_algo(dn);
5844feea
BN		 4088 ecc_strength = of_get_nand_ecc_strength(dn);
4089 ecc_step = of_get_nand_ecc_step_size(dn);
4090
4091 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
4092 (!(ecc_step >= 0) && ecc_strength >= 0)) {
4093 pr_err("must set both strength and step size in DT\n");
4094 return -EINVAL;
4095 }
4096
4097 if (ecc_mode >= 0)
4098 chip->ecc.mode = ecc_mode;
4099
79082457
RM		 4100 if (ecc_algo >= 0)
4101 chip->ecc.algo = ecc_algo;
4102
5844feea
BN		 4103 if (ecc_strength >= 0)
4104 chip->ecc.strength = ecc_strength;
4105
4106 if (ecc_step > 0)
4107 chip->ecc.size = ecc_step;
4108
4109 return 0;
4110}
4111
7aa65bfd 4112/**
3b85c321 4113 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4114 * @mtd: MTD device structure
4115 * @maxchips: number of chips to scan for
4116 * @table: alternative NAND ID table
7aa65bfd 4117 *
8b6e50c9
BN		 4118 * This is the first phase of the normal nand_scan() function. It reads the
4119 * flash ID and sets up MTD fields accordingly.
7aa65bfd
TG		 4120 *
4121 */
5e81e88a
DW		 4122int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4123 struct nand_flash_dev *table)
7aa65bfd 4124{
bb77082f 4125 int i, nand_maf_id, nand_dev_id;
862eba51 4126 struct nand_chip *chip = mtd_to_nand(mtd);
7aa65bfd 4127 struct nand_flash_dev *type;
5844feea
BN		 4128 int ret;
4129
7194a29a
BB		 4130 ret = nand_dt_init(chip);
4131 if (ret)
4132 return ret;
7aa65bfd 4133
f7a8e38f
BN		 4134 if (!mtd->name && mtd->dev.parent)
4135 mtd->name = dev_name(mtd->dev.parent);
4136
2b3c2e2d
AS		 4137 if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) {
4138 /*
4139 * Default functions assigned for chip_select() and
4140 * cmdfunc() both expect cmd_ctrl() to be populated,
4141 * so we need to check that that's the case
4142 */
4143 pr_err("chip.cmd_ctrl() callback is not provided");
4144 return -EINVAL;
4145 }
7aa65bfd 4146 /* Set the default functions */
bb77082f 4147 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
7aa65bfd
TG		 4148
4149 /* Read the flash type */
bb77082f
CZ		 4150 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
4151 &nand_dev_id, table);
7aa65bfd
TG		 4152
4153 if (IS_ERR(type)) {
b1c6e6db 4154 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 4155 pr_warn("No NAND device found\n");
ace4dfee 4156 chip->select_chip(mtd, -1);
7aa65bfd 4157 return PTR_ERR(type);
1da177e4
LT		 4158 }
4159
07300164
HS		 4160 chip->select_chip(mtd, -1);
4161
7aa65bfd 4162 /* Check for a chip array */
e0c7d767 4163 for (i = 1; i < maxchips; i++) {
ace4dfee 4164 chip->select_chip(mtd, i);
ef89a880
KB		 4165 /* See comment in nand_get_flash_type for reset */
4166 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 4167 /* Send the command for reading device ID */
ace4dfee 4168 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 4169 /* Read manufacturer and device IDs */
ace4dfee 4170 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 4171 nand_dev_id != chip->read_byte(mtd)) {
4172 chip->select_chip(mtd, -1);
1da177e4 4173 break;
07300164
HS		 4174 }
4175 chip->select_chip(mtd, -1);
1da177e4
LT		 4176 }
4177 if (i > 1)
20171642 4178 pr_info("%d chips detected\n", i);
61b03bd7 4179
1da177e4 4180 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 4181 chip->numchips = i;
4182 mtd->size = i * chip->chipsize;
7aa65bfd 4183
3b85c321
DW		 4184 return 0;
4185}
7351d3a5 4186EXPORT_SYMBOL(nand_scan_ident);
3b85c321 4187
06f384c9
RM		 4188static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
4189{
4190 struct nand_chip *chip = mtd_to_nand(mtd);
4191 struct nand_ecc_ctrl *ecc = &chip->ecc;
4192
e4225ae8 4193 if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
06f384c9
RM		 4194 return -EINVAL;
4195
4196 switch (ecc->algo) {
4197 case NAND_ECC_HAMMING:
4198 ecc->calculate = nand_calculate_ecc;
4199 ecc->correct = nand_correct_data;
4200 ecc->read_page = nand_read_page_swecc;
4201 ecc->read_subpage = nand_read_subpage;
4202 ecc->write_page = nand_write_page_swecc;
4203 ecc->read_page_raw = nand_read_page_raw;
4204 ecc->write_page_raw = nand_write_page_raw;
4205 ecc->read_oob = nand_read_oob_std;
4206 ecc->write_oob = nand_write_oob_std;
4207 if (!ecc->size)
4208 ecc->size = 256;
4209 ecc->bytes = 3;
4210 ecc->strength = 1;
4211 return 0;
4212 case NAND_ECC_BCH:
4213 if (!mtd_nand_has_bch()) {
4214 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4215 return -EINVAL;
4216 }
4217 ecc->calculate = nand_bch_calculate_ecc;
4218 ecc->correct = nand_bch_correct_data;
4219 ecc->read_page = nand_read_page_swecc;
4220 ecc->read_subpage = nand_read_subpage;
4221 ecc->write_page = nand_write_page_swecc;
4222 ecc->read_page_raw = nand_read_page_raw;
4223 ecc->write_page_raw = nand_write_page_raw;
4224 ecc->read_oob = nand_read_oob_std;
4225 ecc->write_oob = nand_write_oob_std;
4226 /*
4227 * Board driver should supply ecc.size and ecc.strength
4228 * values to select how many bits are correctable.
4229 * Otherwise, default to 4 bits for large page devices.
4230 */
4231 if (!ecc->size && (mtd->oobsize >= 64)) {
4232 ecc->size = 512;
4233 ecc->strength = 4;
4234 }
4235
4236 /*
4237 * if no ecc placement scheme was provided pickup the default
4238 * large page one.
4239 */
4240 if (!mtd->ooblayout) {
4241 /* handle large page devices only */
4242 if (mtd->oobsize < 64) {
4243 WARN(1, "OOB layout is required when using software BCH on small pages\n");
4244 return -EINVAL;
4245 }
4246
4247 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
4248 }
4249
4250 /* See nand_bch_init() for details. */
4251 ecc->bytes = 0;
4252 ecc->priv = nand_bch_init(mtd);
4253 if (!ecc->priv) {
4254 WARN(1, "BCH ECC initialization failed!\n");
4255 return -EINVAL;
4256 }
4257 return 0;
4258 default:
4259 WARN(1, "Unsupported ECC algorithm!\n");
4260 return -EINVAL;
4261 }
4262}
4263
67a9ad9b
EG		 4264/*
4265 * Check if the chip configuration meet the datasheet requirements.
4266
4267 * If our configuration corrects A bits per B bytes and the minimum
4268 * required correction level is X bits per Y bytes, then we must ensure
4269 * both of the following are true:
4270 *
4271 * (1) A / B >= X / Y
4272 * (2) A >= X
4273 *
4274 * Requirement (1) ensures we can correct for the required bitflip density.
4275 * Requirement (2) ensures we can correct even when all bitflips are clumped
4276 * in the same sector.
4277 */
4278static bool nand_ecc_strength_good(struct mtd_info *mtd)
4279{
862eba51 4280 struct nand_chip *chip = mtd_to_nand(mtd);
67a9ad9b
EG		 4281 struct nand_ecc_ctrl *ecc = &chip->ecc;
4282 int corr, ds_corr;
4283
4284 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4285 /* Not enough information */
4286 return true;
4287
4288 /*
4289 * We get the number of corrected bits per page to compare
4290 * the correction density.
4291 */
4292 corr = (mtd->writesize * ecc->strength) / ecc->size;
4293 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4294
4295 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4296}
3b85c321
DW		 4297
4298/**
4299 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 4300 * @mtd: MTD device structure
3b85c321 4301 *
8b6e50c9
BN		 4302 * This is the second phase of the normal nand_scan() function. It fills out
4303 * all the uninitialized function pointers with the defaults and scans for a
4304 * bad block table if appropriate.
3b85c321
DW		 4305 */
4306int nand_scan_tail(struct mtd_info *mtd)
4307{
862eba51 4308 struct nand_chip *chip = mtd_to_nand(mtd);
97de79e0 4309 struct nand_ecc_ctrl *ecc = &chip->ecc;
f02ea4e6 4310 struct nand_buffers *nbuf;
11eaf6df 4311 int ret;
3b85c321 4312
e2414f4c 4313 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
11eaf6df
EG		 4314 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4315 !(chip->bbt_options & NAND_BBT_USE_FLASH)))
4316 return -EINVAL;
e2414f4c 4317
f02ea4e6
HS		 4318 if (!(chip->options & NAND_OWN_BUFFERS)) {
4319 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4320 + mtd->oobsize * 3, GFP_KERNEL);
4321 if (!nbuf)
4322 return -ENOMEM;
4323 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4324 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4325 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4326
4327 chip->buffers = nbuf;
4328 } else {
4329 if (!chip->buffers)
4330 return -ENOMEM;
4331 }
4bf63fcb 4332
7dcdcbef 4333 /* Set the internal oob buffer location, just after the page data */
784f4d5e 4334 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 4335
7aa65bfd 4336 /*
8b6e50c9 4337 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 4338 */
06f384c9 4339 if (!mtd->ooblayout &&
e4225ae8 4340 !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
61b03bd7 4341 switch (mtd->oobsize) {
1da177e4 4342 case 8:
1da177e4 4343 case 16:
41b207a7 4344 mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops);
1da177e4
LT		 4345 break;
4346 case 64:
81ec5364 4347 case 128:
41b207a7 4348 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
81ec5364 4349 break;
1da177e4 4350 default:
11eaf6df
EG		 4351 WARN(1, "No oob scheme defined for oobsize %d\n",
4352 mtd->oobsize);
4353 ret = -EINVAL;
4354 goto err_free;
1da177e4
LT		 4355 }
4356 }
61b03bd7 4357
956e944c
DW		 4358 if (!chip->write_page)
4359 chip->write_page = nand_write_page;
4360
61b03bd7 4361 /*
8b6e50c9 4362 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 4363 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 4364 */
956e944c 4365
97de79e0 4366 switch (ecc->mode) {
6e0cb135
SN		 4367 case NAND_ECC_HW_OOB_FIRST:
4368 /* Similar to NAND_ECC_HW, but a separate read_page handle */
97de79e0 4369 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
11eaf6df
EG		 4370 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4371 ret = -EINVAL;
4372 goto err_free;
6e0cb135 4373 }
97de79e0
HS		 4374 if (!ecc->read_page)
4375 ecc->read_page = nand_read_page_hwecc_oob_first;
6e0cb135 4376
6dfc6d25 4377 case NAND_ECC_HW:
8b6e50c9 4378 /* Use standard hwecc read page function? */
97de79e0
HS		 4379 if (!ecc->read_page)
4380 ecc->read_page = nand_read_page_hwecc;
4381 if (!ecc->write_page)
4382 ecc->write_page = nand_write_page_hwecc;
4383 if (!ecc->read_page_raw)
4384 ecc->read_page_raw = nand_read_page_raw;
4385 if (!ecc->write_page_raw)
4386 ecc->write_page_raw = nand_write_page_raw;
4387 if (!ecc->read_oob)
4388 ecc->read_oob = nand_read_oob_std;
4389 if (!ecc->write_oob)
4390 ecc->write_oob = nand_write_oob_std;
4391 if (!ecc->read_subpage)
4392 ecc->read_subpage = nand_read_subpage;
44991b3d 4393 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
97de79e0 4394 ecc->write_subpage = nand_write_subpage_hwecc;
f5bbdacc 4395
6dfc6d25 4396 case NAND_ECC_HW_SYNDROME:
97de79e0
HS		 4397 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4398 (!ecc->read_page ||
4399 ecc->read_page == nand_read_page_hwecc ||
4400 !ecc->write_page ||
4401 ecc->write_page == nand_write_page_hwecc)) {
11eaf6df
EG		 4402 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4403 ret = -EINVAL;
4404 goto err_free;
6dfc6d25 4405 }
8b6e50c9 4406 /* Use standard syndrome read/write page function? */
97de79e0
HS		 4407 if (!ecc->read_page)
4408 ecc->read_page = nand_read_page_syndrome;
4409 if (!ecc->write_page)
4410 ecc->write_page = nand_write_page_syndrome;
4411 if (!ecc->read_page_raw)
4412 ecc->read_page_raw = nand_read_page_raw_syndrome;
4413 if (!ecc->write_page_raw)
4414 ecc->write_page_raw = nand_write_page_raw_syndrome;
4415 if (!ecc->read_oob)
4416 ecc->read_oob = nand_read_oob_syndrome;
4417 if (!ecc->write_oob)
4418 ecc->write_oob = nand_write_oob_syndrome;
4419
4420 if (mtd->writesize >= ecc->size) {
4421 if (!ecc->strength) {
11eaf6df
EG		 4422 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4423 ret = -EINVAL;
4424 goto err_free;
e2788c98 4425 }
6dfc6d25 4426 break;
e2788c98 4427 }
2ac63d90
RM		 4428 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4429 ecc->size, mtd->writesize);
97de79e0 4430 ecc->mode = NAND_ECC_SOFT;
e9d4faed 4431 ecc->algo = NAND_ECC_HAMMING;
61b03bd7 4432
6dfc6d25 4433 case NAND_ECC_SOFT:
06f384c9
RM		 4434 ret = nand_set_ecc_soft_ops(mtd);
4435 if (ret) {
11eaf6df
EG		 4436 ret = -EINVAL;
4437 goto err_free;
193bd400
ID		 4438 }
4439 break;
4440
61b03bd7 4441 case NAND_ECC_NONE:
2ac63d90 4442 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
97de79e0
HS		 4443 ecc->read_page = nand_read_page_raw;
4444 ecc->write_page = nand_write_page_raw;
4445 ecc->read_oob = nand_read_oob_std;
4446 ecc->read_page_raw = nand_read_page_raw;
4447 ecc->write_page_raw = nand_write_page_raw;
4448 ecc->write_oob = nand_write_oob_std;
4449 ecc->size = mtd->writesize;
4450 ecc->bytes = 0;
4451 ecc->strength = 0;
1da177e4 4452 break;
956e944c 4453
1da177e4 4454 default:
11eaf6df
EG		 4455 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
4456 ret = -EINVAL;
4457 goto err_free;
1da177e4 4458 }
61b03bd7 4459
9ce244b3 4460 /* For many systems, the standard OOB write also works for raw */
97de79e0
HS		 4461 if (!ecc->read_oob_raw)
4462 ecc->read_oob_raw = ecc->read_oob;
4463 if (!ecc->write_oob_raw)
4464 ecc->write_oob_raw = ecc->write_oob;
9ce244b3 4465
846031d3 4466 /* propagate ecc info to mtd_info */
846031d3
BB		 4467 mtd->ecc_strength = ecc->strength;
4468 mtd->ecc_step_size = ecc->size;
67a9ad9b 4469
7aa65bfd
TG		 4470 /*
4471 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 4472 * mode.
7aa65bfd 4473 */
97de79e0
HS		 4474 ecc->steps = mtd->writesize / ecc->size;
4475 if (ecc->steps * ecc->size != mtd->writesize) {
11eaf6df
EG		 4476 WARN(1, "Invalid ECC parameters\n");
4477 ret = -EINVAL;
4478 goto err_free;
1da177e4 4479 }
97de79e0 4480 ecc->total = ecc->steps * ecc->bytes;
61b03bd7 4481
846031d3
BB		 4482 /*
4483 * The number of bytes available for a client to place data into
4484 * the out of band area.
4485 */
4486 ret = mtd_ooblayout_count_freebytes(mtd);
4487 if (ret < 0)
4488 ret = 0;
4489
4490 mtd->oobavail = ret;
4491
4492 /* ECC sanity check: warn if it's too weak */
4493 if (!nand_ecc_strength_good(mtd))
4494 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4495 mtd->name);
4496
8b6e50c9 4497 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
1d0ed69d 4498 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
97de79e0 4499 switch (ecc->steps) {
29072b96
TG		 4500 case 2:
4501 mtd->subpage_sft = 1;
4502 break;
4503 case 4:
4504 case 8:
81ec5364 4505 case 16:
29072b96
TG		 4506 mtd->subpage_sft = 2;
4507 break;
4508 }
4509 }
4510 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4511
04bbd0ea 4512 /* Initialize state */
ace4dfee 4513 chip->state = FL_READY;
1da177e4 4514
1da177e4 4515 /* Invalidate the pagebuffer reference */
ace4dfee 4516 chip->pagebuf = -1;
1da177e4 4517
a5ff4f10 4518 /* Large page NAND with SOFT_ECC should support subpage reads */
4007e2d1
RL		 4519 switch (ecc->mode) {
4520 case NAND_ECC_SOFT:
4007e2d1
RL		 4521 if (chip->page_shift > 9)
4522 chip->options |= NAND_SUBPAGE_READ;
4523 break;
4524
4525 default:
4526 break;
4527 }
a5ff4f10 4528
1da177e4 4529 /* Fill in remaining MTD driver data */
963d1c28 4530 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
93edbad6
ML		 4531 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4532 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 4533 mtd->_erase = nand_erase;
4534 mtd->_point = NULL;
4535 mtd->_unpoint = NULL;
4536 mtd->_read = nand_read;
4537 mtd->_write = nand_write;
4538 mtd->_panic_write = panic_nand_write;
4539 mtd->_read_oob = nand_read_oob;
4540 mtd->_write_oob = nand_write_oob;
4541 mtd->_sync = nand_sync;
4542 mtd->_lock = NULL;
4543 mtd->_unlock = NULL;
4544 mtd->_suspend = nand_suspend;
4545 mtd->_resume = nand_resume;
72ea4036 4546 mtd->_reboot = nand_shutdown;
8471bb73 4547 mtd->_block_isreserved = nand_block_isreserved;
3c3c10bb
AB		 4548 mtd->_block_isbad = nand_block_isbad;
4549 mtd->_block_markbad = nand_block_markbad;
cbcab65a 4550 mtd->writebufsize = mtd->writesize;
1da177e4 4551
ea3b2ea2
SL		 4552 /*
4553 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4554 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4555 * properly set.
4556 */
4557 if (!mtd->bitflip_threshold)
240181fd 4558 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
1da177e4 4559
0040bf38 4560 /* Check, if we should skip the bad block table scan */
ace4dfee 4561 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 4562 return 0;
1da177e4
LT		 4563
4564 /* Build bad block table */
ace4dfee 4565 return chip->scan_bbt(mtd);
11eaf6df
EG		 4566err_free:
4567 if (!(chip->options & NAND_OWN_BUFFERS))
4568 kfree(chip->buffers);
4569 return ret;
1da177e4 4570}
7351d3a5 4571EXPORT_SYMBOL(nand_scan_tail);
1da177e4 4572
8b6e50c9
BN		 4573/*
4574 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 4575 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 4576 * to call us from in-kernel code if the core NAND support is modular.
4577 */
3b85c321
DW		 4578#ifdef MODULE
4579#define caller_is_module() (1)
4580#else
4581#define caller_is_module() \
a6e6abd5 4582 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 4583#endif
4584
4585/**
4586 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4587 * @mtd: MTD device structure
4588 * @maxchips: number of chips to scan for
3b85c321 4589 *
8b6e50c9
BN		 4590 * This fills out all the uninitialized function pointers with the defaults.
4591 * The flash ID is read and the mtd/chip structures are filled with the
20c07a5b 4592 * appropriate values.
3b85c321
DW		 4593 */
4594int nand_scan(struct mtd_info *mtd, int maxchips)
4595{
4596 int ret;
4597
5e81e88a 4598 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 4599 if (!ret)
4600 ret = nand_scan_tail(mtd);
4601 return ret;
4602}
7351d3a5 4603EXPORT_SYMBOL(nand_scan);
3b85c321 4604
1da177e4 4605/**
61b03bd7 4606 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 4607 * @mtd: MTD device structure
4608 */
e0c7d767 4609void nand_release(struct mtd_info *mtd)
1da177e4 4610{
862eba51 4611 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 4612
e4225ae8 4613 if (chip->ecc.mode == NAND_ECC_SOFT &&
06f384c9 4614 chip->ecc.algo == NAND_ECC_BCH)
193bd400
ID		 4615 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4616
5ffcaf3d 4617 mtd_device_unregister(mtd);
1da177e4 4618
fa671646 4619 /* Free bad block table memory */
ace4dfee 4620 kfree(chip->bbt);
4bf63fcb
DW		 4621 if (!(chip->options & NAND_OWN_BUFFERS))
4622 kfree(chip->buffers);
58373ff0
BN		 4623
4624 /* Free bad block descriptor memory */
4625 if (chip->badblock_pattern && chip->badblock_pattern->options
4626 & NAND_BBT_DYNAMICSTRUCT)
4627 kfree(chip->badblock_pattern);
1da177e4 4628}
e0c7d767 4629EXPORT_SYMBOL_GPL(nand_release);
8fe833c1 4630
e0c7d767 4631MODULE_LICENSE("GPL");
7351d3a5
FF		 4632MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4633MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 4634MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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