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mtd: nand: sunxi: fix subpage write
[deliverable/linux.git] / drivers / mtd / nand / sunxi_nand.c
CommitLineData
1fef62c1
BB		 1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
3 *
4 * Derived from:
5 * https://github.com/yuq/sunxi-nfc-mtd
6 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
7 *
8 * https://github.com/hno/Allwinner-Info
9 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
10 *
11 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
12 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25#include <linux/dma-mapping.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/platform_device.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/of_gpio.h>
1fef62c1
BB		 33#include <linux/mtd/mtd.h>
34#include <linux/mtd/nand.h>
35#include <linux/mtd/partitions.h>
36#include <linux/clk.h>
37#include <linux/delay.h>
38#include <linux/dmaengine.h>
39#include <linux/gpio.h>
40#include <linux/interrupt.h>
166f08c7 41#include <linux/iopoll.h>
1fef62c1
BB		 42
43#define NFC_REG_CTL 0x0000
44#define NFC_REG_ST 0x0004
45#define NFC_REG_INT 0x0008
46#define NFC_REG_TIMING_CTL 0x000C
47#define NFC_REG_TIMING_CFG 0x0010
48#define NFC_REG_ADDR_LOW 0x0014
49#define NFC_REG_ADDR_HIGH 0x0018
50#define NFC_REG_SECTOR_NUM 0x001C
51#define NFC_REG_CNT 0x0020
52#define NFC_REG_CMD 0x0024
53#define NFC_REG_RCMD_SET 0x0028
54#define NFC_REG_WCMD_SET 0x002C
55#define NFC_REG_IO_DATA 0x0030
56#define NFC_REG_ECC_CTL 0x0034
57#define NFC_REG_ECC_ST 0x0038
58#define NFC_REG_DEBUG 0x003C
b6a02c08
BB		 59#define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
60#define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
1fef62c1 61#define NFC_REG_SPARE_AREA 0x00A0
4be4e03e 62#define NFC_REG_PAT_ID 0x00A4
1fef62c1
BB		 63#define NFC_RAM0_BASE 0x0400
64#define NFC_RAM1_BASE 0x0800
65
66/* define bit use in NFC_CTL */
67#define NFC_EN BIT(0)
68#define NFC_RESET BIT(1)
b6a02c08
BB		 69#define NFC_BUS_WIDTH_MSK BIT(2)
70#define NFC_BUS_WIDTH_8 (0 << 2)
71#define NFC_BUS_WIDTH_16 (1 << 2)
72#define NFC_RB_SEL_MSK BIT(3)
73#define NFC_RB_SEL(x) ((x) << 3)
74#define NFC_CE_SEL_MSK GENMASK(26, 24)
75#define NFC_CE_SEL(x) ((x) << 24)
1fef62c1 76#define NFC_CE_CTL BIT(6)
b6a02c08
BB		 77#define NFC_PAGE_SHIFT_MSK GENMASK(11, 8)
78#define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
1fef62c1
BB		 79#define NFC_SAM BIT(12)
80#define NFC_RAM_METHOD BIT(14)
81#define NFC_DEBUG_CTL BIT(31)
82
83/* define bit use in NFC_ST */
84#define NFC_RB_B2R BIT(0)
85#define NFC_CMD_INT_FLAG BIT(1)
86#define NFC_DMA_INT_FLAG BIT(2)
87#define NFC_CMD_FIFO_STATUS BIT(3)
88#define NFC_STA BIT(4)
89#define NFC_NATCH_INT_FLAG BIT(5)
b6a02c08 90#define NFC_RB_STATE(x) BIT(x + 8)
1fef62c1
BB		 91
92/* define bit use in NFC_INT */
93#define NFC_B2R_INT_ENABLE BIT(0)
94#define NFC_CMD_INT_ENABLE BIT(1)
95#define NFC_DMA_INT_ENABLE BIT(2)
96#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
97 NFC_CMD_INT_ENABLE | \
98 NFC_DMA_INT_ENABLE)
99
d052e508
RS		 100/* define bit use in NFC_TIMING_CTL */
101#define NFC_TIMING_CTL_EDO BIT(8)
102
9c618292
RS		 103/* define NFC_TIMING_CFG register layout */
104#define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
105 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
106 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
107 (((tCAD) & 0x7) << 8))
108
1fef62c1 109/* define bit use in NFC_CMD */
b6a02c08
BB		 110#define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0)
111#define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8)
112#define NFC_CMD(x) (x)
113#define NFC_ADR_NUM_MSK GENMASK(18, 16)
114#define NFC_ADR_NUM(x) (((x) - 1) << 16)
1fef62c1
BB		 115#define NFC_SEND_ADR BIT(19)
116#define NFC_ACCESS_DIR BIT(20)
117#define NFC_DATA_TRANS BIT(21)
118#define NFC_SEND_CMD1 BIT(22)
119#define NFC_WAIT_FLAG BIT(23)
120#define NFC_SEND_CMD2 BIT(24)
121#define NFC_SEQ BIT(25)
122#define NFC_DATA_SWAP_METHOD BIT(26)
123#define NFC_ROW_AUTO_INC BIT(27)
124#define NFC_SEND_CMD3 BIT(28)
125#define NFC_SEND_CMD4 BIT(29)
b6a02c08
BB		 126#define NFC_CMD_TYPE_MSK GENMASK(31, 30)
127#define NFC_NORMAL_OP (0 << 30)
128#define NFC_ECC_OP (1 << 30)
129#define NFC_PAGE_OP (2 << 30)
1fef62c1
BB		 130
131/* define bit use in NFC_RCMD_SET */
b6a02c08
BB		 132#define NFC_READ_CMD_MSK GENMASK(7, 0)
133#define NFC_RND_READ_CMD0_MSK GENMASK(15, 8)
134#define NFC_RND_READ_CMD1_MSK GENMASK(23, 16)
1fef62c1
BB		 135
136/* define bit use in NFC_WCMD_SET */
b6a02c08
BB		 137#define NFC_PROGRAM_CMD_MSK GENMASK(7, 0)
138#define NFC_RND_WRITE_CMD_MSK GENMASK(15, 8)
139#define NFC_READ_CMD0_MSK GENMASK(23, 16)
140#define NFC_READ_CMD1_MSK GENMASK(31, 24)
1fef62c1
BB		 141
142/* define bit use in NFC_ECC_CTL */
143#define NFC_ECC_EN BIT(0)
144#define NFC_ECC_PIPELINE BIT(3)
145#define NFC_ECC_EXCEPTION BIT(4)
b6a02c08 146#define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
1fef62c1
BB		 147#define NFC_RANDOM_EN BIT(9)
148#define NFC_RANDOM_DIRECTION BIT(10)
b6a02c08
BB		 149#define NFC_ECC_MODE_MSK GENMASK(15, 12)
150#define NFC_ECC_MODE(x) ((x) << 12)
151#define NFC_RANDOM_SEED_MSK GENMASK(30, 16)
152#define NFC_RANDOM_SEED(x) ((x) << 16)
153
154/* define bit use in NFC_ECC_ST */
155#define NFC_ECC_ERR(x) BIT(x)
614049a8 156#define NFC_ECC_ERR_MSK GENMASK(15, 0)
b6a02c08 157#define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
f8b04746 158#define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff)
1fef62c1
BB		 159
160#define NFC_DEFAULT_TIMEOUT_MS 1000
161
162#define NFC_SRAM_SIZE 1024
163
164#define NFC_MAX_CS 7
165
166/*
167 * Ready/Busy detection type: describes the Ready/Busy detection modes
168 *
169 * @RB_NONE: no external detection available, rely on STATUS command
170 * and software timeouts
171 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
172 * pin of the NAND flash chip must be connected to one of the
173 * native NAND R/B pins (those which can be muxed to the NAND
174 * Controller)
175 * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
176 * pin of the NAND flash chip must be connected to a GPIO capable
177 * pin.
178 */
179enum sunxi_nand_rb_type {
180 RB_NONE,
181 RB_NATIVE,
182 RB_GPIO,
183};
184
185/*
186 * Ready/Busy structure: stores information related to Ready/Busy detection
187 *
188 * @type: the Ready/Busy detection mode
189 * @info: information related to the R/B detection mode. Either a gpio
190 * id or a native R/B id (those supported by the NAND controller).
191 */
192struct sunxi_nand_rb {
193 enum sunxi_nand_rb_type type;
194 union {
195 int gpio;
196 int nativeid;
197 } info;
198};
199
200/*
201 * Chip Select structure: stores information related to NAND Chip Select
202 *
203 * @cs: the NAND CS id used to communicate with a NAND Chip
204 * @rb: the Ready/Busy description
205 */
206struct sunxi_nand_chip_sel {
207 u8 cs;
208 struct sunxi_nand_rb rb;
209};
210
211/*
212 * sunxi HW ECC infos: stores information related to HW ECC support
213 *
214 * @mode: the sunxi ECC mode field deduced from ECC requirements
1fef62c1
BB		 215 */
216struct sunxi_nand_hw_ecc {
217 int mode;
1fef62c1
BB		 218};
219
220/*
221 * NAND chip structure: stores NAND chip device related information
222 *
223 * @node: used to store NAND chips into a list
224 * @nand: base NAND chip structure
225 * @mtd: base MTD structure
226 * @clk_rate: clk_rate required for this NAND chip
9c618292 227 * @timing_cfg TIMING_CFG register value for this NAND chip
1fef62c1
BB		 228 * @selected: current active CS
229 * @nsels: number of CS lines required by the NAND chip
230 * @sels: array of CS lines descriptions
231 */
232struct sunxi_nand_chip {
233 struct list_head node;
234 struct nand_chip nand;
1fef62c1 235 unsigned long clk_rate;
9c618292 236 u32 timing_cfg;
d052e508 237 u32 timing_ctl;
1fef62c1 238 int selected;
e9aa671f
BB		 239 int addr_cycles;
240 u32 addr[2];
241 int cmd_cycles;
242 u8 cmd[2];
1fef62c1
BB		 243 int nsels;
244 struct sunxi_nand_chip_sel sels[0];
245};
246
247static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
248{
249 return container_of(nand, struct sunxi_nand_chip, nand);
250}
251
252/*
253 * NAND Controller structure: stores sunxi NAND controller information
254 *
255 * @controller: base controller structure
256 * @dev: parent device (used to print error messages)
257 * @regs: NAND controller registers
258 * @ahb_clk: NAND Controller AHB clock
259 * @mod_clk: NAND Controller mod clock
260 * @assigned_cs: bitmask describing already assigned CS lines
261 * @clk_rate: NAND controller current clock rate
262 * @chips: a list containing all the NAND chips attached to
263 * this NAND controller
264 * @complete: a completion object used to wait for NAND
265 * controller events
266 */
267struct sunxi_nfc {
268 struct nand_hw_control controller;
269 struct device *dev;
270 void __iomem *regs;
271 struct clk *ahb_clk;
272 struct clk *mod_clk;
273 unsigned long assigned_cs;
274 unsigned long clk_rate;
275 struct list_head chips;
276 struct completion complete;
614049a8 277 struct dma_chan *dmac;
1fef62c1
BB		 278};
279
280static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
281{
282 return container_of(ctrl, struct sunxi_nfc, controller);
283}
284
285static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
286{
287 struct sunxi_nfc *nfc = dev_id;
288 u32 st = readl(nfc->regs + NFC_REG_ST);
289 u32 ien = readl(nfc->regs + NFC_REG_INT);
290
291 if (!(ien & st))
292 return IRQ_NONE;
293
294 if ((ien & st) == ien)
295 complete(&nfc->complete);
296
297 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
298 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
299
300 return IRQ_HANDLED;
301}
302
c0c9dfa8
BB		 303static int sunxi_nfc_wait_events(struct sunxi_nfc *nfc, u32 events,
304 bool use_polling, unsigned int timeout_ms)
1fef62c1 305{
c0c9dfa8 306 int ret;
1fef62c1 307
c0c9dfa8
BB		 308 if (events & ~NFC_INT_MASK)
309 return -EINVAL;
1fef62c1
BB		 310
311 if (!timeout_ms)
312 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
313
c0c9dfa8
BB		 314 if (!use_polling) {
315 init_completion(&nfc->complete);
316
317 writel(events, nfc->regs + NFC_REG_INT);
318
319 ret = wait_for_completion_timeout(&nfc->complete,
320 msecs_to_jiffies(timeout_ms));
321
322 writel(0, nfc->regs + NFC_REG_INT);
323 } else {
324 u32 status;
325
326 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
327 (status & events) == events, 1,
328 timeout_ms * 1000);
1fef62c1
BB		 329 }
330
c0c9dfa8
BB		 331 writel(events & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
332
333 if (ret)
334 dev_err(nfc->dev, "wait interrupt timedout\n");
335
336 return ret;
1fef62c1
BB		 337}
338
339static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
340{
166f08c7
BB		 341 u32 status;
342 int ret;
1fef62c1 343
166f08c7
BB		 344 ret = readl_poll_timeout(nfc->regs + NFC_REG_ST, status,
345 !(status & NFC_CMD_FIFO_STATUS), 1,
346 NFC_DEFAULT_TIMEOUT_MS * 1000);
347 if (ret)
348 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
1fef62c1 349
166f08c7 350 return ret;
1fef62c1
BB		 351}
352
353static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
354{
166f08c7
BB		 355 u32 ctl;
356 int ret;
1fef62c1
BB		 357
358 writel(0, nfc->regs + NFC_REG_ECC_CTL);
359 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
360
166f08c7
BB		 361 ret = readl_poll_timeout(nfc->regs + NFC_REG_CTL, ctl,
362 !(ctl & NFC_RESET), 1,
363 NFC_DEFAULT_TIMEOUT_MS * 1000);
364 if (ret)
365 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
1fef62c1 366
166f08c7 367 return ret;
1fef62c1
BB		 368}
369
614049a8
BB		 370static int sunxi_nfc_dma_op_prepare(struct mtd_info *mtd, const void *buf,
371 int chunksize, int nchunks,
372 enum dma_data_direction ddir,
373 struct scatterlist *sg)
374{
375 struct nand_chip *nand = mtd_to_nand(mtd);
376 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
377 struct dma_async_tx_descriptor *dmad;
378 enum dma_transfer_direction tdir;
379 dma_cookie_t dmat;
380 int ret;
381
382 if (ddir == DMA_FROM_DEVICE)
383 tdir = DMA_DEV_TO_MEM;
384 else
385 tdir = DMA_MEM_TO_DEV;
386
387 sg_init_one(sg, buf, nchunks * chunksize);
388 ret = dma_map_sg(nfc->dev, sg, 1, ddir);
389 if (!ret)
390 return -ENOMEM;
391
392 dmad = dmaengine_prep_slave_sg(nfc->dmac, sg, 1, tdir, DMA_CTRL_ACK);
28f3d01e
WY		 393 if (!dmad) {
394 ret = -EINVAL;
614049a8
BB		 395 goto err_unmap_buf;
396 }
397
398 writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
399 nfc->regs + NFC_REG_CTL);
400 writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
401 writel(chunksize, nfc->regs + NFC_REG_CNT);
402 dmat = dmaengine_submit(dmad);
403
404 ret = dma_submit_error(dmat);
405 if (ret)
406 goto err_clr_dma_flag;
407
408 return 0;
409
410err_clr_dma_flag:
411 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
412 nfc->regs + NFC_REG_CTL);
413
414err_unmap_buf:
415 dma_unmap_sg(nfc->dev, sg, 1, ddir);
416 return ret;
417}
418
419static void sunxi_nfc_dma_op_cleanup(struct mtd_info *mtd,
420 enum dma_data_direction ddir,
421 struct scatterlist *sg)
422{
423 struct nand_chip *nand = mtd_to_nand(mtd);
424 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
425
426 dma_unmap_sg(nfc->dev, sg, 1, ddir);
427 writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
428 nfc->regs + NFC_REG_CTL);
429}
430
1fef62c1
BB		 431static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
432{
4bd4ebcc 433 struct nand_chip *nand = mtd_to_nand(mtd);
1fef62c1
BB		 434 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
435 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
436 struct sunxi_nand_rb *rb;
1fef62c1
BB		 437 int ret;
438
439 if (sunxi_nand->selected < 0)
440 return 0;
441
442 rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
443
444 switch (rb->type) {
445 case RB_NATIVE:
1fef62c1 446 ret = !!(readl(nfc->regs + NFC_REG_ST) &
b6a02c08 447 NFC_RB_STATE(rb->info.nativeid));
1fef62c1
BB		 448 break;
449 case RB_GPIO:
450 ret = gpio_get_value(rb->info.gpio);
451 break;
452 case RB_NONE:
453 default:
454 ret = 0;
455 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
456 break;
457 }
458
459 return ret;
460}
461
462static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
463{
4bd4ebcc 464 struct nand_chip *nand = mtd_to_nand(mtd);
1fef62c1
BB		 465 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
466 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
467 struct sunxi_nand_chip_sel *sel;
468 u32 ctl;
469
470 if (chip > 0 && chip >= sunxi_nand->nsels)
471 return;
472
473 if (chip == sunxi_nand->selected)
474 return;
475
476 ctl = readl(nfc->regs + NFC_REG_CTL) &
b6a02c08 477 ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
1fef62c1
BB		 478
479 if (chip >= 0) {
480 sel = &sunxi_nand->sels[chip];
481
b6a02c08 482 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
68ffbf7f 483 NFC_PAGE_SHIFT(nand->page_shift);
1fef62c1
BB		 484 if (sel->rb.type == RB_NONE) {
485 nand->dev_ready = NULL;
486 } else {
487 nand->dev_ready = sunxi_nfc_dev_ready;
488 if (sel->rb.type == RB_NATIVE)
b6a02c08 489 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
1fef62c1
BB		 490 }
491
492 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
493
494 if (nfc->clk_rate != sunxi_nand->clk_rate) {
495 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
496 nfc->clk_rate = sunxi_nand->clk_rate;
497 }
498 }
499
d052e508 500 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
9c618292 501 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
1fef62c1
BB		 502 writel(ctl, nfc->regs + NFC_REG_CTL);
503
504 sunxi_nand->selected = chip;
505}
506
507static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
508{
4bd4ebcc 509 struct nand_chip *nand = mtd_to_nand(mtd);
1fef62c1
BB		 510 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
511 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
512 int ret;
513 int cnt;
514 int offs = 0;
515 u32 tmp;
516
517 while (len > offs) {
518 cnt = min(len - offs, NFC_SRAM_SIZE);
519
520 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
521 if (ret)
522 break;
523
524 writel(cnt, nfc->regs + NFC_REG_CNT);
525 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
526 writel(tmp, nfc->regs + NFC_REG_CMD);
527
c0c9dfa8 528 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
1fef62c1
BB		 529 if (ret)
530 break;
531
532 if (buf)
533 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
534 cnt);
535 offs += cnt;
536 }
537}
538
539static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
540 int len)
541{
4bd4ebcc 542 struct nand_chip *nand = mtd_to_nand(mtd);
1fef62c1
BB		 543 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
544 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
545 int ret;
546 int cnt;
547 int offs = 0;
548 u32 tmp;
549
550 while (len > offs) {
551 cnt = min(len - offs, NFC_SRAM_SIZE);
552
553 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
554 if (ret)
555 break;
556
557 writel(cnt, nfc->regs + NFC_REG_CNT);
558 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
559 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
560 NFC_ACCESS_DIR;
561 writel(tmp, nfc->regs + NFC_REG_CMD);
562
c0c9dfa8 563 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
1fef62c1
BB		 564 if (ret)
565 break;
566
567 offs += cnt;
568 }
569}
570
571static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
572{
573 uint8_t ret;
574
575 sunxi_nfc_read_buf(mtd, &ret, 1);
576
577 return ret;
578}
579
580static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
581 unsigned int ctrl)
582{
4bd4ebcc 583 struct nand_chip *nand = mtd_to_nand(mtd);
1fef62c1
BB		 584 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
585 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
586 int ret;
1fef62c1
BB		 587
588 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
589 if (ret)
590 return;
591
e9aa671f
BB		 592 if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
593 !(ctrl & (NAND_CLE | NAND_ALE))) {
594 u32 cmd = 0;
1fef62c1 595
e9aa671f
BB		 596 if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
597 return;
598
599 if (sunxi_nand->cmd_cycles--)
600 cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
601
602 if (sunxi_nand->cmd_cycles--) {
603 cmd |= NFC_SEND_CMD2;
604 writel(sunxi_nand->cmd[1],
605 nfc->regs + NFC_REG_RCMD_SET);
606 }
607
608 sunxi_nand->cmd_cycles = 0;
609
610 if (sunxi_nand->addr_cycles) {
611 cmd |= NFC_SEND_ADR |
612 NFC_ADR_NUM(sunxi_nand->addr_cycles);
613 writel(sunxi_nand->addr[0],
614 nfc->regs + NFC_REG_ADDR_LOW);
615 }
616
617 if (sunxi_nand->addr_cycles > 4)
618 writel(sunxi_nand->addr[1],
619 nfc->regs + NFC_REG_ADDR_HIGH);
620
621 writel(cmd, nfc->regs + NFC_REG_CMD);
622 sunxi_nand->addr[0] = 0;
623 sunxi_nand->addr[1] = 0;
624 sunxi_nand->addr_cycles = 0;
c0c9dfa8 625 sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
1fef62c1
BB		 626 }
627
e9aa671f
BB		 628 if (ctrl & NAND_CLE) {
629 sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
630 } else if (ctrl & NAND_ALE) {
631 sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
632 dat << ((sunxi_nand->addr_cycles % 4) * 8);
633 sunxi_nand->addr_cycles++;
634 }
1fef62c1
BB		 635}
636
4be4e03e
BB		 637/* These seed values have been extracted from Allwinner's BSP */
638static const u16 sunxi_nfc_randomizer_page_seeds[] = {
639 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
640 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
641 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
642 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
643 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
644 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
645 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
646 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
647 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
648 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
649 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
650 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
651 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
652 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
653 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
654 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
655};
656
657/*
658 * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
659 * have been generated using
660 * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
661 * the randomizer engine does internally before de/scrambling OOB data.
662 *
663 * Those tables are statically defined to avoid calculating randomizer state
664 * at runtime.
665 */
666static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
667 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
668 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
669 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
670 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
671 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
672 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
673 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
674 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
675 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
676 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
677 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
678 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
679 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
680 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
681 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
682 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
683};
684
685static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
686 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
687 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
688 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
689 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
690 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
691 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
692 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
693 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
694 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
695 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
696 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
697 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
698 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
699 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
700 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
701 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
702};
703
704static u16 sunxi_nfc_randomizer_step(u16 state, int count)
705{
706 state &= 0x7fff;
707
708 /*
709 * This loop is just a simple implementation of a Fibonacci LFSR using
710 * the x16 + x15 + 1 polynomial.
711 */
712 while (count--)
713 state = ((state >> 1) |
714 (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
715
716 return state;
717}
718
719static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
720{
721 const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
46c135c2 722 int mod = mtd_div_by_ws(mtd->erasesize, mtd);
4be4e03e
BB		 723
724 if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
725 mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
726
727 if (ecc) {
728 if (mtd->ecc_step_size == 512)
729 seeds = sunxi_nfc_randomizer_ecc512_seeds;
730 else
731 seeds = sunxi_nfc_randomizer_ecc1024_seeds;
732 }
733
734 return seeds[page % mod];
735}
736
737static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
738 int page, bool ecc)
739{
f671a1f3 740 struct nand_chip *nand = mtd_to_nand(mtd);
4be4e03e
BB		 741 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
742 u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
743 u16 state;
744
745 if (!(nand->options & NAND_NEED_SCRAMBLING))
746 return;
747
748 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
749 state = sunxi_nfc_randomizer_state(mtd, page, ecc);
750 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
751 writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
752}
753
754static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
755{
f671a1f3 756 struct nand_chip *nand = mtd_to_nand(mtd);
4be4e03e
BB		 757 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
758
759 if (!(nand->options & NAND_NEED_SCRAMBLING))
760 return;
761
762 writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
763 nfc->regs + NFC_REG_ECC_CTL);
764}
765
766static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
767{
f671a1f3 768 struct nand_chip *nand = mtd_to_nand(mtd);
4be4e03e
BB		 769 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
770
771 if (!(nand->options & NAND_NEED_SCRAMBLING))
772 return;
773
774 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
775 nfc->regs + NFC_REG_ECC_CTL);
776}
777
778static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
779{
780 u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
781
782 bbm[0] ^= state;
783 bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
784}
785
786static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
787 const uint8_t *buf, int len,
788 bool ecc, int page)
789{
790 sunxi_nfc_randomizer_config(mtd, page, ecc);
791 sunxi_nfc_randomizer_enable(mtd);
792 sunxi_nfc_write_buf(mtd, buf, len);
793 sunxi_nfc_randomizer_disable(mtd);
794}
795
796static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
797 int len, bool ecc, int page)
798{
799 sunxi_nfc_randomizer_config(mtd, page, ecc);
800 sunxi_nfc_randomizer_enable(mtd);
801 sunxi_nfc_read_buf(mtd, buf, len);
802 sunxi_nfc_randomizer_disable(mtd);
803}
804
c9118ece
BB		 805static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
806{
4bd4ebcc 807 struct nand_chip *nand = mtd_to_nand(mtd);
c9118ece
BB		 808 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
809 struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
810 u32 ecc_ctl;
811
812 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
813 ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
814 NFC_ECC_BLOCK_SIZE_MSK);
336de7b1
BB		 815 ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION |
816 NFC_ECC_PIPELINE;
c9118ece
BB		 817
818 writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
819}
820
821static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
822{
4bd4ebcc 823 struct nand_chip *nand = mtd_to_nand(mtd);
c9118ece
BB		 824 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
825
826 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
827 nfc->regs + NFC_REG_ECC_CTL);
828}
829
f363e0fa
BB		 830static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
831{
832 buf[0] = user_data;
833 buf[1] = user_data >> 8;
834 buf[2] = user_data >> 16;
835 buf[3] = user_data >> 24;
836}
837
cc6822fb
BB		 838static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
839{
840 return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
841}
842
843static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct mtd_info *mtd, u8 *oob,
844 int step, bool bbm, int page)
845{
846 struct nand_chip *nand = mtd_to_nand(mtd);
847 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
848
849 sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)),
850 oob);
851
852 /* De-randomize the Bad Block Marker. */
853 if (bbm && (nand->options & NAND_NEED_SCRAMBLING))
854 sunxi_nfc_randomize_bbm(mtd, page, oob);
855}
856
857static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct mtd_info *mtd,
858 const u8 *oob, int step,
859 bool bbm, int page)
860{
861 struct nand_chip *nand = mtd_to_nand(mtd);
862 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
863 u8 user_data[4];
864
865 /* Randomize the Bad Block Marker. */
866 if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) {
867 memcpy(user_data, oob, sizeof(user_data));
868 sunxi_nfc_randomize_bbm(mtd, page, user_data);
869 oob = user_data;
870 }
871
872 writel(sunxi_nfc_buf_to_user_data(oob),
873 nfc->regs + NFC_REG_USER_DATA(step));
874}
875
876static void sunxi_nfc_hw_ecc_update_stats(struct mtd_info *mtd,
877 unsigned int *max_bitflips, int ret)
878{
879 if (ret < 0) {
880 mtd->ecc_stats.failed++;
881 } else {
882 mtd->ecc_stats.corrected += ret;
883 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
884 }
885}
886
887static int sunxi_nfc_hw_ecc_correct(struct mtd_info *mtd, u8 *data, u8 *oob,
614049a8 888 int step, u32 status, bool *erased)
cc6822fb
BB		 889{
890 struct nand_chip *nand = mtd_to_nand(mtd);
891 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
892 struct nand_ecc_ctrl *ecc = &nand->ecc;
614049a8 893 u32 tmp;
cc6822fb
BB		 894
895 *erased = false;
896
cc6822fb
BB		 897 if (status & NFC_ECC_ERR(step))
898 return -EBADMSG;
899
900 if (status & NFC_ECC_PAT_FOUND(step)) {
901 u8 pattern;
902
903 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) {
904 pattern = 0x0;
905 } else {
906 pattern = 0xff;
907 *erased = true;
908 }
909
910 if (data)
911 memset(data, pattern, ecc->size);
912
913 if (oob)
914 memset(oob, pattern, ecc->bytes + 4);
915
916 return 0;
917 }
918
919 tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(step));
920
921 return NFC_ECC_ERR_CNT(step, tmp);
922}
923
913821bd
BB		 924static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
925 u8 *data, int data_off,
926 u8 *oob, int oob_off,
927 int *cur_off,
4be4e03e 928 unsigned int *max_bitflips,
828dec15 929 bool bbm, bool oob_required, int page)
913821bd 930{
4bd4ebcc 931 struct nand_chip *nand = mtd_to_nand(mtd);
913821bd
BB		 932 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
933 struct nand_ecc_ctrl *ecc = &nand->ecc;
4be4e03e 934 int raw_mode = 0;
cc6822fb 935 bool erased;
913821bd
BB		 936 int ret;
937
938 if (*cur_off != data_off)
939 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
940
4be4e03e 941 sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
913821bd 942
74eb9ff5 943 if (data_off + ecc->size != oob_off)
913821bd
BB		 944 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
945
946 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
947 if (ret)
948 return ret;
949
4be4e03e 950 sunxi_nfc_randomizer_enable(mtd);
913821bd
BB		 951 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
952 nfc->regs + NFC_REG_CMD);
953
c0c9dfa8 954 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
4be4e03e 955 sunxi_nfc_randomizer_disable(mtd);
913821bd
BB		 956 if (ret)
957 return ret;
958
4be4e03e
BB		 959 *cur_off = oob_off + ecc->bytes + 4;
960
828dec15 961 ret = sunxi_nfc_hw_ecc_correct(mtd, data, oob_required ? oob : NULL, 0,
614049a8 962 readl(nfc->regs + NFC_REG_ECC_ST),
828dec15 963 &erased);
cc6822fb 964 if (erased)
4be4e03e 965 return 1;
913821bd 966
cc6822fb 967 if (ret < 0) {
4be4e03e
BB		 968 /*
969 * Re-read the data with the randomizer disabled to identify
970 * bitflips in erased pages.
971 */
972 if (nand->options & NAND_NEED_SCRAMBLING) {
973 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
974 nand->read_buf(mtd, data, ecc->size);
cc6822fb
BB		 975 } else {
976 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE,
977 ecc->size);
4be4e03e
BB		 978 }
979
cc6822fb
BB		 980 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
981 nand->read_buf(mtd, oob, ecc->bytes + 4);
982
146b503e
BB		 983 ret = nand_check_erased_ecc_chunk(data, ecc->size,
984 oob, ecc->bytes + 4,
985 NULL, 0, ecc->strength);
4be4e03e
BB		 986 if (ret >= 0)
987 raw_mode = 1;
f363e0fa 988 } else {
cc6822fb 989 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
4be4e03e 990
828dec15
BB		 991 if (oob_required) {
992 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
993 sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4,
994 true, page);
913821bd 995
828dec15
BB		 996 sunxi_nfc_hw_ecc_get_prot_oob_bytes(mtd, oob, 0,
997 bbm, page);
998 }
913821bd
BB		 999 }
1000
cc6822fb
BB		 1001 sunxi_nfc_hw_ecc_update_stats(mtd, max_bitflips, ret);
1002
4be4e03e 1003 return raw_mode;
913821bd
BB		 1004}
1005
35d0e24f 1006static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
4be4e03e
BB		 1007 u8 *oob, int *cur_off,
1008 bool randomize, int page)
35d0e24f 1009{
4bd4ebcc 1010 struct nand_chip *nand = mtd_to_nand(mtd);
35d0e24f
BB		 1011 struct nand_ecc_ctrl *ecc = &nand->ecc;
1012 int offset = ((ecc->bytes + 4) * ecc->steps);
1013 int len = mtd->oobsize - offset;
1014
1015 if (len <= 0)
1016 return;
1017
c4f3ef2c 1018 if (!cur_off || *cur_off != offset)
35d0e24f
BB		 1019 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
1020 offset + mtd->writesize, -1);
1021
4be4e03e
BB		 1022 if (!randomize)
1023 sunxi_nfc_read_buf(mtd, oob + offset, len);
1024 else
1025 sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
1026 false, page);
35d0e24f 1027
c4f3ef2c
BB		 1028 if (cur_off)
1029 *cur_off = mtd->oobsize + mtd->writesize;
35d0e24f
BB		 1030}
1031
614049a8
BB		 1032static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
1033 int oob_required, int page,
1034 int nchunks)
1035{
1036 struct nand_chip *nand = mtd_to_nand(mtd);
1037 bool randomized = nand->options & NAND_NEED_SCRAMBLING;
1038 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1039 struct nand_ecc_ctrl *ecc = &nand->ecc;
1040 unsigned int max_bitflips = 0;
1041 int ret, i, raw_mode = 0;
1042 struct scatterlist sg;
1043 u32 status;
1044
1045 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1046 if (ret)
1047 return ret;
1048
1049 ret = sunxi_nfc_dma_op_prepare(mtd, buf, ecc->size, nchunks,
1050 DMA_FROM_DEVICE, &sg);
1051 if (ret)
1052 return ret;
1053
1054 sunxi_nfc_hw_ecc_enable(mtd);
1055 sunxi_nfc_randomizer_config(mtd, page, false);
1056 sunxi_nfc_randomizer_enable(mtd);
1057
1058 writel((NAND_CMD_RNDOUTSTART << 16) | (NAND_CMD_RNDOUT << 8) |
1059 NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET);
1060
1061 dma_async_issue_pending(nfc->dmac);
1062
1063 writel(NFC_PAGE_OP | NFC_DATA_SWAP_METHOD | NFC_DATA_TRANS,
1064 nfc->regs + NFC_REG_CMD);
1065
1066 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
1067 if (ret)
1068 dmaengine_terminate_all(nfc->dmac);
1069
1070 sunxi_nfc_randomizer_disable(mtd);
1071 sunxi_nfc_hw_ecc_disable(mtd);
1072
1073 sunxi_nfc_dma_op_cleanup(mtd, DMA_FROM_DEVICE, &sg);
1074
1075 if (ret)
1076 return ret;
1077
1078 status = readl(nfc->regs + NFC_REG_ECC_ST);
1079
1080 for (i = 0; i < nchunks; i++) {
1081 int data_off = i * ecc->size;
1082 int oob_off = i * (ecc->bytes + 4);
1083 u8 *data = buf + data_off;
1084 u8 *oob = nand->oob_poi + oob_off;
1085 bool erased;
1086
1087 ret = sunxi_nfc_hw_ecc_correct(mtd, randomized ? data : NULL,
1088 oob_required ? oob : NULL,
1089 i, status, &erased);
1090
1091 /* ECC errors are handled in the second loop. */
1092 if (ret < 0)
1093 continue;
1094
1095 if (oob_required && !erased) {
1096 /* TODO: use DMA to retrieve OOB */
252173c6
BB		 1097 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
1098 mtd->writesize + oob_off, -1);
614049a8
BB		 1099 nand->read_buf(mtd, oob, ecc->bytes + 4);
1100
1101 sunxi_nfc_hw_ecc_get_prot_oob_bytes(mtd, oob, i,
1102 !i, page);
1103 }
1104
1105 if (erased)
1106 raw_mode = 1;
1107
1108 sunxi_nfc_hw_ecc_update_stats(mtd, &max_bitflips, ret);
1109 }
1110
1111 if (status & NFC_ECC_ERR_MSK) {
1112 for (i = 0; i < nchunks; i++) {
1113 int data_off = i * ecc->size;
1114 int oob_off = i * (ecc->bytes + 4);
1115 u8 *data = buf + data_off;
1116 u8 *oob = nand->oob_poi + oob_off;
1117
1118 if (!(status & NFC_ECC_ERR(i)))
1119 continue;
1120
1121 /*
1122 * Re-read the data with the randomizer disabled to
1123 * identify bitflips in erased pages.
1124 */
1125 if (randomized) {
1126 /* TODO: use DMA to read page in raw mode */
1127 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
1128 data_off, -1);
1129 nand->read_buf(mtd, data, ecc->size);
1130 }
1131
1132 /* TODO: use DMA to retrieve OOB */
252173c6
BB		 1133 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
1134 mtd->writesize + oob_off, -1);
614049a8
BB		 1135 nand->read_buf(mtd, oob, ecc->bytes + 4);
1136
1137 ret = nand_check_erased_ecc_chunk(data, ecc->size,
1138 oob, ecc->bytes + 4,
1139 NULL, 0,
1140 ecc->strength);
1141 if (ret >= 0)
1142 raw_mode = 1;
1143
1144 sunxi_nfc_hw_ecc_update_stats(mtd, &max_bitflips, ret);
1145 }
1146 }
1147
1148 if (oob_required)
1149 sunxi_nfc_hw_ecc_read_extra_oob(mtd, nand->oob_poi,
1150 NULL, !raw_mode,
1151 page);
1152
1153 return max_bitflips;
1154}
1155
913821bd
BB		 1156static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
1157 const u8 *data, int data_off,
1158 const u8 *oob, int oob_off,
4be4e03e
BB		 1159 int *cur_off, bool bbm,
1160 int page)
913821bd 1161{
4bd4ebcc 1162 struct nand_chip *nand = mtd_to_nand(mtd);
913821bd
BB		 1163 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1164 struct nand_ecc_ctrl *ecc = &nand->ecc;
1165 int ret;
1166
1167 if (data_off != *cur_off)
1168 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
1169
4be4e03e 1170 sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
913821bd 1171
74eb9ff5 1172 if (data_off + ecc->size != oob_off)
913821bd
BB		 1173 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
1174
1175 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1176 if (ret)
1177 return ret;
1178
4be4e03e 1179 sunxi_nfc_randomizer_enable(mtd);
cc6822fb
BB		 1180 sunxi_nfc_hw_ecc_set_prot_oob_bytes(mtd, oob, 0, bbm, page);
1181
913821bd
BB		 1182 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
1183 NFC_ACCESS_DIR | NFC_ECC_OP,
1184 nfc->regs + NFC_REG_CMD);
1185
c0c9dfa8 1186 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
4be4e03e 1187 sunxi_nfc_randomizer_disable(mtd);
913821bd
BB		 1188 if (ret)
1189 return ret;
1190
1191 *cur_off = oob_off + ecc->bytes + 4;
1192
1193 return 0;
1194}
1195
35d0e24f 1196static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
4be4e03e
BB		 1197 u8 *oob, int *cur_off,
1198 int page)
35d0e24f 1199{
4bd4ebcc 1200 struct nand_chip *nand = mtd_to_nand(mtd);
35d0e24f
BB		 1201 struct nand_ecc_ctrl *ecc = &nand->ecc;
1202 int offset = ((ecc->bytes + 4) * ecc->steps);
1203 int len = mtd->oobsize - offset;
1204
1205 if (len <= 0)
1206 return;
1207
c4f3ef2c 1208 if (!cur_off || *cur_off != offset)
35d0e24f
BB		 1209 nand->cmdfunc(mtd, NAND_CMD_RNDIN,
1210 offset + mtd->writesize, -1);
1211
4be4e03e 1212 sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
35d0e24f 1213
c4f3ef2c
BB		 1214 if (cur_off)
1215 *cur_off = mtd->oobsize + mtd->writesize;
35d0e24f
BB		 1216}
1217
1fef62c1
BB		 1218static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
1219 struct nand_chip *chip, uint8_t *buf,
1220 int oob_required, int page)
1221{
1fef62c1 1222 struct nand_ecc_ctrl *ecc = &chip->ecc;
1fef62c1 1223 unsigned int max_bitflips = 0;
b462551c 1224 int ret, i, cur_off = 0;
4be4e03e 1225 bool raw_mode = false;
1fef62c1 1226
c9118ece 1227 sunxi_nfc_hw_ecc_enable(mtd);
1fef62c1
BB		 1228
1229 for (i = 0; i < ecc->steps; i++) {
b462551c
BB		 1230 int data_off = i * ecc->size;
1231 int oob_off = i * (ecc->bytes + 4);
1232 u8 *data = buf + data_off;
1233 u8 *oob = chip->oob_poi + oob_off;
1234
1235 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1236 oob_off + mtd->writesize,
4be4e03e 1237 &cur_off, &max_bitflips,
828dec15 1238 !i, oob_required, page);
4be4e03e 1239 if (ret < 0)
1fef62c1 1240 return ret;
4be4e03e
BB		 1241 else if (ret)
1242 raw_mode = true;
1fef62c1
BB		 1243 }
1244
35d0e24f 1245 if (oob_required)
4be4e03e
BB		 1246 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1247 !raw_mode, page);
1fef62c1 1248
c9118ece 1249 sunxi_nfc_hw_ecc_disable(mtd);
1fef62c1
BB		 1250
1251 return max_bitflips;
1252}
1253
614049a8
BB		 1254static int sunxi_nfc_hw_ecc_read_page_dma(struct mtd_info *mtd,
1255 struct nand_chip *chip, u8 *buf,
1256 int oob_required, int page)
1257{
1258 int ret;
1259
1260 ret = sunxi_nfc_hw_ecc_read_chunks_dma(mtd, buf, oob_required, page,
1261 chip->ecc.steps);
1262 if (ret >= 0)
1263 return ret;
1264
1265 /* Fallback to PIO mode */
1266 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1);
1267
1268 return sunxi_nfc_hw_ecc_read_page(mtd, chip, buf, oob_required, page);
1269}
1270
fe82ccef
BB		 1271static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
1272 struct nand_chip *chip,
1273 u32 data_offs, u32 readlen,
1274 u8 *bufpoi, int page)
1275{
1276 struct nand_ecc_ctrl *ecc = &chip->ecc;
1277 int ret, i, cur_off = 0;
1278 unsigned int max_bitflips = 0;
1279
1280 sunxi_nfc_hw_ecc_enable(mtd);
1281
1282 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1283 for (i = data_offs / ecc->size;
1284 i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
1285 int data_off = i * ecc->size;
1286 int oob_off = i * (ecc->bytes + 4);
1287 u8 *data = bufpoi + data_off;
1288 u8 *oob = chip->oob_poi + oob_off;
1289
1290 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
1291 oob,
1292 oob_off + mtd->writesize,
828dec15
BB		 1293 &cur_off, &max_bitflips, !i,
1294 false, page);
fe82ccef
BB		 1295 if (ret < 0)
1296 return ret;
1297 }
1298
1299 sunxi_nfc_hw_ecc_disable(mtd);
1300
1301 return max_bitflips;
1302}
1303
614049a8
BB		 1304static int sunxi_nfc_hw_ecc_read_subpage_dma(struct mtd_info *mtd,
1305 struct nand_chip *chip,
1306 u32 data_offs, u32 readlen,
1307 u8 *buf, int page)
1308{
1309 int nchunks = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size);
1310 int ret;
1311
1312 ret = sunxi_nfc_hw_ecc_read_chunks_dma(mtd, buf, false, page, nchunks);
1313 if (ret >= 0)
1314 return ret;
1315
1316 /* Fallback to PIO mode */
1317 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1);
1318
1319 return sunxi_nfc_hw_ecc_read_subpage(mtd, chip, data_offs, readlen,
1320 buf, page);
1321}
1322
1fef62c1
BB		 1323static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
1324 struct nand_chip *chip,
45aaeff9
BB		 1325 const uint8_t *buf, int oob_required,
1326 int page)
1fef62c1 1327{
1fef62c1 1328 struct nand_ecc_ctrl *ecc = &chip->ecc;
b462551c 1329 int ret, i, cur_off = 0;
1fef62c1 1330
c9118ece 1331 sunxi_nfc_hw_ecc_enable(mtd);
1fef62c1
BB		 1332
1333 for (i = 0; i < ecc->steps; i++) {
b462551c
BB		 1334 int data_off = i * ecc->size;
1335 int oob_off = i * (ecc->bytes + 4);
1336 const u8 *data = buf + data_off;
1337 const u8 *oob = chip->oob_poi + oob_off;
1338
1339 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1340 oob_off + mtd->writesize,
4be4e03e 1341 &cur_off, !i, page);
1fef62c1
BB		 1342 if (ret)
1343 return ret;
1344 }
1345
4be4e03e
BB		 1346 if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1347 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1348 &cur_off, page);
1fef62c1 1349
c9118ece 1350 sunxi_nfc_hw_ecc_disable(mtd);
1fef62c1
BB		 1351
1352 return 0;
1353}
1354
03b1d11a
BB		 1355static int sunxi_nfc_hw_ecc_write_subpage(struct mtd_info *mtd,
1356 struct nand_chip *chip,
1357 u32 data_offs, u32 data_len,
1358 const u8 *buf, int oob_required,
1359 int page)
1360{
1361 struct nand_ecc_ctrl *ecc = &chip->ecc;
1362 int ret, i, cur_off = 0;
1363
1364 sunxi_nfc_hw_ecc_enable(mtd);
1365
1366 for (i = data_offs / ecc->size;
1367 i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
1368 int data_off = i * ecc->size;
1369 int oob_off = i * (ecc->bytes + 4);
1370 const u8 *data = buf + data_off;
1371 const u8 *oob = chip->oob_poi + oob_off;
1372
1373 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1374 oob_off + mtd->writesize,
1375 &cur_off, !i, page);
1376 if (ret)
1377 return ret;
1378 }
1379
1380 sunxi_nfc_hw_ecc_disable(mtd);
1381
1382 return 0;
1383}
1384
614049a8
BB		 1385static int sunxi_nfc_hw_ecc_write_page_dma(struct mtd_info *mtd,
1386 struct nand_chip *chip,
1387 const u8 *buf,
1388 int oob_required,
1389 int page)
1390{
1391 struct nand_chip *nand = mtd_to_nand(mtd);
1392 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
1393 struct nand_ecc_ctrl *ecc = &nand->ecc;
1394 struct scatterlist sg;
1395 int ret, i;
1396
1397 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
1398 if (ret)
1399 return ret;
1400
1401 ret = sunxi_nfc_dma_op_prepare(mtd, buf, ecc->size, ecc->steps,
1402 DMA_TO_DEVICE, &sg);
1403 if (ret)
1404 goto pio_fallback;
1405
1406 for (i = 0; i < ecc->steps; i++) {
1407 const u8 *oob = nand->oob_poi + (i * (ecc->bytes + 4));
1408
1409 sunxi_nfc_hw_ecc_set_prot_oob_bytes(mtd, oob, i, !i, page);
1410 }
1411
1412 sunxi_nfc_hw_ecc_enable(mtd);
1413 sunxi_nfc_randomizer_config(mtd, page, false);
1414 sunxi_nfc_randomizer_enable(mtd);
1415
1416 writel((NAND_CMD_RNDIN << 8) | NAND_CMD_PAGEPROG,
1417 nfc->regs + NFC_REG_RCMD_SET);
1418
1419 dma_async_issue_pending(nfc->dmac);
1420
1421 writel(NFC_PAGE_OP | NFC_DATA_SWAP_METHOD |
1422 NFC_DATA_TRANS | NFC_ACCESS_DIR,
1423 nfc->regs + NFC_REG_CMD);
1424
1425 ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
1426 if (ret)
1427 dmaengine_terminate_all(nfc->dmac);
1428
1429 sunxi_nfc_randomizer_disable(mtd);
1430 sunxi_nfc_hw_ecc_disable(mtd);
1431
1432 sunxi_nfc_dma_op_cleanup(mtd, DMA_TO_DEVICE, &sg);
1433
1434 if (ret)
1435 return ret;
1436
1437 if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1438 /* TODO: use DMA to transfer extra OOB bytes ? */
1439 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1440 NULL, page);
1441
1442 return 0;
1443
1444pio_fallback:
1445 return sunxi_nfc_hw_ecc_write_page(mtd, chip, buf, oob_required, page);
1446}
1447
1fef62c1
BB		 1448static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
1449 struct nand_chip *chip,
1450 uint8_t *buf, int oob_required,
1451 int page)
1452{
1fef62c1 1453 struct nand_ecc_ctrl *ecc = &chip->ecc;
1fef62c1 1454 unsigned int max_bitflips = 0;
b462551c 1455 int ret, i, cur_off = 0;
4be4e03e 1456 bool raw_mode = false;
1fef62c1 1457
c9118ece 1458 sunxi_nfc_hw_ecc_enable(mtd);
1fef62c1
BB		 1459
1460 for (i = 0; i < ecc->steps; i++) {
b462551c
BB		 1461 int data_off = i * (ecc->size + ecc->bytes + 4);
1462 int oob_off = data_off + ecc->size;
1463 u8 *data = buf + (i * ecc->size);
1464 u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1465
1466 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1467 oob_off, &cur_off,
828dec15
BB		 1468 &max_bitflips, !i,
1469 oob_required,
1470 page);
4be4e03e 1471 if (ret < 0)
1fef62c1 1472 return ret;
4be4e03e
BB		 1473 else if (ret)
1474 raw_mode = true;
1fef62c1
BB		 1475 }
1476
35d0e24f 1477 if (oob_required)
4be4e03e
BB		 1478 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1479 !raw_mode, page);
1fef62c1 1480
c9118ece 1481 sunxi_nfc_hw_ecc_disable(mtd);
1fef62c1
BB		 1482
1483 return max_bitflips;
1484}
1485
1486static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
1487 struct nand_chip *chip,
1488 const uint8_t *buf,
45aaeff9 1489 int oob_required, int page)
1fef62c1 1490{
1fef62c1 1491 struct nand_ecc_ctrl *ecc = &chip->ecc;
b462551c 1492 int ret, i, cur_off = 0;
1fef62c1 1493
c9118ece 1494 sunxi_nfc_hw_ecc_enable(mtd);
1fef62c1
BB		 1495
1496 for (i = 0; i < ecc->steps; i++) {
b462551c
BB		 1497 int data_off = i * (ecc->size + ecc->bytes + 4);
1498 int oob_off = data_off + ecc->size;
1499 const u8 *data = buf + (i * ecc->size);
1500 const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1fef62c1 1501
b462551c 1502 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
4be4e03e
BB		 1503 oob, oob_off, &cur_off,
1504 false, page);
1fef62c1
BB		 1505 if (ret)
1506 return ret;
1fef62c1
BB		 1507 }
1508
4be4e03e
BB		 1509 if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1510 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1511 &cur_off, page);
1fef62c1 1512
c9118ece 1513 sunxi_nfc_hw_ecc_disable(mtd);
1fef62c1
BB		 1514
1515 return 0;
1516}
1517
1c1bdd6f
BB		 1518static int sunxi_nfc_hw_common_ecc_read_oob(struct mtd_info *mtd,
1519 struct nand_chip *chip,
1520 int page)
1521{
1522 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1523
1524 chip->pagebuf = -1;
1525
1526 return chip->ecc.read_page(mtd, chip, chip->buffers->databuf, 1, page);
1527}
1528
1529static int sunxi_nfc_hw_common_ecc_write_oob(struct mtd_info *mtd,
1530 struct nand_chip *chip,
1531 int page)
1532{
1533 int ret, status;
1534
1535 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0, page);
1536
1537 chip->pagebuf = -1;
1538
1539 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1540 ret = chip->ecc.write_page(mtd, chip, chip->buffers->databuf, 1, page);
1541 if (ret)
1542 return ret;
1543
1544 /* Send command to program the OOB data */
1545 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1546
1547 status = chip->waitfunc(mtd, chip);
1548
1549 return status & NAND_STATUS_FAIL ? -EIO : 0;
1550}
1551
9c618292
RS		 1552static const s32 tWB_lut[] = {6, 12, 16, 20};
1553static const s32 tRHW_lut[] = {4, 8, 12, 20};
1554
1555static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
1556 u32 clk_period)
1557{
1558 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
1559 int i;
1560
1561 for (i = 0; i < lut_size; i++) {
1562 if (clk_cycles <= lut[i])
1563 return i;
1564 }
1565
1566 /* Doesn't fit */
1567 return -EINVAL;
1568}
1569
1570#define sunxi_nand_lookup_timing(l, p, c) \
1571 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
1572
1fef62c1
BB		 1573static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
1574 const struct nand_sdr_timings *timings)
1575{
9c618292 1576 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
1fef62c1 1577 u32 min_clk_period = 0;
9c618292 1578 s32 tWB, tADL, tWHR, tRHW, tCAD;
2d43457f 1579 long real_clk_rate;
1fef62c1
BB		 1580
1581 /* T1 <=> tCLS */
1582 if (timings->tCLS_min > min_clk_period)
1583 min_clk_period = timings->tCLS_min;
1584
1585 /* T2 <=> tCLH */
1586 if (timings->tCLH_min > min_clk_period)
1587 min_clk_period = timings->tCLH_min;
1588
1589 /* T3 <=> tCS */
1590 if (timings->tCS_min > min_clk_period)
1591 min_clk_period = timings->tCS_min;
1592
1593 /* T4 <=> tCH */
1594 if (timings->tCH_min > min_clk_period)
1595 min_clk_period = timings->tCH_min;
1596
1597 /* T5 <=> tWP */
1598 if (timings->tWP_min > min_clk_period)
1599 min_clk_period = timings->tWP_min;
1600
1601 /* T6 <=> tWH */
1602 if (timings->tWH_min > min_clk_period)
1603 min_clk_period = timings->tWH_min;
1604
1605 /* T7 <=> tALS */
1606 if (timings->tALS_min > min_clk_period)
1607 min_clk_period = timings->tALS_min;
1608
1609 /* T8 <=> tDS */
1610 if (timings->tDS_min > min_clk_period)
1611 min_clk_period = timings->tDS_min;
1612
1613 /* T9 <=> tDH */
1614 if (timings->tDH_min > min_clk_period)
1615 min_clk_period = timings->tDH_min;
1616
1617 /* T10 <=> tRR */
1618 if (timings->tRR_min > (min_clk_period * 3))
1619 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1620
1621 /* T11 <=> tALH */
1622 if (timings->tALH_min > min_clk_period)
1623 min_clk_period = timings->tALH_min;
1624
1625 /* T12 <=> tRP */
1626 if (timings->tRP_min > min_clk_period)
1627 min_clk_period = timings->tRP_min;
1628
1629 /* T13 <=> tREH */
1630 if (timings->tREH_min > min_clk_period)
1631 min_clk_period = timings->tREH_min;
1632
1633 /* T14 <=> tRC */
1634 if (timings->tRC_min > (min_clk_period * 2))
1635 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1636
1637 /* T15 <=> tWC */
1638 if (timings->tWC_min > (min_clk_period * 2))
1639 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1640
9c618292 1641 /* T16 - T19 + tCAD */
5abcd95d
BB		 1642 if (timings->tWB_max > (min_clk_period * 20))
1643 min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20);
1644
1645 if (timings->tADL_min > (min_clk_period * 32))
1646 min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32);
1647
1648 if (timings->tWHR_min > (min_clk_period * 32))
1649 min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32);
1650
1651 if (timings->tRHW_min > (min_clk_period * 20))
1652 min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20);
1653
9c618292
RS		 1654 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1655 min_clk_period);
1656 if (tWB < 0) {
1657 dev_err(nfc->dev, "unsupported tWB\n");
1658 return tWB;
1659 }
1660
1661 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1662 if (tADL > 3) {
1663 dev_err(nfc->dev, "unsupported tADL\n");
1664 return -EINVAL;
1665 }
1666
1667 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1668 if (tWHR > 3) {
1669 dev_err(nfc->dev, "unsupported tWHR\n");
1670 return -EINVAL;
1671 }
1672
1673 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1674 min_clk_period);
1675 if (tRHW < 0) {
1676 dev_err(nfc->dev, "unsupported tRHW\n");
1677 return tRHW;
1678 }
1679
1680 /*
1681 * TODO: according to ONFI specs this value only applies for DDR NAND,
1682 * but Allwinner seems to set this to 0x7. Mimic them for now.
1683 */
1684 tCAD = 0x7;
1685
1686 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
1687 chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
1fef62c1
BB		 1688
1689 /* Convert min_clk_period from picoseconds to nanoseconds */
1690 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
1691
1692 /*
2f9992e0
BB		 1693 * Unlike what is stated in Allwinner datasheet, the clk_rate should
1694 * be set to (1 / min_clk_period), and not (2 / min_clk_period).
1695 * This new formula was verified with a scope and validated by
1696 * Allwinner engineers.
1fef62c1 1697 */
2f9992e0 1698 chip->clk_rate = NSEC_PER_SEC / min_clk_period;
2d43457f
BB		 1699 real_clk_rate = clk_round_rate(nfc->mod_clk, chip->clk_rate);
1700
1701 /*
1702 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
1703 * output cycle timings shall be used if the host drives tRC less than
1704 * 30 ns.
1705 */
1706 min_clk_period = NSEC_PER_SEC / real_clk_rate;
1707 chip->timing_ctl = ((min_clk_period * 2) < 30) ?
1708 NFC_TIMING_CTL_EDO : 0;
1fef62c1 1709
1fef62c1
BB		 1710 return 0;
1711}
1712
1713static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
1714 struct device_node *np)
1715{
32e9f2d8 1716 struct mtd_info *mtd = nand_to_mtd(&chip->nand);
1fef62c1
BB		 1717 const struct nand_sdr_timings *timings;
1718 int ret;
1719 int mode;
1720
1721 mode = onfi_get_async_timing_mode(&chip->nand);
1722 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
1723 mode = chip->nand.onfi_timing_mode_default;
1724 } else {
1725 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
7eadd47f 1726 int i;
1fef62c1
BB		 1727
1728 mode = fls(mode) - 1;
1729 if (mode < 0)
1730 mode = 0;
1731
1732 feature[0] = mode;
7eadd47f 1733 for (i = 0; i < chip->nsels; i++) {
32e9f2d8
BB		 1734 chip->nand.select_chip(mtd, i);
1735 ret = chip->nand.onfi_set_features(mtd, &chip->nand,
1fef62c1
BB		 1736 ONFI_FEATURE_ADDR_TIMING_MODE,
1737 feature);
32e9f2d8 1738 chip->nand.select_chip(mtd, -1);
7eadd47f
SR		 1739 if (ret)
1740 return ret;
1741 }
1fef62c1
BB		 1742 }
1743
1744 timings = onfi_async_timing_mode_to_sdr_timings(mode);
1745 if (IS_ERR(timings))
1746 return PTR_ERR(timings);
1747
1748 return sunxi_nand_chip_set_timings(chip, timings);
1749}
1750
c66811e6
BB		 1751static int sunxi_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
1752 struct mtd_oob_region *oobregion)
1753{
1754 struct nand_chip *nand = mtd_to_nand(mtd);
1755 struct nand_ecc_ctrl *ecc = &nand->ecc;
1756
1757 if (section >= ecc->steps)
1758 return -ERANGE;
1759
1760 oobregion->offset = section * (ecc->bytes + 4) + 4;
1761 oobregion->length = ecc->bytes;
1762
1763 return 0;
1764}
1765
1766static int sunxi_nand_ooblayout_free(struct mtd_info *mtd, int section,
1767 struct mtd_oob_region *oobregion)
1768{
1769 struct nand_chip *nand = mtd_to_nand(mtd);
1770 struct nand_ecc_ctrl *ecc = &nand->ecc;
1771
1772 if (section > ecc->steps)
1773 return -ERANGE;
1774
1775 /*
1776 * The first 2 bytes are used for BB markers, hence we
1777 * only have 2 bytes available in the first user data
1778 * section.
1779 */
1780 if (!section && ecc->mode == NAND_ECC_HW) {
1781 oobregion->offset = 2;
1782 oobregion->length = 2;
1783
1784 return 0;
1785 }
1786
1787 oobregion->offset = section * (ecc->bytes + 4);
1788
1789 if (section < ecc->steps)
1790 oobregion->length = 4;
1791 else
1792 oobregion->offset = mtd->oobsize - oobregion->offset;
1793
1794 return 0;
1795}
1796
1797static const struct mtd_ooblayout_ops sunxi_nand_ooblayout_ops = {
1798 .ecc = sunxi_nand_ooblayout_ecc,
1799 .free = sunxi_nand_ooblayout_free,
1800};
1801
1fef62c1
BB		 1802static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1803 struct nand_ecc_ctrl *ecc,
1804 struct device_node *np)
1805{
1806 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
4bd4ebcc 1807 struct nand_chip *nand = mtd_to_nand(mtd);
1fef62c1
BB		 1808 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1809 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1810 struct sunxi_nand_hw_ecc *data;
1fef62c1
BB		 1811 int nsectors;
1812 int ret;
1813 int i;
1814
1815 data = kzalloc(sizeof(*data), GFP_KERNEL);
1816 if (!data)
1817 return -ENOMEM;
1818
a92c721d
BB		 1819 if (ecc->size != 512 && ecc->size != 1024)
1820 return -EINVAL;
1821
872164e4
BB		 1822 /* Prefer 1k ECC chunk over 512 ones */
1823 if (ecc->size == 512 && mtd->writesize > 512) {
1824 ecc->size = 1024;
1825 ecc->strength *= 2;
1826 }
1827
1fef62c1
BB		 1828 /* Add ECC info retrieval from DT */
1829 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1830 if (ecc->strength <= strengths[i])
1831 break;
1832 }
1833
1834 if (i >= ARRAY_SIZE(strengths)) {
1835 dev_err(nfc->dev, "unsupported strength\n");
1836 ret = -ENOTSUPP;
1837 goto err;
1838 }
1839
1840 data->mode = i;
1841
1842 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1843 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1844
1845 /* HW ECC always work with even numbers of ECC bytes */
1846 ecc->bytes = ALIGN(ecc->bytes, 2);
1847
1fef62c1
BB		 1848 nsectors = mtd->writesize / ecc->size;
1849
1850 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1851 ret = -EINVAL;
1852 goto err;
1853 }
1854
1c1bdd6f
BB		 1855 ecc->read_oob = sunxi_nfc_hw_common_ecc_read_oob;
1856 ecc->write_oob = sunxi_nfc_hw_common_ecc_write_oob;
c66811e6 1857 mtd_set_ooblayout(mtd, &sunxi_nand_ooblayout_ops);
1fef62c1
BB		 1858 ecc->priv = data;
1859
1860 return 0;
1861
1862err:
1863 kfree(data);
1864
1865 return ret;
1866}
1867
1868static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1869{
1870 kfree(ecc->priv);
1871}
1872
1873static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1874 struct nand_ecc_ctrl *ecc,
1875 struct device_node *np)
1876{
614049a8
BB		 1877 struct nand_chip *nand = mtd_to_nand(mtd);
1878 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1879 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1fef62c1
BB		 1880 int ret;
1881
1882 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1883 if (ret)
1884 return ret;
1885
614049a8
BB		 1886 if (nfc->dmac) {
1887 ecc->read_page = sunxi_nfc_hw_ecc_read_page_dma;
1888 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage_dma;
1889 ecc->write_page = sunxi_nfc_hw_ecc_write_page_dma;
1890 nand->options |= NAND_USE_BOUNCE_BUFFER;
1891 } else {
1892 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1893 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
1894 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1895 }
1896
03b1d11a
BB		 1897 /* TODO: support DMA for raw accesses and subpage write */
1898 ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
1c1bdd6f
BB		 1899 ecc->read_oob_raw = nand_read_oob_std;
1900 ecc->write_oob_raw = nand_write_oob_std;
fe82ccef 1901 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
1fef62c1
BB		 1902
1903 return 0;
1904}
1905
1906static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1907 struct nand_ecc_ctrl *ecc,
1908 struct device_node *np)
1909{
1fef62c1
BB		 1910 int ret;
1911
1912 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1913 if (ret)
1914 return ret;
1915
1916 ecc->prepad = 4;
1917 ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1918 ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1c1bdd6f
BB		 1919 ecc->read_oob_raw = nand_read_oob_syndrome;
1920 ecc->write_oob_raw = nand_write_oob_syndrome;
1fef62c1 1921
1fef62c1
BB		 1922 return 0;
1923}
1924
1925static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1926{
1927 switch (ecc->mode) {
1928 case NAND_ECC_HW:
1929 case NAND_ECC_HW_SYNDROME:
1930 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1931 break;
1932 case NAND_ECC_NONE:
1fef62c1
BB		 1933 default:
1934 break;
1935 }
1936}
1937
1938static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1939 struct device_node *np)
1940{
4bd4ebcc 1941 struct nand_chip *nand = mtd_to_nand(mtd);
1fef62c1
BB		 1942 int ret;
1943
a3d22a55 1944 if (!ecc->size) {
1fef62c1
BB		 1945 ecc->size = nand->ecc_step_ds;
1946 ecc->strength = nand->ecc_strength_ds;
1947 }
1948
1949 if (!ecc->size || !ecc->strength)
1950 return -EINVAL;
1951
1fef62c1 1952 switch (ecc->mode) {
1fef62c1
BB		 1953 case NAND_ECC_HW:
1954 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
1955 if (ret)
1956 return ret;
1957 break;
1958 case NAND_ECC_HW_SYNDROME:
1959 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
1960 if (ret)
1961 return ret;
1962 break;
1963 case NAND_ECC_NONE:
1fef62c1
BB		 1964 case NAND_ECC_SOFT:
1965 break;
1966 default:
1967 return -EINVAL;
1968 }
1969
1970 return 0;
1971}
1972
1973static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1974 struct device_node *np)
1975{
1976 const struct nand_sdr_timings *timings;
1977 struct sunxi_nand_chip *chip;
1fef62c1
BB		 1978 struct mtd_info *mtd;
1979 struct nand_chip *nand;
1980 int nsels;
1981 int ret;
1982 int i;
1983 u32 tmp;
1984
1985 if (!of_get_property(np, "reg", &nsels))
1986 return -EINVAL;
1987
1988 nsels /= sizeof(u32);
1989 if (!nsels) {
1990 dev_err(dev, "invalid reg property size\n");
1991 return -EINVAL;
1992 }
1993
1994 chip = devm_kzalloc(dev,
1995 sizeof(*chip) +
1996 (nsels * sizeof(struct sunxi_nand_chip_sel)),
1997 GFP_KERNEL);
1998 if (!chip) {
1999 dev_err(dev, "could not allocate chip\n");
2000 return -ENOMEM;
2001 }
2002
2003 chip->nsels = nsels;
2004 chip->selected = -1;
2005
2006 for (i = 0; i < nsels; i++) {
2007 ret = of_property_read_u32_index(np, "reg", i, &tmp);
2008 if (ret) {
2009 dev_err(dev, "could not retrieve reg property: %d\n",
2010 ret);
2011 return ret;
2012 }
2013
2014 if (tmp > NFC_MAX_CS) {
2015 dev_err(dev,
2016 "invalid reg value: %u (max CS = 7)\n",
2017 tmp);
2018 return -EINVAL;
2019 }
2020
2021 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
2022 dev_err(dev, "CS %d already assigned\n", tmp);
2023 return -EINVAL;
2024 }
2025
2026 chip->sels[i].cs = tmp;
2027
2028 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
2029 tmp < 2) {
2030 chip->sels[i].rb.type = RB_NATIVE;
2031 chip->sels[i].rb.info.nativeid = tmp;
2032 } else {
2033 ret = of_get_named_gpio(np, "rb-gpios", i);
2034 if (ret >= 0) {
2035 tmp = ret;
2036 chip->sels[i].rb.type = RB_GPIO;
2037 chip->sels[i].rb.info.gpio = tmp;
2038 ret = devm_gpio_request(dev, tmp, "nand-rb");
2039 if (ret)
2040 return ret;
2041
2042 ret = gpio_direction_input(tmp);
2043 if (ret)
2044 return ret;
2045 } else {
2046 chip->sels[i].rb.type = RB_NONE;
2047 }
2048 }
2049 }
2050
1fef62c1
BB		 2051 nand = &chip->nand;
2052 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
2053 nand->chip_delay = 200;
2054 nand->controller = &nfc->controller;
a3d22a55
BB		 2055 /*
2056 * Set the ECC mode to the default value in case nothing is specified
2057 * in the DT.
2058 */
2059 nand->ecc.mode = NAND_ECC_HW;
63752199 2060 nand_set_flash_node(nand, np);
1fef62c1
BB		 2061 nand->select_chip = sunxi_nfc_select_chip;
2062 nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
2063 nand->read_buf = sunxi_nfc_read_buf;
2064 nand->write_buf = sunxi_nfc_write_buf;
2065 nand->read_byte = sunxi_nfc_read_byte;
2066
32e9f2d8 2067 mtd = nand_to_mtd(nand);
1fef62c1 2068 mtd->dev.parent = dev;
1fef62c1 2069
9edb4700
BB		 2070 timings = onfi_async_timing_mode_to_sdr_timings(0);
2071 if (IS_ERR(timings)) {
2072 ret = PTR_ERR(timings);
2073 dev_err(dev,
2074 "could not retrieve timings for ONFI mode 0: %d\n",
2075 ret);
2076 return ret;
2077 }
2078
2079 ret = sunxi_nand_chip_set_timings(chip, timings);
2080 if (ret) {
2081 dev_err(dev, "could not configure chip timings: %d\n", ret);
2082 return ret;
2083 }
2084
1fef62c1
BB		 2085 ret = nand_scan_ident(mtd, nsels, NULL);
2086 if (ret)
2087 return ret;
2088
a3d22a55
BB		 2089 if (nand->bbt_options & NAND_BBT_USE_FLASH)
2090 nand->bbt_options |= NAND_BBT_NO_OOB;
2091
4be4e03e
BB		 2092 if (nand->options & NAND_NEED_SCRAMBLING)
2093 nand->options |= NAND_NO_SUBPAGE_WRITE;
2094
fe82ccef
BB		 2095 nand->options |= NAND_SUBPAGE_READ;
2096
1fef62c1
BB		 2097 ret = sunxi_nand_chip_init_timings(chip, np);
2098 if (ret) {
2099 dev_err(dev, "could not configure chip timings: %d\n", ret);
2100 return ret;
2101 }
2102
2103 ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
2104 if (ret) {
2105 dev_err(dev, "ECC init failed: %d\n", ret);
2106 return ret;
2107 }
2108
2109 ret = nand_scan_tail(mtd);
2110 if (ret) {
2111 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
2112 return ret;
2113 }
2114
a61ae81a 2115 ret = mtd_device_register(mtd, NULL, 0);
1fef62c1
BB		 2116 if (ret) {
2117 dev_err(dev, "failed to register mtd device: %d\n", ret);
2118 nand_release(mtd);
2119 return ret;
2120 }
2121
2122 list_add_tail(&chip->node, &nfc->chips);
2123
2124 return 0;
2125}
2126
2127static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
2128{
2129 struct device_node *np = dev->of_node;
2130 struct device_node *nand_np;
2131 int nchips = of_get_child_count(np);
2132 int ret;
2133
2134 if (nchips > 8) {
2135 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
2136 return -EINVAL;
2137 }
2138
2139 for_each_child_of_node(np, nand_np) {
2140 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
a81c0f07
JL		 2141 if (ret) {
2142 of_node_put(nand_np);
1fef62c1 2143 return ret;
a81c0f07 2144 }
1fef62c1
BB		 2145 }
2146
2147 return 0;
2148}
2149
2150static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
2151{
2152 struct sunxi_nand_chip *chip;
2153
2154 while (!list_empty(&nfc->chips)) {
2155 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
2156 node);
32e9f2d8 2157 nand_release(nand_to_mtd(&chip->nand));
1fef62c1 2158 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
8e375ccd 2159 list_del(&chip->node);
1fef62c1
BB		 2160 }
2161}
2162
2163static int sunxi_nfc_probe(struct platform_device *pdev)
2164{
2165 struct device *dev = &pdev->dev;
2166 struct resource *r;
2167 struct sunxi_nfc *nfc;
2168 int irq;
2169 int ret;
2170
2171 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
2172 if (!nfc)
2173 return -ENOMEM;
2174
2175 nfc->dev = dev;
2176 spin_lock_init(&nfc->controller.lock);
2177 init_waitqueue_head(&nfc->controller.wq);
2178 INIT_LIST_HEAD(&nfc->chips);
2179
2180 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2181 nfc->regs = devm_ioremap_resource(dev, r);
2182 if (IS_ERR(nfc->regs))
2183 return PTR_ERR(nfc->regs);
2184
2185 irq = platform_get_irq(pdev, 0);
2186 if (irq < 0) {
2187 dev_err(dev, "failed to retrieve irq\n");
2188 return irq;
2189 }
2190
2191 nfc->ahb_clk = devm_clk_get(dev, "ahb");
2192 if (IS_ERR(nfc->ahb_clk)) {
2193 dev_err(dev, "failed to retrieve ahb clk\n");
2194 return PTR_ERR(nfc->ahb_clk);
2195 }
2196
2197 ret = clk_prepare_enable(nfc->ahb_clk);
2198 if (ret)
2199 return ret;
2200
2201 nfc->mod_clk = devm_clk_get(dev, "mod");
2202 if (IS_ERR(nfc->mod_clk)) {
2203 dev_err(dev, "failed to retrieve mod clk\n");
2204 ret = PTR_ERR(nfc->mod_clk);
2205 goto out_ahb_clk_unprepare;
2206 }
2207
2208 ret = clk_prepare_enable(nfc->mod_clk);
2209 if (ret)
2210 goto out_ahb_clk_unprepare;
2211
2212 ret = sunxi_nfc_rst(nfc);
2213 if (ret)
2214 goto out_mod_clk_unprepare;
2215
2216 writel(0, nfc->regs + NFC_REG_INT);
2217 ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
2218 0, "sunxi-nand", nfc);
2219 if (ret)
2220 goto out_mod_clk_unprepare;
2221
614049a8
BB		 2222 nfc->dmac = dma_request_slave_channel(dev, "rxtx");
2223 if (nfc->dmac) {
2224 struct dma_slave_config dmac_cfg = { };
2225
2226 dmac_cfg.src_addr = r->start + NFC_REG_IO_DATA;
2227 dmac_cfg.dst_addr = dmac_cfg.src_addr;
2228 dmac_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2229 dmac_cfg.dst_addr_width = dmac_cfg.src_addr_width;
2230 dmac_cfg.src_maxburst = 4;
2231 dmac_cfg.dst_maxburst = 4;
2232 dmaengine_slave_config(nfc->dmac, &dmac_cfg);
2233 } else {
2234 dev_warn(dev, "failed to request rxtx DMA channel\n");
2235 }
2236
1fef62c1
BB		 2237 platform_set_drvdata(pdev, nfc);
2238
1fef62c1
BB		 2239 ret = sunxi_nand_chips_init(dev, nfc);
2240 if (ret) {
2241 dev_err(dev, "failed to init nand chips\n");
614049a8 2242 goto out_release_dmac;
1fef62c1
BB		 2243 }
2244
2245 return 0;
2246
614049a8
BB		 2247out_release_dmac:
2248 if (nfc->dmac)
2249 dma_release_channel(nfc->dmac);
1fef62c1
BB		 2250out_mod_clk_unprepare:
2251 clk_disable_unprepare(nfc->mod_clk);
2252out_ahb_clk_unprepare:
2253 clk_disable_unprepare(nfc->ahb_clk);
2254
2255 return ret;
2256}
2257
2258static int sunxi_nfc_remove(struct platform_device *pdev)
2259{
2260 struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
2261
2262 sunxi_nand_chips_cleanup(nfc);
614049a8
BB		 2263 if (nfc->dmac)
2264 dma_release_channel(nfc->dmac);
dd26a458
BB		 2265 clk_disable_unprepare(nfc->mod_clk);
2266 clk_disable_unprepare(nfc->ahb_clk);
1fef62c1
BB		 2267
2268 return 0;
2269}
2270
2271static const struct of_device_id sunxi_nfc_ids[] = {
2272 { .compatible = "allwinner,sun4i-a10-nand" },
2273 { /* sentinel */ }
2274};
2275MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
2276
2277static struct platform_driver sunxi_nfc_driver = {
2278 .driver = {
2279 .name = "sunxi_nand",
2280 .of_match_table = sunxi_nfc_ids,
2281 },
2282 .probe = sunxi_nfc_probe,
2283 .remove = sunxi_nfc_remove,
2284};
2285module_platform_driver(sunxi_nfc_driver);
2286
2287MODULE_LICENSE("GPL v2");
2288MODULE_AUTHOR("Boris BREZILLON");
2289MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
2290MODULE_ALIAS("platform:sunxi_nand");
Linux kernel - Deliverables
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