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dsa: mv88e6xxx: hide unused functions
[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
19b2f97e 21#include <linux/jiffies.h>
91da11f8 22#include <linux/list.h>
14c7b3c3 23#include <linux/mdio.h>
2bbba277 24#include <linux/module.h>
caac8545 25#include <linux/of_device.h>
b516d453 26#include <linux/of_mdio.h>
91da11f8 27#include <linux/netdevice.h>
c8c1b39a 28#include <linux/gpio/consumer.h>
91da11f8 29#include <linux/phy.h>
c8f0b869 30#include <net/dsa.h>
1f36faf2 31#include <net/switchdev.h>
91da11f8
LB		 32#include "mv88e6xxx.h"
33
fad09c73 34static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 35{
fad09c73
VD		 36 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
37 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 38 dump_stack();
39 }
40}
41
914b32f6
VD		 42/* The switch ADDR[4:1] configuration pins define the chip SMI device address
43 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
44 *
45 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
46 * is the only device connected to the SMI master. In this mode it responds to
47 * all 32 possible SMI addresses, and thus maps directly the internal devices.
48 *
49 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
50 * multiple devices to share the SMI interface. In this mode it responds to only
51 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 52 */
914b32f6 53
fad09c73 54static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 55 int addr, int reg, u16 *val)
56{
fad09c73 57 if (!chip->smi_ops)
914b32f6
VD		 58 return -EOPNOTSUPP;
59
fad09c73 60 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 61}
62
fad09c73 63static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 64 int addr, int reg, u16 val)
65{
fad09c73 66 if (!chip->smi_ops)
914b32f6
VD		 67 return -EOPNOTSUPP;
68
fad09c73 69 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 70}
71
fad09c73 72static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 73 int addr, int reg, u16 *val)
74{
75 int ret;
76
fad09c73 77 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 78 if (ret < 0)
79 return ret;
80
81 *val = ret & 0xffff;
82
83 return 0;
84}
85
fad09c73 86static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 87 int addr, int reg, u16 val)
88{
89 int ret;
90
fad09c73 91 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 92 if (ret < 0)
93 return ret;
94
95 return 0;
96}
97
98static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
99 .read = mv88e6xxx_smi_single_chip_read,
100 .write = mv88e6xxx_smi_single_chip_write,
101};
102
fad09c73 103static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 104{
105 int ret;
106 int i;
107
108 for (i = 0; i < 16; i++) {
fad09c73 109 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 110 if (ret < 0)
111 return ret;
112
cca8b133 113 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 114 return 0;
115 }
116
117 return -ETIMEDOUT;
118}
119
fad09c73 120static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 121 int addr, int reg, u16 *val)
91da11f8
LB		 122{
123 int ret;
124
3675c8d7 125 /* Wait for the bus to become free. */
fad09c73 126 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 127 if (ret < 0)
128 return ret;
129
3675c8d7 130 /* Transmit the read command. */
fad09c73 131 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 132 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 133 if (ret < 0)
134 return ret;
135
3675c8d7 136 /* Wait for the read command to complete. */
fad09c73 137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 138 if (ret < 0)
139 return ret;
140
3675c8d7 141 /* Read the data. */
fad09c73 142 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 143 if (ret < 0)
144 return ret;
145
914b32f6 146 *val = ret & 0xffff;
91da11f8 147
914b32f6 148 return 0;
8d6d09e7
GR		 149}
150
fad09c73 151static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 152 int addr, int reg, u16 val)
91da11f8
LB		 153{
154 int ret;
155
3675c8d7 156 /* Wait for the bus to become free. */
fad09c73 157 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 158 if (ret < 0)
159 return ret;
160
3675c8d7 161 /* Transmit the data to write. */
fad09c73 162 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 163 if (ret < 0)
164 return ret;
165
3675c8d7 166 /* Transmit the write command. */
fad09c73 167 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 168 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 169 if (ret < 0)
170 return ret;
171
3675c8d7 172 /* Wait for the write command to complete. */
fad09c73 173 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 174 if (ret < 0)
175 return ret;
176
177 return 0;
178}
179
914b32f6
VD		 180static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
181 .read = mv88e6xxx_smi_multi_chip_read,
182 .write = mv88e6xxx_smi_multi_chip_write,
183};
184
fad09c73 185static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 186 int addr, int reg, u16 *val)
187{
188 int err;
189
fad09c73 190 assert_reg_lock(chip);
914b32f6 191
fad09c73 192 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 193 if (err)
194 return err;
195
fad09c73 196 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 197 addr, reg, *val);
198
199 return 0;
200}
201
fad09c73 202static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
914b32f6 203 int addr, int reg, u16 val)
91da11f8 204{
914b32f6
VD		 205 int err;
206
fad09c73 207 assert_reg_lock(chip);
91da11f8 208
fad09c73 209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 210 if (err)
211 return err;
212
fad09c73 213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 214 addr, reg, val);
215
914b32f6
VD		 216 return 0;
217}
218
f22ab641
VD		 219/* Indirect write to single pointer-data register with an Update bit */
220static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
221 u16 update)
222{
223 u16 val;
224 int i, err;
225
226 /* Wait until the previous operation is completed */
227 for (i = 0; i < 16; ++i) {
228 err = mv88e6xxx_read(chip, addr, reg, &val);
229 if (err)
230 return err;
231
232 if (!(val & BIT(15)))
233 break;
234 }
235
236 if (i == 16)
237 return -ETIMEDOUT;
238
239 /* Set the Update bit to trigger a write operation */
240 val = BIT(15) | update;
241
242 return mv88e6xxx_write(chip, addr, reg, val);
243}
244
fad09c73 245static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
914b32f6
VD		 246{
247 u16 val;
248 int err;
249
fad09c73 250 err = mv88e6xxx_read(chip, addr, reg, &val);
914b32f6
VD		 251 if (err)
252 return err;
253
254 return val;
255}
256
fad09c73 257static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
914b32f6
VD		 258 int reg, u16 val)
259{
fad09c73 260 return mv88e6xxx_write(chip, addr, reg, val);
8d6d09e7
GR		 261}
262
fad09c73 263static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
03a4a540 264 int addr, int regnum)
91da11f8
LB		 265{
266 if (addr >= 0)
fad09c73 267 return _mv88e6xxx_reg_read(chip, addr, regnum);
91da11f8
LB		 268 return 0xffff;
269}
270
fad09c73 271static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
03a4a540 272 int addr, int regnum, u16 val)
91da11f8
LB		 273{
274 if (addr >= 0)
fad09c73 275 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
91da11f8
LB		 276 return 0;
277}
278
fad09c73 279static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
2e5f0320
LB		 280{
281 int ret;
19b2f97e 282 unsigned long timeout;
2e5f0320 283
fad09c73 284 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 285 if (ret < 0)
286 return ret;
287
fad09c73 288 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
8c9983a2 289 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 290 if (ret)
291 return ret;
2e5f0320 292
19b2f97e
BG		 293 timeout = jiffies + 1 * HZ;
294 while (time_before(jiffies, timeout)) {
fad09c73 295 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 296 if (ret < 0)
297 return ret;
298
19b2f97e 299 usleep_range(1000, 2000);
cca8b133
AL		 300 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
301 GLOBAL_STATUS_PPU_POLLING)
85686581 302 return 0;
2e5f0320
LB		 303 }
304
305 return -ETIMEDOUT;
306}
307
fad09c73 308static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 309{
48ace4ef 310 int ret, err;
19b2f97e 311 unsigned long timeout;
2e5f0320 312
fad09c73 313 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 314 if (ret < 0)
315 return ret;
316
fad09c73 317 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
762eb67b 318 ret | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 319 if (err)
320 return err;
2e5f0320 321
19b2f97e
BG		 322 timeout = jiffies + 1 * HZ;
323 while (time_before(jiffies, timeout)) {
fad09c73 324 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 325 if (ret < 0)
326 return ret;
327
19b2f97e 328 usleep_range(1000, 2000);
cca8b133
AL		 329 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
330 GLOBAL_STATUS_PPU_POLLING)
85686581 331 return 0;
2e5f0320
LB		 332 }
333
334 return -ETIMEDOUT;
335}
336
337static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
338{
fad09c73 339 struct mv88e6xxx_chip *chip;
2e5f0320 340
fad09c73 341 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 342
fad09c73 343 mutex_lock(&chip->reg_lock);
762eb67b 344
fad09c73
VD		 345 if (mutex_trylock(&chip->ppu_mutex)) {
346 if (mv88e6xxx_ppu_enable(chip) == 0)
347 chip->ppu_disabled = 0;
348 mutex_unlock(&chip->ppu_mutex);
2e5f0320 349 }
762eb67b 350
fad09c73 351 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 352}
353
354static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
355{
fad09c73 356 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 357
fad09c73 358 schedule_work(&chip->ppu_work);
2e5f0320
LB		 359}
360
fad09c73 361static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 362{
2e5f0320
LB		 363 int ret;
364
fad09c73 365 mutex_lock(&chip->ppu_mutex);
2e5f0320 366
3675c8d7 367 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 368 * we can access the PHY registers. If it was already
369 * disabled, cancel the timer that is going to re-enable
370 * it.
371 */
fad09c73
VD		 372 if (!chip->ppu_disabled) {
373 ret = mv88e6xxx_ppu_disable(chip);
85686581 374 if (ret < 0) {
fad09c73 375 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 376 return ret;
377 }
fad09c73 378 chip->ppu_disabled = 1;
2e5f0320 379 } else {
fad09c73 380 del_timer(&chip->ppu_timer);
85686581 381 ret = 0;
2e5f0320
LB		 382 }
383
384 return ret;
385}
386
fad09c73 387static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 388{
3675c8d7 389 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 390 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
391 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 392}
393
fad09c73 394static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 395{
fad09c73
VD		 396 mutex_init(&chip->ppu_mutex);
397 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
398 init_timer(&chip->ppu_timer);
399 chip->ppu_timer.data = (unsigned long)chip;
400 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
2e5f0320
LB		 401}
402
fad09c73 403static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
03a4a540 404 int regnum)
2e5f0320
LB		 405{
406 int ret;
407
fad09c73 408 ret = mv88e6xxx_ppu_access_get(chip);
2e5f0320 409 if (ret >= 0) {
fad09c73
VD		 410 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
411 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 412 }
413
414 return ret;
415}
416
fad09c73 417static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
03a4a540 418 int regnum, u16 val)
2e5f0320
LB		 419{
420 int ret;
421
fad09c73 422 ret = mv88e6xxx_ppu_access_get(chip);
2e5f0320 423 if (ret >= 0) {
fad09c73
VD		 424 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
425 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 426 }
427
428 return ret;
429}
2e5f0320 430
fad09c73 431static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 432{
fad09c73 433 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 434}
435
fad09c73 436static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 437{
fad09c73 438 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 439}
440
fad09c73 441static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 442{
fad09c73 443 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 444}
445
fad09c73 446static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 447{
fad09c73 448 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 449}
450
fad09c73 451static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 452{
fad09c73 453 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 454}
455
fad09c73 456static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 457{
fad09c73 458 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 459}
460
fad09c73 461static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 462{
fad09c73 463 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 464}
465
fad09c73 466static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 467{
fad09c73 468 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 469}
470
fad09c73 471static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
f74df0be 472{
fad09c73 473 return chip->info->num_databases;
f74df0be
VD		 474}
475
fad09c73 476static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
b426e5f7
VD		 477{
478 /* Does the device have dedicated FID registers for ATU and VTU ops? */
fad09c73
VD		 479 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
480 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
b426e5f7
VD		 481 return true;
482
483 return false;
484}
485
dea87024
AL		 486/* We expect the switch to perform auto negotiation if there is a real
487 * phy. However, in the case of a fixed link phy, we force the port
488 * settings from the fixed link settings.
489 */
f81ec90f
VD		 490static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
491 struct phy_device *phydev)
dea87024 492{
fad09c73 493 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49052871
AL		 494 u32 reg;
495 int ret;
dea87024
AL		 496
497 if (!phy_is_pseudo_fixed_link(phydev))
498 return;
499
fad09c73 500 mutex_lock(&chip->reg_lock);
dea87024 501
fad09c73 502 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
dea87024
AL		 503 if (ret < 0)
504 goto out;
505
506 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
507 PORT_PCS_CTRL_FORCE_LINK |
508 PORT_PCS_CTRL_DUPLEX_FULL |
509 PORT_PCS_CTRL_FORCE_DUPLEX |
510 PORT_PCS_CTRL_UNFORCED);
511
512 reg |= PORT_PCS_CTRL_FORCE_LINK;
513 if (phydev->link)
57d32310 514 reg |= PORT_PCS_CTRL_LINK_UP;
dea87024 515
fad09c73 516 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
dea87024
AL		 517 goto out;
518
519 switch (phydev->speed) {
520 case SPEED_1000:
521 reg |= PORT_PCS_CTRL_1000;
522 break;
523 case SPEED_100:
524 reg |= PORT_PCS_CTRL_100;
525 break;
526 case SPEED_10:
527 reg |= PORT_PCS_CTRL_10;
528 break;
529 default:
530 pr_info("Unknown speed");
531 goto out;
532 }
533
534 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
535 if (phydev->duplex == DUPLEX_FULL)
536 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
537
fad09c73
VD		 538 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
539 (port >= chip->info->num_ports - 2)) {
e7e72ac0
AL		 540 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
541 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
542 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
543 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
544 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
545 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
546 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
547 }
fad09c73 548 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
dea87024
AL		 549
550out:
fad09c73 551 mutex_unlock(&chip->reg_lock);
dea87024
AL		 552}
553
fad09c73 554static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 555{
556 int ret;
557 int i;
558
559 for (i = 0; i < 10; i++) {
fad09c73 560 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 561 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 562 return 0;
563 }
564
565 return -ETIMEDOUT;
566}
567
fad09c73 568static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8
LB		 569{
570 int ret;
571
fad09c73 572 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
f3a8b6b6
AL		 573 port = (port + 1) << 5;
574
3675c8d7 575 /* Snapshot the hardware statistics counters for this port. */
fad09c73 576 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 577 GLOBAL_STATS_OP_CAPTURE_PORT |
578 GLOBAL_STATS_OP_HIST_RX_TX | port);
579 if (ret < 0)
580 return ret;
91da11f8 581
3675c8d7 582 /* Wait for the snapshotting to complete. */
fad09c73 583 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 584 if (ret < 0)
585 return ret;
586
587 return 0;
588}
589
fad09c73 590static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 591 int stat, u32 *val)
91da11f8
LB		 592{
593 u32 _val;
594 int ret;
595
596 *val = 0;
597
fad09c73 598 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 599 GLOBAL_STATS_OP_READ_CAPTURED |
600 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 601 if (ret < 0)
602 return;
603
fad09c73 604 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 605 if (ret < 0)
606 return;
607
fad09c73 608 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 609 if (ret < 0)
610 return;
611
612 _val = ret << 16;
613
fad09c73 614 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 615 if (ret < 0)
616 return;
617
618 *val = _val | ret;
619}
620
e413e7e1 621static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 622 { "in_good_octets", 8, 0x00, BANK0, },
623 { "in_bad_octets", 4, 0x02, BANK0, },
624 { "in_unicast", 4, 0x04, BANK0, },
625 { "in_broadcasts", 4, 0x06, BANK0, },
626 { "in_multicasts", 4, 0x07, BANK0, },
627 { "in_pause", 4, 0x16, BANK0, },
628 { "in_undersize", 4, 0x18, BANK0, },
629 { "in_fragments", 4, 0x19, BANK0, },
630 { "in_oversize", 4, 0x1a, BANK0, },
631 { "in_jabber", 4, 0x1b, BANK0, },
632 { "in_rx_error", 4, 0x1c, BANK0, },
633 { "in_fcs_error", 4, 0x1d, BANK0, },
634 { "out_octets", 8, 0x0e, BANK0, },
635 { "out_unicast", 4, 0x10, BANK0, },
636 { "out_broadcasts", 4, 0x13, BANK0, },
637 { "out_multicasts", 4, 0x12, BANK0, },
638 { "out_pause", 4, 0x15, BANK0, },
639 { "excessive", 4, 0x11, BANK0, },
640 { "collisions", 4, 0x1e, BANK0, },
641 { "deferred", 4, 0x05, BANK0, },
642 { "single", 4, 0x14, BANK0, },
643 { "multiple", 4, 0x17, BANK0, },
644 { "out_fcs_error", 4, 0x03, BANK0, },
645 { "late", 4, 0x1f, BANK0, },
646 { "hist_64bytes", 4, 0x08, BANK0, },
647 { "hist_65_127bytes", 4, 0x09, BANK0, },
648 { "hist_128_255bytes", 4, 0x0a, BANK0, },
649 { "hist_256_511bytes", 4, 0x0b, BANK0, },
650 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
651 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
652 { "sw_in_discards", 4, 0x10, PORT, },
653 { "sw_in_filtered", 2, 0x12, PORT, },
654 { "sw_out_filtered", 2, 0x13, PORT, },
655 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
662 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
663 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
664 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
665 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
666 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
667 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
668 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
669 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
670 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
671 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
672 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
673 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
674 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
675 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
676 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
677 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
679 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
680 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 681};
682
fad09c73 683static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 684 struct mv88e6xxx_hw_stat *stat)
e413e7e1 685{
f5e2ed02
AL		 686 switch (stat->type) {
687 case BANK0:
e413e7e1 688 return true;
f5e2ed02 689 case BANK1:
fad09c73 690 return mv88e6xxx_6320_family(chip);
f5e2ed02 691 case PORT:
fad09c73
VD		 692 return mv88e6xxx_6095_family(chip) ||
693 mv88e6xxx_6185_family(chip) ||
694 mv88e6xxx_6097_family(chip) ||
695 mv88e6xxx_6165_family(chip) ||
696 mv88e6xxx_6351_family(chip) ||
697 mv88e6xxx_6352_family(chip);
91da11f8 698 }
f5e2ed02 699 return false;
91da11f8
LB		 700}
701
fad09c73 702static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 703 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 704 int port)
705{
80c4627b
AL		 706 u32 low;
707 u32 high = 0;
708 int ret;
709 u64 value;
710
f5e2ed02
AL		 711 switch (s->type) {
712 case PORT:
fad09c73 713 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
80c4627b
AL		 714 if (ret < 0)
715 return UINT64_MAX;
716
717 low = ret;
718 if (s->sizeof_stat == 4) {
fad09c73 719 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
f5e2ed02 720 s->reg + 1);
80c4627b
AL		 721 if (ret < 0)
722 return UINT64_MAX;
723 high = ret;
724 }
f5e2ed02
AL		 725 break;
726 case BANK0:
727 case BANK1:
fad09c73 728 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 729 if (s->sizeof_stat == 8)
fad09c73 730 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 731 }
732 value = (((u64)high) << 16) | low;
733 return value;
734}
735
f81ec90f
VD		 736static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
737 uint8_t *data)
91da11f8 738{
fad09c73 739 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 740 struct mv88e6xxx_hw_stat *stat;
741 int i, j;
91da11f8 742
f5e2ed02
AL		 743 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
744 stat = &mv88e6xxx_hw_stats[i];
fad09c73 745 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 746 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
747 ETH_GSTRING_LEN);
748 j++;
749 }
91da11f8 750 }
e413e7e1
AL		 751}
752
f81ec90f 753static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 754{
fad09c73 755 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 756 struct mv88e6xxx_hw_stat *stat;
757 int i, j;
758
759 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
760 stat = &mv88e6xxx_hw_stats[i];
fad09c73 761 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 762 j++;
763 }
764 return j;
e413e7e1
AL		 765}
766
f81ec90f
VD		 767static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
768 uint64_t *data)
e413e7e1 769{
fad09c73 770 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f5e2ed02
AL		 771 struct mv88e6xxx_hw_stat *stat;
772 int ret;
773 int i, j;
774
fad09c73 775 mutex_lock(&chip->reg_lock);
f5e2ed02 776
fad09c73 777 ret = _mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 778 if (ret < 0) {
fad09c73 779 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 780 return;
781 }
782 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
783 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 784 if (mv88e6xxx_has_stat(chip, stat)) {
785 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 786 j++;
787 }
788 }
789
fad09c73 790 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 791}
792
f81ec90f 793static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 794{
795 return 32 * sizeof(u16);
796}
797
f81ec90f
VD		 798static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
799 struct ethtool_regs *regs, void *_p)
a1ab91f3 800{
fad09c73 801 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
a1ab91f3
GR		 802 u16 *p = _p;
803 int i;
804
805 regs->version = 0;
806
807 memset(p, 0xff, 32 * sizeof(u16));
808
fad09c73 809 mutex_lock(&chip->reg_lock);
23062513 810
a1ab91f3
GR		 811 for (i = 0; i < 32; i++) {
812 int ret;
813
fad09c73 814 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
a1ab91f3
GR		 815 if (ret >= 0)
816 p[i] = ret;
817 }
23062513 818
fad09c73 819 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 820}
821
fad09c73 822static int _mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg, int offset,
3898c148 823 u16 mask)
f3044683
AL		 824{
825 unsigned long timeout = jiffies + HZ / 10;
826
827 while (time_before(jiffies, timeout)) {
828 int ret;
829
fad09c73 830 ret = _mv88e6xxx_reg_read(chip, reg, offset);
3898c148
AL		 831 if (ret < 0)
832 return ret;
f3044683
AL		 833 if (!(ret & mask))
834 return 0;
835
836 usleep_range(1000, 2000);
837 }
838 return -ETIMEDOUT;
839}
840
fad09c73 841static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip)
f3044683 842{
fad09c73 843 return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148 844 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 845}
846
fad09c73 847static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 848{
fad09c73 849 return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
cca8b133 850 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 851}
852
fad09c73 853static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
158bc065 854 int addr, int regnum)
f3044683
AL		 855{
856 int ret;
857
fad09c73 858 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 859 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
860 regnum);
861 if (ret < 0)
862 return ret;
f3044683 863
fad09c73 864 ret = mv88e6xxx_mdio_wait(chip);
f3044683
AL		 865 if (ret < 0)
866 return ret;
867
fad09c73 868 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA);
158bc065
AL		 869
870 return ret;
f3044683
AL		 871}
872
fad09c73 873static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
158bc065 874 int addr, int regnum, u16 val)
f3044683 875{
3898c148
AL		 876 int ret;
877
fad09c73 878 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
3898c148
AL		 879 if (ret < 0)
880 return ret;
f3044683 881
fad09c73 882 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 883 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
884 regnum);
885
fad09c73 886 return mv88e6xxx_mdio_wait(chip);
f3044683
AL		 887}
888
f81ec90f
VD		 889static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
890 struct ethtool_eee *e)
11b3b45d 891{
fad09c73 892 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
11b3b45d
GR		 893 int reg;
894
fad09c73 895 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 896 return -EOPNOTSUPP;
897
fad09c73 898 mutex_lock(&chip->reg_lock);
2f40c698 899
fad09c73 900 reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
11b3b45d 901 if (reg < 0)
2f40c698 902 goto out;
11b3b45d
GR		 903
904 e->eee_enabled = !!(reg & 0x0200);
905 e->tx_lpi_enabled = !!(reg & 0x0100);
906
fad09c73 907 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
11b3b45d 908 if (reg < 0)
2f40c698 909 goto out;
11b3b45d 910
cca8b133 911 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 912 reg = 0;
11b3b45d 913
2f40c698 914out:
fad09c73 915 mutex_unlock(&chip->reg_lock);
2f40c698 916 return reg;
11b3b45d
GR		 917}
918
f81ec90f
VD		 919static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
920 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 921{
fad09c73 922 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2f40c698 923 int reg;
11b3b45d
GR		 924 int ret;
925
fad09c73 926 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 927 return -EOPNOTSUPP;
928
fad09c73 929 mutex_lock(&chip->reg_lock);
11b3b45d 930
fad09c73 931 ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
2f40c698
AL		 932 if (ret < 0)
933 goto out;
934
935 reg = ret & ~0x0300;
936 if (e->eee_enabled)
937 reg |= 0x0200;
938 if (e->tx_lpi_enabled)
939 reg |= 0x0100;
940
fad09c73 941 ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
2f40c698 942out:
fad09c73 943 mutex_unlock(&chip->reg_lock);
2f40c698
AL		 944
945 return ret;
11b3b45d
GR		 946}
947
fad09c73 948static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2
GR		 949{
950 int ret;
951
fad09c73
VD		 952 if (mv88e6xxx_has_fid_reg(chip)) {
953 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
954 fid);
b426e5f7
VD		 955 if (ret < 0)
956 return ret;
fad09c73 957 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 958 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
fad09c73 959 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
11ea809f
VD		 960 if (ret < 0)
961 return ret;
962
fad09c73 963 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
11ea809f
VD		 964 (ret & 0xfff) |
965 ((fid << 8) & 0xf000));
966 if (ret < 0)
967 return ret;
968
969 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
970 cmd |= fid & 0xf;
b426e5f7
VD		 971 }
972
fad09c73 973 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 974 if (ret < 0)
975 return ret;
976
fad09c73 977 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 978}
979
fad09c73 980static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 981 struct mv88e6xxx_atu_entry *entry)
982{
983 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
984
985 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
986 unsigned int mask, shift;
987
988 if (entry->trunk) {
989 data |= GLOBAL_ATU_DATA_TRUNK;
990 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
991 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
992 } else {
993 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
994 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
995 }
996
997 data |= (entry->portv_trunkid << shift) & mask;
998 }
999
fad09c73 1000 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
37705b73
VD		 1001}
1002
fad09c73 1003static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1004 struct mv88e6xxx_atu_entry *entry,
1005 bool static_too)
facd95b2 1006{
7fb5e755
VD		 1007 int op;
1008 int err;
facd95b2 1009
fad09c73 1010 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1011 if (err)
1012 return err;
facd95b2 1013
fad09c73 1014 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1015 if (err)
1016 return err;
1017
1018 if (entry->fid) {
7fb5e755
VD		 1019 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1020 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1021 } else {
1022 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1023 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1024 }
1025
fad09c73 1026 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1027}
1028
fad09c73 1029static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1030 u16 fid, bool static_too)
7fb5e755
VD		 1031{
1032 struct mv88e6xxx_atu_entry entry = {
1033 .fid = fid,
1034 .state = 0, /* EntryState bits must be 0 */
1035 };
70cc99d1 1036
fad09c73 1037 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1038}
1039
fad09c73 1040static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1041 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1042{
1043 struct mv88e6xxx_atu_entry entry = {
1044 .trunk = false,
1045 .fid = fid,
1046 };
1047
1048 /* EntryState bits must be 0xF */
1049 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1050
1051 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1052 entry.portv_trunkid = (to_port & 0x0f) << 4;
1053 entry.portv_trunkid |= from_port & 0x0f;
1054
fad09c73 1055 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1056}
1057
fad09c73 1058static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1059 int port, bool static_too)
9f4d55d2
VD		 1060{
1061 /* Destination port 0xF means remove the entries */
fad09c73 1062 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1063}
1064
2d9deae4
VD		 1065static const char * const mv88e6xxx_port_state_names[] = {
1066 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1067 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1068 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1069 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1070};
1071
fad09c73 1072static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
158bc065 1073 u8 state)
facd95b2 1074{
fad09c73 1075 struct dsa_switch *ds = chip->ds;
c3ffe6d2 1076 int reg, ret = 0;
facd95b2
GR		 1077 u8 oldstate;
1078
fad09c73 1079 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1080 if (reg < 0)
1081 return reg;
facd95b2 1082
cca8b133 1083 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1084
facd95b2
GR		 1085 if (oldstate != state) {
1086 /* Flush forwarding database if we're moving a port
1087 * from Learning or Forwarding state to Disabled or
1088 * Blocking or Listening state.
1089 */
2d9deae4 1090 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
57d32310
VD		 1091 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1092 (state == PORT_CONTROL_STATE_DISABLED ||
1093 state == PORT_CONTROL_STATE_BLOCKING)) {
fad09c73 1094 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
facd95b2 1095 if (ret)
2d9deae4 1096 return ret;
facd95b2 1097 }
2d9deae4 1098
cca8b133 1099 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
fad09c73 1100 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
cca8b133 1101 reg);
2d9deae4
VD		 1102 if (ret)
1103 return ret;
1104
c8b09808 1105 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
2d9deae4
VD		 1106 mv88e6xxx_port_state_names[state],
1107 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1108 }
1109
facd95b2
GR		 1110 return ret;
1111}
1112
fad09c73 1113static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1114{
fad09c73
VD		 1115 struct net_device *bridge = chip->ports[port].bridge_dev;
1116 const u16 mask = (1 << chip->info->num_ports) - 1;
1117 struct dsa_switch *ds = chip->ds;
b7666efe 1118 u16 output_ports = 0;
ede8098d 1119 int reg;
b7666efe
VD		 1120 int i;
1121
1122 /* allow CPU port or DSA link(s) to send frames to every port */
1123 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1124 output_ports = mask;
1125 } else {
fad09c73 1126 for (i = 0; i < chip->info->num_ports; ++i) {
b7666efe 1127 /* allow sending frames to every group member */
fad09c73 1128 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1129 output_ports |= BIT(i);
1130
1131 /* allow sending frames to CPU port and DSA link(s) */
1132 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1133 output_ports |= BIT(i);
1134 }
1135 }
1136
1137 /* prevent frames from going back out of the port they came in on */
1138 output_ports &= ~BIT(port);
facd95b2 1139
fad09c73 1140 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
ede8098d
VD		 1141 if (reg < 0)
1142 return reg;
facd95b2 1143
ede8098d
VD		 1144 reg &= ~mask;
1145 reg |= output_ports & mask;
facd95b2 1146
fad09c73 1147 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1148}
1149
f81ec90f
VD		 1150static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1151 u8 state)
facd95b2 1152{
fad09c73 1153 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
facd95b2 1154 int stp_state;
553eb544 1155 int err;
facd95b2
GR		 1156
1157 switch (state) {
1158 case BR_STATE_DISABLED:
cca8b133 1159 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1160 break;
1161 case BR_STATE_BLOCKING:
1162 case BR_STATE_LISTENING:
cca8b133 1163 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1164 break;
1165 case BR_STATE_LEARNING:
cca8b133 1166 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1167 break;
1168 case BR_STATE_FORWARDING:
1169 default:
cca8b133 1170 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1171 break;
1172 }
1173
fad09c73
VD		 1174 mutex_lock(&chip->reg_lock);
1175 err = _mv88e6xxx_port_state(chip, port, stp_state);
1176 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1177
1178 if (err)
c8b09808
AL		 1179 netdev_err(ds->ports[port].netdev,
1180 "failed to update state to %s\n",
553eb544 1181 mv88e6xxx_port_state_names[stp_state]);
facd95b2
GR		 1182}
1183
fad09c73 1184static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
158bc065 1185 u16 *new, u16 *old)
76e398a6 1186{
fad09c73 1187 struct dsa_switch *ds = chip->ds;
5da96031 1188 u16 pvid;
76e398a6
VD		 1189 int ret;
1190
fad09c73 1191 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
76e398a6
VD		 1192 if (ret < 0)
1193 return ret;
1194
5da96031
VD		 1195 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1196
1197 if (new) {
1198 ret &= ~PORT_DEFAULT_VLAN_MASK;
1199 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1200
fad09c73 1201 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
5da96031
VD		 1202 PORT_DEFAULT_VLAN, ret);
1203 if (ret < 0)
1204 return ret;
1205
c8b09808
AL		 1206 netdev_dbg(ds->ports[port].netdev,
1207 "DefaultVID %d (was %d)\n", *new, pvid);
5da96031
VD		 1208 }
1209
1210 if (old)
1211 *old = pvid;
76e398a6
VD		 1212
1213 return 0;
1214}
1215
fad09c73 1216static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
158bc065 1217 int port, u16 *pvid)
5da96031 1218{
fad09c73 1219 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
5da96031
VD		 1220}
1221
fad09c73 1222static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
158bc065 1223 int port, u16 pvid)
0d3b33e6 1224{
fad09c73 1225 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
0d3b33e6
VD		 1226}
1227
fad09c73 1228static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1229{
fad09c73 1230 return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
6b17e864
VD		 1231 GLOBAL_VTU_OP_BUSY);
1232}
1233
fad09c73 1234static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864
VD		 1235{
1236 int ret;
1237
fad09c73 1238 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
6b17e864
VD		 1239 if (ret < 0)
1240 return ret;
1241
fad09c73 1242 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1243}
1244
fad09c73 1245static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1246{
1247 int ret;
1248
fad09c73 1249 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1250 if (ret < 0)
1251 return ret;
1252
fad09c73 1253 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1254}
1255
fad09c73 1256static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1257 struct mv88e6xxx_vtu_stu_entry *entry,
1258 unsigned int nibble_offset)
1259{
b8fee957
VD		 1260 u16 regs[3];
1261 int i;
1262 int ret;
1263
1264 for (i = 0; i < 3; ++i) {
fad09c73 1265 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1266 GLOBAL_VTU_DATA_0_3 + i);
1267 if (ret < 0)
1268 return ret;
1269
1270 regs[i] = ret;
1271 }
1272
fad09c73 1273 for (i = 0; i < chip->info->num_ports; ++i) {
b8fee957
VD		 1274 unsigned int shift = (i % 4) * 4 + nibble_offset;
1275 u16 reg = regs[i / 4];
1276
1277 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1278 }
1279
1280 return 0;
1281}
1282
fad09c73 1283static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1284 struct mv88e6xxx_vtu_stu_entry *entry)
1285{
fad09c73 1286 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1287}
1288
fad09c73 1289static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1290 struct mv88e6xxx_vtu_stu_entry *entry)
1291{
fad09c73 1292 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1293}
1294
fad09c73 1295static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1296 struct mv88e6xxx_vtu_stu_entry *entry,
1297 unsigned int nibble_offset)
1298{
7dad08d7
VD		 1299 u16 regs[3] = { 0 };
1300 int i;
1301 int ret;
1302
fad09c73 1303 for (i = 0; i < chip->info->num_ports; ++i) {
7dad08d7
VD		 1304 unsigned int shift = (i % 4) * 4 + nibble_offset;
1305 u8 data = entry->data[i];
1306
1307 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1308 }
1309
1310 for (i = 0; i < 3; ++i) {
fad09c73 1311 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
7dad08d7
VD		 1312 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1313 if (ret < 0)
1314 return ret;
1315 }
1316
1317 return 0;
1318}
1319
fad09c73 1320static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1321 struct mv88e6xxx_vtu_stu_entry *entry)
1322{
fad09c73 1323 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1324}
1325
fad09c73 1326static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1327 struct mv88e6xxx_vtu_stu_entry *entry)
1328{
fad09c73 1329 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1330}
1331
fad09c73 1332static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1333{
fad09c73 1334 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
36d04ba1
VD		 1335 vid & GLOBAL_VTU_VID_MASK);
1336}
1337
fad09c73 1338static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1339 struct mv88e6xxx_vtu_stu_entry *entry)
1340{
1341 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1342 int ret;
1343
fad09c73 1344 ret = _mv88e6xxx_vtu_wait(chip);
b8fee957
VD		 1345 if (ret < 0)
1346 return ret;
1347
fad09c73 1348 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
b8fee957
VD		 1349 if (ret < 0)
1350 return ret;
1351
fad09c73 1352 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
b8fee957
VD		 1353 if (ret < 0)
1354 return ret;
1355
1356 next.vid = ret & GLOBAL_VTU_VID_MASK;
1357 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1358
1359 if (next.valid) {
fad09c73 1360 ret = mv88e6xxx_vtu_data_read(chip, &next);
b8fee957
VD		 1361 if (ret < 0)
1362 return ret;
1363
fad09c73
VD		 1364 if (mv88e6xxx_has_fid_reg(chip)) {
1365 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1366 GLOBAL_VTU_FID);
1367 if (ret < 0)
1368 return ret;
1369
1370 next.fid = ret & GLOBAL_VTU_FID_MASK;
fad09c73 1371 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1372 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1373 * VTU DBNum[3:0] are located in VTU Operation 3:0
1374 */
fad09c73 1375 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
11ea809f
VD		 1376 GLOBAL_VTU_OP);
1377 if (ret < 0)
1378 return ret;
1379
1380 next.fid = (ret & 0xf00) >> 4;
1381 next.fid |= ret & 0xf;
2e7bd5ef 1382 }
b8fee957 1383
fad09c73
VD		 1384 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1385 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1386 GLOBAL_VTU_SID);
1387 if (ret < 0)
1388 return ret;
1389
1390 next.sid = ret & GLOBAL_VTU_SID_MASK;
1391 }
1392 }
1393
1394 *entry = next;
1395 return 0;
1396}
1397
f81ec90f
VD		 1398static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1399 struct switchdev_obj_port_vlan *vlan,
1400 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1401{
fad09c73 1402 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
ceff5eff
VD		 1403 struct mv88e6xxx_vtu_stu_entry next;
1404 u16 pvid;
1405 int err;
1406
fad09c73 1407 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1408 return -EOPNOTSUPP;
1409
fad09c73 1410 mutex_lock(&chip->reg_lock);
ceff5eff 1411
fad09c73 1412 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
ceff5eff
VD		 1413 if (err)
1414 goto unlock;
1415
fad09c73 1416 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1417 if (err)
1418 goto unlock;
1419
1420 do {
fad09c73 1421 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1422 if (err)
1423 break;
1424
1425 if (!next.valid)
1426 break;
1427
1428 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1429 continue;
1430
1431 /* reinit and dump this VLAN obj */
57d32310
VD		 1432 vlan->vid_begin = next.vid;
1433 vlan->vid_end = next.vid;
ceff5eff
VD		 1434 vlan->flags = 0;
1435
1436 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1437 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1438
1439 if (next.vid == pvid)
1440 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1441
1442 err = cb(&vlan->obj);
1443 if (err)
1444 break;
1445 } while (next.vid < GLOBAL_VTU_VID_MASK);
1446
1447unlock:
fad09c73 1448 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1449
1450 return err;
1451}
1452
fad09c73 1453static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1454 struct mv88e6xxx_vtu_stu_entry *entry)
1455{
11ea809f 1456 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1457 u16 reg = 0;
1458 int ret;
1459
fad09c73 1460 ret = _mv88e6xxx_vtu_wait(chip);
7dad08d7
VD		 1461 if (ret < 0)
1462 return ret;
1463
1464 if (!entry->valid)
1465 goto loadpurge;
1466
1467 /* Write port member tags */
fad09c73 1468 ret = mv88e6xxx_vtu_data_write(chip, entry);
7dad08d7
VD		 1469 if (ret < 0)
1470 return ret;
1471
fad09c73 1472 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1473 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73
VD		 1474 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1475 reg);
7dad08d7
VD		 1476 if (ret < 0)
1477 return ret;
b426e5f7 1478 }
7dad08d7 1479
fad09c73 1480 if (mv88e6xxx_has_fid_reg(chip)) {
7dad08d7 1481 reg = entry->fid & GLOBAL_VTU_FID_MASK;
fad09c73
VD		 1482 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1483 reg);
7dad08d7
VD		 1484 if (ret < 0)
1485 return ret;
fad09c73 1486 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1487 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1488 * VTU DBNum[3:0] are located in VTU Operation 3:0
1489 */
1490 op |= (entry->fid & 0xf0) << 8;
1491 op |= entry->fid & 0xf;
7dad08d7
VD		 1492 }
1493
1494 reg = GLOBAL_VTU_VID_VALID;
1495loadpurge:
1496 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
fad09c73 1497 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
7dad08d7
VD		 1498 if (ret < 0)
1499 return ret;
1500
fad09c73 1501 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1502}
1503
fad09c73 1504static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
0d3b33e6
VD		 1505 struct mv88e6xxx_vtu_stu_entry *entry)
1506{
1507 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1508 int ret;
1509
fad09c73 1510 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1511 if (ret < 0)
1512 return ret;
1513
fad09c73 1514 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
0d3b33e6
VD		 1515 sid & GLOBAL_VTU_SID_MASK);
1516 if (ret < 0)
1517 return ret;
1518
fad09c73 1519 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
0d3b33e6
VD		 1520 if (ret < 0)
1521 return ret;
1522
fad09c73 1523 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
0d3b33e6
VD		 1524 if (ret < 0)
1525 return ret;
1526
1527 next.sid = ret & GLOBAL_VTU_SID_MASK;
1528
fad09c73 1529 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
0d3b33e6
VD		 1530 if (ret < 0)
1531 return ret;
1532
1533 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1534
1535 if (next.valid) {
fad09c73 1536 ret = mv88e6xxx_stu_data_read(chip, &next);
0d3b33e6
VD		 1537 if (ret < 0)
1538 return ret;
1539 }
1540
1541 *entry = next;
1542 return 0;
1543}
1544
fad09c73 1545static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
0d3b33e6
VD		 1546 struct mv88e6xxx_vtu_stu_entry *entry)
1547{
1548 u16 reg = 0;
1549 int ret;
1550
fad09c73 1551 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1552 if (ret < 0)
1553 return ret;
1554
1555 if (!entry->valid)
1556 goto loadpurge;
1557
1558 /* Write port states */
fad09c73 1559 ret = mv88e6xxx_stu_data_write(chip, entry);
0d3b33e6
VD		 1560 if (ret < 0)
1561 return ret;
1562
1563 reg = GLOBAL_VTU_VID_VALID;
1564loadpurge:
fad09c73 1565 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
0d3b33e6
VD		 1566 if (ret < 0)
1567 return ret;
1568
1569 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73 1570 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
0d3b33e6
VD		 1571 if (ret < 0)
1572 return ret;
1573
fad09c73 1574 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1575}
1576
fad09c73 1577static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
158bc065 1578 u16 *new, u16 *old)
2db9ce1f 1579{
fad09c73 1580 struct dsa_switch *ds = chip->ds;
f74df0be 1581 u16 upper_mask;
2db9ce1f
VD		 1582 u16 fid;
1583 int ret;
1584
fad09c73 1585 if (mv88e6xxx_num_databases(chip) == 4096)
f74df0be 1586 upper_mask = 0xff;
fad09c73 1587 else if (mv88e6xxx_num_databases(chip) == 256)
11ea809f 1588 upper_mask = 0xf;
f74df0be
VD		 1589 else
1590 return -EOPNOTSUPP;
1591
2db9ce1f 1592 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
fad09c73 1593 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
2db9ce1f
VD		 1594 if (ret < 0)
1595 return ret;
1596
1597 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1598
1599 if (new) {
1600 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1601 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1602
fad09c73 1603 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
2db9ce1f
VD		 1604 ret);
1605 if (ret < 0)
1606 return ret;
1607 }
1608
1609 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
fad09c73 1610 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
2db9ce1f
VD		 1611 if (ret < 0)
1612 return ret;
1613
f74df0be 1614 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1615
1616 if (new) {
f74df0be
VD		 1617 ret &= ~upper_mask;
1618 ret |= (*new >> 4) & upper_mask;
2db9ce1f 1619
fad09c73 1620 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2db9ce1f
VD		 1621 ret);
1622 if (ret < 0)
1623 return ret;
1624
c8b09808
AL		 1625 netdev_dbg(ds->ports[port].netdev,
1626 "FID %d (was %d)\n", *new, fid);
2db9ce1f
VD		 1627 }
1628
1629 if (old)
1630 *old = fid;
1631
1632 return 0;
1633}
1634
fad09c73 1635static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
158bc065 1636 int port, u16 *fid)
2db9ce1f 1637{
fad09c73 1638 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
2db9ce1f
VD		 1639}
1640
fad09c73 1641static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
158bc065 1642 int port, u16 fid)
2db9ce1f 1643{
fad09c73 1644 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
2db9ce1f
VD		 1645}
1646
fad09c73 1647static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1648{
1649 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1650 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1651 int i, err;
3285f9e8
VD		 1652
1653 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1654
2db9ce1f 1655 /* Set every FID bit used by the (un)bridged ports */
fad09c73
VD		 1656 for (i = 0; i < chip->info->num_ports; ++i) {
1657 err = _mv88e6xxx_port_fid_get(chip, i, fid);
2db9ce1f
VD		 1658 if (err)
1659 return err;
1660
1661 set_bit(*fid, fid_bitmap);
1662 }
1663
3285f9e8 1664 /* Set every FID bit used by the VLAN entries */
fad09c73 1665 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1666 if (err)
1667 return err;
1668
1669 do {
fad09c73 1670 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1671 if (err)
1672 return err;
1673
1674 if (!vlan.valid)
1675 break;
1676
1677 set_bit(vlan.fid, fid_bitmap);
1678 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1679
1680 /* The reset value 0x000 is used to indicate that multiple address
1681 * databases are not needed. Return the next positive available.
1682 */
1683 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1684 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1685 return -ENOSPC;
1686
1687 /* Clear the database */
fad09c73 1688 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1689}
1690
fad09c73 1691static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09 1692 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1693{
fad09c73 1694 struct dsa_switch *ds = chip->ds;
0d3b33e6
VD		 1695 struct mv88e6xxx_vtu_stu_entry vlan = {
1696 .valid = true,
1697 .vid = vid,
1698 };
3285f9e8
VD		 1699 int i, err;
1700
fad09c73 1701 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1702 if (err)
1703 return err;
0d3b33e6 1704
3d131f07 1705 /* exclude all ports except the CPU and DSA ports */
fad09c73 1706 for (i = 0; i < chip->info->num_ports; ++i)
3d131f07
VD		 1707 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1708 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1709 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1710
fad09c73
VD		 1711 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1712 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
0d3b33e6 1713 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1714
1715 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1716 * implemented, only one STU entry is needed to cover all VTU
1717 * entries. Thus, validate the SID 0.
1718 */
1719 vlan.sid = 0;
fad09c73 1720 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1721 if (err)
1722 return err;
1723
1724 if (vstp.sid != vlan.sid || !vstp.valid) {
1725 memset(&vstp, 0, sizeof(vstp));
1726 vstp.valid = true;
1727 vstp.sid = vlan.sid;
1728
fad09c73 1729 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1730 if (err)
1731 return err;
1732 }
0d3b33e6
VD		 1733 }
1734
1735 *entry = vlan;
1736 return 0;
1737}
1738
fad09c73 1739static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09
VD		 1740 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1741{
1742 int err;
1743
1744 if (!vid)
1745 return -EINVAL;
1746
fad09c73 1747 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1748 if (err)
1749 return err;
1750
fad09c73 1751 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1752 if (err)
1753 return err;
1754
1755 if (entry->vid != vid || !entry->valid) {
1756 if (!creat)
1757 return -EOPNOTSUPP;
1758 /* -ENOENT would've been more appropriate, but switchdev expects
1759 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1760 */
1761
fad09c73 1762 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1763 }
1764
1765 return err;
1766}
1767
da9c359e
VD		 1768static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1769 u16 vid_begin, u16 vid_end)
1770{
fad09c73 1771 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
da9c359e
VD		 1772 struct mv88e6xxx_vtu_stu_entry vlan;
1773 int i, err;
1774
1775 if (!vid_begin)
1776 return -EOPNOTSUPP;
1777
fad09c73 1778 mutex_lock(&chip->reg_lock);
da9c359e 1779
fad09c73 1780 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1781 if (err)
1782 goto unlock;
1783
1784 do {
fad09c73 1785 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1786 if (err)
1787 goto unlock;
1788
1789 if (!vlan.valid)
1790 break;
1791
1792 if (vlan.vid > vid_end)
1793 break;
1794
fad09c73 1795 for (i = 0; i < chip->info->num_ports; ++i) {
da9c359e
VD		 1796 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1797 continue;
1798
1799 if (vlan.data[i] ==
1800 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1801 continue;
1802
fad09c73
VD		 1803 if (chip->ports[i].bridge_dev ==
1804 chip->ports[port].bridge_dev)
da9c359e
VD		 1805 break; /* same bridge, check next VLAN */
1806
c8b09808 1807 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1808 "hardware VLAN %d already used by %s\n",
1809 vlan.vid,
fad09c73 1810 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1811 err = -EOPNOTSUPP;
1812 goto unlock;
1813 }
1814 } while (vlan.vid < vid_end);
1815
1816unlock:
fad09c73 1817 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1818
1819 return err;
1820}
1821
214cdb99
VD		 1822static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1823 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1824 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1825 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1826 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1827};
1828
f81ec90f
VD		 1829static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1830 bool vlan_filtering)
214cdb99 1831{
fad09c73 1832 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
214cdb99
VD		 1833 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1834 PORT_CONTROL_2_8021Q_DISABLED;
1835 int ret;
1836
fad09c73 1837 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1838 return -EOPNOTSUPP;
1839
fad09c73 1840 mutex_lock(&chip->reg_lock);
214cdb99 1841
fad09c73 1842 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
214cdb99
VD		 1843 if (ret < 0)
1844 goto unlock;
1845
1846 old = ret & PORT_CONTROL_2_8021Q_MASK;
1847
5220ef1e
VD		 1848 if (new != old) {
1849 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1850 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1851
fad09c73 1852 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
5220ef1e
VD		 1853 ret);
1854 if (ret < 0)
1855 goto unlock;
1856
c8b09808 1857 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
5220ef1e
VD		 1858 mv88e6xxx_port_8021q_mode_names[new],
1859 mv88e6xxx_port_8021q_mode_names[old]);
1860 }
214cdb99 1861
5220ef1e 1862 ret = 0;
214cdb99 1863unlock:
fad09c73 1864 mutex_unlock(&chip->reg_lock);
214cdb99
VD		 1865
1866 return ret;
1867}
1868
57d32310
VD		 1869static int
1870mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1871 const struct switchdev_obj_port_vlan *vlan,
1872 struct switchdev_trans *trans)
76e398a6 1873{
fad09c73 1874 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
da9c359e
VD		 1875 int err;
1876
fad09c73 1877 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1878 return -EOPNOTSUPP;
1879
da9c359e
VD		 1880 /* If the requested port doesn't belong to the same bridge as the VLAN
1881 * members, do not support it (yet) and fallback to software VLAN.
1882 */
1883 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1884 vlan->vid_end);
1885 if (err)
1886 return err;
1887
76e398a6
VD		 1888 /* We don't need any dynamic resource from the kernel (yet),
1889 * so skip the prepare phase.
1890 */
1891 return 0;
1892}
1893
fad09c73 1894static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1895 u16 vid, bool untagged)
0d3b33e6 1896{
0d3b33e6
VD		 1897 struct mv88e6xxx_vtu_stu_entry vlan;
1898 int err;
1899
fad09c73 1900 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1901 if (err)
76e398a6 1902 return err;
0d3b33e6 1903
0d3b33e6
VD		 1904 vlan.data[port] = untagged ?
1905 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1906 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1907
fad09c73 1908 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1909}
1910
f81ec90f
VD		 1911static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1912 const struct switchdev_obj_port_vlan *vlan,
1913 struct switchdev_trans *trans)
76e398a6 1914{
fad09c73 1915 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
76e398a6
VD		 1916 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1917 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1918 u16 vid;
76e398a6 1919
fad09c73 1920 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1921 return;
1922
fad09c73 1923 mutex_lock(&chip->reg_lock);
76e398a6 1924
4d5770b3 1925 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1926 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1927 netdev_err(ds->ports[port].netdev,
1928 "failed to add VLAN %d%c\n",
4d5770b3 1929 vid, untagged ? 'u' : 't');
76e398a6 1930
fad09c73 1931 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
c8b09808 1932 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1933 vlan->vid_end);
0d3b33e6 1934
fad09c73 1935 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1936}
1937
fad09c73 1938static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1939 int port, u16 vid)
7dad08d7 1940{
fad09c73 1941 struct dsa_switch *ds = chip->ds;
7dad08d7 1942 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1943 int i, err;
1944
fad09c73 1945 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1946 if (err)
76e398a6 1947 return err;
7dad08d7 1948
2fb5ef09
VD		 1949 /* Tell switchdev if this VLAN is handled in software */
1950 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1951 return -EOPNOTSUPP;
7dad08d7
VD		 1952
1953 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1954
1955 /* keep the VLAN unless all ports are excluded */
f02bdffc 1956 vlan.valid = false;
fad09c73 1957 for (i = 0; i < chip->info->num_ports; ++i) {
3d131f07 1958 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1959 continue;
1960
1961 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1962 vlan.valid = true;
7dad08d7
VD		 1963 break;
1964 }
1965 }
1966
fad09c73 1967 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1968 if (err)
1969 return err;
1970
fad09c73 1971 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 1972}
1973
f81ec90f
VD		 1974static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1975 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1976{
fad09c73 1977 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
76e398a6
VD		 1978 u16 pvid, vid;
1979 int err = 0;
1980
fad09c73 1981 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1982 return -EOPNOTSUPP;
1983
fad09c73 1984 mutex_lock(&chip->reg_lock);
76e398a6 1985
fad09c73 1986 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
7dad08d7
VD		 1987 if (err)
1988 goto unlock;
1989
76e398a6 1990 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 1991 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 1992 if (err)
1993 goto unlock;
1994
1995 if (vid == pvid) {
fad09c73 1996 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
76e398a6
VD		 1997 if (err)
1998 goto unlock;
1999 }
2000 }
2001
7dad08d7 2002unlock:
fad09c73 2003 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2004
2005 return err;
2006}
2007
fad09c73 2008static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2009 const unsigned char *addr)
defb05b9
GR		 2010{
2011 int i, ret;
2012
2013 for (i = 0; i < 3; i++) {
cca8b133 2014 ret = _mv88e6xxx_reg_write(
fad09c73 2015 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
cca8b133 2016 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2017 if (ret < 0)
2018 return ret;
2019 }
2020
2021 return 0;
2022}
2023
fad09c73 2024static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2025 unsigned char *addr)
defb05b9
GR		 2026{
2027 int i, ret;
2028
2029 for (i = 0; i < 3; i++) {
fad09c73 2030 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
cca8b133 2031 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2032 if (ret < 0)
2033 return ret;
2034 addr[i * 2] = ret >> 8;
2035 addr[i * 2 + 1] = ret & 0xff;
2036 }
2037
2038 return 0;
2039}
2040
fad09c73 2041static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2042 struct mv88e6xxx_atu_entry *entry)
defb05b9 2043{
6630e236
VD		 2044 int ret;
2045
fad09c73 2046 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2047 if (ret < 0)
2048 return ret;
2049
fad09c73 2050 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2051 if (ret < 0)
2052 return ret;
2053
fad09c73 2054 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2055 if (ret < 0)
87820510
VD		 2056 return ret;
2057
fad09c73 2058 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2059}
87820510 2060
fad09c73 2061static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
fd231c82
VD		 2062 const unsigned char *addr, u16 vid,
2063 u8 state)
2064{
2065 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2066 struct mv88e6xxx_vtu_stu_entry vlan;
2067 int err;
2068
2db9ce1f
VD		 2069 /* Null VLAN ID corresponds to the port private database */
2070 if (vid == 0)
fad09c73 2071 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2db9ce1f 2072 else
fad09c73 2073 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2074 if (err)
2075 return err;
fd231c82 2076
3285f9e8 2077 entry.fid = vlan.fid;
fd231c82
VD		 2078 entry.state = state;
2079 ether_addr_copy(entry.mac, addr);
2080 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2081 entry.trunk = false;
2082 entry.portv_trunkid = BIT(port);
2083 }
2084
fad09c73 2085 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2086}
2087
f81ec90f
VD		 2088static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2089 const struct switchdev_obj_port_fdb *fdb,
2090 struct switchdev_trans *trans)
146a3206
VD		 2091{
2092 /* We don't need any dynamic resource from the kernel (yet),
2093 * so skip the prepare phase.
2094 */
2095 return 0;
2096}
2097
f81ec90f
VD		 2098static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2099 const struct switchdev_obj_port_fdb *fdb,
2100 struct switchdev_trans *trans)
87820510 2101{
1f36faf2 2102 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 2103 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2104 GLOBAL_ATU_DATA_STATE_UC_STATIC;
fad09c73 2105 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
87820510 2106
fad09c73
VD		 2107 mutex_lock(&chip->reg_lock);
2108 if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
c8b09808
AL		 2109 netdev_err(ds->ports[port].netdev,
2110 "failed to load MAC address\n");
fad09c73 2111 mutex_unlock(&chip->reg_lock);
87820510
VD		 2112}
2113
f81ec90f
VD		 2114static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2115 const struct switchdev_obj_port_fdb *fdb)
87820510 2116{
fad09c73 2117 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
87820510
VD		 2118 int ret;
2119
fad09c73
VD		 2120 mutex_lock(&chip->reg_lock);
2121 ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
cdf09697 2122 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2123 mutex_unlock(&chip->reg_lock);
87820510
VD		 2124
2125 return ret;
2126}
2127
fad09c73 2128static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2129 struct mv88e6xxx_atu_entry *entry)
6630e236 2130{
1d194046
VD		 2131 struct mv88e6xxx_atu_entry next = { 0 };
2132 int ret;
2133
2134 next.fid = fid;
defb05b9 2135
fad09c73 2136 ret = _mv88e6xxx_atu_wait(chip);
cdf09697
DM		 2137 if (ret < 0)
2138 return ret;
6630e236 2139
fad09c73 2140 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2141 if (ret < 0)
2142 return ret;
6630e236 2143
fad09c73 2144 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
1d194046
VD		 2145 if (ret < 0)
2146 return ret;
6630e236 2147
fad09c73 2148 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2149 if (ret < 0)
2150 return ret;
6630e236 2151
1d194046
VD		 2152 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2153 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2154 unsigned int mask, shift;
2155
2156 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2157 next.trunk = true;
2158 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2159 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2160 } else {
2161 next.trunk = false;
2162 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2163 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2164 }
2165
2166 next.portv_trunkid = (ret & mask) >> shift;
2167 }
cdf09697 2168
1d194046 2169 *entry = next;
cdf09697
DM		 2170 return 0;
2171}
2172
fad09c73 2173static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
158bc065 2174 u16 fid, u16 vid, int port,
74b6ba0d
VD		 2175 struct switchdev_obj_port_fdb *fdb,
2176 int (*cb)(struct switchdev_obj *obj))
2177{
2178 struct mv88e6xxx_atu_entry addr = {
2179 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2180 };
2181 int err;
2182
fad09c73 2183 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2184 if (err)
2185 return err;
2186
2187 do {
fad09c73 2188 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d
VD		 2189 if (err)
2190 break;
2191
2192 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2193 break;
2194
2195 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2196 bool is_static = addr.state ==
2197 (is_multicast_ether_addr(addr.mac) ?
2198 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2199 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2200
2201 fdb->vid = vid;
2202 ether_addr_copy(fdb->addr, addr.mac);
2203 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2204
2205 err = cb(&fdb->obj);
2206 if (err)
2207 break;
2208 }
2209 } while (!is_broadcast_ether_addr(addr.mac));
2210
2211 return err;
2212}
2213
f81ec90f
VD		 2214static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2215 struct switchdev_obj_port_fdb *fdb,
2216 int (*cb)(struct switchdev_obj *obj))
f33475bd 2217{
fad09c73 2218 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
f33475bd
VD		 2219 struct mv88e6xxx_vtu_stu_entry vlan = {
2220 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2221 };
2db9ce1f 2222 u16 fid;
f33475bd
VD		 2223 int err;
2224
fad09c73 2225 mutex_lock(&chip->reg_lock);
f33475bd 2226
2db9ce1f 2227 /* Dump port's default Filtering Information Database (VLAN ID 0) */
fad09c73 2228 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2db9ce1f
VD		 2229 if (err)
2230 goto unlock;
2231
fad09c73 2232 err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2db9ce1f
VD		 2233 if (err)
2234 goto unlock;
2235
74b6ba0d 2236 /* Dump VLANs' Filtering Information Databases */
fad09c73 2237 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd
VD		 2238 if (err)
2239 goto unlock;
2240
2241 do {
fad09c73 2242 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2243 if (err)
74b6ba0d 2244 break;
f33475bd
VD		 2245
2246 if (!vlan.valid)
2247 break;
2248
fad09c73
VD		 2249 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2250 port, fdb, cb);
f33475bd 2251 if (err)
74b6ba0d 2252 break;
f33475bd
VD		 2253 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2254
2255unlock:
fad09c73 2256 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2257
2258 return err;
2259}
2260
f81ec90f
VD		 2261static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2262 struct net_device *bridge)
e79a8bcb 2263{
fad09c73 2264 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1d9619d5 2265 int i, err = 0;
466dfa07 2266
fad09c73 2267 mutex_lock(&chip->reg_lock);
466dfa07 2268
b7666efe 2269 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2270 chip->ports[port].bridge_dev = bridge;
b7666efe 2271
fad09c73
VD		 2272 for (i = 0; i < chip->info->num_ports; ++i) {
2273 if (chip->ports[i].bridge_dev == bridge) {
2274 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2275 if (err)
2276 break;
2277 }
2278 }
2279
fad09c73 2280 mutex_unlock(&chip->reg_lock);
a6692754 2281
466dfa07 2282 return err;
e79a8bcb
VD		 2283}
2284
f81ec90f 2285static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2286{
fad09c73
VD		 2287 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2288 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2289 int i;
466dfa07 2290
fad09c73 2291 mutex_lock(&chip->reg_lock);
466dfa07 2292
b7666efe 2293 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2294 chip->ports[port].bridge_dev = NULL;
b7666efe 2295
fad09c73
VD		 2296 for (i = 0; i < chip->info->num_ports; ++i)
2297 if (i == port || chip->ports[i].bridge_dev == bridge)
2298 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2299 netdev_warn(ds->ports[i].netdev,
2300 "failed to remap\n");
b7666efe 2301
fad09c73 2302 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2303}
2304
fad09c73 2305static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
03a4a540 2306 int port, int page, int reg, int val)
75baacf0
PU		 2307{
2308 int ret;
2309
fad09c73 2310 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
75baacf0
PU		 2311 if (ret < 0)
2312 goto restore_page_0;
2313
fad09c73 2314 ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
75baacf0 2315restore_page_0:
fad09c73 2316 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
75baacf0
PU		 2317
2318 return ret;
2319}
2320
fad09c73 2321static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
03a4a540 2322 int port, int page, int reg)
75baacf0
PU		 2323{
2324 int ret;
2325
fad09c73 2326 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
75baacf0
PU		 2327 if (ret < 0)
2328 goto restore_page_0;
2329
fad09c73 2330 ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
75baacf0 2331restore_page_0:
fad09c73 2332 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
75baacf0
PU		 2333
2334 return ret;
2335}
2336
fad09c73 2337static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2338{
fad09c73 2339 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2340 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2341 struct gpio_desc *gpiod = chip->reset;
552238b5
VD		 2342 unsigned long timeout;
2343 int ret;
2344 int i;
2345
2346 /* Set all ports to the disabled state. */
fad09c73
VD		 2347 for (i = 0; i < chip->info->num_ports; i++) {
2348 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
552238b5
VD		 2349 if (ret < 0)
2350 return ret;
2351
fad09c73 2352 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
552238b5
VD		 2353 ret & 0xfffc);
2354 if (ret)
2355 return ret;
2356 }
2357
2358 /* Wait for transmit queues to drain. */
2359 usleep_range(2000, 4000);
2360
2361 /* If there is a gpio connected to the reset pin, toggle it */
2362 if (gpiod) {
2363 gpiod_set_value_cansleep(gpiod, 1);
2364 usleep_range(10000, 20000);
2365 gpiod_set_value_cansleep(gpiod, 0);
2366 usleep_range(10000, 20000);
2367 }
2368
2369 /* Reset the switch. Keep the PPU active if requested. The PPU
2370 * needs to be active to support indirect phy register access
2371 * through global registers 0x18 and 0x19.
2372 */
2373 if (ppu_active)
fad09c73 2374 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
552238b5 2375 else
fad09c73 2376 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
552238b5
VD		 2377 if (ret)
2378 return ret;
2379
2380 /* Wait up to one second for reset to complete. */
2381 timeout = jiffies + 1 * HZ;
2382 while (time_before(jiffies, timeout)) {
fad09c73 2383 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
552238b5
VD		 2384 if (ret < 0)
2385 return ret;
2386
2387 if ((ret & is_reset) == is_reset)
2388 break;
2389 usleep_range(1000, 2000);
2390 }
2391 if (time_after(jiffies, timeout))
2392 ret = -ETIMEDOUT;
2393 else
2394 ret = 0;
2395
2396 return ret;
2397}
2398
fad09c73 2399static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
13a7ebb3
PU		 2400{
2401 int ret;
2402
fad09c73 2403 ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
03a4a540 2404 PAGE_FIBER_SERDES, MII_BMCR);
13a7ebb3
PU		 2405 if (ret < 0)
2406 return ret;
2407
2408 if (ret & BMCR_PDOWN) {
2409 ret &= ~BMCR_PDOWN;
fad09c73 2410 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
03a4a540
AL		 2411 PAGE_FIBER_SERDES, MII_BMCR,
2412 ret);
13a7ebb3
PU		 2413 }
2414
2415 return ret;
2416}
2417
8f6345b2
VD		 2418static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2419 int reg, u16 *val)
2420{
2421 int addr = chip->info->port_base_addr + port;
2422
2423 if (port >= chip->info->num_ports)
2424 return -EINVAL;
2425
2426 return mv88e6xxx_read(chip, addr, reg, val);
2427}
2428
fad09c73 2429static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2430{
fad09c73 2431 struct dsa_switch *ds = chip->ds;
f02bdffc 2432 int ret;
54d792f2 2433 u16 reg;
d827e88a 2434
fad09c73
VD		 2435 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2436 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2437 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2438 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2439 /* MAC Forcing register: don't force link, speed,
2440 * duplex or flow control state to any particular
2441 * values on physical ports, but force the CPU port
2442 * and all DSA ports to their maximum bandwidth and
2443 * full duplex.
2444 */
fad09c73 2445 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2446 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2447 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2448 reg |= PORT_PCS_CTRL_FORCE_LINK |
2449 PORT_PCS_CTRL_LINK_UP |
2450 PORT_PCS_CTRL_DUPLEX_FULL |
2451 PORT_PCS_CTRL_FORCE_DUPLEX;
fad09c73 2452 if (mv88e6xxx_6065_family(chip))
54d792f2
AL		 2453 reg |= PORT_PCS_CTRL_100;
2454 else
2455 reg |= PORT_PCS_CTRL_1000;
2456 } else {
2457 reg |= PORT_PCS_CTRL_UNFORCED;
2458 }
2459
fad09c73 2460 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2461 PORT_PCS_CTRL, reg);
2462 if (ret)
a1a6a4d1 2463 return ret;
54d792f2
AL		 2464 }
2465
2466 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2467 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2468 * tunneling, determine priority by looking at 802.1p and IP
2469 * priority fields (IP prio has precedence), and set STP state
2470 * to Forwarding.
2471 *
2472 * If this is the CPU link, use DSA or EDSA tagging depending
2473 * on which tagging mode was configured.
2474 *
2475 * If this is a link to another switch, use DSA tagging mode.
2476 *
2477 * If this is the upstream port for this switch, enable
2478 * forwarding of unknown unicasts and multicasts.
2479 */
2480 reg = 0;
fad09c73
VD		 2481 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2482 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2483 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2484 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2485 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2486 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2487 PORT_CONTROL_STATE_FORWARDING;
2488 if (dsa_is_cpu_port(ds, port)) {
fad09c73 2489 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
54d792f2 2490 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2491 if (mv88e6xxx_6352_family(chip) ||
2492 mv88e6xxx_6351_family(chip) ||
2493 mv88e6xxx_6165_family(chip) ||
2494 mv88e6xxx_6097_family(chip) ||
2495 mv88e6xxx_6320_family(chip)) {
5377b802
AL		 2496 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2497 PORT_CONTROL_FORWARD_UNKNOWN |
c047a1f9 2498 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2499 }
2500
fad09c73
VD		 2501 if (mv88e6xxx_6352_family(chip) ||
2502 mv88e6xxx_6351_family(chip) ||
2503 mv88e6xxx_6165_family(chip) ||
2504 mv88e6xxx_6097_family(chip) ||
2505 mv88e6xxx_6095_family(chip) ||
2506 mv88e6xxx_6065_family(chip) ||
2507 mv88e6xxx_6185_family(chip) ||
2508 mv88e6xxx_6320_family(chip)) {
57d32310 2509 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
54d792f2
AL		 2510 }
2511 }
6083ce71 2512 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2513 if (mv88e6xxx_6095_family(chip) ||
2514 mv88e6xxx_6185_family(chip))
6083ce71 2515 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2516 if (mv88e6xxx_6352_family(chip) ||
2517 mv88e6xxx_6351_family(chip) ||
2518 mv88e6xxx_6165_family(chip) ||
2519 mv88e6xxx_6097_family(chip) ||
2520 mv88e6xxx_6320_family(chip)) {
54d792f2 2521 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2522 }
2523
54d792f2
AL		 2524 if (port == dsa_upstream_port(ds))
2525 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2526 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2527 }
2528 if (reg) {
fad09c73 2529 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2530 PORT_CONTROL, reg);
2531 if (ret)
a1a6a4d1 2532 return ret;
54d792f2
AL		 2533 }
2534
13a7ebb3
PU		 2535 /* If this port is connected to a SerDes, make sure the SerDes is not
2536 * powered down.
2537 */
fad09c73
VD		 2538 if (mv88e6xxx_6352_family(chip)) {
2539 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
13a7ebb3 2540 if (ret < 0)
a1a6a4d1 2541 return ret;
13a7ebb3
PU		 2542 ret &= PORT_STATUS_CMODE_MASK;
2543 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2544 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2545 (ret == PORT_STATUS_CMODE_SGMII)) {
fad09c73 2546 ret = mv88e6xxx_power_on_serdes(chip);
13a7ebb3 2547 if (ret < 0)
a1a6a4d1 2548 return ret;
13a7ebb3
PU		 2549 }
2550 }
2551
8efdda4a 2552 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2553 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2554 * untagged frames on this port, do a destination address lookup on all
2555 * received packets as usual, disable ARP mirroring and don't send a
2556 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2557 */
2558 reg = 0;
fad09c73
VD		 2559 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2560 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2561 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2562 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2563 reg = PORT_CONTROL_2_MAP_DA;
2564
fad09c73
VD		 2565 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2566 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2567 reg |= PORT_CONTROL_2_JUMBO_10240;
2568
fad09c73 2569 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2570 /* Set the upstream port this port should use */
2571 reg |= dsa_upstream_port(ds);
2572 /* enable forwarding of unknown multicast addresses to
2573 * the upstream port
2574 */
2575 if (port == dsa_upstream_port(ds))
2576 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2577 }
2578
46fbe5e5 2579 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2580
54d792f2 2581 if (reg) {
fad09c73 2582 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2583 PORT_CONTROL_2, reg);
2584 if (ret)
a1a6a4d1 2585 return ret;
54d792f2
AL		 2586 }
2587
2588 /* Port Association Vector: when learning source addresses
2589 * of packets, add the address to the address database using
2590 * a port bitmap that has only the bit for this port set and
2591 * the other bits clear.
2592 */
4c7ea3c0 2593 reg = 1 << port;
996ecb82
VD		 2594 /* Disable learning for CPU port */
2595 if (dsa_is_cpu_port(ds, port))
65fa4027 2596 reg = 0;
4c7ea3c0 2597
fad09c73
VD		 2598 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2599 reg);
54d792f2 2600 if (ret)
a1a6a4d1 2601 return ret;
54d792f2
AL		 2602
2603 /* Egress rate control 2: disable egress rate control. */
fad09c73 2604 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
54d792f2
AL		 2605 0x0000);
2606 if (ret)
a1a6a4d1 2607 return ret;
54d792f2 2608
fad09c73
VD		 2609 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2610 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2611 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2612 /* Do not limit the period of time that this port can
2613 * be paused for by the remote end or the period of
2614 * time that this port can pause the remote end.
2615 */
fad09c73 2616 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2617 PORT_PAUSE_CTRL, 0x0000);
2618 if (ret)
a1a6a4d1 2619 return ret;
54d792f2
AL		 2620
2621 /* Port ATU control: disable limiting the number of
2622 * address database entries that this port is allowed
2623 * to use.
2624 */
fad09c73 2625 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2626 PORT_ATU_CONTROL, 0x0000);
2627 /* Priority Override: disable DA, SA and VTU priority
2628 * override.
2629 */
fad09c73 2630 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2631 PORT_PRI_OVERRIDE, 0x0000);
2632 if (ret)
a1a6a4d1 2633 return ret;
54d792f2
AL		 2634
2635 /* Port Ethertype: use the Ethertype DSA Ethertype
2636 * value.
2637 */
fad09c73 2638 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2639 PORT_ETH_TYPE, ETH_P_EDSA);
2640 if (ret)
a1a6a4d1 2641 return ret;
54d792f2
AL		 2642 /* Tag Remap: use an identity 802.1p prio -> switch
2643 * prio mapping.
2644 */
fad09c73 2645 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2646 PORT_TAG_REGMAP_0123, 0x3210);
2647 if (ret)
a1a6a4d1 2648 return ret;
54d792f2
AL		 2649
2650 /* Tag Remap 2: use an identity 802.1p prio -> switch
2651 * prio mapping.
2652 */
fad09c73 2653 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2654 PORT_TAG_REGMAP_4567, 0x7654);
2655 if (ret)
a1a6a4d1 2656 return ret;
54d792f2
AL		 2657 }
2658
fad09c73
VD		 2659 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2660 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2661 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2662 mv88e6xxx_6320_family(chip)) {
54d792f2 2663 /* Rate Control: disable ingress rate limiting. */
fad09c73 2664 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2665 PORT_RATE_CONTROL, 0x0001);
2666 if (ret)
a1a6a4d1 2667 return ret;
54d792f2
AL		 2668 }
2669
366f0a0f
GR		 2670 /* Port Control 1: disable trunking, disable sending
2671 * learning messages to this port.
d827e88a 2672 */
fad09c73
VD		 2673 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2674 0x0000);
d827e88a 2675 if (ret)
a1a6a4d1 2676 return ret;
d827e88a 2677
207afda1 2678 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2679 * database, and allow bidirectional communication between the
2680 * CPU and DSA port(s), and the other ports.
d827e88a 2681 */
fad09c73 2682 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2db9ce1f 2683 if (ret)
a1a6a4d1 2684 return ret;
2db9ce1f 2685
fad09c73 2686 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
d827e88a 2687 if (ret)
a1a6a4d1 2688 return ret;
d827e88a
GR		 2689
2690 /* Default VLAN ID and priority: don't set a default VLAN
2691 * ID, and set the default packet priority to zero.
2692 */
fad09c73 2693 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
47cf1e65 2694 0x0000);
a1a6a4d1
VD		 2695 if (ret)
2696 return ret;
dbde9e66 2697
dbde9e66
AL		 2698 return 0;
2699}
2700
3b4caa1b
VD		 2701static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2702{
2703 int err;
2704
2705 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2706 (addr[0] << 8) | addr[1]);
2707 if (err)
2708 return err;
2709
2710 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2711 (addr[2] << 8) | addr[3]);
2712 if (err)
2713 return err;
2714
2715 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2716 (addr[4] << 8) | addr[5]);
2717}
2718
acddbd21
VD		 2719static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2720 unsigned int msecs)
2721{
2722 const unsigned int coeff = chip->info->age_time_coeff;
2723 const unsigned int min = 0x01 * coeff;
2724 const unsigned int max = 0xff * coeff;
2725 u8 age_time;
2726 u16 val;
2727 int err;
2728
2729 if (msecs < min || msecs > max)
2730 return -ERANGE;
2731
2732 /* Round to nearest multiple of coeff */
2733 age_time = (msecs + coeff / 2) / coeff;
2734
2735 err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2736 if (err)
2737 return err;
2738
2739 /* AgeTime is 11:4 bits */
2740 val &= ~0xff0;
2741 val |= age_time << 4;
2742
2743 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2744}
2745
2cfcd964
VD		 2746static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2747 unsigned int ageing_time)
2748{
2749 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2750 int err;
2751
2752 mutex_lock(&chip->reg_lock);
2753 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2754 mutex_unlock(&chip->reg_lock);
2755
2756 return err;
2757}
2758
9729934c 2759static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2760{
fad09c73 2761 struct dsa_switch *ds = chip->ds;
b0745e87 2762 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2763 u16 reg;
552238b5 2764 int err;
54d792f2 2765
119477bd
VD		 2766 /* Enable the PHY Polling Unit if present, don't discard any packets,
2767 * and mask all interrupt sources.
2768 */
2769 reg = 0;
fad09c73
VD		 2770 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2771 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2772 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2773
fad09c73 2774 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
119477bd
VD		 2775 if (err)
2776 return err;
2777
b0745e87
VD		 2778 /* Configure the upstream port, and configure it as the port to which
2779 * ingress and egress and ARP monitor frames are to be sent.
2780 */
2781 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2782 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2783 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
fad09c73
VD		 2784 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2785 reg);
b0745e87
VD		 2786 if (err)
2787 return err;
2788
50484ff4 2789 /* Disable remote management, and set the switch's DSA device number. */
fad09c73 2790 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
50484ff4
VD		 2791 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2792 (ds->index & 0x1f));
2793 if (err)
2794 return err;
2795
acddbd21
VD		 2796 /* Clear all the VTU and STU entries */
2797 err = _mv88e6xxx_vtu_stu_flush(chip);
2798 if (err < 0)
2799 return err;
2800
54d792f2
AL		 2801 /* Set the default address aging time to 5 minutes, and
2802 * enable address learn messages to be sent to all message
2803 * ports.
2804 */
acddbd21
VD		 2805 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2806 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2807 if (err)
08a01261 2808 return err;
54d792f2 2809
acddbd21
VD		 2810 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2811 if (err)
9729934c
VD		 2812 return err;
2813
2814 /* Clear all ATU entries */
2815 err = _mv88e6xxx_atu_flush(chip, 0, true);
2816 if (err)
2817 return err;
2818
54d792f2 2819 /* Configure the IP ToS mapping registers. */
fad09c73 2820 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2821 if (err)
08a01261 2822 return err;
fad09c73 2823 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2824 if (err)
08a01261 2825 return err;
fad09c73 2826 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2827 if (err)
08a01261 2828 return err;
fad09c73 2829 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2830 if (err)
08a01261 2831 return err;
fad09c73 2832 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2833 if (err)
08a01261 2834 return err;
fad09c73 2835 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2836 if (err)
08a01261 2837 return err;
fad09c73 2838 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2839 if (err)
08a01261 2840 return err;
fad09c73 2841 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2842 if (err)
08a01261 2843 return err;
54d792f2
AL		 2844
2845 /* Configure the IEEE 802.1p priority mapping register. */
fad09c73 2846 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2847 if (err)
08a01261 2848 return err;
54d792f2 2849
9729934c
VD		 2850 /* Clear the statistics counters for all ports */
2851 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2852 GLOBAL_STATS_OP_FLUSH_ALL);
2853 if (err)
2854 return err;
2855
2856 /* Wait for the flush to complete. */
2857 err = _mv88e6xxx_stats_wait(chip);
2858 if (err)
2859 return err;
2860
2861 return 0;
2862}
2863
f22ab641
VD		 2864static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2865 int target, int port)
2866{
2867 u16 val = (target << 8) | (port & 0xf);
2868
2869 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2870}
2871
2872static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2873{
2874 int target, port;
2875 int err;
2876
2877 /* Initialize the routing port to the 32 possible target devices */
2878 for (target = 0; target < 32; ++target) {
2879 port = 0xf;
2880
2881 if (target < DSA_MAX_SWITCHES) {
2882 port = chip->ds->rtable[target];
2883 if (port == DSA_RTABLE_NONE)
2884 port = 0xf;
2885 }
2886
2887 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2888 if (err)
2889 break;
2890 }
2891
2892 return err;
2893}
2894
5154041f
VD		 2895static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2896 bool hask, u16 mask)
2897{
2898 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2899 u16 val = (num << 12) | (mask & port_mask);
2900
2901 if (hask)
2902 val |= GLOBAL2_TRUNK_MASK_HASK;
2903
2904 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2905}
2906
2907static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2908 u16 map)
2909{
2910 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2911 u16 val = (id << 11) | (map & port_mask);
2912
2913 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2914}
2915
2916static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2917{
2918 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2919 int i, err;
2920
2921 /* Clear all eight possible Trunk Mask vectors */
2922 for (i = 0; i < 8; ++i) {
2923 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2924 if (err)
2925 return err;
2926 }
2927
2928 /* Clear all sixteen possible Trunk ID routing vectors */
2929 for (i = 0; i < 16; ++i) {
2930 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2931 if (err)
2932 return err;
2933 }
2934
2935 return 0;
2936}
2937
8ec61c7f
VD		 2938static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2939{
2940 int port, err;
2941
2942 /* Init all Ingress Rate Limit resources of all ports */
2943 for (port = 0; port < chip->info->num_ports; ++port) {
2944 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2945 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2946 GLOBAL2_IRL_CMD_OP_INIT_ALL |
2947 (port << 8));
2948 if (err)
2949 break;
2950
2951 /* Wait for the operation to complete */
2952 err = _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2953 GLOBAL2_IRL_CMD_BUSY);
2954 if (err)
2955 break;
2956 }
2957
2958 return err;
2959}
2960
3b4caa1b
VD		 2961/* Indirect write to the Switch MAC/WoL/WoF register */
2962static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2963 unsigned int pointer, u8 data)
2964{
2965 u16 val = (pointer << 8) | data;
2966
2967 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2968}
2969
2970static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2971{
2972 int i, err;
2973
2974 for (i = 0; i < 6; i++) {
2975 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2976 if (err)
2977 break;
2978 }
2979
2980 return err;
2981}
2982
9bda889f
VD		 2983static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2984 u8 data)
2985{
2986 u16 val = (pointer << 8) | (data & 0x7);
2987
2988 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2989}
2990
2991static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2992{
2993 int i, err;
2994
2995 /* Clear all sixteen possible Priority Override entries */
2996 for (i = 0; i < 16; i++) {
2997 err = mv88e6xxx_g2_pot_write(chip, i, 0);
2998 if (err)
2999 break;
3000 }
3001
3002 return err;
3003}
3004
855b1932
VD		 3005static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3006{
3007 return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3008 GLOBAL2_EEPROM_CMD_BUSY |
3009 GLOBAL2_EEPROM_CMD_RUNNING);
3010}
3011
3012static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3013{
3014 int err;
3015
3016 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3017 if (err)
3018 return err;
3019
3020 return mv88e6xxx_g2_eeprom_wait(chip);
3021}
3022
3023static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3024 u8 addr, u16 *data)
3025{
3026 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3027 int err;
3028
3029 err = mv88e6xxx_g2_eeprom_wait(chip);
3030 if (err)
3031 return err;
3032
3033 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3034 if (err)
3035 return err;
3036
3037 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3038}
3039
3040static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3041 u8 addr, u16 data)
3042{
3043 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3044 int err;
3045
3046 err = mv88e6xxx_g2_eeprom_wait(chip);
3047 if (err)
3048 return err;
3049
3050 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3051 if (err)
3052 return err;
3053
3054 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3055}
3056
9729934c
VD		 3057static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3058{
47395ed2 3059 u16 reg;
9729934c 3060 int err;
9729934c 3061
47395ed2
VD		 3062 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3063 /* Consider the frames with reserved multicast destination
3064 * addresses matching 01:80:c2:00:00:2x as MGMT.
3065 */
3066 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3067 0xffff);
3068 if (err)
3069 return err;
3070 }
3071
3072 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3073 /* Consider the frames with reserved multicast destination
3074 * addresses matching 01:80:c2:00:00:0x as MGMT.
3075 */
3076 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3077 0xffff);
3078 if (err)
3079 return err;
3080 }
54d792f2
AL		 3081
3082 /* Ignore removed tag data on doubly tagged packets, disable
3083 * flow control messages, force flow control priority to the
3084 * highest, and send all special multicast frames to the CPU
3085 * port at the highest priority.
3086 */
47395ed2
VD		 3087 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3088 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3089 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3090 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3091 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
48ace4ef 3092 if (err)
08a01261 3093 return err;
54d792f2
AL		 3094
3095 /* Program the DSA routing table. */
f22ab641
VD		 3096 err = mv88e6xxx_g2_set_device_mapping(chip);
3097 if (err)
3098 return err;
54d792f2 3099
5154041f
VD		 3100 /* Clear all trunk masks and mapping. */
3101 err = mv88e6xxx_g2_clear_trunk(chip);
3102 if (err)
3103 return err;
54d792f2 3104
8ec61c7f
VD		 3105 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3106 /* Disable ingress rate limiting by resetting all per port
3107 * ingress rate limit resources to their initial state.
3108 */
3109 err = mv88e6xxx_g2_clear_irl(chip);
3110 if (err)
3111 return err;
3112 }
3113
63ed880d
VD		 3114 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3115 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3116 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3117 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
48ace4ef 3118 if (err)
08a01261 3119 return err;
63ed880d 3120 }
54d792f2 3121
9bda889f 3122 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
54d792f2 3123 /* Clear the priority override table. */
9bda889f
VD		 3124 err = mv88e6xxx_g2_clear_pot(chip);
3125 if (err)
3126 return err;
54d792f2
AL		 3127 }
3128
9729934c 3129 return 0;
08a01261
VD		 3130}
3131
f81ec90f 3132static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 3133{
fad09c73 3134 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
08a01261 3135 int err;
a1a6a4d1
VD		 3136 int i;
3137
fad09c73
VD		 3138 chip->ds = ds;
3139 ds->slave_mii_bus = chip->mdio_bus;
08a01261 3140
fad09c73 3141 mutex_lock(&chip->reg_lock);
08a01261 3142
fad09c73 3143 err = mv88e6xxx_switch_reset(chip);
08a01261
VD		 3144 if (err)
3145 goto unlock;
3146
9729934c
VD		 3147 /* Setup Switch Port Registers */
3148 for (i = 0; i < chip->info->num_ports; i++) {
3149 err = mv88e6xxx_setup_port(chip, i);
3150 if (err)
3151 goto unlock;
3152 }
3153
3154 /* Setup Switch Global 1 Registers */
3155 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 3156 if (err)
3157 goto unlock;
3158
9729934c
VD		 3159 /* Setup Switch Global 2 Registers */
3160 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3161 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 3162 if (err)
3163 goto unlock;
3164 }
08a01261 3165
6b17e864 3166unlock:
fad09c73 3167 mutex_unlock(&chip->reg_lock);
db687a56 3168
48ace4ef 3169 return err;
54d792f2
AL		 3170}
3171
3b4caa1b
VD		 3172static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3173{
3174 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3175 int err;
3176
3177 mutex_lock(&chip->reg_lock);
3178
3179 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3180 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3181 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3182 else
3183 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3184
3185 mutex_unlock(&chip->reg_lock);
3186
3187 return err;
3188}
3189
601bbae0 3190#ifdef CONFIG_NET_DSA_HWMON
57d32310
VD		 3191static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3192 int reg)
49143585 3193{
fad09c73 3194 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49143585
AL		 3195 int ret;
3196
fad09c73
VD		 3197 mutex_lock(&chip->reg_lock);
3198 ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3199 mutex_unlock(&chip->reg_lock);
75baacf0 3200
49143585
AL		 3201 return ret;
3202}
3203
57d32310
VD		 3204static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3205 int reg, int val)
49143585 3206{
fad09c73 3207 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
49143585
AL		 3208 int ret;
3209
fad09c73
VD		 3210 mutex_lock(&chip->reg_lock);
3211 ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3212 mutex_unlock(&chip->reg_lock);
75baacf0 3213
fd3a0ee4
AL		 3214 return ret;
3215}
601bbae0 3216#endif
fd3a0ee4 3217
fad09c73 3218static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
fd3a0ee4 3219{
fad09c73 3220 if (port >= 0 && port < chip->info->num_ports)
fd3a0ee4
AL		 3221 return port;
3222 return -EINVAL;
3223}
3224
b516d453 3225static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
fd3a0ee4 3226{
fad09c73
VD		 3227 struct mv88e6xxx_chip *chip = bus->priv;
3228 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
fd3a0ee4
AL		 3229 int ret;
3230
3231 if (addr < 0)
158bc065 3232 return 0xffff;
fd3a0ee4 3233
fad09c73 3234 mutex_lock(&chip->reg_lock);
8c9983a2 3235
fad09c73
VD		 3236 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3237 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3238 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3239 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
8c9983a2 3240 else
fad09c73 3241 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
8c9983a2 3242
fad09c73 3243 mutex_unlock(&chip->reg_lock);
fd3a0ee4
AL		 3244 return ret;
3245}
3246
b516d453 3247static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
03a4a540 3248 u16 val)
fd3a0ee4 3249{
fad09c73
VD		 3250 struct mv88e6xxx_chip *chip = bus->priv;
3251 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
fd3a0ee4
AL		 3252 int ret;
3253
3254 if (addr < 0)
158bc065 3255 return 0xffff;
fd3a0ee4 3256
fad09c73 3257 mutex_lock(&chip->reg_lock);
8c9983a2 3258
fad09c73
VD		 3259 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3260 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3261 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3262 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
8c9983a2 3263 else
fad09c73 3264 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
8c9983a2 3265
fad09c73 3266 mutex_unlock(&chip->reg_lock);
fd3a0ee4
AL		 3267 return ret;
3268}
3269
fad09c73 3270static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 3271 struct device_node *np)
3272{
3273 static int index;
3274 struct mii_bus *bus;
3275 int err;
3276
fad09c73
VD		 3277 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3278 mv88e6xxx_ppu_state_init(chip);
b516d453
AL		 3279
3280 if (np)
fad09c73 3281 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 3282
fad09c73 3283 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 3284 if (!bus)
3285 return -ENOMEM;
3286
fad09c73 3287 bus->priv = (void *)chip;
b516d453
AL		 3288 if (np) {
3289 bus->name = np->full_name;
3290 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3291 } else {
3292 bus->name = "mv88e6xxx SMI";
3293 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3294 }
3295
3296 bus->read = mv88e6xxx_mdio_read;
3297 bus->write = mv88e6xxx_mdio_write;
fad09c73 3298 bus->parent = chip->dev;
b516d453 3299
fad09c73
VD		 3300 if (chip->mdio_np)
3301 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 3302 else
3303 err = mdiobus_register(bus);
3304 if (err) {
fad09c73 3305 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 3306 goto out;
3307 }
fad09c73 3308 chip->mdio_bus = bus;
b516d453
AL		 3309
3310 return 0;
3311
3312out:
fad09c73
VD		 3313 if (chip->mdio_np)
3314 of_node_put(chip->mdio_np);
b516d453
AL		 3315
3316 return err;
3317}
3318
fad09c73 3319static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3320
3321{
fad09c73 3322 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 3323
3324 mdiobus_unregister(bus);
3325
fad09c73
VD		 3326 if (chip->mdio_np)
3327 of_node_put(chip->mdio_np);
b516d453
AL		 3328}
3329
c22995c5
GR		 3330#ifdef CONFIG_NET_DSA_HWMON
3331
3332static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3333{
fad09c73 3334 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
c22995c5
GR		 3335 int ret;
3336 int val;
3337
3338 *temp = 0;
3339
fad09c73 3340 mutex_lock(&chip->reg_lock);
c22995c5 3341
fad09c73 3342 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3343 if (ret < 0)
3344 goto error;
3345
3346 /* Enable temperature sensor */
fad09c73 3347 ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
c22995c5
GR		 3348 if (ret < 0)
3349 goto error;
3350
fad09c73 3351 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
c22995c5
GR		 3352 if (ret < 0)
3353 goto error;
3354
3355 /* Wait for temperature to stabilize */
3356 usleep_range(10000, 12000);
3357
fad09c73 3358 val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
c22995c5
GR		 3359 if (val < 0) {
3360 ret = val;
3361 goto error;
3362 }
3363
3364 /* Disable temperature sensor */
fad09c73 3365 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
c22995c5
GR		 3366 if (ret < 0)
3367 goto error;
3368
3369 *temp = ((val & 0x1f) - 5) * 5;
3370
3371error:
fad09c73
VD		 3372 mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3373 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3374 return ret;
3375}
3376
3377static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3378{
fad09c73
VD		 3379 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3380 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3381 int ret;
3382
3383 *temp = 0;
3384
03a4a540 3385 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
c22995c5
GR		 3386 if (ret < 0)
3387 return ret;
3388
3389 *temp = (ret & 0xff) - 25;
3390
3391 return 0;
3392}
3393
f81ec90f 3394static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3395{
fad09c73 3396 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
158bc065 3397
fad09c73 3398 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3399 return -EOPNOTSUPP;
3400
fad09c73 3401 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3402 return mv88e63xx_get_temp(ds, temp);
3403
3404 return mv88e61xx_get_temp(ds, temp);
3405}
3406
f81ec90f 3407static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3408{
fad09c73
VD		 3409 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3410 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3411 int ret;
3412
fad09c73 3413 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3414 return -EOPNOTSUPP;
3415
3416 *temp = 0;
3417
03a4a540 3418 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
c22995c5
GR		 3419 if (ret < 0)
3420 return ret;
3421
3422 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3423
3424 return 0;
3425}
3426
f81ec90f 3427static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3428{
fad09c73
VD		 3429 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3430 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3431 int ret;
3432
fad09c73 3433 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3434 return -EOPNOTSUPP;
3435
03a4a540 3436 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
c22995c5
GR		 3437 if (ret < 0)
3438 return ret;
3439 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
03a4a540
AL		 3440 return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3441 (ret & 0xe0ff) | (temp << 8));
c22995c5
GR		 3442}
3443
f81ec90f 3444static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3445{
fad09c73
VD		 3446 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3447 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
c22995c5
GR		 3448 int ret;
3449
fad09c73 3450 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3451 return -EOPNOTSUPP;
3452
3453 *alarm = false;
3454
03a4a540 3455 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
c22995c5
GR		 3456 if (ret < 0)
3457 return ret;
3458
3459 *alarm = !!(ret & 0x40);
3460
3461 return 0;
3462}
3463#endif /* CONFIG_NET_DSA_HWMON */
3464
855b1932
VD		 3465static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3466{
3467 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3468
3469 return chip->eeprom_len;
3470}
3471
3472static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3473 struct ethtool_eeprom *eeprom, u8 *data)
3474{
3475 unsigned int offset = eeprom->offset;
3476 unsigned int len = eeprom->len;
3477 u16 val;
3478 int err;
3479
3480 eeprom->len = 0;
3481
3482 if (offset & 1) {
3483 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3484 if (err)
3485 return err;
3486
3487 *data++ = (val >> 8) & 0xff;
3488
3489 offset++;
3490 len--;
3491 eeprom->len++;
3492 }
3493
3494 while (len >= 2) {
3495 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3496 if (err)
3497 return err;
3498
3499 *data++ = val & 0xff;
3500 *data++ = (val >> 8) & 0xff;
3501
3502 offset += 2;
3503 len -= 2;
3504 eeprom->len += 2;
3505 }
3506
3507 if (len) {
3508 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3509 if (err)
3510 return err;
3511
3512 *data++ = val & 0xff;
3513
3514 offset++;
3515 len--;
3516 eeprom->len++;
3517 }
3518
3519 return 0;
3520}
3521
3522static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3523 struct ethtool_eeprom *eeprom, u8 *data)
3524{
3525 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3526 int err;
3527
3528 mutex_lock(&chip->reg_lock);
3529
3530 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3531 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3532 else
3533 err = -EOPNOTSUPP;
3534
3535 mutex_unlock(&chip->reg_lock);
3536
3537 if (err)
3538 return err;
3539
3540 eeprom->magic = 0xc3ec4951;
3541
3542 return 0;
3543}
3544
3545static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3546 struct ethtool_eeprom *eeprom, u8 *data)
3547{
3548 unsigned int offset = eeprom->offset;
3549 unsigned int len = eeprom->len;
3550 u16 val;
3551 int err;
3552
3553 /* Ensure the RO WriteEn bit is set */
3554 err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3555 if (err)
3556 return err;
3557
3558 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3559 return -EROFS;
3560
3561 eeprom->len = 0;
3562
3563 if (offset & 1) {
3564 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3565 if (err)
3566 return err;
3567
3568 val = (*data++ << 8) | (val & 0xff);
3569
3570 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3571 if (err)
3572 return err;
3573
3574 offset++;
3575 len--;
3576 eeprom->len++;
3577 }
3578
3579 while (len >= 2) {
3580 val = *data++;
3581 val |= *data++ << 8;
3582
3583 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3584 if (err)
3585 return err;
3586
3587 offset += 2;
3588 len -= 2;
3589 eeprom->len += 2;
3590 }
3591
3592 if (len) {
3593 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3594 if (err)
3595 return err;
3596
3597 val = (val & 0xff00) | *data++;
3598
3599 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3600 if (err)
3601 return err;
3602
3603 offset++;
3604 len--;
3605 eeprom->len++;
3606 }
3607
3608 return 0;
3609}
3610
3611static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3612 struct ethtool_eeprom *eeprom, u8 *data)
3613{
3614 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3615 int err;
3616
3617 if (eeprom->magic != 0xc3ec4951)
3618 return -EINVAL;
3619
3620 mutex_lock(&chip->reg_lock);
3621
3622 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3623 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3624 else
3625 err = -EOPNOTSUPP;
3626
3627 mutex_unlock(&chip->reg_lock);
3628
3629 return err;
3630}
3631
f81ec90f
VD		 3632static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3633 [MV88E6085] = {
3634 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3635 .family = MV88E6XXX_FAMILY_6097,
3636 .name = "Marvell 88E6085",
3637 .num_databases = 4096,
3638 .num_ports = 10,
9dddd478 3639 .port_base_addr = 0x10,
acddbd21 3640 .age_time_coeff = 15000,
f81ec90f
VD		 3641 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3642 },
3643
3644 [MV88E6095] = {
3645 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3646 .family = MV88E6XXX_FAMILY_6095,
3647 .name = "Marvell 88E6095/88E6095F",
3648 .num_databases = 256,
3649 .num_ports = 11,
9dddd478 3650 .port_base_addr = 0x10,
acddbd21 3651 .age_time_coeff = 15000,
f81ec90f
VD		 3652 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3653 },
3654
3655 [MV88E6123] = {
3656 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3657 .family = MV88E6XXX_FAMILY_6165,
3658 .name = "Marvell 88E6123",
3659 .num_databases = 4096,
3660 .num_ports = 3,
9dddd478 3661 .port_base_addr = 0x10,
acddbd21 3662 .age_time_coeff = 15000,
f81ec90f
VD		 3663 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3664 },
3665
3666 [MV88E6131] = {
3667 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3668 .family = MV88E6XXX_FAMILY_6185,
3669 .name = "Marvell 88E6131",
3670 .num_databases = 256,
3671 .num_ports = 8,
9dddd478 3672 .port_base_addr = 0x10,
acddbd21 3673 .age_time_coeff = 15000,
f81ec90f
VD		 3674 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3675 },
3676
3677 [MV88E6161] = {
3678 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3679 .family = MV88E6XXX_FAMILY_6165,
3680 .name = "Marvell 88E6161",
3681 .num_databases = 4096,
3682 .num_ports = 6,
9dddd478 3683 .port_base_addr = 0x10,
acddbd21 3684 .age_time_coeff = 15000,
f81ec90f
VD		 3685 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3686 },
3687
3688 [MV88E6165] = {
3689 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3690 .family = MV88E6XXX_FAMILY_6165,
3691 .name = "Marvell 88E6165",
3692 .num_databases = 4096,
3693 .num_ports = 6,
9dddd478 3694 .port_base_addr = 0x10,
acddbd21 3695 .age_time_coeff = 15000,
f81ec90f
VD		 3696 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3697 },
3698
3699 [MV88E6171] = {
3700 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3701 .family = MV88E6XXX_FAMILY_6351,
3702 .name = "Marvell 88E6171",
3703 .num_databases = 4096,
3704 .num_ports = 7,
9dddd478 3705 .port_base_addr = 0x10,
acddbd21 3706 .age_time_coeff = 15000,
f81ec90f
VD		 3707 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3708 },
3709
3710 [MV88E6172] = {
3711 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3712 .family = MV88E6XXX_FAMILY_6352,
3713 .name = "Marvell 88E6172",
3714 .num_databases = 4096,
3715 .num_ports = 7,
9dddd478 3716 .port_base_addr = 0x10,
acddbd21 3717 .age_time_coeff = 15000,
f81ec90f
VD		 3718 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3719 },
3720
3721 [MV88E6175] = {
3722 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3723 .family = MV88E6XXX_FAMILY_6351,
3724 .name = "Marvell 88E6175",
3725 .num_databases = 4096,
3726 .num_ports = 7,
9dddd478 3727 .port_base_addr = 0x10,
acddbd21 3728 .age_time_coeff = 15000,
f81ec90f
VD		 3729 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3730 },
3731
3732 [MV88E6176] = {
3733 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3734 .family = MV88E6XXX_FAMILY_6352,
3735 .name = "Marvell 88E6176",
3736 .num_databases = 4096,
3737 .num_ports = 7,
9dddd478 3738 .port_base_addr = 0x10,
acddbd21 3739 .age_time_coeff = 15000,
f81ec90f
VD		 3740 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3741 },
3742
3743 [MV88E6185] = {
3744 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3745 .family = MV88E6XXX_FAMILY_6185,
3746 .name = "Marvell 88E6185",
3747 .num_databases = 256,
3748 .num_ports = 10,
9dddd478 3749 .port_base_addr = 0x10,
acddbd21 3750 .age_time_coeff = 15000,
f81ec90f
VD		 3751 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3752 },
3753
3754 [MV88E6240] = {
3755 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3756 .family = MV88E6XXX_FAMILY_6352,
3757 .name = "Marvell 88E6240",
3758 .num_databases = 4096,
3759 .num_ports = 7,
9dddd478 3760 .port_base_addr = 0x10,
acddbd21 3761 .age_time_coeff = 15000,
f81ec90f
VD		 3762 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3763 },
3764
3765 [MV88E6320] = {
3766 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3767 .family = MV88E6XXX_FAMILY_6320,
3768 .name = "Marvell 88E6320",
3769 .num_databases = 4096,
3770 .num_ports = 7,
9dddd478 3771 .port_base_addr = 0x10,
acddbd21 3772 .age_time_coeff = 15000,
f81ec90f
VD		 3773 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3774 },
3775
3776 [MV88E6321] = {
3777 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3778 .family = MV88E6XXX_FAMILY_6320,
3779 .name = "Marvell 88E6321",
3780 .num_databases = 4096,
3781 .num_ports = 7,
9dddd478 3782 .port_base_addr = 0x10,
acddbd21 3783 .age_time_coeff = 15000,
f81ec90f
VD		 3784 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3785 },
3786
3787 [MV88E6350] = {
3788 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3789 .family = MV88E6XXX_FAMILY_6351,
3790 .name = "Marvell 88E6350",
3791 .num_databases = 4096,
3792 .num_ports = 7,
9dddd478 3793 .port_base_addr = 0x10,
acddbd21 3794 .age_time_coeff = 15000,
f81ec90f
VD		 3795 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3796 },
3797
3798 [MV88E6351] = {
3799 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3800 .family = MV88E6XXX_FAMILY_6351,
3801 .name = "Marvell 88E6351",
3802 .num_databases = 4096,
3803 .num_ports = 7,
9dddd478 3804 .port_base_addr = 0x10,
acddbd21 3805 .age_time_coeff = 15000,
f81ec90f
VD		 3806 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3807 },
3808
3809 [MV88E6352] = {
3810 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3811 .family = MV88E6XXX_FAMILY_6352,
3812 .name = "Marvell 88E6352",
3813 .num_databases = 4096,
3814 .num_ports = 7,
9dddd478 3815 .port_base_addr = 0x10,
acddbd21 3816 .age_time_coeff = 15000,
f81ec90f
VD		 3817 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3818 },
3819};
3820
5f7c0367 3821static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3822{
a439c061 3823 int i;
b9b37713 3824
5f7c0367
VD		 3825 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3826 if (mv88e6xxx_table[i].prod_num == prod_num)
3827 return &mv88e6xxx_table[i];
b9b37713 3828
b9b37713
VD		 3829 return NULL;
3830}
3831
fad09c73 3832static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3833{
3834 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3835 unsigned int prod_num, rev;
3836 u16 id;
3837 int err;
bc46a3d5 3838
8f6345b2
VD		 3839 mutex_lock(&chip->reg_lock);
3840 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3841 mutex_unlock(&chip->reg_lock);
3842 if (err)
3843 return err;
bc46a3d5
VD		 3844
3845 prod_num = (id & 0xfff0) >> 4;
3846 rev = id & 0x000f;
3847
3848 info = mv88e6xxx_lookup_info(prod_num);
3849 if (!info)
3850 return -ENODEV;
3851
caac8545 3852 /* Update the compatible info with the probed one */
fad09c73 3853 chip->info = info;
bc46a3d5 3854
fad09c73
VD		 3855 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3856 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3857
3858 return 0;
3859}
3860
fad09c73 3861static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3862{
fad09c73 3863 struct mv88e6xxx_chip *chip;
469d729f 3864
fad09c73
VD		 3865 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3866 if (!chip)
469d729f
VD		 3867 return NULL;
3868
fad09c73 3869 chip->dev = dev;
469d729f 3870
fad09c73 3871 mutex_init(&chip->reg_lock);
469d729f 3872
fad09c73 3873 return chip;
469d729f
VD		 3874}
3875
fad09c73 3876static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3877 struct mii_bus *bus, int sw_addr)
3878{
3879 /* ADDR[0] pin is unavailable externally and considered zero */
3880 if (sw_addr & 0x1)
3881 return -EINVAL;
3882
914b32f6 3883 if (sw_addr == 0)
fad09c73
VD		 3884 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3885 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_MULTI_CHIP))
3886 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3887 else
3888 return -EINVAL;
3889
fad09c73
VD		 3890 chip->bus = bus;
3891 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3892
3893 return 0;
3894}
3895
fcdce7d0
AL		 3896static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3897 struct device *host_dev, int sw_addr,
3898 void **priv)
a77d43f1 3899{
fad09c73 3900 struct mv88e6xxx_chip *chip;
a439c061 3901 struct mii_bus *bus;
b516d453 3902 int err;
a77d43f1 3903
a439c061 3904 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3905 if (!bus)
3906 return NULL;
3907
fad09c73
VD		 3908 chip = mv88e6xxx_alloc_chip(dsa_dev);
3909 if (!chip)
469d729f
VD		 3910 return NULL;
3911
caac8545 3912 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3913 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3914
fad09c73 3915 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3916 if (err)
3917 goto free;
3918
fad09c73 3919 err = mv88e6xxx_detect(chip);
bc46a3d5 3920 if (err)
469d729f 3921 goto free;
a439c061 3922
fad09c73 3923 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3924 if (err)
469d729f 3925 goto free;
b516d453 3926
fad09c73 3927 *priv = chip;
a439c061 3928
fad09c73 3929 return chip->info->name;
469d729f 3930free:
fad09c73 3931 devm_kfree(dsa_dev, chip);
469d729f
VD		 3932
3933 return NULL;
a77d43f1
AL		 3934}
3935
57d32310 3936static struct dsa_switch_driver mv88e6xxx_switch_driver = {
f81ec90f 3937 .tag_protocol = DSA_TAG_PROTO_EDSA,
fcdce7d0 3938 .probe = mv88e6xxx_drv_probe,
f81ec90f
VD		 3939 .setup = mv88e6xxx_setup,
3940 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3941 .adjust_link = mv88e6xxx_adjust_link,
3942 .get_strings = mv88e6xxx_get_strings,
3943 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3944 .get_sset_count = mv88e6xxx_get_sset_count,
3945 .set_eee = mv88e6xxx_set_eee,
3946 .get_eee = mv88e6xxx_get_eee,
3947#ifdef CONFIG_NET_DSA_HWMON
3948 .get_temp = mv88e6xxx_get_temp,
3949 .get_temp_limit = mv88e6xxx_get_temp_limit,
3950 .set_temp_limit = mv88e6xxx_set_temp_limit,
3951 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3952#endif
f8cd8753 3953 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3954 .get_eeprom = mv88e6xxx_get_eeprom,
3955 .set_eeprom = mv88e6xxx_set_eeprom,
3956 .get_regs_len = mv88e6xxx_get_regs_len,
3957 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3958 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3959 .port_bridge_join = mv88e6xxx_port_bridge_join,
3960 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3961 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3962 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3963 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3964 .port_vlan_add = mv88e6xxx_port_vlan_add,
3965 .port_vlan_del = mv88e6xxx_port_vlan_del,
3966 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3967 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3968 .port_fdb_add = mv88e6xxx_port_fdb_add,
3969 .port_fdb_del = mv88e6xxx_port_fdb_del,
3970 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3971};
3972
fad09c73 3973static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 3974 struct device_node *np)
3975{
fad09c73 3976 struct device *dev = chip->dev;
b7e66a5f
VD		 3977 struct dsa_switch *ds;
3978
3979 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3980 if (!ds)
3981 return -ENOMEM;
3982
3983 ds->dev = dev;
fad09c73 3984 ds->priv = chip;
b7e66a5f
VD		 3985 ds->drv = &mv88e6xxx_switch_driver;
3986
3987 dev_set_drvdata(dev, ds);
3988
3989 return dsa_register_switch(ds, np);
3990}
3991
fad09c73 3992static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3993{
fad09c73 3994 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3995}
3996
57d32310 3997static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3998{
14c7b3c3 3999 struct device *dev = &mdiodev->dev;
f8cd8753 4000 struct device_node *np = dev->of_node;
caac8545 4001 const struct mv88e6xxx_info *compat_info;
fad09c73 4002 struct mv88e6xxx_chip *chip;
f8cd8753 4003 u32 eeprom_len;
52638f71 4004 int err;
14c7b3c3 4005
caac8545
VD		 4006 compat_info = of_device_get_match_data(dev);
4007 if (!compat_info)
4008 return -EINVAL;
4009
fad09c73
VD		 4010 chip = mv88e6xxx_alloc_chip(dev);
4011 if (!chip)
14c7b3c3
AL		 4012 return -ENOMEM;
4013
fad09c73 4014 chip->info = compat_info;
caac8545 4015
fad09c73 4016 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 4017 if (err)
4018 return err;
14c7b3c3 4019
fad09c73 4020 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 4021 if (err)
4022 return err;
14c7b3c3 4023
fad09c73
VD		 4024 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4025 if (IS_ERR(chip->reset))
4026 return PTR_ERR(chip->reset);
52638f71 4027
855b1932 4028 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
f8cd8753 4029 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 4030 chip->eeprom_len = eeprom_len;
f8cd8753 4031
fad09c73 4032 err = mv88e6xxx_mdio_register(chip, np);
b516d453
AL		 4033 if (err)
4034 return err;
4035
fad09c73 4036 err = mv88e6xxx_register_switch(chip, np);
83c0afae 4037 if (err) {
fad09c73 4038 mv88e6xxx_mdio_unregister(chip);
83c0afae
AL		 4039 return err;
4040 }
4041
98e67308
BH		 4042 return 0;
4043}
14c7b3c3
AL		 4044
4045static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4046{
4047 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
fad09c73 4048 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
14c7b3c3 4049
fad09c73
VD		 4050 mv88e6xxx_unregister_switch(chip);
4051 mv88e6xxx_mdio_unregister(chip);
14c7b3c3
AL		 4052}
4053
4054static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 4055 {
4056 .compatible = "marvell,mv88e6085",
4057 .data = &mv88e6xxx_table[MV88E6085],
4058 },
14c7b3c3
AL		 4059 { /* sentinel */ },
4060};
4061
4062MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4063
4064static struct mdio_driver mv88e6xxx_driver = {
4065 .probe = mv88e6xxx_probe,
4066 .remove = mv88e6xxx_remove,
4067 .mdiodrv.driver = {
4068 .name = "mv88e6085",
4069 .of_match_table = mv88e6xxx_of_match,
4070 },
4071};
4072
4073static int __init mv88e6xxx_init(void)
4074{
4075 register_switch_driver(&mv88e6xxx_switch_driver);
4076 return mdio_driver_register(&mv88e6xxx_driver);
4077}
98e67308
BH		 4078module_init(mv88e6xxx_init);
4079
4080static void __exit mv88e6xxx_cleanup(void)
4081{
14c7b3c3 4082 mdio_driver_unregister(&mv88e6xxx_driver);
f81ec90f 4083 unregister_switch_driver(&mv88e6xxx_switch_driver);
98e67308
BH		 4084}
4085module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 4086
4087MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4088MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4089MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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