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Merge remote-tracking branch 'omap_dss2/for-next'
[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
91da11f8 1/*
0d3cd4b6
VD		 2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
91da11f8
LB		 4 * Copyright (c) 2008 Marvell Semiconductor
5 *
b8fee957
VD		 6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
14c7b3c3
AL		 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
91da11f8
LB		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
19b2f97e 17#include <linux/delay.h>
defb05b9 18#include <linux/etherdevice.h>
dea87024 19#include <linux/ethtool.h>
facd95b2 20#include <linux/if_bridge.h>
19b2f97e 21#include <linux/jiffies.h>
91da11f8 22#include <linux/list.h>
14c7b3c3 23#include <linux/mdio.h>
2bbba277 24#include <linux/module.h>
caac8545 25#include <linux/of_device.h>
b516d453 26#include <linux/of_mdio.h>
91da11f8 27#include <linux/netdevice.h>
c8c1b39a 28#include <linux/gpio/consumer.h>
91da11f8 29#include <linux/phy.h>
c8f0b869 30#include <net/dsa.h>
1f36faf2 31#include <net/switchdev.h>
ec561276 32
91da11f8 33#include "mv88e6xxx.h"
ec561276 34#include "global2.h"
91da11f8 35
fad09c73 36static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 37{
fad09c73
VD		 38 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
39 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 40 dump_stack();
41 }
42}
43
914b32f6
VD		 44/* The switch ADDR[4:1] configuration pins define the chip SMI device address
45 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
46 *
47 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
48 * is the only device connected to the SMI master. In this mode it responds to
49 * all 32 possible SMI addresses, and thus maps directly the internal devices.
50 *
51 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
52 * multiple devices to share the SMI interface. In this mode it responds to only
53 * 2 registers, used to indirectly access the internal SMI devices.
91da11f8 54 */
914b32f6 55
fad09c73 56static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 57 int addr, int reg, u16 *val)
58{
fad09c73 59 if (!chip->smi_ops)
914b32f6
VD		 60 return -EOPNOTSUPP;
61
fad09c73 62 return chip->smi_ops->read(chip, addr, reg, val);
914b32f6
VD		 63}
64
fad09c73 65static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 66 int addr, int reg, u16 val)
67{
fad09c73 68 if (!chip->smi_ops)
914b32f6
VD		 69 return -EOPNOTSUPP;
70
fad09c73 71 return chip->smi_ops->write(chip, addr, reg, val);
914b32f6
VD		 72}
73
fad09c73 74static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
914b32f6
VD		 75 int addr, int reg, u16 *val)
76{
77 int ret;
78
fad09c73 79 ret = mdiobus_read_nested(chip->bus, addr, reg);
914b32f6
VD		 80 if (ret < 0)
81 return ret;
82
83 *val = ret & 0xffff;
84
85 return 0;
86}
87
fad09c73 88static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
914b32f6
VD		 89 int addr, int reg, u16 val)
90{
91 int ret;
92
fad09c73 93 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
914b32f6
VD		 94 if (ret < 0)
95 return ret;
96
97 return 0;
98}
99
100static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
101 .read = mv88e6xxx_smi_single_chip_read,
102 .write = mv88e6xxx_smi_single_chip_write,
103};
104
fad09c73 105static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 106{
107 int ret;
108 int i;
109
110 for (i = 0; i < 16; i++) {
fad09c73 111 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
91da11f8
LB		 112 if (ret < 0)
113 return ret;
114
cca8b133 115 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 116 return 0;
117 }
118
119 return -ETIMEDOUT;
120}
121
fad09c73 122static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
914b32f6 123 int addr, int reg, u16 *val)
91da11f8
LB		 124{
125 int ret;
126
3675c8d7 127 /* Wait for the bus to become free. */
fad09c73 128 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 129 if (ret < 0)
130 return ret;
131
3675c8d7 132 /* Transmit the read command. */
fad09c73 133 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 134 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 135 if (ret < 0)
136 return ret;
137
3675c8d7 138 /* Wait for the read command to complete. */
fad09c73 139 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 140 if (ret < 0)
141 return ret;
142
3675c8d7 143 /* Read the data. */
fad09c73 144 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
bb92ea5e
VD		 145 if (ret < 0)
146 return ret;
147
914b32f6 148 *val = ret & 0xffff;
91da11f8 149
914b32f6 150 return 0;
8d6d09e7
GR		 151}
152
fad09c73 153static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
914b32f6 154 int addr, int reg, u16 val)
91da11f8
LB		 155{
156 int ret;
157
3675c8d7 158 /* Wait for the bus to become free. */
fad09c73 159 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 160 if (ret < 0)
161 return ret;
162
3675c8d7 163 /* Transmit the data to write. */
fad09c73 164 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
91da11f8
LB		 165 if (ret < 0)
166 return ret;
167
3675c8d7 168 /* Transmit the write command. */
fad09c73 169 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
6e899e6c 170 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 171 if (ret < 0)
172 return ret;
173
3675c8d7 174 /* Wait for the write command to complete. */
fad09c73 175 ret = mv88e6xxx_smi_multi_chip_wait(chip);
91da11f8
LB		 176 if (ret < 0)
177 return ret;
178
179 return 0;
180}
181
914b32f6
VD		 182static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
183 .read = mv88e6xxx_smi_multi_chip_read,
184 .write = mv88e6xxx_smi_multi_chip_write,
185};
186
ec561276 187int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 188{
189 int err;
190
fad09c73 191 assert_reg_lock(chip);
914b32f6 192
fad09c73 193 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 194 if (err)
195 return err;
196
fad09c73 197 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 198 addr, reg, *val);
199
200 return 0;
201}
202
ec561276 203int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 204{
914b32f6
VD		 205 int err;
206
fad09c73 207 assert_reg_lock(chip);
91da11f8 208
fad09c73 209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 210 if (err)
211 return err;
212
fad09c73 213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 214 addr, reg, val);
215
914b32f6
VD		 216 return 0;
217}
218
e57e5e77
VD		 219static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
220 int reg, u16 *val)
221{
222 int addr = phy; /* PHY devices addresses start at 0x0 */
223
224 if (!chip->phy_ops)
225 return -EOPNOTSUPP;
226
227 return chip->phy_ops->read(chip, addr, reg, val);
228}
229
230static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
231 int reg, u16 val)
232{
233 int addr = phy; /* PHY devices addresses start at 0x0 */
234
235 if (!chip->phy_ops)
236 return -EOPNOTSUPP;
237
238 return chip->phy_ops->write(chip, addr, reg, val);
239}
240
09cb7dfd
VD		 241static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
242{
243 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
244 return -EOPNOTSUPP;
245
246 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
247}
248
249static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
250{
251 int err;
252
253 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
254 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
255 if (unlikely(err)) {
256 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
257 phy, err);
258 }
259}
260
261static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
262 u8 page, int reg, u16 *val)
263{
264 int err;
265
266 /* There is no paging for registers 22 */
267 if (reg == PHY_PAGE)
268 return -EINVAL;
269
270 err = mv88e6xxx_phy_page_get(chip, phy, page);
271 if (!err) {
272 err = mv88e6xxx_phy_read(chip, phy, reg, val);
273 mv88e6xxx_phy_page_put(chip, phy);
274 }
275
276 return err;
277}
278
279static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
280 u8 page, int reg, u16 val)
281{
282 int err;
283
284 /* There is no paging for registers 22 */
285 if (reg == PHY_PAGE)
286 return -EINVAL;
287
288 err = mv88e6xxx_phy_page_get(chip, phy, page);
289 if (!err) {
290 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
291 mv88e6xxx_phy_page_put(chip, phy);
292 }
293
294 return err;
295}
296
297static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
298{
299 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
300 reg, val);
301}
302
303static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
304{
305 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307}
308
ec561276 309int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
2d79af6e 310{
6441e669 311 int i;
2d79af6e 312
6441e669 313 for (i = 0; i < 16; i++) {
2d79af6e
VD		 314 u16 val;
315 int err;
316
317 err = mv88e6xxx_read(chip, addr, reg, &val);
318 if (err)
319 return err;
320
321 if (!(val & mask))
322 return 0;
323
324 usleep_range(1000, 2000);
325 }
326
30853553 327 dev_err(chip->dev, "Timeout while waiting for switch\n");
2d79af6e
VD		 328 return -ETIMEDOUT;
329}
330
f22ab641 331/* Indirect write to single pointer-data register with an Update bit */
ec561276 332int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
f22ab641
VD		 333{
334 u16 val;
0f02b4f7 335 int err;
f22ab641
VD		 336
337 /* Wait until the previous operation is completed */
0f02b4f7
AL		 338 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
339 if (err)
340 return err;
f22ab641
VD		 341
342 /* Set the Update bit to trigger a write operation */
343 val = BIT(15) | update;
344
345 return mv88e6xxx_write(chip, addr, reg, val);
346}
347
fad09c73 348static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
914b32f6
VD		 349{
350 u16 val;
351 int err;
352
fad09c73 353 err = mv88e6xxx_read(chip, addr, reg, &val);
914b32f6
VD		 354 if (err)
355 return err;
356
357 return val;
358}
359
fad09c73 360static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
914b32f6
VD		 361 int reg, u16 val)
362{
fad09c73 363 return mv88e6xxx_write(chip, addr, reg, val);
8d6d09e7
GR		 364}
365
fad09c73 366static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
2e5f0320
LB		 367{
368 int ret;
6441e669 369 int i;
2e5f0320 370
fad09c73 371 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 372 if (ret < 0)
373 return ret;
374
fad09c73 375 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
8c9983a2 376 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 377 if (ret)
378 return ret;
2e5f0320 379
6441e669 380 for (i = 0; i < 16; i++) {
fad09c73 381 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 382 if (ret < 0)
383 return ret;
384
19b2f97e 385 usleep_range(1000, 2000);
cca8b133
AL		 386 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
387 GLOBAL_STATUS_PPU_POLLING)
85686581 388 return 0;
2e5f0320
LB		 389 }
390
391 return -ETIMEDOUT;
392}
393
fad09c73 394static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
2e5f0320 395{
6441e669 396 int ret, err, i;
2e5f0320 397
fad09c73 398 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 399 if (ret < 0)
400 return ret;
401
fad09c73 402 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
762eb67b 403 ret | GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 404 if (err)
405 return err;
2e5f0320 406
6441e669 407 for (i = 0; i < 16; i++) {
fad09c73 408 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 409 if (ret < 0)
410 return ret;
411
19b2f97e 412 usleep_range(1000, 2000);
cca8b133
AL		 413 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
414 GLOBAL_STATUS_PPU_POLLING)
85686581 415 return 0;
2e5f0320
LB		 416 }
417
418 return -ETIMEDOUT;
419}
420
421static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
422{
fad09c73 423 struct mv88e6xxx_chip *chip;
2e5f0320 424
fad09c73 425 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
762eb67b 426
fad09c73 427 mutex_lock(&chip->reg_lock);
762eb67b 428
fad09c73
VD		 429 if (mutex_trylock(&chip->ppu_mutex)) {
430 if (mv88e6xxx_ppu_enable(chip) == 0)
431 chip->ppu_disabled = 0;
432 mutex_unlock(&chip->ppu_mutex);
2e5f0320 433 }
762eb67b 434
fad09c73 435 mutex_unlock(&chip->reg_lock);
2e5f0320
LB		 436}
437
438static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
439{
fad09c73 440 struct mv88e6xxx_chip *chip = (void *)_ps;
2e5f0320 441
fad09c73 442 schedule_work(&chip->ppu_work);
2e5f0320
LB		 443}
444
fad09c73 445static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
2e5f0320 446{
2e5f0320
LB		 447 int ret;
448
fad09c73 449 mutex_lock(&chip->ppu_mutex);
2e5f0320 450
3675c8d7 451 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 452 * we can access the PHY registers. If it was already
453 * disabled, cancel the timer that is going to re-enable
454 * it.
455 */
fad09c73
VD		 456 if (!chip->ppu_disabled) {
457 ret = mv88e6xxx_ppu_disable(chip);
85686581 458 if (ret < 0) {
fad09c73 459 mutex_unlock(&chip->ppu_mutex);
85686581
BG		 460 return ret;
461 }
fad09c73 462 chip->ppu_disabled = 1;
2e5f0320 463 } else {
fad09c73 464 del_timer(&chip->ppu_timer);
85686581 465 ret = 0;
2e5f0320
LB		 466 }
467
468 return ret;
469}
470
fad09c73 471static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
2e5f0320 472{
3675c8d7 473 /* Schedule a timer to re-enable the PHY polling unit. */
fad09c73
VD		 474 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
475 mutex_unlock(&chip->ppu_mutex);
2e5f0320
LB		 476}
477
fad09c73 478static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
2e5f0320 479{
fad09c73
VD		 480 mutex_init(&chip->ppu_mutex);
481 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
482 init_timer(&chip->ppu_timer);
483 chip->ppu_timer.data = (unsigned long)chip;
484 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
2e5f0320
LB		 485}
486
930188ce
AL		 487static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
488{
489 del_timer_sync(&chip->ppu_timer);
490}
491
e57e5e77
VD		 492static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
493 int reg, u16 *val)
2e5f0320 494{
e57e5e77 495 int err;
2e5f0320 496
e57e5e77
VD		 497 err = mv88e6xxx_ppu_access_get(chip);
498 if (!err) {
499 err = mv88e6xxx_read(chip, addr, reg, val);
fad09c73 500 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 501 }
502
e57e5e77 503 return err;
2e5f0320
LB		 504}
505
e57e5e77
VD		 506static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
507 int reg, u16 val)
2e5f0320 508{
e57e5e77 509 int err;
2e5f0320 510
e57e5e77
VD		 511 err = mv88e6xxx_ppu_access_get(chip);
512 if (!err) {
513 err = mv88e6xxx_write(chip, addr, reg, val);
fad09c73 514 mv88e6xxx_ppu_access_put(chip);
2e5f0320
LB		 515 }
516
e57e5e77 517 return err;
2e5f0320 518}
2e5f0320 519
e57e5e77
VD		 520static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
521 .read = mv88e6xxx_phy_ppu_read,
522 .write = mv88e6xxx_phy_ppu_write,
523};
524
fad09c73 525static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
54d792f2 526{
fad09c73 527 return chip->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 528}
529
fad09c73 530static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
54d792f2 531{
fad09c73 532 return chip->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 533}
534
fad09c73 535static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
54d792f2 536{
fad09c73 537 return chip->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 538}
539
fad09c73 540static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
54d792f2 541{
fad09c73 542 return chip->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 543}
544
fad09c73 545static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
54d792f2 546{
fad09c73 547 return chip->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 548}
549
fad09c73 550static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
7c3d0d67 551{
fad09c73 552 return chip->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 553}
554
fad09c73 555static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
54d792f2 556{
fad09c73 557 return chip->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 558}
559
fad09c73 560static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
f3a8b6b6 561{
fad09c73 562 return chip->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 563}
564
fad09c73 565static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
f74df0be 566{
fad09c73 567 return chip->info->num_databases;
f74df0be
VD		 568}
569
fad09c73 570static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
b426e5f7
VD		 571{
572 /* Does the device have dedicated FID registers for ATU and VTU ops? */
fad09c73
VD		 573 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
574 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
b426e5f7
VD		 575 return true;
576
577 return false;
578}
579
dea87024
AL		 580/* We expect the switch to perform auto negotiation if there is a real
581 * phy. However, in the case of a fixed link phy, we force the port
582 * settings from the fixed link settings.
583 */
f81ec90f
VD		 584static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
585 struct phy_device *phydev)
dea87024 586{
04bed143 587 struct mv88e6xxx_chip *chip = ds->priv;
49052871
AL		 588 u32 reg;
589 int ret;
dea87024
AL		 590
591 if (!phy_is_pseudo_fixed_link(phydev))
592 return;
593
fad09c73 594 mutex_lock(&chip->reg_lock);
dea87024 595
fad09c73 596 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
dea87024
AL		 597 if (ret < 0)
598 goto out;
599
600 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
601 PORT_PCS_CTRL_FORCE_LINK |
602 PORT_PCS_CTRL_DUPLEX_FULL |
603 PORT_PCS_CTRL_FORCE_DUPLEX |
604 PORT_PCS_CTRL_UNFORCED);
605
606 reg |= PORT_PCS_CTRL_FORCE_LINK;
607 if (phydev->link)
57d32310 608 reg |= PORT_PCS_CTRL_LINK_UP;
dea87024 609
fad09c73 610 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
dea87024
AL		 611 goto out;
612
613 switch (phydev->speed) {
614 case SPEED_1000:
615 reg |= PORT_PCS_CTRL_1000;
616 break;
617 case SPEED_100:
618 reg |= PORT_PCS_CTRL_100;
619 break;
620 case SPEED_10:
621 reg |= PORT_PCS_CTRL_10;
622 break;
623 default:
624 pr_info("Unknown speed");
625 goto out;
626 }
627
628 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
629 if (phydev->duplex == DUPLEX_FULL)
630 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
631
fad09c73
VD		 632 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
633 (port >= chip->info->num_ports - 2)) {
e7e72ac0
AL		 634 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
635 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
636 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
637 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
638 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
639 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
640 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
641 }
fad09c73 642 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
dea87024
AL		 643
644out:
fad09c73 645 mutex_unlock(&chip->reg_lock);
dea87024
AL		 646}
647
fad09c73 648static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
91da11f8
LB		 649{
650 int ret;
651 int i;
652
653 for (i = 0; i < 10; i++) {
fad09c73 654 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 655 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 656 return 0;
657 }
658
659 return -ETIMEDOUT;
660}
661
fad09c73 662static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8
LB		 663{
664 int ret;
665
fad09c73 666 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
f3a8b6b6
AL		 667 port = (port + 1) << 5;
668
3675c8d7 669 /* Snapshot the hardware statistics counters for this port. */
fad09c73 670 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 671 GLOBAL_STATS_OP_CAPTURE_PORT |
672 GLOBAL_STATS_OP_HIST_RX_TX | port);
673 if (ret < 0)
674 return ret;
91da11f8 675
3675c8d7 676 /* Wait for the snapshotting to complete. */
fad09c73 677 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 678 if (ret < 0)
679 return ret;
680
681 return 0;
682}
683
fad09c73 684static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
158bc065 685 int stat, u32 *val)
91da11f8
LB		 686{
687 u32 _val;
688 int ret;
689
690 *val = 0;
691
fad09c73 692 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 693 GLOBAL_STATS_OP_READ_CAPTURED |
694 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 695 if (ret < 0)
696 return;
697
fad09c73 698 ret = _mv88e6xxx_stats_wait(chip);
91da11f8
LB		 699 if (ret < 0)
700 return;
701
fad09c73 702 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 703 if (ret < 0)
704 return;
705
706 _val = ret << 16;
707
fad09c73 708 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 709 if (ret < 0)
710 return;
711
712 *val = _val | ret;
713}
714
e413e7e1 715static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 716 { "in_good_octets", 8, 0x00, BANK0, },
717 { "in_bad_octets", 4, 0x02, BANK0, },
718 { "in_unicast", 4, 0x04, BANK0, },
719 { "in_broadcasts", 4, 0x06, BANK0, },
720 { "in_multicasts", 4, 0x07, BANK0, },
721 { "in_pause", 4, 0x16, BANK0, },
722 { "in_undersize", 4, 0x18, BANK0, },
723 { "in_fragments", 4, 0x19, BANK0, },
724 { "in_oversize", 4, 0x1a, BANK0, },
725 { "in_jabber", 4, 0x1b, BANK0, },
726 { "in_rx_error", 4, 0x1c, BANK0, },
727 { "in_fcs_error", 4, 0x1d, BANK0, },
728 { "out_octets", 8, 0x0e, BANK0, },
729 { "out_unicast", 4, 0x10, BANK0, },
730 { "out_broadcasts", 4, 0x13, BANK0, },
731 { "out_multicasts", 4, 0x12, BANK0, },
732 { "out_pause", 4, 0x15, BANK0, },
733 { "excessive", 4, 0x11, BANK0, },
734 { "collisions", 4, 0x1e, BANK0, },
735 { "deferred", 4, 0x05, BANK0, },
736 { "single", 4, 0x14, BANK0, },
737 { "multiple", 4, 0x17, BANK0, },
738 { "out_fcs_error", 4, 0x03, BANK0, },
739 { "late", 4, 0x1f, BANK0, },
740 { "hist_64bytes", 4, 0x08, BANK0, },
741 { "hist_65_127bytes", 4, 0x09, BANK0, },
742 { "hist_128_255bytes", 4, 0x0a, BANK0, },
743 { "hist_256_511bytes", 4, 0x0b, BANK0, },
744 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
745 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
746 { "sw_in_discards", 4, 0x10, PORT, },
747 { "sw_in_filtered", 2, 0x12, PORT, },
748 { "sw_out_filtered", 2, 0x13, PORT, },
749 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
750 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
751 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
752 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
753 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
754 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
755 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
756 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
757 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
758 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
759 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
760 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
761 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
762 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
763 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
764 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
765 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
766 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
767 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
768 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
769 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
770 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
771 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
772 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
773 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
774 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 775};
776
fad09c73 777static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 778 struct mv88e6xxx_hw_stat *stat)
e413e7e1 779{
f5e2ed02
AL		 780 switch (stat->type) {
781 case BANK0:
e413e7e1 782 return true;
f5e2ed02 783 case BANK1:
fad09c73 784 return mv88e6xxx_6320_family(chip);
f5e2ed02 785 case PORT:
fad09c73
VD		 786 return mv88e6xxx_6095_family(chip) ||
787 mv88e6xxx_6185_family(chip) ||
788 mv88e6xxx_6097_family(chip) ||
789 mv88e6xxx_6165_family(chip) ||
790 mv88e6xxx_6351_family(chip) ||
791 mv88e6xxx_6352_family(chip);
91da11f8 792 }
f5e2ed02 793 return false;
91da11f8
LB		 794}
795
fad09c73 796static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 797 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 798 int port)
799{
80c4627b
AL		 800 u32 low;
801 u32 high = 0;
802 int ret;
803 u64 value;
804
f5e2ed02
AL		 805 switch (s->type) {
806 case PORT:
fad09c73 807 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
80c4627b
AL		 808 if (ret < 0)
809 return UINT64_MAX;
810
811 low = ret;
812 if (s->sizeof_stat == 4) {
fad09c73 813 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
f5e2ed02 814 s->reg + 1);
80c4627b
AL		 815 if (ret < 0)
816 return UINT64_MAX;
817 high = ret;
818 }
f5e2ed02
AL		 819 break;
820 case BANK0:
821 case BANK1:
fad09c73 822 _mv88e6xxx_stats_read(chip, s->reg, &low);
80c4627b 823 if (s->sizeof_stat == 8)
fad09c73 824 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
80c4627b
AL		 825 }
826 value = (((u64)high) << 16) | low;
827 return value;
828}
829
f81ec90f
VD		 830static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
831 uint8_t *data)
91da11f8 832{
04bed143 833 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 834 struct mv88e6xxx_hw_stat *stat;
835 int i, j;
91da11f8 836
f5e2ed02
AL		 837 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
838 stat = &mv88e6xxx_hw_stats[i];
fad09c73 839 if (mv88e6xxx_has_stat(chip, stat)) {
f5e2ed02
AL		 840 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
841 ETH_GSTRING_LEN);
842 j++;
843 }
91da11f8 844 }
e413e7e1
AL		 845}
846
f81ec90f 847static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
e413e7e1 848{
04bed143 849 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 850 struct mv88e6xxx_hw_stat *stat;
851 int i, j;
852
853 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
854 stat = &mv88e6xxx_hw_stats[i];
fad09c73 855 if (mv88e6xxx_has_stat(chip, stat))
f5e2ed02
AL		 856 j++;
857 }
858 return j;
e413e7e1
AL		 859}
860
f81ec90f
VD		 861static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
862 uint64_t *data)
e413e7e1 863{
04bed143 864 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02
AL		 865 struct mv88e6xxx_hw_stat *stat;
866 int ret;
867 int i, j;
868
fad09c73 869 mutex_lock(&chip->reg_lock);
f5e2ed02 870
fad09c73 871 ret = _mv88e6xxx_stats_snapshot(chip, port);
f5e2ed02 872 if (ret < 0) {
fad09c73 873 mutex_unlock(&chip->reg_lock);
f5e2ed02
AL		 874 return;
875 }
876 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
877 stat = &mv88e6xxx_hw_stats[i];
fad09c73
VD		 878 if (mv88e6xxx_has_stat(chip, stat)) {
879 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
f5e2ed02
AL		 880 j++;
881 }
882 }
883
fad09c73 884 mutex_unlock(&chip->reg_lock);
e413e7e1
AL		 885}
886
f81ec90f 887static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3
GR		 888{
889 return 32 * sizeof(u16);
890}
891
f81ec90f
VD		 892static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
893 struct ethtool_regs *regs, void *_p)
a1ab91f3 894{
04bed143 895 struct mv88e6xxx_chip *chip = ds->priv;
a1ab91f3
GR		 896 u16 *p = _p;
897 int i;
898
899 regs->version = 0;
900
901 memset(p, 0xff, 32 * sizeof(u16));
902
fad09c73 903 mutex_lock(&chip->reg_lock);
23062513 904
a1ab91f3
GR		 905 for (i = 0; i < 32; i++) {
906 int ret;
907
fad09c73 908 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
a1ab91f3
GR		 909 if (ret >= 0)
910 p[i] = ret;
911 }
23062513 912
fad09c73 913 mutex_unlock(&chip->reg_lock);
a1ab91f3
GR		 914}
915
fad09c73 916static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
facd95b2 917{
2d79af6e
VD		 918 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
919 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 920}
921
f81ec90f
VD		 922static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
923 struct ethtool_eee *e)
11b3b45d 924{
04bed143 925 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 926 u16 reg;
927 int err;
11b3b45d 928
fad09c73 929 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 930 return -EOPNOTSUPP;
931
fad09c73 932 mutex_lock(&chip->reg_lock);
2f40c698 933
9c93829c
VD		 934 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
935 if (err)
2f40c698 936 goto out;
11b3b45d
GR		 937
938 e->eee_enabled = !!(reg & 0x0200);
939 e->tx_lpi_enabled = !!(reg & 0x0100);
940
9c93829c
VD		 941 err = mv88e6xxx_read(chip, REG_PORT(port), PORT_STATUS, &reg);
942 if (err)
2f40c698 943 goto out;
11b3b45d 944
cca8b133 945 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 946out:
fad09c73 947 mutex_unlock(&chip->reg_lock);
9c93829c
VD		 948
949 return err;
11b3b45d
GR		 950}
951
f81ec90f
VD		 952static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
953 struct phy_device *phydev, struct ethtool_eee *e)
11b3b45d 954{
04bed143 955 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c
VD		 956 u16 reg;
957 int err;
11b3b45d 958
fad09c73 959 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
aadbdb8a
VD		 960 return -EOPNOTSUPP;
961
fad09c73 962 mutex_lock(&chip->reg_lock);
11b3b45d 963
9c93829c
VD		 964 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
965 if (err)
2f40c698
AL		 966 goto out;
967
9c93829c 968 reg &= ~0x0300;
2f40c698
AL		 969 if (e->eee_enabled)
970 reg |= 0x0200;
971 if (e->tx_lpi_enabled)
972 reg |= 0x0100;
973
9c93829c 974 err = mv88e6xxx_phy_write(chip, port, 16, reg);
2f40c698 975out:
fad09c73 976 mutex_unlock(&chip->reg_lock);
2f40c698 977
9c93829c 978 return err;
11b3b45d
GR		 979}
980
fad09c73 981static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
facd95b2
GR		 982{
983 int ret;
984
fad09c73
VD		 985 if (mv88e6xxx_has_fid_reg(chip)) {
986 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
987 fid);
b426e5f7
VD		 988 if (ret < 0)
989 return ret;
fad09c73 990 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f 991 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
fad09c73 992 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
11ea809f
VD		 993 if (ret < 0)
994 return ret;
995
fad09c73 996 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
11ea809f
VD		 997 (ret & 0xfff) |
998 ((fid << 8) & 0xf000));
999 if (ret < 0)
1000 return ret;
1001
1002 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1003 cmd |= fid & 0xf;
b426e5f7
VD		 1004 }
1005
fad09c73 1006 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 1007 if (ret < 0)
1008 return ret;
1009
fad09c73 1010 return _mv88e6xxx_atu_wait(chip);
facd95b2
GR		 1011}
1012
fad09c73 1013static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
37705b73
VD		 1014 struct mv88e6xxx_atu_entry *entry)
1015{
1016 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1017
1018 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1019 unsigned int mask, shift;
1020
1021 if (entry->trunk) {
1022 data |= GLOBAL_ATU_DATA_TRUNK;
1023 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1024 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1025 } else {
1026 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1027 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1028 }
1029
1030 data |= (entry->portv_trunkid << shift) & mask;
1031 }
1032
fad09c73 1033 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
37705b73
VD		 1034}
1035
fad09c73 1036static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
7fb5e755
VD		 1037 struct mv88e6xxx_atu_entry *entry,
1038 bool static_too)
facd95b2 1039{
7fb5e755
VD		 1040 int op;
1041 int err;
facd95b2 1042
fad09c73 1043 err = _mv88e6xxx_atu_wait(chip);
7fb5e755
VD		 1044 if (err)
1045 return err;
facd95b2 1046
fad09c73 1047 err = _mv88e6xxx_atu_data_write(chip, entry);
7fb5e755
VD		 1048 if (err)
1049 return err;
1050
1051 if (entry->fid) {
7fb5e755
VD		 1052 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1053 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1054 } else {
1055 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1056 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1057 }
1058
fad09c73 1059 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
7fb5e755
VD		 1060}
1061
fad09c73 1062static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
158bc065 1063 u16 fid, bool static_too)
7fb5e755
VD		 1064{
1065 struct mv88e6xxx_atu_entry entry = {
1066 .fid = fid,
1067 .state = 0, /* EntryState bits must be 0 */
1068 };
70cc99d1 1069
fad09c73 1070 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
7fb5e755
VD		 1071}
1072
fad09c73 1073static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1074 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1075{
1076 struct mv88e6xxx_atu_entry entry = {
1077 .trunk = false,
1078 .fid = fid,
1079 };
1080
1081 /* EntryState bits must be 0xF */
1082 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1083
1084 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1085 entry.portv_trunkid = (to_port & 0x0f) << 4;
1086 entry.portv_trunkid |= from_port & 0x0f;
1087
fad09c73 1088 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
9f4d55d2
VD		 1089}
1090
fad09c73 1091static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
158bc065 1092 int port, bool static_too)
9f4d55d2
VD		 1093{
1094 /* Destination port 0xF means remove the entries */
fad09c73 1095 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1096}
1097
2d9deae4
VD		 1098static const char * const mv88e6xxx_port_state_names[] = {
1099 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1100 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1101 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1102 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1103};
1104
fad09c73 1105static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
158bc065 1106 u8 state)
facd95b2 1107{
fad09c73 1108 struct dsa_switch *ds = chip->ds;
c3ffe6d2 1109 int reg, ret = 0;
facd95b2
GR		 1110 u8 oldstate;
1111
fad09c73 1112 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1113 if (reg < 0)
1114 return reg;
facd95b2 1115
cca8b133 1116 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1117
facd95b2
GR		 1118 if (oldstate != state) {
1119 /* Flush forwarding database if we're moving a port
1120 * from Learning or Forwarding state to Disabled or
1121 * Blocking or Listening state.
1122 */
2d9deae4 1123 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
57d32310
VD		 1124 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1125 (state == PORT_CONTROL_STATE_DISABLED ||
1126 state == PORT_CONTROL_STATE_BLOCKING)) {
fad09c73 1127 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
facd95b2 1128 if (ret)
2d9deae4 1129 return ret;
facd95b2 1130 }
2d9deae4 1131
cca8b133 1132 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
fad09c73 1133 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
cca8b133 1134 reg);
2d9deae4
VD		 1135 if (ret)
1136 return ret;
1137
c8b09808 1138 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
2d9deae4
VD		 1139 mv88e6xxx_port_state_names[state],
1140 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1141 }
1142
facd95b2
GR		 1143 return ret;
1144}
1145
fad09c73 1146static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
facd95b2 1147{
fad09c73
VD		 1148 struct net_device *bridge = chip->ports[port].bridge_dev;
1149 const u16 mask = (1 << chip->info->num_ports) - 1;
1150 struct dsa_switch *ds = chip->ds;
b7666efe 1151 u16 output_ports = 0;
ede8098d 1152 int reg;
b7666efe
VD		 1153 int i;
1154
1155 /* allow CPU port or DSA link(s) to send frames to every port */
1156 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1157 output_ports = mask;
1158 } else {
fad09c73 1159 for (i = 0; i < chip->info->num_ports; ++i) {
b7666efe 1160 /* allow sending frames to every group member */
fad09c73 1161 if (bridge && chip->ports[i].bridge_dev == bridge)
b7666efe
VD		 1162 output_ports |= BIT(i);
1163
1164 /* allow sending frames to CPU port and DSA link(s) */
1165 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1166 output_ports |= BIT(i);
1167 }
1168 }
1169
1170 /* prevent frames from going back out of the port they came in on */
1171 output_ports &= ~BIT(port);
facd95b2 1172
fad09c73 1173 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
ede8098d
VD		 1174 if (reg < 0)
1175 return reg;
facd95b2 1176
ede8098d
VD		 1177 reg &= ~mask;
1178 reg |= output_ports & mask;
facd95b2 1179
fad09c73 1180 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1181}
1182
f81ec90f
VD		 1183static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1184 u8 state)
facd95b2 1185{
04bed143 1186 struct mv88e6xxx_chip *chip = ds->priv;
facd95b2 1187 int stp_state;
553eb544 1188 int err;
facd95b2
GR		 1189
1190 switch (state) {
1191 case BR_STATE_DISABLED:
cca8b133 1192 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1193 break;
1194 case BR_STATE_BLOCKING:
1195 case BR_STATE_LISTENING:
cca8b133 1196 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1197 break;
1198 case BR_STATE_LEARNING:
cca8b133 1199 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1200 break;
1201 case BR_STATE_FORWARDING:
1202 default:
cca8b133 1203 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1204 break;
1205 }
1206
fad09c73
VD		 1207 mutex_lock(&chip->reg_lock);
1208 err = _mv88e6xxx_port_state(chip, port, stp_state);
1209 mutex_unlock(&chip->reg_lock);
553eb544
VD		 1210
1211 if (err)
c8b09808
AL		 1212 netdev_err(ds->ports[port].netdev,
1213 "failed to update state to %s\n",
553eb544 1214 mv88e6xxx_port_state_names[stp_state]);
facd95b2
GR		 1215}
1216
fad09c73 1217static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
158bc065 1218 u16 *new, u16 *old)
76e398a6 1219{
fad09c73 1220 struct dsa_switch *ds = chip->ds;
5da96031 1221 u16 pvid;
76e398a6
VD		 1222 int ret;
1223
fad09c73 1224 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
76e398a6
VD		 1225 if (ret < 0)
1226 return ret;
1227
5da96031
VD		 1228 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1229
1230 if (new) {
1231 ret &= ~PORT_DEFAULT_VLAN_MASK;
1232 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1233
fad09c73 1234 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
5da96031
VD		 1235 PORT_DEFAULT_VLAN, ret);
1236 if (ret < 0)
1237 return ret;
1238
c8b09808
AL		 1239 netdev_dbg(ds->ports[port].netdev,
1240 "DefaultVID %d (was %d)\n", *new, pvid);
5da96031
VD		 1241 }
1242
1243 if (old)
1244 *old = pvid;
76e398a6
VD		 1245
1246 return 0;
1247}
1248
fad09c73 1249static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
158bc065 1250 int port, u16 *pvid)
5da96031 1251{
fad09c73 1252 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
5da96031
VD		 1253}
1254
fad09c73 1255static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
158bc065 1256 int port, u16 pvid)
0d3b33e6 1257{
fad09c73 1258 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
0d3b33e6
VD		 1259}
1260
fad09c73 1261static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
6b17e864 1262{
2d79af6e
VD		 1263 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1264 GLOBAL_VTU_OP_BUSY);
6b17e864
VD		 1265}
1266
fad09c73 1267static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
6b17e864
VD		 1268{
1269 int ret;
1270
fad09c73 1271 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
6b17e864
VD		 1272 if (ret < 0)
1273 return ret;
1274
fad09c73 1275 return _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1276}
1277
fad09c73 1278static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
6b17e864
VD		 1279{
1280 int ret;
1281
fad09c73 1282 ret = _mv88e6xxx_vtu_wait(chip);
6b17e864
VD		 1283 if (ret < 0)
1284 return ret;
1285
fad09c73 1286 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1287}
1288
fad09c73 1289static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1290 struct mv88e6xxx_vtu_stu_entry *entry,
1291 unsigned int nibble_offset)
1292{
b8fee957
VD		 1293 u16 regs[3];
1294 int i;
1295 int ret;
1296
1297 for (i = 0; i < 3; ++i) {
fad09c73 1298 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1299 GLOBAL_VTU_DATA_0_3 + i);
1300 if (ret < 0)
1301 return ret;
1302
1303 regs[i] = ret;
1304 }
1305
fad09c73 1306 for (i = 0; i < chip->info->num_ports; ++i) {
b8fee957
VD		 1307 unsigned int shift = (i % 4) * 4 + nibble_offset;
1308 u16 reg = regs[i / 4];
1309
1310 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1311 }
1312
1313 return 0;
1314}
1315
fad09c73 1316static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1317 struct mv88e6xxx_vtu_stu_entry *entry)
1318{
fad09c73 1319 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
15d7d7d4
VD		 1320}
1321
fad09c73 1322static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1323 struct mv88e6xxx_vtu_stu_entry *entry)
1324{
fad09c73 1325 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
15d7d7d4
VD		 1326}
1327
fad09c73 1328static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1329 struct mv88e6xxx_vtu_stu_entry *entry,
1330 unsigned int nibble_offset)
1331{
7dad08d7
VD		 1332 u16 regs[3] = { 0 };
1333 int i;
1334 int ret;
1335
fad09c73 1336 for (i = 0; i < chip->info->num_ports; ++i) {
7dad08d7
VD		 1337 unsigned int shift = (i % 4) * 4 + nibble_offset;
1338 u8 data = entry->data[i];
1339
1340 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1341 }
1342
1343 for (i = 0; i < 3; ++i) {
fad09c73 1344 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
7dad08d7
VD		 1345 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1346 if (ret < 0)
1347 return ret;
1348 }
1349
1350 return 0;
1351}
1352
fad09c73 1353static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1354 struct mv88e6xxx_vtu_stu_entry *entry)
1355{
fad09c73 1356 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
15d7d7d4
VD		 1357}
1358
fad09c73 1359static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
15d7d7d4
VD		 1360 struct mv88e6xxx_vtu_stu_entry *entry)
1361{
fad09c73 1362 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
15d7d7d4
VD		 1363}
1364
fad09c73 1365static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
36d04ba1 1366{
fad09c73 1367 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
36d04ba1
VD		 1368 vid & GLOBAL_VTU_VID_MASK);
1369}
1370
fad09c73 1371static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
b8fee957
VD		 1372 struct mv88e6xxx_vtu_stu_entry *entry)
1373{
1374 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1375 int ret;
1376
fad09c73 1377 ret = _mv88e6xxx_vtu_wait(chip);
b8fee957
VD		 1378 if (ret < 0)
1379 return ret;
1380
fad09c73 1381 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
b8fee957
VD		 1382 if (ret < 0)
1383 return ret;
1384
fad09c73 1385 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
b8fee957
VD		 1386 if (ret < 0)
1387 return ret;
1388
1389 next.vid = ret & GLOBAL_VTU_VID_MASK;
1390 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1391
1392 if (next.valid) {
fad09c73 1393 ret = mv88e6xxx_vtu_data_read(chip, &next);
b8fee957
VD		 1394 if (ret < 0)
1395 return ret;
1396
fad09c73
VD		 1397 if (mv88e6xxx_has_fid_reg(chip)) {
1398 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1399 GLOBAL_VTU_FID);
1400 if (ret < 0)
1401 return ret;
1402
1403 next.fid = ret & GLOBAL_VTU_FID_MASK;
fad09c73 1404 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1405 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1406 * VTU DBNum[3:0] are located in VTU Operation 3:0
1407 */
fad09c73 1408 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
11ea809f
VD		 1409 GLOBAL_VTU_OP);
1410 if (ret < 0)
1411 return ret;
1412
1413 next.fid = (ret & 0xf00) >> 4;
1414 next.fid |= ret & 0xf;
2e7bd5ef 1415 }
b8fee957 1416
fad09c73
VD		 1417 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1418 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
b8fee957
VD		 1419 GLOBAL_VTU_SID);
1420 if (ret < 0)
1421 return ret;
1422
1423 next.sid = ret & GLOBAL_VTU_SID_MASK;
1424 }
1425 }
1426
1427 *entry = next;
1428 return 0;
1429}
1430
f81ec90f
VD		 1431static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1432 struct switchdev_obj_port_vlan *vlan,
1433 int (*cb)(struct switchdev_obj *obj))
ceff5eff 1434{
04bed143 1435 struct mv88e6xxx_chip *chip = ds->priv;
ceff5eff
VD		 1436 struct mv88e6xxx_vtu_stu_entry next;
1437 u16 pvid;
1438 int err;
1439
fad09c73 1440 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1441 return -EOPNOTSUPP;
1442
fad09c73 1443 mutex_lock(&chip->reg_lock);
ceff5eff 1444
fad09c73 1445 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
ceff5eff
VD		 1446 if (err)
1447 goto unlock;
1448
fad09c73 1449 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1450 if (err)
1451 goto unlock;
1452
1453 do {
fad09c73 1454 err = _mv88e6xxx_vtu_getnext(chip, &next);
ceff5eff
VD		 1455 if (err)
1456 break;
1457
1458 if (!next.valid)
1459 break;
1460
1461 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1462 continue;
1463
1464 /* reinit and dump this VLAN obj */
57d32310
VD		 1465 vlan->vid_begin = next.vid;
1466 vlan->vid_end = next.vid;
ceff5eff
VD		 1467 vlan->flags = 0;
1468
1469 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1470 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1471
1472 if (next.vid == pvid)
1473 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1474
1475 err = cb(&vlan->obj);
1476 if (err)
1477 break;
1478 } while (next.vid < GLOBAL_VTU_VID_MASK);
1479
1480unlock:
fad09c73 1481 mutex_unlock(&chip->reg_lock);
ceff5eff
VD		 1482
1483 return err;
1484}
1485
fad09c73 1486static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
7dad08d7
VD		 1487 struct mv88e6xxx_vtu_stu_entry *entry)
1488{
11ea809f 1489 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1490 u16 reg = 0;
1491 int ret;
1492
fad09c73 1493 ret = _mv88e6xxx_vtu_wait(chip);
7dad08d7
VD		 1494 if (ret < 0)
1495 return ret;
1496
1497 if (!entry->valid)
1498 goto loadpurge;
1499
1500 /* Write port member tags */
fad09c73 1501 ret = mv88e6xxx_vtu_data_write(chip, entry);
7dad08d7
VD		 1502 if (ret < 0)
1503 return ret;
1504
fad09c73 1505 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
7dad08d7 1506 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73
VD		 1507 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1508 reg);
7dad08d7
VD		 1509 if (ret < 0)
1510 return ret;
b426e5f7 1511 }
7dad08d7 1512
fad09c73 1513 if (mv88e6xxx_has_fid_reg(chip)) {
7dad08d7 1514 reg = entry->fid & GLOBAL_VTU_FID_MASK;
fad09c73
VD		 1515 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1516 reg);
7dad08d7
VD		 1517 if (ret < 0)
1518 return ret;
fad09c73 1519 } else if (mv88e6xxx_num_databases(chip) == 256) {
11ea809f
VD		 1520 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1521 * VTU DBNum[3:0] are located in VTU Operation 3:0
1522 */
1523 op |= (entry->fid & 0xf0) << 8;
1524 op |= entry->fid & 0xf;
7dad08d7
VD		 1525 }
1526
1527 reg = GLOBAL_VTU_VID_VALID;
1528loadpurge:
1529 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
fad09c73 1530 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
7dad08d7
VD		 1531 if (ret < 0)
1532 return ret;
1533
fad09c73 1534 return _mv88e6xxx_vtu_cmd(chip, op);
7dad08d7
VD		 1535}
1536
fad09c73 1537static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
0d3b33e6
VD		 1538 struct mv88e6xxx_vtu_stu_entry *entry)
1539{
1540 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1541 int ret;
1542
fad09c73 1543 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1544 if (ret < 0)
1545 return ret;
1546
fad09c73 1547 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
0d3b33e6
VD		 1548 sid & GLOBAL_VTU_SID_MASK);
1549 if (ret < 0)
1550 return ret;
1551
fad09c73 1552 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
0d3b33e6
VD		 1553 if (ret < 0)
1554 return ret;
1555
fad09c73 1556 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
0d3b33e6
VD		 1557 if (ret < 0)
1558 return ret;
1559
1560 next.sid = ret & GLOBAL_VTU_SID_MASK;
1561
fad09c73 1562 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
0d3b33e6
VD		 1563 if (ret < 0)
1564 return ret;
1565
1566 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1567
1568 if (next.valid) {
fad09c73 1569 ret = mv88e6xxx_stu_data_read(chip, &next);
0d3b33e6
VD		 1570 if (ret < 0)
1571 return ret;
1572 }
1573
1574 *entry = next;
1575 return 0;
1576}
1577
fad09c73 1578static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
0d3b33e6
VD		 1579 struct mv88e6xxx_vtu_stu_entry *entry)
1580{
1581 u16 reg = 0;
1582 int ret;
1583
fad09c73 1584 ret = _mv88e6xxx_vtu_wait(chip);
0d3b33e6
VD		 1585 if (ret < 0)
1586 return ret;
1587
1588 if (!entry->valid)
1589 goto loadpurge;
1590
1591 /* Write port states */
fad09c73 1592 ret = mv88e6xxx_stu_data_write(chip, entry);
0d3b33e6
VD		 1593 if (ret < 0)
1594 return ret;
1595
1596 reg = GLOBAL_VTU_VID_VALID;
1597loadpurge:
fad09c73 1598 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
0d3b33e6
VD		 1599 if (ret < 0)
1600 return ret;
1601
1602 reg = entry->sid & GLOBAL_VTU_SID_MASK;
fad09c73 1603 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
0d3b33e6
VD		 1604 if (ret < 0)
1605 return ret;
1606
fad09c73 1607 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1608}
1609
fad09c73 1610static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
158bc065 1611 u16 *new, u16 *old)
2db9ce1f 1612{
fad09c73 1613 struct dsa_switch *ds = chip->ds;
f74df0be 1614 u16 upper_mask;
2db9ce1f
VD		 1615 u16 fid;
1616 int ret;
1617
fad09c73 1618 if (mv88e6xxx_num_databases(chip) == 4096)
f74df0be 1619 upper_mask = 0xff;
fad09c73 1620 else if (mv88e6xxx_num_databases(chip) == 256)
11ea809f 1621 upper_mask = 0xf;
f74df0be
VD		 1622 else
1623 return -EOPNOTSUPP;
1624
2db9ce1f 1625 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
fad09c73 1626 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
2db9ce1f
VD		 1627 if (ret < 0)
1628 return ret;
1629
1630 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1631
1632 if (new) {
1633 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1634 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1635
fad09c73 1636 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
2db9ce1f
VD		 1637 ret);
1638 if (ret < 0)
1639 return ret;
1640 }
1641
1642 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
fad09c73 1643 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
2db9ce1f
VD		 1644 if (ret < 0)
1645 return ret;
1646
f74df0be 1647 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1648
1649 if (new) {
f74df0be
VD		 1650 ret &= ~upper_mask;
1651 ret |= (*new >> 4) & upper_mask;
2db9ce1f 1652
fad09c73 1653 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2db9ce1f
VD		 1654 ret);
1655 if (ret < 0)
1656 return ret;
1657
c8b09808
AL		 1658 netdev_dbg(ds->ports[port].netdev,
1659 "FID %d (was %d)\n", *new, fid);
2db9ce1f
VD		 1660 }
1661
1662 if (old)
1663 *old = fid;
1664
1665 return 0;
1666}
1667
fad09c73 1668static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
158bc065 1669 int port, u16 *fid)
2db9ce1f 1670{
fad09c73 1671 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
2db9ce1f
VD		 1672}
1673
fad09c73 1674static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
158bc065 1675 int port, u16 fid)
2db9ce1f 1676{
fad09c73 1677 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
2db9ce1f
VD		 1678}
1679
fad09c73 1680static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
3285f9e8
VD		 1681{
1682 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1683 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1684 int i, err;
3285f9e8
VD		 1685
1686 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1687
2db9ce1f 1688 /* Set every FID bit used by the (un)bridged ports */
fad09c73
VD		 1689 for (i = 0; i < chip->info->num_ports; ++i) {
1690 err = _mv88e6xxx_port_fid_get(chip, i, fid);
2db9ce1f
VD		 1691 if (err)
1692 return err;
1693
1694 set_bit(*fid, fid_bitmap);
1695 }
1696
3285f9e8 1697 /* Set every FID bit used by the VLAN entries */
fad09c73 1698 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1699 if (err)
1700 return err;
1701
1702 do {
fad09c73 1703 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
3285f9e8
VD		 1704 if (err)
1705 return err;
1706
1707 if (!vlan.valid)
1708 break;
1709
1710 set_bit(vlan.fid, fid_bitmap);
1711 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1712
1713 /* The reset value 0x000 is used to indicate that multiple address
1714 * databases are not needed. Return the next positive available.
1715 */
1716 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1717 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1718 return -ENOSPC;
1719
1720 /* Clear the database */
fad09c73 1721 return _mv88e6xxx_atu_flush(chip, *fid, true);
3285f9e8
VD		 1722}
1723
fad09c73 1724static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09 1725 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1726{
fad09c73 1727 struct dsa_switch *ds = chip->ds;
0d3b33e6
VD		 1728 struct mv88e6xxx_vtu_stu_entry vlan = {
1729 .valid = true,
1730 .vid = vid,
1731 };
3285f9e8
VD		 1732 int i, err;
1733
fad09c73 1734 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
3285f9e8
VD		 1735 if (err)
1736 return err;
0d3b33e6 1737
3d131f07 1738 /* exclude all ports except the CPU and DSA ports */
fad09c73 1739 for (i = 0; i < chip->info->num_ports; ++i)
3d131f07
VD		 1740 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1741 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1742 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1743
fad09c73
VD		 1744 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1745 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
0d3b33e6 1746 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1747
1748 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1749 * implemented, only one STU entry is needed to cover all VTU
1750 * entries. Thus, validate the SID 0.
1751 */
1752 vlan.sid = 0;
fad09c73 1753 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1754 if (err)
1755 return err;
1756
1757 if (vstp.sid != vlan.sid || !vstp.valid) {
1758 memset(&vstp, 0, sizeof(vstp));
1759 vstp.valid = true;
1760 vstp.sid = vlan.sid;
1761
fad09c73 1762 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
0d3b33e6
VD		 1763 if (err)
1764 return err;
1765 }
0d3b33e6
VD		 1766 }
1767
1768 *entry = vlan;
1769 return 0;
1770}
1771
fad09c73 1772static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
2fb5ef09
VD		 1773 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1774{
1775 int err;
1776
1777 if (!vid)
1778 return -EINVAL;
1779
fad09c73 1780 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2fb5ef09
VD		 1781 if (err)
1782 return err;
1783
fad09c73 1784 err = _mv88e6xxx_vtu_getnext(chip, entry);
2fb5ef09
VD		 1785 if (err)
1786 return err;
1787
1788 if (entry->vid != vid || !entry->valid) {
1789 if (!creat)
1790 return -EOPNOTSUPP;
1791 /* -ENOENT would've been more appropriate, but switchdev expects
1792 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1793 */
1794
fad09c73 1795 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2fb5ef09
VD		 1796 }
1797
1798 return err;
1799}
1800
da9c359e
VD		 1801static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1802 u16 vid_begin, u16 vid_end)
1803{
04bed143 1804 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1805 struct mv88e6xxx_vtu_stu_entry vlan;
1806 int i, err;
1807
1808 if (!vid_begin)
1809 return -EOPNOTSUPP;
1810
fad09c73 1811 mutex_lock(&chip->reg_lock);
da9c359e 1812
fad09c73 1813 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
da9c359e
VD		 1814 if (err)
1815 goto unlock;
1816
1817 do {
fad09c73 1818 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
da9c359e
VD		 1819 if (err)
1820 goto unlock;
1821
1822 if (!vlan.valid)
1823 break;
1824
1825 if (vlan.vid > vid_end)
1826 break;
1827
fad09c73 1828 for (i = 0; i < chip->info->num_ports; ++i) {
da9c359e
VD		 1829 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1830 continue;
1831
1832 if (vlan.data[i] ==
1833 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1834 continue;
1835
fad09c73
VD		 1836 if (chip->ports[i].bridge_dev ==
1837 chip->ports[port].bridge_dev)
da9c359e
VD		 1838 break; /* same bridge, check next VLAN */
1839
c8b09808 1840 netdev_warn(ds->ports[port].netdev,
da9c359e
VD		 1841 "hardware VLAN %d already used by %s\n",
1842 vlan.vid,
fad09c73 1843 netdev_name(chip->ports[i].bridge_dev));
da9c359e
VD		 1844 err = -EOPNOTSUPP;
1845 goto unlock;
1846 }
1847 } while (vlan.vid < vid_end);
1848
1849unlock:
fad09c73 1850 mutex_unlock(&chip->reg_lock);
da9c359e
VD		 1851
1852 return err;
1853}
1854
214cdb99
VD		 1855static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1856 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1857 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1858 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1859 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1860};
1861
f81ec90f
VD		 1862static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1863 bool vlan_filtering)
214cdb99 1864{
04bed143 1865 struct mv88e6xxx_chip *chip = ds->priv;
214cdb99
VD		 1866 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1867 PORT_CONTROL_2_8021Q_DISABLED;
1868 int ret;
1869
fad09c73 1870 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1871 return -EOPNOTSUPP;
1872
fad09c73 1873 mutex_lock(&chip->reg_lock);
214cdb99 1874
fad09c73 1875 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
214cdb99
VD		 1876 if (ret < 0)
1877 goto unlock;
1878
1879 old = ret & PORT_CONTROL_2_8021Q_MASK;
1880
5220ef1e
VD		 1881 if (new != old) {
1882 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1883 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1884
fad09c73 1885 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
5220ef1e
VD		 1886 ret);
1887 if (ret < 0)
1888 goto unlock;
1889
c8b09808 1890 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
5220ef1e
VD		 1891 mv88e6xxx_port_8021q_mode_names[new],
1892 mv88e6xxx_port_8021q_mode_names[old]);
1893 }
214cdb99 1894
5220ef1e 1895 ret = 0;
214cdb99 1896unlock:
fad09c73 1897 mutex_unlock(&chip->reg_lock);
214cdb99
VD		 1898
1899 return ret;
1900}
1901
57d32310
VD		 1902static int
1903mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1904 const struct switchdev_obj_port_vlan *vlan,
1905 struct switchdev_trans *trans)
76e398a6 1906{
04bed143 1907 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1908 int err;
1909
fad09c73 1910 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1911 return -EOPNOTSUPP;
1912
da9c359e
VD		 1913 /* If the requested port doesn't belong to the same bridge as the VLAN
1914 * members, do not support it (yet) and fallback to software VLAN.
1915 */
1916 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1917 vlan->vid_end);
1918 if (err)
1919 return err;
1920
76e398a6
VD		 1921 /* We don't need any dynamic resource from the kernel (yet),
1922 * so skip the prepare phase.
1923 */
1924 return 0;
1925}
1926
fad09c73 1927static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
158bc065 1928 u16 vid, bool untagged)
0d3b33e6 1929{
0d3b33e6
VD		 1930 struct mv88e6xxx_vtu_stu_entry vlan;
1931 int err;
1932
fad09c73 1933 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
0d3b33e6 1934 if (err)
76e398a6 1935 return err;
0d3b33e6 1936
0d3b33e6
VD		 1937 vlan.data[port] = untagged ?
1938 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1939 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1940
fad09c73 1941 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 1942}
1943
f81ec90f
VD		 1944static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1945 const struct switchdev_obj_port_vlan *vlan,
1946 struct switchdev_trans *trans)
76e398a6 1947{
04bed143 1948 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 1949 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1950 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1951 u16 vid;
76e398a6 1952
fad09c73 1953 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 1954 return;
1955
fad09c73 1956 mutex_lock(&chip->reg_lock);
76e398a6 1957
4d5770b3 1958 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
fad09c73 1959 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
c8b09808
AL		 1960 netdev_err(ds->ports[port].netdev,
1961 "failed to add VLAN %d%c\n",
4d5770b3 1962 vid, untagged ? 'u' : 't');
76e398a6 1963
fad09c73 1964 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
c8b09808 1965 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
4d5770b3 1966 vlan->vid_end);
0d3b33e6 1967
fad09c73 1968 mutex_unlock(&chip->reg_lock);
0d3b33e6
VD		 1969}
1970
fad09c73 1971static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
158bc065 1972 int port, u16 vid)
7dad08d7 1973{
fad09c73 1974 struct dsa_switch *ds = chip->ds;
7dad08d7 1975 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1976 int i, err;
1977
fad09c73 1978 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
7dad08d7 1979 if (err)
76e398a6 1980 return err;
7dad08d7 1981
2fb5ef09
VD		 1982 /* Tell switchdev if this VLAN is handled in software */
1983 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1984 return -EOPNOTSUPP;
7dad08d7
VD		 1985
1986 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1987
1988 /* keep the VLAN unless all ports are excluded */
f02bdffc 1989 vlan.valid = false;
fad09c73 1990 for (i = 0; i < chip->info->num_ports; ++i) {
3d131f07 1991 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1992 continue;
1993
1994 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1995 vlan.valid = true;
7dad08d7
VD		 1996 break;
1997 }
1998 }
1999
fad09c73 2000 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 2001 if (err)
2002 return err;
2003
fad09c73 2004 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 2005}
2006
f81ec90f
VD		 2007static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2008 const struct switchdev_obj_port_vlan *vlan)
76e398a6 2009{
04bed143 2010 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 2011 u16 pvid, vid;
2012 int err = 0;
2013
fad09c73 2014 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
54d77b5b
VD		 2015 return -EOPNOTSUPP;
2016
fad09c73 2017 mutex_lock(&chip->reg_lock);
76e398a6 2018
fad09c73 2019 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
7dad08d7
VD		 2020 if (err)
2021 goto unlock;
2022
76e398a6 2023 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
fad09c73 2024 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
76e398a6
VD		 2025 if (err)
2026 goto unlock;
2027
2028 if (vid == pvid) {
fad09c73 2029 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
76e398a6
VD		 2030 if (err)
2031 goto unlock;
2032 }
2033 }
2034
7dad08d7 2035unlock:
fad09c73 2036 mutex_unlock(&chip->reg_lock);
7dad08d7
VD		 2037
2038 return err;
2039}
2040
fad09c73 2041static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
c5723ac5 2042 const unsigned char *addr)
defb05b9
GR		 2043{
2044 int i, ret;
2045
2046 for (i = 0; i < 3; i++) {
cca8b133 2047 ret = _mv88e6xxx_reg_write(
fad09c73 2048 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
cca8b133 2049 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2050 if (ret < 0)
2051 return ret;
2052 }
2053
2054 return 0;
2055}
2056
fad09c73 2057static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
158bc065 2058 unsigned char *addr)
defb05b9
GR		 2059{
2060 int i, ret;
2061
2062 for (i = 0; i < 3; i++) {
fad09c73 2063 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
cca8b133 2064 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2065 if (ret < 0)
2066 return ret;
2067 addr[i * 2] = ret >> 8;
2068 addr[i * 2 + 1] = ret & 0xff;
2069 }
2070
2071 return 0;
2072}
2073
fad09c73 2074static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
fd231c82 2075 struct mv88e6xxx_atu_entry *entry)
defb05b9 2076{
6630e236
VD		 2077 int ret;
2078
fad09c73 2079 ret = _mv88e6xxx_atu_wait(chip);
defb05b9
GR		 2080 if (ret < 0)
2081 return ret;
2082
fad09c73 2083 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
defb05b9
GR		 2084 if (ret < 0)
2085 return ret;
2086
fad09c73 2087 ret = _mv88e6xxx_atu_data_write(chip, entry);
fd231c82 2088 if (ret < 0)
87820510
VD		 2089 return ret;
2090
fad09c73 2091 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2092}
87820510 2093
83dabd1f
VD		 2094static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2095 const unsigned char *addr, u16 vid,
2096 u8 state)
fd231c82
VD		 2097{
2098 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2099 struct mv88e6xxx_vtu_stu_entry vlan;
2100 int err;
2101
2db9ce1f
VD		 2102 /* Null VLAN ID corresponds to the port private database */
2103 if (vid == 0)
fad09c73 2104 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2db9ce1f 2105 else
fad09c73 2106 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
3285f9e8
VD		 2107 if (err)
2108 return err;
fd231c82 2109
3285f9e8 2110 entry.fid = vlan.fid;
fd231c82
VD		 2111 entry.state = state;
2112 ether_addr_copy(entry.mac, addr);
2113 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2114 entry.trunk = false;
2115 entry.portv_trunkid = BIT(port);
2116 }
2117
fad09c73 2118 return _mv88e6xxx_atu_load(chip, &entry);
87820510
VD		 2119}
2120
f81ec90f
VD		 2121static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2122 const struct switchdev_obj_port_fdb *fdb,
2123 struct switchdev_trans *trans)
146a3206
VD		 2124{
2125 /* We don't need any dynamic resource from the kernel (yet),
2126 * so skip the prepare phase.
2127 */
2128 return 0;
2129}
2130
f81ec90f
VD		 2131static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2132 const struct switchdev_obj_port_fdb *fdb,
2133 struct switchdev_trans *trans)
87820510 2134{
04bed143 2135 struct mv88e6xxx_chip *chip = ds->priv;
87820510 2136
fad09c73 2137 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2138 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2139 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2140 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
fad09c73 2141 mutex_unlock(&chip->reg_lock);
87820510
VD		 2142}
2143
f81ec90f
VD		 2144static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2145 const struct switchdev_obj_port_fdb *fdb)
87820510 2146{
04bed143 2147 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2148 int err;
87820510 2149
fad09c73 2150 mutex_lock(&chip->reg_lock);
83dabd1f
VD		 2151 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2152 GLOBAL_ATU_DATA_STATE_UNUSED);
fad09c73 2153 mutex_unlock(&chip->reg_lock);
87820510 2154
83dabd1f 2155 return err;
87820510
VD		 2156}
2157
fad09c73 2158static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
1d194046 2159 struct mv88e6xxx_atu_entry *entry)
6630e236 2160{
1d194046
VD		 2161 struct mv88e6xxx_atu_entry next = { 0 };
2162 int ret;
2163
2164 next.fid = fid;
defb05b9 2165
fad09c73 2166 ret = _mv88e6xxx_atu_wait(chip);
cdf09697
DM		 2167 if (ret < 0)
2168 return ret;
6630e236 2169
fad09c73 2170 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2171 if (ret < 0)
2172 return ret;
6630e236 2173
fad09c73 2174 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
1d194046
VD		 2175 if (ret < 0)
2176 return ret;
6630e236 2177
fad09c73 2178 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2179 if (ret < 0)
2180 return ret;
6630e236 2181
1d194046
VD		 2182 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2183 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2184 unsigned int mask, shift;
2185
2186 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2187 next.trunk = true;
2188 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2189 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2190 } else {
2191 next.trunk = false;
2192 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2193 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2194 }
2195
2196 next.portv_trunkid = (ret & mask) >> shift;
2197 }
cdf09697 2198
1d194046 2199 *entry = next;
cdf09697
DM		 2200 return 0;
2201}
2202
83dabd1f
VD		 2203static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2204 u16 fid, u16 vid, int port,
2205 struct switchdev_obj *obj,
2206 int (*cb)(struct switchdev_obj *obj))
74b6ba0d
VD		 2207{
2208 struct mv88e6xxx_atu_entry addr = {
2209 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2210 };
2211 int err;
2212
fad09c73 2213 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
74b6ba0d
VD		 2214 if (err)
2215 return err;
2216
2217 do {
fad09c73 2218 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
74b6ba0d 2219 if (err)
83dabd1f 2220 return err;
74b6ba0d
VD		 2221
2222 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2223 break;
2224
83dabd1f
VD		 2225 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2226 continue;
2227
2228 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2229 struct switchdev_obj_port_fdb *fdb;
74b6ba0d 2230
83dabd1f
VD		 2231 if (!is_unicast_ether_addr(addr.mac))
2232 continue;
2233
2234 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
74b6ba0d
VD		 2235 fdb->vid = vid;
2236 ether_addr_copy(fdb->addr, addr.mac);
83dabd1f
VD		 2237 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2238 fdb->ndm_state = NUD_NOARP;
2239 else
2240 fdb->ndm_state = NUD_REACHABLE;
7df8fbdd
VD		 2241 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2242 struct switchdev_obj_port_mdb *mdb;
2243
2244 if (!is_multicast_ether_addr(addr.mac))
2245 continue;
2246
2247 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2248 mdb->vid = vid;
2249 ether_addr_copy(mdb->addr, addr.mac);
83dabd1f
VD		 2250 } else {
2251 return -EOPNOTSUPP;
74b6ba0d 2252 }
83dabd1f
VD		 2253
2254 err = cb(obj);
2255 if (err)
2256 return err;
74b6ba0d
VD		 2257 } while (!is_broadcast_ether_addr(addr.mac));
2258
2259 return err;
2260}
2261
83dabd1f
VD		 2262static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2263 struct switchdev_obj *obj,
2264 int (*cb)(struct switchdev_obj *obj))
f33475bd 2265{
f33475bd
VD		 2266 struct mv88e6xxx_vtu_stu_entry vlan = {
2267 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2268 };
2db9ce1f 2269 u16 fid;
f33475bd
VD		 2270 int err;
2271
2db9ce1f 2272 /* Dump port's default Filtering Information Database (VLAN ID 0) */
fad09c73 2273 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2db9ce1f 2274 if (err)
83dabd1f 2275 return err;
2db9ce1f 2276
83dabd1f 2277 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2db9ce1f 2278 if (err)
83dabd1f 2279 return err;
2db9ce1f 2280
74b6ba0d 2281 /* Dump VLANs' Filtering Information Databases */
fad09c73 2282 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
f33475bd 2283 if (err)
83dabd1f 2284 return err;
f33475bd
VD		 2285
2286 do {
fad09c73 2287 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
f33475bd 2288 if (err)
83dabd1f 2289 return err;
f33475bd
VD		 2290
2291 if (!vlan.valid)
2292 break;
2293
83dabd1f
VD		 2294 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2295 obj, cb);
f33475bd 2296 if (err)
83dabd1f 2297 return err;
f33475bd
VD		 2298 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2299
83dabd1f
VD		 2300 return err;
2301}
2302
2303static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2304 struct switchdev_obj_port_fdb *fdb,
2305 int (*cb)(struct switchdev_obj *obj))
2306{
04bed143 2307 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f
VD		 2308 int err;
2309
2310 mutex_lock(&chip->reg_lock);
2311 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
fad09c73 2312 mutex_unlock(&chip->reg_lock);
f33475bd
VD		 2313
2314 return err;
2315}
2316
f81ec90f
VD		 2317static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2318 struct net_device *bridge)
e79a8bcb 2319{
04bed143 2320 struct mv88e6xxx_chip *chip = ds->priv;
1d9619d5 2321 int i, err = 0;
466dfa07 2322
fad09c73 2323 mutex_lock(&chip->reg_lock);
466dfa07 2324
b7666efe 2325 /* Assign the bridge and remap each port's VLANTable */
fad09c73 2326 chip->ports[port].bridge_dev = bridge;
b7666efe 2327
fad09c73
VD		 2328 for (i = 0; i < chip->info->num_ports; ++i) {
2329 if (chip->ports[i].bridge_dev == bridge) {
2330 err = _mv88e6xxx_port_based_vlan_map(chip, i);
b7666efe
VD		 2331 if (err)
2332 break;
2333 }
2334 }
2335
fad09c73 2336 mutex_unlock(&chip->reg_lock);
a6692754 2337
466dfa07 2338 return err;
e79a8bcb
VD		 2339}
2340
f81ec90f 2341static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2342{
04bed143 2343 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 2344 struct net_device *bridge = chip->ports[port].bridge_dev;
16bfa702 2345 int i;
466dfa07 2346
fad09c73 2347 mutex_lock(&chip->reg_lock);
466dfa07 2348
b7666efe 2349 /* Unassign the bridge and remap each port's VLANTable */
fad09c73 2350 chip->ports[port].bridge_dev = NULL;
b7666efe 2351
fad09c73
VD		 2352 for (i = 0; i < chip->info->num_ports; ++i)
2353 if (i == port || chip->ports[i].bridge_dev == bridge)
2354 if (_mv88e6xxx_port_based_vlan_map(chip, i))
c8b09808
AL		 2355 netdev_warn(ds->ports[i].netdev,
2356 "failed to remap\n");
b7666efe 2357
fad09c73 2358 mutex_unlock(&chip->reg_lock);
66d9cd0f
VD		 2359}
2360
fad09c73 2361static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
552238b5 2362{
fad09c73 2363 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
552238b5 2364 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
fad09c73 2365 struct gpio_desc *gpiod = chip->reset;
552238b5
VD		 2366 unsigned long timeout;
2367 int ret;
2368 int i;
2369
2370 /* Set all ports to the disabled state. */
fad09c73
VD		 2371 for (i = 0; i < chip->info->num_ports; i++) {
2372 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
552238b5
VD		 2373 if (ret < 0)
2374 return ret;
2375
fad09c73 2376 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
552238b5
VD		 2377 ret & 0xfffc);
2378 if (ret)
2379 return ret;
2380 }
2381
2382 /* Wait for transmit queues to drain. */
2383 usleep_range(2000, 4000);
2384
2385 /* If there is a gpio connected to the reset pin, toggle it */
2386 if (gpiod) {
2387 gpiod_set_value_cansleep(gpiod, 1);
2388 usleep_range(10000, 20000);
2389 gpiod_set_value_cansleep(gpiod, 0);
2390 usleep_range(10000, 20000);
2391 }
2392
2393 /* Reset the switch. Keep the PPU active if requested. The PPU
2394 * needs to be active to support indirect phy register access
2395 * through global registers 0x18 and 0x19.
2396 */
2397 if (ppu_active)
fad09c73 2398 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
552238b5 2399 else
fad09c73 2400 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
552238b5
VD		 2401 if (ret)
2402 return ret;
2403
2404 /* Wait up to one second for reset to complete. */
2405 timeout = jiffies + 1 * HZ;
2406 while (time_before(jiffies, timeout)) {
fad09c73 2407 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
552238b5
VD		 2408 if (ret < 0)
2409 return ret;
2410
2411 if ((ret & is_reset) == is_reset)
2412 break;
2413 usleep_range(1000, 2000);
2414 }
2415 if (time_after(jiffies, timeout))
2416 ret = -ETIMEDOUT;
2417 else
2418 ret = 0;
2419
2420 return ret;
2421}
2422
09cb7dfd 2423static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
13a7ebb3 2424{
09cb7dfd
VD		 2425 u16 val;
2426 int err;
13a7ebb3 2427
09cb7dfd
VD		 2428 /* Clear Power Down bit */
2429 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2430 if (err)
2431 return err;
13a7ebb3 2432
09cb7dfd
VD		 2433 if (val & BMCR_PDOWN) {
2434 val &= ~BMCR_PDOWN;
2435 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
13a7ebb3
PU		 2436 }
2437
09cb7dfd 2438 return err;
13a7ebb3
PU		 2439}
2440
8f6345b2
VD		 2441static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2442 int reg, u16 *val)
2443{
2444 int addr = chip->info->port_base_addr + port;
2445
2446 if (port >= chip->info->num_ports)
2447 return -EINVAL;
2448
2449 return mv88e6xxx_read(chip, addr, reg, val);
2450}
2451
fad09c73 2452static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2453{
fad09c73 2454 struct dsa_switch *ds = chip->ds;
f02bdffc 2455 int ret;
54d792f2 2456 u16 reg;
d827e88a 2457
fad09c73
VD		 2458 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2459 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2460 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2461 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2462 /* MAC Forcing register: don't force link, speed,
2463 * duplex or flow control state to any particular
2464 * values on physical ports, but force the CPU port
2465 * and all DSA ports to their maximum bandwidth and
2466 * full duplex.
2467 */
fad09c73 2468 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2469 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2470 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2471 reg |= PORT_PCS_CTRL_FORCE_LINK |
2472 PORT_PCS_CTRL_LINK_UP |
2473 PORT_PCS_CTRL_DUPLEX_FULL |
2474 PORT_PCS_CTRL_FORCE_DUPLEX;
fad09c73 2475 if (mv88e6xxx_6065_family(chip))
54d792f2
AL		 2476 reg |= PORT_PCS_CTRL_100;
2477 else
2478 reg |= PORT_PCS_CTRL_1000;
2479 } else {
2480 reg |= PORT_PCS_CTRL_UNFORCED;
2481 }
2482
fad09c73 2483 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2484 PORT_PCS_CTRL, reg);
2485 if (ret)
a1a6a4d1 2486 return ret;
54d792f2
AL		 2487 }
2488
2489 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2490 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2491 * tunneling, determine priority by looking at 802.1p and IP
2492 * priority fields (IP prio has precedence), and set STP state
2493 * to Forwarding.
2494 *
2495 * If this is the CPU link, use DSA or EDSA tagging depending
2496 * on which tagging mode was configured.
2497 *
2498 * If this is a link to another switch, use DSA tagging mode.
2499 *
2500 * If this is the upstream port for this switch, enable
2501 * forwarding of unknown unicasts and multicasts.
2502 */
2503 reg = 0;
fad09c73
VD		 2504 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2505 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2506 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2507 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2508 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2509 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2510 PORT_CONTROL_STATE_FORWARDING;
2511 if (dsa_is_cpu_port(ds, port)) {
2bbb33be 2512 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
5377b802 2513 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
c047a1f9 2514 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2bbb33be
AL		 2515 else
2516 reg |= PORT_CONTROL_DSA_TAG;
f027e0cc
JL		 2517 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2518 PORT_CONTROL_FORWARD_UNKNOWN;
54d792f2 2519 }
6083ce71 2520 if (dsa_is_dsa_port(ds, port)) {
fad09c73
VD		 2521 if (mv88e6xxx_6095_family(chip) ||
2522 mv88e6xxx_6185_family(chip))
6083ce71 2523 reg |= PORT_CONTROL_DSA_TAG;
fad09c73
VD		 2524 if (mv88e6xxx_6352_family(chip) ||
2525 mv88e6xxx_6351_family(chip) ||
2526 mv88e6xxx_6165_family(chip) ||
2527 mv88e6xxx_6097_family(chip) ||
2528 mv88e6xxx_6320_family(chip)) {
54d792f2 2529 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2530 }
2531
54d792f2
AL		 2532 if (port == dsa_upstream_port(ds))
2533 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2534 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2535 }
2536 if (reg) {
fad09c73 2537 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2538 PORT_CONTROL, reg);
2539 if (ret)
a1a6a4d1 2540 return ret;
54d792f2
AL		 2541 }
2542
13a7ebb3
PU		 2543 /* If this port is connected to a SerDes, make sure the SerDes is not
2544 * powered down.
2545 */
09cb7dfd 2546 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
fad09c73 2547 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
13a7ebb3 2548 if (ret < 0)
a1a6a4d1 2549 return ret;
13a7ebb3
PU		 2550 ret &= PORT_STATUS_CMODE_MASK;
2551 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2552 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2553 (ret == PORT_STATUS_CMODE_SGMII)) {
09cb7dfd 2554 ret = mv88e6xxx_serdes_power_on(chip);
13a7ebb3 2555 if (ret < 0)
a1a6a4d1 2556 return ret;
13a7ebb3
PU		 2557 }
2558 }
2559
8efdda4a 2560 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2561 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2562 * untagged frames on this port, do a destination address lookup on all
2563 * received packets as usual, disable ARP mirroring and don't send a
2564 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2565 */
2566 reg = 0;
fad09c73
VD		 2567 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2568 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2569 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2570 mv88e6xxx_6185_family(chip))
54d792f2
AL		 2571 reg = PORT_CONTROL_2_MAP_DA;
2572
fad09c73
VD		 2573 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2574 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
54d792f2
AL		 2575 reg |= PORT_CONTROL_2_JUMBO_10240;
2576
fad09c73 2577 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
54d792f2
AL		 2578 /* Set the upstream port this port should use */
2579 reg |= dsa_upstream_port(ds);
2580 /* enable forwarding of unknown multicast addresses to
2581 * the upstream port
2582 */
2583 if (port == dsa_upstream_port(ds))
2584 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2585 }
2586
46fbe5e5 2587 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2588
54d792f2 2589 if (reg) {
fad09c73 2590 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2591 PORT_CONTROL_2, reg);
2592 if (ret)
a1a6a4d1 2593 return ret;
54d792f2
AL		 2594 }
2595
2596 /* Port Association Vector: when learning source addresses
2597 * of packets, add the address to the address database using
2598 * a port bitmap that has only the bit for this port set and
2599 * the other bits clear.
2600 */
4c7ea3c0 2601 reg = 1 << port;
996ecb82
VD		 2602 /* Disable learning for CPU port */
2603 if (dsa_is_cpu_port(ds, port))
65fa4027 2604 reg = 0;
4c7ea3c0 2605
fad09c73
VD		 2606 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2607 reg);
54d792f2 2608 if (ret)
a1a6a4d1 2609 return ret;
54d792f2
AL		 2610
2611 /* Egress rate control 2: disable egress rate control. */
fad09c73 2612 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
54d792f2
AL		 2613 0x0000);
2614 if (ret)
a1a6a4d1 2615 return ret;
54d792f2 2616
fad09c73
VD		 2617 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2618 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2619 mv88e6xxx_6320_family(chip)) {
54d792f2
AL		 2620 /* Do not limit the period of time that this port can
2621 * be paused for by the remote end or the period of
2622 * time that this port can pause the remote end.
2623 */
fad09c73 2624 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2625 PORT_PAUSE_CTRL, 0x0000);
2626 if (ret)
a1a6a4d1 2627 return ret;
54d792f2
AL		 2628
2629 /* Port ATU control: disable limiting the number of
2630 * address database entries that this port is allowed
2631 * to use.
2632 */
fad09c73 2633 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2634 PORT_ATU_CONTROL, 0x0000);
2635 /* Priority Override: disable DA, SA and VTU priority
2636 * override.
2637 */
fad09c73 2638 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2639 PORT_PRI_OVERRIDE, 0x0000);
2640 if (ret)
a1a6a4d1 2641 return ret;
54d792f2
AL		 2642
2643 /* Port Ethertype: use the Ethertype DSA Ethertype
2644 * value.
2645 */
2bbb33be
AL		 2646 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2647 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2648 PORT_ETH_TYPE, ETH_P_EDSA);
2649 if (ret)
2650 return ret;
2651 }
2652
54d792f2
AL		 2653 /* Tag Remap: use an identity 802.1p prio -> switch
2654 * prio mapping.
2655 */
fad09c73 2656 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2657 PORT_TAG_REGMAP_0123, 0x3210);
2658 if (ret)
a1a6a4d1 2659 return ret;
54d792f2
AL		 2660
2661 /* Tag Remap 2: use an identity 802.1p prio -> switch
2662 * prio mapping.
2663 */
fad09c73 2664 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2665 PORT_TAG_REGMAP_4567, 0x7654);
2666 if (ret)
a1a6a4d1 2667 return ret;
54d792f2
AL		 2668 }
2669
1bc261fa 2670 /* Rate Control: disable ingress rate limiting. */
fad09c73
VD		 2671 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2672 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
fad09c73 2673 mv88e6xxx_6320_family(chip)) {
fad09c73 2674 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
54d792f2
AL		 2675 PORT_RATE_CONTROL, 0x0001);
2676 if (ret)
a1a6a4d1 2677 return ret;
1bc261fa
JL		 2678 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2679 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2680 PORT_RATE_CONTROL, 0x0000);
2681 if (ret)
2682 return ret;
54d792f2
AL		 2683 }
2684
366f0a0f
GR		 2685 /* Port Control 1: disable trunking, disable sending
2686 * learning messages to this port.
d827e88a 2687 */
fad09c73
VD		 2688 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2689 0x0000);
d827e88a 2690 if (ret)
a1a6a4d1 2691 return ret;
d827e88a 2692
207afda1 2693 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2694 * database, and allow bidirectional communication between the
2695 * CPU and DSA port(s), and the other ports.
d827e88a 2696 */
fad09c73 2697 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2db9ce1f 2698 if (ret)
a1a6a4d1 2699 return ret;
2db9ce1f 2700
fad09c73 2701 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
d827e88a 2702 if (ret)
a1a6a4d1 2703 return ret;
d827e88a
GR		 2704
2705 /* Default VLAN ID and priority: don't set a default VLAN
2706 * ID, and set the default packet priority to zero.
2707 */
fad09c73 2708 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
47cf1e65 2709 0x0000);
a1a6a4d1
VD		 2710 if (ret)
2711 return ret;
dbde9e66 2712
dbde9e66
AL		 2713 return 0;
2714}
2715
3b4caa1b
VD		 2716static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2717{
2718 int err;
2719
2720 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2721 (addr[0] << 8) | addr[1]);
2722 if (err)
2723 return err;
2724
2725 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2726 (addr[2] << 8) | addr[3]);
2727 if (err)
2728 return err;
2729
2730 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2731 (addr[4] << 8) | addr[5]);
2732}
2733
acddbd21
VD		 2734static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2735 unsigned int msecs)
2736{
2737 const unsigned int coeff = chip->info->age_time_coeff;
2738 const unsigned int min = 0x01 * coeff;
2739 const unsigned int max = 0xff * coeff;
2740 u8 age_time;
2741 u16 val;
2742 int err;
2743
2744 if (msecs < min || msecs > max)
2745 return -ERANGE;
2746
2747 /* Round to nearest multiple of coeff */
2748 age_time = (msecs + coeff / 2) / coeff;
2749
2750 err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2751 if (err)
2752 return err;
2753
2754 /* AgeTime is 11:4 bits */
2755 val &= ~0xff0;
2756 val |= age_time << 4;
2757
2758 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2759}
2760
2cfcd964
VD		 2761static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2762 unsigned int ageing_time)
2763{
04bed143 2764 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 2765 int err;
2766
2767 mutex_lock(&chip->reg_lock);
2768 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2769 mutex_unlock(&chip->reg_lock);
2770
2771 return err;
2772}
2773
9729934c 2774static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
acdaffcc 2775{
fad09c73 2776 struct dsa_switch *ds = chip->ds;
b0745e87 2777 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2778 u16 reg;
552238b5 2779 int err;
54d792f2 2780
119477bd
VD		 2781 /* Enable the PHY Polling Unit if present, don't discard any packets,
2782 * and mask all interrupt sources.
2783 */
2784 reg = 0;
fad09c73
VD		 2785 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2786 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
119477bd
VD		 2787 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2788
fad09c73 2789 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
119477bd
VD		 2790 if (err)
2791 return err;
2792
b0745e87
VD		 2793 /* Configure the upstream port, and configure it as the port to which
2794 * ingress and egress and ARP monitor frames are to be sent.
2795 */
2796 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2797 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2798 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
fad09c73
VD		 2799 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2800 reg);
b0745e87
VD		 2801 if (err)
2802 return err;
2803
50484ff4 2804 /* Disable remote management, and set the switch's DSA device number. */
fad09c73 2805 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
50484ff4
VD		 2806 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2807 (ds->index & 0x1f));
2808 if (err)
2809 return err;
2810
acddbd21
VD		 2811 /* Clear all the VTU and STU entries */
2812 err = _mv88e6xxx_vtu_stu_flush(chip);
2813 if (err < 0)
2814 return err;
2815
54d792f2
AL		 2816 /* Set the default address aging time to 5 minutes, and
2817 * enable address learn messages to be sent to all message
2818 * ports.
2819 */
acddbd21
VD		 2820 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2821 GLOBAL_ATU_CONTROL_LEARN2ALL);
48ace4ef 2822 if (err)
08a01261 2823 return err;
54d792f2 2824
acddbd21
VD		 2825 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2826 if (err)
9729934c
VD		 2827 return err;
2828
2829 /* Clear all ATU entries */
2830 err = _mv88e6xxx_atu_flush(chip, 0, true);
2831 if (err)
2832 return err;
2833
54d792f2 2834 /* Configure the IP ToS mapping registers. */
fad09c73 2835 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2836 if (err)
08a01261 2837 return err;
fad09c73 2838 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2839 if (err)
08a01261 2840 return err;
fad09c73 2841 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2842 if (err)
08a01261 2843 return err;
fad09c73 2844 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2845 if (err)
08a01261 2846 return err;
fad09c73 2847 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2848 if (err)
08a01261 2849 return err;
fad09c73 2850 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2851 if (err)
08a01261 2852 return err;
fad09c73 2853 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2854 if (err)
08a01261 2855 return err;
fad09c73 2856 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2857 if (err)
08a01261 2858 return err;
54d792f2
AL		 2859
2860 /* Configure the IEEE 802.1p priority mapping register. */
fad09c73 2861 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2862 if (err)
08a01261 2863 return err;
54d792f2 2864
9729934c
VD		 2865 /* Clear the statistics counters for all ports */
2866 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2867 GLOBAL_STATS_OP_FLUSH_ALL);
2868 if (err)
2869 return err;
2870
2871 /* Wait for the flush to complete. */
2872 err = _mv88e6xxx_stats_wait(chip);
2873 if (err)
2874 return err;
2875
2876 return 0;
2877}
2878
f81ec90f 2879static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 2880{
04bed143 2881 struct mv88e6xxx_chip *chip = ds->priv;
08a01261 2882 int err;
a1a6a4d1
VD		 2883 int i;
2884
fad09c73
VD		 2885 chip->ds = ds;
2886 ds->slave_mii_bus = chip->mdio_bus;
08a01261 2887
fad09c73 2888 mutex_lock(&chip->reg_lock);
08a01261 2889
fad09c73 2890 err = mv88e6xxx_switch_reset(chip);
08a01261
VD		 2891 if (err)
2892 goto unlock;
2893
9729934c
VD		 2894 /* Setup Switch Port Registers */
2895 for (i = 0; i < chip->info->num_ports; i++) {
2896 err = mv88e6xxx_setup_port(chip, i);
2897 if (err)
2898 goto unlock;
2899 }
2900
2901 /* Setup Switch Global 1 Registers */
2902 err = mv88e6xxx_g1_setup(chip);
a1a6a4d1
VD		 2903 if (err)
2904 goto unlock;
2905
9729934c
VD		 2906 /* Setup Switch Global 2 Registers */
2907 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2908 err = mv88e6xxx_g2_setup(chip);
a1a6a4d1
VD		 2909 if (err)
2910 goto unlock;
2911 }
08a01261 2912
6b17e864 2913unlock:
fad09c73 2914 mutex_unlock(&chip->reg_lock);
db687a56 2915
48ace4ef 2916 return err;
54d792f2
AL		 2917}
2918
3b4caa1b
VD		 2919static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2920{
04bed143 2921 struct mv88e6xxx_chip *chip = ds->priv;
3b4caa1b
VD		 2922 int err;
2923
2924 mutex_lock(&chip->reg_lock);
2925
2926 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
2927 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
2928 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
2929 else
2930 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
2931
2932 mutex_unlock(&chip->reg_lock);
2933
2934 return err;
2935}
2936
e57e5e77 2937static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 2938{
fad09c73 2939 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77
VD		 2940 u16 val;
2941 int err;
fd3a0ee4 2942
e57e5e77 2943 if (phy >= chip->info->num_ports)
158bc065 2944 return 0xffff;
fd3a0ee4 2945
fad09c73 2946 mutex_lock(&chip->reg_lock);
e57e5e77 2947 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
fad09c73 2948 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2949
2950 return err ? err : val;
fd3a0ee4
AL		 2951}
2952
e57e5e77 2953static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 2954{
fad09c73 2955 struct mv88e6xxx_chip *chip = bus->priv;
e57e5e77 2956 int err;
fd3a0ee4 2957
e57e5e77 2958 if (phy >= chip->info->num_ports)
158bc065 2959 return 0xffff;
fd3a0ee4 2960
fad09c73 2961 mutex_lock(&chip->reg_lock);
e57e5e77 2962 err = mv88e6xxx_phy_write(chip, phy, reg, val);
fad09c73 2963 mutex_unlock(&chip->reg_lock);
e57e5e77
VD		 2964
2965 return err;
fd3a0ee4
AL		 2966}
2967
fad09c73 2968static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
b516d453
AL		 2969 struct device_node *np)
2970{
2971 static int index;
2972 struct mii_bus *bus;
2973 int err;
2974
b516d453 2975 if (np)
fad09c73 2976 chip->mdio_np = of_get_child_by_name(np, "mdio");
b516d453 2977
fad09c73 2978 bus = devm_mdiobus_alloc(chip->dev);
b516d453
AL		 2979 if (!bus)
2980 return -ENOMEM;
2981
fad09c73 2982 bus->priv = (void *)chip;
b516d453
AL		 2983 if (np) {
2984 bus->name = np->full_name;
2985 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2986 } else {
2987 bus->name = "mv88e6xxx SMI";
2988 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2989 }
2990
2991 bus->read = mv88e6xxx_mdio_read;
2992 bus->write = mv88e6xxx_mdio_write;
fad09c73 2993 bus->parent = chip->dev;
b516d453 2994
fad09c73
VD		 2995 if (chip->mdio_np)
2996 err = of_mdiobus_register(bus, chip->mdio_np);
b516d453
AL		 2997 else
2998 err = mdiobus_register(bus);
2999 if (err) {
fad09c73 3000 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
b516d453
AL		 3001 goto out;
3002 }
fad09c73 3003 chip->mdio_bus = bus;
b516d453
AL		 3004
3005 return 0;
3006
3007out:
fad09c73
VD		 3008 if (chip->mdio_np)
3009 of_node_put(chip->mdio_np);
b516d453
AL		 3010
3011 return err;
3012}
3013
fad09c73 3014static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
b516d453
AL		 3015
3016{
fad09c73 3017 struct mii_bus *bus = chip->mdio_bus;
b516d453
AL		 3018
3019 mdiobus_unregister(bus);
3020
fad09c73
VD		 3021 if (chip->mdio_np)
3022 of_node_put(chip->mdio_np);
b516d453
AL		 3023}
3024
c22995c5
GR		 3025#ifdef CONFIG_NET_DSA_HWMON
3026
3027static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3028{
04bed143 3029 struct mv88e6xxx_chip *chip = ds->priv;
9c93829c 3030 u16 val;
c22995c5 3031 int ret;
c22995c5
GR		 3032
3033 *temp = 0;
3034
fad09c73 3035 mutex_lock(&chip->reg_lock);
c22995c5 3036
9c93829c 3037 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
c22995c5
GR		 3038 if (ret < 0)
3039 goto error;
3040
3041 /* Enable temperature sensor */
9c93829c 3042 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
c22995c5
GR		 3043 if (ret < 0)
3044 goto error;
3045
9c93829c 3046 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
c22995c5
GR		 3047 if (ret < 0)
3048 goto error;
3049
3050 /* Wait for temperature to stabilize */
3051 usleep_range(10000, 12000);
3052
9c93829c
VD		 3053 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3054 if (ret < 0)
c22995c5 3055 goto error;
c22995c5
GR		 3056
3057 /* Disable temperature sensor */
9c93829c 3058 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
c22995c5
GR		 3059 if (ret < 0)
3060 goto error;
3061
3062 *temp = ((val & 0x1f) - 5) * 5;
3063
3064error:
9c93829c 3065 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
fad09c73 3066 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3067 return ret;
3068}
3069
3070static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3071{
04bed143 3072 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3073 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3074 u16 val;
c22995c5
GR		 3075 int ret;
3076
3077 *temp = 0;
3078
9c93829c
VD		 3079 mutex_lock(&chip->reg_lock);
3080 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3081 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3082 if (ret < 0)
3083 return ret;
3084
9c93829c 3085 *temp = (val & 0xff) - 25;
c22995c5
GR		 3086
3087 return 0;
3088}
3089
f81ec90f 3090static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
c22995c5 3091{
04bed143 3092 struct mv88e6xxx_chip *chip = ds->priv;
158bc065 3093
fad09c73 3094 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
6594f615
VD		 3095 return -EOPNOTSUPP;
3096
fad09c73 3097 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
c22995c5
GR		 3098 return mv88e63xx_get_temp(ds, temp);
3099
3100 return mv88e61xx_get_temp(ds, temp);
3101}
3102
f81ec90f 3103static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
c22995c5 3104{
04bed143 3105 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3106 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3107 u16 val;
c22995c5
GR		 3108 int ret;
3109
fad09c73 3110 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3111 return -EOPNOTSUPP;
3112
3113 *temp = 0;
3114
9c93829c
VD		 3115 mutex_lock(&chip->reg_lock);
3116 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3117 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3118 if (ret < 0)
3119 return ret;
3120
9c93829c 3121 *temp = (((val >> 8) & 0x1f) * 5) - 25;
c22995c5
GR		 3122
3123 return 0;
3124}
3125
f81ec90f 3126static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
c22995c5 3127{
04bed143 3128 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3129 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c
VD		 3130 u16 val;
3131 int err;
c22995c5 3132
fad09c73 3133 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3134 return -EOPNOTSUPP;
3135
9c93829c
VD		 3136 mutex_lock(&chip->reg_lock);
3137 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3138 if (err)
3139 goto unlock;
c22995c5 3140 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
9c93829c
VD		 3141 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3142 (val & 0xe0ff) | (temp << 8));
3143unlock:
3144 mutex_unlock(&chip->reg_lock);
3145
3146 return err;
c22995c5
GR		 3147}
3148
f81ec90f 3149static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
c22995c5 3150{
04bed143 3151 struct mv88e6xxx_chip *chip = ds->priv;
fad09c73 3152 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
9c93829c 3153 u16 val;
c22995c5
GR		 3154 int ret;
3155
fad09c73 3156 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3157 return -EOPNOTSUPP;
3158
3159 *alarm = false;
3160
9c93829c
VD		 3161 mutex_lock(&chip->reg_lock);
3162 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3163 mutex_unlock(&chip->reg_lock);
c22995c5
GR		 3164 if (ret < 0)
3165 return ret;
3166
9c93829c 3167 *alarm = !!(val & 0x40);
c22995c5
GR		 3168
3169 return 0;
3170}
3171#endif /* CONFIG_NET_DSA_HWMON */
3172
855b1932
VD		 3173static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3174{
04bed143 3175 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3176
3177 return chip->eeprom_len;
3178}
3179
855b1932
VD		 3180static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3181 struct ethtool_eeprom *eeprom, u8 *data)
3182{
04bed143 3183 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3184 int err;
3185
3186 mutex_lock(&chip->reg_lock);
3187
3188 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
ec561276 3189 err = mv88e6xxx_g2_get_eeprom16(chip, eeprom, data);
855b1932
VD		 3190 else
3191 err = -EOPNOTSUPP;
3192
3193 mutex_unlock(&chip->reg_lock);
3194
3195 if (err)
3196 return err;
3197
3198 eeprom->magic = 0xc3ec4951;
3199
3200 return 0;
3201}
3202
855b1932
VD		 3203static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3204 struct ethtool_eeprom *eeprom, u8 *data)
3205{
04bed143 3206 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3207 int err;
3208
3209 if (eeprom->magic != 0xc3ec4951)
3210 return -EINVAL;
3211
3212 mutex_lock(&chip->reg_lock);
3213
3214 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
ec561276 3215 err = mv88e6xxx_g2_set_eeprom16(chip, eeprom, data);
855b1932
VD		 3216 else
3217 err = -EOPNOTSUPP;
3218
3219 mutex_unlock(&chip->reg_lock);
3220
3221 return err;
3222}
3223
f81ec90f
VD		 3224static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3225 [MV88E6085] = {
3226 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3227 .family = MV88E6XXX_FAMILY_6097,
3228 .name = "Marvell 88E6085",
3229 .num_databases = 4096,
3230 .num_ports = 10,
9dddd478 3231 .port_base_addr = 0x10,
acddbd21 3232 .age_time_coeff = 15000,
f81ec90f
VD		 3233 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3234 },
3235
3236 [MV88E6095] = {
3237 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3238 .family = MV88E6XXX_FAMILY_6095,
3239 .name = "Marvell 88E6095/88E6095F",
3240 .num_databases = 256,
3241 .num_ports = 11,
9dddd478 3242 .port_base_addr = 0x10,
acddbd21 3243 .age_time_coeff = 15000,
f81ec90f
VD		 3244 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3245 },
3246
3247 [MV88E6123] = {
3248 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3249 .family = MV88E6XXX_FAMILY_6165,
3250 .name = "Marvell 88E6123",
3251 .num_databases = 4096,
3252 .num_ports = 3,
9dddd478 3253 .port_base_addr = 0x10,
acddbd21 3254 .age_time_coeff = 15000,
f81ec90f
VD		 3255 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3256 },
3257
3258 [MV88E6131] = {
3259 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3260 .family = MV88E6XXX_FAMILY_6185,
3261 .name = "Marvell 88E6131",
3262 .num_databases = 256,
3263 .num_ports = 8,
9dddd478 3264 .port_base_addr = 0x10,
acddbd21 3265 .age_time_coeff = 15000,
f81ec90f
VD		 3266 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3267 },
3268
3269 [MV88E6161] = {
3270 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3271 .family = MV88E6XXX_FAMILY_6165,
3272 .name = "Marvell 88E6161",
3273 .num_databases = 4096,
3274 .num_ports = 6,
9dddd478 3275 .port_base_addr = 0x10,
acddbd21 3276 .age_time_coeff = 15000,
f81ec90f
VD		 3277 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3278 },
3279
3280 [MV88E6165] = {
3281 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3282 .family = MV88E6XXX_FAMILY_6165,
3283 .name = "Marvell 88E6165",
3284 .num_databases = 4096,
3285 .num_ports = 6,
9dddd478 3286 .port_base_addr = 0x10,
acddbd21 3287 .age_time_coeff = 15000,
f81ec90f
VD		 3288 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3289 },
3290
3291 [MV88E6171] = {
3292 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3293 .family = MV88E6XXX_FAMILY_6351,
3294 .name = "Marvell 88E6171",
3295 .num_databases = 4096,
3296 .num_ports = 7,
9dddd478 3297 .port_base_addr = 0x10,
acddbd21 3298 .age_time_coeff = 15000,
f81ec90f
VD		 3299 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3300 },
3301
3302 [MV88E6172] = {
3303 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3304 .family = MV88E6XXX_FAMILY_6352,
3305 .name = "Marvell 88E6172",
3306 .num_databases = 4096,
3307 .num_ports = 7,
9dddd478 3308 .port_base_addr = 0x10,
acddbd21 3309 .age_time_coeff = 15000,
f81ec90f
VD		 3310 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3311 },
3312
3313 [MV88E6175] = {
3314 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3315 .family = MV88E6XXX_FAMILY_6351,
3316 .name = "Marvell 88E6175",
3317 .num_databases = 4096,
3318 .num_ports = 7,
9dddd478 3319 .port_base_addr = 0x10,
acddbd21 3320 .age_time_coeff = 15000,
f81ec90f
VD		 3321 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3322 },
3323
3324 [MV88E6176] = {
3325 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3326 .family = MV88E6XXX_FAMILY_6352,
3327 .name = "Marvell 88E6176",
3328 .num_databases = 4096,
3329 .num_ports = 7,
9dddd478 3330 .port_base_addr = 0x10,
acddbd21 3331 .age_time_coeff = 15000,
f81ec90f
VD		 3332 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3333 },
3334
3335 [MV88E6185] = {
3336 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3337 .family = MV88E6XXX_FAMILY_6185,
3338 .name = "Marvell 88E6185",
3339 .num_databases = 256,
3340 .num_ports = 10,
9dddd478 3341 .port_base_addr = 0x10,
acddbd21 3342 .age_time_coeff = 15000,
f81ec90f
VD		 3343 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3344 },
3345
3346 [MV88E6240] = {
3347 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3348 .family = MV88E6XXX_FAMILY_6352,
3349 .name = "Marvell 88E6240",
3350 .num_databases = 4096,
3351 .num_ports = 7,
9dddd478 3352 .port_base_addr = 0x10,
acddbd21 3353 .age_time_coeff = 15000,
f81ec90f
VD		 3354 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3355 },
3356
3357 [MV88E6320] = {
3358 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3359 .family = MV88E6XXX_FAMILY_6320,
3360 .name = "Marvell 88E6320",
3361 .num_databases = 4096,
3362 .num_ports = 7,
9dddd478 3363 .port_base_addr = 0x10,
acddbd21 3364 .age_time_coeff = 15000,
f81ec90f
VD		 3365 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3366 },
3367
3368 [MV88E6321] = {
3369 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3370 .family = MV88E6XXX_FAMILY_6320,
3371 .name = "Marvell 88E6321",
3372 .num_databases = 4096,
3373 .num_ports = 7,
9dddd478 3374 .port_base_addr = 0x10,
acddbd21 3375 .age_time_coeff = 15000,
f81ec90f
VD		 3376 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3377 },
3378
3379 [MV88E6350] = {
3380 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3381 .family = MV88E6XXX_FAMILY_6351,
3382 .name = "Marvell 88E6350",
3383 .num_databases = 4096,
3384 .num_ports = 7,
9dddd478 3385 .port_base_addr = 0x10,
acddbd21 3386 .age_time_coeff = 15000,
f81ec90f
VD		 3387 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3388 },
3389
3390 [MV88E6351] = {
3391 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3392 .family = MV88E6XXX_FAMILY_6351,
3393 .name = "Marvell 88E6351",
3394 .num_databases = 4096,
3395 .num_ports = 7,
9dddd478 3396 .port_base_addr = 0x10,
acddbd21 3397 .age_time_coeff = 15000,
f81ec90f
VD		 3398 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3399 },
3400
3401 [MV88E6352] = {
3402 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3403 .family = MV88E6XXX_FAMILY_6352,
3404 .name = "Marvell 88E6352",
3405 .num_databases = 4096,
3406 .num_ports = 7,
9dddd478 3407 .port_base_addr = 0x10,
acddbd21 3408 .age_time_coeff = 15000,
f81ec90f
VD		 3409 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3410 },
3411};
3412
5f7c0367 3413static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 3414{
a439c061 3415 int i;
b9b37713 3416
5f7c0367
VD		 3417 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3418 if (mv88e6xxx_table[i].prod_num == prod_num)
3419 return &mv88e6xxx_table[i];
b9b37713 3420
b9b37713
VD		 3421 return NULL;
3422}
3423
fad09c73 3424static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 3425{
3426 const struct mv88e6xxx_info *info;
8f6345b2
VD		 3427 unsigned int prod_num, rev;
3428 u16 id;
3429 int err;
bc46a3d5 3430
8f6345b2
VD		 3431 mutex_lock(&chip->reg_lock);
3432 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3433 mutex_unlock(&chip->reg_lock);
3434 if (err)
3435 return err;
bc46a3d5
VD		 3436
3437 prod_num = (id & 0xfff0) >> 4;
3438 rev = id & 0x000f;
3439
3440 info = mv88e6xxx_lookup_info(prod_num);
3441 if (!info)
3442 return -ENODEV;
3443
caac8545 3444 /* Update the compatible info with the probed one */
fad09c73 3445 chip->info = info;
bc46a3d5 3446
ca070c10
VD		 3447 err = mv88e6xxx_g2_require(chip);
3448 if (err)
3449 return err;
3450
fad09c73
VD		 3451 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3452 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 3453
3454 return 0;
3455}
3456
fad09c73 3457static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 3458{
fad09c73 3459 struct mv88e6xxx_chip *chip;
469d729f 3460
fad09c73
VD		 3461 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3462 if (!chip)
469d729f
VD		 3463 return NULL;
3464
fad09c73 3465 chip->dev = dev;
469d729f 3466
fad09c73 3467 mutex_init(&chip->reg_lock);
469d729f 3468
fad09c73 3469 return chip;
469d729f
VD		 3470}
3471
ec561276
VD		 3472static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3473 .read = mv88e6xxx_g2_smi_phy_read,
3474 .write = mv88e6xxx_g2_smi_phy_write,
3475};
3476
e57e5e77
VD		 3477static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3478 .read = mv88e6xxx_read,
3479 .write = mv88e6xxx_write,
3480};
3481
3482static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3483{
3484 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3485 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3486 } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3487 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3488 mv88e6xxx_ppu_state_init(chip);
3489 } else {
3490 chip->phy_ops = &mv88e6xxx_phy_ops;
3491 }
3492}
3493
930188ce
AL		 3494static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3495{
3496 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3497 mv88e6xxx_ppu_state_destroy(chip);
3498 }
3499}
3500
fad09c73 3501static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4a70c4ab
VD		 3502 struct mii_bus *bus, int sw_addr)
3503{
3504 /* ADDR[0] pin is unavailable externally and considered zero */
3505 if (sw_addr & 0x1)
3506 return -EINVAL;
3507
914b32f6 3508 if (sw_addr == 0)
fad09c73 3509 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
a0ffff24 3510 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
fad09c73 3511 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
914b32f6
VD		 3512 else
3513 return -EINVAL;
3514
fad09c73
VD		 3515 chip->bus = bus;
3516 chip->sw_addr = sw_addr;
4a70c4ab
VD		 3517
3518 return 0;
3519}
3520
7b314362
AL		 3521static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3522{
04bed143 3523 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be
AL		 3524
3525 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3526 return DSA_TAG_PROTO_EDSA;
3527
3528 return DSA_TAG_PROTO_DSA;
7b314362
AL		 3529}
3530
fcdce7d0
AL		 3531static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3532 struct device *host_dev, int sw_addr,
3533 void **priv)
a77d43f1 3534{
fad09c73 3535 struct mv88e6xxx_chip *chip;
a439c061 3536 struct mii_bus *bus;
b516d453 3537 int err;
a77d43f1 3538
a439c061 3539 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3540 if (!bus)
3541 return NULL;
3542
fad09c73
VD		 3543 chip = mv88e6xxx_alloc_chip(dsa_dev);
3544 if (!chip)
469d729f
VD		 3545 return NULL;
3546
caac8545 3547 /* Legacy SMI probing will only support chips similar to 88E6085 */
fad09c73 3548 chip->info = &mv88e6xxx_table[MV88E6085];
caac8545 3549
fad09c73 3550 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4a70c4ab
VD		 3551 if (err)
3552 goto free;
3553
fad09c73 3554 err = mv88e6xxx_detect(chip);
bc46a3d5 3555 if (err)
469d729f 3556 goto free;
a439c061 3557
e57e5e77
VD		 3558 mv88e6xxx_phy_init(chip);
3559
fad09c73 3560 err = mv88e6xxx_mdio_register(chip, NULL);
b516d453 3561 if (err)
469d729f 3562 goto free;
b516d453 3563
fad09c73 3564 *priv = chip;
a439c061 3565
fad09c73 3566 return chip->info->name;
469d729f 3567free:
fad09c73 3568 devm_kfree(dsa_dev, chip);
469d729f
VD		 3569
3570 return NULL;
a77d43f1
AL		 3571}
3572
7df8fbdd
VD		 3573static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3574 const struct switchdev_obj_port_mdb *mdb,
3575 struct switchdev_trans *trans)
3576{
3577 /* We don't need any dynamic resource from the kernel (yet),
3578 * so skip the prepare phase.
3579 */
3580
3581 return 0;
3582}
3583
3584static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3585 const struct switchdev_obj_port_mdb *mdb,
3586 struct switchdev_trans *trans)
3587{
04bed143 3588 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3589
3590 mutex_lock(&chip->reg_lock);
3591 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3592 GLOBAL_ATU_DATA_STATE_MC_STATIC))
3593 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3594 mutex_unlock(&chip->reg_lock);
3595}
3596
3597static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3598 const struct switchdev_obj_port_mdb *mdb)
3599{
04bed143 3600 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3601 int err;
3602
3603 mutex_lock(&chip->reg_lock);
3604 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3605 GLOBAL_ATU_DATA_STATE_UNUSED);
3606 mutex_unlock(&chip->reg_lock);
3607
3608 return err;
3609}
3610
3611static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3612 struct switchdev_obj_port_mdb *mdb,
3613 int (*cb)(struct switchdev_obj *obj))
3614{
04bed143 3615 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 3616 int err;
3617
3618 mutex_lock(&chip->reg_lock);
3619 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3620 mutex_unlock(&chip->reg_lock);
3621
3622 return err;
3623}
3624
9d490b4e 3625static struct dsa_switch_ops mv88e6xxx_switch_ops = {
fcdce7d0 3626 .probe = mv88e6xxx_drv_probe,
7b314362 3627 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
f81ec90f
VD		 3628 .setup = mv88e6xxx_setup,
3629 .set_addr = mv88e6xxx_set_addr,
f81ec90f
VD		 3630 .adjust_link = mv88e6xxx_adjust_link,
3631 .get_strings = mv88e6xxx_get_strings,
3632 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3633 .get_sset_count = mv88e6xxx_get_sset_count,
3634 .set_eee = mv88e6xxx_set_eee,
3635 .get_eee = mv88e6xxx_get_eee,
3636#ifdef CONFIG_NET_DSA_HWMON
3637 .get_temp = mv88e6xxx_get_temp,
3638 .get_temp_limit = mv88e6xxx_get_temp_limit,
3639 .set_temp_limit = mv88e6xxx_set_temp_limit,
3640 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3641#endif
f8cd8753 3642 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 3643 .get_eeprom = mv88e6xxx_get_eeprom,
3644 .set_eeprom = mv88e6xxx_set_eeprom,
3645 .get_regs_len = mv88e6xxx_get_regs_len,
3646 .get_regs = mv88e6xxx_get_regs,
2cfcd964 3647 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 3648 .port_bridge_join = mv88e6xxx_port_bridge_join,
3649 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3650 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3651 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3652 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3653 .port_vlan_add = mv88e6xxx_port_vlan_add,
3654 .port_vlan_del = mv88e6xxx_port_vlan_del,
3655 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3656 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3657 .port_fdb_add = mv88e6xxx_port_fdb_add,
3658 .port_fdb_del = mv88e6xxx_port_fdb_del,
3659 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 3660 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3661 .port_mdb_add = mv88e6xxx_port_mdb_add,
3662 .port_mdb_del = mv88e6xxx_port_mdb_del,
3663 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
f81ec90f
VD		 3664};
3665
fad09c73 3666static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
b7e66a5f
VD		 3667 struct device_node *np)
3668{
fad09c73 3669 struct device *dev = chip->dev;
b7e66a5f
VD		 3670 struct dsa_switch *ds;
3671
3672 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3673 if (!ds)
3674 return -ENOMEM;
3675
3676 ds->dev = dev;
fad09c73 3677 ds->priv = chip;
9d490b4e 3678 ds->ops = &mv88e6xxx_switch_ops;
b7e66a5f
VD		 3679
3680 dev_set_drvdata(dev, ds);
3681
3682 return dsa_register_switch(ds, np);
3683}
3684
fad09c73 3685static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 3686{
fad09c73 3687 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 3688}
3689
57d32310 3690static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 3691{
14c7b3c3 3692 struct device *dev = &mdiodev->dev;
f8cd8753 3693 struct device_node *np = dev->of_node;
caac8545 3694 const struct mv88e6xxx_info *compat_info;
fad09c73 3695 struct mv88e6xxx_chip *chip;
f8cd8753 3696 u32 eeprom_len;
52638f71 3697 int err;
14c7b3c3 3698
caac8545
VD		 3699 compat_info = of_device_get_match_data(dev);
3700 if (!compat_info)
3701 return -EINVAL;
3702
fad09c73
VD		 3703 chip = mv88e6xxx_alloc_chip(dev);
3704 if (!chip)
14c7b3c3
AL		 3705 return -ENOMEM;
3706
fad09c73 3707 chip->info = compat_info;
caac8545 3708
fad09c73 3709 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab
VD		 3710 if (err)
3711 return err;
14c7b3c3 3712
fad09c73 3713 err = mv88e6xxx_detect(chip);
bc46a3d5
VD		 3714 if (err)
3715 return err;
14c7b3c3 3716
e57e5e77
VD		 3717 mv88e6xxx_phy_init(chip);
3718
fad09c73
VD		 3719 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3720 if (IS_ERR(chip->reset))
3721 return PTR_ERR(chip->reset);
52638f71 3722
855b1932 3723 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
f8cd8753 3724 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
fad09c73 3725 chip->eeprom_len = eeprom_len;
f8cd8753 3726
fad09c73 3727 err = mv88e6xxx_mdio_register(chip, np);
b516d453
AL		 3728 if (err)
3729 return err;
3730
fad09c73 3731 err = mv88e6xxx_register_switch(chip, np);
83c0afae 3732 if (err) {
fad09c73 3733 mv88e6xxx_mdio_unregister(chip);
83c0afae
AL		 3734 return err;
3735 }
3736
98e67308
BH		 3737 return 0;
3738}
14c7b3c3
AL		 3739
3740static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3741{
3742 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
04bed143 3743 struct mv88e6xxx_chip *chip = ds->priv;
14c7b3c3 3744
930188ce 3745 mv88e6xxx_phy_destroy(chip);
fad09c73
VD		 3746 mv88e6xxx_unregister_switch(chip);
3747 mv88e6xxx_mdio_unregister(chip);
14c7b3c3
AL		 3748}
3749
3750static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 3751 {
3752 .compatible = "marvell,mv88e6085",
3753 .data = &mv88e6xxx_table[MV88E6085],
3754 },
14c7b3c3
AL		 3755 { /* sentinel */ },
3756};
3757
3758MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3759
3760static struct mdio_driver mv88e6xxx_driver = {
3761 .probe = mv88e6xxx_probe,
3762 .remove = mv88e6xxx_remove,
3763 .mdiodrv.driver = {
3764 .name = "mv88e6085",
3765 .of_match_table = mv88e6xxx_of_match,
3766 },
3767};
3768
3769static int __init mv88e6xxx_init(void)
3770{
9d490b4e 3771 register_switch_driver(&mv88e6xxx_switch_ops);
14c7b3c3
AL		 3772 return mdio_driver_register(&mv88e6xxx_driver);
3773}
98e67308
BH		 3774module_init(mv88e6xxx_init);
3775
3776static void __exit mv88e6xxx_cleanup(void)
3777{
14c7b3c3 3778 mdio_driver_unregister(&mv88e6xxx_driver);
9d490b4e 3779 unregister_switch_driver(&mv88e6xxx_switch_ops);
98e67308
BH		 3780}
3781module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 3782
3783MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3784MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3785MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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