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e1000: reorder e1000_param.c
[deliverable/linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
1da177e4 31char e1000_driver_name[] = "e1000";
3ad2cc67 32static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 33#ifndef CONFIG_E1000_NAPI
34#define DRIVERNAPI
35#else
36#define DRIVERNAPI "-NAPI"
37#endif
ff1e55b0 38#define DRV_VERSION "7.2.9-k4"DRIVERNAPI
1da177e4 39char e1000_driver_version[] = DRV_VERSION;
3d41e30a 40static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
1da177e4
LT		 41
42/* e1000_pci_tbl - PCI Device ID Table
43 *
44 * Last entry must be all 0s
45 *
46 * Macro expands to...
47 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
48 */
49static struct pci_device_id e1000_pci_tbl[] = {
50 INTEL_E1000_ETHERNET_DEVICE(0x1000),
51 INTEL_E1000_ETHERNET_DEVICE(0x1001),
52 INTEL_E1000_ETHERNET_DEVICE(0x1004),
53 INTEL_E1000_ETHERNET_DEVICE(0x1008),
54 INTEL_E1000_ETHERNET_DEVICE(0x1009),
55 INTEL_E1000_ETHERNET_DEVICE(0x100C),
56 INTEL_E1000_ETHERNET_DEVICE(0x100D),
57 INTEL_E1000_ETHERNET_DEVICE(0x100E),
58 INTEL_E1000_ETHERNET_DEVICE(0x100F),
59 INTEL_E1000_ETHERNET_DEVICE(0x1010),
60 INTEL_E1000_ETHERNET_DEVICE(0x1011),
61 INTEL_E1000_ETHERNET_DEVICE(0x1012),
62 INTEL_E1000_ETHERNET_DEVICE(0x1013),
63 INTEL_E1000_ETHERNET_DEVICE(0x1014),
64 INTEL_E1000_ETHERNET_DEVICE(0x1015),
65 INTEL_E1000_ETHERNET_DEVICE(0x1016),
66 INTEL_E1000_ETHERNET_DEVICE(0x1017),
67 INTEL_E1000_ETHERNET_DEVICE(0x1018),
68 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 69 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 70 INTEL_E1000_ETHERNET_DEVICE(0x101D),
71 INTEL_E1000_ETHERNET_DEVICE(0x101E),
72 INTEL_E1000_ETHERNET_DEVICE(0x1026),
73 INTEL_E1000_ETHERNET_DEVICE(0x1027),
74 INTEL_E1000_ETHERNET_DEVICE(0x1028),
ae2c3860
AK		 75 INTEL_E1000_ETHERNET_DEVICE(0x1049),
76 INTEL_E1000_ETHERNET_DEVICE(0x104A),
77 INTEL_E1000_ETHERNET_DEVICE(0x104B),
78 INTEL_E1000_ETHERNET_DEVICE(0x104C),
79 INTEL_E1000_ETHERNET_DEVICE(0x104D),
07b8fede
MC		 80 INTEL_E1000_ETHERNET_DEVICE(0x105E),
81 INTEL_E1000_ETHERNET_DEVICE(0x105F),
82 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 83 INTEL_E1000_ETHERNET_DEVICE(0x1075),
84 INTEL_E1000_ETHERNET_DEVICE(0x1076),
85 INTEL_E1000_ETHERNET_DEVICE(0x1077),
86 INTEL_E1000_ETHERNET_DEVICE(0x1078),
87 INTEL_E1000_ETHERNET_DEVICE(0x1079),
88 INTEL_E1000_ETHERNET_DEVICE(0x107A),
89 INTEL_E1000_ETHERNET_DEVICE(0x107B),
90 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 91 INTEL_E1000_ETHERNET_DEVICE(0x107D),
92 INTEL_E1000_ETHERNET_DEVICE(0x107E),
93 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 94 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 95 INTEL_E1000_ETHERNET_DEVICE(0x108B),
96 INTEL_E1000_ETHERNET_DEVICE(0x108C),
6418ecc6
JK		 97 INTEL_E1000_ETHERNET_DEVICE(0x1096),
98 INTEL_E1000_ETHERNET_DEVICE(0x1098),
b7ee49db 99 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 100 INTEL_E1000_ETHERNET_DEVICE(0x109A),
5881cde8 101 INTEL_E1000_ETHERNET_DEVICE(0x10A4),
b7ee49db 102 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
6418ecc6 103 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
ae2c3860
AK		 104 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
105 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
fc2307d0
AK		 106 INTEL_E1000_ETHERNET_DEVICE(0x10BC),
107 INTEL_E1000_ETHERNET_DEVICE(0x10C4),
108 INTEL_E1000_ETHERNET_DEVICE(0x10C5),
1da177e4
LT		 109 /* required last entry */
110 {0,}
111};
112
113MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
114
35574764
NN		 115int e1000_up(struct e1000_adapter *adapter);
116void e1000_down(struct e1000_adapter *adapter);
117void e1000_reinit_locked(struct e1000_adapter *adapter);
118void e1000_reset(struct e1000_adapter *adapter);
119int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
120int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
121int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
122void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
123void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67 124static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
35574764 125 struct e1000_tx_ring *txdr);
3ad2cc67 126static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
35574764 127 struct e1000_rx_ring *rxdr);
3ad2cc67 128static void e1000_free_tx_resources(struct e1000_adapter *adapter,
35574764 129 struct e1000_tx_ring *tx_ring);
3ad2cc67 130static void e1000_free_rx_resources(struct e1000_adapter *adapter,
35574764
NN		 131 struct e1000_rx_ring *rx_ring);
132void e1000_update_stats(struct e1000_adapter *adapter);
1da177e4
LT		 133
134static int e1000_init_module(void);
135static void e1000_exit_module(void);
136static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
137static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 138static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 139static int e1000_sw_init(struct e1000_adapter *adapter);
140static int e1000_open(struct net_device *netdev);
141static int e1000_close(struct net_device *netdev);
142static void e1000_configure_tx(struct e1000_adapter *adapter);
143static void e1000_configure_rx(struct e1000_adapter *adapter);
144static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 145static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
146static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
147static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
148 struct e1000_tx_ring *tx_ring);
149static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
150 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 151static void e1000_set_multi(struct net_device *netdev);
152static void e1000_update_phy_info(unsigned long data);
153static void e1000_watchdog(unsigned long data);
1da177e4
LT		 154static void e1000_82547_tx_fifo_stall(unsigned long data);
155static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
156static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
157static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
158static int e1000_set_mac(struct net_device *netdev, void *p);
7d12e780 159static irqreturn_t e1000_intr(int irq, void *data);
581d708e
MC		 160static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
161 struct e1000_tx_ring *tx_ring);
1da177e4 162#ifdef CONFIG_E1000_NAPI
581d708e 163static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 164static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 165 struct e1000_rx_ring *rx_ring,
1da177e4 166 int *work_done, int work_to_do);
2d7edb92 167static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 168 struct e1000_rx_ring *rx_ring,
2d7edb92 169 int *work_done, int work_to_do);
1da177e4 170#else
581d708e
MC		 171static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
172 struct e1000_rx_ring *rx_ring);
173static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
174 struct e1000_rx_ring *rx_ring);
1da177e4 175#endif
581d708e 176static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 177 struct e1000_rx_ring *rx_ring,
178 int cleaned_count);
581d708e 179static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 180 struct e1000_rx_ring *rx_ring,
181 int cleaned_count);
1da177e4
LT		 182static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
183static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
184 int cmd);
35574764 185void e1000_set_ethtool_ops(struct net_device *netdev);
1da177e4
LT		 186static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
187static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
188static void e1000_tx_timeout(struct net_device *dev);
87041639 189static void e1000_reset_task(struct net_device *dev);
1da177e4 190static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 191static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
192 struct sk_buff *skb);
1da177e4
LT		 193
194static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
195static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
196static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
197static void e1000_restore_vlan(struct e1000_adapter *adapter);
198
977e74b5 199static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
6fdfef16 200#ifdef CONFIG_PM
1da177e4
LT		 201static int e1000_resume(struct pci_dev *pdev);
202#endif
c653e635 203static void e1000_shutdown(struct pci_dev *pdev);
1da177e4
LT		 204
205#ifdef CONFIG_NET_POLL_CONTROLLER
206/* for netdump / net console */
207static void e1000_netpoll (struct net_device *netdev);
208#endif
209
35574764
NN		 210extern void e1000_check_options(struct e1000_adapter *adapter);
211
9026729b
AK		 212static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
213 pci_channel_state_t state);
214static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
215static void e1000_io_resume(struct pci_dev *pdev);
216
217static struct pci_error_handlers e1000_err_handler = {
218 .error_detected = e1000_io_error_detected,
219 .slot_reset = e1000_io_slot_reset,
220 .resume = e1000_io_resume,
221};
24025e4e 222
1da177e4
LT		 223static struct pci_driver e1000_driver = {
224 .name = e1000_driver_name,
225 .id_table = e1000_pci_tbl,
226 .probe = e1000_probe,
227 .remove = __devexit_p(e1000_remove),
c4e24f01 228#ifdef CONFIG_PM
1da177e4 229 /* Power Managment Hooks */
1da177e4 230 .suspend = e1000_suspend,
c653e635 231 .resume = e1000_resume,
1da177e4 232#endif
9026729b
AK		 233 .shutdown = e1000_shutdown,
234 .err_handler = &e1000_err_handler
1da177e4
LT		 235};
236
237MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
238MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
239MODULE_LICENSE("GPL");
240MODULE_VERSION(DRV_VERSION);
241
242static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
243module_param(debug, int, 0);
244MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
245
246/**
247 * e1000_init_module - Driver Registration Routine
248 *
249 * e1000_init_module is the first routine called when the driver is
250 * loaded. All it does is register with the PCI subsystem.
251 **/
252
253static int __init
254e1000_init_module(void)
255{
256 int ret;
257 printk(KERN_INFO "%s - version %s\n",
258 e1000_driver_string, e1000_driver_version);
259
260 printk(KERN_INFO "%s\n", e1000_copyright);
261
29917620 262 ret = pci_register_driver(&e1000_driver);
8b378def 263
1da177e4
LT		 264 return ret;
265}
266
267module_init(e1000_init_module);
268
269/**
270 * e1000_exit_module - Driver Exit Cleanup Routine
271 *
272 * e1000_exit_module is called just before the driver is removed
273 * from memory.
274 **/
275
276static void __exit
277e1000_exit_module(void)
278{
1da177e4
LT		 279 pci_unregister_driver(&e1000_driver);
280}
281
282module_exit(e1000_exit_module);
283
2db10a08
AK		 284static int e1000_request_irq(struct e1000_adapter *adapter)
285{
286 struct net_device *netdev = adapter->netdev;
287 int flags, err = 0;
288
c0bc8721 289 flags = IRQF_SHARED;
2db10a08
AK		 290#ifdef CONFIG_PCI_MSI
291 if (adapter->hw.mac_type > e1000_82547_rev_2) {
292 adapter->have_msi = TRUE;
293 if ((err = pci_enable_msi(adapter->pdev))) {
294 DPRINTK(PROBE, ERR,
295 "Unable to allocate MSI interrupt Error: %d\n", err);
296 adapter->have_msi = FALSE;
297 }
298 }
299 if (adapter->have_msi)
61ef5c00 300 flags &= ~IRQF_SHARED;
2db10a08
AK		 301#endif
302 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags,
303 netdev->name, netdev)))
304 DPRINTK(PROBE, ERR,
305 "Unable to allocate interrupt Error: %d\n", err);
306
307 return err;
308}
309
310static void e1000_free_irq(struct e1000_adapter *adapter)
311{
312 struct net_device *netdev = adapter->netdev;
313
314 free_irq(adapter->pdev->irq, netdev);
315
316#ifdef CONFIG_PCI_MSI
317 if (adapter->have_msi)
318 pci_disable_msi(adapter->pdev);
319#endif
320}
321
1da177e4
LT		 322/**
323 * e1000_irq_disable - Mask off interrupt generation on the NIC
324 * @adapter: board private structure
325 **/
326
e619d523 327static void
1da177e4
LT		 328e1000_irq_disable(struct e1000_adapter *adapter)
329{
330 atomic_inc(&adapter->irq_sem);
331 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
332 E1000_WRITE_FLUSH(&adapter->hw);
333 synchronize_irq(adapter->pdev->irq);
334}
335
336/**
337 * e1000_irq_enable - Enable default interrupt generation settings
338 * @adapter: board private structure
339 **/
340
e619d523 341static void
1da177e4
LT		 342e1000_irq_enable(struct e1000_adapter *adapter)
343{
96838a40 344 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 345 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
346 E1000_WRITE_FLUSH(&adapter->hw);
347 }
348}
3ad2cc67
AB		 349
350static void
2d7edb92
MC		 351e1000_update_mng_vlan(struct e1000_adapter *adapter)
352{
353 struct net_device *netdev = adapter->netdev;
354 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
355 uint16_t old_vid = adapter->mng_vlan_id;
96838a40
JB		 356 if (adapter->vlgrp) {
357 if (!adapter->vlgrp->vlan_devices[vid]) {
358 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 359 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
360 e1000_vlan_rx_add_vid(netdev, vid);
361 adapter->mng_vlan_id = vid;
362 } else
363 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 364
365 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
366 (vid != old_vid) &&
2d7edb92
MC		 367 !adapter->vlgrp->vlan_devices[old_vid])
368 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 369 } else
370 adapter->mng_vlan_id = vid;
2d7edb92
MC		 371 }
372}
b55ccb35
JK		 373
374/**
375 * e1000_release_hw_control - release control of the h/w to f/w
376 * @adapter: address of board private structure
377 *
378 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
379 * For ASF and Pass Through versions of f/w this means that the
380 * driver is no longer loaded. For AMT version (only with 82573) i
90fb5135 381 * of the f/w this means that the network i/f is closed.
76c224bc 382 *
b55ccb35
JK		 383 **/
384
e619d523 385static void
b55ccb35
JK		 386e1000_release_hw_control(struct e1000_adapter *adapter)
387{
388 uint32_t ctrl_ext;
389 uint32_t swsm;
cd94dd0b 390 uint32_t extcnf;
b55ccb35
JK		 391
392 /* Let firmware taken over control of h/w */
393 switch (adapter->hw.mac_type) {
394 case e1000_82571:
395 case e1000_82572:
4cc15f54 396 case e1000_80003es2lan:
b55ccb35
JK		 397 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
398 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
399 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
400 break;
401 case e1000_82573:
402 swsm = E1000_READ_REG(&adapter->hw, SWSM);
403 E1000_WRITE_REG(&adapter->hw, SWSM,
404 swsm & ~E1000_SWSM_DRV_LOAD);
cd94dd0b
AK		 405 case e1000_ich8lan:
406 extcnf = E1000_READ_REG(&adapter->hw, CTRL_EXT);
407 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
408 extcnf & ~E1000_CTRL_EXT_DRV_LOAD);
409 break;
b55ccb35
JK		 410 default:
411 break;
412 }
413}
414
415/**
416 * e1000_get_hw_control - get control of the h/w from f/w
417 * @adapter: address of board private structure
418 *
419 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
76c224bc
AK		 420 * For ASF and Pass Through versions of f/w this means that
421 * the driver is loaded. For AMT version (only with 82573)
90fb5135 422 * of the f/w this means that the network i/f is open.
76c224bc 423 *
b55ccb35
JK		 424 **/
425
e619d523 426static void
b55ccb35
JK		 427e1000_get_hw_control(struct e1000_adapter *adapter)
428{
429 uint32_t ctrl_ext;
430 uint32_t swsm;
cd94dd0b 431 uint32_t extcnf;
90fb5135 432
b55ccb35
JK		 433 /* Let firmware know the driver has taken over */
434 switch (adapter->hw.mac_type) {
435 case e1000_82571:
436 case e1000_82572:
4cc15f54 437 case e1000_80003es2lan:
b55ccb35
JK		 438 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
439 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
440 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
441 break;
442 case e1000_82573:
443 swsm = E1000_READ_REG(&adapter->hw, SWSM);
444 E1000_WRITE_REG(&adapter->hw, SWSM,
445 swsm | E1000_SWSM_DRV_LOAD);
446 break;
cd94dd0b
AK		 447 case e1000_ich8lan:
448 extcnf = E1000_READ_REG(&adapter->hw, EXTCNF_CTRL);
449 E1000_WRITE_REG(&adapter->hw, EXTCNF_CTRL,
450 extcnf | E1000_EXTCNF_CTRL_SWFLAG);
451 break;
b55ccb35
JK		 452 default:
453 break;
454 }
455}
456
1da177e4
LT		 457int
458e1000_up(struct e1000_adapter *adapter)
459{
460 struct net_device *netdev = adapter->netdev;
2db10a08 461 int i;
1da177e4
LT		 462
463 /* hardware has been reset, we need to reload some things */
464
1da177e4
LT		 465 e1000_set_multi(netdev);
466
467 e1000_restore_vlan(adapter);
468
469 e1000_configure_tx(adapter);
470 e1000_setup_rctl(adapter);
471 e1000_configure_rx(adapter);
72d64a43
JK		 472 /* call E1000_DESC_UNUSED which always leaves
473 * at least 1 descriptor unused to make sure
474 * next_to_use != next_to_clean */
f56799ea 475 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 476 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 477 adapter->alloc_rx_buf(adapter, ring,
478 E1000_DESC_UNUSED(ring));
f56799ea 479 }
1da177e4 480
7bfa4816
JK		 481 adapter->tx_queue_len = netdev->tx_queue_len;
482
1da177e4
LT		 483#ifdef CONFIG_E1000_NAPI
484 netif_poll_enable(netdev);
485#endif
5de55624
MC		 486 e1000_irq_enable(adapter);
487
1314bbf3
AK		 488 clear_bit(__E1000_DOWN, &adapter->flags);
489
490 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
1da177e4
LT		 491 return 0;
492}
493
79f05bf0
AK		 494/**
495 * e1000_power_up_phy - restore link in case the phy was powered down
496 * @adapter: address of board private structure
497 *
498 * The phy may be powered down to save power and turn off link when the
499 * driver is unloaded and wake on lan is not enabled (among others)
500 * *** this routine MUST be followed by a call to e1000_reset ***
501 *
502 **/
503
d658266e 504void e1000_power_up_phy(struct e1000_adapter *adapter)
79f05bf0
AK		 505{
506 uint16_t mii_reg = 0;
507
508 /* Just clear the power down bit to wake the phy back up */
509 if (adapter->hw.media_type == e1000_media_type_copper) {
510 /* according to the manual, the phy will retain its
511 * settings across a power-down/up cycle */
512 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
513 mii_reg &= ~MII_CR_POWER_DOWN;
514 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
515 }
516}
517
518static void e1000_power_down_phy(struct e1000_adapter *adapter)
519{
61c2505f
BA		 520 /* Power down the PHY so no link is implied when interface is down *
521 * The PHY cannot be powered down if any of the following is TRUE *
79f05bf0
AK		 522 * (a) WoL is enabled
523 * (b) AMT is active
524 * (c) SoL/IDER session is active */
525 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
61c2505f 526 adapter->hw.media_type == e1000_media_type_copper) {
79f05bf0 527 uint16_t mii_reg = 0;
61c2505f
BA		 528
529 switch (adapter->hw.mac_type) {
530 case e1000_82540:
531 case e1000_82545:
532 case e1000_82545_rev_3:
533 case e1000_82546:
534 case e1000_82546_rev_3:
535 case e1000_82541:
536 case e1000_82541_rev_2:
537 case e1000_82547:
538 case e1000_82547_rev_2:
539 if (E1000_READ_REG(&adapter->hw, MANC) &
540 E1000_MANC_SMBUS_EN)
541 goto out;
542 break;
543 case e1000_82571:
544 case e1000_82572:
545 case e1000_82573:
546 case e1000_80003es2lan:
547 case e1000_ich8lan:
548 if (e1000_check_mng_mode(&adapter->hw) ||
549 e1000_check_phy_reset_block(&adapter->hw))
550 goto out;
551 break;
552 default:
553 goto out;
554 }
79f05bf0
AK		 555 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
556 mii_reg |= MII_CR_POWER_DOWN;
557 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
558 mdelay(1);
559 }
61c2505f
BA		 560out:
561 return;
79f05bf0
AK		 562}
563
1da177e4
LT		 564void
565e1000_down(struct e1000_adapter *adapter)
566{
567 struct net_device *netdev = adapter->netdev;
568
1314bbf3
AK		 569 /* signal that we're down so the interrupt handler does not
570 * reschedule our watchdog timer */
571 set_bit(__E1000_DOWN, &adapter->flags);
572
1da177e4 573 e1000_irq_disable(adapter);
c1605eb3 574
1da177e4
LT		 575 del_timer_sync(&adapter->tx_fifo_stall_timer);
576 del_timer_sync(&adapter->watchdog_timer);
577 del_timer_sync(&adapter->phy_info_timer);
578
579#ifdef CONFIG_E1000_NAPI
580 netif_poll_disable(netdev);
581#endif
7bfa4816 582 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 583 adapter->link_speed = 0;
584 adapter->link_duplex = 0;
585 netif_carrier_off(netdev);
586 netif_stop_queue(netdev);
587
588 e1000_reset(adapter);
581d708e
MC		 589 e1000_clean_all_tx_rings(adapter);
590 e1000_clean_all_rx_rings(adapter);
1da177e4 591}
1da177e4 592
2db10a08
AK		 593void
594e1000_reinit_locked(struct e1000_adapter *adapter)
595{
596 WARN_ON(in_interrupt());
597 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
598 msleep(1);
599 e1000_down(adapter);
600 e1000_up(adapter);
601 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 602}
603
604void
605e1000_reset(struct e1000_adapter *adapter)
606{
2d7edb92 607 uint32_t pba, manc;
1125ecbc 608 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 609
610 /* Repartition Pba for greater than 9k mtu
611 * To take effect CTRL.RST is required.
612 */
613
2d7edb92
MC		 614 switch (adapter->hw.mac_type) {
615 case e1000_82547:
0e6ef3e0 616 case e1000_82547_rev_2:
2d7edb92
MC		 617 pba = E1000_PBA_30K;
618 break;
868d5309
MC		 619 case e1000_82571:
620 case e1000_82572:
6418ecc6 621 case e1000_80003es2lan:
868d5309
MC		 622 pba = E1000_PBA_38K;
623 break;
2d7edb92
MC		 624 case e1000_82573:
625 pba = E1000_PBA_12K;
626 break;
cd94dd0b
AK		 627 case e1000_ich8lan:
628 pba = E1000_PBA_8K;
629 break;
2d7edb92
MC		 630 default:
631 pba = E1000_PBA_48K;
632 break;
633 }
634
96838a40 635 if ((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 636 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 637 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 638
639
96838a40 640 if (adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 641 adapter->tx_fifo_head = 0;
642 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
643 adapter->tx_fifo_size =
644 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
645 atomic_set(&adapter->tx_fifo_stall, 0);
646 }
2d7edb92 647
1da177e4
LT		 648 E1000_WRITE_REG(&adapter->hw, PBA, pba);
649
650 /* flow control settings */
f11b7f85
JK		 651 /* Set the FC high water mark to 90% of the FIFO size.
652 * Required to clear last 3 LSB */
653 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
cd94dd0b
AK		 654 /* We can't use 90% on small FIFOs because the remainder
655 * would be less than 1 full frame. In this case, we size
656 * it to allow at least a full frame above the high water
657 * mark. */
658 if (pba < E1000_PBA_16K)
659 fc_high_water_mark = (pba * 1024) - 1600;
f11b7f85
JK		 660
661 adapter->hw.fc_high_water = fc_high_water_mark;
662 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 663 if (adapter->hw.mac_type == e1000_80003es2lan)
664 adapter->hw.fc_pause_time = 0xFFFF;
665 else
666 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 667 adapter->hw.fc_send_xon = 1;
668 adapter->hw.fc = adapter->hw.original_fc;
669
2d7edb92 670 /* Allow time for pending master requests to run */
1da177e4 671 e1000_reset_hw(&adapter->hw);
96838a40 672 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 673 E1000_WRITE_REG(&adapter->hw, WUC, 0);
09ae3e88 674
96838a40 675 if (e1000_init_hw(&adapter->hw))
1da177e4 676 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 677 e1000_update_mng_vlan(adapter);
1da177e4
LT		 678 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
679 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
680
681 e1000_reset_adaptive(&adapter->hw);
682 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
9a53a202
AK		 683
684 if (!adapter->smart_power_down &&
685 (adapter->hw.mac_type == e1000_82571 ||
686 adapter->hw.mac_type == e1000_82572)) {
687 uint16_t phy_data = 0;
688 /* speed up time to link by disabling smart power down, ignore
689 * the return value of this function because there is nothing
690 * different we would do if it failed */
691 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
692 &phy_data);
693 phy_data &= ~IGP02E1000_PM_SPD;
694 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
695 phy_data);
696 }
697
4ccc12ae
JB		 698 if ((adapter->en_mng_pt) &&
699 (adapter->hw.mac_type >= e1000_82540) &&
700 (adapter->hw.mac_type < e1000_82571) &&
701 (adapter->hw.media_type == e1000_media_type_copper)) {
2d7edb92
MC		 702 manc = E1000_READ_REG(&adapter->hw, MANC);
703 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
704 E1000_WRITE_REG(&adapter->hw, MANC, manc);
705 }
1da177e4
LT		 706}
707
708/**
709 * e1000_probe - Device Initialization Routine
710 * @pdev: PCI device information struct
711 * @ent: entry in e1000_pci_tbl
712 *
713 * Returns 0 on success, negative on failure
714 *
715 * e1000_probe initializes an adapter identified by a pci_dev structure.
716 * The OS initialization, configuring of the adapter private structure,
717 * and a hardware reset occur.
718 **/
719
720static int __devinit
721e1000_probe(struct pci_dev *pdev,
722 const struct pci_device_id *ent)
723{
724 struct net_device *netdev;
725 struct e1000_adapter *adapter;
2d7edb92 726 unsigned long mmio_start, mmio_len;
cd94dd0b 727 unsigned long flash_start, flash_len;
2d7edb92 728
1da177e4 729 static int cards_found = 0;
120cd576 730 static int global_quad_port_a = 0; /* global ksp3 port a indication */
2d7edb92 731 int i, err, pci_using_dac;
120cd576 732 uint16_t eeprom_data = 0;
1da177e4 733 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 734 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 735 return err;
736
cd94dd0b
AK		 737 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
738 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 739 pci_using_dac = 1;
740 } else {
cd94dd0b
AK		 741 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
742 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4 743 E1000_ERR("No usable DMA configuration, aborting\n");
6dd62ab0 744 goto err_dma;
1da177e4
LT		 745 }
746 pci_using_dac = 0;
747 }
748
96838a40 749 if ((err = pci_request_regions(pdev, e1000_driver_name)))
6dd62ab0 750 goto err_pci_reg;
1da177e4
LT		 751
752 pci_set_master(pdev);
753
6dd62ab0 754 err = -ENOMEM;
1da177e4 755 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6dd62ab0 756 if (!netdev)
1da177e4 757 goto err_alloc_etherdev;
1da177e4
LT		 758
759 SET_MODULE_OWNER(netdev);
760 SET_NETDEV_DEV(netdev, &pdev->dev);
761
762 pci_set_drvdata(pdev, netdev);
60490fe0 763 adapter = netdev_priv(netdev);
1da177e4
LT		 764 adapter->netdev = netdev;
765 adapter->pdev = pdev;
766 adapter->hw.back = adapter;
767 adapter->msg_enable = (1 << debug) - 1;
768
769 mmio_start = pci_resource_start(pdev, BAR_0);
770 mmio_len = pci_resource_len(pdev, BAR_0);
771
6dd62ab0 772 err = -EIO;
1da177e4 773 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6dd62ab0 774 if (!adapter->hw.hw_addr)
1da177e4 775 goto err_ioremap;
1da177e4 776
96838a40
JB		 777 for (i = BAR_1; i <= BAR_5; i++) {
778 if (pci_resource_len(pdev, i) == 0)
1da177e4 779 continue;
96838a40 780 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 781 adapter->hw.io_base = pci_resource_start(pdev, i);
782 break;
783 }
784 }
785
786 netdev->open = &e1000_open;
787 netdev->stop = &e1000_close;
788 netdev->hard_start_xmit = &e1000_xmit_frame;
789 netdev->get_stats = &e1000_get_stats;
790 netdev->set_multicast_list = &e1000_set_multi;
791 netdev->set_mac_address = &e1000_set_mac;
792 netdev->change_mtu = &e1000_change_mtu;
793 netdev->do_ioctl = &e1000_ioctl;
794 e1000_set_ethtool_ops(netdev);
795 netdev->tx_timeout = &e1000_tx_timeout;
796 netdev->watchdog_timeo = 5 * HZ;
797#ifdef CONFIG_E1000_NAPI
798 netdev->poll = &e1000_clean;
799 netdev->weight = 64;
800#endif
801 netdev->vlan_rx_register = e1000_vlan_rx_register;
802 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
803 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
804#ifdef CONFIG_NET_POLL_CONTROLLER
805 netdev->poll_controller = e1000_netpoll;
806#endif
0eb5a34c 807 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1da177e4
LT		 808
809 netdev->mem_start = mmio_start;
810 netdev->mem_end = mmio_start + mmio_len;
811 netdev->base_addr = adapter->hw.io_base;
812
813 adapter->bd_number = cards_found;
814
815 /* setup the private structure */
816
96838a40 817 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 818 goto err_sw_init;
819
6dd62ab0 820 err = -EIO;
cd94dd0b
AK		 821 /* Flash BAR mapping must happen after e1000_sw_init
822 * because it depends on mac_type */
823 if ((adapter->hw.mac_type == e1000_ich8lan) &&
824 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
825 flash_start = pci_resource_start(pdev, 1);
826 flash_len = pci_resource_len(pdev, 1);
827 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6dd62ab0 828 if (!adapter->hw.flash_address)
cd94dd0b 829 goto err_flashmap;
cd94dd0b
AK		 830 }
831
6dd62ab0 832 if (e1000_check_phy_reset_block(&adapter->hw))
2d7edb92
MC		 833 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
834
96838a40 835 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 836 netdev->features = NETIF_F_SG |
837 NETIF_F_HW_CSUM |
838 NETIF_F_HW_VLAN_TX |
839 NETIF_F_HW_VLAN_RX |
840 NETIF_F_HW_VLAN_FILTER;
cd94dd0b
AK		 841 if (adapter->hw.mac_type == e1000_ich8lan)
842 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
1da177e4
LT		 843 }
844
845#ifdef NETIF_F_TSO
96838a40 846 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 847 (adapter->hw.mac_type != e1000_82547))
848 netdev->features |= NETIF_F_TSO;
2d7edb92 849
87ca4e5b 850#ifdef NETIF_F_TSO6
96838a40 851 if (adapter->hw.mac_type > e1000_82547_rev_2)
87ca4e5b 852 netdev->features |= NETIF_F_TSO6;
2d7edb92 853#endif
1da177e4 854#endif
96838a40 855 if (pci_using_dac)
1da177e4
LT		 856 netdev->features |= NETIF_F_HIGHDMA;
857
76c224bc
AK		 858 netdev->features |= NETIF_F_LLTX;
859
2d7edb92
MC		 860 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
861
cd94dd0b
AK		 862 /* initialize eeprom parameters */
863
864 if (e1000_init_eeprom_params(&adapter->hw)) {
865 E1000_ERR("EEPROM initialization failed\n");
6dd62ab0 866 goto err_eeprom;
cd94dd0b
AK		 867 }
868
96838a40 869 /* before reading the EEPROM, reset the controller to
1da177e4 870 * put the device in a known good starting state */
96838a40 871
1da177e4
LT		 872 e1000_reset_hw(&adapter->hw);
873
874 /* make sure the EEPROM is good */
875
96838a40 876 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4 877 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
1da177e4
LT		 878 goto err_eeprom;
879 }
880
881 /* copy the MAC address out of the EEPROM */
882
96838a40 883 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 884 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
885 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 886 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 887
96838a40 888 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4 889 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
1da177e4
LT		 890 goto err_eeprom;
891 }
892
1da177e4
LT		 893 e1000_get_bus_info(&adapter->hw);
894
895 init_timer(&adapter->tx_fifo_stall_timer);
896 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
897 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
898
899 init_timer(&adapter->watchdog_timer);
900 adapter->watchdog_timer.function = &e1000_watchdog;
901 adapter->watchdog_timer.data = (unsigned long) adapter;
902
1da177e4
LT		 903 init_timer(&adapter->phy_info_timer);
904 adapter->phy_info_timer.function = &e1000_update_phy_info;
905 adapter->phy_info_timer.data = (unsigned long) adapter;
906
87041639
JK		 907 INIT_WORK(&adapter->reset_task,
908 (void (*)(void *))e1000_reset_task, netdev);
1da177e4 909
1da177e4
LT		 910 e1000_check_options(adapter);
911
912 /* Initial Wake on LAN setting
913 * If APM wake is enabled in the EEPROM,
914 * enable the ACPI Magic Packet filter
915 */
916
96838a40 917 switch (adapter->hw.mac_type) {
1da177e4
LT		 918 case e1000_82542_rev2_0:
919 case e1000_82542_rev2_1:
920 case e1000_82543:
921 break;
922 case e1000_82544:
923 e1000_read_eeprom(&adapter->hw,
924 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
925 eeprom_apme_mask = E1000_EEPROM_82544_APM;
926 break;
cd94dd0b
AK		 927 case e1000_ich8lan:
928 e1000_read_eeprom(&adapter->hw,
929 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
930 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
931 break;
1da177e4
LT		 932 case e1000_82546:
933 case e1000_82546_rev_3:
fd803241 934 case e1000_82571:
6418ecc6 935 case e1000_80003es2lan:
96838a40 936 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 937 e1000_read_eeprom(&adapter->hw,
938 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
939 break;
940 }
941 /* Fall Through */
942 default:
943 e1000_read_eeprom(&adapter->hw,
944 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
945 break;
946 }
96838a40 947 if (eeprom_data & eeprom_apme_mask)
120cd576
JB		 948 adapter->eeprom_wol |= E1000_WUFC_MAG;
949
950 /* now that we have the eeprom settings, apply the special cases
951 * where the eeprom may be wrong or the board simply won't support
952 * wake on lan on a particular port */
953 switch (pdev->device) {
954 case E1000_DEV_ID_82546GB_PCIE:
955 adapter->eeprom_wol = 0;
956 break;
957 case E1000_DEV_ID_82546EB_FIBER:
958 case E1000_DEV_ID_82546GB_FIBER:
959 case E1000_DEV_ID_82571EB_FIBER:
960 /* Wake events only supported on port A for dual fiber
961 * regardless of eeprom setting */
962 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
963 adapter->eeprom_wol = 0;
964 break;
965 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
5881cde8 966 case E1000_DEV_ID_82571EB_QUAD_COPPER:
fc2307d0 967 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
120cd576
JB		 968 /* if quad port adapter, disable WoL on all but port A */
969 if (global_quad_port_a != 0)
970 adapter->eeprom_wol = 0;
971 else
972 adapter->quad_port_a = 1;
973 /* Reset for multiple quad port adapters */
974 if (++global_quad_port_a == 4)
975 global_quad_port_a = 0;
976 break;
977 }
978
979 /* initialize the wol settings based on the eeprom settings */
980 adapter->wol = adapter->eeprom_wol;
1da177e4 981
fb3d47d4
JK		 982 /* print bus type/speed/width info */
983 {
984 struct e1000_hw *hw = &adapter->hw;
985 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
986 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
987 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
988 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
989 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
990 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
991 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
992 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
993 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
994 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
995 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
996 "32-bit"));
997 }
998
999 for (i = 0; i < 6; i++)
1000 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
1001
1da177e4
LT		 1002 /* reset the hardware with the new settings */
1003 e1000_reset(adapter);
1004
b55ccb35
JK		 1005 /* If the controller is 82573 and f/w is AMT, do not set
1006 * DRV_LOAD until the interface is up. For all other cases,
1007 * let the f/w know that the h/w is now under the control
1008 * of the driver. */
1009 if (adapter->hw.mac_type != e1000_82573 ||
1010 !e1000_check_mng_mode(&adapter->hw))
1011 e1000_get_hw_control(adapter);
2d7edb92 1012
1da177e4 1013 strcpy(netdev->name, "eth%d");
96838a40 1014 if ((err = register_netdev(netdev)))
1da177e4
LT		 1015 goto err_register;
1016
1314bbf3
AK		 1017 /* tell the stack to leave us alone until e1000_open() is called */
1018 netif_carrier_off(netdev);
1019 netif_stop_queue(netdev);
1020
1da177e4
LT		 1021 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
1022
1023 cards_found++;
1024 return 0;
1025
1026err_register:
6dd62ab0
VA		 1027 e1000_release_hw_control(adapter);
1028err_eeprom:
1029 if (!e1000_check_phy_reset_block(&adapter->hw))
1030 e1000_phy_hw_reset(&adapter->hw);
1031
cd94dd0b
AK		 1032 if (adapter->hw.flash_address)
1033 iounmap(adapter->hw.flash_address);
1034err_flashmap:
6dd62ab0
VA		 1035#ifdef CONFIG_E1000_NAPI
1036 for (i = 0; i < adapter->num_rx_queues; i++)
1037 dev_put(&adapter->polling_netdev[i]);
1038#endif
1039
1040 kfree(adapter->tx_ring);
1041 kfree(adapter->rx_ring);
1042#ifdef CONFIG_E1000_NAPI
1043 kfree(adapter->polling_netdev);
1044#endif
1da177e4 1045err_sw_init:
1da177e4
LT		 1046 iounmap(adapter->hw.hw_addr);
1047err_ioremap:
1048 free_netdev(netdev);
1049err_alloc_etherdev:
1050 pci_release_regions(pdev);
6dd62ab0
VA		 1051err_pci_reg:
1052err_dma:
1053 pci_disable_device(pdev);
1da177e4
LT		 1054 return err;
1055}
1056
1057/**
1058 * e1000_remove - Device Removal Routine
1059 * @pdev: PCI device information struct
1060 *
1061 * e1000_remove is called by the PCI subsystem to alert the driver
1062 * that it should release a PCI device. The could be caused by a
1063 * Hot-Plug event, or because the driver is going to be removed from
1064 * memory.
1065 **/
1066
1067static void __devexit
1068e1000_remove(struct pci_dev *pdev)
1069{
1070 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 1071 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 1072 uint32_t manc;
581d708e
MC		 1073#ifdef CONFIG_E1000_NAPI
1074 int i;
1075#endif
1da177e4 1076
be2b28ed
JG		 1077 flush_scheduled_work();
1078
4ccc12ae
JB		 1079 if (adapter->hw.mac_type >= e1000_82540 &&
1080 adapter->hw.mac_type < e1000_82571 &&
1081 adapter->hw.media_type == e1000_media_type_copper) {
1da177e4 1082 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 1083 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 1084 manc |= E1000_MANC_ARP_EN;
1085 E1000_WRITE_REG(&adapter->hw, MANC, manc);
1086 }
1087 }
1088
b55ccb35
JK		 1089 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1090 * would have already happened in close and is redundant. */
1091 e1000_release_hw_control(adapter);
2d7edb92 1092
1da177e4 1093 unregister_netdev(netdev);
581d708e 1094#ifdef CONFIG_E1000_NAPI
f56799ea 1095 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 1096 dev_put(&adapter->polling_netdev[i]);
581d708e 1097#endif
1da177e4 1098
96838a40 1099 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 1100 e1000_phy_hw_reset(&adapter->hw);
1da177e4 1101
24025e4e
MC		 1102 kfree(adapter->tx_ring);
1103 kfree(adapter->rx_ring);
1104#ifdef CONFIG_E1000_NAPI
1105 kfree(adapter->polling_netdev);
1106#endif
1107
1da177e4 1108 iounmap(adapter->hw.hw_addr);
cd94dd0b
AK		 1109 if (adapter->hw.flash_address)
1110 iounmap(adapter->hw.flash_address);
1da177e4
LT		 1111 pci_release_regions(pdev);
1112
1113 free_netdev(netdev);
1114
1115 pci_disable_device(pdev);
1116}
1117
1118/**
1119 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
1120 * @adapter: board private structure to initialize
1121 *
1122 * e1000_sw_init initializes the Adapter private data structure.
1123 * Fields are initialized based on PCI device information and
1124 * OS network device settings (MTU size).
1125 **/
1126
1127static int __devinit
1128e1000_sw_init(struct e1000_adapter *adapter)
1129{
1130 struct e1000_hw *hw = &adapter->hw;
1131 struct net_device *netdev = adapter->netdev;
1132 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 1133#ifdef CONFIG_E1000_NAPI
1134 int i;
1135#endif
1da177e4
LT		 1136
1137 /* PCI config space info */
1138
1139 hw->vendor_id = pdev->vendor;
1140 hw->device_id = pdev->device;
1141 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1142 hw->subsystem_id = pdev->subsystem_device;
1143
1144 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
1145
1146 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
1147
eb0f8054 1148 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9e2feace 1149 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 1150 hw->max_frame_size = netdev->mtu +
1151 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1152 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
1153
1154 /* identify the MAC */
1155
96838a40 1156 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 1157 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
1158 return -EIO;
1159 }
1160
96838a40 1161 switch (hw->mac_type) {
1da177e4
LT		 1162 default:
1163 break;
1164 case e1000_82541:
1165 case e1000_82547:
1166 case e1000_82541_rev_2:
1167 case e1000_82547_rev_2:
1168 hw->phy_init_script = 1;
1169 break;
1170 }
1171
1172 e1000_set_media_type(hw);
1173
1174 hw->wait_autoneg_complete = FALSE;
1175 hw->tbi_compatibility_en = TRUE;
1176 hw->adaptive_ifs = TRUE;
1177
1178 /* Copper options */
1179
96838a40 1180 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1181 hw->mdix = AUTO_ALL_MODES;
1182 hw->disable_polarity_correction = FALSE;
1183 hw->master_slave = E1000_MASTER_SLAVE;
1184 }
1185
f56799ea
JK		 1186 adapter->num_tx_queues = 1;
1187 adapter->num_rx_queues = 1;
581d708e
MC		 1188
1189 if (e1000_alloc_queues(adapter)) {
1190 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1191 return -ENOMEM;
1192 }
1193
1194#ifdef CONFIG_E1000_NAPI
f56799ea 1195 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1196 adapter->polling_netdev[i].priv = adapter;
1197 adapter->polling_netdev[i].poll = &e1000_clean;
1198 adapter->polling_netdev[i].weight = 64;
1199 dev_hold(&adapter->polling_netdev[i]);
1200 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1201 }
7bfa4816 1202 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1203#endif
1204
1da177e4
LT		 1205 atomic_set(&adapter->irq_sem, 1);
1206 spin_lock_init(&adapter->stats_lock);
1da177e4 1207
1314bbf3
AK		 1208 set_bit(__E1000_DOWN, &adapter->flags);
1209
1da177e4
LT		 1210 return 0;
1211}
1212
581d708e
MC		 1213/**
1214 * e1000_alloc_queues - Allocate memory for all rings
1215 * @adapter: board private structure to initialize
1216 *
1217 * We allocate one ring per queue at run-time since we don't know the
1218 * number of queues at compile-time. The polling_netdev array is
1219 * intended for Multiqueue, but should work fine with a single queue.
1220 **/
1221
1222static int __devinit
1223e1000_alloc_queues(struct e1000_adapter *adapter)
1224{
1225 int size;
1226
f56799ea 1227 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1228 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1229 if (!adapter->tx_ring)
1230 return -ENOMEM;
1231 memset(adapter->tx_ring, 0, size);
1232
f56799ea 1233 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1234 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1235 if (!adapter->rx_ring) {
1236 kfree(adapter->tx_ring);
1237 return -ENOMEM;
1238 }
1239 memset(adapter->rx_ring, 0, size);
1240
1241#ifdef CONFIG_E1000_NAPI
f56799ea 1242 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1243 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1244 if (!adapter->polling_netdev) {
1245 kfree(adapter->tx_ring);
1246 kfree(adapter->rx_ring);
1247 return -ENOMEM;
1248 }
1249 memset(adapter->polling_netdev, 0, size);
1250#endif
1251
1252 return E1000_SUCCESS;
1253}
1254
1da177e4
LT		 1255/**
1256 * e1000_open - Called when a network interface is made active
1257 * @netdev: network interface device structure
1258 *
1259 * Returns 0 on success, negative value on failure
1260 *
1261 * The open entry point is called when a network interface is made
1262 * active by the system (IFF_UP). At this point all resources needed
1263 * for transmit and receive operations are allocated, the interrupt
1264 * handler is registered with the OS, the watchdog timer is started,
1265 * and the stack is notified that the interface is ready.
1266 **/
1267
1268static int
1269e1000_open(struct net_device *netdev)
1270{
60490fe0 1271 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1272 int err;
1273
2db10a08 1274 /* disallow open during test */
1314bbf3 1275 if (test_bit(__E1000_TESTING, &adapter->flags))
2db10a08
AK		 1276 return -EBUSY;
1277
1da177e4 1278 /* allocate transmit descriptors */
581d708e 1279 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1280 goto err_setup_tx;
1281
1282 /* allocate receive descriptors */
581d708e 1283 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1284 goto err_setup_rx;
1285
2db10a08
AK		 1286 err = e1000_request_irq(adapter);
1287 if (err)
401a552b 1288 goto err_req_irq;
2db10a08 1289
79f05bf0
AK		 1290 e1000_power_up_phy(adapter);
1291
96838a40 1292 if ((err = e1000_up(adapter)))
1da177e4 1293 goto err_up;
2d7edb92 1294 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1295 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1296 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1297 e1000_update_mng_vlan(adapter);
1298 }
1da177e4 1299
b55ccb35
JK		 1300 /* If AMT is enabled, let the firmware know that the network
1301 * interface is now open */
1302 if (adapter->hw.mac_type == e1000_82573 &&
1303 e1000_check_mng_mode(&adapter->hw))
1304 e1000_get_hw_control(adapter);
1305
1da177e4
LT		 1306 return E1000_SUCCESS;
1307
1308err_up:
401a552b
VA		 1309 e1000_power_down_phy(adapter);
1310 e1000_free_irq(adapter);
1311err_req_irq:
581d708e 1312 e1000_free_all_rx_resources(adapter);
1da177e4 1313err_setup_rx:
581d708e 1314 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1315err_setup_tx:
1316 e1000_reset(adapter);
1317
1318 return err;
1319}
1320
1321/**
1322 * e1000_close - Disables a network interface
1323 * @netdev: network interface device structure
1324 *
1325 * Returns 0, this is not allowed to fail
1326 *
1327 * The close entry point is called when an interface is de-activated
1328 * by the OS. The hardware is still under the drivers control, but
1329 * needs to be disabled. A global MAC reset is issued to stop the
1330 * hardware, and all transmit and receive resources are freed.
1331 **/
1332
1333static int
1334e1000_close(struct net_device *netdev)
1335{
60490fe0 1336 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 1337
2db10a08 1338 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 1339 e1000_down(adapter);
79f05bf0 1340 e1000_power_down_phy(adapter);
2db10a08 1341 e1000_free_irq(adapter);
1da177e4 1342
581d708e
MC		 1343 e1000_free_all_tx_resources(adapter);
1344 e1000_free_all_rx_resources(adapter);
1da177e4 1345
4666560a
BA		 1346 /* kill manageability vlan ID if supported, but not if a vlan with
1347 * the same ID is registered on the host OS (let 8021q kill it) */
96838a40 1348 if ((adapter->hw.mng_cookie.status &
4666560a
BA		 1349 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
1350 !(adapter->vlgrp &&
1351 adapter->vlgrp->vlan_devices[adapter->mng_vlan_id])) {
2d7edb92
MC		 1352 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1353 }
b55ccb35
JK		 1354
1355 /* If AMT is enabled, let the firmware know that the network
1356 * interface is now closed */
1357 if (adapter->hw.mac_type == e1000_82573 &&
1358 e1000_check_mng_mode(&adapter->hw))
1359 e1000_release_hw_control(adapter);
1360
1da177e4
LT		 1361 return 0;
1362}
1363
1364/**
1365 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1366 * @adapter: address of board private structure
2d7edb92
MC		 1367 * @start: address of beginning of memory
1368 * @len: length of memory
1da177e4 1369 **/
e619d523 1370static boolean_t
1da177e4
LT		 1371e1000_check_64k_bound(struct e1000_adapter *adapter,
1372 void *start, unsigned long len)
1373{
1374 unsigned long begin = (unsigned long) start;
1375 unsigned long end = begin + len;
1376
2648345f
MC		 1377 /* First rev 82545 and 82546 need to not allow any memory
1378 * write location to cross 64k boundary due to errata 23 */
1da177e4 1379 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1380 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1381 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1382 }
1383
1384 return TRUE;
1385}
1386
1387/**
1388 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1389 * @adapter: board private structure
581d708e 1390 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1391 *
1392 * Return 0 on success, negative on failure
1393 **/
1394
3ad2cc67 1395static int
581d708e
MC		 1396e1000_setup_tx_resources(struct e1000_adapter *adapter,
1397 struct e1000_tx_ring *txdr)
1da177e4 1398{
1da177e4
LT		 1399 struct pci_dev *pdev = adapter->pdev;
1400 int size;
1401
1402 size = sizeof(struct e1000_buffer) * txdr->count;
cd94dd0b 1403 txdr->buffer_info = vmalloc(size);
96838a40 1404 if (!txdr->buffer_info) {
2648345f
MC		 1405 DPRINTK(PROBE, ERR,
1406 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1407 return -ENOMEM;
1408 }
1409 memset(txdr->buffer_info, 0, size);
1410
1411 /* round up to nearest 4K */
1412
1413 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1414 E1000_ROUNDUP(txdr->size, 4096);
1415
1416 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1417 if (!txdr->desc) {
1da177e4 1418setup_tx_desc_die:
1da177e4 1419 vfree(txdr->buffer_info);
2648345f
MC		 1420 DPRINTK(PROBE, ERR,
1421 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1422 return -ENOMEM;
1423 }
1424
2648345f 1425 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1426 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1427 void *olddesc = txdr->desc;
1428 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1429 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1430 "at %p\n", txdr->size, txdr->desc);
1431 /* Try again, without freeing the previous */
1da177e4 1432 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1433 /* Failed allocation, critical failure */
96838a40 1434 if (!txdr->desc) {
1da177e4
LT		 1435 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1436 goto setup_tx_desc_die;
1437 }
1438
1439 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1440 /* give up */
2648345f
MC		 1441 pci_free_consistent(pdev, txdr->size, txdr->desc,
1442 txdr->dma);
1da177e4
LT		 1443 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1444 DPRINTK(PROBE, ERR,
2648345f
MC		 1445 "Unable to allocate aligned memory "
1446 "for the transmit descriptor ring\n");
1da177e4
LT		 1447 vfree(txdr->buffer_info);
1448 return -ENOMEM;
1449 } else {
2648345f 1450 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1451 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1452 }
1453 }
1454 memset(txdr->desc, 0, txdr->size);
1455
1456 txdr->next_to_use = 0;
1457 txdr->next_to_clean = 0;
2ae76d98 1458 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1459
1460 return 0;
1461}
1462
581d708e
MC		 1463/**
1464 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1465 * (Descriptors) for all queues
1466 * @adapter: board private structure
1467 *
581d708e
MC		 1468 * Return 0 on success, negative on failure
1469 **/
1470
1471int
1472e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1473{
1474 int i, err = 0;
1475
f56799ea 1476 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1477 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1478 if (err) {
1479 DPRINTK(PROBE, ERR,
1480 "Allocation for Tx Queue %u failed\n", i);
3fbbc72e
VA		 1481 for (i-- ; i >= 0; i--)
1482 e1000_free_tx_resources(adapter,
1483 &adapter->tx_ring[i]);
581d708e
MC		 1484 break;
1485 }
1486 }
1487
1488 return err;
1489}
1490
1da177e4
LT		 1491/**
1492 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1493 * @adapter: board private structure
1494 *
1495 * Configure the Tx unit of the MAC after a reset.
1496 **/
1497
1498static void
1499e1000_configure_tx(struct e1000_adapter *adapter)
1500{
581d708e
MC		 1501 uint64_t tdba;
1502 struct e1000_hw *hw = &adapter->hw;
1503 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1504 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1505
1506 /* Setup the HW Tx Head and Tail descriptor pointers */
1507
f56799ea 1508 switch (adapter->num_tx_queues) {
24025e4e
MC		 1509 case 1:
1510 default:
581d708e
MC		 1511 tdba = adapter->tx_ring[0].dma;
1512 tdlen = adapter->tx_ring[0].count *
1513 sizeof(struct e1000_tx_desc);
581d708e 1514 E1000_WRITE_REG(hw, TDLEN, tdlen);
4ca213a6
AK		 1515 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1516 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
581d708e 1517 E1000_WRITE_REG(hw, TDT, 0);
4ca213a6 1518 E1000_WRITE_REG(hw, TDH, 0);
6a951698
AK		 1519 adapter->tx_ring[0].tdh = ((hw->mac_type >= e1000_82543) ? E1000_TDH : E1000_82542_TDH);
1520 adapter->tx_ring[0].tdt = ((hw->mac_type >= e1000_82543) ? E1000_TDT : E1000_82542_TDT);
24025e4e
MC		 1521 break;
1522 }
1da177e4
LT		 1523
1524 /* Set the default values for the Tx Inter Packet Gap timer */
1525
0fadb059
JK		 1526 if (hw->media_type == e1000_media_type_fiber ||
1527 hw->media_type == e1000_media_type_internal_serdes)
1528 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1529 else
1530 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1531
581d708e 1532 switch (hw->mac_type) {
1da177e4
LT		 1533 case e1000_82542_rev2_0:
1534 case e1000_82542_rev2_1:
1535 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1536 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1537 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1538 break;
87041639
JK		 1539 case e1000_80003es2lan:
1540 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1541 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1542 break;
1da177e4 1543 default:
0fadb059
JK		 1544 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1545 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1546 break;
1da177e4 1547 }
0fadb059
JK		 1548 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1549 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1550 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1551
1552 /* Set the Tx Interrupt Delay register */
1553
581d708e
MC		 1554 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1555 if (hw->mac_type >= e1000_82540)
1556 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1557
1558 /* Program the Transmit Control Register */
1559
581d708e 1560 tctl = E1000_READ_REG(hw, TCTL);
1da177e4 1561 tctl &= ~E1000_TCTL_CT;
7e6c9861 1562 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1563 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1564
2ae76d98
MC		 1565 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1566 tarc = E1000_READ_REG(hw, TARC0);
90fb5135
AK		 1567 /* set the speed mode bit, we'll clear it if we're not at
1568 * gigabit link later */
09ae3e88 1569 tarc |= (1 << 21);
2ae76d98 1570 E1000_WRITE_REG(hw, TARC0, tarc);
87041639
JK		 1571 } else if (hw->mac_type == e1000_80003es2lan) {
1572 tarc = E1000_READ_REG(hw, TARC0);
1573 tarc |= 1;
87041639
JK		 1574 E1000_WRITE_REG(hw, TARC0, tarc);
1575 tarc = E1000_READ_REG(hw, TARC1);
1576 tarc |= 1;
1577 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1578 }
1579
581d708e 1580 e1000_config_collision_dist(hw);
1da177e4
LT		 1581
1582 /* Setup Transmit Descriptor Settings for eop descriptor */
6a042dab
JB		 1583 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
1584
1585 /* only set IDE if we are delaying interrupts using the timers */
1586 if (adapter->tx_int_delay)
1587 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
1da177e4 1588
581d708e 1589 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1590 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1591 else
1592 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1593
1594 /* Cache if we're 82544 running in PCI-X because we'll
1595 * need this to apply a workaround later in the send path. */
581d708e
MC		 1596 if (hw->mac_type == e1000_82544 &&
1597 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1598 adapter->pcix_82544 = 1;
7e6c9861
JK		 1599
1600 E1000_WRITE_REG(hw, TCTL, tctl);
1601
1da177e4
LT		 1602}
1603
1604/**
1605 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1606 * @adapter: board private structure
581d708e 1607 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1608 *
1609 * Returns 0 on success, negative on failure
1610 **/
1611
3ad2cc67 1612static int
581d708e
MC		 1613e1000_setup_rx_resources(struct e1000_adapter *adapter,
1614 struct e1000_rx_ring *rxdr)
1da177e4 1615{
1da177e4 1616 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1617 int size, desc_len;
1da177e4
LT		 1618
1619 size = sizeof(struct e1000_buffer) * rxdr->count;
cd94dd0b 1620 rxdr->buffer_info = vmalloc(size);
581d708e 1621 if (!rxdr->buffer_info) {
2648345f
MC		 1622 DPRINTK(PROBE, ERR,
1623 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1624 return -ENOMEM;
1625 }
1626 memset(rxdr->buffer_info, 0, size);
1627
2d7edb92
MC		 1628 size = sizeof(struct e1000_ps_page) * rxdr->count;
1629 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
96838a40 1630 if (!rxdr->ps_page) {
2d7edb92
MC		 1631 vfree(rxdr->buffer_info);
1632 DPRINTK(PROBE, ERR,
1633 "Unable to allocate memory for the receive descriptor ring\n");
1634 return -ENOMEM;
1635 }
1636 memset(rxdr->ps_page, 0, size);
1637
1638 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1639 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
96838a40 1640 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1641 vfree(rxdr->buffer_info);
1642 kfree(rxdr->ps_page);
1643 DPRINTK(PROBE, ERR,
1644 "Unable to allocate memory for the receive descriptor ring\n");
1645 return -ENOMEM;
1646 }
1647 memset(rxdr->ps_page_dma, 0, size);
1648
96838a40 1649 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1650 desc_len = sizeof(struct e1000_rx_desc);
1651 else
1652 desc_len = sizeof(union e1000_rx_desc_packet_split);
1653
1da177e4
LT		 1654 /* Round up to nearest 4K */
1655
2d7edb92 1656 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1657 E1000_ROUNDUP(rxdr->size, 4096);
1658
1659 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1660
581d708e
MC		 1661 if (!rxdr->desc) {
1662 DPRINTK(PROBE, ERR,
1663 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1664setup_rx_desc_die:
1da177e4 1665 vfree(rxdr->buffer_info);
2d7edb92
MC		 1666 kfree(rxdr->ps_page);
1667 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1668 return -ENOMEM;
1669 }
1670
2648345f 1671 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1672 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1673 void *olddesc = rxdr->desc;
1674 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1675 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1676 "at %p\n", rxdr->size, rxdr->desc);
1677 /* Try again, without freeing the previous */
1da177e4 1678 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1679 /* Failed allocation, critical failure */
581d708e 1680 if (!rxdr->desc) {
1da177e4 1681 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1682 DPRINTK(PROBE, ERR,
1683 "Unable to allocate memory "
1684 "for the receive descriptor ring\n");
1da177e4
LT		 1685 goto setup_rx_desc_die;
1686 }
1687
1688 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1689 /* give up */
2648345f
MC		 1690 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1691 rxdr->dma);
1da177e4 1692 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1693 DPRINTK(PROBE, ERR,
1694 "Unable to allocate aligned memory "
1695 "for the receive descriptor ring\n");
581d708e 1696 goto setup_rx_desc_die;
1da177e4 1697 } else {
2648345f 1698 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1699 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1700 }
1701 }
1702 memset(rxdr->desc, 0, rxdr->size);
1703
1704 rxdr->next_to_clean = 0;
1705 rxdr->next_to_use = 0;
1706
1707 return 0;
1708}
1709
581d708e
MC		 1710/**
1711 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1712 * (Descriptors) for all queues
1713 * @adapter: board private structure
1714 *
581d708e
MC		 1715 * Return 0 on success, negative on failure
1716 **/
1717
1718int
1719e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1720{
1721 int i, err = 0;
1722
f56799ea 1723 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1724 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1725 if (err) {
1726 DPRINTK(PROBE, ERR,
1727 "Allocation for Rx Queue %u failed\n", i);
3fbbc72e
VA		 1728 for (i-- ; i >= 0; i--)
1729 e1000_free_rx_resources(adapter,
1730 &adapter->rx_ring[i]);
581d708e
MC		 1731 break;
1732 }
1733 }
1734
1735 return err;
1736}
1737
1da177e4 1738/**
2648345f 1739 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1740 * @adapter: Board private structure
1741 **/
e4c811c9
MC		 1742#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1743 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1744static void
1745e1000_setup_rctl(struct e1000_adapter *adapter)
1746{
2d7edb92
MC		 1747 uint32_t rctl, rfctl;
1748 uint32_t psrctl = 0;
35ec56bb 1749#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1750 uint32_t pages = 0;
1751#endif
1da177e4
LT		 1752
1753 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1754
1755 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1756
1757 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1758 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1759 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1760
0fadb059 1761 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1762 rctl |= E1000_RCTL_SBP;
1763 else
1764 rctl &= ~E1000_RCTL_SBP;
1765
2d7edb92
MC		 1766 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1767 rctl &= ~E1000_RCTL_LPE;
1768 else
1769 rctl |= E1000_RCTL_LPE;
1770
1da177e4 1771 /* Setup buffer sizes */
9e2feace
AK		 1772 rctl &= ~E1000_RCTL_SZ_4096;
1773 rctl |= E1000_RCTL_BSEX;
1774 switch (adapter->rx_buffer_len) {
1775 case E1000_RXBUFFER_256:
1776 rctl |= E1000_RCTL_SZ_256;
1777 rctl &= ~E1000_RCTL_BSEX;
1778 break;
1779 case E1000_RXBUFFER_512:
1780 rctl |= E1000_RCTL_SZ_512;
1781 rctl &= ~E1000_RCTL_BSEX;
1782 break;
1783 case E1000_RXBUFFER_1024:
1784 rctl |= E1000_RCTL_SZ_1024;
1785 rctl &= ~E1000_RCTL_BSEX;
1786 break;
a1415ee6
JK		 1787 case E1000_RXBUFFER_2048:
1788 default:
1789 rctl |= E1000_RCTL_SZ_2048;
1790 rctl &= ~E1000_RCTL_BSEX;
1791 break;
1792 case E1000_RXBUFFER_4096:
1793 rctl |= E1000_RCTL_SZ_4096;
1794 break;
1795 case E1000_RXBUFFER_8192:
1796 rctl |= E1000_RCTL_SZ_8192;
1797 break;
1798 case E1000_RXBUFFER_16384:
1799 rctl |= E1000_RCTL_SZ_16384;
1800 break;
2d7edb92
MC		 1801 }
1802
35ec56bb 1803#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1804 /* 82571 and greater support packet-split where the protocol
1805 * header is placed in skb->data and the packet data is
1806 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1807 * In the case of a non-split, skb->data is linearly filled,
1808 * followed by the page buffers. Therefore, skb->data is
1809 * sized to hold the largest protocol header.
1810 */
e64d7d02
JB		 1811 /* allocations using alloc_page take too long for regular MTU
1812 * so only enable packet split for jumbo frames */
e4c811c9 1813 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
e64d7d02
JB		 1814 if ((adapter->hw.mac_type >= e1000_82571) && (pages <= 3) &&
1815 PAGE_SIZE <= 16384 && (rctl & E1000_RCTL_LPE))
e4c811c9
MC		 1816 adapter->rx_ps_pages = pages;
1817 else
1818 adapter->rx_ps_pages = 0;
2d7edb92 1819#endif
e4c811c9 1820 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1821 /* Configure extra packet-split registers */
1822 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1823 rfctl |= E1000_RFCTL_EXTEN;
87ca4e5b
AK		 1824 /* disable packet split support for IPv6 extension headers,
1825 * because some malformed IPv6 headers can hang the RX */
1826 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
1827 E1000_RFCTL_NEW_IPV6_EXT_DIS);
1828
2d7edb92
MC		 1829 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1830
7dfee0cb 1831 rctl |= E1000_RCTL_DTYP_PS;
96838a40 1832
2d7edb92
MC		 1833 psrctl |= adapter->rx_ps_bsize0 >>
1834 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1835
1836 switch (adapter->rx_ps_pages) {
1837 case 3:
1838 psrctl |= PAGE_SIZE <<
1839 E1000_PSRCTL_BSIZE3_SHIFT;
1840 case 2:
1841 psrctl |= PAGE_SIZE <<
1842 E1000_PSRCTL_BSIZE2_SHIFT;
1843 case 1:
1844 psrctl |= PAGE_SIZE >>
1845 E1000_PSRCTL_BSIZE1_SHIFT;
1846 break;
1847 }
2d7edb92
MC		 1848
1849 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1850 }
1851
1852 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1853}
1854
1855/**
1856 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1857 * @adapter: board private structure
1858 *
1859 * Configure the Rx unit of the MAC after a reset.
1860 **/
1861
1862static void
1863e1000_configure_rx(struct e1000_adapter *adapter)
1864{
581d708e
MC		 1865 uint64_t rdba;
1866 struct e1000_hw *hw = &adapter->hw;
1867 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 1868
e4c811c9 1869 if (adapter->rx_ps_pages) {
0f15a8fa 1870 /* this is a 32 byte descriptor */
581d708e 1871 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1872 sizeof(union e1000_rx_desc_packet_split);
1873 adapter->clean_rx = e1000_clean_rx_irq_ps;
1874 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1875 } else {
581d708e
MC		 1876 rdlen = adapter->rx_ring[0].count *
1877 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1878 adapter->clean_rx = e1000_clean_rx_irq;
1879 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1880 }
1da177e4
LT		 1881
1882 /* disable receives while setting up the descriptors */
581d708e
MC		 1883 rctl = E1000_READ_REG(hw, RCTL);
1884 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1885
1886 /* set the Receive Delay Timer Register */
581d708e 1887 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1888
581d708e
MC		 1889 if (hw->mac_type >= e1000_82540) {
1890 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
96838a40 1891 if (adapter->itr > 1)
581d708e 1892 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1893 1000000000 / (adapter->itr * 256));
1894 }
1895
2ae76d98 1896 if (hw->mac_type >= e1000_82571) {
2ae76d98 1897 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1898 /* Reset delay timers after every interrupt */
6fc7a7ec 1899 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9
JK		 1900#ifdef CONFIG_E1000_NAPI
1901 /* Auto-Mask interrupts upon ICR read. */
1902 ctrl_ext |= E1000_CTRL_EXT_IAME;
1903#endif
2ae76d98 1904 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1905 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1906 E1000_WRITE_FLUSH(hw);
1907 }
1908
581d708e
MC		 1909 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1910 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1911 switch (adapter->num_rx_queues) {
24025e4e
MC		 1912 case 1:
1913 default:
581d708e 1914 rdba = adapter->rx_ring[0].dma;
581d708e 1915 E1000_WRITE_REG(hw, RDLEN, rdlen);
4ca213a6
AK		 1916 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1917 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
581d708e 1918 E1000_WRITE_REG(hw, RDT, 0);
4ca213a6 1919 E1000_WRITE_REG(hw, RDH, 0);
6a951698
AK		 1920 adapter->rx_ring[0].rdh = ((hw->mac_type >= e1000_82543) ? E1000_RDH : E1000_82542_RDH);
1921 adapter->rx_ring[0].rdt = ((hw->mac_type >= e1000_82543) ? E1000_RDT : E1000_82542_RDT);
581d708e 1922 break;
24025e4e
MC		 1923 }
1924
1da177e4 1925 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1926 if (hw->mac_type >= e1000_82543) {
1927 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 1928 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 1929 rxcsum |= E1000_RXCSUM_TUOFL;
1930
868d5309 1931 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1932 * Must be used in conjunction with packet-split. */
96838a40
JB		 1933 if ((hw->mac_type >= e1000_82571) &&
1934 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1935 rxcsum |= E1000_RXCSUM_IPPCSE;
1936 }
1937 } else {
1938 rxcsum &= ~E1000_RXCSUM_TUOFL;
1939 /* don't need to clear IPPCSE as it defaults to 0 */
1940 }
581d708e 1941 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 1942 }
1943
21c4d5e0
AK		 1944 /* enable early receives on 82573, only takes effect if using > 2048
1945 * byte total frame size. for example only for jumbo frames */
1946#define E1000_ERT_2048 0x100
1947 if (hw->mac_type == e1000_82573)
1948 E1000_WRITE_REG(hw, ERT, E1000_ERT_2048);
1949
1da177e4 1950 /* Enable Receives */
581d708e 1951 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1952}
1953
1954/**
581d708e 1955 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1956 * @adapter: board private structure
581d708e 1957 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1958 *
1959 * Free all transmit software resources
1960 **/
1961
3ad2cc67 1962static void
581d708e
MC		 1963e1000_free_tx_resources(struct e1000_adapter *adapter,
1964 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1965{
1966 struct pci_dev *pdev = adapter->pdev;
1967
581d708e 1968 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1969
581d708e
MC		 1970 vfree(tx_ring->buffer_info);
1971 tx_ring->buffer_info = NULL;
1da177e4 1972
581d708e 1973 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1974
581d708e
MC		 1975 tx_ring->desc = NULL;
1976}
1977
1978/**
1979 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1980 * @adapter: board private structure
1981 *
1982 * Free all transmit software resources
1983 **/
1984
1985void
1986e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1987{
1988 int i;
1989
f56799ea 1990 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1991 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1992}
1993
e619d523 1994static void
1da177e4
LT		 1995e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1996 struct e1000_buffer *buffer_info)
1997{
96838a40 1998 if (buffer_info->dma) {
2648345f
MC		 1999 pci_unmap_page(adapter->pdev,
2000 buffer_info->dma,
2001 buffer_info->length,
2002 PCI_DMA_TODEVICE);
a9ebadd6 2003 buffer_info->dma = 0;
1da177e4 2004 }
a9ebadd6 2005 if (buffer_info->skb) {
1da177e4 2006 dev_kfree_skb_any(buffer_info->skb);
a9ebadd6
JB		 2007 buffer_info->skb = NULL;
2008 }
2009 /* buffer_info must be completely set up in the transmit path */
1da177e4
LT		 2010}
2011
2012/**
2013 * e1000_clean_tx_ring - Free Tx Buffers
2014 * @adapter: board private structure
581d708e 2015 * @tx_ring: ring to be cleaned
1da177e4
LT		 2016 **/
2017
2018static void
581d708e
MC		 2019e1000_clean_tx_ring(struct e1000_adapter *adapter,
2020 struct e1000_tx_ring *tx_ring)
1da177e4 2021{
1da177e4
LT		 2022 struct e1000_buffer *buffer_info;
2023 unsigned long size;
2024 unsigned int i;
2025
2026 /* Free all the Tx ring sk_buffs */
2027
96838a40 2028 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 2029 buffer_info = &tx_ring->buffer_info[i];
2030 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
2031 }
2032
2033 size = sizeof(struct e1000_buffer) * tx_ring->count;
2034 memset(tx_ring->buffer_info, 0, size);
2035
2036 /* Zero out the descriptor ring */
2037
2038 memset(tx_ring->desc, 0, tx_ring->size);
2039
2040 tx_ring->next_to_use = 0;
2041 tx_ring->next_to_clean = 0;
fd803241 2042 tx_ring->last_tx_tso = 0;
1da177e4 2043
581d708e
MC		 2044 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
2045 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
2046}
2047
2048/**
2049 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
2050 * @adapter: board private structure
2051 **/
2052
2053static void
2054e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
2055{
2056 int i;
2057
f56799ea 2058 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2059 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2060}
2061
2062/**
2063 * e1000_free_rx_resources - Free Rx Resources
2064 * @adapter: board private structure
581d708e 2065 * @rx_ring: ring to clean the resources from
1da177e4
LT		 2066 *
2067 * Free all receive software resources
2068 **/
2069
3ad2cc67 2070static void
581d708e
MC		 2071e1000_free_rx_resources(struct e1000_adapter *adapter,
2072 struct e1000_rx_ring *rx_ring)
1da177e4 2073{
1da177e4
LT		 2074 struct pci_dev *pdev = adapter->pdev;
2075
581d708e 2076 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 2077
2078 vfree(rx_ring->buffer_info);
2079 rx_ring->buffer_info = NULL;
2d7edb92
MC		 2080 kfree(rx_ring->ps_page);
2081 rx_ring->ps_page = NULL;
2082 kfree(rx_ring->ps_page_dma);
2083 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 2084
2085 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2086
2087 rx_ring->desc = NULL;
2088}
2089
2090/**
581d708e 2091 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2092 * @adapter: board private structure
581d708e
MC		 2093 *
2094 * Free all receive software resources
2095 **/
2096
2097void
2098e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2099{
2100 int i;
2101
f56799ea 2102 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2103 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2104}
2105
2106/**
2107 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2108 * @adapter: board private structure
2109 * @rx_ring: ring to free buffers from
1da177e4
LT		 2110 **/
2111
2112static void
581d708e
MC		 2113e1000_clean_rx_ring(struct e1000_adapter *adapter,
2114 struct e1000_rx_ring *rx_ring)
1da177e4 2115{
1da177e4 2116 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2117 struct e1000_ps_page *ps_page;
2118 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2119 struct pci_dev *pdev = adapter->pdev;
2120 unsigned long size;
2d7edb92 2121 unsigned int i, j;
1da177e4
LT		 2122
2123 /* Free all the Rx ring sk_buffs */
96838a40 2124 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2125 buffer_info = &rx_ring->buffer_info[i];
96838a40 2126 if (buffer_info->skb) {
1da177e4
LT		 2127 pci_unmap_single(pdev,
2128 buffer_info->dma,
2129 buffer_info->length,
2130 PCI_DMA_FROMDEVICE);
2131
2132 dev_kfree_skb(buffer_info->skb);
2133 buffer_info->skb = NULL;
997f5cbd
JK		 2134 }
2135 ps_page = &rx_ring->ps_page[i];
2136 ps_page_dma = &rx_ring->ps_page_dma[i];
2137 for (j = 0; j < adapter->rx_ps_pages; j++) {
2138 if (!ps_page->ps_page[j]) break;
2139 pci_unmap_page(pdev,
2140 ps_page_dma->ps_page_dma[j],
2141 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2142 ps_page_dma->ps_page_dma[j] = 0;
2143 put_page(ps_page->ps_page[j]);
2144 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2145 }
2146 }
2147
2148 size = sizeof(struct e1000_buffer) * rx_ring->count;
2149 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2150 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2151 memset(rx_ring->ps_page, 0, size);
2152 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2153 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2154
2155 /* Zero out the descriptor ring */
2156
2157 memset(rx_ring->desc, 0, rx_ring->size);
2158
2159 rx_ring->next_to_clean = 0;
2160 rx_ring->next_to_use = 0;
2161
581d708e
MC		 2162 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2163 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2164}
2165
2166/**
2167 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2168 * @adapter: board private structure
2169 **/
2170
2171static void
2172e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2173{
2174 int i;
2175
f56799ea 2176 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2177 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2178}
2179
2180/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2181 * and memory write and invalidate disabled for certain operations
2182 */
2183static void
2184e1000_enter_82542_rst(struct e1000_adapter *adapter)
2185{
2186 struct net_device *netdev = adapter->netdev;
2187 uint32_t rctl;
2188
2189 e1000_pci_clear_mwi(&adapter->hw);
2190
2191 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2192 rctl |= E1000_RCTL_RST;
2193 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2194 E1000_WRITE_FLUSH(&adapter->hw);
2195 mdelay(5);
2196
96838a40 2197 if (netif_running(netdev))
581d708e 2198 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2199}
2200
2201static void
2202e1000_leave_82542_rst(struct e1000_adapter *adapter)
2203{
2204 struct net_device *netdev = adapter->netdev;
2205 uint32_t rctl;
2206
2207 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2208 rctl &= ~E1000_RCTL_RST;
2209 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2210 E1000_WRITE_FLUSH(&adapter->hw);
2211 mdelay(5);
2212
96838a40 2213 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2214 e1000_pci_set_mwi(&adapter->hw);
2215
96838a40 2216 if (netif_running(netdev)) {
72d64a43
JK		 2217 /* No need to loop, because 82542 supports only 1 queue */
2218 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2219 e1000_configure_rx(adapter);
72d64a43 2220 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2221 }
2222}
2223
2224/**
2225 * e1000_set_mac - Change the Ethernet Address of the NIC
2226 * @netdev: network interface device structure
2227 * @p: pointer to an address structure
2228 *
2229 * Returns 0 on success, negative on failure
2230 **/
2231
2232static int
2233e1000_set_mac(struct net_device *netdev, void *p)
2234{
60490fe0 2235 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2236 struct sockaddr *addr = p;
2237
96838a40 2238 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2239 return -EADDRNOTAVAIL;
2240
2241 /* 82542 2.0 needs to be in reset to write receive address registers */
2242
96838a40 2243 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2244 e1000_enter_82542_rst(adapter);
2245
2246 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2247 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2248
2249 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2250
868d5309
MC		 2251 /* With 82571 controllers, LAA may be overwritten (with the default)
2252 * due to controller reset from the other port. */
2253 if (adapter->hw.mac_type == e1000_82571) {
2254 /* activate the work around */
2255 adapter->hw.laa_is_present = 1;
2256
96838a40
JB		 2257 /* Hold a copy of the LAA in RAR[14] This is done so that
2258 * between the time RAR[0] gets clobbered and the time it
2259 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2260 * of the RARs and no incoming packets directed to this port
96838a40 2261 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2262 * RAR[14] */
96838a40 2263 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2264 E1000_RAR_ENTRIES - 1);
2265 }
2266
96838a40 2267 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2268 e1000_leave_82542_rst(adapter);
2269
2270 return 0;
2271}
2272
2273/**
2274 * e1000_set_multi - Multicast and Promiscuous mode set
2275 * @netdev: network interface device structure
2276 *
2277 * The set_multi entry point is called whenever the multicast address
2278 * list or the network interface flags are updated. This routine is
2279 * responsible for configuring the hardware for proper multicast,
2280 * promiscuous mode, and all-multi behavior.
2281 **/
2282
2283static void
2284e1000_set_multi(struct net_device *netdev)
2285{
60490fe0 2286 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2287 struct e1000_hw *hw = &adapter->hw;
2288 struct dev_mc_list *mc_ptr;
2289 uint32_t rctl;
2290 uint32_t hash_value;
868d5309 2291 int i, rar_entries = E1000_RAR_ENTRIES;
cd94dd0b
AK		 2292 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2293 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2294 E1000_NUM_MTA_REGISTERS;
2295
2296 if (adapter->hw.mac_type == e1000_ich8lan)
2297 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
1da177e4 2298
868d5309
MC		 2299 /* reserve RAR[14] for LAA over-write work-around */
2300 if (adapter->hw.mac_type == e1000_82571)
2301 rar_entries--;
1da177e4 2302
2648345f
MC		 2303 /* Check for Promiscuous and All Multicast modes */
2304
1da177e4
LT		 2305 rctl = E1000_READ_REG(hw, RCTL);
2306
96838a40 2307 if (netdev->flags & IFF_PROMISC) {
1da177e4 2308 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2309 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2310 rctl |= E1000_RCTL_MPE;
2311 rctl &= ~E1000_RCTL_UPE;
2312 } else {
2313 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2314 }
2315
2316 E1000_WRITE_REG(hw, RCTL, rctl);
2317
2318 /* 82542 2.0 needs to be in reset to write receive address registers */
2319
96838a40 2320 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2321 e1000_enter_82542_rst(adapter);
2322
2323 /* load the first 14 multicast address into the exact filters 1-14
2324 * RAR 0 is used for the station MAC adddress
2325 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2326 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2327 */
2328 mc_ptr = netdev->mc_list;
2329
96838a40 2330 for (i = 1; i < rar_entries; i++) {
868d5309 2331 if (mc_ptr) {
1da177e4
LT		 2332 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2333 mc_ptr = mc_ptr->next;
2334 } else {
2335 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
4ca213a6 2336 E1000_WRITE_FLUSH(hw);
1da177e4 2337 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
4ca213a6 2338 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 2339 }
2340 }
2341
2342 /* clear the old settings from the multicast hash table */
2343
cd94dd0b 2344 for (i = 0; i < mta_reg_count; i++) {
1da177e4 2345 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 2346 E1000_WRITE_FLUSH(hw);
2347 }
1da177e4
LT		 2348
2349 /* load any remaining addresses into the hash table */
2350
96838a40 2351 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2352 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2353 e1000_mta_set(hw, hash_value);
2354 }
2355
96838a40 2356 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2357 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2358}
2359
2360/* Need to wait a few seconds after link up to get diagnostic information from
2361 * the phy */
2362
2363static void
2364e1000_update_phy_info(unsigned long data)
2365{
2366 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2367 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2368}
2369
2370/**
2371 * e1000_82547_tx_fifo_stall - Timer Call-back
2372 * @data: pointer to adapter cast into an unsigned long
2373 **/
2374
2375static void
2376e1000_82547_tx_fifo_stall(unsigned long data)
2377{
2378 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2379 struct net_device *netdev = adapter->netdev;
2380 uint32_t tctl;
2381
96838a40
JB		 2382 if (atomic_read(&adapter->tx_fifo_stall)) {
2383 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2384 E1000_READ_REG(&adapter->hw, TDH)) &&
2385 (E1000_READ_REG(&adapter->hw, TDFT) ==
2386 E1000_READ_REG(&adapter->hw, TDFH)) &&
2387 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2388 E1000_READ_REG(&adapter->hw, TDFHS))) {
2389 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2390 E1000_WRITE_REG(&adapter->hw, TCTL,
2391 tctl & ~E1000_TCTL_EN);
2392 E1000_WRITE_REG(&adapter->hw, TDFT,
2393 adapter->tx_head_addr);
2394 E1000_WRITE_REG(&adapter->hw, TDFH,
2395 adapter->tx_head_addr);
2396 E1000_WRITE_REG(&adapter->hw, TDFTS,
2397 adapter->tx_head_addr);
2398 E1000_WRITE_REG(&adapter->hw, TDFHS,
2399 adapter->tx_head_addr);
2400 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2401 E1000_WRITE_FLUSH(&adapter->hw);
2402
2403 adapter->tx_fifo_head = 0;
2404 atomic_set(&adapter->tx_fifo_stall, 0);
2405 netif_wake_queue(netdev);
2406 } else {
2407 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2408 }
2409 }
2410}
2411
2412/**
2413 * e1000_watchdog - Timer Call-back
2414 * @data: pointer to adapter cast into an unsigned long
2415 **/
2416static void
2417e1000_watchdog(unsigned long data)
2418{
2419 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1da177e4 2420 struct net_device *netdev = adapter->netdev;
545c67c0 2421 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2422 uint32_t link, tctl;
cd94dd0b
AK		 2423 int32_t ret_val;
2424
2425 ret_val = e1000_check_for_link(&adapter->hw);
2426 if ((ret_val == E1000_ERR_PHY) &&
2427 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2428 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2429 /* See e1000_kumeran_lock_loss_workaround() */
2430 DPRINTK(LINK, INFO,
2431 "Gigabit has been disabled, downgrading speed\n");
2432 }
90fb5135 2433
2d7edb92
MC		 2434 if (adapter->hw.mac_type == e1000_82573) {
2435 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2436 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2437 e1000_update_mng_vlan(adapter);
96838a40 2438 }
1da177e4 2439
96838a40 2440 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2441 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2442 link = !adapter->hw.serdes_link_down;
2443 else
2444 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2445
96838a40
JB		 2446 if (link) {
2447 if (!netif_carrier_ok(netdev)) {
fe7fe28e 2448 boolean_t txb2b = 1;
1da177e4
LT		 2449 e1000_get_speed_and_duplex(&adapter->hw,
2450 &adapter->link_speed,
2451 &adapter->link_duplex);
2452
2453 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2454 adapter->link_speed,
2455 adapter->link_duplex == FULL_DUPLEX ?
2456 "Full Duplex" : "Half Duplex");
2457
7e6c9861
JK		 2458 /* tweak tx_queue_len according to speed/duplex
2459 * and adjust the timeout factor */
66a2b0a3
JK		 2460 netdev->tx_queue_len = adapter->tx_queue_len;
2461 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2462 switch (adapter->link_speed) {
2463 case SPEED_10:
fe7fe28e 2464 txb2b = 0;
7e6c9861
JK		 2465 netdev->tx_queue_len = 10;
2466 adapter->tx_timeout_factor = 8;
2467 break;
2468 case SPEED_100:
fe7fe28e 2469 txb2b = 0;
7e6c9861
JK		 2470 netdev->tx_queue_len = 100;
2471 /* maybe add some timeout factor ? */
2472 break;
2473 }
2474
fe7fe28e 2475 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2476 adapter->hw.mac_type == e1000_82572) &&
fe7fe28e 2477 txb2b == 0) {
7e6c9861
JK		 2478 uint32_t tarc0;
2479 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
90fb5135 2480 tarc0 &= ~(1 << 21);
7e6c9861
JK		 2481 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2482 }
90fb5135 2483
7e6c9861
JK		 2484#ifdef NETIF_F_TSO
2485 /* disable TSO for pcie and 10/100 speeds, to avoid
2486 * some hardware issues */
2487 if (!adapter->tso_force &&
2488 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2489 switch (adapter->link_speed) {
2490 case SPEED_10:
66a2b0a3 2491 case SPEED_100:
7e6c9861
JK		 2492 DPRINTK(PROBE,INFO,
2493 "10/100 speed: disabling TSO\n");
2494 netdev->features &= ~NETIF_F_TSO;
87ca4e5b
AK		 2495#ifdef NETIF_F_TSO6
2496 netdev->features &= ~NETIF_F_TSO6;
2497#endif
7e6c9861
JK		 2498 break;
2499 case SPEED_1000:
2500 netdev->features |= NETIF_F_TSO;
87ca4e5b
AK		 2501#ifdef NETIF_F_TSO6
2502 netdev->features |= NETIF_F_TSO6;
2503#endif
7e6c9861
JK		 2504 break;
2505 default:
2506 /* oops */
66a2b0a3
JK		 2507 break;
2508 }
2509 }
7e6c9861
JK		 2510#endif
2511
2512 /* enable transmits in the hardware, need to do this
2513 * after setting TARC0 */
2514 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2515 tctl |= E1000_TCTL_EN;
2516 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2517
1da177e4
LT		 2518 netif_carrier_on(netdev);
2519 netif_wake_queue(netdev);
2520 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2521 adapter->smartspeed = 0;
2522 }
2523 } else {
96838a40 2524 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2525 adapter->link_speed = 0;
2526 adapter->link_duplex = 0;
2527 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2528 netif_carrier_off(netdev);
2529 netif_stop_queue(netdev);
2530 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
87041639
JK		 2531
2532 /* 80003ES2LAN workaround--
2533 * For packet buffer work-around on link down event;
2534 * disable receives in the ISR and
2535 * reset device here in the watchdog
2536 */
8fc897b0 2537 if (adapter->hw.mac_type == e1000_80003es2lan)
87041639
JK		 2538 /* reset device */
2539 schedule_work(&adapter->reset_task);
1da177e4
LT		 2540 }
2541
2542 e1000_smartspeed(adapter);
2543 }
2544
2545 e1000_update_stats(adapter);
2546
2547 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2548 adapter->tpt_old = adapter->stats.tpt;
2549 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2550 adapter->colc_old = adapter->stats.colc;
2551
2552 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2553 adapter->gorcl_old = adapter->stats.gorcl;
2554 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2555 adapter->gotcl_old = adapter->stats.gotcl;
2556
2557 e1000_update_adaptive(&adapter->hw);
2558
f56799ea 2559 if (!netif_carrier_ok(netdev)) {
581d708e 2560 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2561 /* We've lost link, so the controller stops DMA,
2562 * but we've got queued Tx work that's never going
2563 * to get done, so reset controller to flush Tx.
2564 * (Do the reset outside of interrupt context). */
87041639
JK		 2565 adapter->tx_timeout_count++;
2566 schedule_work(&adapter->reset_task);
1da177e4
LT		 2567 }
2568 }
2569
2570 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
96838a40 2571 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1da177e4
LT		 2572 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2573 * asymmetrical Tx or Rx gets ITR=8000; everyone
2574 * else is between 2000-8000. */
2575 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
96838a40 2576 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1da177e4
LT		 2577 adapter->gotcl - adapter->gorcl :
2578 adapter->gorcl - adapter->gotcl) / 10000;
2579 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2580 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2581 }
2582
2583 /* Cause software interrupt to ensure rx ring is cleaned */
2584 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2585
2648345f 2586 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2587 adapter->detect_tx_hung = TRUE;
2588
96838a40 2589 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2590 * reset from the other port. Set the appropriate LAA in RAR[0] */
2591 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2592 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2593
1da177e4
LT		 2594 /* Reset the timer */
2595 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2596}
2597
2598#define E1000_TX_FLAGS_CSUM 0x00000001
2599#define E1000_TX_FLAGS_VLAN 0x00000002
2600#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2601#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2602#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2603#define E1000_TX_FLAGS_VLAN_SHIFT 16
2604
e619d523 2605static int
581d708e
MC		 2606e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2607 struct sk_buff *skb)
1da177e4
LT		 2608{
2609#ifdef NETIF_F_TSO
2610 struct e1000_context_desc *context_desc;
545c67c0 2611 struct e1000_buffer *buffer_info;
1da177e4
LT		 2612 unsigned int i;
2613 uint32_t cmd_length = 0;
2d7edb92 2614 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2615 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2616 int err;
2617
89114afd 2618 if (skb_is_gso(skb)) {
1da177e4
LT		 2619 if (skb_header_cloned(skb)) {
2620 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2621 if (err)
2622 return err;
2623 }
2624
2625 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
7967168c 2626 mss = skb_shinfo(skb)->gso_size;
60828236 2627 if (skb->protocol == htons(ETH_P_IP)) {
2d7edb92
MC		 2628 skb->nh.iph->tot_len = 0;
2629 skb->nh.iph->check = 0;
2630 skb->h.th->check =
2631 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2632 skb->nh.iph->daddr,
2633 0,
2634 IPPROTO_TCP,
2635 0);
2636 cmd_length = E1000_TXD_CMD_IP;
2637 ipcse = skb->h.raw - skb->data - 1;
87ca4e5b 2638#ifdef NETIF_F_TSO6
e15fdd03 2639 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2d7edb92
MC		 2640 skb->nh.ipv6h->payload_len = 0;
2641 skb->h.th->check =
2642 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2643 &skb->nh.ipv6h->daddr,
2644 0,
2645 IPPROTO_TCP,
2646 0);
2647 ipcse = 0;
2648#endif
2649 }
1da177e4
LT		 2650 ipcss = skb->nh.raw - skb->data;
2651 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2652 tucss = skb->h.raw - skb->data;
2653 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2654 tucse = 0;
2655
2656 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2657 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2658
581d708e
MC		 2659 i = tx_ring->next_to_use;
2660 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2661 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2662
2663 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2664 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2665 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2666 context_desc->upper_setup.tcp_fields.tucss = tucss;
2667 context_desc->upper_setup.tcp_fields.tucso = tucso;
2668 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2669 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2670 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2671 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2672
545c67c0 2673 buffer_info->time_stamp = jiffies;
a9ebadd6 2674 buffer_info->next_to_watch = i;
545c67c0 2675
581d708e
MC		 2676 if (++i == tx_ring->count) i = 0;
2677 tx_ring->next_to_use = i;
1da177e4 2678
8241e35e 2679 return TRUE;
1da177e4
LT		 2680 }
2681#endif
2682
8241e35e 2683 return FALSE;
1da177e4
LT		 2684}
2685
e619d523 2686static boolean_t
581d708e
MC		 2687e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2688 struct sk_buff *skb)
1da177e4
LT		 2689{
2690 struct e1000_context_desc *context_desc;
545c67c0 2691 struct e1000_buffer *buffer_info;
1da177e4
LT		 2692 unsigned int i;
2693 uint8_t css;
2694
84fa7933 2695 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1da177e4
LT		 2696 css = skb->h.raw - skb->data;
2697
581d708e 2698 i = tx_ring->next_to_use;
545c67c0 2699 buffer_info = &tx_ring->buffer_info[i];
581d708e 2700 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2701
2702 context_desc->upper_setup.tcp_fields.tucss = css;
2703 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2704 context_desc->upper_setup.tcp_fields.tucse = 0;
2705 context_desc->tcp_seg_setup.data = 0;
2706 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2707
545c67c0 2708 buffer_info->time_stamp = jiffies;
a9ebadd6 2709 buffer_info->next_to_watch = i;
545c67c0 2710
581d708e
MC		 2711 if (unlikely(++i == tx_ring->count)) i = 0;
2712 tx_ring->next_to_use = i;
1da177e4
LT		 2713
2714 return TRUE;
2715 }
2716
2717 return FALSE;
2718}
2719
2720#define E1000_MAX_TXD_PWR 12
2721#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2722
e619d523 2723static int
581d708e
MC		 2724e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2725 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2726 unsigned int nr_frags, unsigned int mss)
1da177e4 2727{
1da177e4
LT		 2728 struct e1000_buffer *buffer_info;
2729 unsigned int len = skb->len;
2730 unsigned int offset = 0, size, count = 0, i;
2731 unsigned int f;
2732 len -= skb->data_len;
2733
2734 i = tx_ring->next_to_use;
2735
96838a40 2736 while (len) {
1da177e4
LT		 2737 buffer_info = &tx_ring->buffer_info[i];
2738 size = min(len, max_per_txd);
2739#ifdef NETIF_F_TSO
fd803241
JK		 2740 /* Workaround for Controller erratum --
2741 * descriptor for non-tso packet in a linear SKB that follows a
2742 * tso gets written back prematurely before the data is fully
0f15a8fa 2743 * DMA'd to the controller */
fd803241 2744 if (!skb->data_len && tx_ring->last_tx_tso &&
89114afd 2745 !skb_is_gso(skb)) {
fd803241
JK		 2746 tx_ring->last_tx_tso = 0;
2747 size -= 4;
2748 }
2749
1da177e4
LT		 2750 /* Workaround for premature desc write-backs
2751 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2752 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4
LT		 2753 size -= 4;
2754#endif
97338bde
MC		 2755 /* work-around for errata 10 and it applies
2756 * to all controllers in PCI-X mode
2757 * The fix is to make sure that the first descriptor of a
2758 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2759 */
96838a40 2760 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2761 (size > 2015) && count == 0))
2762 size = 2015;
96838a40 2763
1da177e4
LT		 2764 /* Workaround for potential 82544 hang in PCI-X. Avoid
2765 * terminating buffers within evenly-aligned dwords. */
96838a40 2766 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2767 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2768 size > 4))
2769 size -= 4;
2770
2771 buffer_info->length = size;
2772 buffer_info->dma =
2773 pci_map_single(adapter->pdev,
2774 skb->data + offset,
2775 size,
2776 PCI_DMA_TODEVICE);
2777 buffer_info->time_stamp = jiffies;
a9ebadd6 2778 buffer_info->next_to_watch = i;
1da177e4
LT		 2779
2780 len -= size;
2781 offset += size;
2782 count++;
96838a40 2783 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2784 }
2785
96838a40 2786 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 2787 struct skb_frag_struct *frag;
2788
2789 frag = &skb_shinfo(skb)->frags[f];
2790 len = frag->size;
2791 offset = frag->page_offset;
2792
96838a40 2793 while (len) {
1da177e4
LT		 2794 buffer_info = &tx_ring->buffer_info[i];
2795 size = min(len, max_per_txd);
2796#ifdef NETIF_F_TSO
2797 /* Workaround for premature desc write-backs
2798 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2799 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4
LT		 2800 size -= 4;
2801#endif
2802 /* Workaround for potential 82544 hang in PCI-X.
2803 * Avoid terminating buffers within evenly-aligned
2804 * dwords. */
96838a40 2805 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2806 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2807 size > 4))
2808 size -= 4;
2809
2810 buffer_info->length = size;
2811 buffer_info->dma =
2812 pci_map_page(adapter->pdev,
2813 frag->page,
2814 offset,
2815 size,
2816 PCI_DMA_TODEVICE);
2817 buffer_info->time_stamp = jiffies;
a9ebadd6 2818 buffer_info->next_to_watch = i;
1da177e4
LT		 2819
2820 len -= size;
2821 offset += size;
2822 count++;
96838a40 2823 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2824 }
2825 }
2826
2827 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2828 tx_ring->buffer_info[i].skb = skb;
2829 tx_ring->buffer_info[first].next_to_watch = i;
2830
2831 return count;
2832}
2833
e619d523 2834static void
581d708e
MC		 2835e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2836 int tx_flags, int count)
1da177e4 2837{
1da177e4
LT		 2838 struct e1000_tx_desc *tx_desc = NULL;
2839 struct e1000_buffer *buffer_info;
2840 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2841 unsigned int i;
2842
96838a40 2843 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 2844 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2845 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2846 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2847
96838a40 2848 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 2849 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2850 }
2851
96838a40 2852 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 2853 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2854 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2855 }
2856
96838a40 2857 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 2858 txd_lower |= E1000_TXD_CMD_VLE;
2859 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2860 }
2861
2862 i = tx_ring->next_to_use;
2863
96838a40 2864 while (count--) {
1da177e4
LT		 2865 buffer_info = &tx_ring->buffer_info[i];
2866 tx_desc = E1000_TX_DESC(*tx_ring, i);
2867 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2868 tx_desc->lower.data =
2869 cpu_to_le32(txd_lower | buffer_info->length);
2870 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 2871 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2872 }
2873
2874 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2875
2876 /* Force memory writes to complete before letting h/w
2877 * know there are new descriptors to fetch. (Only
2878 * applicable for weak-ordered memory model archs,
2879 * such as IA-64). */
2880 wmb();
2881
2882 tx_ring->next_to_use = i;
581d708e 2883 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
2ce9047f
JB		 2884 /* we need this if more than one processor can write to our tail
2885 * at a time, it syncronizes IO on IA64/Altix systems */
2886 mmiowb();
1da177e4
LT		 2887}
2888
2889/**
2890 * 82547 workaround to avoid controller hang in half-duplex environment.
2891 * The workaround is to avoid queuing a large packet that would span
2892 * the internal Tx FIFO ring boundary by notifying the stack to resend
2893 * the packet at a later time. This gives the Tx FIFO an opportunity to
2894 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2895 * to the beginning of the Tx FIFO.
2896 **/
2897
2898#define E1000_FIFO_HDR 0x10
2899#define E1000_82547_PAD_LEN 0x3E0
2900
e619d523 2901static int
1da177e4
LT		 2902e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2903{
2904 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2905 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2906
2907 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2908
96838a40 2909 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 2910 goto no_fifo_stall_required;
2911
96838a40 2912 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 2913 return 1;
2914
96838a40 2915 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 2916 atomic_set(&adapter->tx_fifo_stall, 1);
2917 return 1;
2918 }
2919
2920no_fifo_stall_required:
2921 adapter->tx_fifo_head += skb_fifo_len;
96838a40 2922 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 2923 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2924 return 0;
2925}
2926
2d7edb92 2927#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 2928static int
2d7edb92
MC		 2929e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2930{
2931 struct e1000_hw *hw = &adapter->hw;
2932 uint16_t length, offset;
96838a40
JB		 2933 if (vlan_tx_tag_present(skb)) {
2934 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 2935 ( adapter->hw.mng_cookie.status &
2936 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2937 return 0;
2938 }
20a44028 2939 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 2940 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 2941 if ((htons(ETH_P_IP) == eth->h_proto)) {
2942 const struct iphdr *ip =
2d7edb92 2943 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 2944 if (IPPROTO_UDP == ip->protocol) {
2945 struct udphdr *udp =
2946 (struct udphdr *)((uint8_t *)ip +
2d7edb92 2947 (ip->ihl << 2));
96838a40 2948 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 2949 offset = (uint8_t *)udp + 8 - skb->data;
2950 length = skb->len - offset;
2951
2952 return e1000_mng_write_dhcp_info(hw,
96838a40 2953 (uint8_t *)udp + 8,
2d7edb92
MC		 2954 length);
2955 }
2956 }
2957 }
2958 }
2959 return 0;
2960}
2961
65c7973f
JB		 2962static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
2963{
2964 struct e1000_adapter *adapter = netdev_priv(netdev);
2965 struct e1000_tx_ring *tx_ring = adapter->tx_ring;
2966
2967 netif_stop_queue(netdev);
2968 /* Herbert's original patch had:
2969 * smp_mb__after_netif_stop_queue();
2970 * but since that doesn't exist yet, just open code it. */
2971 smp_mb();
2972
2973 /* We need to check again in a case another CPU has just
2974 * made room available. */
2975 if (likely(E1000_DESC_UNUSED(tx_ring) < size))
2976 return -EBUSY;
2977
2978 /* A reprieve! */
2979 netif_start_queue(netdev);
fcfb1224 2980 ++adapter->restart_queue;
65c7973f
JB		 2981 return 0;
2982}
2983
2984static int e1000_maybe_stop_tx(struct net_device *netdev,
2985 struct e1000_tx_ring *tx_ring, int size)
2986{
2987 if (likely(E1000_DESC_UNUSED(tx_ring) >= size))
2988 return 0;
2989 return __e1000_maybe_stop_tx(netdev, size);
2990}
2991
1da177e4
LT		 2992#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2993static int
2994e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2995{
60490fe0 2996 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2997 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2998 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2999 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
3000 unsigned int tx_flags = 0;
3001 unsigned int len = skb->len;
3002 unsigned long flags;
3003 unsigned int nr_frags = 0;
3004 unsigned int mss = 0;
3005 int count = 0;
76c224bc 3006 int tso;
1da177e4
LT		 3007 unsigned int f;
3008 len -= skb->data_len;
3009
65c7973f
JB		 3010 /* This goes back to the question of how to logically map a tx queue
3011 * to a flow. Right now, performance is impacted slightly negatively
3012 * if using multiple tx queues. If the stack breaks away from a
3013 * single qdisc implementation, we can look at this again. */
581d708e 3014 tx_ring = adapter->tx_ring;
24025e4e 3015
581d708e 3016 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 3017 dev_kfree_skb_any(skb);
3018 return NETDEV_TX_OK;
3019 }
3020
032fe6e9
JB		 3021 /* 82571 and newer doesn't need the workaround that limited descriptor
3022 * length to 4kB */
3023 if (adapter->hw.mac_type >= e1000_82571)
3024 max_per_txd = 8192;
3025
1da177e4 3026#ifdef NETIF_F_TSO
7967168c 3027 mss = skb_shinfo(skb)->gso_size;
76c224bc 3028 /* The controller does a simple calculation to
1da177e4
LT		 3029 * make sure there is enough room in the FIFO before
3030 * initiating the DMA for each buffer. The calc is:
3031 * 4 = ceil(buffer len/mss). To make sure we don't
3032 * overrun the FIFO, adjust the max buffer len if mss
3033 * drops. */
96838a40 3034 if (mss) {
9a3056da 3035 uint8_t hdr_len;
1da177e4
LT		 3036 max_per_txd = min(mss << 2, max_per_txd);
3037 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 3038
90fb5135
AK		 3039 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
3040 * points to just header, pull a few bytes of payload from
3041 * frags into skb->data */
9a3056da 3042 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
9f687888
JK		 3043 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
3044 switch (adapter->hw.mac_type) {
3045 unsigned int pull_size;
3046 case e1000_82571:
3047 case e1000_82572:
3048 case e1000_82573:
cd94dd0b 3049 case e1000_ich8lan:
9f687888
JK		 3050 pull_size = min((unsigned int)4, skb->data_len);
3051 if (!__pskb_pull_tail(skb, pull_size)) {
a5eafce2 3052 DPRINTK(DRV, ERR,
9f687888
JK		 3053 "__pskb_pull_tail failed.\n");
3054 dev_kfree_skb_any(skb);
749dfc70 3055 return NETDEV_TX_OK;
9f687888
JK		 3056 }
3057 len = skb->len - skb->data_len;
3058 break;
3059 default:
3060 /* do nothing */
3061 break;
d74bbd3b 3062 }
9a3056da 3063 }
1da177e4
LT		 3064 }
3065
9a3056da 3066 /* reserve a descriptor for the offload context */
84fa7933 3067 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
1da177e4 3068 count++;
2648345f 3069 count++;
1da177e4 3070#else
84fa7933 3071 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 3072 count++;
3073#endif
fd803241
JK		 3074
3075#ifdef NETIF_F_TSO
3076 /* Controller Erratum workaround */
89114afd 3077 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
fd803241
JK		 3078 count++;
3079#endif
3080
1da177e4
LT		 3081 count += TXD_USE_COUNT(len, max_txd_pwr);
3082
96838a40 3083 if (adapter->pcix_82544)
1da177e4
LT		 3084 count++;
3085
96838a40 3086 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 3087 * in PCI-X mode, so add one more descriptor to the count
3088 */
96838a40 3089 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3090 (len > 2015)))
3091 count++;
3092
1da177e4 3093 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 3094 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 3095 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
3096 max_txd_pwr);
96838a40 3097 if (adapter->pcix_82544)
1da177e4
LT		 3098 count += nr_frags;
3099
0f15a8fa
JK		 3100
3101 if (adapter->hw.tx_pkt_filtering &&
3102 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 3103 e1000_transfer_dhcp_info(adapter, skb);
3104
581d708e
MC		 3105 local_irq_save(flags);
3106 if (!spin_trylock(&tx_ring->tx_lock)) {
3107 /* Collision - tell upper layer to requeue */
3108 local_irq_restore(flags);
3109 return NETDEV_TX_LOCKED;
3110 }
1da177e4
LT		 3111
3112 /* need: count + 2 desc gap to keep tail from touching
3113 * head, otherwise try next time */
65c7973f 3114 if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2))) {
581d708e 3115 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3116 return NETDEV_TX_BUSY;
3117 }
3118
96838a40
JB		 3119 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
3120 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4 3121 netif_stop_queue(netdev);
1314bbf3 3122 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
581d708e 3123 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3124 return NETDEV_TX_BUSY;
3125 }
3126 }
3127
96838a40 3128 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 3129 tx_flags |= E1000_TX_FLAGS_VLAN;
3130 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
3131 }
3132
581d708e 3133 first = tx_ring->next_to_use;
96838a40 3134
581d708e 3135 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 3136 if (tso < 0) {
3137 dev_kfree_skb_any(skb);
581d708e 3138 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3139 return NETDEV_TX_OK;
3140 }
3141
fd803241
JK		 3142 if (likely(tso)) {
3143 tx_ring->last_tx_tso = 1;
1da177e4 3144 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 3145 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 3146 tx_flags |= E1000_TX_FLAGS_CSUM;
3147
2d7edb92 3148 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 3149 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 3150 * no longer assume, we must. */
60828236 3151 if (likely(skb->protocol == htons(ETH_P_IP)))
2d7edb92
MC		 3152 tx_flags |= E1000_TX_FLAGS_IPV4;
3153
581d708e
MC		 3154 e1000_tx_queue(adapter, tx_ring, tx_flags,
3155 e1000_tx_map(adapter, tx_ring, skb, first,
3156 max_per_txd, nr_frags, mss));
1da177e4
LT		 3157
3158 netdev->trans_start = jiffies;
3159
3160 /* Make sure there is space in the ring for the next send. */
65c7973f 3161 e1000_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 2);
1da177e4 3162
581d708e 3163 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3164 return NETDEV_TX_OK;
3165}
3166
3167/**
3168 * e1000_tx_timeout - Respond to a Tx Hang
3169 * @netdev: network interface device structure
3170 **/
3171
3172static void
3173e1000_tx_timeout(struct net_device *netdev)
3174{
60490fe0 3175 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3176
3177 /* Do the reset outside of interrupt context */
87041639
JK		 3178 adapter->tx_timeout_count++;
3179 schedule_work(&adapter->reset_task);
1da177e4
LT		 3180}
3181
3182static void
87041639 3183e1000_reset_task(struct net_device *netdev)
1da177e4 3184{
60490fe0 3185 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3186
2db10a08 3187 e1000_reinit_locked(adapter);
1da177e4
LT		 3188}
3189
3190/**
3191 * e1000_get_stats - Get System Network Statistics
3192 * @netdev: network interface device structure
3193 *
3194 * Returns the address of the device statistics structure.
3195 * The statistics are actually updated from the timer callback.
3196 **/
3197
3198static struct net_device_stats *
3199e1000_get_stats(struct net_device *netdev)
3200{
60490fe0 3201 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3202
6b7660cd 3203 /* only return the current stats */
1da177e4
LT		 3204 return &adapter->net_stats;
3205}
3206
3207/**
3208 * e1000_change_mtu - Change the Maximum Transfer Unit
3209 * @netdev: network interface device structure
3210 * @new_mtu: new value for maximum frame size
3211 *
3212 * Returns 0 on success, negative on failure
3213 **/
3214
3215static int
3216e1000_change_mtu(struct net_device *netdev, int new_mtu)
3217{
60490fe0 3218 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3219 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 3220 uint16_t eeprom_data = 0;
1da177e4 3221
96838a40
JB		 3222 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3223 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3224 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3225 return -EINVAL;
2d7edb92 3226 }
1da177e4 3227
997f5cbd
JK		 3228 /* Adapter-specific max frame size limits. */
3229 switch (adapter->hw.mac_type) {
9e2feace 3230 case e1000_undefined ... e1000_82542_rev2_1:
cd94dd0b 3231 case e1000_ich8lan:
997f5cbd
JK		 3232 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3233 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3234 return -EINVAL;
2d7edb92 3235 }
997f5cbd 3236 break;
85b22eb6 3237 case e1000_82573:
249d71d6
BA		 3238 /* Jumbo Frames not supported if:
3239 * - this is not an 82573L device
3240 * - ASPM is enabled in any way (0x1A bits 3:2) */
85b22eb6
JK		 3241 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
3242 &eeprom_data);
249d71d6
BA		 3243 if ((adapter->hw.device_id != E1000_DEV_ID_82573L) ||
3244 (eeprom_data & EEPROM_WORD1A_ASPM_MASK)) {
85b22eb6
JK		 3245 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3246 DPRINTK(PROBE, ERR,
3247 "Jumbo Frames not supported.\n");
3248 return -EINVAL;
3249 }
3250 break;
3251 }
249d71d6
BA		 3252 /* ERT will be enabled later to enable wire speed receives */
3253
85b22eb6 3254 /* fall through to get support */
997f5cbd
JK		 3255 case e1000_82571:
3256 case e1000_82572:
87041639 3257 case e1000_80003es2lan:
997f5cbd
JK		 3258#define MAX_STD_JUMBO_FRAME_SIZE 9234
3259 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3260 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3261 return -EINVAL;
3262 }
3263 break;
3264 default:
3265 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3266 break;
1da177e4
LT		 3267 }
3268
87f5032e 3269 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
9e2feace
AK		 3270 * means we reserve 2 more, this pushes us to allocate from the next
3271 * larger slab size
3272 * i.e. RXBUFFER_2048 --> size-4096 slab */
3273
3274 if (max_frame <= E1000_RXBUFFER_256)
3275 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3276 else if (max_frame <= E1000_RXBUFFER_512)
3277 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3278 else if (max_frame <= E1000_RXBUFFER_1024)
3279 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3280 else if (max_frame <= E1000_RXBUFFER_2048)
3281 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3282 else if (max_frame <= E1000_RXBUFFER_4096)
3283 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3284 else if (max_frame <= E1000_RXBUFFER_8192)
3285 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3286 else if (max_frame <= E1000_RXBUFFER_16384)
3287 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3288
3289 /* adjust allocation if LPE protects us, and we aren't using SBP */
9e2feace
AK		 3290 if (!adapter->hw.tbi_compatibility_on &&
3291 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3292 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3293 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3294
2d7edb92
MC		 3295 netdev->mtu = new_mtu;
3296
2db10a08
AK		 3297 if (netif_running(netdev))
3298 e1000_reinit_locked(adapter);
1da177e4 3299
1da177e4
LT		 3300 adapter->hw.max_frame_size = max_frame;
3301
3302 return 0;
3303}
3304
3305/**
3306 * e1000_update_stats - Update the board statistics counters
3307 * @adapter: board private structure
3308 **/
3309
3310void
3311e1000_update_stats(struct e1000_adapter *adapter)
3312{
3313 struct e1000_hw *hw = &adapter->hw;
282f33c9 3314 struct pci_dev *pdev = adapter->pdev;
1da177e4
LT		 3315 unsigned long flags;
3316 uint16_t phy_tmp;
3317
3318#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3319
282f33c9
LV		 3320 /*
3321 * Prevent stats update while adapter is being reset, or if the pci
3322 * connection is down.
3323 */
9026729b 3324 if (adapter->link_speed == 0)
282f33c9
LV		 3325 return;
3326 if (pdev->error_state && pdev->error_state != pci_channel_io_normal)
9026729b
AK		 3327 return;
3328
1da177e4
LT		 3329 spin_lock_irqsave(&adapter->stats_lock, flags);
3330
3331 /* these counters are modified from e1000_adjust_tbi_stats,
3332 * called from the interrupt context, so they must only
3333 * be written while holding adapter->stats_lock
3334 */
3335
3336 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3337 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3338 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3339 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3340 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3341 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3342 adapter->stats.roc += E1000_READ_REG(hw, ROC);
cd94dd0b
AK		 3343
3344 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3345 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3346 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3347 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3348 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3349 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3350 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
cd94dd0b 3351 }
1da177e4
LT		 3352
3353 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3354 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3355 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3356 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3357 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3358 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3359 adapter->stats.dc += E1000_READ_REG(hw, DC);
3360 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3361 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3362 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3363 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3364 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3365 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3366 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3367 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3368 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3369 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3370 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3371 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3372 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3373 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3374 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3375 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3376 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3377 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3378 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
cd94dd0b
AK		 3379
3380 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3381 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3382 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3383 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3384 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3385 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3386 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 3387 }
3388
1da177e4
LT		 3389 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3390 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3391
3392 /* used for adaptive IFS */
3393
3394 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3395 adapter->stats.tpt += hw->tx_packet_delta;
3396 hw->collision_delta = E1000_READ_REG(hw, COLC);
3397 adapter->stats.colc += hw->collision_delta;
3398
96838a40 3399 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3400 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3401 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3402 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3403 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3404 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3405 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3406 }
96838a40 3407 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3408 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3409 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 3410
3411 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3412 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3413 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3414 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3415 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3416 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3417 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3418 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
cd94dd0b 3419 }
2d7edb92 3420 }
1da177e4
LT		 3421
3422 /* Fill out the OS statistics structure */
1da177e4
LT		 3423 adapter->net_stats.rx_packets = adapter->stats.gprc;
3424 adapter->net_stats.tx_packets = adapter->stats.gptc;
3425 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3426 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3427 adapter->net_stats.multicast = adapter->stats.mprc;
3428 adapter->net_stats.collisions = adapter->stats.colc;
3429
3430 /* Rx Errors */
3431
87041639
JK		 3432 /* RLEC on some newer hardware can be incorrect so build
3433 * our own version based on RUC and ROC */
1da177e4
LT		 3434 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3435 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3436 adapter->stats.ruc + adapter->stats.roc +
3437 adapter->stats.cexterr;
49559854
MW		 3438 adapter->stats.rlerrc = adapter->stats.ruc + adapter->stats.roc;
3439 adapter->net_stats.rx_length_errors = adapter->stats.rlerrc;
1da177e4
LT		 3440 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3441 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3442 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3443
3444 /* Tx Errors */
49559854
MW		 3445 adapter->stats.txerrc = adapter->stats.ecol + adapter->stats.latecol;
3446 adapter->net_stats.tx_errors = adapter->stats.txerrc;
1da177e4
LT		 3447 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3448 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3449 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3450
3451 /* Tx Dropped needs to be maintained elsewhere */
3452
3453 /* Phy Stats */
96838a40
JB		 3454 if (hw->media_type == e1000_media_type_copper) {
3455 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3456 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3457 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3458 adapter->phy_stats.idle_errors += phy_tmp;
3459 }
3460
96838a40 3461 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3462 (hw->phy_type == e1000_phy_m88) &&
3463 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3464 adapter->phy_stats.receive_errors += phy_tmp;
3465 }
3466
3467 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3468}
3469
3470/**
3471 * e1000_intr - Interrupt Handler
3472 * @irq: interrupt number
3473 * @data: pointer to a network interface device structure
1da177e4
LT		 3474 **/
3475
3476static irqreturn_t
7d12e780 3477e1000_intr(int irq, void *data)
1da177e4
LT		 3478{
3479 struct net_device *netdev = data;
60490fe0 3480 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3481 struct e1000_hw *hw = &adapter->hw;
87041639 3482 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3483#ifndef CONFIG_E1000_NAPI
581d708e 3484 int i;
1e613fd9
JK		 3485#else
3486 /* Interrupt Auto-Mask...upon reading ICR,
3487 * interrupts are masked. No need for the
3488 * IMC write, but it does mean we should
3489 * account for it ASAP. */
3490 if (likely(hw->mac_type >= e1000_82571))
3491 atomic_inc(&adapter->irq_sem);
be2b28ed 3492#endif
1da177e4 3493
1e613fd9
JK		 3494 if (unlikely(!icr)) {
3495#ifdef CONFIG_E1000_NAPI
3496 if (hw->mac_type >= e1000_82571)
3497 e1000_irq_enable(adapter);
3498#endif
1da177e4 3499 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3500 }
1da177e4 3501
96838a40 3502 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3503 hw->get_link_status = 1;
87041639
JK		 3504 /* 80003ES2LAN workaround--
3505 * For packet buffer work-around on link down event;
3506 * disable receives here in the ISR and
3507 * reset adapter in watchdog
3508 */
3509 if (netif_carrier_ok(netdev) &&
3510 (adapter->hw.mac_type == e1000_80003es2lan)) {
3511 /* disable receives */
3512 rctl = E1000_READ_REG(hw, RCTL);
3513 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3514 }
1314bbf3
AK		 3515 /* guard against interrupt when we're going down */
3516 if (!test_bit(__E1000_DOWN, &adapter->flags))
3517 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1da177e4
LT		 3518 }
3519
3520#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3521 if (unlikely(hw->mac_type < e1000_82571)) {
3522 atomic_inc(&adapter->irq_sem);
3523 E1000_WRITE_REG(hw, IMC, ~0);
3524 E1000_WRITE_FLUSH(hw);
3525 }
d3d9e484
AK		 3526 if (likely(netif_rx_schedule_prep(netdev)))
3527 __netif_rx_schedule(netdev);
581d708e 3528 else
90fb5135
AK		 3529 /* this really should not happen! if it does it is basically a
3530 * bug, but not a hard error, so enable ints and continue */
581d708e 3531 e1000_irq_enable(adapter);
c1605eb3 3532#else
1da177e4 3533 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3534 * Due to Hub Link bus being occupied, an interrupt
3535 * de-assertion message is not able to be sent.
3536 * When an interrupt assertion message is generated later,
3537 * two messages are re-ordered and sent out.
3538 * That causes APIC to think 82547 is in de-assertion
3539 * state, while 82547 is in assertion state, resulting
3540 * in dead lock. Writing IMC forces 82547 into
3541 * de-assertion state.
3542 */
3543 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3544 atomic_inc(&adapter->irq_sem);
2648345f 3545 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3546 }
3547
96838a40
JB		 3548 for (i = 0; i < E1000_MAX_INTR; i++)
3549 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
581d708e 3550 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3551 break;
3552
96838a40 3553 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3554 e1000_irq_enable(adapter);
581d708e 3555
c1605eb3 3556#endif
1da177e4
LT		 3557 return IRQ_HANDLED;
3558}
3559
3560#ifdef CONFIG_E1000_NAPI
3561/**
3562 * e1000_clean - NAPI Rx polling callback
3563 * @adapter: board private structure
3564 **/
3565
3566static int
581d708e 3567e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3568{
581d708e
MC		 3569 struct e1000_adapter *adapter;
3570 int work_to_do = min(*budget, poll_dev->quota);
d3d9e484 3571 int tx_cleaned = 0, work_done = 0;
581d708e
MC		 3572
3573 /* Must NOT use netdev_priv macro here. */
3574 adapter = poll_dev->priv;
3575
3576 /* Keep link state information with original netdev */
d3d9e484 3577 if (!netif_carrier_ok(poll_dev))
581d708e 3578 goto quit_polling;
2648345f 3579
d3d9e484
AK		 3580 /* e1000_clean is called per-cpu. This lock protects
3581 * tx_ring[0] from being cleaned by multiple cpus
3582 * simultaneously. A failure obtaining the lock means
3583 * tx_ring[0] is currently being cleaned anyway. */
3584 if (spin_trylock(&adapter->tx_queue_lock)) {
3585 tx_cleaned = e1000_clean_tx_irq(adapter,
3586 &adapter->tx_ring[0]);
3587 spin_unlock(&adapter->tx_queue_lock);
581d708e
MC		 3588 }
3589
d3d9e484 3590 adapter->clean_rx(adapter, &adapter->rx_ring[0],
581d708e 3591 &work_done, work_to_do);
1da177e4
LT		 3592
3593 *budget -= work_done;
581d708e 3594 poll_dev->quota -= work_done;
96838a40 3595
2b02893e 3596 /* If no Tx and not enough Rx work done, exit the polling mode */
96838a40 3597 if ((!tx_cleaned && (work_done == 0)) ||
d3d9e484 3598 !netif_running(poll_dev)) {
581d708e
MC		 3599quit_polling:
3600 netif_rx_complete(poll_dev);
1da177e4
LT		 3601 e1000_irq_enable(adapter);
3602 return 0;
3603 }
3604
3605 return 1;
3606}
3607
3608#endif
3609/**
3610 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3611 * @adapter: board private structure
3612 **/
3613
3614static boolean_t
581d708e
MC		 3615e1000_clean_tx_irq(struct e1000_adapter *adapter,
3616 struct e1000_tx_ring *tx_ring)
1da177e4 3617{
1da177e4
LT		 3618 struct net_device *netdev = adapter->netdev;
3619 struct e1000_tx_desc *tx_desc, *eop_desc;
3620 struct e1000_buffer *buffer_info;
3621 unsigned int i, eop;
2a1af5d7
JK		 3622#ifdef CONFIG_E1000_NAPI
3623 unsigned int count = 0;
3624#endif
1da177e4
LT		 3625 boolean_t cleaned = FALSE;
3626
3627 i = tx_ring->next_to_clean;
3628 eop = tx_ring->buffer_info[i].next_to_watch;
3629 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3630
581d708e 3631 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3632 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3633 tx_desc = E1000_TX_DESC(*tx_ring, i);
3634 buffer_info = &tx_ring->buffer_info[i];
3635 cleaned = (i == eop);
3636
fd803241 3637 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
a9ebadd6 3638 tx_desc->upper.data = 0;
1da177e4 3639
96838a40 3640 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3641 }
581d708e 3642
1da177e4
LT		 3643 eop = tx_ring->buffer_info[i].next_to_watch;
3644 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 3645#ifdef CONFIG_E1000_NAPI
3646#define E1000_TX_WEIGHT 64
3647 /* weight of a sort for tx, to avoid endless transmit cleanup */
3648 if (count++ == E1000_TX_WEIGHT) break;
3649#endif
1da177e4
LT		 3650 }
3651
3652 tx_ring->next_to_clean = i;
3653
77b2aad5 3654#define TX_WAKE_THRESHOLD 32
65c7973f
JB		 3655 if (unlikely(cleaned && netif_carrier_ok(netdev) &&
3656 E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
3657 /* Make sure that anybody stopping the queue after this
3658 * sees the new next_to_clean.
3659 */
3660 smp_mb();
fcfb1224 3661 if (netif_queue_stopped(netdev)) {
77b2aad5 3662 netif_wake_queue(netdev);
fcfb1224
JB		 3663 ++adapter->restart_queue;
3664 }
77b2aad5 3665 }
2648345f 3666
581d708e 3667 if (adapter->detect_tx_hung) {
2648345f 3668 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3669 * check with the clearing of time_stamp and movement of i */
3670 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3671 if (tx_ring->buffer_info[eop].dma &&
3672 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 3673 (adapter->tx_timeout_factor * HZ))
70b8f1e1 3674 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3675 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3676
3677 /* detected Tx unit hang */
c6963ef5 3678 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3679 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3680 " TDH <%x>\n"
3681 " TDT <%x>\n"
3682 " next_to_use <%x>\n"
3683 " next_to_clean <%x>\n"
3684 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3685 " time_stamp <%lx>\n"
3686 " next_to_watch <%x>\n"
3687 " jiffies <%lx>\n"
3688 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3689 (unsigned long)((tx_ring - adapter->tx_ring) /
3690 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3691 readl(adapter->hw.hw_addr + tx_ring->tdh),
3692 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3693 tx_ring->next_to_use,
392137fa
JK		 3694 tx_ring->next_to_clean,
3695 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3696 eop,
3697 jiffies,
3698 eop_desc->upper.fields.status);
1da177e4 3699 netif_stop_queue(netdev);
70b8f1e1 3700 }
1da177e4 3701 }
1da177e4
LT		 3702 return cleaned;
3703}
3704
3705/**
3706 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3707 * @adapter: board private structure
3708 * @status_err: receive descriptor status and error fields
3709 * @csum: receive descriptor csum field
3710 * @sk_buff: socket buffer with received data
1da177e4
LT		 3711 **/
3712
e619d523 3713static void
1da177e4 3714e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3715 uint32_t status_err, uint32_t csum,
3716 struct sk_buff *skb)
1da177e4 3717{
2d7edb92
MC		 3718 uint16_t status = (uint16_t)status_err;
3719 uint8_t errors = (uint8_t)(status_err >> 24);
3720 skb->ip_summed = CHECKSUM_NONE;
3721
1da177e4 3722 /* 82543 or newer only */
96838a40 3723 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3724 /* Ignore Checksum bit is set */
96838a40 3725 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 3726 /* TCP/UDP checksum error bit is set */
96838a40 3727 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3728 /* let the stack verify checksum errors */
1da177e4 3729 adapter->hw_csum_err++;
2d7edb92
MC		 3730 return;
3731 }
3732 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 3733 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
3734 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 3735 return;
1da177e4 3736 } else {
96838a40 3737 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 3738 return;
3739 }
3740 /* It must be a TCP or UDP packet with a valid checksum */
3741 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3742 /* TCP checksum is good */
3743 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3744 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3745 /* IP fragment with UDP payload */
3746 /* Hardware complements the payload checksum, so we undo it
3747 * and then put the value in host order for further stack use.
3748 */
3749 csum = ntohl(csum ^ 0xFFFF);
3750 skb->csum = csum;
84fa7933 3751 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 3752 }
2d7edb92 3753 adapter->hw_csum_good++;
1da177e4
LT		 3754}
3755
3756/**
2d7edb92 3757 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3758 * @adapter: board private structure
3759 **/
3760
3761static boolean_t
3762#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3763e1000_clean_rx_irq(struct e1000_adapter *adapter,
3764 struct e1000_rx_ring *rx_ring,
3765 int *work_done, int work_to_do)
1da177e4 3766#else
581d708e
MC		 3767e1000_clean_rx_irq(struct e1000_adapter *adapter,
3768 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3769#endif
3770{
1da177e4
LT		 3771 struct net_device *netdev = adapter->netdev;
3772 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 3773 struct e1000_rx_desc *rx_desc, *next_rxd;
3774 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 3775 unsigned long flags;
3776 uint32_t length;
3777 uint8_t last_byte;
3778 unsigned int i;
72d64a43 3779 int cleaned_count = 0;
a1415ee6 3780 boolean_t cleaned = FALSE;
1da177e4
LT		 3781
3782 i = rx_ring->next_to_clean;
3783 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 3784 buffer_info = &rx_ring->buffer_info[i];
1da177e4 3785
b92ff8ee 3786 while (rx_desc->status & E1000_RXD_STAT_DD) {
24f476ee 3787 struct sk_buff *skb;
a292ca6e 3788 u8 status;
90fb5135 3789
1da177e4 3790#ifdef CONFIG_E1000_NAPI
96838a40 3791 if (*work_done >= work_to_do)
1da177e4
LT		 3792 break;
3793 (*work_done)++;
3794#endif
a292ca6e 3795 status = rx_desc->status;
b92ff8ee 3796 skb = buffer_info->skb;
86c3d59f
JB		 3797 buffer_info->skb = NULL;
3798
30320be8
JK		 3799 prefetch(skb->data - NET_IP_ALIGN);
3800
86c3d59f
JB		 3801 if (++i == rx_ring->count) i = 0;
3802 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 3803 prefetch(next_rxd);
3804
86c3d59f 3805 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 3806
72d64a43
JK		 3807 cleaned = TRUE;
3808 cleaned_count++;
a292ca6e
JK		 3809 pci_unmap_single(pdev,
3810 buffer_info->dma,
3811 buffer_info->length,
1da177e4
LT		 3812 PCI_DMA_FROMDEVICE);
3813
1da177e4
LT		 3814 length = le16_to_cpu(rx_desc->length);
3815
a1415ee6
JK		 3816 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
3817 /* All receives must fit into a single buffer */
3818 E1000_DBG("%s: Receive packet consumed multiple"
3819 " buffers\n", netdev->name);
864c4e45 3820 /* recycle */
8fc897b0 3821 buffer_info->skb = skb;
1da177e4
LT		 3822 goto next_desc;
3823 }
3824
96838a40 3825 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 3826 last_byte = *(skb->data + length - 1);
b92ff8ee 3827 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 3828 rx_desc->errors, length, last_byte)) {
3829 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 3830 e1000_tbi_adjust_stats(&adapter->hw,
3831 &adapter->stats,
1da177e4
LT		 3832 length, skb->data);
3833 spin_unlock_irqrestore(&adapter->stats_lock,
3834 flags);
3835 length--;
3836 } else {
9e2feace
AK		 3837 /* recycle */
3838 buffer_info->skb = skb;
1da177e4
LT		 3839 goto next_desc;
3840 }
1cb5821f 3841 }
1da177e4 3842
d2a1e213
JB		 3843 /* adjust length to remove Ethernet CRC, this must be
3844 * done after the TBI_ACCEPT workaround above */
3845 length -= 4;
3846
a292ca6e
JK		 3847 /* code added for copybreak, this should improve
3848 * performance for small packets with large amounts
3849 * of reassembly being done in the stack */
3850#define E1000_CB_LENGTH 256
a1415ee6 3851 if (length < E1000_CB_LENGTH) {
a292ca6e 3852 struct sk_buff *new_skb =
87f5032e 3853 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
a292ca6e
JK		 3854 if (new_skb) {
3855 skb_reserve(new_skb, NET_IP_ALIGN);
a292ca6e
JK		 3856 memcpy(new_skb->data - NET_IP_ALIGN,
3857 skb->data - NET_IP_ALIGN,
3858 length + NET_IP_ALIGN);
3859 /* save the skb in buffer_info as good */
3860 buffer_info->skb = skb;
3861 skb = new_skb;
a292ca6e 3862 }
996695de
AK		 3863 /* else just continue with the old one */
3864 }
a292ca6e 3865 /* end copybreak code */
996695de 3866 skb_put(skb, length);
1da177e4
LT		 3867
3868 /* Receive Checksum Offload */
a292ca6e
JK		 3869 e1000_rx_checksum(adapter,
3870 (uint32_t)(status) |
2d7edb92 3871 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 3872 le16_to_cpu(rx_desc->csum), skb);
96838a40 3873
1da177e4
LT		 3874 skb->protocol = eth_type_trans(skb, netdev);
3875#ifdef CONFIG_E1000_NAPI
96838a40 3876 if (unlikely(adapter->vlgrp &&
a292ca6e 3877 (status & E1000_RXD_STAT_VP))) {
1da177e4 3878 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3879 le16_to_cpu(rx_desc->special) &
3880 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3881 } else {
3882 netif_receive_skb(skb);
3883 }
3884#else /* CONFIG_E1000_NAPI */
96838a40 3885 if (unlikely(adapter->vlgrp &&
b92ff8ee 3886 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 3887 vlan_hwaccel_rx(skb, adapter->vlgrp,
3888 le16_to_cpu(rx_desc->special) &
3889 E1000_RXD_SPC_VLAN_MASK);
3890 } else {
3891 netif_rx(skb);
3892 }
3893#endif /* CONFIG_E1000_NAPI */
3894 netdev->last_rx = jiffies;
3895
3896next_desc:
3897 rx_desc->status = 0;
1da177e4 3898
72d64a43
JK		 3899 /* return some buffers to hardware, one at a time is too slow */
3900 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3901 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3902 cleaned_count = 0;
3903 }
3904
30320be8 3905 /* use prefetched values */
86c3d59f
JB		 3906 rx_desc = next_rxd;
3907 buffer_info = next_buffer;
1da177e4 3908 }
1da177e4 3909 rx_ring->next_to_clean = i;
72d64a43
JK		 3910
3911 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3912 if (cleaned_count)
3913 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92
MC		 3914
3915 return cleaned;
3916}
3917
3918/**
3919 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3920 * @adapter: board private structure
3921 **/
3922
3923static boolean_t
3924#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3925e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3926 struct e1000_rx_ring *rx_ring,
3927 int *work_done, int work_to_do)
2d7edb92 3928#else
581d708e
MC		 3929e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3930 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3931#endif
3932{
86c3d59f 3933 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 3934 struct net_device *netdev = adapter->netdev;
3935 struct pci_dev *pdev = adapter->pdev;
86c3d59f 3936 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 3937 struct e1000_ps_page *ps_page;
3938 struct e1000_ps_page_dma *ps_page_dma;
24f476ee 3939 struct sk_buff *skb;
2d7edb92
MC		 3940 unsigned int i, j;
3941 uint32_t length, staterr;
72d64a43 3942 int cleaned_count = 0;
2d7edb92
MC		 3943 boolean_t cleaned = FALSE;
3944
3945 i = rx_ring->next_to_clean;
3946 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3947 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 3948 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 3949
96838a40 3950 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 3951 ps_page = &rx_ring->ps_page[i];
3952 ps_page_dma = &rx_ring->ps_page_dma[i];
3953#ifdef CONFIG_E1000_NAPI
96838a40 3954 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 3955 break;
3956 (*work_done)++;
3957#endif
86c3d59f
JB		 3958 skb = buffer_info->skb;
3959
30320be8
JK		 3960 /* in the packet split case this is header only */
3961 prefetch(skb->data - NET_IP_ALIGN);
3962
86c3d59f
JB		 3963 if (++i == rx_ring->count) i = 0;
3964 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 3965 prefetch(next_rxd);
3966
86c3d59f 3967 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 3968
2d7edb92 3969 cleaned = TRUE;
72d64a43 3970 cleaned_count++;
2d7edb92
MC		 3971 pci_unmap_single(pdev, buffer_info->dma,
3972 buffer_info->length,
3973 PCI_DMA_FROMDEVICE);
3974
96838a40 3975 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 3976 E1000_DBG("%s: Packet Split buffers didn't pick up"
3977 " the full packet\n", netdev->name);
3978 dev_kfree_skb_irq(skb);
3979 goto next_desc;
3980 }
1da177e4 3981
96838a40 3982 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 3983 dev_kfree_skb_irq(skb);
3984 goto next_desc;
3985 }
3986
3987 length = le16_to_cpu(rx_desc->wb.middle.length0);
3988
96838a40 3989 if (unlikely(!length)) {
2d7edb92
MC		 3990 E1000_DBG("%s: Last part of the packet spanning"
3991 " multiple descriptors\n", netdev->name);
3992 dev_kfree_skb_irq(skb);
3993 goto next_desc;
3994 }
3995
3996 /* Good Receive */
3997 skb_put(skb, length);
3998
dc7c6add
JK		 3999 {
4000 /* this looks ugly, but it seems compiler issues make it
4001 more efficient than reusing j */
4002 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
4003
4004 /* page alloc/put takes too long and effects small packet
4005 * throughput, so unsplit small packets and save the alloc/put*/
9e2feace 4006 if (l1 && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add 4007 u8 *vaddr;
76c224bc 4008 /* there is no documentation about how to call
dc7c6add
JK		 4009 * kmap_atomic, so we can't hold the mapping
4010 * very long */
4011 pci_dma_sync_single_for_cpu(pdev,
4012 ps_page_dma->ps_page_dma[0],
4013 PAGE_SIZE,
4014 PCI_DMA_FROMDEVICE);
4015 vaddr = kmap_atomic(ps_page->ps_page[0],
4016 KM_SKB_DATA_SOFTIRQ);
4017 memcpy(skb->tail, vaddr, l1);
4018 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
4019 pci_dma_sync_single_for_device(pdev,
4020 ps_page_dma->ps_page_dma[0],
4021 PAGE_SIZE, PCI_DMA_FROMDEVICE);
f235a2ab
AK		 4022 /* remove the CRC */
4023 l1 -= 4;
dc7c6add 4024 skb_put(skb, l1);
dc7c6add
JK		 4025 goto copydone;
4026 } /* if */
4027 }
90fb5135 4028
96838a40 4029 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 4030 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 4031 break;
2d7edb92
MC		 4032 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
4033 PAGE_SIZE, PCI_DMA_FROMDEVICE);
4034 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 4035 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
4036 length);
2d7edb92 4037 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 4038 skb->len += length;
4039 skb->data_len += length;
5d51b80f 4040 skb->truesize += length;
2d7edb92
MC		 4041 }
4042
f235a2ab
AK		 4043 /* strip the ethernet crc, problem is we're using pages now so
4044 * this whole operation can get a little cpu intensive */
4045 pskb_trim(skb, skb->len - 4);
4046
dc7c6add 4047copydone:
2d7edb92 4048 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 4049 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 4050 skb->protocol = eth_type_trans(skb, netdev);
4051
96838a40 4052 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 4053 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 4054 adapter->rx_hdr_split++;
2d7edb92 4055#ifdef CONFIG_E1000_NAPI
96838a40 4056 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4057 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 4058 le16_to_cpu(rx_desc->wb.middle.vlan) &
4059 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 4060 } else {
4061 netif_receive_skb(skb);
4062 }
4063#else /* CONFIG_E1000_NAPI */
96838a40 4064 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4065 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 4066 le16_to_cpu(rx_desc->wb.middle.vlan) &
4067 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 4068 } else {
4069 netif_rx(skb);
4070 }
4071#endif /* CONFIG_E1000_NAPI */
4072 netdev->last_rx = jiffies;
4073
4074next_desc:
c3d7a3a4 4075 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 4076 buffer_info->skb = NULL;
2d7edb92 4077
72d64a43
JK		 4078 /* return some buffers to hardware, one at a time is too slow */
4079 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4080 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4081 cleaned_count = 0;
4082 }
4083
30320be8 4084 /* use prefetched values */
86c3d59f
JB		 4085 rx_desc = next_rxd;
4086 buffer_info = next_buffer;
4087
683a38f3 4088 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 4089 }
4090 rx_ring->next_to_clean = i;
72d64a43
JK		 4091
4092 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4093 if (cleaned_count)
4094 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4
LT		 4095
4096 return cleaned;
4097}
4098
4099/**
2d7edb92 4100 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 4101 * @adapter: address of board private structure
4102 **/
4103
4104static void
581d708e 4105e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 4106 struct e1000_rx_ring *rx_ring,
a292ca6e 4107 int cleaned_count)
1da177e4 4108{
1da177e4
LT		 4109 struct net_device *netdev = adapter->netdev;
4110 struct pci_dev *pdev = adapter->pdev;
4111 struct e1000_rx_desc *rx_desc;
4112 struct e1000_buffer *buffer_info;
4113 struct sk_buff *skb;
2648345f
MC		 4114 unsigned int i;
4115 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 4116
4117 i = rx_ring->next_to_use;
4118 buffer_info = &rx_ring->buffer_info[i];
4119
a292ca6e 4120 while (cleaned_count--) {
ca6f7224
CH		 4121 skb = buffer_info->skb;
4122 if (skb) {
a292ca6e
JK		 4123 skb_trim(skb, 0);
4124 goto map_skb;
4125 }
4126
ca6f7224 4127 skb = netdev_alloc_skb(netdev, bufsz);
96838a40 4128 if (unlikely(!skb)) {
1da177e4 4129 /* Better luck next round */
72d64a43 4130 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 4131 break;
4132 }
4133
2648345f 4134 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 4135 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4136 struct sk_buff *oldskb = skb;
2648345f
MC		 4137 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
4138 "at %p\n", bufsz, skb->data);
4139 /* Try again, without freeing the previous */
87f5032e 4140 skb = netdev_alloc_skb(netdev, bufsz);
2648345f 4141 /* Failed allocation, critical failure */
1da177e4
LT		 4142 if (!skb) {
4143 dev_kfree_skb(oldskb);
4144 break;
4145 }
2648345f 4146
1da177e4
LT		 4147 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4148 /* give up */
4149 dev_kfree_skb(skb);
4150 dev_kfree_skb(oldskb);
4151 break; /* while !buffer_info->skb */
1da177e4 4152 }
ca6f7224
CH		 4153
4154 /* Use new allocation */
4155 dev_kfree_skb(oldskb);
1da177e4 4156 }
1da177e4
LT		 4157 /* Make buffer alignment 2 beyond a 16 byte boundary
4158 * this will result in a 16 byte aligned IP header after
4159 * the 14 byte MAC header is removed
4160 */
4161 skb_reserve(skb, NET_IP_ALIGN);
4162
1da177e4
LT		 4163 buffer_info->skb = skb;
4164 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 4165map_skb:
1da177e4
LT		 4166 buffer_info->dma = pci_map_single(pdev,
4167 skb->data,
4168 adapter->rx_buffer_len,
4169 PCI_DMA_FROMDEVICE);
4170
2648345f
MC		 4171 /* Fix for errata 23, can't cross 64kB boundary */
4172 if (!e1000_check_64k_bound(adapter,
4173 (void *)(unsigned long)buffer_info->dma,
4174 adapter->rx_buffer_len)) {
4175 DPRINTK(RX_ERR, ERR,
4176 "dma align check failed: %u bytes at %p\n",
4177 adapter->rx_buffer_len,
4178 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 4179 dev_kfree_skb(skb);
4180 buffer_info->skb = NULL;
4181
2648345f 4182 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 4183 adapter->rx_buffer_len,
4184 PCI_DMA_FROMDEVICE);
4185
4186 break; /* while !buffer_info->skb */
4187 }
1da177e4
LT		 4188 rx_desc = E1000_RX_DESC(*rx_ring, i);
4189 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4190
96838a40
JB		 4191 if (unlikely(++i == rx_ring->count))
4192 i = 0;
1da177e4
LT		 4193 buffer_info = &rx_ring->buffer_info[i];
4194 }
4195
b92ff8ee
JB		 4196 if (likely(rx_ring->next_to_use != i)) {
4197 rx_ring->next_to_use = i;
4198 if (unlikely(i-- == 0))
4199 i = (rx_ring->count - 1);
4200
4201 /* Force memory writes to complete before letting h/w
4202 * know there are new descriptors to fetch. (Only
4203 * applicable for weak-ordered memory model archs,
4204 * such as IA-64). */
4205 wmb();
4206 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4207 }
1da177e4
LT		 4208}
4209
2d7edb92
MC		 4210/**
4211 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
4212 * @adapter: address of board private structure
4213 **/
4214
4215static void
581d708e 4216e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 4217 struct e1000_rx_ring *rx_ring,
4218 int cleaned_count)
2d7edb92 4219{
2d7edb92
MC		 4220 struct net_device *netdev = adapter->netdev;
4221 struct pci_dev *pdev = adapter->pdev;
4222 union e1000_rx_desc_packet_split *rx_desc;
4223 struct e1000_buffer *buffer_info;
4224 struct e1000_ps_page *ps_page;
4225 struct e1000_ps_page_dma *ps_page_dma;
4226 struct sk_buff *skb;
4227 unsigned int i, j;
4228
4229 i = rx_ring->next_to_use;
4230 buffer_info = &rx_ring->buffer_info[i];
4231 ps_page = &rx_ring->ps_page[i];
4232 ps_page_dma = &rx_ring->ps_page_dma[i];
4233
72d64a43 4234 while (cleaned_count--) {
2d7edb92
MC		 4235 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4236
96838a40 4237 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4238 if (j < adapter->rx_ps_pages) {
4239 if (likely(!ps_page->ps_page[j])) {
4240 ps_page->ps_page[j] =
4241 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4242 if (unlikely(!ps_page->ps_page[j])) {
4243 adapter->alloc_rx_buff_failed++;
e4c811c9 4244 goto no_buffers;
b92ff8ee 4245 }
e4c811c9
MC		 4246 ps_page_dma->ps_page_dma[j] =
4247 pci_map_page(pdev,
4248 ps_page->ps_page[j],
4249 0, PAGE_SIZE,
4250 PCI_DMA_FROMDEVICE);
4251 }
4252 /* Refresh the desc even if buffer_addrs didn't
96838a40 4253 * change because each write-back erases
e4c811c9
MC		 4254 * this info.
4255 */
4256 rx_desc->read.buffer_addr[j+1] =
4257 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4258 } else
4259 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4260 }
4261
87f5032e 4262 skb = netdev_alloc_skb(netdev,
90fb5135 4263 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
2d7edb92 4264
b92ff8ee
JB		 4265 if (unlikely(!skb)) {
4266 adapter->alloc_rx_buff_failed++;
2d7edb92 4267 break;
b92ff8ee 4268 }
2d7edb92
MC		 4269
4270 /* Make buffer alignment 2 beyond a 16 byte boundary
4271 * this will result in a 16 byte aligned IP header after
4272 * the 14 byte MAC header is removed
4273 */
4274 skb_reserve(skb, NET_IP_ALIGN);
4275
2d7edb92
MC		 4276 buffer_info->skb = skb;
4277 buffer_info->length = adapter->rx_ps_bsize0;
4278 buffer_info->dma = pci_map_single(pdev, skb->data,
4279 adapter->rx_ps_bsize0,
4280 PCI_DMA_FROMDEVICE);
4281
4282 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4283
96838a40 4284 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4285 buffer_info = &rx_ring->buffer_info[i];
4286 ps_page = &rx_ring->ps_page[i];
4287 ps_page_dma = &rx_ring->ps_page_dma[i];
4288 }
4289
4290no_buffers:
b92ff8ee
JB		 4291 if (likely(rx_ring->next_to_use != i)) {
4292 rx_ring->next_to_use = i;
4293 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4294
4295 /* Force memory writes to complete before letting h/w
4296 * know there are new descriptors to fetch. (Only
4297 * applicable for weak-ordered memory model archs,
4298 * such as IA-64). */
4299 wmb();
4300 /* Hardware increments by 16 bytes, but packet split
4301 * descriptors are 32 bytes...so we increment tail
4302 * twice as much.
4303 */
4304 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4305 }
2d7edb92
MC		 4306}
4307
1da177e4
LT		 4308/**
4309 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4310 * @adapter:
4311 **/
4312
4313static void
4314e1000_smartspeed(struct e1000_adapter *adapter)
4315{
4316 uint16_t phy_status;
4317 uint16_t phy_ctrl;
4318
96838a40 4319 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4320 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4321 return;
4322
96838a40 4323 if (adapter->smartspeed == 0) {
1da177e4
LT		 4324 /* If Master/Slave config fault is asserted twice,
4325 * we assume back-to-back */
4326 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4327 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4328 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4329 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4330 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4331 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4332 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4333 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4334 phy_ctrl);
4335 adapter->smartspeed++;
96838a40 4336 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4337 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4338 &phy_ctrl)) {
4339 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4340 MII_CR_RESTART_AUTO_NEG);
4341 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4342 phy_ctrl);
4343 }
4344 }
4345 return;
96838a40 4346 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4347 /* If still no link, perhaps using 2/3 pair cable */
4348 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4349 phy_ctrl |= CR_1000T_MS_ENABLE;
4350 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4351 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4352 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4353 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4354 MII_CR_RESTART_AUTO_NEG);
4355 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4356 }
4357 }
4358 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4359 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4360 adapter->smartspeed = 0;
4361}
4362
4363/**
4364 * e1000_ioctl -
4365 * @netdev:
4366 * @ifreq:
4367 * @cmd:
4368 **/
4369
4370static int
4371e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4372{
4373 switch (cmd) {
4374 case SIOCGMIIPHY:
4375 case SIOCGMIIREG:
4376 case SIOCSMIIREG:
4377 return e1000_mii_ioctl(netdev, ifr, cmd);
4378 default:
4379 return -EOPNOTSUPP;
4380 }
4381}
4382
4383/**
4384 * e1000_mii_ioctl -
4385 * @netdev:
4386 * @ifreq:
4387 * @cmd:
4388 **/
4389
4390static int
4391e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4392{
60490fe0 4393 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4394 struct mii_ioctl_data *data = if_mii(ifr);
4395 int retval;
4396 uint16_t mii_reg;
4397 uint16_t spddplx;
97876fc6 4398 unsigned long flags;
1da177e4 4399
96838a40 4400 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4401 return -EOPNOTSUPP;
4402
4403 switch (cmd) {
4404 case SIOCGMIIPHY:
4405 data->phy_id = adapter->hw.phy_addr;
4406 break;
4407 case SIOCGMIIREG:
96838a40 4408 if (!capable(CAP_NET_ADMIN))
1da177e4 4409 return -EPERM;
97876fc6 4410 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4411 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4412 &data->val_out)) {
4413 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4414 return -EIO;
97876fc6
MC		 4415 }
4416 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4417 break;
4418 case SIOCSMIIREG:
96838a40 4419 if (!capable(CAP_NET_ADMIN))
1da177e4 4420 return -EPERM;
96838a40 4421 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4422 return -EFAULT;
4423 mii_reg = data->val_in;
97876fc6 4424 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4425 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4426 mii_reg)) {
4427 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4428 return -EIO;
97876fc6 4429 }
dc86d32a 4430 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4431 switch (data->reg_num) {
4432 case PHY_CTRL:
96838a40 4433 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4434 break;
96838a40 4435 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4436 adapter->hw.autoneg = 1;
4437 adapter->hw.autoneg_advertised = 0x2F;
4438 } else {
4439 if (mii_reg & 0x40)
4440 spddplx = SPEED_1000;
4441 else if (mii_reg & 0x2000)
4442 spddplx = SPEED_100;
4443 else
4444 spddplx = SPEED_10;
4445 spddplx += (mii_reg & 0x100)
cb764326
JK		 4446 ? DUPLEX_FULL :
4447 DUPLEX_HALF;
1da177e4
LT		 4448 retval = e1000_set_spd_dplx(adapter,
4449 spddplx);
96838a40 4450 if (retval) {
97876fc6 4451 spin_unlock_irqrestore(
96838a40 4452 &adapter->stats_lock,
97876fc6 4453 flags);
1da177e4 4454 return retval;
97876fc6 4455 }
1da177e4 4456 }
2db10a08
AK		 4457 if (netif_running(adapter->netdev))
4458 e1000_reinit_locked(adapter);
4459 else
1da177e4
LT		 4460 e1000_reset(adapter);
4461 break;
4462 case M88E1000_PHY_SPEC_CTRL:
4463 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4464 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4465 spin_unlock_irqrestore(
4466 &adapter->stats_lock, flags);
1da177e4 4467 return -EIO;
97876fc6 4468 }
1da177e4
LT		 4469 break;
4470 }
4471 } else {
4472 switch (data->reg_num) {
4473 case PHY_CTRL:
96838a40 4474 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4475 break;
2db10a08
AK		 4476 if (netif_running(adapter->netdev))
4477 e1000_reinit_locked(adapter);
4478 else
1da177e4
LT		 4479 e1000_reset(adapter);
4480 break;
4481 }
4482 }
97876fc6 4483 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4484 break;
4485 default:
4486 return -EOPNOTSUPP;
4487 }
4488 return E1000_SUCCESS;
4489}
4490
4491void
4492e1000_pci_set_mwi(struct e1000_hw *hw)
4493{
4494 struct e1000_adapter *adapter = hw->back;
2648345f 4495 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4496
96838a40 4497 if (ret_val)
2648345f 4498 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4499}
4500
4501void
4502e1000_pci_clear_mwi(struct e1000_hw *hw)
4503{
4504 struct e1000_adapter *adapter = hw->back;
4505
4506 pci_clear_mwi(adapter->pdev);
4507}
4508
4509void
4510e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4511{
4512 struct e1000_adapter *adapter = hw->back;
4513
4514 pci_read_config_word(adapter->pdev, reg, value);
4515}
4516
4517void
4518e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4519{
4520 struct e1000_adapter *adapter = hw->back;
4521
4522 pci_write_config_word(adapter->pdev, reg, *value);
4523}
4524
caeccb68
JK		 4525int32_t
4526e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4527{
4528 struct e1000_adapter *adapter = hw->back;
4529 uint16_t cap_offset;
4530
4531 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
4532 if (!cap_offset)
4533 return -E1000_ERR_CONFIG;
4534
4535 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
4536
4537 return E1000_SUCCESS;
4538}
4539
1da177e4
LT		 4540void
4541e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4542{
4543 outl(value, port);
4544}
4545
4546static void
4547e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4548{
60490fe0 4549 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4550 uint32_t ctrl, rctl;
4551
4552 e1000_irq_disable(adapter);
4553 adapter->vlgrp = grp;
4554
96838a40 4555 if (grp) {
1da177e4
LT		 4556 /* enable VLAN tag insert/strip */
4557 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4558 ctrl |= E1000_CTRL_VME;
4559 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4560
cd94dd0b 4561 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4562 /* enable VLAN receive filtering */
4563 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4564 rctl |= E1000_RCTL_VFE;
4565 rctl &= ~E1000_RCTL_CFIEN;
4566 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4567 e1000_update_mng_vlan(adapter);
cd94dd0b 4568 }
1da177e4
LT		 4569 } else {
4570 /* disable VLAN tag insert/strip */
4571 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4572 ctrl &= ~E1000_CTRL_VME;
4573 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4574
cd94dd0b 4575 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4576 /* disable VLAN filtering */
4577 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4578 rctl &= ~E1000_RCTL_VFE;
4579 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4580 if (adapter->mng_vlan_id !=
4581 (uint16_t)E1000_MNG_VLAN_NONE) {
4582 e1000_vlan_rx_kill_vid(netdev,
4583 adapter->mng_vlan_id);
4584 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4585 }
cd94dd0b 4586 }
1da177e4
LT		 4587 }
4588
4589 e1000_irq_enable(adapter);
4590}
4591
4592static void
4593e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4594{
60490fe0 4595 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4596 uint32_t vfta, index;
96838a40
JB		 4597
4598 if ((adapter->hw.mng_cookie.status &
4599 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4600 (vid == adapter->mng_vlan_id))
2d7edb92 4601 return;
1da177e4
LT		 4602 /* add VID to filter table */
4603 index = (vid >> 5) & 0x7F;
4604 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4605 vfta |= (1 << (vid & 0x1F));
4606 e1000_write_vfta(&adapter->hw, index, vfta);
4607}
4608
4609static void
4610e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4611{
60490fe0 4612 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4613 uint32_t vfta, index;
4614
4615 e1000_irq_disable(adapter);
4616
96838a40 4617 if (adapter->vlgrp)
1da177e4
LT		 4618 adapter->vlgrp->vlan_devices[vid] = NULL;
4619
4620 e1000_irq_enable(adapter);
4621
96838a40
JB		 4622 if ((adapter->hw.mng_cookie.status &
4623 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4624 (vid == adapter->mng_vlan_id)) {
4625 /* release control to f/w */
4626 e1000_release_hw_control(adapter);
2d7edb92 4627 return;
ff147013
JK		 4628 }
4629
1da177e4
LT		 4630 /* remove VID from filter table */
4631 index = (vid >> 5) & 0x7F;
4632 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4633 vfta &= ~(1 << (vid & 0x1F));
4634 e1000_write_vfta(&adapter->hw, index, vfta);
4635}
4636
4637static void
4638e1000_restore_vlan(struct e1000_adapter *adapter)
4639{
4640 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4641
96838a40 4642 if (adapter->vlgrp) {
1da177e4 4643 uint16_t vid;
96838a40
JB		 4644 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4645 if (!adapter->vlgrp->vlan_devices[vid])
1da177e4
LT		 4646 continue;
4647 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4648 }
4649 }
4650}
4651
4652int
4653e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4654{
4655 adapter->hw.autoneg = 0;
4656
6921368f 4657 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 4658 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 4659 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4660 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4661 return -EINVAL;
4662 }
4663
96838a40 4664 switch (spddplx) {
1da177e4
LT		 4665 case SPEED_10 + DUPLEX_HALF:
4666 adapter->hw.forced_speed_duplex = e1000_10_half;
4667 break;
4668 case SPEED_10 + DUPLEX_FULL:
4669 adapter->hw.forced_speed_duplex = e1000_10_full;
4670 break;
4671 case SPEED_100 + DUPLEX_HALF:
4672 adapter->hw.forced_speed_duplex = e1000_100_half;
4673 break;
4674 case SPEED_100 + DUPLEX_FULL:
4675 adapter->hw.forced_speed_duplex = e1000_100_full;
4676 break;
4677 case SPEED_1000 + DUPLEX_FULL:
4678 adapter->hw.autoneg = 1;
4679 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4680 break;
4681 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4682 default:
2648345f 4683 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4684 return -EINVAL;
4685 }
4686 return 0;
4687}
4688
b6a1d5f8 4689#ifdef CONFIG_PM
0f15a8fa
JK		 4690/* Save/restore 16 or 64 dwords of PCI config space depending on which
4691 * bus we're on (PCI(X) vs. PCI-E)
2f82665f
JB		 4692 */
4693#define PCIE_CONFIG_SPACE_LEN 256
4694#define PCI_CONFIG_SPACE_LEN 64
4695static int
4696e1000_pci_save_state(struct e1000_adapter *adapter)
4697{
4698 struct pci_dev *dev = adapter->pdev;
4699 int size;
4700 int i;
0f15a8fa 4701
2f82665f
JB		 4702 if (adapter->hw.mac_type >= e1000_82571)
4703 size = PCIE_CONFIG_SPACE_LEN;
4704 else
4705 size = PCI_CONFIG_SPACE_LEN;
4706
4707 WARN_ON(adapter->config_space != NULL);
4708
4709 adapter->config_space = kmalloc(size, GFP_KERNEL);
4710 if (!adapter->config_space) {
4711 DPRINTK(PROBE, ERR, "unable to allocate %d bytes\n", size);
4712 return -ENOMEM;
4713 }
4714 for (i = 0; i < (size / 4); i++)
4715 pci_read_config_dword(dev, i * 4, &adapter->config_space[i]);
4716 return 0;
4717}
4718
4719static void
4720e1000_pci_restore_state(struct e1000_adapter *adapter)
4721{
4722 struct pci_dev *dev = adapter->pdev;
4723 int size;
4724 int i;
0f15a8fa 4725
2f82665f
JB		 4726 if (adapter->config_space == NULL)
4727 return;
0f15a8fa 4728
2f82665f
JB		 4729 if (adapter->hw.mac_type >= e1000_82571)
4730 size = PCIE_CONFIG_SPACE_LEN;
4731 else
4732 size = PCI_CONFIG_SPACE_LEN;
4733 for (i = 0; i < (size / 4); i++)
4734 pci_write_config_dword(dev, i * 4, adapter->config_space[i]);
4735 kfree(adapter->config_space);
4736 adapter->config_space = NULL;
4737 return;
4738}
4739#endif /* CONFIG_PM */
4740
1da177e4 4741static int
829ca9a3 4742e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4743{
4744 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4745 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4746 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4 4747 uint32_t wufc = adapter->wol;
6fdfef16 4748#ifdef CONFIG_PM
240b1710 4749 int retval = 0;
6fdfef16 4750#endif
1da177e4
LT		 4751
4752 netif_device_detach(netdev);
4753
2db10a08
AK		 4754 if (netif_running(netdev)) {
4755 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 4756 e1000_down(adapter);
2db10a08 4757 }
1da177e4 4758
2f82665f 4759#ifdef CONFIG_PM
0f15a8fa
JK		 4760 /* Implement our own version of pci_save_state(pdev) because pci-
4761 * express adapters have 256-byte config spaces. */
2f82665f
JB		 4762 retval = e1000_pci_save_state(adapter);
4763 if (retval)
4764 return retval;
4765#endif
4766
1da177e4 4767 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 4768 if (status & E1000_STATUS_LU)
1da177e4
LT		 4769 wufc &= ~E1000_WUFC_LNKC;
4770
96838a40 4771 if (wufc) {
1da177e4
LT		 4772 e1000_setup_rctl(adapter);
4773 e1000_set_multi(netdev);
4774
4775 /* turn on all-multi mode if wake on multicast is enabled */
120cd576 4776 if (wufc & E1000_WUFC_MC) {
1da177e4
LT		 4777 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4778 rctl |= E1000_RCTL_MPE;
4779 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4780 }
4781
96838a40 4782 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 4783 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4784 /* advertise wake from D3Cold */
4785 #define E1000_CTRL_ADVD3WUC 0x00100000
4786 /* phy power management enable */
4787 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4788 ctrl |= E1000_CTRL_ADVD3WUC |
4789 E1000_CTRL_EN_PHY_PWR_MGMT;
4790 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4791 }
4792
96838a40 4793 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 4794 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4795 /* keep the laser running in D3 */
4796 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4797 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4798 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4799 }
4800
2d7edb92
MC		 4801 /* Allow time for pending master requests to run */
4802 e1000_disable_pciex_master(&adapter->hw);
4803
1da177e4
LT		 4804 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4805 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 4806 pci_enable_wake(pdev, PCI_D3hot, 1);
4807 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4808 } else {
4809 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4810 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 4811 pci_enable_wake(pdev, PCI_D3hot, 0);
4812 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4813 }
4814
4ccc12ae
JB		 4815 if (adapter->hw.mac_type >= e1000_82540 &&
4816 adapter->hw.mac_type < e1000_82571 &&
4817 adapter->hw.media_type == e1000_media_type_copper) {
1da177e4 4818 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 4819 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 4820 manc |= E1000_MANC_ARP_EN;
4821 E1000_WRITE_REG(&adapter->hw, MANC, manc);
d0e027db
AK		 4822 pci_enable_wake(pdev, PCI_D3hot, 1);
4823 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4824 }
4825 }
4826
cd94dd0b
AK		 4827 if (adapter->hw.phy_type == e1000_phy_igp_3)
4828 e1000_phy_powerdown_workaround(&adapter->hw);
4829
edd106fc
AK		 4830 if (netif_running(netdev))
4831 e1000_free_irq(adapter);
4832
b55ccb35
JK		 4833 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4834 * would have already happened in close and is redundant. */
4835 e1000_release_hw_control(adapter);
2d7edb92 4836
1da177e4 4837 pci_disable_device(pdev);
240b1710 4838
d0e027db 4839 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4840
4841 return 0;
4842}
4843
2f82665f 4844#ifdef CONFIG_PM
1da177e4
LT		 4845static int
4846e1000_resume(struct pci_dev *pdev)
4847{
4848 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4849 struct e1000_adapter *adapter = netdev_priv(netdev);
3d1dd8cb 4850 uint32_t manc, err;
1da177e4 4851
d0e027db 4852 pci_set_power_state(pdev, PCI_D0);
2f82665f 4853 e1000_pci_restore_state(adapter);
3d1dd8cb
AK		 4854 if ((err = pci_enable_device(pdev))) {
4855 printk(KERN_ERR "e1000: Cannot enable PCI device from suspend\n");
4856 return err;
4857 }
a4cb847d 4858 pci_set_master(pdev);
1da177e4 4859
d0e027db
AK		 4860 pci_enable_wake(pdev, PCI_D3hot, 0);
4861 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4 4862
edd106fc
AK		 4863 if (netif_running(netdev) && (err = e1000_request_irq(adapter)))
4864 return err;
4865
4866 e1000_power_up_phy(adapter);
1da177e4
LT		 4867 e1000_reset(adapter);
4868 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4869
96838a40 4870 if (netif_running(netdev))
1da177e4
LT		 4871 e1000_up(adapter);
4872
4873 netif_device_attach(netdev);
4874
4ccc12ae
JB		 4875 if (adapter->hw.mac_type >= e1000_82540 &&
4876 adapter->hw.mac_type < e1000_82571 &&
4877 adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4878 manc = E1000_READ_REG(&adapter->hw, MANC);
4879 manc &= ~(E1000_MANC_ARP_EN);
4880 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4881 }
4882
b55ccb35
JK		 4883 /* If the controller is 82573 and f/w is AMT, do not set
4884 * DRV_LOAD until the interface is up. For all other cases,
4885 * let the f/w know that the h/w is now under the control
4886 * of the driver. */
4887 if (adapter->hw.mac_type != e1000_82573 ||
4888 !e1000_check_mng_mode(&adapter->hw))
4889 e1000_get_hw_control(adapter);
2d7edb92 4890
1da177e4
LT		 4891 return 0;
4892}
4893#endif
c653e635
AK		 4894
4895static void e1000_shutdown(struct pci_dev *pdev)
4896{
4897 e1000_suspend(pdev, PMSG_SUSPEND);
4898}
4899
1da177e4
LT		 4900#ifdef CONFIG_NET_POLL_CONTROLLER
4901/*
4902 * Polling 'interrupt' - used by things like netconsole to send skbs
4903 * without having to re-enable interrupts. It's not called while
4904 * the interrupt routine is executing.
4905 */
4906static void
2648345f 4907e1000_netpoll(struct net_device *netdev)
1da177e4 4908{
60490fe0 4909 struct e1000_adapter *adapter = netdev_priv(netdev);
d3d9e484 4910
1da177e4 4911 disable_irq(adapter->pdev->irq);
7d12e780 4912 e1000_intr(adapter->pdev->irq, netdev);
c4cfe567 4913 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4914#ifndef CONFIG_E1000_NAPI
4915 adapter->clean_rx(adapter, adapter->rx_ring);
4916#endif
1da177e4
LT		 4917 enable_irq(adapter->pdev->irq);
4918}
4919#endif
4920
9026729b
AK		 4921/**
4922 * e1000_io_error_detected - called when PCI error is detected
4923 * @pdev: Pointer to PCI device
4924 * @state: The current pci conneection state
4925 *
4926 * This function is called after a PCI bus error affecting
4927 * this device has been detected.
4928 */
4929static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4930{
4931 struct net_device *netdev = pci_get_drvdata(pdev);
4932 struct e1000_adapter *adapter = netdev->priv;
4933
4934 netif_device_detach(netdev);
4935
4936 if (netif_running(netdev))
4937 e1000_down(adapter);
72e8d6bb 4938 pci_disable_device(pdev);
9026729b
AK		 4939
4940 /* Request a slot slot reset. */
4941 return PCI_ERS_RESULT_NEED_RESET;
4942}
4943
4944/**
4945 * e1000_io_slot_reset - called after the pci bus has been reset.
4946 * @pdev: Pointer to PCI device
4947 *
4948 * Restart the card from scratch, as if from a cold-boot. Implementation
4949 * resembles the first-half of the e1000_resume routine.
4950 */
4951static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
4952{
4953 struct net_device *netdev = pci_get_drvdata(pdev);
4954 struct e1000_adapter *adapter = netdev->priv;
4955
4956 if (pci_enable_device(pdev)) {
4957 printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n");
4958 return PCI_ERS_RESULT_DISCONNECT;
4959 }
4960 pci_set_master(pdev);
4961
dbf38c94
LV		 4962 pci_enable_wake(pdev, PCI_D3hot, 0);
4963 pci_enable_wake(pdev, PCI_D3cold, 0);
9026729b 4964
9026729b
AK		 4965 e1000_reset(adapter);
4966 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4967
4968 return PCI_ERS_RESULT_RECOVERED;
4969}
4970
4971/**
4972 * e1000_io_resume - called when traffic can start flowing again.
4973 * @pdev: Pointer to PCI device
4974 *
4975 * This callback is called when the error recovery driver tells us that
4976 * its OK to resume normal operation. Implementation resembles the
4977 * second-half of the e1000_resume routine.
4978 */
4979static void e1000_io_resume(struct pci_dev *pdev)
4980{
4981 struct net_device *netdev = pci_get_drvdata(pdev);
4982 struct e1000_adapter *adapter = netdev->priv;
4983 uint32_t manc, swsm;
4984
4985 if (netif_running(netdev)) {
4986 if (e1000_up(adapter)) {
4987 printk("e1000: can't bring device back up after reset\n");
4988 return;
4989 }
4990 }
4991
4992 netif_device_attach(netdev);
4993
4994 if (adapter->hw.mac_type >= e1000_82540 &&
4ccc12ae 4995 adapter->hw.mac_type < e1000_82571 &&
9026729b
AK		 4996 adapter->hw.media_type == e1000_media_type_copper) {
4997 manc = E1000_READ_REG(&adapter->hw, MANC);
4998 manc &= ~(E1000_MANC_ARP_EN);
4999 E1000_WRITE_REG(&adapter->hw, MANC, manc);
5000 }
5001
5002 switch (adapter->hw.mac_type) {
5003 case e1000_82573:
5004 swsm = E1000_READ_REG(&adapter->hw, SWSM);
5005 E1000_WRITE_REG(&adapter->hw, SWSM,
5006 swsm | E1000_SWSM_DRV_LOAD);
5007 break;
5008 default:
5009 break;
5010 }
5011
5012 if (netif_running(netdev))
5013 mod_timer(&adapter->watchdog_timer, jiffies);
5014}
5015
1da177e4 5016/* e1000_main.c */
Linux kernel - Deliverables
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