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[PATCH] e1000: Added interrupt auto mask support
[deliverable/linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
2b02893e
MC		 32 * 6.0.58 4/20/05
33 * o Accepted ethtool cleanup patch from Stephen Hemminger
2648345f
MC		 34 * 6.0.44+ 2/15/05
35 * o applied Anton's patch to resolve tx hang in hardware
36 * o Applied Andrew Mortons patch - e1000 stops working after resume
1da177e4
LT		 37 */
38
39char e1000_driver_name[] = "e1000";
3ad2cc67 40static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 41#ifndef CONFIG_E1000_NAPI
42#define DRIVERNAPI
43#else
44#define DRIVERNAPI "-NAPI"
45#endif
4ee9c020 46#define DRV_VERSION "6.3.9-k2"DRIVERNAPI
1da177e4 47char e1000_driver_version[] = DRV_VERSION;
3ad2cc67 48static char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
1da177e4
LT		 49
50/* e1000_pci_tbl - PCI Device ID Table
51 *
52 * Last entry must be all 0s
53 *
54 * Macro expands to...
55 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
56 */
57static struct pci_device_id e1000_pci_tbl[] = {
58 INTEL_E1000_ETHERNET_DEVICE(0x1000),
59 INTEL_E1000_ETHERNET_DEVICE(0x1001),
60 INTEL_E1000_ETHERNET_DEVICE(0x1004),
61 INTEL_E1000_ETHERNET_DEVICE(0x1008),
62 INTEL_E1000_ETHERNET_DEVICE(0x1009),
63 INTEL_E1000_ETHERNET_DEVICE(0x100C),
64 INTEL_E1000_ETHERNET_DEVICE(0x100D),
65 INTEL_E1000_ETHERNET_DEVICE(0x100E),
66 INTEL_E1000_ETHERNET_DEVICE(0x100F),
67 INTEL_E1000_ETHERNET_DEVICE(0x1010),
68 INTEL_E1000_ETHERNET_DEVICE(0x1011),
69 INTEL_E1000_ETHERNET_DEVICE(0x1012),
70 INTEL_E1000_ETHERNET_DEVICE(0x1013),
71 INTEL_E1000_ETHERNET_DEVICE(0x1014),
72 INTEL_E1000_ETHERNET_DEVICE(0x1015),
73 INTEL_E1000_ETHERNET_DEVICE(0x1016),
74 INTEL_E1000_ETHERNET_DEVICE(0x1017),
75 INTEL_E1000_ETHERNET_DEVICE(0x1018),
76 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 77 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 78 INTEL_E1000_ETHERNET_DEVICE(0x101D),
79 INTEL_E1000_ETHERNET_DEVICE(0x101E),
80 INTEL_E1000_ETHERNET_DEVICE(0x1026),
81 INTEL_E1000_ETHERNET_DEVICE(0x1027),
82 INTEL_E1000_ETHERNET_DEVICE(0x1028),
07b8fede
MC		 83 INTEL_E1000_ETHERNET_DEVICE(0x105E),
84 INTEL_E1000_ETHERNET_DEVICE(0x105F),
85 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 86 INTEL_E1000_ETHERNET_DEVICE(0x1075),
87 INTEL_E1000_ETHERNET_DEVICE(0x1076),
88 INTEL_E1000_ETHERNET_DEVICE(0x1077),
89 INTEL_E1000_ETHERNET_DEVICE(0x1078),
90 INTEL_E1000_ETHERNET_DEVICE(0x1079),
91 INTEL_E1000_ETHERNET_DEVICE(0x107A),
92 INTEL_E1000_ETHERNET_DEVICE(0x107B),
93 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 94 INTEL_E1000_ETHERNET_DEVICE(0x107D),
95 INTEL_E1000_ETHERNET_DEVICE(0x107E),
96 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 97 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 98 INTEL_E1000_ETHERNET_DEVICE(0x108B),
99 INTEL_E1000_ETHERNET_DEVICE(0x108C),
07b8fede 100 INTEL_E1000_ETHERNET_DEVICE(0x109A),
1da177e4
LT		 101 /* required last entry */
102 {0,}
103};
104
105MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
106
107int e1000_up(struct e1000_adapter *adapter);
108void e1000_down(struct e1000_adapter *adapter);
109void e1000_reset(struct e1000_adapter *adapter);
110int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
581d708e
MC		 111int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
112int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
113void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
114void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67
AB		 115static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
116 struct e1000_tx_ring *txdr);
117static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
118 struct e1000_rx_ring *rxdr);
119static void e1000_free_tx_resources(struct e1000_adapter *adapter,
120 struct e1000_tx_ring *tx_ring);
121static void e1000_free_rx_resources(struct e1000_adapter *adapter,
122 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 123void e1000_update_stats(struct e1000_adapter *adapter);
124
125/* Local Function Prototypes */
126
127static int e1000_init_module(void);
128static void e1000_exit_module(void);
129static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
130static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e
MC		 131static int e1000_alloc_queues(struct e1000_adapter *adapter);
132#ifdef CONFIG_E1000_MQ
133static void e1000_setup_queue_mapping(struct e1000_adapter *adapter);
134#endif
1da177e4
LT		 135static int e1000_sw_init(struct e1000_adapter *adapter);
136static int e1000_open(struct net_device *netdev);
137static int e1000_close(struct net_device *netdev);
138static void e1000_configure_tx(struct e1000_adapter *adapter);
139static void e1000_configure_rx(struct e1000_adapter *adapter);
140static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 141static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
142static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
143static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
144 struct e1000_tx_ring *tx_ring);
145static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
146 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 147static void e1000_set_multi(struct net_device *netdev);
148static void e1000_update_phy_info(unsigned long data);
149static void e1000_watchdog(unsigned long data);
150static void e1000_watchdog_task(struct e1000_adapter *adapter);
151static void e1000_82547_tx_fifo_stall(unsigned long data);
152static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
153static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
154static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
155static int e1000_set_mac(struct net_device *netdev, void *p);
156static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 157static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
158 struct e1000_tx_ring *tx_ring);
1da177e4 159#ifdef CONFIG_E1000_NAPI
581d708e 160static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 161static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 162 struct e1000_rx_ring *rx_ring,
1da177e4 163 int *work_done, int work_to_do);
2d7edb92 164static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 165 struct e1000_rx_ring *rx_ring,
2d7edb92 166 int *work_done, int work_to_do);
1da177e4 167#else
581d708e
MC		 168static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
169 struct e1000_rx_ring *rx_ring);
170static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
171 struct e1000_rx_ring *rx_ring);
1da177e4 172#endif
581d708e
MC		 173static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
174 struct e1000_rx_ring *rx_ring);
175static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
176 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 177static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
178static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
179 int cmd);
180void e1000_set_ethtool_ops(struct net_device *netdev);
181static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
182static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
183static void e1000_tx_timeout(struct net_device *dev);
184static void e1000_tx_timeout_task(struct net_device *dev);
185static void e1000_smartspeed(struct e1000_adapter *adapter);
186static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
187 struct sk_buff *skb);
188
189static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
190static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
191static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
192static void e1000_restore_vlan(struct e1000_adapter *adapter);
193
1da177e4 194#ifdef CONFIG_PM
977e74b5 195static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 196static int e1000_resume(struct pci_dev *pdev);
197#endif
198
199#ifdef CONFIG_NET_POLL_CONTROLLER
200/* for netdump / net console */
201static void e1000_netpoll (struct net_device *netdev);
202#endif
203
24025e4e
MC		 204#ifdef CONFIG_E1000_MQ
205/* for multiple Rx queues */
206void e1000_rx_schedule(void *data);
207#endif
208
1da177e4
LT		 209/* Exported from other modules */
210
211extern void e1000_check_options(struct e1000_adapter *adapter);
212
213static struct pci_driver e1000_driver = {
214 .name = e1000_driver_name,
215 .id_table = e1000_pci_tbl,
216 .probe = e1000_probe,
217 .remove = __devexit_p(e1000_remove),
218 /* Power Managment Hooks */
219#ifdef CONFIG_PM
220 .suspend = e1000_suspend,
221 .resume = e1000_resume
222#endif
223};
224
225MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
226MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
227MODULE_LICENSE("GPL");
228MODULE_VERSION(DRV_VERSION);
229
230static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
231module_param(debug, int, 0);
232MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
233
234/**
235 * e1000_init_module - Driver Registration Routine
236 *
237 * e1000_init_module is the first routine called when the driver is
238 * loaded. All it does is register with the PCI subsystem.
239 **/
240
241static int __init
242e1000_init_module(void)
243{
244 int ret;
245 printk(KERN_INFO "%s - version %s\n",
246 e1000_driver_string, e1000_driver_version);
247
248 printk(KERN_INFO "%s\n", e1000_copyright);
249
250 ret = pci_module_init(&e1000_driver);
8b378def 251
1da177e4
LT		 252 return ret;
253}
254
255module_init(e1000_init_module);
256
257/**
258 * e1000_exit_module - Driver Exit Cleanup Routine
259 *
260 * e1000_exit_module is called just before the driver is removed
261 * from memory.
262 **/
263
264static void __exit
265e1000_exit_module(void)
266{
1da177e4
LT		 267 pci_unregister_driver(&e1000_driver);
268}
269
270module_exit(e1000_exit_module);
271
272/**
273 * e1000_irq_disable - Mask off interrupt generation on the NIC
274 * @adapter: board private structure
275 **/
276
277static inline void
278e1000_irq_disable(struct e1000_adapter *adapter)
279{
280 atomic_inc(&adapter->irq_sem);
281 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
282 E1000_WRITE_FLUSH(&adapter->hw);
283 synchronize_irq(adapter->pdev->irq);
284}
285
286/**
287 * e1000_irq_enable - Enable default interrupt generation settings
288 * @adapter: board private structure
289 **/
290
291static inline void
292e1000_irq_enable(struct e1000_adapter *adapter)
293{
294 if(likely(atomic_dec_and_test(&adapter->irq_sem))) {
295 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
296 E1000_WRITE_FLUSH(&adapter->hw);
297 }
298}
3ad2cc67
AB		 299
300static void
2d7edb92
MC		 301e1000_update_mng_vlan(struct e1000_adapter *adapter)
302{
303 struct net_device *netdev = adapter->netdev;
304 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
305 uint16_t old_vid = adapter->mng_vlan_id;
306 if(adapter->vlgrp) {
307 if(!adapter->vlgrp->vlan_devices[vid]) {
308 if(adapter->hw.mng_cookie.status &
309 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
310 e1000_vlan_rx_add_vid(netdev, vid);
311 adapter->mng_vlan_id = vid;
312 } else
313 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
314
315 if((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
316 (vid != old_vid) &&
317 !adapter->vlgrp->vlan_devices[old_vid])
318 e1000_vlan_rx_kill_vid(netdev, old_vid);
319 }
320 }
321}
b55ccb35
JK		 322
323/**
324 * e1000_release_hw_control - release control of the h/w to f/w
325 * @adapter: address of board private structure
326 *
327 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
328 * For ASF and Pass Through versions of f/w this means that the
329 * driver is no longer loaded. For AMT version (only with 82573) i
330 * of the f/w this means that the netowrk i/f is closed.
331 *
332 **/
333
334static inline void
335e1000_release_hw_control(struct e1000_adapter *adapter)
336{
337 uint32_t ctrl_ext;
338 uint32_t swsm;
339
340 /* Let firmware taken over control of h/w */
341 switch (adapter->hw.mac_type) {
342 case e1000_82571:
343 case e1000_82572:
344 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
345 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
346 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
347 break;
348 case e1000_82573:
349 swsm = E1000_READ_REG(&adapter->hw, SWSM);
350 E1000_WRITE_REG(&adapter->hw, SWSM,
351 swsm & ~E1000_SWSM_DRV_LOAD);
352 default:
353 break;
354 }
355}
356
357/**
358 * e1000_get_hw_control - get control of the h/w from f/w
359 * @adapter: address of board private structure
360 *
361 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
362 * For ASF and Pass Through versions of f/w this means that
363 * the driver is loaded. For AMT version (only with 82573)
364 * of the f/w this means that the netowrk i/f is open.
365 *
366 **/
367
368static inline void
369e1000_get_hw_control(struct e1000_adapter *adapter)
370{
371 uint32_t ctrl_ext;
372 uint32_t swsm;
373 /* Let firmware know the driver has taken over */
374 switch (adapter->hw.mac_type) {
375 case e1000_82571:
376 case e1000_82572:
377 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
378 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
379 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
380 break;
381 case e1000_82573:
382 swsm = E1000_READ_REG(&adapter->hw, SWSM);
383 E1000_WRITE_REG(&adapter->hw, SWSM,
384 swsm | E1000_SWSM_DRV_LOAD);
385 break;
386 default:
387 break;
388 }
389}
390
1da177e4
LT		 391int
392e1000_up(struct e1000_adapter *adapter)
393{
394 struct net_device *netdev = adapter->netdev;
581d708e 395 int i, err;
1da177e4
LT		 396
397 /* hardware has been reset, we need to reload some things */
398
399 /* Reset the PHY if it was previously powered down */
400 if(adapter->hw.media_type == e1000_media_type_copper) {
401 uint16_t mii_reg;
402 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
403 if(mii_reg & MII_CR_POWER_DOWN)
404 e1000_phy_reset(&adapter->hw);
405 }
406
407 e1000_set_multi(netdev);
408
409 e1000_restore_vlan(adapter);
410
411 e1000_configure_tx(adapter);
412 e1000_setup_rctl(adapter);
413 e1000_configure_rx(adapter);
f56799ea 414 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e 415 adapter->alloc_rx_buf(adapter, &adapter->rx_ring[i]);
f56799ea 416 }
1da177e4 417
fa4f7ef3
MC		 418#ifdef CONFIG_PCI_MSI
419 if(adapter->hw.mac_type > e1000_82547_rev_2) {
420 adapter->have_msi = TRUE;
421 if((err = pci_enable_msi(adapter->pdev))) {
422 DPRINTK(PROBE, ERR,
423 "Unable to allocate MSI interrupt Error: %d\n", err);
424 adapter->have_msi = FALSE;
425 }
426 }
427#endif
1da177e4
LT		 428 if((err = request_irq(adapter->pdev->irq, &e1000_intr,
429 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 430 netdev->name, netdev))) {
431 DPRINTK(PROBE, ERR,
432 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 433 return err;
2648345f 434 }
1da177e4 435
7bfa4816
JK		 436#ifdef CONFIG_E1000_MQ
437 e1000_setup_queue_mapping(adapter);
438#endif
439
440 adapter->tx_queue_len = netdev->tx_queue_len;
441
1da177e4 442 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 443
444#ifdef CONFIG_E1000_NAPI
445 netif_poll_enable(netdev);
446#endif
5de55624
MC		 447 e1000_irq_enable(adapter);
448
1da177e4
LT		 449 return 0;
450}
451
452void
453e1000_down(struct e1000_adapter *adapter)
454{
455 struct net_device *netdev = adapter->netdev;
57128197
JK		 456 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
457 e1000_check_mng_mode(&adapter->hw);
1da177e4
LT		 458
459 e1000_irq_disable(adapter);
24025e4e
MC		 460#ifdef CONFIG_E1000_MQ
461 while (atomic_read(&adapter->rx_sched_call_data.count) != 0);
462#endif
1da177e4 463 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3
MC		 464#ifdef CONFIG_PCI_MSI
465 if(adapter->hw.mac_type > e1000_82547_rev_2 &&
466 adapter->have_msi == TRUE)
467 pci_disable_msi(adapter->pdev);
468#endif
1da177e4
LT		 469 del_timer_sync(&adapter->tx_fifo_stall_timer);
470 del_timer_sync(&adapter->watchdog_timer);
471 del_timer_sync(&adapter->phy_info_timer);
472
473#ifdef CONFIG_E1000_NAPI
474 netif_poll_disable(netdev);
475#endif
7bfa4816 476 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 477 adapter->link_speed = 0;
478 adapter->link_duplex = 0;
479 netif_carrier_off(netdev);
480 netif_stop_queue(netdev);
481
482 e1000_reset(adapter);
581d708e
MC		 483 e1000_clean_all_tx_rings(adapter);
484 e1000_clean_all_rx_rings(adapter);
1da177e4 485
57128197
JK		 486 /* Power down the PHY so no link is implied when interface is down *
487 * The PHY cannot be powered down if any of the following is TRUE *
488 * (a) WoL is enabled
489 * (b) AMT is active
490 * (c) SoL/IDER session is active */
491 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
2d7edb92 492 adapter->hw.media_type == e1000_media_type_copper &&
57128197
JK		 493 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
494 !mng_mode_enabled &&
495 !e1000_check_phy_reset_block(&adapter->hw)) {
1da177e4
LT		 496 uint16_t mii_reg;
497 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
498 mii_reg |= MII_CR_POWER_DOWN;
499 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 500 mdelay(1);
1da177e4
LT		 501 }
502}
503
504void
505e1000_reset(struct e1000_adapter *adapter)
506{
2d7edb92 507 uint32_t pba, manc;
1125ecbc 508 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 509
510 /* Repartition Pba for greater than 9k mtu
511 * To take effect CTRL.RST is required.
512 */
513
2d7edb92
MC		 514 switch (adapter->hw.mac_type) {
515 case e1000_82547:
0e6ef3e0 516 case e1000_82547_rev_2:
2d7edb92
MC		 517 pba = E1000_PBA_30K;
518 break;
868d5309
MC		 519 case e1000_82571:
520 case e1000_82572:
521 pba = E1000_PBA_38K;
522 break;
2d7edb92
MC		 523 case e1000_82573:
524 pba = E1000_PBA_12K;
525 break;
526 default:
527 pba = E1000_PBA_48K;
528 break;
529 }
530
1125ecbc 531 if((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 532 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 533 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 534
535
536 if(adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 537 adapter->tx_fifo_head = 0;
538 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
539 adapter->tx_fifo_size =
540 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
541 atomic_set(&adapter->tx_fifo_stall, 0);
542 }
2d7edb92 543
1da177e4
LT		 544 E1000_WRITE_REG(&adapter->hw, PBA, pba);
545
546 /* flow control settings */
f11b7f85
JK		 547 /* Set the FC high water mark to 90% of the FIFO size.
548 * Required to clear last 3 LSB */
549 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
550
551 adapter->hw.fc_high_water = fc_high_water_mark;
552 adapter->hw.fc_low_water = fc_high_water_mark - 8;
1da177e4
LT		 553 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
554 adapter->hw.fc_send_xon = 1;
555 adapter->hw.fc = adapter->hw.original_fc;
556
2d7edb92 557 /* Allow time for pending master requests to run */
1da177e4
LT		 558 e1000_reset_hw(&adapter->hw);
559 if(adapter->hw.mac_type >= e1000_82544)
560 E1000_WRITE_REG(&adapter->hw, WUC, 0);
561 if(e1000_init_hw(&adapter->hw))
562 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 563 e1000_update_mng_vlan(adapter);
1da177e4
LT		 564 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
565 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
566
567 e1000_reset_adaptive(&adapter->hw);
568 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 569 if (adapter->en_mng_pt) {
570 manc = E1000_READ_REG(&adapter->hw, MANC);
571 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
572 E1000_WRITE_REG(&adapter->hw, MANC, manc);
573 }
1da177e4
LT		 574}
575
576/**
577 * e1000_probe - Device Initialization Routine
578 * @pdev: PCI device information struct
579 * @ent: entry in e1000_pci_tbl
580 *
581 * Returns 0 on success, negative on failure
582 *
583 * e1000_probe initializes an adapter identified by a pci_dev structure.
584 * The OS initialization, configuring of the adapter private structure,
585 * and a hardware reset occur.
586 **/
587
588static int __devinit
589e1000_probe(struct pci_dev *pdev,
590 const struct pci_device_id *ent)
591{
592 struct net_device *netdev;
593 struct e1000_adapter *adapter;
2d7edb92 594 unsigned long mmio_start, mmio_len;
2d7edb92 595
1da177e4 596 static int cards_found = 0;
2d7edb92 597 int i, err, pci_using_dac;
1da177e4
LT		 598 uint16_t eeprom_data;
599 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
1da177e4
LT		 600 if((err = pci_enable_device(pdev)))
601 return err;
602
603 if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
604 pci_using_dac = 1;
605 } else {
606 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
607 E1000_ERR("No usable DMA configuration, aborting\n");
608 return err;
609 }
610 pci_using_dac = 0;
611 }
612
613 if((err = pci_request_regions(pdev, e1000_driver_name)))
614 return err;
615
616 pci_set_master(pdev);
617
618 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
619 if(!netdev) {
620 err = -ENOMEM;
621 goto err_alloc_etherdev;
622 }
623
624 SET_MODULE_OWNER(netdev);
625 SET_NETDEV_DEV(netdev, &pdev->dev);
626
627 pci_set_drvdata(pdev, netdev);
60490fe0 628 adapter = netdev_priv(netdev);
1da177e4
LT		 629 adapter->netdev = netdev;
630 adapter->pdev = pdev;
631 adapter->hw.back = adapter;
632 adapter->msg_enable = (1 << debug) - 1;
633
634 mmio_start = pci_resource_start(pdev, BAR_0);
635 mmio_len = pci_resource_len(pdev, BAR_0);
636
637 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
638 if(!adapter->hw.hw_addr) {
639 err = -EIO;
640 goto err_ioremap;
641 }
642
643 for(i = BAR_1; i <= BAR_5; i++) {
644 if(pci_resource_len(pdev, i) == 0)
645 continue;
646 if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
647 adapter->hw.io_base = pci_resource_start(pdev, i);
648 break;
649 }
650 }
651
652 netdev->open = &e1000_open;
653 netdev->stop = &e1000_close;
654 netdev->hard_start_xmit = &e1000_xmit_frame;
655 netdev->get_stats = &e1000_get_stats;
656 netdev->set_multicast_list = &e1000_set_multi;
657 netdev->set_mac_address = &e1000_set_mac;
658 netdev->change_mtu = &e1000_change_mtu;
659 netdev->do_ioctl = &e1000_ioctl;
660 e1000_set_ethtool_ops(netdev);
661 netdev->tx_timeout = &e1000_tx_timeout;
662 netdev->watchdog_timeo = 5 * HZ;
663#ifdef CONFIG_E1000_NAPI
664 netdev->poll = &e1000_clean;
665 netdev->weight = 64;
666#endif
667 netdev->vlan_rx_register = e1000_vlan_rx_register;
668 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
669 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
670#ifdef CONFIG_NET_POLL_CONTROLLER
671 netdev->poll_controller = e1000_netpoll;
672#endif
673 strcpy(netdev->name, pci_name(pdev));
674
675 netdev->mem_start = mmio_start;
676 netdev->mem_end = mmio_start + mmio_len;
677 netdev->base_addr = adapter->hw.io_base;
678
679 adapter->bd_number = cards_found;
680
681 /* setup the private structure */
682
683 if((err = e1000_sw_init(adapter)))
684 goto err_sw_init;
685
2d7edb92
MC		 686 if((err = e1000_check_phy_reset_block(&adapter->hw)))
687 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
688
1da177e4
LT		 689 if(adapter->hw.mac_type >= e1000_82543) {
690 netdev->features = NETIF_F_SG |
691 NETIF_F_HW_CSUM |
692 NETIF_F_HW_VLAN_TX |
693 NETIF_F_HW_VLAN_RX |
694 NETIF_F_HW_VLAN_FILTER;
695 }
696
697#ifdef NETIF_F_TSO
698 if((adapter->hw.mac_type >= e1000_82544) &&
699 (adapter->hw.mac_type != e1000_82547))
700 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 701
702#ifdef NETIF_F_TSO_IPV6
703 if(adapter->hw.mac_type > e1000_82547_rev_2)
704 netdev->features |= NETIF_F_TSO_IPV6;
705#endif
1da177e4
LT		 706#endif
707 if(pci_using_dac)
708 netdev->features |= NETIF_F_HIGHDMA;
709
710 /* hard_start_xmit is safe against parallel locking */
711 netdev->features |= NETIF_F_LLTX;
712
2d7edb92
MC		 713 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
714
1da177e4
LT		 715 /* before reading the EEPROM, reset the controller to
716 * put the device in a known good starting state */
717
718 e1000_reset_hw(&adapter->hw);
719
720 /* make sure the EEPROM is good */
721
722 if(e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
723 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
724 err = -EIO;
725 goto err_eeprom;
726 }
727
728 /* copy the MAC address out of the EEPROM */
729
2648345f 730 if(e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 731 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
732 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 733 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 734
9beb0ac1 735 if(!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 736 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
737 err = -EIO;
738 goto err_eeprom;
739 }
740
741 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
742
743 e1000_get_bus_info(&adapter->hw);
744
745 init_timer(&adapter->tx_fifo_stall_timer);
746 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
747 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
748
749 init_timer(&adapter->watchdog_timer);
750 adapter->watchdog_timer.function = &e1000_watchdog;
751 adapter->watchdog_timer.data = (unsigned long) adapter;
752
753 INIT_WORK(&adapter->watchdog_task,
754 (void (*)(void *))e1000_watchdog_task, adapter);
755
756 init_timer(&adapter->phy_info_timer);
757 adapter->phy_info_timer.function = &e1000_update_phy_info;
758 adapter->phy_info_timer.data = (unsigned long) adapter;
759
760 INIT_WORK(&adapter->tx_timeout_task,
761 (void (*)(void *))e1000_tx_timeout_task, netdev);
762
763 /* we're going to reset, so assume we have no link for now */
764
765 netif_carrier_off(netdev);
766 netif_stop_queue(netdev);
767
768 e1000_check_options(adapter);
769
770 /* Initial Wake on LAN setting
771 * If APM wake is enabled in the EEPROM,
772 * enable the ACPI Magic Packet filter
773 */
774
775 switch(adapter->hw.mac_type) {
776 case e1000_82542_rev2_0:
777 case e1000_82542_rev2_1:
778 case e1000_82543:
779 break;
780 case e1000_82544:
781 e1000_read_eeprom(&adapter->hw,
782 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
783 eeprom_apme_mask = E1000_EEPROM_82544_APM;
784 break;
785 case e1000_82546:
786 case e1000_82546_rev_3:
fd803241 787 case e1000_82571:
1da177e4
LT		 788 if((E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
789 && (adapter->hw.media_type == e1000_media_type_copper)) {
790 e1000_read_eeprom(&adapter->hw,
791 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
792 break;
793 }
794 /* Fall Through */
795 default:
796 e1000_read_eeprom(&adapter->hw,
797 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
798 break;
799 }
800 if(eeprom_data & eeprom_apme_mask)
801 adapter->wol |= E1000_WUFC_MAG;
802
803 /* reset the hardware with the new settings */
804 e1000_reset(adapter);
805
b55ccb35
JK		 806 /* If the controller is 82573 and f/w is AMT, do not set
807 * DRV_LOAD until the interface is up. For all other cases,
808 * let the f/w know that the h/w is now under the control
809 * of the driver. */
810 if (adapter->hw.mac_type != e1000_82573 ||
811 !e1000_check_mng_mode(&adapter->hw))
812 e1000_get_hw_control(adapter);
2d7edb92 813
1da177e4
LT		 814 strcpy(netdev->name, "eth%d");
815 if((err = register_netdev(netdev)))
816 goto err_register;
817
818 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
819
820 cards_found++;
821 return 0;
822
823err_register:
824err_sw_init:
825err_eeprom:
826 iounmap(adapter->hw.hw_addr);
827err_ioremap:
828 free_netdev(netdev);
829err_alloc_etherdev:
830 pci_release_regions(pdev);
831 return err;
832}
833
834/**
835 * e1000_remove - Device Removal Routine
836 * @pdev: PCI device information struct
837 *
838 * e1000_remove is called by the PCI subsystem to alert the driver
839 * that it should release a PCI device. The could be caused by a
840 * Hot-Plug event, or because the driver is going to be removed from
841 * memory.
842 **/
843
844static void __devexit
845e1000_remove(struct pci_dev *pdev)
846{
847 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 848 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 849 uint32_t manc;
581d708e
MC		 850#ifdef CONFIG_E1000_NAPI
851 int i;
852#endif
1da177e4 853
be2b28ed
JG		 854 flush_scheduled_work();
855
1da177e4
LT		 856 if(adapter->hw.mac_type >= e1000_82540 &&
857 adapter->hw.media_type == e1000_media_type_copper) {
858 manc = E1000_READ_REG(&adapter->hw, MANC);
859 if(manc & E1000_MANC_SMBUS_EN) {
860 manc |= E1000_MANC_ARP_EN;
861 E1000_WRITE_REG(&adapter->hw, MANC, manc);
862 }
863 }
864
b55ccb35
JK		 865 /* Release control of h/w to f/w. If f/w is AMT enabled, this
866 * would have already happened in close and is redundant. */
867 e1000_release_hw_control(adapter);
2d7edb92 868
1da177e4 869 unregister_netdev(netdev);
581d708e 870#ifdef CONFIG_E1000_NAPI
f56799ea 871 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 872 __dev_put(&adapter->polling_netdev[i]);
873#endif
1da177e4 874
2d7edb92
MC		 875 if(!e1000_check_phy_reset_block(&adapter->hw))
876 e1000_phy_hw_reset(&adapter->hw);
1da177e4 877
24025e4e
MC		 878 kfree(adapter->tx_ring);
879 kfree(adapter->rx_ring);
880#ifdef CONFIG_E1000_NAPI
881 kfree(adapter->polling_netdev);
882#endif
883
1da177e4
LT		 884 iounmap(adapter->hw.hw_addr);
885 pci_release_regions(pdev);
886
24025e4e
MC		 887#ifdef CONFIG_E1000_MQ
888 free_percpu(adapter->cpu_netdev);
889 free_percpu(adapter->cpu_tx_ring);
890#endif
1da177e4
LT		 891 free_netdev(netdev);
892
893 pci_disable_device(pdev);
894}
895
896/**
897 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
898 * @adapter: board private structure to initialize
899 *
900 * e1000_sw_init initializes the Adapter private data structure.
901 * Fields are initialized based on PCI device information and
902 * OS network device settings (MTU size).
903 **/
904
905static int __devinit
906e1000_sw_init(struct e1000_adapter *adapter)
907{
908 struct e1000_hw *hw = &adapter->hw;
909 struct net_device *netdev = adapter->netdev;
910 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 911#ifdef CONFIG_E1000_NAPI
912 int i;
913#endif
1da177e4
LT		 914
915 /* PCI config space info */
916
917 hw->vendor_id = pdev->vendor;
918 hw->device_id = pdev->device;
919 hw->subsystem_vendor_id = pdev->subsystem_vendor;
920 hw->subsystem_id = pdev->subsystem_device;
921
922 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
923
924 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
925
926 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2d7edb92 927 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
1da177e4
LT		 928 hw->max_frame_size = netdev->mtu +
929 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
930 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
931
932 /* identify the MAC */
933
934 if(e1000_set_mac_type(hw)) {
935 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
936 return -EIO;
937 }
938
939 /* initialize eeprom parameters */
940
2d7edb92
MC		 941 if(e1000_init_eeprom_params(hw)) {
942 E1000_ERR("EEPROM initialization failed\n");
943 return -EIO;
944 }
1da177e4
LT		 945
946 switch(hw->mac_type) {
947 default:
948 break;
949 case e1000_82541:
950 case e1000_82547:
951 case e1000_82541_rev_2:
952 case e1000_82547_rev_2:
953 hw->phy_init_script = 1;
954 break;
955 }
956
957 e1000_set_media_type(hw);
958
959 hw->wait_autoneg_complete = FALSE;
960 hw->tbi_compatibility_en = TRUE;
961 hw->adaptive_ifs = TRUE;
962
963 /* Copper options */
964
965 if(hw->media_type == e1000_media_type_copper) {
966 hw->mdix = AUTO_ALL_MODES;
967 hw->disable_polarity_correction = FALSE;
968 hw->master_slave = E1000_MASTER_SLAVE;
969 }
970
24025e4e
MC		 971#ifdef CONFIG_E1000_MQ
972 /* Number of supported queues */
973 switch (hw->mac_type) {
974 case e1000_82571:
975 case e1000_82572:
f56799ea
JK		 976 /* These controllers support 2 tx queues, but with a single
977 * qdisc implementation, multiple tx queues aren't quite as
978 * interesting. If we can find a logical way of mapping
979 * flows to a queue, then perhaps we can up the num_tx_queue
980 * count back to its default. Until then, we run the risk of
981 * terrible performance due to SACK overload. */
982 adapter->num_tx_queues = 1;
983 adapter->num_rx_queues = 2;
24025e4e
MC		 984 break;
985 default:
f56799ea
JK		 986 adapter->num_tx_queues = 1;
987 adapter->num_rx_queues = 1;
24025e4e
MC		 988 break;
989 }
f56799ea
JK		 990 adapter->num_rx_queues = min(adapter->num_rx_queues, num_online_cpus());
991 adapter->num_tx_queues = min(adapter->num_tx_queues, num_online_cpus());
7bfa4816
JK		 992 DPRINTK(DRV, INFO, "Multiqueue Enabled: Rx Queue count = %u %s\n",
993 adapter->num_rx_queues,
994 ((adapter->num_rx_queues == 1)
995 ? ((num_online_cpus() > 1)
996 ? "(due to unsupported feature in current adapter)"
997 : "(due to unsupported system configuration)")
998 : ""));
999 DPRINTK(DRV, INFO, "Multiqueue Enabled: Tx Queue count = %u\n",
1000 adapter->num_tx_queues);
24025e4e 1001#else
f56799ea
JK		 1002 adapter->num_tx_queues = 1;
1003 adapter->num_rx_queues = 1;
24025e4e 1004#endif
581d708e
MC		 1005
1006 if (e1000_alloc_queues(adapter)) {
1007 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1008 return -ENOMEM;
1009 }
1010
1011#ifdef CONFIG_E1000_NAPI
f56799ea 1012 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1013 adapter->polling_netdev[i].priv = adapter;
1014 adapter->polling_netdev[i].poll = &e1000_clean;
1015 adapter->polling_netdev[i].weight = 64;
1016 dev_hold(&adapter->polling_netdev[i]);
1017 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1018 }
7bfa4816 1019 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1020#endif
1021
1da177e4
LT		 1022 atomic_set(&adapter->irq_sem, 1);
1023 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1024
1025 return 0;
1026}
1027
581d708e
MC		 1028/**
1029 * e1000_alloc_queues - Allocate memory for all rings
1030 * @adapter: board private structure to initialize
1031 *
1032 * We allocate one ring per queue at run-time since we don't know the
1033 * number of queues at compile-time. The polling_netdev array is
1034 * intended for Multiqueue, but should work fine with a single queue.
1035 **/
1036
1037static int __devinit
1038e1000_alloc_queues(struct e1000_adapter *adapter)
1039{
1040 int size;
1041
f56799ea 1042 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1043 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1044 if (!adapter->tx_ring)
1045 return -ENOMEM;
1046 memset(adapter->tx_ring, 0, size);
1047
f56799ea 1048 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1049 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1050 if (!adapter->rx_ring) {
1051 kfree(adapter->tx_ring);
1052 return -ENOMEM;
1053 }
1054 memset(adapter->rx_ring, 0, size);
1055
1056#ifdef CONFIG_E1000_NAPI
f56799ea 1057 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1058 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1059 if (!adapter->polling_netdev) {
1060 kfree(adapter->tx_ring);
1061 kfree(adapter->rx_ring);
1062 return -ENOMEM;
1063 }
1064 memset(adapter->polling_netdev, 0, size);
1065#endif
1066
7bfa4816
JK		 1067#ifdef CONFIG_E1000_MQ
1068 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1069 adapter->rx_sched_call_data.info = adapter->netdev;
1070
1071 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1072 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1073#endif
1074
581d708e
MC		 1075 return E1000_SUCCESS;
1076}
1077
24025e4e
MC		 1078#ifdef CONFIG_E1000_MQ
1079static void __devinit
1080e1000_setup_queue_mapping(struct e1000_adapter *adapter)
1081{
1082 int i, cpu;
1083
1084 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1085 adapter->rx_sched_call_data.info = adapter->netdev;
1086 cpus_clear(adapter->rx_sched_call_data.cpumask);
1087
1088 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1089 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1090
1091 lock_cpu_hotplug();
1092 i = 0;
1093 for_each_online_cpu(cpu) {
f56799ea 1094 *per_cpu_ptr(adapter->cpu_tx_ring, cpu) = &adapter->tx_ring[i % adapter->num_tx_queues];
24025e4e
MC		 1095 /* This is incomplete because we'd like to assign separate
1096 * physical cpus to these netdev polling structures and
1097 * avoid saturating a subset of cpus.
1098 */
f56799ea 1099 if (i < adapter->num_rx_queues) {
24025e4e 1100 *per_cpu_ptr(adapter->cpu_netdev, cpu) = &adapter->polling_netdev[i];
7bfa4816
JK		 1101 adapter->rx_ring[i].cpu = cpu;
1102 cpu_set(cpu, adapter->cpumask);
24025e4e
MC		 1103 } else
1104 *per_cpu_ptr(adapter->cpu_netdev, cpu) = NULL;
1105
1106 i++;
1107 }
1108 unlock_cpu_hotplug();
1109}
1110#endif
1111
1da177e4
LT		 1112/**
1113 * e1000_open - Called when a network interface is made active
1114 * @netdev: network interface device structure
1115 *
1116 * Returns 0 on success, negative value on failure
1117 *
1118 * The open entry point is called when a network interface is made
1119 * active by the system (IFF_UP). At this point all resources needed
1120 * for transmit and receive operations are allocated, the interrupt
1121 * handler is registered with the OS, the watchdog timer is started,
1122 * and the stack is notified that the interface is ready.
1123 **/
1124
1125static int
1126e1000_open(struct net_device *netdev)
1127{
60490fe0 1128 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1129 int err;
1130
1131 /* allocate transmit descriptors */
1132
581d708e 1133 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1134 goto err_setup_tx;
1135
1136 /* allocate receive descriptors */
1137
581d708e 1138 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1139 goto err_setup_rx;
1140
1141 if((err = e1000_up(adapter)))
1142 goto err_up;
2d7edb92
MC		 1143 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
1144 if((adapter->hw.mng_cookie.status &
1145 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1146 e1000_update_mng_vlan(adapter);
1147 }
1da177e4 1148
b55ccb35
JK		 1149 /* If AMT is enabled, let the firmware know that the network
1150 * interface is now open */
1151 if (adapter->hw.mac_type == e1000_82573 &&
1152 e1000_check_mng_mode(&adapter->hw))
1153 e1000_get_hw_control(adapter);
1154
1da177e4
LT		 1155 return E1000_SUCCESS;
1156
1157err_up:
581d708e 1158 e1000_free_all_rx_resources(adapter);
1da177e4 1159err_setup_rx:
581d708e 1160 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1161err_setup_tx:
1162 e1000_reset(adapter);
1163
1164 return err;
1165}
1166
1167/**
1168 * e1000_close - Disables a network interface
1169 * @netdev: network interface device structure
1170 *
1171 * Returns 0, this is not allowed to fail
1172 *
1173 * The close entry point is called when an interface is de-activated
1174 * by the OS. The hardware is still under the drivers control, but
1175 * needs to be disabled. A global MAC reset is issued to stop the
1176 * hardware, and all transmit and receive resources are freed.
1177 **/
1178
1179static int
1180e1000_close(struct net_device *netdev)
1181{
60490fe0 1182 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1183
1184 e1000_down(adapter);
1185
581d708e
MC		 1186 e1000_free_all_tx_resources(adapter);
1187 e1000_free_all_rx_resources(adapter);
1da177e4 1188
2d7edb92
MC		 1189 if((adapter->hw.mng_cookie.status &
1190 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1191 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1192 }
b55ccb35
JK		 1193
1194 /* If AMT is enabled, let the firmware know that the network
1195 * interface is now closed */
1196 if (adapter->hw.mac_type == e1000_82573 &&
1197 e1000_check_mng_mode(&adapter->hw))
1198 e1000_release_hw_control(adapter);
1199
1da177e4
LT		 1200 return 0;
1201}
1202
1203/**
1204 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1205 * @adapter: address of board private structure
2d7edb92
MC		 1206 * @start: address of beginning of memory
1207 * @len: length of memory
1da177e4
LT		 1208 **/
1209static inline boolean_t
1210e1000_check_64k_bound(struct e1000_adapter *adapter,
1211 void *start, unsigned long len)
1212{
1213 unsigned long begin = (unsigned long) start;
1214 unsigned long end = begin + len;
1215
2648345f
MC		 1216 /* First rev 82545 and 82546 need to not allow any memory
1217 * write location to cross 64k boundary due to errata 23 */
1da177e4 1218 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1219 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1220 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1221 }
1222
1223 return TRUE;
1224}
1225
1226/**
1227 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1228 * @adapter: board private structure
581d708e 1229 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1230 *
1231 * Return 0 on success, negative on failure
1232 **/
1233
3ad2cc67 1234static int
581d708e
MC		 1235e1000_setup_tx_resources(struct e1000_adapter *adapter,
1236 struct e1000_tx_ring *txdr)
1da177e4 1237{
1da177e4
LT		 1238 struct pci_dev *pdev = adapter->pdev;
1239 int size;
1240
1241 size = sizeof(struct e1000_buffer) * txdr->count;
a7ec15da
RT		 1242
1243 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
1da177e4 1244 if(!txdr->buffer_info) {
2648345f
MC		 1245 DPRINTK(PROBE, ERR,
1246 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1247 return -ENOMEM;
1248 }
1249 memset(txdr->buffer_info, 0, size);
1250
1251 /* round up to nearest 4K */
1252
1253 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1254 E1000_ROUNDUP(txdr->size, 4096);
1255
1256 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1257 if(!txdr->desc) {
1258setup_tx_desc_die:
1da177e4 1259 vfree(txdr->buffer_info);
2648345f
MC		 1260 DPRINTK(PROBE, ERR,
1261 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1262 return -ENOMEM;
1263 }
1264
2648345f 1265 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1266 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1267 void *olddesc = txdr->desc;
1268 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1269 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1270 "at %p\n", txdr->size, txdr->desc);
1271 /* Try again, without freeing the previous */
1da177e4 1272 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1da177e4 1273 if(!txdr->desc) {
2648345f 1274 /* Failed allocation, critical failure */
1da177e4
LT		 1275 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1276 goto setup_tx_desc_die;
1277 }
1278
1279 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1280 /* give up */
2648345f
MC		 1281 pci_free_consistent(pdev, txdr->size, txdr->desc,
1282 txdr->dma);
1da177e4
LT		 1283 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1284 DPRINTK(PROBE, ERR,
2648345f
MC		 1285 "Unable to allocate aligned memory "
1286 "for the transmit descriptor ring\n");
1da177e4
LT		 1287 vfree(txdr->buffer_info);
1288 return -ENOMEM;
1289 } else {
2648345f 1290 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1291 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1292 }
1293 }
1294 memset(txdr->desc, 0, txdr->size);
1295
1296 txdr->next_to_use = 0;
1297 txdr->next_to_clean = 0;
2ae76d98 1298 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1299
1300 return 0;
1301}
1302
581d708e
MC		 1303/**
1304 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1305 * (Descriptors) for all queues
1306 * @adapter: board private structure
1307 *
1308 * If this function returns with an error, then it's possible one or
1309 * more of the rings is populated (while the rest are not). It is the
1310 * callers duty to clean those orphaned rings.
1311 *
1312 * Return 0 on success, negative on failure
1313 **/
1314
1315int
1316e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1317{
1318 int i, err = 0;
1319
f56799ea 1320 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1321 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1322 if (err) {
1323 DPRINTK(PROBE, ERR,
1324 "Allocation for Tx Queue %u failed\n", i);
1325 break;
1326 }
1327 }
1328
1329 return err;
1330}
1331
1da177e4
LT		 1332/**
1333 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1334 * @adapter: board private structure
1335 *
1336 * Configure the Tx unit of the MAC after a reset.
1337 **/
1338
1339static void
1340e1000_configure_tx(struct e1000_adapter *adapter)
1341{
581d708e
MC		 1342 uint64_t tdba;
1343 struct e1000_hw *hw = &adapter->hw;
1344 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1345 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1346
1347 /* Setup the HW Tx Head and Tail descriptor pointers */
1348
f56799ea 1349 switch (adapter->num_tx_queues) {
24025e4e
MC		 1350 case 2:
1351 tdba = adapter->tx_ring[1].dma;
1352 tdlen = adapter->tx_ring[1].count *
1353 sizeof(struct e1000_tx_desc);
1354 E1000_WRITE_REG(hw, TDBAL1, (tdba & 0x00000000ffffffffULL));
1355 E1000_WRITE_REG(hw, TDBAH1, (tdba >> 32));
1356 E1000_WRITE_REG(hw, TDLEN1, tdlen);
1357 E1000_WRITE_REG(hw, TDH1, 0);
1358 E1000_WRITE_REG(hw, TDT1, 0);
1359 adapter->tx_ring[1].tdh = E1000_TDH1;
1360 adapter->tx_ring[1].tdt = E1000_TDT1;
1361 /* Fall Through */
1362 case 1:
1363 default:
581d708e
MC		 1364 tdba = adapter->tx_ring[0].dma;
1365 tdlen = adapter->tx_ring[0].count *
1366 sizeof(struct e1000_tx_desc);
1367 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1368 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1369 E1000_WRITE_REG(hw, TDLEN, tdlen);
1370 E1000_WRITE_REG(hw, TDH, 0);
1371 E1000_WRITE_REG(hw, TDT, 0);
1372 adapter->tx_ring[0].tdh = E1000_TDH;
1373 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1374 break;
1375 }
1da177e4
LT		 1376
1377 /* Set the default values for the Tx Inter Packet Gap timer */
1378
0fadb059
JK		 1379 if (hw->media_type == e1000_media_type_fiber ||
1380 hw->media_type == e1000_media_type_internal_serdes)
1381 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1382 else
1383 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1384
581d708e 1385 switch (hw->mac_type) {
1da177e4
LT		 1386 case e1000_82542_rev2_0:
1387 case e1000_82542_rev2_1:
1388 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1389 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1390 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4
LT		 1391 break;
1392 default:
0fadb059
JK		 1393 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1394 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1395 break;
1da177e4 1396 }
0fadb059
JK		 1397 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1398 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1399 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1400
1401 /* Set the Tx Interrupt Delay register */
1402
581d708e
MC		 1403 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1404 if (hw->mac_type >= e1000_82540)
1405 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1406
1407 /* Program the Transmit Control Register */
1408
581d708e 1409 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1410
1411 tctl &= ~E1000_TCTL_CT;
24025e4e 1412 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1413 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1414
581d708e 1415 E1000_WRITE_REG(hw, TCTL, tctl);
1da177e4 1416
2ae76d98
MC		 1417 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1418 tarc = E1000_READ_REG(hw, TARC0);
1419 tarc |= ((1 << 25) | (1 << 21));
1420 E1000_WRITE_REG(hw, TARC0, tarc);
1421 tarc = E1000_READ_REG(hw, TARC1);
1422 tarc |= (1 << 25);
1423 if (tctl & E1000_TCTL_MULR)
1424 tarc &= ~(1 << 28);
1425 else
1426 tarc |= (1 << 28);
1427 E1000_WRITE_REG(hw, TARC1, tarc);
1428 }
1429
581d708e 1430 e1000_config_collision_dist(hw);
1da177e4
LT		 1431
1432 /* Setup Transmit Descriptor Settings for eop descriptor */
1433 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1434 E1000_TXD_CMD_IFCS;
1435
581d708e 1436 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1437 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1438 else
1439 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1440
1441 /* Cache if we're 82544 running in PCI-X because we'll
1442 * need this to apply a workaround later in the send path. */
581d708e
MC		 1443 if (hw->mac_type == e1000_82544 &&
1444 hw->bus_type == e1000_bus_type_pcix)
1da177e4
LT		 1445 adapter->pcix_82544 = 1;
1446}
1447
1448/**
1449 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1450 * @adapter: board private structure
581d708e 1451 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1452 *
1453 * Returns 0 on success, negative on failure
1454 **/
1455
3ad2cc67 1456static int
581d708e
MC		 1457e1000_setup_rx_resources(struct e1000_adapter *adapter,
1458 struct e1000_rx_ring *rxdr)
1da177e4 1459{
1da177e4 1460 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1461 int size, desc_len;
1da177e4
LT		 1462
1463 size = sizeof(struct e1000_buffer) * rxdr->count;
a7ec15da 1464 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
581d708e 1465 if (!rxdr->buffer_info) {
2648345f
MC		 1466 DPRINTK(PROBE, ERR,
1467 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1468 return -ENOMEM;
1469 }
1470 memset(rxdr->buffer_info, 0, size);
1471
2d7edb92
MC		 1472 size = sizeof(struct e1000_ps_page) * rxdr->count;
1473 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
1474 if(!rxdr->ps_page) {
1475 vfree(rxdr->buffer_info);
1476 DPRINTK(PROBE, ERR,
1477 "Unable to allocate memory for the receive descriptor ring\n");
1478 return -ENOMEM;
1479 }
1480 memset(rxdr->ps_page, 0, size);
1481
1482 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1483 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
1484 if(!rxdr->ps_page_dma) {
1485 vfree(rxdr->buffer_info);
1486 kfree(rxdr->ps_page);
1487 DPRINTK(PROBE, ERR,
1488 "Unable to allocate memory for the receive descriptor ring\n");
1489 return -ENOMEM;
1490 }
1491 memset(rxdr->ps_page_dma, 0, size);
1492
1493 if(adapter->hw.mac_type <= e1000_82547_rev_2)
1494 desc_len = sizeof(struct e1000_rx_desc);
1495 else
1496 desc_len = sizeof(union e1000_rx_desc_packet_split);
1497
1da177e4
LT		 1498 /* Round up to nearest 4K */
1499
2d7edb92 1500 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1501 E1000_ROUNDUP(rxdr->size, 4096);
1502
1503 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1504
581d708e
MC		 1505 if (!rxdr->desc) {
1506 DPRINTK(PROBE, ERR,
1507 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1508setup_rx_desc_die:
1da177e4 1509 vfree(rxdr->buffer_info);
2d7edb92
MC		 1510 kfree(rxdr->ps_page);
1511 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1512 return -ENOMEM;
1513 }
1514
2648345f 1515 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1516 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1517 void *olddesc = rxdr->desc;
1518 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1519 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1520 "at %p\n", rxdr->size, rxdr->desc);
1521 /* Try again, without freeing the previous */
1da177e4 1522 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1523 /* Failed allocation, critical failure */
581d708e 1524 if (!rxdr->desc) {
1da177e4 1525 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1526 DPRINTK(PROBE, ERR,
1527 "Unable to allocate memory "
1528 "for the receive descriptor ring\n");
1da177e4
LT		 1529 goto setup_rx_desc_die;
1530 }
1531
1532 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1533 /* give up */
2648345f
MC		 1534 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1535 rxdr->dma);
1da177e4 1536 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1537 DPRINTK(PROBE, ERR,
1538 "Unable to allocate aligned memory "
1539 "for the receive descriptor ring\n");
581d708e 1540 goto setup_rx_desc_die;
1da177e4 1541 } else {
2648345f 1542 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1543 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1544 }
1545 }
1546 memset(rxdr->desc, 0, rxdr->size);
1547
1548 rxdr->next_to_clean = 0;
1549 rxdr->next_to_use = 0;
997f5cbd
JK		 1550 rxdr->rx_skb_top = NULL;
1551 rxdr->rx_skb_prev = NULL;
1da177e4
LT		 1552
1553 return 0;
1554}
1555
581d708e
MC		 1556/**
1557 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1558 * (Descriptors) for all queues
1559 * @adapter: board private structure
1560 *
1561 * If this function returns with an error, then it's possible one or
1562 * more of the rings is populated (while the rest are not). It is the
1563 * callers duty to clean those orphaned rings.
1564 *
1565 * Return 0 on success, negative on failure
1566 **/
1567
1568int
1569e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1570{
1571 int i, err = 0;
1572
f56799ea 1573 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1574 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1575 if (err) {
1576 DPRINTK(PROBE, ERR,
1577 "Allocation for Rx Queue %u failed\n", i);
1578 break;
1579 }
1580 }
1581
1582 return err;
1583}
1584
1da177e4 1585/**
2648345f 1586 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1587 * @adapter: Board private structure
1588 **/
e4c811c9
MC		 1589#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1590 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1591static void
1592e1000_setup_rctl(struct e1000_adapter *adapter)
1593{
2d7edb92
MC		 1594 uint32_t rctl, rfctl;
1595 uint32_t psrctl = 0;
e4c811c9
MC		 1596#ifdef CONFIG_E1000_PACKET_SPLIT
1597 uint32_t pages = 0;
1598#endif
1da177e4
LT		 1599
1600 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1601
1602 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1603
1604 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1605 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1606 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1607
0fadb059
JK		 1608 if (adapter->hw.mac_type > e1000_82543)
1609 rctl |= E1000_RCTL_SECRC;
1610
1611 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1612 rctl |= E1000_RCTL_SBP;
1613 else
1614 rctl &= ~E1000_RCTL_SBP;
1615
2d7edb92
MC		 1616 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1617 rctl &= ~E1000_RCTL_LPE;
1618 else
1619 rctl |= E1000_RCTL_LPE;
1620
1da177e4 1621 /* Setup buffer sizes */
868d5309 1622 if(adapter->hw.mac_type >= e1000_82571) {
2d7edb92
MC		 1623 /* We can now specify buffers in 1K increments.
1624 * BSIZE and BSEX are ignored in this case. */
1625 rctl |= adapter->rx_buffer_len << 0x11;
1626 } else {
1627 rctl &= ~E1000_RCTL_SZ_4096;
1628 rctl |= E1000_RCTL_BSEX;
1629 switch (adapter->rx_buffer_len) {
1630 case E1000_RXBUFFER_2048:
1631 default:
1632 rctl |= E1000_RCTL_SZ_2048;
1633 rctl &= ~E1000_RCTL_BSEX;
1634 break;
1635 case E1000_RXBUFFER_4096:
1636 rctl |= E1000_RCTL_SZ_4096;
1637 break;
1638 case E1000_RXBUFFER_8192:
1639 rctl |= E1000_RCTL_SZ_8192;
1640 break;
1641 case E1000_RXBUFFER_16384:
1642 rctl |= E1000_RCTL_SZ_16384;
1643 break;
1644 }
1645 }
1646
1647#ifdef CONFIG_E1000_PACKET_SPLIT
1648 /* 82571 and greater support packet-split where the protocol
1649 * header is placed in skb->data and the packet data is
1650 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1651 * In the case of a non-split, skb->data is linearly filled,
1652 * followed by the page buffers. Therefore, skb->data is
1653 * sized to hold the largest protocol header.
1654 */
e4c811c9
MC		 1655 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1656 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1657 PAGE_SIZE <= 16384)
1658 adapter->rx_ps_pages = pages;
1659 else
1660 adapter->rx_ps_pages = 0;
2d7edb92 1661#endif
e4c811c9 1662 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1663 /* Configure extra packet-split registers */
1664 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1665 rfctl |= E1000_RFCTL_EXTEN;
1666 /* disable IPv6 packet split support */
1667 rfctl |= E1000_RFCTL_IPV6_DIS;
1668 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1669
1670 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
1671
1672 psrctl |= adapter->rx_ps_bsize0 >>
1673 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1674
1675 switch (adapter->rx_ps_pages) {
1676 case 3:
1677 psrctl |= PAGE_SIZE <<
1678 E1000_PSRCTL_BSIZE3_SHIFT;
1679 case 2:
1680 psrctl |= PAGE_SIZE <<
1681 E1000_PSRCTL_BSIZE2_SHIFT;
1682 case 1:
1683 psrctl |= PAGE_SIZE >>
1684 E1000_PSRCTL_BSIZE1_SHIFT;
1685 break;
1686 }
2d7edb92
MC		 1687
1688 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1689 }
1690
1691 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1692}
1693
1694/**
1695 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1696 * @adapter: board private structure
1697 *
1698 * Configure the Rx unit of the MAC after a reset.
1699 **/
1700
1701static void
1702e1000_configure_rx(struct e1000_adapter *adapter)
1703{
581d708e
MC		 1704 uint64_t rdba;
1705 struct e1000_hw *hw = &adapter->hw;
1706 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
1707#ifdef CONFIG_E1000_MQ
1708 uint32_t reta, mrqc;
1709 int i;
1710#endif
2d7edb92 1711
e4c811c9 1712 if (adapter->rx_ps_pages) {
581d708e 1713 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1714 sizeof(union e1000_rx_desc_packet_split);
1715 adapter->clean_rx = e1000_clean_rx_irq_ps;
1716 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1717 } else {
581d708e
MC		 1718 rdlen = adapter->rx_ring[0].count *
1719 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1720 adapter->clean_rx = e1000_clean_rx_irq;
1721 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1722 }
1da177e4
LT		 1723
1724 /* disable receives while setting up the descriptors */
581d708e
MC		 1725 rctl = E1000_READ_REG(hw, RCTL);
1726 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1727
1728 /* set the Receive Delay Timer Register */
581d708e 1729 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1730
581d708e
MC		 1731 if (hw->mac_type >= e1000_82540) {
1732 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
1da177e4 1733 if(adapter->itr > 1)
581d708e 1734 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1735 1000000000 / (adapter->itr * 256));
1736 }
1737
2ae76d98 1738 if (hw->mac_type >= e1000_82571) {
2ae76d98 1739 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1740 /* Reset delay timers after every interrupt */
2ae76d98 1741 ctrl_ext |= E1000_CTRL_EXT_CANC;
1e613fd9
JK		 1742#ifdef CONFIG_E1000_NAPI
1743 /* Auto-Mask interrupts upon ICR read. */
1744 ctrl_ext |= E1000_CTRL_EXT_IAME;
1745#endif
2ae76d98 1746 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1747 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1748 E1000_WRITE_FLUSH(hw);
1749 }
1750
581d708e
MC		 1751 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1752 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1753 switch (adapter->num_rx_queues) {
24025e4e
MC		 1754#ifdef CONFIG_E1000_MQ
1755 case 2:
1756 rdba = adapter->rx_ring[1].dma;
1757 E1000_WRITE_REG(hw, RDBAL1, (rdba & 0x00000000ffffffffULL));
1758 E1000_WRITE_REG(hw, RDBAH1, (rdba >> 32));
1759 E1000_WRITE_REG(hw, RDLEN1, rdlen);
1760 E1000_WRITE_REG(hw, RDH1, 0);
1761 E1000_WRITE_REG(hw, RDT1, 0);
1762 adapter->rx_ring[1].rdh = E1000_RDH1;
1763 adapter->rx_ring[1].rdt = E1000_RDT1;
1764 /* Fall Through */
1765#endif
1766 case 1:
1767 default:
581d708e
MC		 1768 rdba = adapter->rx_ring[0].dma;
1769 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1770 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1771 E1000_WRITE_REG(hw, RDLEN, rdlen);
1772 E1000_WRITE_REG(hw, RDH, 0);
1773 E1000_WRITE_REG(hw, RDT, 0);
1774 adapter->rx_ring[0].rdh = E1000_RDH;
1775 adapter->rx_ring[0].rdt = E1000_RDT;
1776 break;
24025e4e
MC		 1777 }
1778
1779#ifdef CONFIG_E1000_MQ
f56799ea 1780 if (adapter->num_rx_queues > 1) {
24025e4e
MC		 1781 uint32_t random[10];
1782
1783 get_random_bytes(&random[0], 40);
1784
1785 if (hw->mac_type <= e1000_82572) {
1786 E1000_WRITE_REG(hw, RSSIR, 0);
1787 E1000_WRITE_REG(hw, RSSIM, 0);
1788 }
1789
f56799ea 1790 switch (adapter->num_rx_queues) {
24025e4e
MC		 1791 case 2:
1792 default:
1793 reta = 0x00800080;
1794 mrqc = E1000_MRQC_ENABLE_RSS_2Q;
1795 break;
1796 }
1797
1798 /* Fill out redirection table */
1799 for (i = 0; i < 32; i++)
1800 E1000_WRITE_REG_ARRAY(hw, RETA, i, reta);
1801 /* Fill out hash function seeds */
1802 for (i = 0; i < 10; i++)
1803 E1000_WRITE_REG_ARRAY(hw, RSSRK, i, random[i]);
1804
1805 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1806 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1807 E1000_WRITE_REG(hw, MRQC, mrqc);
1808 }
1809
1810 /* Multiqueue and packet checksumming are mutually exclusive. */
1811 if (hw->mac_type >= e1000_82571) {
1812 rxcsum = E1000_READ_REG(hw, RXCSUM);
1813 rxcsum |= E1000_RXCSUM_PCSD;
1814 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1815 }
1816
1817#else
1da177e4
LT		 1818
1819 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1820 if (hw->mac_type >= e1000_82543) {
1821 rxcsum = E1000_READ_REG(hw, RXCSUM);
2d7edb92
MC		 1822 if(adapter->rx_csum == TRUE) {
1823 rxcsum |= E1000_RXCSUM_TUOFL;
1824
868d5309 1825 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1826 * Must be used in conjunction with packet-split. */
e4c811c9
MC		 1827 if ((hw->mac_type >= e1000_82571) &&
1828 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1829 rxcsum |= E1000_RXCSUM_IPPCSE;
1830 }
1831 } else {
1832 rxcsum &= ~E1000_RXCSUM_TUOFL;
1833 /* don't need to clear IPPCSE as it defaults to 0 */
1834 }
581d708e 1835 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4 1836 }
24025e4e 1837#endif /* CONFIG_E1000_MQ */
1da177e4 1838
581d708e
MC		 1839 if (hw->mac_type == e1000_82573)
1840 E1000_WRITE_REG(hw, ERT, 0x0100);
2d7edb92 1841
1da177e4 1842 /* Enable Receives */
581d708e 1843 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1844}
1845
1846/**
581d708e 1847 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1848 * @adapter: board private structure
581d708e 1849 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1850 *
1851 * Free all transmit software resources
1852 **/
1853
3ad2cc67 1854static void
581d708e
MC		 1855e1000_free_tx_resources(struct e1000_adapter *adapter,
1856 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1857{
1858 struct pci_dev *pdev = adapter->pdev;
1859
581d708e 1860 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1861
581d708e
MC		 1862 vfree(tx_ring->buffer_info);
1863 tx_ring->buffer_info = NULL;
1da177e4 1864
581d708e 1865 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1866
581d708e
MC		 1867 tx_ring->desc = NULL;
1868}
1869
1870/**
1871 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1872 * @adapter: board private structure
1873 *
1874 * Free all transmit software resources
1875 **/
1876
1877void
1878e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1879{
1880 int i;
1881
f56799ea 1882 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1883 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1884}
1885
1886static inline void
1887e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1888 struct e1000_buffer *buffer_info)
1889{
1da177e4 1890 if(buffer_info->dma) {
2648345f
MC		 1891 pci_unmap_page(adapter->pdev,
1892 buffer_info->dma,
1893 buffer_info->length,
1894 PCI_DMA_TODEVICE);
1da177e4
LT		 1895 buffer_info->dma = 0;
1896 }
1897 if(buffer_info->skb) {
1898 dev_kfree_skb_any(buffer_info->skb);
1899 buffer_info->skb = NULL;
1900 }
1901}
1902
1903/**
1904 * e1000_clean_tx_ring - Free Tx Buffers
1905 * @adapter: board private structure
581d708e 1906 * @tx_ring: ring to be cleaned
1da177e4
LT		 1907 **/
1908
1909static void
581d708e
MC		 1910e1000_clean_tx_ring(struct e1000_adapter *adapter,
1911 struct e1000_tx_ring *tx_ring)
1da177e4 1912{
1da177e4
LT		 1913 struct e1000_buffer *buffer_info;
1914 unsigned long size;
1915 unsigned int i;
1916
1917 /* Free all the Tx ring sk_buffs */
1918
1da177e4
LT		 1919 for(i = 0; i < tx_ring->count; i++) {
1920 buffer_info = &tx_ring->buffer_info[i];
1921 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1922 }
1923
1924 size = sizeof(struct e1000_buffer) * tx_ring->count;
1925 memset(tx_ring->buffer_info, 0, size);
1926
1927 /* Zero out the descriptor ring */
1928
1929 memset(tx_ring->desc, 0, tx_ring->size);
1930
1931 tx_ring->next_to_use = 0;
1932 tx_ring->next_to_clean = 0;
fd803241 1933 tx_ring->last_tx_tso = 0;
1da177e4 1934
581d708e
MC		 1935 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1936 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1937}
1938
1939/**
1940 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1941 * @adapter: board private structure
1942 **/
1943
1944static void
1945e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1946{
1947 int i;
1948
f56799ea 1949 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1950 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1951}
1952
1953/**
1954 * e1000_free_rx_resources - Free Rx Resources
1955 * @adapter: board private structure
581d708e 1956 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1957 *
1958 * Free all receive software resources
1959 **/
1960
3ad2cc67 1961static void
581d708e
MC		 1962e1000_free_rx_resources(struct e1000_adapter *adapter,
1963 struct e1000_rx_ring *rx_ring)
1da177e4 1964{
1da177e4
LT		 1965 struct pci_dev *pdev = adapter->pdev;
1966
581d708e 1967 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1968
1969 vfree(rx_ring->buffer_info);
1970 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1971 kfree(rx_ring->ps_page);
1972 rx_ring->ps_page = NULL;
1973 kfree(rx_ring->ps_page_dma);
1974 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1975
1976 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1977
1978 rx_ring->desc = NULL;
1979}
1980
1981/**
581d708e 1982 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 1983 * @adapter: board private structure
581d708e
MC		 1984 *
1985 * Free all receive software resources
1986 **/
1987
1988void
1989e1000_free_all_rx_resources(struct e1000_adapter *adapter)
1990{
1991 int i;
1992
f56799ea 1993 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 1994 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
1995}
1996
1997/**
1998 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1999 * @adapter: board private structure
2000 * @rx_ring: ring to free buffers from
1da177e4
LT		 2001 **/
2002
2003static void
581d708e
MC		 2004e1000_clean_rx_ring(struct e1000_adapter *adapter,
2005 struct e1000_rx_ring *rx_ring)
1da177e4 2006{
1da177e4 2007 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2008 struct e1000_ps_page *ps_page;
2009 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2010 struct pci_dev *pdev = adapter->pdev;
2011 unsigned long size;
2d7edb92 2012 unsigned int i, j;
1da177e4
LT		 2013
2014 /* Free all the Rx ring sk_buffs */
2015
2016 for(i = 0; i < rx_ring->count; i++) {
2017 buffer_info = &rx_ring->buffer_info[i];
2018 if(buffer_info->skb) {
2d7edb92
MC		 2019 ps_page = &rx_ring->ps_page[i];
2020 ps_page_dma = &rx_ring->ps_page_dma[i];
1da177e4
LT		 2021 pci_unmap_single(pdev,
2022 buffer_info->dma,
2023 buffer_info->length,
2024 PCI_DMA_FROMDEVICE);
2025
2026 dev_kfree_skb(buffer_info->skb);
2027 buffer_info->skb = NULL;
997f5cbd
JK		 2028 }
2029 ps_page = &rx_ring->ps_page[i];
2030 ps_page_dma = &rx_ring->ps_page_dma[i];
2031 for (j = 0; j < adapter->rx_ps_pages; j++) {
2032 if (!ps_page->ps_page[j]) break;
2033 pci_unmap_page(pdev,
2034 ps_page_dma->ps_page_dma[j],
2035 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2036 ps_page_dma->ps_page_dma[j] = 0;
2037 put_page(ps_page->ps_page[j]);
2038 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2039 }
2040 }
2041
997f5cbd
JK		 2042 /* there also may be some cached data in our adapter */
2043 if (rx_ring->rx_skb_top) {
2044 dev_kfree_skb(rx_ring->rx_skb_top);
2045
2046 /* rx_skb_prev will be wiped out by rx_skb_top */
2047 rx_ring->rx_skb_top = NULL;
2048 rx_ring->rx_skb_prev = NULL;
2049 }
2050
2051
1da177e4
LT		 2052 size = sizeof(struct e1000_buffer) * rx_ring->count;
2053 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2054 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2055 memset(rx_ring->ps_page, 0, size);
2056 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2057 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2058
2059 /* Zero out the descriptor ring */
2060
2061 memset(rx_ring->desc, 0, rx_ring->size);
2062
2063 rx_ring->next_to_clean = 0;
2064 rx_ring->next_to_use = 0;
2065
581d708e
MC		 2066 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2067 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2068}
2069
2070/**
2071 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2072 * @adapter: board private structure
2073 **/
2074
2075static void
2076e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2077{
2078 int i;
2079
f56799ea 2080 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2081 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2082}
2083
2084/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2085 * and memory write and invalidate disabled for certain operations
2086 */
2087static void
2088e1000_enter_82542_rst(struct e1000_adapter *adapter)
2089{
2090 struct net_device *netdev = adapter->netdev;
2091 uint32_t rctl;
2092
2093 e1000_pci_clear_mwi(&adapter->hw);
2094
2095 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2096 rctl |= E1000_RCTL_RST;
2097 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2098 E1000_WRITE_FLUSH(&adapter->hw);
2099 mdelay(5);
2100
2101 if(netif_running(netdev))
581d708e 2102 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2103}
2104
2105static void
2106e1000_leave_82542_rst(struct e1000_adapter *adapter)
2107{
2108 struct net_device *netdev = adapter->netdev;
2109 uint32_t rctl;
2110
2111 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2112 rctl &= ~E1000_RCTL_RST;
2113 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2114 E1000_WRITE_FLUSH(&adapter->hw);
2115 mdelay(5);
2116
2117 if(adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
2118 e1000_pci_set_mwi(&adapter->hw);
2119
2120 if(netif_running(netdev)) {
2121 e1000_configure_rx(adapter);
581d708e 2122 e1000_alloc_rx_buffers(adapter, &adapter->rx_ring[0]);
1da177e4
LT		 2123 }
2124}
2125
2126/**
2127 * e1000_set_mac - Change the Ethernet Address of the NIC
2128 * @netdev: network interface device structure
2129 * @p: pointer to an address structure
2130 *
2131 * Returns 0 on success, negative on failure
2132 **/
2133
2134static int
2135e1000_set_mac(struct net_device *netdev, void *p)
2136{
60490fe0 2137 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2138 struct sockaddr *addr = p;
2139
2140 if(!is_valid_ether_addr(addr->sa_data))
2141 return -EADDRNOTAVAIL;
2142
2143 /* 82542 2.0 needs to be in reset to write receive address registers */
2144
2145 if(adapter->hw.mac_type == e1000_82542_rev2_0)
2146 e1000_enter_82542_rst(adapter);
2147
2148 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2149 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2150
2151 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2152
868d5309
MC		 2153 /* With 82571 controllers, LAA may be overwritten (with the default)
2154 * due to controller reset from the other port. */
2155 if (adapter->hw.mac_type == e1000_82571) {
2156 /* activate the work around */
2157 adapter->hw.laa_is_present = 1;
2158
2159 /* Hold a copy of the LAA in RAR[14] This is done so that
2160 * between the time RAR[0] gets clobbered and the time it
2161 * gets fixed (in e1000_watchdog), the actual LAA is in one
2162 * of the RARs and no incoming packets directed to this port
2163 * are dropped. Eventaully the LAA will be in RAR[0] and
2164 * RAR[14] */
2165 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
2166 E1000_RAR_ENTRIES - 1);
2167 }
2168
1da177e4
LT		 2169 if(adapter->hw.mac_type == e1000_82542_rev2_0)
2170 e1000_leave_82542_rst(adapter);
2171
2172 return 0;
2173}
2174
2175/**
2176 * e1000_set_multi - Multicast and Promiscuous mode set
2177 * @netdev: network interface device structure
2178 *
2179 * The set_multi entry point is called whenever the multicast address
2180 * list or the network interface flags are updated. This routine is
2181 * responsible for configuring the hardware for proper multicast,
2182 * promiscuous mode, and all-multi behavior.
2183 **/
2184
2185static void
2186e1000_set_multi(struct net_device *netdev)
2187{
60490fe0 2188 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2189 struct e1000_hw *hw = &adapter->hw;
2190 struct dev_mc_list *mc_ptr;
2191 uint32_t rctl;
2192 uint32_t hash_value;
868d5309 2193 int i, rar_entries = E1000_RAR_ENTRIES;
1da177e4 2194
868d5309
MC		 2195 /* reserve RAR[14] for LAA over-write work-around */
2196 if (adapter->hw.mac_type == e1000_82571)
2197 rar_entries--;
1da177e4 2198
2648345f
MC		 2199 /* Check for Promiscuous and All Multicast modes */
2200
1da177e4
LT		 2201 rctl = E1000_READ_REG(hw, RCTL);
2202
2203 if(netdev->flags & IFF_PROMISC) {
2204 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2205 } else if(netdev->flags & IFF_ALLMULTI) {
2206 rctl |= E1000_RCTL_MPE;
2207 rctl &= ~E1000_RCTL_UPE;
2208 } else {
2209 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2210 }
2211
2212 E1000_WRITE_REG(hw, RCTL, rctl);
2213
2214 /* 82542 2.0 needs to be in reset to write receive address registers */
2215
2216 if(hw->mac_type == e1000_82542_rev2_0)
2217 e1000_enter_82542_rst(adapter);
2218
2219 /* load the first 14 multicast address into the exact filters 1-14
2220 * RAR 0 is used for the station MAC adddress
2221 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2222 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2223 */
2224 mc_ptr = netdev->mc_list;
2225
868d5309
MC		 2226 for(i = 1; i < rar_entries; i++) {
2227 if (mc_ptr) {
1da177e4
LT		 2228 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2229 mc_ptr = mc_ptr->next;
2230 } else {
2231 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2232 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2233 }
2234 }
2235
2236 /* clear the old settings from the multicast hash table */
2237
2238 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
2239 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2240
2241 /* load any remaining addresses into the hash table */
2242
2243 for(; mc_ptr; mc_ptr = mc_ptr->next) {
2244 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2245 e1000_mta_set(hw, hash_value);
2246 }
2247
2248 if(hw->mac_type == e1000_82542_rev2_0)
2249 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2250}
2251
2252/* Need to wait a few seconds after link up to get diagnostic information from
2253 * the phy */
2254
2255static void
2256e1000_update_phy_info(unsigned long data)
2257{
2258 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2259 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2260}
2261
2262/**
2263 * e1000_82547_tx_fifo_stall - Timer Call-back
2264 * @data: pointer to adapter cast into an unsigned long
2265 **/
2266
2267static void
2268e1000_82547_tx_fifo_stall(unsigned long data)
2269{
2270 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2271 struct net_device *netdev = adapter->netdev;
2272 uint32_t tctl;
2273
2274 if(atomic_read(&adapter->tx_fifo_stall)) {
2275 if((E1000_READ_REG(&adapter->hw, TDT) ==
2276 E1000_READ_REG(&adapter->hw, TDH)) &&
2277 (E1000_READ_REG(&adapter->hw, TDFT) ==
2278 E1000_READ_REG(&adapter->hw, TDFH)) &&
2279 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2280 E1000_READ_REG(&adapter->hw, TDFHS))) {
2281 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2282 E1000_WRITE_REG(&adapter->hw, TCTL,
2283 tctl & ~E1000_TCTL_EN);
2284 E1000_WRITE_REG(&adapter->hw, TDFT,
2285 adapter->tx_head_addr);
2286 E1000_WRITE_REG(&adapter->hw, TDFH,
2287 adapter->tx_head_addr);
2288 E1000_WRITE_REG(&adapter->hw, TDFTS,
2289 adapter->tx_head_addr);
2290 E1000_WRITE_REG(&adapter->hw, TDFHS,
2291 adapter->tx_head_addr);
2292 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2293 E1000_WRITE_FLUSH(&adapter->hw);
2294
2295 adapter->tx_fifo_head = 0;
2296 atomic_set(&adapter->tx_fifo_stall, 0);
2297 netif_wake_queue(netdev);
2298 } else {
2299 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2300 }
2301 }
2302}
2303
2304/**
2305 * e1000_watchdog - Timer Call-back
2306 * @data: pointer to adapter cast into an unsigned long
2307 **/
2308static void
2309e1000_watchdog(unsigned long data)
2310{
2311 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2312
2313 /* Do the rest outside of interrupt context */
2314 schedule_work(&adapter->watchdog_task);
2315}
2316
2317static void
2318e1000_watchdog_task(struct e1000_adapter *adapter)
2319{
2320 struct net_device *netdev = adapter->netdev;
545c67c0 2321 struct e1000_tx_ring *txdr = adapter->tx_ring;
1da177e4
LT		 2322 uint32_t link;
2323
2324 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 2325 if (adapter->hw.mac_type == e1000_82573) {
2326 e1000_enable_tx_pkt_filtering(&adapter->hw);
2327 if(adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2328 e1000_update_mng_vlan(adapter);
2329 }
1da177e4
LT		 2330
2331 if((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
2332 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2333 link = !adapter->hw.serdes_link_down;
2334 else
2335 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2336
2337 if(link) {
2338 if(!netif_carrier_ok(netdev)) {
2339 e1000_get_speed_and_duplex(&adapter->hw,
2340 &adapter->link_speed,
2341 &adapter->link_duplex);
2342
2343 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2344 adapter->link_speed,
2345 adapter->link_duplex == FULL_DUPLEX ?
2346 "Full Duplex" : "Half Duplex");
2347
66a2b0a3
JK		 2348 /* tweak tx_queue_len according to speed/duplex */
2349 netdev->tx_queue_len = adapter->tx_queue_len;
2350 adapter->tx_timeout_factor = 1;
2351 if (adapter->link_duplex == HALF_DUPLEX) {
2352 switch (adapter->link_speed) {
2353 case SPEED_10:
2354 netdev->tx_queue_len = 10;
2355 adapter->tx_timeout_factor = 8;
2356 break;
2357 case SPEED_100:
2358 netdev->tx_queue_len = 100;
2359 break;
2360 }
2361 }
2362
1da177e4
LT		 2363 netif_carrier_on(netdev);
2364 netif_wake_queue(netdev);
2365 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2366 adapter->smartspeed = 0;
2367 }
2368 } else {
2369 if(netif_carrier_ok(netdev)) {
2370 adapter->link_speed = 0;
2371 adapter->link_duplex = 0;
2372 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2373 netif_carrier_off(netdev);
2374 netif_stop_queue(netdev);
2375 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2376 }
2377
2378 e1000_smartspeed(adapter);
2379 }
2380
2381 e1000_update_stats(adapter);
2382
2383 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2384 adapter->tpt_old = adapter->stats.tpt;
2385 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2386 adapter->colc_old = adapter->stats.colc;
2387
2388 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2389 adapter->gorcl_old = adapter->stats.gorcl;
2390 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2391 adapter->gotcl_old = adapter->stats.gotcl;
2392
2393 e1000_update_adaptive(&adapter->hw);
2394
f56799ea
JK		 2395#ifdef CONFIG_E1000_MQ
2396 txdr = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2397#endif
2398 if (!netif_carrier_ok(netdev)) {
581d708e 2399 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2400 /* We've lost link, so the controller stops DMA,
2401 * but we've got queued Tx work that's never going
2402 * to get done, so reset controller to flush Tx.
2403 * (Do the reset outside of interrupt context). */
2404 schedule_work(&adapter->tx_timeout_task);
2405 }
2406 }
2407
2408 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
2409 if(adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
2410 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2411 * asymmetrical Tx or Rx gets ITR=8000; everyone
2412 * else is between 2000-8000. */
2413 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
2414 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
2415 adapter->gotcl - adapter->gorcl :
2416 adapter->gorcl - adapter->gotcl) / 10000;
2417 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2418 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2419 }
2420
2421 /* Cause software interrupt to ensure rx ring is cleaned */
2422 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2423
2648345f 2424 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2425 adapter->detect_tx_hung = TRUE;
2426
868d5309
MC		 2427 /* With 82571 controllers, LAA may be overwritten due to controller
2428 * reset from the other port. Set the appropriate LAA in RAR[0] */
2429 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2430 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2431
1da177e4
LT		 2432 /* Reset the timer */
2433 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2434}
2435
2436#define E1000_TX_FLAGS_CSUM 0x00000001
2437#define E1000_TX_FLAGS_VLAN 0x00000002
2438#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2439#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2440#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2441#define E1000_TX_FLAGS_VLAN_SHIFT 16
2442
2443static inline int
581d708e
MC		 2444e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2445 struct sk_buff *skb)
1da177e4
LT		 2446{
2447#ifdef NETIF_F_TSO
2448 struct e1000_context_desc *context_desc;
545c67c0 2449 struct e1000_buffer *buffer_info;
1da177e4
LT		 2450 unsigned int i;
2451 uint32_t cmd_length = 0;
2d7edb92 2452 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2453 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2454 int err;
2455
2456 if(skb_shinfo(skb)->tso_size) {
2457 if (skb_header_cloned(skb)) {
2458 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2459 if (err)
2460 return err;
2461 }
2462
2463 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2464 mss = skb_shinfo(skb)->tso_size;
2d7edb92
MC		 2465 if(skb->protocol == ntohs(ETH_P_IP)) {
2466 skb->nh.iph->tot_len = 0;
2467 skb->nh.iph->check = 0;
2468 skb->h.th->check =
2469 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2470 skb->nh.iph->daddr,
2471 0,
2472 IPPROTO_TCP,
2473 0);
2474 cmd_length = E1000_TXD_CMD_IP;
2475 ipcse = skb->h.raw - skb->data - 1;
2476#ifdef NETIF_F_TSO_IPV6
2477 } else if(skb->protocol == ntohs(ETH_P_IPV6)) {
2478 skb->nh.ipv6h->payload_len = 0;
2479 skb->h.th->check =
2480 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2481 &skb->nh.ipv6h->daddr,
2482 0,
2483 IPPROTO_TCP,
2484 0);
2485 ipcse = 0;
2486#endif
2487 }
1da177e4
LT		 2488 ipcss = skb->nh.raw - skb->data;
2489 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2490 tucss = skb->h.raw - skb->data;
2491 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2492 tucse = 0;
2493
2494 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2495 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2496
581d708e
MC		 2497 i = tx_ring->next_to_use;
2498 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2499 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2500
2501 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2502 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2503 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2504 context_desc->upper_setup.tcp_fields.tucss = tucss;
2505 context_desc->upper_setup.tcp_fields.tucso = tucso;
2506 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2507 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2508 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2509 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2510
545c67c0
JK		 2511 buffer_info->time_stamp = jiffies;
2512
581d708e
MC		 2513 if (++i == tx_ring->count) i = 0;
2514 tx_ring->next_to_use = i;
1da177e4
LT		 2515
2516 return 1;
2517 }
2518#endif
2519
2520 return 0;
2521}
2522
2523static inline boolean_t
581d708e
MC		 2524e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2525 struct sk_buff *skb)
1da177e4
LT		 2526{
2527 struct e1000_context_desc *context_desc;
545c67c0 2528 struct e1000_buffer *buffer_info;
1da177e4
LT		 2529 unsigned int i;
2530 uint8_t css;
2531
2532 if(likely(skb->ip_summed == CHECKSUM_HW)) {
2533 css = skb->h.raw - skb->data;
2534
581d708e 2535 i = tx_ring->next_to_use;
545c67c0 2536 buffer_info = &tx_ring->buffer_info[i];
581d708e 2537 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2538
2539 context_desc->upper_setup.tcp_fields.tucss = css;
2540 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2541 context_desc->upper_setup.tcp_fields.tucse = 0;
2542 context_desc->tcp_seg_setup.data = 0;
2543 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2544
545c67c0
JK		 2545 buffer_info->time_stamp = jiffies;
2546
581d708e
MC		 2547 if (unlikely(++i == tx_ring->count)) i = 0;
2548 tx_ring->next_to_use = i;
1da177e4
LT		 2549
2550 return TRUE;
2551 }
2552
2553 return FALSE;
2554}
2555
2556#define E1000_MAX_TXD_PWR 12
2557#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2558
2559static inline int
581d708e
MC		 2560e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2561 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2562 unsigned int nr_frags, unsigned int mss)
1da177e4 2563{
1da177e4
LT		 2564 struct e1000_buffer *buffer_info;
2565 unsigned int len = skb->len;
2566 unsigned int offset = 0, size, count = 0, i;
2567 unsigned int f;
2568 len -= skb->data_len;
2569
2570 i = tx_ring->next_to_use;
2571
2572 while(len) {
2573 buffer_info = &tx_ring->buffer_info[i];
2574 size = min(len, max_per_txd);
2575#ifdef NETIF_F_TSO
fd803241
JK		 2576 /* Workaround for Controller erratum --
2577 * descriptor for non-tso packet in a linear SKB that follows a
2578 * tso gets written back prematurely before the data is fully
2579 * DMAd to the controller */
2580 if (!skb->data_len && tx_ring->last_tx_tso &&
2581 !skb_shinfo(skb)->tso_size) {
2582 tx_ring->last_tx_tso = 0;
2583 size -= 4;
2584 }
2585
1da177e4
LT		 2586 /* Workaround for premature desc write-backs
2587 * in TSO mode. Append 4-byte sentinel desc */
2588 if(unlikely(mss && !nr_frags && size == len && size > 8))
2589 size -= 4;
2590#endif
97338bde
MC		 2591 /* work-around for errata 10 and it applies
2592 * to all controllers in PCI-X mode
2593 * The fix is to make sure that the first descriptor of a
2594 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2595 */
2596 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2597 (size > 2015) && count == 0))
2598 size = 2015;
2599
1da177e4
LT		 2600 /* Workaround for potential 82544 hang in PCI-X. Avoid
2601 * terminating buffers within evenly-aligned dwords. */
2602 if(unlikely(adapter->pcix_82544 &&
2603 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2604 size > 4))
2605 size -= 4;
2606
2607 buffer_info->length = size;
2608 buffer_info->dma =
2609 pci_map_single(adapter->pdev,
2610 skb->data + offset,
2611 size,
2612 PCI_DMA_TODEVICE);
2613 buffer_info->time_stamp = jiffies;
2614
2615 len -= size;
2616 offset += size;
2617 count++;
2618 if(unlikely(++i == tx_ring->count)) i = 0;
2619 }
2620
2621 for(f = 0; f < nr_frags; f++) {
2622 struct skb_frag_struct *frag;
2623
2624 frag = &skb_shinfo(skb)->frags[f];
2625 len = frag->size;
2626 offset = frag->page_offset;
2627
2628 while(len) {
2629 buffer_info = &tx_ring->buffer_info[i];
2630 size = min(len, max_per_txd);
2631#ifdef NETIF_F_TSO
2632 /* Workaround for premature desc write-backs
2633 * in TSO mode. Append 4-byte sentinel desc */
2634 if(unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
2635 size -= 4;
2636#endif
2637 /* Workaround for potential 82544 hang in PCI-X.
2638 * Avoid terminating buffers within evenly-aligned
2639 * dwords. */
2640 if(unlikely(adapter->pcix_82544 &&
2641 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2642 size > 4))
2643 size -= 4;
2644
2645 buffer_info->length = size;
2646 buffer_info->dma =
2647 pci_map_page(adapter->pdev,
2648 frag->page,
2649 offset,
2650 size,
2651 PCI_DMA_TODEVICE);
2652 buffer_info->time_stamp = jiffies;
2653
2654 len -= size;
2655 offset += size;
2656 count++;
2657 if(unlikely(++i == tx_ring->count)) i = 0;
2658 }
2659 }
2660
2661 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2662 tx_ring->buffer_info[i].skb = skb;
2663 tx_ring->buffer_info[first].next_to_watch = i;
2664
2665 return count;
2666}
2667
2668static inline void
581d708e
MC		 2669e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2670 int tx_flags, int count)
1da177e4 2671{
1da177e4
LT		 2672 struct e1000_tx_desc *tx_desc = NULL;
2673 struct e1000_buffer *buffer_info;
2674 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2675 unsigned int i;
2676
2677 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) {
2678 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2679 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2680 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2681
2682 if(likely(tx_flags & E1000_TX_FLAGS_IPV4))
2683 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2684 }
2685
2686 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
2687 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2688 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2689 }
2690
2691 if(unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
2692 txd_lower |= E1000_TXD_CMD_VLE;
2693 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2694 }
2695
2696 i = tx_ring->next_to_use;
2697
2698 while(count--) {
2699 buffer_info = &tx_ring->buffer_info[i];
2700 tx_desc = E1000_TX_DESC(*tx_ring, i);
2701 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2702 tx_desc->lower.data =
2703 cpu_to_le32(txd_lower | buffer_info->length);
2704 tx_desc->upper.data = cpu_to_le32(txd_upper);
2705 if(unlikely(++i == tx_ring->count)) i = 0;
2706 }
2707
2708 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2709
2710 /* Force memory writes to complete before letting h/w
2711 * know there are new descriptors to fetch. (Only
2712 * applicable for weak-ordered memory model archs,
2713 * such as IA-64). */
2714 wmb();
2715
2716 tx_ring->next_to_use = i;
581d708e 2717 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2718}
2719
2720/**
2721 * 82547 workaround to avoid controller hang in half-duplex environment.
2722 * The workaround is to avoid queuing a large packet that would span
2723 * the internal Tx FIFO ring boundary by notifying the stack to resend
2724 * the packet at a later time. This gives the Tx FIFO an opportunity to
2725 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2726 * to the beginning of the Tx FIFO.
2727 **/
2728
2729#define E1000_FIFO_HDR 0x10
2730#define E1000_82547_PAD_LEN 0x3E0
2731
2732static inline int
2733e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2734{
2735 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2736 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2737
2738 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2739
2740 if(adapter->link_duplex != HALF_DUPLEX)
2741 goto no_fifo_stall_required;
2742
2743 if(atomic_read(&adapter->tx_fifo_stall))
2744 return 1;
2745
2746 if(skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
2747 atomic_set(&adapter->tx_fifo_stall, 1);
2748 return 1;
2749 }
2750
2751no_fifo_stall_required:
2752 adapter->tx_fifo_head += skb_fifo_len;
2753 if(adapter->tx_fifo_head >= adapter->tx_fifo_size)
2754 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2755 return 0;
2756}
2757
2d7edb92
MC		 2758#define MINIMUM_DHCP_PACKET_SIZE 282
2759static inline int
2760e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2761{
2762 struct e1000_hw *hw = &adapter->hw;
2763 uint16_t length, offset;
2764 if(vlan_tx_tag_present(skb)) {
2765 if(!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2766 ( adapter->hw.mng_cookie.status &
2767 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2768 return 0;
2769 }
a174fd88 2770 if ((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
2d7edb92
MC		 2771 struct ethhdr *eth = (struct ethhdr *) skb->data;
2772 if((htons(ETH_P_IP) == eth->h_proto)) {
2773 const struct iphdr *ip =
2774 (struct iphdr *)((uint8_t *)skb->data+14);
2775 if(IPPROTO_UDP == ip->protocol) {
2776 struct udphdr *udp =
2777 (struct udphdr *)((uint8_t *)ip +
2778 (ip->ihl << 2));
2779 if(ntohs(udp->dest) == 67) {
2780 offset = (uint8_t *)udp + 8 - skb->data;
2781 length = skb->len - offset;
2782
2783 return e1000_mng_write_dhcp_info(hw,
2784 (uint8_t *)udp + 8,
2785 length);
2786 }
2787 }
2788 }
2789 }
2790 return 0;
2791}
2792
1da177e4
LT		 2793#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2794static int
2795e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2796{
60490fe0 2797 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2798 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2799 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2800 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2801 unsigned int tx_flags = 0;
2802 unsigned int len = skb->len;
2803 unsigned long flags;
2804 unsigned int nr_frags = 0;
2805 unsigned int mss = 0;
2806 int count = 0;
2807 int tso;
2808 unsigned int f;
2809 len -= skb->data_len;
2810
24025e4e
MC		 2811#ifdef CONFIG_E1000_MQ
2812 tx_ring = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2813#else
581d708e 2814 tx_ring = adapter->tx_ring;
24025e4e
MC		 2815#endif
2816
581d708e 2817 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2818 dev_kfree_skb_any(skb);
2819 return NETDEV_TX_OK;
2820 }
2821
2822#ifdef NETIF_F_TSO
2823 mss = skb_shinfo(skb)->tso_size;
2648345f 2824 /* The controller does a simple calculation to
1da177e4
LT		 2825 * make sure there is enough room in the FIFO before
2826 * initiating the DMA for each buffer. The calc is:
2827 * 4 = ceil(buffer len/mss). To make sure we don't
2828 * overrun the FIFO, adjust the max buffer len if mss
2829 * drops. */
2830 if(mss) {
9a3056da 2831 uint8_t hdr_len;
1da177e4
LT		 2832 max_per_txd = min(mss << 2, max_per_txd);
2833 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da
JK		 2834
2835 /* TSO Workaround for 82571/2 Controllers -- if skb->data
2836 * points to just header, pull a few bytes of payload from
2837 * frags into skb->data */
2838 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2839 if (skb->data_len && (hdr_len == (skb->len - skb->data_len)) &&
2840 (adapter->hw.mac_type == e1000_82571 ||
2841 adapter->hw.mac_type == e1000_82572)) {
d74bbd3b
JK		 2842 unsigned int pull_size;
2843 pull_size = min((unsigned int)4, skb->data_len);
2844 if (!__pskb_pull_tail(skb, pull_size)) {
2845 printk(KERN_ERR "__pskb_pull_tail failed.\n");
2846 dev_kfree_skb_any(skb);
2847 return -EFAULT;
2848 }
9a3056da
JK		 2849 len = skb->len - skb->data_len;
2850 }
1da177e4
LT		 2851 }
2852
2853 if((mss) || (skb->ip_summed == CHECKSUM_HW))
9a3056da 2854 /* reserve a descriptor for the offload context */
1da177e4 2855 count++;
2648345f 2856 count++;
1da177e4
LT		 2857#else
2858 if(skb->ip_summed == CHECKSUM_HW)
2859 count++;
2860#endif
fd803241
JK		 2861
2862#ifdef NETIF_F_TSO
2863 /* Controller Erratum workaround */
2864 if (!skb->data_len && tx_ring->last_tx_tso &&
2865 !skb_shinfo(skb)->tso_size)
2866 count++;
2867#endif
2868
1da177e4
LT		 2869 count += TXD_USE_COUNT(len, max_txd_pwr);
2870
2871 if(adapter->pcix_82544)
2872 count++;
2873
97338bde
MC		 2874 /* work-around for errata 10 and it applies to all controllers
2875 * in PCI-X mode, so add one more descriptor to the count
2876 */
2877 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2878 (len > 2015)))
2879 count++;
2880
1da177e4
LT		 2881 nr_frags = skb_shinfo(skb)->nr_frags;
2882 for(f = 0; f < nr_frags; f++)
2883 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2884 max_txd_pwr);
2885 if(adapter->pcix_82544)
2886 count += nr_frags;
2887
2d7edb92
MC		 2888 if(adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
2889 e1000_transfer_dhcp_info(adapter, skb);
2890
581d708e
MC		 2891 local_irq_save(flags);
2892 if (!spin_trylock(&tx_ring->tx_lock)) {
2893 /* Collision - tell upper layer to requeue */
2894 local_irq_restore(flags);
2895 return NETDEV_TX_LOCKED;
2896 }
1da177e4
LT		 2897
2898 /* need: count + 2 desc gap to keep tail from touching
2899 * head, otherwise try next time */
581d708e 2900 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2901 netif_stop_queue(netdev);
581d708e 2902 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2903 return NETDEV_TX_BUSY;
2904 }
2905
2906 if(unlikely(adapter->hw.mac_type == e1000_82547)) {
2907 if(unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
2908 netif_stop_queue(netdev);
2909 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2910 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2911 return NETDEV_TX_BUSY;
2912 }
2913 }
2914
2915 if(unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
2916 tx_flags |= E1000_TX_FLAGS_VLAN;
2917 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2918 }
2919
581d708e 2920 first = tx_ring->next_to_use;
1da177e4 2921
581d708e 2922 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2923 if (tso < 0) {
2924 dev_kfree_skb_any(skb);
581d708e 2925 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2926 return NETDEV_TX_OK;
2927 }
2928
fd803241
JK		 2929 if (likely(tso)) {
2930 tx_ring->last_tx_tso = 1;
1da177e4 2931 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 2932 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 2933 tx_flags |= E1000_TX_FLAGS_CSUM;
2934
2d7edb92 2935 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 2936 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 2937 * no longer assume, we must. */
581d708e 2938 if (likely(skb->protocol == ntohs(ETH_P_IP)))
2d7edb92
MC		 2939 tx_flags |= E1000_TX_FLAGS_IPV4;
2940
581d708e
MC		 2941 e1000_tx_queue(adapter, tx_ring, tx_flags,
2942 e1000_tx_map(adapter, tx_ring, skb, first,
2943 max_per_txd, nr_frags, mss));
1da177e4
LT		 2944
2945 netdev->trans_start = jiffies;
2946
2947 /* Make sure there is space in the ring for the next send. */
581d708e 2948 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 2949 netif_stop_queue(netdev);
2950
581d708e 2951 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2952 return NETDEV_TX_OK;
2953}
2954
2955/**
2956 * e1000_tx_timeout - Respond to a Tx Hang
2957 * @netdev: network interface device structure
2958 **/
2959
2960static void
2961e1000_tx_timeout(struct net_device *netdev)
2962{
60490fe0 2963 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2964
2965 /* Do the reset outside of interrupt context */
2966 schedule_work(&adapter->tx_timeout_task);
2967}
2968
2969static void
2970e1000_tx_timeout_task(struct net_device *netdev)
2971{
60490fe0 2972 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2973
6b7660cd 2974 adapter->tx_timeout_count++;
1da177e4
LT		 2975 e1000_down(adapter);
2976 e1000_up(adapter);
2977}
2978
2979/**
2980 * e1000_get_stats - Get System Network Statistics
2981 * @netdev: network interface device structure
2982 *
2983 * Returns the address of the device statistics structure.
2984 * The statistics are actually updated from the timer callback.
2985 **/
2986
2987static struct net_device_stats *
2988e1000_get_stats(struct net_device *netdev)
2989{
60490fe0 2990 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2991
6b7660cd 2992 /* only return the current stats */
1da177e4
LT		 2993 return &adapter->net_stats;
2994}
2995
2996/**
2997 * e1000_change_mtu - Change the Maximum Transfer Unit
2998 * @netdev: network interface device structure
2999 * @new_mtu: new value for maximum frame size
3000 *
3001 * Returns 0 on success, negative on failure
3002 **/
3003
3004static int
3005e1000_change_mtu(struct net_device *netdev, int new_mtu)
3006{
60490fe0 3007 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3008 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
3009
3010 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3011 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3012 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3013 return -EINVAL;
2d7edb92 3014 }
1da177e4 3015
997f5cbd
JK		 3016 /* Adapter-specific max frame size limits. */
3017 switch (adapter->hw.mac_type) {
3018 case e1000_82542_rev2_0:
3019 case e1000_82542_rev2_1:
3020 case e1000_82573:
3021 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3022 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3023 return -EINVAL;
2d7edb92 3024 }
997f5cbd
JK		 3025 break;
3026 case e1000_82571:
3027 case e1000_82572:
3028#define MAX_STD_JUMBO_FRAME_SIZE 9234
3029 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3030 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3031 return -EINVAL;
3032 }
3033 break;
3034 default:
3035 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3036 break;
1da177e4
LT		 3037 }
3038
997f5cbd
JK		 3039 /* since the driver code now supports splitting a packet across
3040 * multiple descriptors, most of the fifo related limitations on
3041 * jumbo frame traffic have gone away.
3042 * simply use 2k descriptors for everything.
3043 *
3044 * NOTE: dev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3045 * means we reserve 2 more, this pushes us to allocate from the next
3046 * larger slab size
3047 * i.e. RXBUFFER_2048 --> size-4096 slab */
3048
3049 /* recent hardware supports 1KB granularity */
3050 if (adapter->hw.mac_type > e1000_82547_rev_2) {
3051 adapter->rx_buffer_len =
3052 ((max_frame < E1000_RXBUFFER_2048) ?
3053 max_frame : E1000_RXBUFFER_2048);
3054 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
3055 } else
3056 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3057
2d7edb92
MC		 3058 netdev->mtu = new_mtu;
3059
3060 if(netif_running(netdev)) {
1da177e4
LT		 3061 e1000_down(adapter);
3062 e1000_up(adapter);
3063 }
3064
1da177e4
LT		 3065 adapter->hw.max_frame_size = max_frame;
3066
3067 return 0;
3068}
3069
3070/**
3071 * e1000_update_stats - Update the board statistics counters
3072 * @adapter: board private structure
3073 **/
3074
3075void
3076e1000_update_stats(struct e1000_adapter *adapter)
3077{
3078 struct e1000_hw *hw = &adapter->hw;
3079 unsigned long flags;
3080 uint16_t phy_tmp;
3081
3082#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3083
3084 spin_lock_irqsave(&adapter->stats_lock, flags);
3085
3086 /* these counters are modified from e1000_adjust_tbi_stats,
3087 * called from the interrupt context, so they must only
3088 * be written while holding adapter->stats_lock
3089 */
3090
3091 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3092 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3093 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3094 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3095 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3096 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3097 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3098 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3099 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3100 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3101 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3102 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3103 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3104
3105 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3106 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3107 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3108 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3109 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3110 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3111 adapter->stats.dc += E1000_READ_REG(hw, DC);
3112 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3113 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3114 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3115 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3116 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3117 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3118 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3119 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3120 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3121 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3122 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3123 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3124 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3125 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3126 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3127 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3128 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3129 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3130 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3131 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3132 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3133 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3134 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3135 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3136 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3137 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3138 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3139
3140 /* used for adaptive IFS */
3141
3142 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3143 adapter->stats.tpt += hw->tx_packet_delta;
3144 hw->collision_delta = E1000_READ_REG(hw, COLC);
3145 adapter->stats.colc += hw->collision_delta;
3146
3147 if(hw->mac_type >= e1000_82543) {
3148 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3149 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3150 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3151 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3152 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3153 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3154 }
2d7edb92
MC		 3155 if(hw->mac_type > e1000_82547_rev_2) {
3156 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3157 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3158 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3159 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3160 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3161 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3162 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3163 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3164 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3165 }
1da177e4
LT		 3166
3167 /* Fill out the OS statistics structure */
3168
3169 adapter->net_stats.rx_packets = adapter->stats.gprc;
3170 adapter->net_stats.tx_packets = adapter->stats.gptc;
3171 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3172 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3173 adapter->net_stats.multicast = adapter->stats.mprc;
3174 adapter->net_stats.collisions = adapter->stats.colc;
3175
3176 /* Rx Errors */
3177
3178 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3179 adapter->stats.crcerrs + adapter->stats.algnerrc +
6b7660cd
JK		 3180 adapter->stats.rlec + adapter->stats.cexterr;
3181 adapter->net_stats.rx_dropped = 0;
1da177e4
LT		 3182 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3183 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3184 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3185 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3186
3187 /* Tx Errors */
3188
3189 adapter->net_stats.tx_errors = adapter->stats.ecol +
3190 adapter->stats.latecol;
3191 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3192 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3193 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3194
3195 /* Tx Dropped needs to be maintained elsewhere */
3196
3197 /* Phy Stats */
3198
3199 if(hw->media_type == e1000_media_type_copper) {
3200 if((adapter->link_speed == SPEED_1000) &&
3201 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3202 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3203 adapter->phy_stats.idle_errors += phy_tmp;
3204 }
3205
3206 if((hw->mac_type <= e1000_82546) &&
3207 (hw->phy_type == e1000_phy_m88) &&
3208 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3209 adapter->phy_stats.receive_errors += phy_tmp;
3210 }
3211
3212 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3213}
3214
24025e4e
MC		 3215#ifdef CONFIG_E1000_MQ
3216void
3217e1000_rx_schedule(void *data)
3218{
3219 struct net_device *poll_dev, *netdev = data;
3220 struct e1000_adapter *adapter = netdev->priv;
3221 int this_cpu = get_cpu();
3222
3223 poll_dev = *per_cpu_ptr(adapter->cpu_netdev, this_cpu);
3224 if (poll_dev == NULL) {
3225 put_cpu();
3226 return;
3227 }
3228
3229 if (likely(netif_rx_schedule_prep(poll_dev)))
3230 __netif_rx_schedule(poll_dev);
3231 else
3232 e1000_irq_enable(adapter);
3233
3234 put_cpu();
3235}
3236#endif
3237
1da177e4
LT		 3238/**
3239 * e1000_intr - Interrupt Handler
3240 * @irq: interrupt number
3241 * @data: pointer to a network interface device structure
3242 * @pt_regs: CPU registers structure
3243 **/
3244
3245static irqreturn_t
3246e1000_intr(int irq, void *data, struct pt_regs *regs)
3247{
3248 struct net_device *netdev = data;
60490fe0 3249 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3250 struct e1000_hw *hw = &adapter->hw;
3251 uint32_t icr = E1000_READ_REG(hw, ICR);
1e613fd9 3252#ifndef CONFIG_E1000_NAPI
581d708e 3253 int i;
1e613fd9
JK		 3254#else
3255 /* Interrupt Auto-Mask...upon reading ICR,
3256 * interrupts are masked. No need for the
3257 * IMC write, but it does mean we should
3258 * account for it ASAP. */
3259 if (likely(hw->mac_type >= e1000_82571))
3260 atomic_inc(&adapter->irq_sem);
be2b28ed 3261#endif
1da177e4 3262
1e613fd9
JK		 3263 if (unlikely(!icr)) {
3264#ifdef CONFIG_E1000_NAPI
3265 if (hw->mac_type >= e1000_82571)
3266 e1000_irq_enable(adapter);
3267#endif
1da177e4 3268 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3269 }
1da177e4
LT		 3270
3271 if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
3272 hw->get_link_status = 1;
3273 mod_timer(&adapter->watchdog_timer, jiffies);
3274 }
3275
3276#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3277 if (unlikely(hw->mac_type < e1000_82571)) {
3278 atomic_inc(&adapter->irq_sem);
3279 E1000_WRITE_REG(hw, IMC, ~0);
3280 E1000_WRITE_FLUSH(hw);
3281 }
24025e4e
MC		 3282#ifdef CONFIG_E1000_MQ
3283 if (atomic_read(&adapter->rx_sched_call_data.count) == 0) {
f56799ea
JK		 3284 /* We must setup the cpumask once count == 0 since
3285 * each cpu bit is cleared when the work is done. */
3286 adapter->rx_sched_call_data.cpumask = adapter->cpumask;
3287 atomic_add(adapter->num_rx_queues - 1, &adapter->irq_sem);
3288 atomic_set(&adapter->rx_sched_call_data.count,
3289 adapter->num_rx_queues);
24025e4e
MC		 3290 smp_call_async_mask(&adapter->rx_sched_call_data);
3291 } else {
3292 printk("call_data.count == %u\n", atomic_read(&adapter->rx_sched_call_data.count));
1da177e4 3293 }
be2b28ed 3294#else /* if !CONFIG_E1000_MQ */
581d708e
MC		 3295 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
3296 __netif_rx_schedule(&adapter->polling_netdev[0]);
3297 else
3298 e1000_irq_enable(adapter);
be2b28ed
JG		 3299#endif /* CONFIG_E1000_MQ */
3300
3301#else /* if !CONFIG_E1000_NAPI */
1da177e4
LT		 3302 /* Writing IMC and IMS is needed for 82547.
3303 Due to Hub Link bus being occupied, an interrupt
3304 de-assertion message is not able to be sent.
3305 When an interrupt assertion message is generated later,
3306 two messages are re-ordered and sent out.
3307 That causes APIC to think 82547 is in de-assertion
3308 state, while 82547 is in assertion state, resulting
3309 in dead lock. Writing IMC forces 82547 into
3310 de-assertion state.
3311 */
3312 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){
3313 atomic_inc(&adapter->irq_sem);
2648345f 3314 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3315 }
3316
3317 for(i = 0; i < E1000_MAX_INTR; i++)
581d708e
MC		 3318 if(unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
3319 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3320 break;
3321
3322 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
3323 e1000_irq_enable(adapter);
581d708e 3324
be2b28ed 3325#endif /* CONFIG_E1000_NAPI */
1da177e4
LT		 3326
3327 return IRQ_HANDLED;
3328}
3329
3330#ifdef CONFIG_E1000_NAPI
3331/**
3332 * e1000_clean - NAPI Rx polling callback
3333 * @adapter: board private structure
3334 **/
3335
3336static int
581d708e 3337e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3338{
581d708e
MC		 3339 struct e1000_adapter *adapter;
3340 int work_to_do = min(*budget, poll_dev->quota);
3341 int tx_cleaned, i = 0, work_done = 0;
3342
3343 /* Must NOT use netdev_priv macro here. */
3344 adapter = poll_dev->priv;
3345
3346 /* Keep link state information with original netdev */
3347 if (!netif_carrier_ok(adapter->netdev))
3348 goto quit_polling;
2648345f 3349
581d708e
MC		 3350 while (poll_dev != &adapter->polling_netdev[i]) {
3351 i++;
f56799ea 3352 if (unlikely(i == adapter->num_rx_queues))
581d708e
MC		 3353 BUG();
3354 }
3355
3356 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3357 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3358 &work_done, work_to_do);
1da177e4
LT		 3359
3360 *budget -= work_done;
581d708e 3361 poll_dev->quota -= work_done;
1da177e4 3362
2b02893e 3363 /* If no Tx and not enough Rx work done, exit the polling mode */
581d708e
MC		 3364 if((!tx_cleaned && (work_done == 0)) ||
3365 !netif_running(adapter->netdev)) {
3366quit_polling:
3367 netif_rx_complete(poll_dev);
1da177e4
LT		 3368 e1000_irq_enable(adapter);
3369 return 0;
3370 }
3371
3372 return 1;
3373}
3374
3375#endif
3376/**
3377 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3378 * @adapter: board private structure
3379 **/
3380
3381static boolean_t
581d708e
MC		 3382e1000_clean_tx_irq(struct e1000_adapter *adapter,
3383 struct e1000_tx_ring *tx_ring)
1da177e4 3384{
1da177e4
LT		 3385 struct net_device *netdev = adapter->netdev;
3386 struct e1000_tx_desc *tx_desc, *eop_desc;
3387 struct e1000_buffer *buffer_info;
3388 unsigned int i, eop;
3389 boolean_t cleaned = FALSE;
3390
3391 i = tx_ring->next_to_clean;
3392 eop = tx_ring->buffer_info[i].next_to_watch;
3393 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3394
581d708e 3395 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
1da177e4
LT		 3396 for(cleaned = FALSE; !cleaned; ) {
3397 tx_desc = E1000_TX_DESC(*tx_ring, i);
3398 buffer_info = &tx_ring->buffer_info[i];
3399 cleaned = (i == eop);
3400
fd803241 3401 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1da177e4
LT		 3402
3403 tx_desc->buffer_addr = 0;
3404 tx_desc->lower.data = 0;
3405 tx_desc->upper.data = 0;
3406
1da177e4
LT		 3407 if(unlikely(++i == tx_ring->count)) i = 0;
3408 }
581d708e 3409
7bfa4816
JK		 3410#ifdef CONFIG_E1000_MQ
3411 tx_ring->tx_stats.packets++;
3412#endif
3413
1da177e4
LT		 3414 eop = tx_ring->buffer_info[i].next_to_watch;
3415 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3416 }
3417
3418 tx_ring->next_to_clean = i;
3419
581d708e 3420 spin_lock(&tx_ring->tx_lock);
1da177e4
LT		 3421
3422 if(unlikely(cleaned && netif_queue_stopped(netdev) &&
3423 netif_carrier_ok(netdev)))
3424 netif_wake_queue(netdev);
3425
581d708e 3426 spin_unlock(&tx_ring->tx_lock);
2648345f 3427
581d708e 3428 if (adapter->detect_tx_hung) {
2648345f 3429 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3430 * check with the clearing of time_stamp and movement of i */
3431 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3432 if (tx_ring->buffer_info[eop].dma &&
3433 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
3434 adapter->tx_timeout_factor * HZ)
70b8f1e1 3435 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3436 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3437
3438 /* detected Tx unit hang */
c6963ef5 3439 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3440 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3441 " TDH <%x>\n"
3442 " TDT <%x>\n"
3443 " next_to_use <%x>\n"
3444 " next_to_clean <%x>\n"
3445 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3446 " time_stamp <%lx>\n"
3447 " next_to_watch <%x>\n"
3448 " jiffies <%lx>\n"
3449 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3450 (unsigned long)((tx_ring - adapter->tx_ring) /
3451 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3452 readl(adapter->hw.hw_addr + tx_ring->tdh),
3453 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3454 tx_ring->next_to_use,
392137fa
JK		 3455 tx_ring->next_to_clean,
3456 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3457 eop,
3458 jiffies,
3459 eop_desc->upper.fields.status);
1da177e4 3460 netif_stop_queue(netdev);
70b8f1e1 3461 }
1da177e4 3462 }
1da177e4
LT		 3463 return cleaned;
3464}
3465
3466/**
3467 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3468 * @adapter: board private structure
3469 * @status_err: receive descriptor status and error fields
3470 * @csum: receive descriptor csum field
3471 * @sk_buff: socket buffer with received data
1da177e4
LT		 3472 **/
3473
3474static inline void
3475e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3476 uint32_t status_err, uint32_t csum,
3477 struct sk_buff *skb)
1da177e4 3478{
2d7edb92
MC		 3479 uint16_t status = (uint16_t)status_err;
3480 uint8_t errors = (uint8_t)(status_err >> 24);
3481 skb->ip_summed = CHECKSUM_NONE;
3482
1da177e4 3483 /* 82543 or newer only */
2d7edb92 3484 if(unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3485 /* Ignore Checksum bit is set */
2d7edb92
MC		 3486 if(unlikely(status & E1000_RXD_STAT_IXSM)) return;
3487 /* TCP/UDP checksum error bit is set */
3488 if(unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3489 /* let the stack verify checksum errors */
1da177e4 3490 adapter->hw_csum_err++;
2d7edb92
MC		 3491 return;
3492 }
3493 /* TCP/UDP Checksum has not been calculated */
3494 if(adapter->hw.mac_type <= e1000_82547_rev_2) {
3495 if(!(status & E1000_RXD_STAT_TCPCS))
3496 return;
1da177e4 3497 } else {
2d7edb92
MC		 3498 if(!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
3499 return;
3500 }
3501 /* It must be a TCP or UDP packet with a valid checksum */
3502 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3503 /* TCP checksum is good */
3504 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3505 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3506 /* IP fragment with UDP payload */
3507 /* Hardware complements the payload checksum, so we undo it
3508 * and then put the value in host order for further stack use.
3509 */
3510 csum = ntohl(csum ^ 0xFFFF);
3511 skb->csum = csum;
3512 skb->ip_summed = CHECKSUM_HW;
1da177e4 3513 }
2d7edb92 3514 adapter->hw_csum_good++;
1da177e4
LT		 3515}
3516
3517/**
2d7edb92 3518 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3519 * @adapter: board private structure
3520 **/
3521
3522static boolean_t
3523#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3524e1000_clean_rx_irq(struct e1000_adapter *adapter,
3525 struct e1000_rx_ring *rx_ring,
3526 int *work_done, int work_to_do)
1da177e4 3527#else
581d708e
MC		 3528e1000_clean_rx_irq(struct e1000_adapter *adapter,
3529 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3530#endif
3531{
1da177e4
LT		 3532 struct net_device *netdev = adapter->netdev;
3533 struct pci_dev *pdev = adapter->pdev;
3534 struct e1000_rx_desc *rx_desc;
3535 struct e1000_buffer *buffer_info;
3536 struct sk_buff *skb;
3537 unsigned long flags;
3538 uint32_t length;
3539 uint8_t last_byte;
3540 unsigned int i;
3541 boolean_t cleaned = FALSE;
3542
3543 i = rx_ring->next_to_clean;
3544 rx_desc = E1000_RX_DESC(*rx_ring, i);
3545
3546 while(rx_desc->status & E1000_RXD_STAT_DD) {
3547 buffer_info = &rx_ring->buffer_info[i];
3548#ifdef CONFIG_E1000_NAPI
3549 if(*work_done >= work_to_do)
3550 break;
3551 (*work_done)++;
3552#endif
3553 cleaned = TRUE;
3554
3555 pci_unmap_single(pdev,
3556 buffer_info->dma,
3557 buffer_info->length,
3558 PCI_DMA_FROMDEVICE);
3559
3560 skb = buffer_info->skb;
3561 length = le16_to_cpu(rx_desc->length);
3562
3563 if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) {
3564 /* All receives must fit into a single buffer */
3565 E1000_DBG("%s: Receive packet consumed multiple"
2648345f 3566 " buffers\n", netdev->name);
1da177e4
LT		 3567 dev_kfree_skb_irq(skb);
3568 goto next_desc;
3569 }
3570
3571 if(unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
3572 last_byte = *(skb->data + length - 1);
3573 if(TBI_ACCEPT(&adapter->hw, rx_desc->status,
3574 rx_desc->errors, length, last_byte)) {
3575 spin_lock_irqsave(&adapter->stats_lock, flags);
3576 e1000_tbi_adjust_stats(&adapter->hw,
3577 &adapter->stats,
3578 length, skb->data);
3579 spin_unlock_irqrestore(&adapter->stats_lock,
3580 flags);
3581 length--;
3582 } else {
3583 dev_kfree_skb_irq(skb);
3584 goto next_desc;
3585 }
3586 }
3587
3588 /* Good Receive */
3589 skb_put(skb, length - ETHERNET_FCS_SIZE);
3590
3591 /* Receive Checksum Offload */
2d7edb92
MC		 3592 e1000_rx_checksum(adapter,
3593 (uint32_t)(rx_desc->status) |
3594 ((uint32_t)(rx_desc->errors) << 24),
3595 rx_desc->csum, skb);
1da177e4
LT		 3596 skb->protocol = eth_type_trans(skb, netdev);
3597#ifdef CONFIG_E1000_NAPI
3598 if(unlikely(adapter->vlgrp &&
3599 (rx_desc->status & E1000_RXD_STAT_VP))) {
3600 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3601 le16_to_cpu(rx_desc->special) &
3602 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3603 } else {
3604 netif_receive_skb(skb);
3605 }
3606#else /* CONFIG_E1000_NAPI */
3607 if(unlikely(adapter->vlgrp &&
3608 (rx_desc->status & E1000_RXD_STAT_VP))) {
3609 vlan_hwaccel_rx(skb, adapter->vlgrp,
3610 le16_to_cpu(rx_desc->special) &
3611 E1000_RXD_SPC_VLAN_MASK);
3612 } else {
3613 netif_rx(skb);
3614 }
3615#endif /* CONFIG_E1000_NAPI */
3616 netdev->last_rx = jiffies;
7bfa4816
JK		 3617#ifdef CONFIG_E1000_MQ
3618 rx_ring->rx_stats.packets++;
3619 rx_ring->rx_stats.bytes += length;
3620#endif
1da177e4
LT		 3621
3622next_desc:
3623 rx_desc->status = 0;
3624 buffer_info->skb = NULL;
3625 if(unlikely(++i == rx_ring->count)) i = 0;
3626
3627 rx_desc = E1000_RX_DESC(*rx_ring, i);
3628 }
1da177e4 3629 rx_ring->next_to_clean = i;
581d708e 3630 adapter->alloc_rx_buf(adapter, rx_ring);
2d7edb92
MC		 3631
3632 return cleaned;
3633}
3634
3635/**
3636 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3637 * @adapter: board private structure
3638 **/
3639
3640static boolean_t
3641#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3642e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3643 struct e1000_rx_ring *rx_ring,
3644 int *work_done, int work_to_do)
2d7edb92 3645#else
581d708e
MC		 3646e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3647 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3648#endif
3649{
2d7edb92
MC		 3650 union e1000_rx_desc_packet_split *rx_desc;
3651 struct net_device *netdev = adapter->netdev;
3652 struct pci_dev *pdev = adapter->pdev;
3653 struct e1000_buffer *buffer_info;
3654 struct e1000_ps_page *ps_page;
3655 struct e1000_ps_page_dma *ps_page_dma;
3656 struct sk_buff *skb;
3657 unsigned int i, j;
3658 uint32_t length, staterr;
3659 boolean_t cleaned = FALSE;
3660
3661 i = rx_ring->next_to_clean;
3662 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3663 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3664
3665 while(staterr & E1000_RXD_STAT_DD) {
3666 buffer_info = &rx_ring->buffer_info[i];
3667 ps_page = &rx_ring->ps_page[i];
3668 ps_page_dma = &rx_ring->ps_page_dma[i];
3669#ifdef CONFIG_E1000_NAPI
3670 if(unlikely(*work_done >= work_to_do))
3671 break;
3672 (*work_done)++;
3673#endif
3674 cleaned = TRUE;
3675 pci_unmap_single(pdev, buffer_info->dma,
3676 buffer_info->length,
3677 PCI_DMA_FROMDEVICE);
3678
3679 skb = buffer_info->skb;
3680
3681 if(unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
3682 E1000_DBG("%s: Packet Split buffers didn't pick up"
3683 " the full packet\n", netdev->name);
3684 dev_kfree_skb_irq(skb);
3685 goto next_desc;
3686 }
1da177e4 3687
2d7edb92
MC		 3688 if(unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3689 dev_kfree_skb_irq(skb);
3690 goto next_desc;
3691 }
3692
3693 length = le16_to_cpu(rx_desc->wb.middle.length0);
3694
3695 if(unlikely(!length)) {
3696 E1000_DBG("%s: Last part of the packet spanning"
3697 " multiple descriptors\n", netdev->name);
3698 dev_kfree_skb_irq(skb);
3699 goto next_desc;
3700 }
3701
3702 /* Good Receive */
3703 skb_put(skb, length);
3704
e4c811c9 3705 for(j = 0; j < adapter->rx_ps_pages; j++) {
2d7edb92
MC		 3706 if(!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
3707 break;
3708
3709 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3710 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3711 ps_page_dma->ps_page_dma[j] = 0;
3712 skb_shinfo(skb)->frags[j].page =
3713 ps_page->ps_page[j];
3714 ps_page->ps_page[j] = NULL;
3715 skb_shinfo(skb)->frags[j].page_offset = 0;
3716 skb_shinfo(skb)->frags[j].size = length;
3717 skb_shinfo(skb)->nr_frags++;
3718 skb->len += length;
3719 skb->data_len += length;
3720 }
3721
3722 e1000_rx_checksum(adapter, staterr,
3723 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
3724 skb->protocol = eth_type_trans(skb, netdev);
3725
2d7edb92 3726 if(likely(rx_desc->wb.upper.header_status &
e4c811c9
MC		 3727 E1000_RXDPS_HDRSTAT_HDRSP)) {
3728 adapter->rx_hdr_split++;
3729#ifdef HAVE_RX_ZERO_COPY
2d7edb92
MC		 3730 skb_shinfo(skb)->zero_copy = TRUE;
3731#endif
e4c811c9 3732 }
2d7edb92
MC		 3733#ifdef CONFIG_E1000_NAPI
3734 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3735 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3736 le16_to_cpu(rx_desc->wb.middle.vlan) &
3737 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3738 } else {
3739 netif_receive_skb(skb);
3740 }
3741#else /* CONFIG_E1000_NAPI */
3742 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3743 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3744 le16_to_cpu(rx_desc->wb.middle.vlan) &
3745 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3746 } else {
3747 netif_rx(skb);
3748 }
3749#endif /* CONFIG_E1000_NAPI */
3750 netdev->last_rx = jiffies;
7bfa4816
JK		 3751#ifdef CONFIG_E1000_MQ
3752 rx_ring->rx_stats.packets++;
3753 rx_ring->rx_stats.bytes += length;
3754#endif
2d7edb92
MC		 3755
3756next_desc:
3757 rx_desc->wb.middle.status_error &= ~0xFF;
3758 buffer_info->skb = NULL;
3759 if(unlikely(++i == rx_ring->count)) i = 0;
3760
3761 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3762 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3763 }
3764 rx_ring->next_to_clean = i;
581d708e 3765 adapter->alloc_rx_buf(adapter, rx_ring);
1da177e4
LT		 3766
3767 return cleaned;
3768}
3769
3770/**
2d7edb92 3771 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3772 * @adapter: address of board private structure
3773 **/
3774
3775static void
581d708e
MC		 3776e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3777 struct e1000_rx_ring *rx_ring)
1da177e4 3778{
1da177e4
LT		 3779 struct net_device *netdev = adapter->netdev;
3780 struct pci_dev *pdev = adapter->pdev;
3781 struct e1000_rx_desc *rx_desc;
3782 struct e1000_buffer *buffer_info;
3783 struct sk_buff *skb;
2648345f
MC		 3784 unsigned int i;
3785 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3786
3787 i = rx_ring->next_to_use;
3788 buffer_info = &rx_ring->buffer_info[i];
3789
3790 while(!buffer_info->skb) {
1da177e4 3791 skb = dev_alloc_skb(bufsz);
2648345f 3792
1da177e4
LT		 3793 if(unlikely(!skb)) {
3794 /* Better luck next round */
3795 break;
3796 }
3797
2648345f 3798 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3799 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3800 struct sk_buff *oldskb = skb;
2648345f
MC		 3801 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3802 "at %p\n", bufsz, skb->data);
3803 /* Try again, without freeing the previous */
1da177e4 3804 skb = dev_alloc_skb(bufsz);
2648345f 3805 /* Failed allocation, critical failure */
1da177e4
LT		 3806 if (!skb) {
3807 dev_kfree_skb(oldskb);
3808 break;
3809 }
2648345f 3810
1da177e4
LT		 3811 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3812 /* give up */
3813 dev_kfree_skb(skb);
3814 dev_kfree_skb(oldskb);
3815 break; /* while !buffer_info->skb */
3816 } else {
2648345f 3817 /* Use new allocation */
1da177e4
LT		 3818 dev_kfree_skb(oldskb);
3819 }
3820 }
1da177e4
LT		 3821 /* Make buffer alignment 2 beyond a 16 byte boundary
3822 * this will result in a 16 byte aligned IP header after
3823 * the 14 byte MAC header is removed
3824 */
3825 skb_reserve(skb, NET_IP_ALIGN);
3826
3827 skb->dev = netdev;
3828
3829 buffer_info->skb = skb;
3830 buffer_info->length = adapter->rx_buffer_len;
3831 buffer_info->dma = pci_map_single(pdev,
3832 skb->data,
3833 adapter->rx_buffer_len,
3834 PCI_DMA_FROMDEVICE);
3835
2648345f
MC		 3836 /* Fix for errata 23, can't cross 64kB boundary */
3837 if (!e1000_check_64k_bound(adapter,
3838 (void *)(unsigned long)buffer_info->dma,
3839 adapter->rx_buffer_len)) {
3840 DPRINTK(RX_ERR, ERR,
3841 "dma align check failed: %u bytes at %p\n",
3842 adapter->rx_buffer_len,
3843 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 3844 dev_kfree_skb(skb);
3845 buffer_info->skb = NULL;
3846
2648345f 3847 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 3848 adapter->rx_buffer_len,
3849 PCI_DMA_FROMDEVICE);
3850
3851 break; /* while !buffer_info->skb */
3852 }
1da177e4
LT		 3853 rx_desc = E1000_RX_DESC(*rx_ring, i);
3854 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3855
3856 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3857 /* Force memory writes to complete before letting h/w
3858 * know there are new descriptors to fetch. (Only
3859 * applicable for weak-ordered memory model archs,
3860 * such as IA-64). */
3861 wmb();
581d708e 3862 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
1da177e4
LT		 3863 }
3864
3865 if(unlikely(++i == rx_ring->count)) i = 0;
3866 buffer_info = &rx_ring->buffer_info[i];
3867 }
3868
3869 rx_ring->next_to_use = i;
3870}
3871
2d7edb92
MC		 3872/**
3873 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3874 * @adapter: address of board private structure
3875 **/
3876
3877static void
581d708e
MC		 3878e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
3879 struct e1000_rx_ring *rx_ring)
2d7edb92 3880{
2d7edb92
MC		 3881 struct net_device *netdev = adapter->netdev;
3882 struct pci_dev *pdev = adapter->pdev;
3883 union e1000_rx_desc_packet_split *rx_desc;
3884 struct e1000_buffer *buffer_info;
3885 struct e1000_ps_page *ps_page;
3886 struct e1000_ps_page_dma *ps_page_dma;
3887 struct sk_buff *skb;
3888 unsigned int i, j;
3889
3890 i = rx_ring->next_to_use;
3891 buffer_info = &rx_ring->buffer_info[i];
3892 ps_page = &rx_ring->ps_page[i];
3893 ps_page_dma = &rx_ring->ps_page_dma[i];
3894
3895 while(!buffer_info->skb) {
3896 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3897
3898 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 3899 if (j < adapter->rx_ps_pages) {
3900 if (likely(!ps_page->ps_page[j])) {
3901 ps_page->ps_page[j] =
3902 alloc_page(GFP_ATOMIC);
3903 if (unlikely(!ps_page->ps_page[j]))
3904 goto no_buffers;
3905 ps_page_dma->ps_page_dma[j] =
3906 pci_map_page(pdev,
3907 ps_page->ps_page[j],
3908 0, PAGE_SIZE,
3909 PCI_DMA_FROMDEVICE);
3910 }
3911 /* Refresh the desc even if buffer_addrs didn't
3912 * change because each write-back erases
3913 * this info.
3914 */
3915 rx_desc->read.buffer_addr[j+1] =
3916 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
3917 } else
3918 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 3919 }
3920
3921 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3922
3923 if(unlikely(!skb))
3924 break;
3925
3926 /* Make buffer alignment 2 beyond a 16 byte boundary
3927 * this will result in a 16 byte aligned IP header after
3928 * the 14 byte MAC header is removed
3929 */
3930 skb_reserve(skb, NET_IP_ALIGN);
3931
3932 skb->dev = netdev;
3933
3934 buffer_info->skb = skb;
3935 buffer_info->length = adapter->rx_ps_bsize0;
3936 buffer_info->dma = pci_map_single(pdev, skb->data,
3937 adapter->rx_ps_bsize0,
3938 PCI_DMA_FROMDEVICE);
3939
3940 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
3941
3942 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3943 /* Force memory writes to complete before letting h/w
3944 * know there are new descriptors to fetch. (Only
3945 * applicable for weak-ordered memory model archs,
3946 * such as IA-64). */
3947 wmb();
3948 /* Hardware increments by 16 bytes, but packet split
3949 * descriptors are 32 bytes...so we increment tail
3950 * twice as much.
3951 */
581d708e 3952 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
2d7edb92
MC		 3953 }
3954
3955 if(unlikely(++i == rx_ring->count)) i = 0;
3956 buffer_info = &rx_ring->buffer_info[i];
3957 ps_page = &rx_ring->ps_page[i];
3958 ps_page_dma = &rx_ring->ps_page_dma[i];
3959 }
3960
3961no_buffers:
3962 rx_ring->next_to_use = i;
3963}
3964
1da177e4
LT		 3965/**
3966 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
3967 * @adapter:
3968 **/
3969
3970static void
3971e1000_smartspeed(struct e1000_adapter *adapter)
3972{
3973 uint16_t phy_status;
3974 uint16_t phy_ctrl;
3975
3976 if((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
3977 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
3978 return;
3979
3980 if(adapter->smartspeed == 0) {
3981 /* If Master/Slave config fault is asserted twice,
3982 * we assume back-to-back */
3983 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
3984 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
3985 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
3986 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
3987 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
3988 if(phy_ctrl & CR_1000T_MS_ENABLE) {
3989 phy_ctrl &= ~CR_1000T_MS_ENABLE;
3990 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
3991 phy_ctrl);
3992 adapter->smartspeed++;
3993 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
3994 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
3995 &phy_ctrl)) {
3996 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
3997 MII_CR_RESTART_AUTO_NEG);
3998 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
3999 phy_ctrl);
4000 }
4001 }
4002 return;
4003 } else if(adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
4004 /* If still no link, perhaps using 2/3 pair cable */
4005 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4006 phy_ctrl |= CR_1000T_MS_ENABLE;
4007 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
4008 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
4009 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4010 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4011 MII_CR_RESTART_AUTO_NEG);
4012 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4013 }
4014 }
4015 /* Restart process after E1000_SMARTSPEED_MAX iterations */
4016 if(adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
4017 adapter->smartspeed = 0;
4018}
4019
4020/**
4021 * e1000_ioctl -
4022 * @netdev:
4023 * @ifreq:
4024 * @cmd:
4025 **/
4026
4027static int
4028e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4029{
4030 switch (cmd) {
4031 case SIOCGMIIPHY:
4032 case SIOCGMIIREG:
4033 case SIOCSMIIREG:
4034 return e1000_mii_ioctl(netdev, ifr, cmd);
4035 default:
4036 return -EOPNOTSUPP;
4037 }
4038}
4039
4040/**
4041 * e1000_mii_ioctl -
4042 * @netdev:
4043 * @ifreq:
4044 * @cmd:
4045 **/
4046
4047static int
4048e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4049{
60490fe0 4050 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4051 struct mii_ioctl_data *data = if_mii(ifr);
4052 int retval;
4053 uint16_t mii_reg;
4054 uint16_t spddplx;
97876fc6 4055 unsigned long flags;
1da177e4
LT		 4056
4057 if(adapter->hw.media_type != e1000_media_type_copper)
4058 return -EOPNOTSUPP;
4059
4060 switch (cmd) {
4061 case SIOCGMIIPHY:
4062 data->phy_id = adapter->hw.phy_addr;
4063 break;
4064 case SIOCGMIIREG:
97876fc6 4065 if(!capable(CAP_NET_ADMIN))
1da177e4 4066 return -EPERM;
97876fc6
MC		 4067 spin_lock_irqsave(&adapter->stats_lock, flags);
4068 if(e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4069 &data->val_out)) {
4070 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4071 return -EIO;
97876fc6
MC		 4072 }
4073 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4074 break;
4075 case SIOCSMIIREG:
97876fc6 4076 if(!capable(CAP_NET_ADMIN))
1da177e4 4077 return -EPERM;
97876fc6 4078 if(data->reg_num & ~(0x1F))
1da177e4
LT		 4079 return -EFAULT;
4080 mii_reg = data->val_in;
97876fc6
MC		 4081 spin_lock_irqsave(&adapter->stats_lock, flags);
4082 if(e1000_write_phy_reg(&adapter->hw, data->reg_num,
4083 mii_reg)) {
4084 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4085 return -EIO;
97876fc6
MC		 4086 }
4087 if(adapter->hw.phy_type == e1000_phy_m88) {
1da177e4
LT		 4088 switch (data->reg_num) {
4089 case PHY_CTRL:
4090 if(mii_reg & MII_CR_POWER_DOWN)
4091 break;
4092 if(mii_reg & MII_CR_AUTO_NEG_EN) {
4093 adapter->hw.autoneg = 1;
4094 adapter->hw.autoneg_advertised = 0x2F;
4095 } else {
4096 if (mii_reg & 0x40)
4097 spddplx = SPEED_1000;
4098 else if (mii_reg & 0x2000)
4099 spddplx = SPEED_100;
4100 else
4101 spddplx = SPEED_10;
4102 spddplx += (mii_reg & 0x100)
4103 ? FULL_DUPLEX :
4104 HALF_DUPLEX;
4105 retval = e1000_set_spd_dplx(adapter,
4106 spddplx);
97876fc6
MC		 4107 if(retval) {
4108 spin_unlock_irqrestore(
4109 &adapter->stats_lock,
4110 flags);
1da177e4 4111 return retval;
97876fc6 4112 }
1da177e4
LT		 4113 }
4114 if(netif_running(adapter->netdev)) {
4115 e1000_down(adapter);
4116 e1000_up(adapter);
4117 } else
4118 e1000_reset(adapter);
4119 break;
4120 case M88E1000_PHY_SPEC_CTRL:
4121 case M88E1000_EXT_PHY_SPEC_CTRL:
97876fc6
MC		 4122 if(e1000_phy_reset(&adapter->hw)) {
4123 spin_unlock_irqrestore(
4124 &adapter->stats_lock, flags);
1da177e4 4125 return -EIO;
97876fc6 4126 }
1da177e4
LT		 4127 break;
4128 }
4129 } else {
4130 switch (data->reg_num) {
4131 case PHY_CTRL:
4132 if(mii_reg & MII_CR_POWER_DOWN)
4133 break;
4134 if(netif_running(adapter->netdev)) {
4135 e1000_down(adapter);
4136 e1000_up(adapter);
4137 } else
4138 e1000_reset(adapter);
4139 break;
4140 }
4141 }
97876fc6 4142 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4143 break;
4144 default:
4145 return -EOPNOTSUPP;
4146 }
4147 return E1000_SUCCESS;
4148}
4149
4150void
4151e1000_pci_set_mwi(struct e1000_hw *hw)
4152{
4153 struct e1000_adapter *adapter = hw->back;
2648345f 4154 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4155
2648345f
MC		 4156 if(ret_val)
4157 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4158}
4159
4160void
4161e1000_pci_clear_mwi(struct e1000_hw *hw)
4162{
4163 struct e1000_adapter *adapter = hw->back;
4164
4165 pci_clear_mwi(adapter->pdev);
4166}
4167
4168void
4169e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4170{
4171 struct e1000_adapter *adapter = hw->back;
4172
4173 pci_read_config_word(adapter->pdev, reg, value);
4174}
4175
4176void
4177e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4178{
4179 struct e1000_adapter *adapter = hw->back;
4180
4181 pci_write_config_word(adapter->pdev, reg, *value);
4182}
4183
4184uint32_t
4185e1000_io_read(struct e1000_hw *hw, unsigned long port)
4186{
4187 return inl(port);
4188}
4189
4190void
4191e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4192{
4193 outl(value, port);
4194}
4195
4196static void
4197e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4198{
60490fe0 4199 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4200 uint32_t ctrl, rctl;
4201
4202 e1000_irq_disable(adapter);
4203 adapter->vlgrp = grp;
4204
4205 if(grp) {
4206 /* enable VLAN tag insert/strip */
4207 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4208 ctrl |= E1000_CTRL_VME;
4209 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4210
4211 /* enable VLAN receive filtering */
4212 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4213 rctl |= E1000_RCTL_VFE;
4214 rctl &= ~E1000_RCTL_CFIEN;
4215 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4216 e1000_update_mng_vlan(adapter);
1da177e4
LT		 4217 } else {
4218 /* disable VLAN tag insert/strip */
4219 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4220 ctrl &= ~E1000_CTRL_VME;
4221 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4222
4223 /* disable VLAN filtering */
4224 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4225 rctl &= ~E1000_RCTL_VFE;
4226 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92
MC		 4227 if(adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
4228 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4229 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4230 }
1da177e4
LT		 4231 }
4232
4233 e1000_irq_enable(adapter);
4234}
4235
4236static void
4237e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4238{
60490fe0 4239 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4240 uint32_t vfta, index;
2d7edb92
MC		 4241 if((adapter->hw.mng_cookie.status &
4242 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4243 (vid == adapter->mng_vlan_id))
4244 return;
1da177e4
LT		 4245 /* add VID to filter table */
4246 index = (vid >> 5) & 0x7F;
4247 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4248 vfta |= (1 << (vid & 0x1F));
4249 e1000_write_vfta(&adapter->hw, index, vfta);
4250}
4251
4252static void
4253e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4254{
60490fe0 4255 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4256 uint32_t vfta, index;
4257
4258 e1000_irq_disable(adapter);
4259
4260 if(adapter->vlgrp)
4261 adapter->vlgrp->vlan_devices[vid] = NULL;
4262
4263 e1000_irq_enable(adapter);
4264
2d7edb92
MC		 4265 if((adapter->hw.mng_cookie.status &
4266 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4267 (vid == adapter->mng_vlan_id)) {
4268 /* release control to f/w */
4269 e1000_release_hw_control(adapter);
2d7edb92 4270 return;
ff147013
JK		 4271 }
4272
1da177e4
LT		 4273 /* remove VID from filter table */
4274 index = (vid >> 5) & 0x7F;
4275 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4276 vfta &= ~(1 << (vid & 0x1F));
4277 e1000_write_vfta(&adapter->hw, index, vfta);
4278}
4279
4280static void
4281e1000_restore_vlan(struct e1000_adapter *adapter)
4282{
4283 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4284
4285 if(adapter->vlgrp) {
4286 uint16_t vid;
4287 for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4288 if(!adapter->vlgrp->vlan_devices[vid])
4289 continue;
4290 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4291 }
4292 }
4293}
4294
4295int
4296e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4297{
4298 adapter->hw.autoneg = 0;
4299
6921368f
MC		 4300 /* Fiber NICs only allow 1000 gbps Full duplex */
4301 if((adapter->hw.media_type == e1000_media_type_fiber) &&
4302 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4303 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4304 return -EINVAL;
4305 }
4306
1da177e4
LT		 4307 switch(spddplx) {
4308 case SPEED_10 + DUPLEX_HALF:
4309 adapter->hw.forced_speed_duplex = e1000_10_half;
4310 break;
4311 case SPEED_10 + DUPLEX_FULL:
4312 adapter->hw.forced_speed_duplex = e1000_10_full;
4313 break;
4314 case SPEED_100 + DUPLEX_HALF:
4315 adapter->hw.forced_speed_duplex = e1000_100_half;
4316 break;
4317 case SPEED_100 + DUPLEX_FULL:
4318 adapter->hw.forced_speed_duplex = e1000_100_full;
4319 break;
4320 case SPEED_1000 + DUPLEX_FULL:
4321 adapter->hw.autoneg = 1;
4322 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4323 break;
4324 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4325 default:
2648345f 4326 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4327 return -EINVAL;
4328 }
4329 return 0;
4330}
4331
b6a1d5f8 4332#ifdef CONFIG_PM
1da177e4 4333static int
829ca9a3 4334e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4335{
4336 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4337 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4338 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4
LT		 4339 uint32_t wufc = adapter->wol;
4340
4341 netif_device_detach(netdev);
4342
4343 if(netif_running(netdev))
4344 e1000_down(adapter);
4345
4346 status = E1000_READ_REG(&adapter->hw, STATUS);
4347 if(status & E1000_STATUS_LU)
4348 wufc &= ~E1000_WUFC_LNKC;
4349
4350 if(wufc) {
4351 e1000_setup_rctl(adapter);
4352 e1000_set_multi(netdev);
4353
4354 /* turn on all-multi mode if wake on multicast is enabled */
4355 if(adapter->wol & E1000_WUFC_MC) {
4356 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4357 rctl |= E1000_RCTL_MPE;
4358 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4359 }
4360
4361 if(adapter->hw.mac_type >= e1000_82540) {
4362 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4363 /* advertise wake from D3Cold */
4364 #define E1000_CTRL_ADVD3WUC 0x00100000
4365 /* phy power management enable */
4366 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4367 ctrl |= E1000_CTRL_ADVD3WUC |
4368 E1000_CTRL_EN_PHY_PWR_MGMT;
4369 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4370 }
4371
4372 if(adapter->hw.media_type == e1000_media_type_fiber ||
4373 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4374 /* keep the laser running in D3 */
4375 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4376 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4377 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4378 }
4379
2d7edb92
MC		 4380 /* Allow time for pending master requests to run */
4381 e1000_disable_pciex_master(&adapter->hw);
4382
1da177e4
LT		 4383 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4384 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
4385 pci_enable_wake(pdev, 3, 1);
4386 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
4387 } else {
4388 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4389 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
4390 pci_enable_wake(pdev, 3, 0);
4391 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
4392 }
4393
4394 pci_save_state(pdev);
4395
4396 if(adapter->hw.mac_type >= e1000_82540 &&
4397 adapter->hw.media_type == e1000_media_type_copper) {
4398 manc = E1000_READ_REG(&adapter->hw, MANC);
4399 if(manc & E1000_MANC_SMBUS_EN) {
4400 manc |= E1000_MANC_ARP_EN;
4401 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4402 pci_enable_wake(pdev, 3, 1);
4403 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
4404 }
4405 }
4406
b55ccb35
JK		 4407 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4408 * would have already happened in close and is redundant. */
4409 e1000_release_hw_control(adapter);
2d7edb92 4410
1da177e4 4411 pci_disable_device(pdev);
829ca9a3 4412 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4413
4414 return 0;
4415}
4416
1da177e4
LT		 4417static int
4418e1000_resume(struct pci_dev *pdev)
4419{
4420 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4421 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4422 uint32_t manc, ret_val;
1da177e4 4423
829ca9a3 4424 pci_set_power_state(pdev, PCI_D0);
1da177e4 4425 pci_restore_state(pdev);
2b02893e 4426 ret_val = pci_enable_device(pdev);
a4cb847d 4427 pci_set_master(pdev);
1da177e4 4428
829ca9a3
PM		 4429 pci_enable_wake(pdev, PCI_D3hot, 0);
4430 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4431
4432 e1000_reset(adapter);
4433 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4434
4435 if(netif_running(netdev))
4436 e1000_up(adapter);
4437
4438 netif_device_attach(netdev);
4439
4440 if(adapter->hw.mac_type >= e1000_82540 &&
4441 adapter->hw.media_type == e1000_media_type_copper) {
4442 manc = E1000_READ_REG(&adapter->hw, MANC);
4443 manc &= ~(E1000_MANC_ARP_EN);
4444 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4445 }
4446
b55ccb35
JK		 4447 /* If the controller is 82573 and f/w is AMT, do not set
4448 * DRV_LOAD until the interface is up. For all other cases,
4449 * let the f/w know that the h/w is now under the control
4450 * of the driver. */
4451 if (adapter->hw.mac_type != e1000_82573 ||
4452 !e1000_check_mng_mode(&adapter->hw))
4453 e1000_get_hw_control(adapter);
2d7edb92 4454
1da177e4
LT		 4455 return 0;
4456}
4457#endif
1da177e4
LT		 4458#ifdef CONFIG_NET_POLL_CONTROLLER
4459/*
4460 * Polling 'interrupt' - used by things like netconsole to send skbs
4461 * without having to re-enable interrupts. It's not called while
4462 * the interrupt routine is executing.
4463 */
4464static void
2648345f 4465e1000_netpoll(struct net_device *netdev)
1da177e4 4466{
60490fe0 4467 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4468 disable_irq(adapter->pdev->irq);
4469 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4470 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4471#ifndef CONFIG_E1000_NAPI
4472 adapter->clean_rx(adapter, adapter->rx_ring);
4473#endif
1da177e4
LT		 4474 enable_irq(adapter->pdev->irq);
4475}
4476#endif
4477
4478/* e1000_main.c */
Linux kernel - Deliverables
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