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e1000: IRQ resources cleanup
[deliverable/linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
3d41e30a 4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
3d41e30a 25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27
28*******************************************************************************/
29
30#include "e1000.h"
31
1da177e4 32char e1000_driver_name[] = "e1000";
3ad2cc67 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 34#ifndef CONFIG_E1000_NAPI
35#define DRIVERNAPI
36#else
37#define DRIVERNAPI "-NAPI"
38#endif
dc335d97 39#define DRV_VERSION "7.1.9-k6"DRIVERNAPI
1da177e4 40char e1000_driver_version[] = DRV_VERSION;
3d41e30a 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
1da177e4
LT		 42
43/* e1000_pci_tbl - PCI Device ID Table
44 *
45 * Last entry must be all 0s
46 *
47 * Macro expands to...
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */
50static struct pci_device_id e1000_pci_tbl[] = {
1da177e4
LT		 51 INTEL_E1000_ETHERNET_DEVICE(0x1001),
52 INTEL_E1000_ETHERNET_DEVICE(0x1004),
53 INTEL_E1000_ETHERNET_DEVICE(0x1008),
54 INTEL_E1000_ETHERNET_DEVICE(0x1009),
55 INTEL_E1000_ETHERNET_DEVICE(0x100C),
56 INTEL_E1000_ETHERNET_DEVICE(0x100D),
57 INTEL_E1000_ETHERNET_DEVICE(0x100E),
58 INTEL_E1000_ETHERNET_DEVICE(0x100F),
59 INTEL_E1000_ETHERNET_DEVICE(0x1010),
60 INTEL_E1000_ETHERNET_DEVICE(0x1011),
61 INTEL_E1000_ETHERNET_DEVICE(0x1012),
62 INTEL_E1000_ETHERNET_DEVICE(0x1013),
63 INTEL_E1000_ETHERNET_DEVICE(0x1014),
64 INTEL_E1000_ETHERNET_DEVICE(0x1015),
65 INTEL_E1000_ETHERNET_DEVICE(0x1016),
66 INTEL_E1000_ETHERNET_DEVICE(0x1017),
67 INTEL_E1000_ETHERNET_DEVICE(0x1018),
68 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 69 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 70 INTEL_E1000_ETHERNET_DEVICE(0x101D),
71 INTEL_E1000_ETHERNET_DEVICE(0x101E),
72 INTEL_E1000_ETHERNET_DEVICE(0x1026),
73 INTEL_E1000_ETHERNET_DEVICE(0x1027),
74 INTEL_E1000_ETHERNET_DEVICE(0x1028),
ae2c3860
AK		 75 INTEL_E1000_ETHERNET_DEVICE(0x1049),
76 INTEL_E1000_ETHERNET_DEVICE(0x104A),
77 INTEL_E1000_ETHERNET_DEVICE(0x104B),
78 INTEL_E1000_ETHERNET_DEVICE(0x104C),
79 INTEL_E1000_ETHERNET_DEVICE(0x104D),
07b8fede
MC		 80 INTEL_E1000_ETHERNET_DEVICE(0x105E),
81 INTEL_E1000_ETHERNET_DEVICE(0x105F),
82 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 83 INTEL_E1000_ETHERNET_DEVICE(0x1075),
84 INTEL_E1000_ETHERNET_DEVICE(0x1076),
85 INTEL_E1000_ETHERNET_DEVICE(0x1077),
86 INTEL_E1000_ETHERNET_DEVICE(0x1078),
87 INTEL_E1000_ETHERNET_DEVICE(0x1079),
88 INTEL_E1000_ETHERNET_DEVICE(0x107A),
89 INTEL_E1000_ETHERNET_DEVICE(0x107B),
90 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 91 INTEL_E1000_ETHERNET_DEVICE(0x107D),
92 INTEL_E1000_ETHERNET_DEVICE(0x107E),
93 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 94 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 95 INTEL_E1000_ETHERNET_DEVICE(0x108B),
96 INTEL_E1000_ETHERNET_DEVICE(0x108C),
6418ecc6
JK		 97 INTEL_E1000_ETHERNET_DEVICE(0x1096),
98 INTEL_E1000_ETHERNET_DEVICE(0x1098),
b7ee49db 99 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 100 INTEL_E1000_ETHERNET_DEVICE(0x109A),
b7ee49db 101 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
6418ecc6 102 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
ae2c3860
AK		 103 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
104 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
1da177e4
LT		 105 /* required last entry */
106 {0,}
107};
108
109MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
110
3ad2cc67 111static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 112 struct e1000_tx_ring *txdr);
3ad2cc67 113static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 114 struct e1000_rx_ring *rxdr);
3ad2cc67 115static void e1000_free_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 116 struct e1000_tx_ring *tx_ring);
3ad2cc67 117static void e1000_free_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 118 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 119
120/* Local Function Prototypes */
121
122static int e1000_init_module(void);
123static void e1000_exit_module(void);
124static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
125static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 126static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 127static int e1000_sw_init(struct e1000_adapter *adapter);
128static int e1000_open(struct net_device *netdev);
129static int e1000_close(struct net_device *netdev);
130static void e1000_configure_tx(struct e1000_adapter *adapter);
131static void e1000_configure_rx(struct e1000_adapter *adapter);
132static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 133static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
134static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
135static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
136 struct e1000_tx_ring *tx_ring);
137static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
138 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 139static void e1000_set_multi(struct net_device *netdev);
140static void e1000_update_phy_info(unsigned long data);
141static void e1000_watchdog(unsigned long data);
1da177e4
LT		 142static void e1000_82547_tx_fifo_stall(unsigned long data);
143static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
144static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
145static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
146static int e1000_set_mac(struct net_device *netdev, void *p);
147static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 148static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
149 struct e1000_tx_ring *tx_ring);
1da177e4 150#ifdef CONFIG_E1000_NAPI
581d708e 151static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 152static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 153 struct e1000_rx_ring *rx_ring,
1da177e4 154 int *work_done, int work_to_do);
2d7edb92 155static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 156 struct e1000_rx_ring *rx_ring,
2d7edb92 157 int *work_done, int work_to_do);
1da177e4 158#else
581d708e
MC		 159static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
160 struct e1000_rx_ring *rx_ring);
161static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
162 struct e1000_rx_ring *rx_ring);
1da177e4 163#endif
581d708e 164static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 165 struct e1000_rx_ring *rx_ring,
166 int cleaned_count);
581d708e 167static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 168 struct e1000_rx_ring *rx_ring,
169 int cleaned_count);
1da177e4
LT		 170static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
171static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
172 int cmd);
1da177e4
LT		 173static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
174static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
175static void e1000_tx_timeout(struct net_device *dev);
87041639 176static void e1000_reset_task(struct net_device *dev);
1da177e4 177static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 178static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
179 struct sk_buff *skb);
1da177e4
LT		 180
181static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
182static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
183static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
184static void e1000_restore_vlan(struct e1000_adapter *adapter);
185
977e74b5 186static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
6fdfef16 187#ifdef CONFIG_PM
1da177e4
LT		 188static int e1000_resume(struct pci_dev *pdev);
189#endif
c653e635 190static void e1000_shutdown(struct pci_dev *pdev);
1da177e4
LT		 191
192#ifdef CONFIG_NET_POLL_CONTROLLER
193/* for netdump / net console */
194static void e1000_netpoll (struct net_device *netdev);
195#endif
196
9026729b
AK		 197static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
198 pci_channel_state_t state);
199static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
200static void e1000_io_resume(struct pci_dev *pdev);
201
202static struct pci_error_handlers e1000_err_handler = {
203 .error_detected = e1000_io_error_detected,
204 .slot_reset = e1000_io_slot_reset,
205 .resume = e1000_io_resume,
206};
24025e4e 207
1da177e4
LT		 208static struct pci_driver e1000_driver = {
209 .name = e1000_driver_name,
210 .id_table = e1000_pci_tbl,
211 .probe = e1000_probe,
212 .remove = __devexit_p(e1000_remove),
213 /* Power Managment Hooks */
1da177e4 214 .suspend = e1000_suspend,
6fdfef16 215#ifdef CONFIG_PM
c653e635 216 .resume = e1000_resume,
1da177e4 217#endif
9026729b
AK		 218 .shutdown = e1000_shutdown,
219 .err_handler = &e1000_err_handler
1da177e4
LT		 220};
221
222MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
223MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(DRV_VERSION);
226
227static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
228module_param(debug, int, 0);
229MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
230
231/**
232 * e1000_init_module - Driver Registration Routine
233 *
234 * e1000_init_module is the first routine called when the driver is
235 * loaded. All it does is register with the PCI subsystem.
236 **/
237
238static int __init
239e1000_init_module(void)
240{
241 int ret;
242 printk(KERN_INFO "%s - version %s\n",
243 e1000_driver_string, e1000_driver_version);
244
245 printk(KERN_INFO "%s\n", e1000_copyright);
246
29917620 247 ret = pci_register_driver(&e1000_driver);
8b378def 248
1da177e4
LT		 249 return ret;
250}
251
252module_init(e1000_init_module);
253
254/**
255 * e1000_exit_module - Driver Exit Cleanup Routine
256 *
257 * e1000_exit_module is called just before the driver is removed
258 * from memory.
259 **/
260
261static void __exit
262e1000_exit_module(void)
263{
1da177e4
LT		 264 pci_unregister_driver(&e1000_driver);
265}
266
267module_exit(e1000_exit_module);
268
2db10a08
AK		 269static int e1000_request_irq(struct e1000_adapter *adapter)
270{
271 struct net_device *netdev = adapter->netdev;
272 int flags, err = 0;
273
c0bc8721 274 flags = IRQF_SHARED;
2db10a08
AK		 275#ifdef CONFIG_PCI_MSI
276 if (adapter->hw.mac_type > e1000_82547_rev_2) {
277 adapter->have_msi = TRUE;
278 if ((err = pci_enable_msi(adapter->pdev))) {
279 DPRINTK(PROBE, ERR,
280 "Unable to allocate MSI interrupt Error: %d\n", err);
281 adapter->have_msi = FALSE;
282 }
283 }
284 if (adapter->have_msi)
61ef5c00 285 flags &= ~IRQF_SHARED;
2db10a08
AK		 286#endif
287 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags,
288 netdev->name, netdev)))
289 DPRINTK(PROBE, ERR,
290 "Unable to allocate interrupt Error: %d\n", err);
291
292 return err;
293}
294
295static void e1000_free_irq(struct e1000_adapter *adapter)
296{
297 struct net_device *netdev = adapter->netdev;
298
299 free_irq(adapter->pdev->irq, netdev);
300
301#ifdef CONFIG_PCI_MSI
302 if (adapter->have_msi)
303 pci_disable_msi(adapter->pdev);
304#endif
305}
306
1da177e4
LT		 307/**
308 * e1000_irq_disable - Mask off interrupt generation on the NIC
309 * @adapter: board private structure
310 **/
311
e619d523 312static void
1da177e4
LT		 313e1000_irq_disable(struct e1000_adapter *adapter)
314{
315 atomic_inc(&adapter->irq_sem);
316 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
317 E1000_WRITE_FLUSH(&adapter->hw);
318 synchronize_irq(adapter->pdev->irq);
319}
320
321/**
322 * e1000_irq_enable - Enable default interrupt generation settings
323 * @adapter: board private structure
324 **/
325
e619d523 326static void
1da177e4
LT		 327e1000_irq_enable(struct e1000_adapter *adapter)
328{
96838a40 329 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 330 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
331 E1000_WRITE_FLUSH(&adapter->hw);
332 }
333}
3ad2cc67
AB		 334
335static void
2d7edb92
MC		 336e1000_update_mng_vlan(struct e1000_adapter *adapter)
337{
338 struct net_device *netdev = adapter->netdev;
339 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
340 uint16_t old_vid = adapter->mng_vlan_id;
96838a40
JB		 341 if (adapter->vlgrp) {
342 if (!adapter->vlgrp->vlan_devices[vid]) {
343 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 344 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
345 e1000_vlan_rx_add_vid(netdev, vid);
346 adapter->mng_vlan_id = vid;
347 } else
348 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 349
350 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
351 (vid != old_vid) &&
2d7edb92
MC		 352 !adapter->vlgrp->vlan_devices[old_vid])
353 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 354 } else
355 adapter->mng_vlan_id = vid;
2d7edb92
MC		 356 }
357}
b55ccb35
JK		 358
359/**
360 * e1000_release_hw_control - release control of the h/w to f/w
361 * @adapter: address of board private structure
362 *
363 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
364 * For ASF and Pass Through versions of f/w this means that the
365 * driver is no longer loaded. For AMT version (only with 82573) i
366 * of the f/w this means that the netowrk i/f is closed.
76c224bc 367 *
b55ccb35
JK		 368 **/
369
e619d523 370static void
b55ccb35
JK		 371e1000_release_hw_control(struct e1000_adapter *adapter)
372{
373 uint32_t ctrl_ext;
374 uint32_t swsm;
cd94dd0b 375 uint32_t extcnf;
b55ccb35
JK		 376
377 /* Let firmware taken over control of h/w */
378 switch (adapter->hw.mac_type) {
379 case e1000_82571:
380 case e1000_82572:
4cc15f54 381 case e1000_80003es2lan:
b55ccb35
JK		 382 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
383 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
384 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
385 break;
386 case e1000_82573:
387 swsm = E1000_READ_REG(&adapter->hw, SWSM);
388 E1000_WRITE_REG(&adapter->hw, SWSM,
389 swsm & ~E1000_SWSM_DRV_LOAD);
cd94dd0b
AK		 390 case e1000_ich8lan:
391 extcnf = E1000_READ_REG(&adapter->hw, CTRL_EXT);
392 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
393 extcnf & ~E1000_CTRL_EXT_DRV_LOAD);
394 break;
b55ccb35
JK		 395 default:
396 break;
397 }
398}
399
400/**
401 * e1000_get_hw_control - get control of the h/w from f/w
402 * @adapter: address of board private structure
403 *
404 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
76c224bc
AK		 405 * For ASF and Pass Through versions of f/w this means that
406 * the driver is loaded. For AMT version (only with 82573)
b55ccb35 407 * of the f/w this means that the netowrk i/f is open.
76c224bc 408 *
b55ccb35
JK		 409 **/
410
e619d523 411static void
b55ccb35
JK		 412e1000_get_hw_control(struct e1000_adapter *adapter)
413{
414 uint32_t ctrl_ext;
415 uint32_t swsm;
cd94dd0b 416 uint32_t extcnf;
b55ccb35
JK		 417 /* Let firmware know the driver has taken over */
418 switch (adapter->hw.mac_type) {
419 case e1000_82571:
420 case e1000_82572:
4cc15f54 421 case e1000_80003es2lan:
b55ccb35
JK		 422 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
423 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
424 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
425 break;
426 case e1000_82573:
427 swsm = E1000_READ_REG(&adapter->hw, SWSM);
428 E1000_WRITE_REG(&adapter->hw, SWSM,
429 swsm | E1000_SWSM_DRV_LOAD);
430 break;
cd94dd0b
AK		 431 case e1000_ich8lan:
432 extcnf = E1000_READ_REG(&adapter->hw, EXTCNF_CTRL);
433 E1000_WRITE_REG(&adapter->hw, EXTCNF_CTRL,
434 extcnf | E1000_EXTCNF_CTRL_SWFLAG);
435 break;
b55ccb35
JK		 436 default:
437 break;
438 }
439}
440
1da177e4
LT		 441int
442e1000_up(struct e1000_adapter *adapter)
443{
444 struct net_device *netdev = adapter->netdev;
2db10a08 445 int i;
1da177e4
LT		 446
447 /* hardware has been reset, we need to reload some things */
448
1da177e4
LT		 449 e1000_set_multi(netdev);
450
451 e1000_restore_vlan(adapter);
452
453 e1000_configure_tx(adapter);
454 e1000_setup_rctl(adapter);
455 e1000_configure_rx(adapter);
72d64a43
JK		 456 /* call E1000_DESC_UNUSED which always leaves
457 * at least 1 descriptor unused to make sure
458 * next_to_use != next_to_clean */
f56799ea 459 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 460 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 461 adapter->alloc_rx_buf(adapter, ring,
462 E1000_DESC_UNUSED(ring));
f56799ea 463 }
1da177e4 464
7bfa4816
JK		 465 adapter->tx_queue_len = netdev->tx_queue_len;
466
1da177e4 467 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 468
469#ifdef CONFIG_E1000_NAPI
470 netif_poll_enable(netdev);
471#endif
5de55624
MC		 472 e1000_irq_enable(adapter);
473
1da177e4
LT		 474 return 0;
475}
476
79f05bf0
AK		 477/**
478 * e1000_power_up_phy - restore link in case the phy was powered down
479 * @adapter: address of board private structure
480 *
481 * The phy may be powered down to save power and turn off link when the
482 * driver is unloaded and wake on lan is not enabled (among others)
483 * *** this routine MUST be followed by a call to e1000_reset ***
484 *
485 **/
486
d658266e 487void e1000_power_up_phy(struct e1000_adapter *adapter)
79f05bf0
AK		 488{
489 uint16_t mii_reg = 0;
490
491 /* Just clear the power down bit to wake the phy back up */
492 if (adapter->hw.media_type == e1000_media_type_copper) {
493 /* according to the manual, the phy will retain its
494 * settings across a power-down/up cycle */
495 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
496 mii_reg &= ~MII_CR_POWER_DOWN;
497 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
498 }
499}
500
501static void e1000_power_down_phy(struct e1000_adapter *adapter)
502{
503 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
504 e1000_check_mng_mode(&adapter->hw);
505 /* Power down the PHY so no link is implied when interface is down
506 * The PHY cannot be powered down if any of the following is TRUE
507 * (a) WoL is enabled
508 * (b) AMT is active
509 * (c) SoL/IDER session is active */
510 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 511 adapter->hw.mac_type != e1000_ich8lan &&
79f05bf0
AK		 512 adapter->hw.media_type == e1000_media_type_copper &&
513 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
514 !mng_mode_enabled &&
515 !e1000_check_phy_reset_block(&adapter->hw)) {
516 uint16_t mii_reg = 0;
517 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
518 mii_reg |= MII_CR_POWER_DOWN;
519 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
520 mdelay(1);
521 }
522}
523
1da177e4
LT		 524void
525e1000_down(struct e1000_adapter *adapter)
526{
527 struct net_device *netdev = adapter->netdev;
528
529 e1000_irq_disable(adapter);
c1605eb3 530
1da177e4
LT		 531 del_timer_sync(&adapter->tx_fifo_stall_timer);
532 del_timer_sync(&adapter->watchdog_timer);
533 del_timer_sync(&adapter->phy_info_timer);
534
535#ifdef CONFIG_E1000_NAPI
536 netif_poll_disable(netdev);
537#endif
7bfa4816 538 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 539 adapter->link_speed = 0;
540 adapter->link_duplex = 0;
541 netif_carrier_off(netdev);
542 netif_stop_queue(netdev);
543
544 e1000_reset(adapter);
581d708e
MC		 545 e1000_clean_all_tx_rings(adapter);
546 e1000_clean_all_rx_rings(adapter);
1da177e4 547}
1da177e4 548
2db10a08
AK		 549void
550e1000_reinit_locked(struct e1000_adapter *adapter)
551{
552 WARN_ON(in_interrupt());
553 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
554 msleep(1);
555 e1000_down(adapter);
556 e1000_up(adapter);
557 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 558}
559
560void
561e1000_reset(struct e1000_adapter *adapter)
562{
2d7edb92 563 uint32_t pba, manc;
1125ecbc 564 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 565
566 /* Repartition Pba for greater than 9k mtu
567 * To take effect CTRL.RST is required.
568 */
569
2d7edb92
MC		 570 switch (adapter->hw.mac_type) {
571 case e1000_82547:
0e6ef3e0 572 case e1000_82547_rev_2:
2d7edb92
MC		 573 pba = E1000_PBA_30K;
574 break;
868d5309
MC		 575 case e1000_82571:
576 case e1000_82572:
6418ecc6 577 case e1000_80003es2lan:
868d5309
MC		 578 pba = E1000_PBA_38K;
579 break;
2d7edb92
MC		 580 case e1000_82573:
581 pba = E1000_PBA_12K;
582 break;
cd94dd0b
AK		 583 case e1000_ich8lan:
584 pba = E1000_PBA_8K;
585 break;
2d7edb92
MC		 586 default:
587 pba = E1000_PBA_48K;
588 break;
589 }
590
96838a40 591 if ((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 592 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 593 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 594
595
96838a40 596 if (adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 597 adapter->tx_fifo_head = 0;
598 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
599 adapter->tx_fifo_size =
600 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
601 atomic_set(&adapter->tx_fifo_stall, 0);
602 }
2d7edb92 603
1da177e4
LT		 604 E1000_WRITE_REG(&adapter->hw, PBA, pba);
605
606 /* flow control settings */
f11b7f85
JK		 607 /* Set the FC high water mark to 90% of the FIFO size.
608 * Required to clear last 3 LSB */
609 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
cd94dd0b
AK		 610 /* We can't use 90% on small FIFOs because the remainder
611 * would be less than 1 full frame. In this case, we size
612 * it to allow at least a full frame above the high water
613 * mark. */
614 if (pba < E1000_PBA_16K)
615 fc_high_water_mark = (pba * 1024) - 1600;
f11b7f85
JK		 616
617 adapter->hw.fc_high_water = fc_high_water_mark;
618 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 619 if (adapter->hw.mac_type == e1000_80003es2lan)
620 adapter->hw.fc_pause_time = 0xFFFF;
621 else
622 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 623 adapter->hw.fc_send_xon = 1;
624 adapter->hw.fc = adapter->hw.original_fc;
625
2d7edb92 626 /* Allow time for pending master requests to run */
1da177e4 627 e1000_reset_hw(&adapter->hw);
96838a40 628 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 629 E1000_WRITE_REG(&adapter->hw, WUC, 0);
96838a40 630 if (e1000_init_hw(&adapter->hw))
1da177e4 631 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 632 e1000_update_mng_vlan(adapter);
1da177e4
LT		 633 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
634 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
635
636 e1000_reset_adaptive(&adapter->hw);
637 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
9a53a202
AK		 638
639 if (!adapter->smart_power_down &&
640 (adapter->hw.mac_type == e1000_82571 ||
641 adapter->hw.mac_type == e1000_82572)) {
642 uint16_t phy_data = 0;
643 /* speed up time to link by disabling smart power down, ignore
644 * the return value of this function because there is nothing
645 * different we would do if it failed */
646 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
647 &phy_data);
648 phy_data &= ~IGP02E1000_PM_SPD;
649 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
650 phy_data);
651 }
652
cd94dd0b
AK		 653 if (adapter->hw.mac_type < e1000_ich8lan)
654 /* FIXME: this code is duplicate and wrong for PCI Express */
2d7edb92
MC		 655 if (adapter->en_mng_pt) {
656 manc = E1000_READ_REG(&adapter->hw, MANC);
657 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
658 E1000_WRITE_REG(&adapter->hw, MANC, manc);
659 }
1da177e4
LT		 660}
661
662/**
663 * e1000_probe - Device Initialization Routine
664 * @pdev: PCI device information struct
665 * @ent: entry in e1000_pci_tbl
666 *
667 * Returns 0 on success, negative on failure
668 *
669 * e1000_probe initializes an adapter identified by a pci_dev structure.
670 * The OS initialization, configuring of the adapter private structure,
671 * and a hardware reset occur.
672 **/
673
674static int __devinit
675e1000_probe(struct pci_dev *pdev,
676 const struct pci_device_id *ent)
677{
678 struct net_device *netdev;
679 struct e1000_adapter *adapter;
2d7edb92 680 unsigned long mmio_start, mmio_len;
cd94dd0b 681 unsigned long flash_start, flash_len;
2d7edb92 682
1da177e4 683 static int cards_found = 0;
84916829 684 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */
2d7edb92 685 int i, err, pci_using_dac;
1da177e4
LT		 686 uint16_t eeprom_data;
687 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 688 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 689 return err;
690
cd94dd0b
AK		 691 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
692 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 693 pci_using_dac = 1;
694 } else {
cd94dd0b
AK		 695 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
696 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4
LT		 697 E1000_ERR("No usable DMA configuration, aborting\n");
698 return err;
699 }
700 pci_using_dac = 0;
701 }
702
96838a40 703 if ((err = pci_request_regions(pdev, e1000_driver_name)))
1da177e4
LT		 704 return err;
705
706 pci_set_master(pdev);
707
708 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
96838a40 709 if (!netdev) {
1da177e4
LT		 710 err = -ENOMEM;
711 goto err_alloc_etherdev;
712 }
713
714 SET_MODULE_OWNER(netdev);
715 SET_NETDEV_DEV(netdev, &pdev->dev);
716
717 pci_set_drvdata(pdev, netdev);
60490fe0 718 adapter = netdev_priv(netdev);
1da177e4
LT		 719 adapter->netdev = netdev;
720 adapter->pdev = pdev;
721 adapter->hw.back = adapter;
722 adapter->msg_enable = (1 << debug) - 1;
723
724 mmio_start = pci_resource_start(pdev, BAR_0);
725 mmio_len = pci_resource_len(pdev, BAR_0);
726
727 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
96838a40 728 if (!adapter->hw.hw_addr) {
1da177e4
LT		 729 err = -EIO;
730 goto err_ioremap;
731 }
732
96838a40
JB		 733 for (i = BAR_1; i <= BAR_5; i++) {
734 if (pci_resource_len(pdev, i) == 0)
1da177e4 735 continue;
96838a40 736 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 737 adapter->hw.io_base = pci_resource_start(pdev, i);
738 break;
739 }
740 }
741
742 netdev->open = &e1000_open;
743 netdev->stop = &e1000_close;
744 netdev->hard_start_xmit = &e1000_xmit_frame;
745 netdev->get_stats = &e1000_get_stats;
746 netdev->set_multicast_list = &e1000_set_multi;
747 netdev->set_mac_address = &e1000_set_mac;
748 netdev->change_mtu = &e1000_change_mtu;
749 netdev->do_ioctl = &e1000_ioctl;
750 e1000_set_ethtool_ops(netdev);
751 netdev->tx_timeout = &e1000_tx_timeout;
752 netdev->watchdog_timeo = 5 * HZ;
753#ifdef CONFIG_E1000_NAPI
754 netdev->poll = &e1000_clean;
755 netdev->weight = 64;
756#endif
757 netdev->vlan_rx_register = e1000_vlan_rx_register;
758 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
759 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
760#ifdef CONFIG_NET_POLL_CONTROLLER
761 netdev->poll_controller = e1000_netpoll;
762#endif
763 strcpy(netdev->name, pci_name(pdev));
764
765 netdev->mem_start = mmio_start;
766 netdev->mem_end = mmio_start + mmio_len;
767 netdev->base_addr = adapter->hw.io_base;
768
769 adapter->bd_number = cards_found;
770
771 /* setup the private structure */
772
96838a40 773 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 774 goto err_sw_init;
775
cd94dd0b
AK		 776 /* Flash BAR mapping must happen after e1000_sw_init
777 * because it depends on mac_type */
778 if ((adapter->hw.mac_type == e1000_ich8lan) &&
779 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
780 flash_start = pci_resource_start(pdev, 1);
781 flash_len = pci_resource_len(pdev, 1);
782 adapter->hw.flash_address = ioremap(flash_start, flash_len);
783 if (!adapter->hw.flash_address) {
784 err = -EIO;
785 goto err_flashmap;
786 }
787 }
788
96838a40 789 if ((err = e1000_check_phy_reset_block(&adapter->hw)))
2d7edb92
MC		 790 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
791
84916829 792 /* if ksp3, indicate if it's port a being setup */
76c224bc
AK		 793 if (pdev->device == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 &&
794 e1000_ksp3_port_a == 0)
84916829
JK		 795 adapter->ksp3_port_a = 1;
796 e1000_ksp3_port_a++;
797 /* Reset for multiple KP3 adapters */
798 if (e1000_ksp3_port_a == 4)
799 e1000_ksp3_port_a = 0;
800
96838a40 801 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 802 netdev->features = NETIF_F_SG |
803 NETIF_F_HW_CSUM |
804 NETIF_F_HW_VLAN_TX |
805 NETIF_F_HW_VLAN_RX |
806 NETIF_F_HW_VLAN_FILTER;
cd94dd0b
AK		 807 if (adapter->hw.mac_type == e1000_ich8lan)
808 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
1da177e4
LT		 809 }
810
811#ifdef NETIF_F_TSO
96838a40 812 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 813 (adapter->hw.mac_type != e1000_82547))
814 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 815
816#ifdef NETIF_F_TSO_IPV6
96838a40 817 if (adapter->hw.mac_type > e1000_82547_rev_2)
2d7edb92
MC		 818 netdev->features |= NETIF_F_TSO_IPV6;
819#endif
1da177e4 820#endif
96838a40 821 if (pci_using_dac)
1da177e4
LT		 822 netdev->features |= NETIF_F_HIGHDMA;
823
76c224bc
AK		 824 netdev->features |= NETIF_F_LLTX;
825
2d7edb92
MC		 826 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
827
cd94dd0b
AK		 828 /* initialize eeprom parameters */
829
830 if (e1000_init_eeprom_params(&adapter->hw)) {
831 E1000_ERR("EEPROM initialization failed\n");
832 return -EIO;
833 }
834
96838a40 835 /* before reading the EEPROM, reset the controller to
1da177e4 836 * put the device in a known good starting state */
96838a40 837
1da177e4
LT		 838 e1000_reset_hw(&adapter->hw);
839
840 /* make sure the EEPROM is good */
841
96838a40 842 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4
LT		 843 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
844 err = -EIO;
845 goto err_eeprom;
846 }
847
848 /* copy the MAC address out of the EEPROM */
849
96838a40 850 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 851 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
852 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 853 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 854
96838a40 855 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 856 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
857 err = -EIO;
858 goto err_eeprom;
859 }
860
861 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
862
863 e1000_get_bus_info(&adapter->hw);
864
865 init_timer(&adapter->tx_fifo_stall_timer);
866 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
867 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
868
869 init_timer(&adapter->watchdog_timer);
870 adapter->watchdog_timer.function = &e1000_watchdog;
871 adapter->watchdog_timer.data = (unsigned long) adapter;
872
1da177e4
LT		 873 init_timer(&adapter->phy_info_timer);
874 adapter->phy_info_timer.function = &e1000_update_phy_info;
875 adapter->phy_info_timer.data = (unsigned long) adapter;
876
87041639
JK		 877 INIT_WORK(&adapter->reset_task,
878 (void (*)(void *))e1000_reset_task, netdev);
1da177e4
LT		 879
880 /* we're going to reset, so assume we have no link for now */
881
882 netif_carrier_off(netdev);
883 netif_stop_queue(netdev);
884
885 e1000_check_options(adapter);
886
887 /* Initial Wake on LAN setting
888 * If APM wake is enabled in the EEPROM,
889 * enable the ACPI Magic Packet filter
890 */
891
96838a40 892 switch (adapter->hw.mac_type) {
1da177e4
LT		 893 case e1000_82542_rev2_0:
894 case e1000_82542_rev2_1:
895 case e1000_82543:
896 break;
897 case e1000_82544:
898 e1000_read_eeprom(&adapter->hw,
899 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
900 eeprom_apme_mask = E1000_EEPROM_82544_APM;
901 break;
cd94dd0b
AK		 902 case e1000_ich8lan:
903 e1000_read_eeprom(&adapter->hw,
904 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
905 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
906 break;
1da177e4
LT		 907 case e1000_82546:
908 case e1000_82546_rev_3:
fd803241 909 case e1000_82571:
6418ecc6 910 case e1000_80003es2lan:
96838a40 911 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 912 e1000_read_eeprom(&adapter->hw,
913 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
914 break;
915 }
916 /* Fall Through */
917 default:
918 e1000_read_eeprom(&adapter->hw,
919 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
920 break;
921 }
96838a40 922 if (eeprom_data & eeprom_apme_mask)
1da177e4
LT		 923 adapter->wol |= E1000_WUFC_MAG;
924
fb3d47d4
JK		 925 /* print bus type/speed/width info */
926 {
927 struct e1000_hw *hw = &adapter->hw;
928 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
929 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
930 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
931 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
932 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
933 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
934 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
935 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
936 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
937 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
938 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
939 "32-bit"));
940 }
941
942 for (i = 0; i < 6; i++)
943 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
944
1da177e4
LT		 945 /* reset the hardware with the new settings */
946 e1000_reset(adapter);
947
b55ccb35
JK		 948 /* If the controller is 82573 and f/w is AMT, do not set
949 * DRV_LOAD until the interface is up. For all other cases,
950 * let the f/w know that the h/w is now under the control
951 * of the driver. */
952 if (adapter->hw.mac_type != e1000_82573 ||
953 !e1000_check_mng_mode(&adapter->hw))
954 e1000_get_hw_control(adapter);
2d7edb92 955
1da177e4 956 strcpy(netdev->name, "eth%d");
96838a40 957 if ((err = register_netdev(netdev)))
1da177e4
LT		 958 goto err_register;
959
960 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
961
962 cards_found++;
963 return 0;
964
965err_register:
cd94dd0b
AK		 966 if (adapter->hw.flash_address)
967 iounmap(adapter->hw.flash_address);
968err_flashmap:
1da177e4
LT		 969err_sw_init:
970err_eeprom:
971 iounmap(adapter->hw.hw_addr);
972err_ioremap:
973 free_netdev(netdev);
974err_alloc_etherdev:
975 pci_release_regions(pdev);
976 return err;
977}
978
979/**
980 * e1000_remove - Device Removal Routine
981 * @pdev: PCI device information struct
982 *
983 * e1000_remove is called by the PCI subsystem to alert the driver
984 * that it should release a PCI device. The could be caused by a
985 * Hot-Plug event, or because the driver is going to be removed from
986 * memory.
987 **/
988
989static void __devexit
990e1000_remove(struct pci_dev *pdev)
991{
992 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 993 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 994 uint32_t manc;
581d708e
MC		 995#ifdef CONFIG_E1000_NAPI
996 int i;
997#endif
1da177e4 998
be2b28ed
JG		 999 flush_scheduled_work();
1000
96838a40 1001 if (adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 1002 adapter->hw.mac_type != e1000_ich8lan &&
1da177e4
LT		 1003 adapter->hw.media_type == e1000_media_type_copper) {
1004 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 1005 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 1006 manc |= E1000_MANC_ARP_EN;
1007 E1000_WRITE_REG(&adapter->hw, MANC, manc);
1008 }
1009 }
1010
b55ccb35
JK		 1011 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1012 * would have already happened in close and is redundant. */
1013 e1000_release_hw_control(adapter);
2d7edb92 1014
1da177e4 1015 unregister_netdev(netdev);
581d708e 1016#ifdef CONFIG_E1000_NAPI
f56799ea 1017 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 1018 dev_put(&adapter->polling_netdev[i]);
581d708e 1019#endif
1da177e4 1020
96838a40 1021 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 1022 e1000_phy_hw_reset(&adapter->hw);
1da177e4 1023
24025e4e
MC		 1024 kfree(adapter->tx_ring);
1025 kfree(adapter->rx_ring);
1026#ifdef CONFIG_E1000_NAPI
1027 kfree(adapter->polling_netdev);
1028#endif
1029
1da177e4 1030 iounmap(adapter->hw.hw_addr);
cd94dd0b
AK		 1031 if (adapter->hw.flash_address)
1032 iounmap(adapter->hw.flash_address);
1da177e4
LT		 1033 pci_release_regions(pdev);
1034
1035 free_netdev(netdev);
1036
1037 pci_disable_device(pdev);
1038}
1039
1040/**
1041 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
1042 * @adapter: board private structure to initialize
1043 *
1044 * e1000_sw_init initializes the Adapter private data structure.
1045 * Fields are initialized based on PCI device information and
1046 * OS network device settings (MTU size).
1047 **/
1048
1049static int __devinit
1050e1000_sw_init(struct e1000_adapter *adapter)
1051{
1052 struct e1000_hw *hw = &adapter->hw;
1053 struct net_device *netdev = adapter->netdev;
1054 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 1055#ifdef CONFIG_E1000_NAPI
1056 int i;
1057#endif
1da177e4
LT		 1058
1059 /* PCI config space info */
1060
1061 hw->vendor_id = pdev->vendor;
1062 hw->device_id = pdev->device;
1063 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1064 hw->subsystem_id = pdev->subsystem_device;
1065
1066 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
1067
1068 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
1069
eb0f8054 1070 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9e2feace 1071 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 1072 hw->max_frame_size = netdev->mtu +
1073 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1074 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
1075
1076 /* identify the MAC */
1077
96838a40 1078 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 1079 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
1080 return -EIO;
1081 }
1082
96838a40 1083 switch (hw->mac_type) {
1da177e4
LT		 1084 default:
1085 break;
1086 case e1000_82541:
1087 case e1000_82547:
1088 case e1000_82541_rev_2:
1089 case e1000_82547_rev_2:
1090 hw->phy_init_script = 1;
1091 break;
1092 }
1093
1094 e1000_set_media_type(hw);
1095
1096 hw->wait_autoneg_complete = FALSE;
1097 hw->tbi_compatibility_en = TRUE;
1098 hw->adaptive_ifs = TRUE;
1099
1100 /* Copper options */
1101
96838a40 1102 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1103 hw->mdix = AUTO_ALL_MODES;
1104 hw->disable_polarity_correction = FALSE;
1105 hw->master_slave = E1000_MASTER_SLAVE;
1106 }
1107
f56799ea
JK		 1108 adapter->num_tx_queues = 1;
1109 adapter->num_rx_queues = 1;
581d708e
MC		 1110
1111 if (e1000_alloc_queues(adapter)) {
1112 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1113 return -ENOMEM;
1114 }
1115
1116#ifdef CONFIG_E1000_NAPI
f56799ea 1117 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1118 adapter->polling_netdev[i].priv = adapter;
1119 adapter->polling_netdev[i].poll = &e1000_clean;
1120 adapter->polling_netdev[i].weight = 64;
1121 dev_hold(&adapter->polling_netdev[i]);
1122 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1123 }
7bfa4816 1124 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1125#endif
1126
1da177e4
LT		 1127 atomic_set(&adapter->irq_sem, 1);
1128 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1129
1130 return 0;
1131}
1132
581d708e
MC		 1133/**
1134 * e1000_alloc_queues - Allocate memory for all rings
1135 * @adapter: board private structure to initialize
1136 *
1137 * We allocate one ring per queue at run-time since we don't know the
1138 * number of queues at compile-time. The polling_netdev array is
1139 * intended for Multiqueue, but should work fine with a single queue.
1140 **/
1141
1142static int __devinit
1143e1000_alloc_queues(struct e1000_adapter *adapter)
1144{
1145 int size;
1146
f56799ea 1147 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1148 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1149 if (!adapter->tx_ring)
1150 return -ENOMEM;
1151 memset(adapter->tx_ring, 0, size);
1152
f56799ea 1153 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1154 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1155 if (!adapter->rx_ring) {
1156 kfree(adapter->tx_ring);
1157 return -ENOMEM;
1158 }
1159 memset(adapter->rx_ring, 0, size);
1160
1161#ifdef CONFIG_E1000_NAPI
f56799ea 1162 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1163 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1164 if (!adapter->polling_netdev) {
1165 kfree(adapter->tx_ring);
1166 kfree(adapter->rx_ring);
1167 return -ENOMEM;
1168 }
1169 memset(adapter->polling_netdev, 0, size);
1170#endif
1171
1172 return E1000_SUCCESS;
1173}
1174
1da177e4
LT		 1175/**
1176 * e1000_open - Called when a network interface is made active
1177 * @netdev: network interface device structure
1178 *
1179 * Returns 0 on success, negative value on failure
1180 *
1181 * The open entry point is called when a network interface is made
1182 * active by the system (IFF_UP). At this point all resources needed
1183 * for transmit and receive operations are allocated, the interrupt
1184 * handler is registered with the OS, the watchdog timer is started,
1185 * and the stack is notified that the interface is ready.
1186 **/
1187
1188static int
1189e1000_open(struct net_device *netdev)
1190{
60490fe0 1191 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1192 int err;
1193
2db10a08
AK		 1194 /* disallow open during test */
1195 if (test_bit(__E1000_DRIVER_TESTING, &adapter->flags))
1196 return -EBUSY;
1197
1da177e4
LT		 1198 /* allocate transmit descriptors */
1199
581d708e 1200 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1201 goto err_setup_tx;
1202
1203 /* allocate receive descriptors */
1204
581d708e 1205 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1206 goto err_setup_rx;
1207
2db10a08
AK		 1208 err = e1000_request_irq(adapter);
1209 if (err)
401a552b 1210 goto err_req_irq;
2db10a08 1211
79f05bf0
AK		 1212 e1000_power_up_phy(adapter);
1213
96838a40 1214 if ((err = e1000_up(adapter)))
1da177e4 1215 goto err_up;
2d7edb92 1216 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1217 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1218 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1219 e1000_update_mng_vlan(adapter);
1220 }
1da177e4 1221
b55ccb35
JK		 1222 /* If AMT is enabled, let the firmware know that the network
1223 * interface is now open */
1224 if (adapter->hw.mac_type == e1000_82573 &&
1225 e1000_check_mng_mode(&adapter->hw))
1226 e1000_get_hw_control(adapter);
1227
1da177e4
LT		 1228 return E1000_SUCCESS;
1229
1230err_up:
401a552b
VA		 1231 e1000_power_down_phy(adapter);
1232 e1000_free_irq(adapter);
1233err_req_irq:
581d708e 1234 e1000_free_all_rx_resources(adapter);
1da177e4 1235err_setup_rx:
581d708e 1236 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1237err_setup_tx:
1238 e1000_reset(adapter);
1239
1240 return err;
1241}
1242
1243/**
1244 * e1000_close - Disables a network interface
1245 * @netdev: network interface device structure
1246 *
1247 * Returns 0, this is not allowed to fail
1248 *
1249 * The close entry point is called when an interface is de-activated
1250 * by the OS. The hardware is still under the drivers control, but
1251 * needs to be disabled. A global MAC reset is issued to stop the
1252 * hardware, and all transmit and receive resources are freed.
1253 **/
1254
1255static int
1256e1000_close(struct net_device *netdev)
1257{
60490fe0 1258 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 1259
2db10a08 1260 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 1261 e1000_down(adapter);
79f05bf0 1262 e1000_power_down_phy(adapter);
2db10a08 1263 e1000_free_irq(adapter);
1da177e4 1264
581d708e
MC		 1265 e1000_free_all_tx_resources(adapter);
1266 e1000_free_all_rx_resources(adapter);
1da177e4 1267
96838a40 1268 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1269 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1270 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1271 }
b55ccb35
JK		 1272
1273 /* If AMT is enabled, let the firmware know that the network
1274 * interface is now closed */
1275 if (adapter->hw.mac_type == e1000_82573 &&
1276 e1000_check_mng_mode(&adapter->hw))
1277 e1000_release_hw_control(adapter);
1278
1da177e4
LT		 1279 return 0;
1280}
1281
1282/**
1283 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1284 * @adapter: address of board private structure
2d7edb92
MC		 1285 * @start: address of beginning of memory
1286 * @len: length of memory
1da177e4 1287 **/
e619d523 1288static boolean_t
1da177e4
LT		 1289e1000_check_64k_bound(struct e1000_adapter *adapter,
1290 void *start, unsigned long len)
1291{
1292 unsigned long begin = (unsigned long) start;
1293 unsigned long end = begin + len;
1294
2648345f
MC		 1295 /* First rev 82545 and 82546 need to not allow any memory
1296 * write location to cross 64k boundary due to errata 23 */
1da177e4 1297 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1298 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1299 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1300 }
1301
1302 return TRUE;
1303}
1304
1305/**
1306 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1307 * @adapter: board private structure
581d708e 1308 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1309 *
1310 * Return 0 on success, negative on failure
1311 **/
1312
3ad2cc67 1313static int
581d708e
MC		 1314e1000_setup_tx_resources(struct e1000_adapter *adapter,
1315 struct e1000_tx_ring *txdr)
1da177e4 1316{
1da177e4
LT		 1317 struct pci_dev *pdev = adapter->pdev;
1318 int size;
1319
1320 size = sizeof(struct e1000_buffer) * txdr->count;
cd94dd0b 1321 txdr->buffer_info = vmalloc(size);
96838a40 1322 if (!txdr->buffer_info) {
2648345f
MC		 1323 DPRINTK(PROBE, ERR,
1324 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1325 return -ENOMEM;
1326 }
1327 memset(txdr->buffer_info, 0, size);
1328
1329 /* round up to nearest 4K */
1330
1331 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1332 E1000_ROUNDUP(txdr->size, 4096);
1333
1334 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1335 if (!txdr->desc) {
1da177e4 1336setup_tx_desc_die:
1da177e4 1337 vfree(txdr->buffer_info);
2648345f
MC		 1338 DPRINTK(PROBE, ERR,
1339 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1340 return -ENOMEM;
1341 }
1342
2648345f 1343 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1344 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1345 void *olddesc = txdr->desc;
1346 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1347 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1348 "at %p\n", txdr->size, txdr->desc);
1349 /* Try again, without freeing the previous */
1da177e4 1350 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1351 /* Failed allocation, critical failure */
96838a40 1352 if (!txdr->desc) {
1da177e4
LT		 1353 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1354 goto setup_tx_desc_die;
1355 }
1356
1357 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1358 /* give up */
2648345f
MC		 1359 pci_free_consistent(pdev, txdr->size, txdr->desc,
1360 txdr->dma);
1da177e4
LT		 1361 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1362 DPRINTK(PROBE, ERR,
2648345f
MC		 1363 "Unable to allocate aligned memory "
1364 "for the transmit descriptor ring\n");
1da177e4
LT		 1365 vfree(txdr->buffer_info);
1366 return -ENOMEM;
1367 } else {
2648345f 1368 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1369 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1370 }
1371 }
1372 memset(txdr->desc, 0, txdr->size);
1373
1374 txdr->next_to_use = 0;
1375 txdr->next_to_clean = 0;
2ae76d98 1376 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1377
1378 return 0;
1379}
1380
581d708e
MC		 1381/**
1382 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1383 * (Descriptors) for all queues
1384 * @adapter: board private structure
1385 *
1386 * If this function returns with an error, then it's possible one or
1387 * more of the rings is populated (while the rest are not). It is the
1388 * callers duty to clean those orphaned rings.
1389 *
1390 * Return 0 on success, negative on failure
1391 **/
1392
1393int
1394e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1395{
1396 int i, err = 0;
1397
f56799ea 1398 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1399 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1400 if (err) {
1401 DPRINTK(PROBE, ERR,
1402 "Allocation for Tx Queue %u failed\n", i);
1403 break;
1404 }
1405 }
1406
1407 return err;
1408}
1409
1da177e4
LT		 1410/**
1411 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1412 * @adapter: board private structure
1413 *
1414 * Configure the Tx unit of the MAC after a reset.
1415 **/
1416
1417static void
1418e1000_configure_tx(struct e1000_adapter *adapter)
1419{
581d708e
MC		 1420 uint64_t tdba;
1421 struct e1000_hw *hw = &adapter->hw;
1422 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1423 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1424
1425 /* Setup the HW Tx Head and Tail descriptor pointers */
1426
f56799ea 1427 switch (adapter->num_tx_queues) {
24025e4e
MC		 1428 case 1:
1429 default:
581d708e
MC		 1430 tdba = adapter->tx_ring[0].dma;
1431 tdlen = adapter->tx_ring[0].count *
1432 sizeof(struct e1000_tx_desc);
581d708e 1433 E1000_WRITE_REG(hw, TDLEN, tdlen);
4ca213a6
AK		 1434 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1435 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
581d708e 1436 E1000_WRITE_REG(hw, TDT, 0);
4ca213a6 1437 E1000_WRITE_REG(hw, TDH, 0);
581d708e
MC		 1438 adapter->tx_ring[0].tdh = E1000_TDH;
1439 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1440 break;
1441 }
1da177e4
LT		 1442
1443 /* Set the default values for the Tx Inter Packet Gap timer */
1444
0fadb059
JK		 1445 if (hw->media_type == e1000_media_type_fiber ||
1446 hw->media_type == e1000_media_type_internal_serdes)
1447 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1448 else
1449 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1450
581d708e 1451 switch (hw->mac_type) {
1da177e4
LT		 1452 case e1000_82542_rev2_0:
1453 case e1000_82542_rev2_1:
1454 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1455 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1456 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1457 break;
87041639
JK		 1458 case e1000_80003es2lan:
1459 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1460 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1461 break;
1da177e4 1462 default:
0fadb059
JK		 1463 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1464 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1465 break;
1da177e4 1466 }
0fadb059
JK		 1467 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1468 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1469 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1470
1471 /* Set the Tx Interrupt Delay register */
1472
581d708e
MC		 1473 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1474 if (hw->mac_type >= e1000_82540)
1475 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1476
1477 /* Program the Transmit Control Register */
1478
581d708e 1479 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1480
1481 tctl &= ~E1000_TCTL_CT;
7e6c9861 1482 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1483 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1484
7e6c9861
JK		 1485#ifdef DISABLE_MULR
1486 /* disable Multiple Reads for debugging */
1487 tctl &= ~E1000_TCTL_MULR;
1488#endif
1da177e4 1489
2ae76d98
MC		 1490 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1491 tarc = E1000_READ_REG(hw, TARC0);
1492 tarc |= ((1 << 25) | (1 << 21));
1493 E1000_WRITE_REG(hw, TARC0, tarc);
1494 tarc = E1000_READ_REG(hw, TARC1);
1495 tarc |= (1 << 25);
1496 if (tctl & E1000_TCTL_MULR)
1497 tarc &= ~(1 << 28);
1498 else
1499 tarc |= (1 << 28);
1500 E1000_WRITE_REG(hw, TARC1, tarc);
87041639
JK		 1501 } else if (hw->mac_type == e1000_80003es2lan) {
1502 tarc = E1000_READ_REG(hw, TARC0);
1503 tarc |= 1;
87041639
JK		 1504 E1000_WRITE_REG(hw, TARC0, tarc);
1505 tarc = E1000_READ_REG(hw, TARC1);
1506 tarc |= 1;
1507 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1508 }
1509
581d708e 1510 e1000_config_collision_dist(hw);
1da177e4
LT		 1511
1512 /* Setup Transmit Descriptor Settings for eop descriptor */
1513 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1514 E1000_TXD_CMD_IFCS;
1515
581d708e 1516 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1517 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1518 else
1519 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1520
1521 /* Cache if we're 82544 running in PCI-X because we'll
1522 * need this to apply a workaround later in the send path. */
581d708e
MC		 1523 if (hw->mac_type == e1000_82544 &&
1524 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1525 adapter->pcix_82544 = 1;
7e6c9861
JK		 1526
1527 E1000_WRITE_REG(hw, TCTL, tctl);
1528
1da177e4
LT		 1529}
1530
1531/**
1532 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1533 * @adapter: board private structure
581d708e 1534 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1535 *
1536 * Returns 0 on success, negative on failure
1537 **/
1538
3ad2cc67 1539static int
581d708e
MC		 1540e1000_setup_rx_resources(struct e1000_adapter *adapter,
1541 struct e1000_rx_ring *rxdr)
1da177e4 1542{
1da177e4 1543 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1544 int size, desc_len;
1da177e4
LT		 1545
1546 size = sizeof(struct e1000_buffer) * rxdr->count;
cd94dd0b 1547 rxdr->buffer_info = vmalloc(size);
581d708e 1548 if (!rxdr->buffer_info) {
2648345f
MC		 1549 DPRINTK(PROBE, ERR,
1550 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1551 return -ENOMEM;
1552 }
1553 memset(rxdr->buffer_info, 0, size);
1554
2d7edb92
MC		 1555 size = sizeof(struct e1000_ps_page) * rxdr->count;
1556 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
96838a40 1557 if (!rxdr->ps_page) {
2d7edb92
MC		 1558 vfree(rxdr->buffer_info);
1559 DPRINTK(PROBE, ERR,
1560 "Unable to allocate memory for the receive descriptor ring\n");
1561 return -ENOMEM;
1562 }
1563 memset(rxdr->ps_page, 0, size);
1564
1565 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1566 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
96838a40 1567 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1568 vfree(rxdr->buffer_info);
1569 kfree(rxdr->ps_page);
1570 DPRINTK(PROBE, ERR,
1571 "Unable to allocate memory for the receive descriptor ring\n");
1572 return -ENOMEM;
1573 }
1574 memset(rxdr->ps_page_dma, 0, size);
1575
96838a40 1576 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1577 desc_len = sizeof(struct e1000_rx_desc);
1578 else
1579 desc_len = sizeof(union e1000_rx_desc_packet_split);
1580
1da177e4
LT		 1581 /* Round up to nearest 4K */
1582
2d7edb92 1583 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1584 E1000_ROUNDUP(rxdr->size, 4096);
1585
1586 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1587
581d708e
MC		 1588 if (!rxdr->desc) {
1589 DPRINTK(PROBE, ERR,
1590 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1591setup_rx_desc_die:
1da177e4 1592 vfree(rxdr->buffer_info);
2d7edb92
MC		 1593 kfree(rxdr->ps_page);
1594 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1595 return -ENOMEM;
1596 }
1597
2648345f 1598 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1599 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1600 void *olddesc = rxdr->desc;
1601 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1602 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1603 "at %p\n", rxdr->size, rxdr->desc);
1604 /* Try again, without freeing the previous */
1da177e4 1605 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1606 /* Failed allocation, critical failure */
581d708e 1607 if (!rxdr->desc) {
1da177e4 1608 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1609 DPRINTK(PROBE, ERR,
1610 "Unable to allocate memory "
1611 "for the receive descriptor ring\n");
1da177e4
LT		 1612 goto setup_rx_desc_die;
1613 }
1614
1615 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1616 /* give up */
2648345f
MC		 1617 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1618 rxdr->dma);
1da177e4 1619 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1620 DPRINTK(PROBE, ERR,
1621 "Unable to allocate aligned memory "
1622 "for the receive descriptor ring\n");
581d708e 1623 goto setup_rx_desc_die;
1da177e4 1624 } else {
2648345f 1625 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1626 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1627 }
1628 }
1629 memset(rxdr->desc, 0, rxdr->size);
1630
1631 rxdr->next_to_clean = 0;
1632 rxdr->next_to_use = 0;
1633
1634 return 0;
1635}
1636
581d708e
MC		 1637/**
1638 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1639 * (Descriptors) for all queues
1640 * @adapter: board private structure
1641 *
1642 * If this function returns with an error, then it's possible one or
1643 * more of the rings is populated (while the rest are not). It is the
1644 * callers duty to clean those orphaned rings.
1645 *
1646 * Return 0 on success, negative on failure
1647 **/
1648
1649int
1650e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1651{
1652 int i, err = 0;
1653
f56799ea 1654 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1655 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1656 if (err) {
1657 DPRINTK(PROBE, ERR,
1658 "Allocation for Rx Queue %u failed\n", i);
1659 break;
1660 }
1661 }
1662
1663 return err;
1664}
1665
1da177e4 1666/**
2648345f 1667 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1668 * @adapter: Board private structure
1669 **/
e4c811c9
MC		 1670#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1671 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1672static void
1673e1000_setup_rctl(struct e1000_adapter *adapter)
1674{
2d7edb92
MC		 1675 uint32_t rctl, rfctl;
1676 uint32_t psrctl = 0;
35ec56bb 1677#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1678 uint32_t pages = 0;
1679#endif
1da177e4
LT		 1680
1681 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1682
1683 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1684
1685 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1686 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1687 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1688
0fadb059 1689 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1690 rctl |= E1000_RCTL_SBP;
1691 else
1692 rctl &= ~E1000_RCTL_SBP;
1693
2d7edb92
MC		 1694 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1695 rctl &= ~E1000_RCTL_LPE;
1696 else
1697 rctl |= E1000_RCTL_LPE;
1698
1da177e4 1699 /* Setup buffer sizes */
9e2feace
AK		 1700 rctl &= ~E1000_RCTL_SZ_4096;
1701 rctl |= E1000_RCTL_BSEX;
1702 switch (adapter->rx_buffer_len) {
1703 case E1000_RXBUFFER_256:
1704 rctl |= E1000_RCTL_SZ_256;
1705 rctl &= ~E1000_RCTL_BSEX;
1706 break;
1707 case E1000_RXBUFFER_512:
1708 rctl |= E1000_RCTL_SZ_512;
1709 rctl &= ~E1000_RCTL_BSEX;
1710 break;
1711 case E1000_RXBUFFER_1024:
1712 rctl |= E1000_RCTL_SZ_1024;
1713 rctl &= ~E1000_RCTL_BSEX;
1714 break;
a1415ee6
JK		 1715 case E1000_RXBUFFER_2048:
1716 default:
1717 rctl |= E1000_RCTL_SZ_2048;
1718 rctl &= ~E1000_RCTL_BSEX;
1719 break;
1720 case E1000_RXBUFFER_4096:
1721 rctl |= E1000_RCTL_SZ_4096;
1722 break;
1723 case E1000_RXBUFFER_8192:
1724 rctl |= E1000_RCTL_SZ_8192;
1725 break;
1726 case E1000_RXBUFFER_16384:
1727 rctl |= E1000_RCTL_SZ_16384;
1728 break;
2d7edb92
MC		 1729 }
1730
35ec56bb 1731#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1732 /* 82571 and greater support packet-split where the protocol
1733 * header is placed in skb->data and the packet data is
1734 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1735 * In the case of a non-split, skb->data is linearly filled,
1736 * followed by the page buffers. Therefore, skb->data is
1737 * sized to hold the largest protocol header.
1738 */
e4c811c9
MC		 1739 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1740 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1741 PAGE_SIZE <= 16384)
1742 adapter->rx_ps_pages = pages;
1743 else
1744 adapter->rx_ps_pages = 0;
2d7edb92 1745#endif
e4c811c9 1746 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1747 /* Configure extra packet-split registers */
1748 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1749 rfctl |= E1000_RFCTL_EXTEN;
1750 /* disable IPv6 packet split support */
1751 rfctl |= E1000_RFCTL_IPV6_DIS;
1752 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1753
7dfee0cb 1754 rctl |= E1000_RCTL_DTYP_PS;
96838a40 1755
2d7edb92
MC		 1756 psrctl |= adapter->rx_ps_bsize0 >>
1757 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1758
1759 switch (adapter->rx_ps_pages) {
1760 case 3:
1761 psrctl |= PAGE_SIZE <<
1762 E1000_PSRCTL_BSIZE3_SHIFT;
1763 case 2:
1764 psrctl |= PAGE_SIZE <<
1765 E1000_PSRCTL_BSIZE2_SHIFT;
1766 case 1:
1767 psrctl |= PAGE_SIZE >>
1768 E1000_PSRCTL_BSIZE1_SHIFT;
1769 break;
1770 }
2d7edb92
MC		 1771
1772 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1773 }
1774
1775 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1776}
1777
1778/**
1779 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1780 * @adapter: board private structure
1781 *
1782 * Configure the Rx unit of the MAC after a reset.
1783 **/
1784
1785static void
1786e1000_configure_rx(struct e1000_adapter *adapter)
1787{
581d708e
MC		 1788 uint64_t rdba;
1789 struct e1000_hw *hw = &adapter->hw;
1790 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 1791
e4c811c9 1792 if (adapter->rx_ps_pages) {
0f15a8fa 1793 /* this is a 32 byte descriptor */
581d708e 1794 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1795 sizeof(union e1000_rx_desc_packet_split);
1796 adapter->clean_rx = e1000_clean_rx_irq_ps;
1797 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1798 } else {
581d708e
MC		 1799 rdlen = adapter->rx_ring[0].count *
1800 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1801 adapter->clean_rx = e1000_clean_rx_irq;
1802 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1803 }
1da177e4
LT		 1804
1805 /* disable receives while setting up the descriptors */
581d708e
MC		 1806 rctl = E1000_READ_REG(hw, RCTL);
1807 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1808
1809 /* set the Receive Delay Timer Register */
581d708e 1810 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1811
581d708e
MC		 1812 if (hw->mac_type >= e1000_82540) {
1813 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
96838a40 1814 if (adapter->itr > 1)
581d708e 1815 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1816 1000000000 / (adapter->itr * 256));
1817 }
1818
2ae76d98 1819 if (hw->mac_type >= e1000_82571) {
2ae76d98 1820 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1821 /* Reset delay timers after every interrupt */
6fc7a7ec 1822 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9
JK		 1823#ifdef CONFIG_E1000_NAPI
1824 /* Auto-Mask interrupts upon ICR read. */
1825 ctrl_ext |= E1000_CTRL_EXT_IAME;
1826#endif
2ae76d98 1827 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1828 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1829 E1000_WRITE_FLUSH(hw);
1830 }
1831
581d708e
MC		 1832 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1833 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1834 switch (adapter->num_rx_queues) {
24025e4e
MC		 1835 case 1:
1836 default:
581d708e 1837 rdba = adapter->rx_ring[0].dma;
581d708e 1838 E1000_WRITE_REG(hw, RDLEN, rdlen);
4ca213a6
AK		 1839 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1840 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
581d708e 1841 E1000_WRITE_REG(hw, RDT, 0);
4ca213a6 1842 E1000_WRITE_REG(hw, RDH, 0);
581d708e
MC		 1843 adapter->rx_ring[0].rdh = E1000_RDH;
1844 adapter->rx_ring[0].rdt = E1000_RDT;
1845 break;
24025e4e
MC		 1846 }
1847
1da177e4 1848 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1849 if (hw->mac_type >= e1000_82543) {
1850 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 1851 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 1852 rxcsum |= E1000_RXCSUM_TUOFL;
1853
868d5309 1854 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1855 * Must be used in conjunction with packet-split. */
96838a40
JB		 1856 if ((hw->mac_type >= e1000_82571) &&
1857 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1858 rxcsum |= E1000_RXCSUM_IPPCSE;
1859 }
1860 } else {
1861 rxcsum &= ~E1000_RXCSUM_TUOFL;
1862 /* don't need to clear IPPCSE as it defaults to 0 */
1863 }
581d708e 1864 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 1865 }
1866
1867 /* Enable Receives */
581d708e 1868 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1869}
1870
1871/**
581d708e 1872 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1873 * @adapter: board private structure
581d708e 1874 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1875 *
1876 * Free all transmit software resources
1877 **/
1878
3ad2cc67 1879static void
581d708e
MC		 1880e1000_free_tx_resources(struct e1000_adapter *adapter,
1881 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1882{
1883 struct pci_dev *pdev = adapter->pdev;
1884
581d708e 1885 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1886
581d708e
MC		 1887 vfree(tx_ring->buffer_info);
1888 tx_ring->buffer_info = NULL;
1da177e4 1889
581d708e 1890 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1891
581d708e
MC		 1892 tx_ring->desc = NULL;
1893}
1894
1895/**
1896 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1897 * @adapter: board private structure
1898 *
1899 * Free all transmit software resources
1900 **/
1901
1902void
1903e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1904{
1905 int i;
1906
f56799ea 1907 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1908 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1909}
1910
e619d523 1911static void
1da177e4
LT		 1912e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1913 struct e1000_buffer *buffer_info)
1914{
96838a40 1915 if (buffer_info->dma) {
2648345f
MC		 1916 pci_unmap_page(adapter->pdev,
1917 buffer_info->dma,
1918 buffer_info->length,
1919 PCI_DMA_TODEVICE);
1da177e4 1920 }
8241e35e 1921 if (buffer_info->skb)
1da177e4 1922 dev_kfree_skb_any(buffer_info->skb);
8241e35e 1923 memset(buffer_info, 0, sizeof(struct e1000_buffer));
1da177e4
LT		 1924}
1925
1926/**
1927 * e1000_clean_tx_ring - Free Tx Buffers
1928 * @adapter: board private structure
581d708e 1929 * @tx_ring: ring to be cleaned
1da177e4
LT		 1930 **/
1931
1932static void
581d708e
MC		 1933e1000_clean_tx_ring(struct e1000_adapter *adapter,
1934 struct e1000_tx_ring *tx_ring)
1da177e4 1935{
1da177e4
LT		 1936 struct e1000_buffer *buffer_info;
1937 unsigned long size;
1938 unsigned int i;
1939
1940 /* Free all the Tx ring sk_buffs */
1941
96838a40 1942 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 1943 buffer_info = &tx_ring->buffer_info[i];
1944 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1945 }
1946
1947 size = sizeof(struct e1000_buffer) * tx_ring->count;
1948 memset(tx_ring->buffer_info, 0, size);
1949
1950 /* Zero out the descriptor ring */
1951
1952 memset(tx_ring->desc, 0, tx_ring->size);
1953
1954 tx_ring->next_to_use = 0;
1955 tx_ring->next_to_clean = 0;
fd803241 1956 tx_ring->last_tx_tso = 0;
1da177e4 1957
581d708e
MC		 1958 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1959 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1960}
1961
1962/**
1963 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1964 * @adapter: board private structure
1965 **/
1966
1967static void
1968e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1969{
1970 int i;
1971
f56799ea 1972 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1973 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1974}
1975
1976/**
1977 * e1000_free_rx_resources - Free Rx Resources
1978 * @adapter: board private structure
581d708e 1979 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1980 *
1981 * Free all receive software resources
1982 **/
1983
3ad2cc67 1984static void
581d708e
MC		 1985e1000_free_rx_resources(struct e1000_adapter *adapter,
1986 struct e1000_rx_ring *rx_ring)
1da177e4 1987{
1da177e4
LT		 1988 struct pci_dev *pdev = adapter->pdev;
1989
581d708e 1990 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1991
1992 vfree(rx_ring->buffer_info);
1993 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1994 kfree(rx_ring->ps_page);
1995 rx_ring->ps_page = NULL;
1996 kfree(rx_ring->ps_page_dma);
1997 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1998
1999 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2000
2001 rx_ring->desc = NULL;
2002}
2003
2004/**
581d708e 2005 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2006 * @adapter: board private structure
581d708e
MC		 2007 *
2008 * Free all receive software resources
2009 **/
2010
2011void
2012e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2013{
2014 int i;
2015
f56799ea 2016 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2017 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2018}
2019
2020/**
2021 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2022 * @adapter: board private structure
2023 * @rx_ring: ring to free buffers from
1da177e4
LT		 2024 **/
2025
2026static void
581d708e
MC		 2027e1000_clean_rx_ring(struct e1000_adapter *adapter,
2028 struct e1000_rx_ring *rx_ring)
1da177e4 2029{
1da177e4 2030 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2031 struct e1000_ps_page *ps_page;
2032 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2033 struct pci_dev *pdev = adapter->pdev;
2034 unsigned long size;
2d7edb92 2035 unsigned int i, j;
1da177e4
LT		 2036
2037 /* Free all the Rx ring sk_buffs */
96838a40 2038 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2039 buffer_info = &rx_ring->buffer_info[i];
96838a40 2040 if (buffer_info->skb) {
1da177e4
LT		 2041 pci_unmap_single(pdev,
2042 buffer_info->dma,
2043 buffer_info->length,
2044 PCI_DMA_FROMDEVICE);
2045
2046 dev_kfree_skb(buffer_info->skb);
2047 buffer_info->skb = NULL;
997f5cbd
JK		 2048 }
2049 ps_page = &rx_ring->ps_page[i];
2050 ps_page_dma = &rx_ring->ps_page_dma[i];
2051 for (j = 0; j < adapter->rx_ps_pages; j++) {
2052 if (!ps_page->ps_page[j]) break;
2053 pci_unmap_page(pdev,
2054 ps_page_dma->ps_page_dma[j],
2055 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2056 ps_page_dma->ps_page_dma[j] = 0;
2057 put_page(ps_page->ps_page[j]);
2058 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2059 }
2060 }
2061
2062 size = sizeof(struct e1000_buffer) * rx_ring->count;
2063 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2064 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2065 memset(rx_ring->ps_page, 0, size);
2066 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2067 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2068
2069 /* Zero out the descriptor ring */
2070
2071 memset(rx_ring->desc, 0, rx_ring->size);
2072
2073 rx_ring->next_to_clean = 0;
2074 rx_ring->next_to_use = 0;
2075
581d708e
MC		 2076 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2077 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2078}
2079
2080/**
2081 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2082 * @adapter: board private structure
2083 **/
2084
2085static void
2086e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2087{
2088 int i;
2089
f56799ea 2090 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2091 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2092}
2093
2094/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2095 * and memory write and invalidate disabled for certain operations
2096 */
2097static void
2098e1000_enter_82542_rst(struct e1000_adapter *adapter)
2099{
2100 struct net_device *netdev = adapter->netdev;
2101 uint32_t rctl;
2102
2103 e1000_pci_clear_mwi(&adapter->hw);
2104
2105 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2106 rctl |= E1000_RCTL_RST;
2107 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2108 E1000_WRITE_FLUSH(&adapter->hw);
2109 mdelay(5);
2110
96838a40 2111 if (netif_running(netdev))
581d708e 2112 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2113}
2114
2115static void
2116e1000_leave_82542_rst(struct e1000_adapter *adapter)
2117{
2118 struct net_device *netdev = adapter->netdev;
2119 uint32_t rctl;
2120
2121 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2122 rctl &= ~E1000_RCTL_RST;
2123 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2124 E1000_WRITE_FLUSH(&adapter->hw);
2125 mdelay(5);
2126
96838a40 2127 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2128 e1000_pci_set_mwi(&adapter->hw);
2129
96838a40 2130 if (netif_running(netdev)) {
72d64a43
JK		 2131 /* No need to loop, because 82542 supports only 1 queue */
2132 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2133 e1000_configure_rx(adapter);
72d64a43 2134 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2135 }
2136}
2137
2138/**
2139 * e1000_set_mac - Change the Ethernet Address of the NIC
2140 * @netdev: network interface device structure
2141 * @p: pointer to an address structure
2142 *
2143 * Returns 0 on success, negative on failure
2144 **/
2145
2146static int
2147e1000_set_mac(struct net_device *netdev, void *p)
2148{
60490fe0 2149 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2150 struct sockaddr *addr = p;
2151
96838a40 2152 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2153 return -EADDRNOTAVAIL;
2154
2155 /* 82542 2.0 needs to be in reset to write receive address registers */
2156
96838a40 2157 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2158 e1000_enter_82542_rst(adapter);
2159
2160 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2161 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2162
2163 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2164
868d5309
MC		 2165 /* With 82571 controllers, LAA may be overwritten (with the default)
2166 * due to controller reset from the other port. */
2167 if (adapter->hw.mac_type == e1000_82571) {
2168 /* activate the work around */
2169 adapter->hw.laa_is_present = 1;
2170
96838a40
JB		 2171 /* Hold a copy of the LAA in RAR[14] This is done so that
2172 * between the time RAR[0] gets clobbered and the time it
2173 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2174 * of the RARs and no incoming packets directed to this port
96838a40 2175 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2176 * RAR[14] */
96838a40 2177 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2178 E1000_RAR_ENTRIES - 1);
2179 }
2180
96838a40 2181 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2182 e1000_leave_82542_rst(adapter);
2183
2184 return 0;
2185}
2186
2187/**
2188 * e1000_set_multi - Multicast and Promiscuous mode set
2189 * @netdev: network interface device structure
2190 *
2191 * The set_multi entry point is called whenever the multicast address
2192 * list or the network interface flags are updated. This routine is
2193 * responsible for configuring the hardware for proper multicast,
2194 * promiscuous mode, and all-multi behavior.
2195 **/
2196
2197static void
2198e1000_set_multi(struct net_device *netdev)
2199{
60490fe0 2200 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2201 struct e1000_hw *hw = &adapter->hw;
2202 struct dev_mc_list *mc_ptr;
2203 uint32_t rctl;
2204 uint32_t hash_value;
868d5309 2205 int i, rar_entries = E1000_RAR_ENTRIES;
cd94dd0b
AK		 2206 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2207 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2208 E1000_NUM_MTA_REGISTERS;
2209
2210 if (adapter->hw.mac_type == e1000_ich8lan)
2211 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
1da177e4 2212
868d5309
MC		 2213 /* reserve RAR[14] for LAA over-write work-around */
2214 if (adapter->hw.mac_type == e1000_82571)
2215 rar_entries--;
1da177e4 2216
2648345f
MC		 2217 /* Check for Promiscuous and All Multicast modes */
2218
1da177e4
LT		 2219 rctl = E1000_READ_REG(hw, RCTL);
2220
96838a40 2221 if (netdev->flags & IFF_PROMISC) {
1da177e4 2222 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2223 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2224 rctl |= E1000_RCTL_MPE;
2225 rctl &= ~E1000_RCTL_UPE;
2226 } else {
2227 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2228 }
2229
2230 E1000_WRITE_REG(hw, RCTL, rctl);
2231
2232 /* 82542 2.0 needs to be in reset to write receive address registers */
2233
96838a40 2234 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2235 e1000_enter_82542_rst(adapter);
2236
2237 /* load the first 14 multicast address into the exact filters 1-14
2238 * RAR 0 is used for the station MAC adddress
2239 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2240 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2241 */
2242 mc_ptr = netdev->mc_list;
2243
96838a40 2244 for (i = 1; i < rar_entries; i++) {
868d5309 2245 if (mc_ptr) {
1da177e4
LT		 2246 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2247 mc_ptr = mc_ptr->next;
2248 } else {
2249 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
4ca213a6 2250 E1000_WRITE_FLUSH(hw);
1da177e4 2251 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
4ca213a6 2252 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 2253 }
2254 }
2255
2256 /* clear the old settings from the multicast hash table */
2257
cd94dd0b 2258 for (i = 0; i < mta_reg_count; i++) {
1da177e4 2259 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 2260 E1000_WRITE_FLUSH(hw);
2261 }
1da177e4
LT		 2262
2263 /* load any remaining addresses into the hash table */
2264
96838a40 2265 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2266 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2267 e1000_mta_set(hw, hash_value);
2268 }
2269
96838a40 2270 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2271 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2272}
2273
2274/* Need to wait a few seconds after link up to get diagnostic information from
2275 * the phy */
2276
2277static void
2278e1000_update_phy_info(unsigned long data)
2279{
2280 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2281 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2282}
2283
2284/**
2285 * e1000_82547_tx_fifo_stall - Timer Call-back
2286 * @data: pointer to adapter cast into an unsigned long
2287 **/
2288
2289static void
2290e1000_82547_tx_fifo_stall(unsigned long data)
2291{
2292 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2293 struct net_device *netdev = adapter->netdev;
2294 uint32_t tctl;
2295
96838a40
JB		 2296 if (atomic_read(&adapter->tx_fifo_stall)) {
2297 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2298 E1000_READ_REG(&adapter->hw, TDH)) &&
2299 (E1000_READ_REG(&adapter->hw, TDFT) ==
2300 E1000_READ_REG(&adapter->hw, TDFH)) &&
2301 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2302 E1000_READ_REG(&adapter->hw, TDFHS))) {
2303 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2304 E1000_WRITE_REG(&adapter->hw, TCTL,
2305 tctl & ~E1000_TCTL_EN);
2306 E1000_WRITE_REG(&adapter->hw, TDFT,
2307 adapter->tx_head_addr);
2308 E1000_WRITE_REG(&adapter->hw, TDFH,
2309 adapter->tx_head_addr);
2310 E1000_WRITE_REG(&adapter->hw, TDFTS,
2311 adapter->tx_head_addr);
2312 E1000_WRITE_REG(&adapter->hw, TDFHS,
2313 adapter->tx_head_addr);
2314 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2315 E1000_WRITE_FLUSH(&adapter->hw);
2316
2317 adapter->tx_fifo_head = 0;
2318 atomic_set(&adapter->tx_fifo_stall, 0);
2319 netif_wake_queue(netdev);
2320 } else {
2321 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2322 }
2323 }
2324}
2325
2326/**
2327 * e1000_watchdog - Timer Call-back
2328 * @data: pointer to adapter cast into an unsigned long
2329 **/
2330static void
2331e1000_watchdog(unsigned long data)
2332{
2333 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1da177e4 2334 struct net_device *netdev = adapter->netdev;
545c67c0 2335 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2336 uint32_t link, tctl;
cd94dd0b
AK		 2337 int32_t ret_val;
2338
2339 ret_val = e1000_check_for_link(&adapter->hw);
2340 if ((ret_val == E1000_ERR_PHY) &&
2341 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2342 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2343 /* See e1000_kumeran_lock_loss_workaround() */
2344 DPRINTK(LINK, INFO,
2345 "Gigabit has been disabled, downgrading speed\n");
2346 }
2d7edb92
MC		 2347 if (adapter->hw.mac_type == e1000_82573) {
2348 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2349 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2350 e1000_update_mng_vlan(adapter);
96838a40 2351 }
1da177e4 2352
96838a40 2353 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2354 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2355 link = !adapter->hw.serdes_link_down;
2356 else
2357 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2358
96838a40
JB		 2359 if (link) {
2360 if (!netif_carrier_ok(netdev)) {
fe7fe28e 2361 boolean_t txb2b = 1;
1da177e4
LT		 2362 e1000_get_speed_and_duplex(&adapter->hw,
2363 &adapter->link_speed,
2364 &adapter->link_duplex);
2365
2366 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2367 adapter->link_speed,
2368 adapter->link_duplex == FULL_DUPLEX ?
2369 "Full Duplex" : "Half Duplex");
2370
7e6c9861
JK		 2371 /* tweak tx_queue_len according to speed/duplex
2372 * and adjust the timeout factor */
66a2b0a3
JK		 2373 netdev->tx_queue_len = adapter->tx_queue_len;
2374 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2375 switch (adapter->link_speed) {
2376 case SPEED_10:
fe7fe28e 2377 txb2b = 0;
7e6c9861
JK		 2378 netdev->tx_queue_len = 10;
2379 adapter->tx_timeout_factor = 8;
2380 break;
2381 case SPEED_100:
fe7fe28e 2382 txb2b = 0;
7e6c9861
JK		 2383 netdev->tx_queue_len = 100;
2384 /* maybe add some timeout factor ? */
2385 break;
2386 }
2387
fe7fe28e 2388 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2389 adapter->hw.mac_type == e1000_82572) &&
fe7fe28e 2390 txb2b == 0) {
7e6c9861
JK		 2391#define SPEED_MODE_BIT (1 << 21)
2392 uint32_t tarc0;
2393 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
2394 tarc0 &= ~SPEED_MODE_BIT;
2395 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2396 }
2397
2398#ifdef NETIF_F_TSO
2399 /* disable TSO for pcie and 10/100 speeds, to avoid
2400 * some hardware issues */
2401 if (!adapter->tso_force &&
2402 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2403 switch (adapter->link_speed) {
2404 case SPEED_10:
66a2b0a3 2405 case SPEED_100:
7e6c9861
JK		 2406 DPRINTK(PROBE,INFO,
2407 "10/100 speed: disabling TSO\n");
2408 netdev->features &= ~NETIF_F_TSO;
2409 break;
2410 case SPEED_1000:
2411 netdev->features |= NETIF_F_TSO;
2412 break;
2413 default:
2414 /* oops */
66a2b0a3
JK		 2415 break;
2416 }
2417 }
7e6c9861
JK		 2418#endif
2419
2420 /* enable transmits in the hardware, need to do this
2421 * after setting TARC0 */
2422 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2423 tctl |= E1000_TCTL_EN;
2424 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2425
1da177e4
LT		 2426 netif_carrier_on(netdev);
2427 netif_wake_queue(netdev);
2428 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2429 adapter->smartspeed = 0;
2430 }
2431 } else {
96838a40 2432 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2433 adapter->link_speed = 0;
2434 adapter->link_duplex = 0;
2435 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2436 netif_carrier_off(netdev);
2437 netif_stop_queue(netdev);
2438 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
87041639
JK		 2439
2440 /* 80003ES2LAN workaround--
2441 * For packet buffer work-around on link down event;
2442 * disable receives in the ISR and
2443 * reset device here in the watchdog
2444 */
8fc897b0 2445 if (adapter->hw.mac_type == e1000_80003es2lan)
87041639
JK		 2446 /* reset device */
2447 schedule_work(&adapter->reset_task);
1da177e4
LT		 2448 }
2449
2450 e1000_smartspeed(adapter);
2451 }
2452
2453 e1000_update_stats(adapter);
2454
2455 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2456 adapter->tpt_old = adapter->stats.tpt;
2457 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2458 adapter->colc_old = adapter->stats.colc;
2459
2460 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2461 adapter->gorcl_old = adapter->stats.gorcl;
2462 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2463 adapter->gotcl_old = adapter->stats.gotcl;
2464
2465 e1000_update_adaptive(&adapter->hw);
2466
f56799ea 2467 if (!netif_carrier_ok(netdev)) {
581d708e 2468 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2469 /* We've lost link, so the controller stops DMA,
2470 * but we've got queued Tx work that's never going
2471 * to get done, so reset controller to flush Tx.
2472 * (Do the reset outside of interrupt context). */
87041639
JK		 2473 adapter->tx_timeout_count++;
2474 schedule_work(&adapter->reset_task);
1da177e4
LT		 2475 }
2476 }
2477
2478 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
96838a40 2479 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1da177e4
LT		 2480 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2481 * asymmetrical Tx or Rx gets ITR=8000; everyone
2482 * else is between 2000-8000. */
2483 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
96838a40 2484 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1da177e4
LT		 2485 adapter->gotcl - adapter->gorcl :
2486 adapter->gorcl - adapter->gotcl) / 10000;
2487 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2488 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2489 }
2490
2491 /* Cause software interrupt to ensure rx ring is cleaned */
2492 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2493
2648345f 2494 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2495 adapter->detect_tx_hung = TRUE;
2496
96838a40 2497 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2498 * reset from the other port. Set the appropriate LAA in RAR[0] */
2499 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2500 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2501
1da177e4
LT		 2502 /* Reset the timer */
2503 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2504}
2505
2506#define E1000_TX_FLAGS_CSUM 0x00000001
2507#define E1000_TX_FLAGS_VLAN 0x00000002
2508#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2509#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2510#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2511#define E1000_TX_FLAGS_VLAN_SHIFT 16
2512
e619d523 2513static int
581d708e
MC		 2514e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2515 struct sk_buff *skb)
1da177e4
LT		 2516{
2517#ifdef NETIF_F_TSO
2518 struct e1000_context_desc *context_desc;
545c67c0 2519 struct e1000_buffer *buffer_info;
1da177e4
LT		 2520 unsigned int i;
2521 uint32_t cmd_length = 0;
2d7edb92 2522 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2523 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2524 int err;
2525
89114afd 2526 if (skb_is_gso(skb)) {
1da177e4
LT		 2527 if (skb_header_cloned(skb)) {
2528 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2529 if (err)
2530 return err;
2531 }
2532
2533 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
7967168c 2534 mss = skb_shinfo(skb)->gso_size;
60828236 2535 if (skb->protocol == htons(ETH_P_IP)) {
2d7edb92
MC		 2536 skb->nh.iph->tot_len = 0;
2537 skb->nh.iph->check = 0;
2538 skb->h.th->check =
2539 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2540 skb->nh.iph->daddr,
2541 0,
2542 IPPROTO_TCP,
2543 0);
2544 cmd_length = E1000_TXD_CMD_IP;
2545 ipcse = skb->h.raw - skb->data - 1;
2546#ifdef NETIF_F_TSO_IPV6
e15fdd03 2547 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2d7edb92
MC		 2548 skb->nh.ipv6h->payload_len = 0;
2549 skb->h.th->check =
2550 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2551 &skb->nh.ipv6h->daddr,
2552 0,
2553 IPPROTO_TCP,
2554 0);
2555 ipcse = 0;
2556#endif
2557 }
1da177e4
LT		 2558 ipcss = skb->nh.raw - skb->data;
2559 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2560 tucss = skb->h.raw - skb->data;
2561 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2562 tucse = 0;
2563
2564 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2565 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2566
581d708e
MC		 2567 i = tx_ring->next_to_use;
2568 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2569 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2570
2571 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2572 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2573 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2574 context_desc->upper_setup.tcp_fields.tucss = tucss;
2575 context_desc->upper_setup.tcp_fields.tucso = tucso;
2576 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2577 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2578 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2579 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2580
545c67c0
JK		 2581 buffer_info->time_stamp = jiffies;
2582
581d708e
MC		 2583 if (++i == tx_ring->count) i = 0;
2584 tx_ring->next_to_use = i;
1da177e4 2585
8241e35e 2586 return TRUE;
1da177e4
LT		 2587 }
2588#endif
2589
8241e35e 2590 return FALSE;
1da177e4
LT		 2591}
2592
e619d523 2593static boolean_t
581d708e
MC		 2594e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2595 struct sk_buff *skb)
1da177e4
LT		 2596{
2597 struct e1000_context_desc *context_desc;
545c67c0 2598 struct e1000_buffer *buffer_info;
1da177e4
LT		 2599 unsigned int i;
2600 uint8_t css;
2601
96838a40 2602 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1da177e4
LT		 2603 css = skb->h.raw - skb->data;
2604
581d708e 2605 i = tx_ring->next_to_use;
545c67c0 2606 buffer_info = &tx_ring->buffer_info[i];
581d708e 2607 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2608
2609 context_desc->upper_setup.tcp_fields.tucss = css;
2610 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2611 context_desc->upper_setup.tcp_fields.tucse = 0;
2612 context_desc->tcp_seg_setup.data = 0;
2613 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2614
545c67c0
JK		 2615 buffer_info->time_stamp = jiffies;
2616
581d708e
MC		 2617 if (unlikely(++i == tx_ring->count)) i = 0;
2618 tx_ring->next_to_use = i;
1da177e4
LT		 2619
2620 return TRUE;
2621 }
2622
2623 return FALSE;
2624}
2625
2626#define E1000_MAX_TXD_PWR 12
2627#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2628
e619d523 2629static int
581d708e
MC		 2630e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2631 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2632 unsigned int nr_frags, unsigned int mss)
1da177e4 2633{
1da177e4
LT		 2634 struct e1000_buffer *buffer_info;
2635 unsigned int len = skb->len;
2636 unsigned int offset = 0, size, count = 0, i;
2637 unsigned int f;
2638 len -= skb->data_len;
2639
2640 i = tx_ring->next_to_use;
2641
96838a40 2642 while (len) {
1da177e4
LT		 2643 buffer_info = &tx_ring->buffer_info[i];
2644 size = min(len, max_per_txd);
2645#ifdef NETIF_F_TSO
fd803241
JK		 2646 /* Workaround for Controller erratum --
2647 * descriptor for non-tso packet in a linear SKB that follows a
2648 * tso gets written back prematurely before the data is fully
0f15a8fa 2649 * DMA'd to the controller */
fd803241 2650 if (!skb->data_len && tx_ring->last_tx_tso &&
89114afd 2651 !skb_is_gso(skb)) {
fd803241
JK		 2652 tx_ring->last_tx_tso = 0;
2653 size -= 4;
2654 }
2655
1da177e4
LT		 2656 /* Workaround for premature desc write-backs
2657 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2658 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4
LT		 2659 size -= 4;
2660#endif
97338bde
MC		 2661 /* work-around for errata 10 and it applies
2662 * to all controllers in PCI-X mode
2663 * The fix is to make sure that the first descriptor of a
2664 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2665 */
96838a40 2666 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2667 (size > 2015) && count == 0))
2668 size = 2015;
96838a40 2669
1da177e4
LT		 2670 /* Workaround for potential 82544 hang in PCI-X. Avoid
2671 * terminating buffers within evenly-aligned dwords. */
96838a40 2672 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2673 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2674 size > 4))
2675 size -= 4;
2676
2677 buffer_info->length = size;
2678 buffer_info->dma =
2679 pci_map_single(adapter->pdev,
2680 skb->data + offset,
2681 size,
2682 PCI_DMA_TODEVICE);
2683 buffer_info->time_stamp = jiffies;
2684
2685 len -= size;
2686 offset += size;
2687 count++;
96838a40 2688 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2689 }
2690
96838a40 2691 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 2692 struct skb_frag_struct *frag;
2693
2694 frag = &skb_shinfo(skb)->frags[f];
2695 len = frag->size;
2696 offset = frag->page_offset;
2697
96838a40 2698 while (len) {
1da177e4
LT		 2699 buffer_info = &tx_ring->buffer_info[i];
2700 size = min(len, max_per_txd);
2701#ifdef NETIF_F_TSO
2702 /* Workaround for premature desc write-backs
2703 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2704 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4
LT		 2705 size -= 4;
2706#endif
2707 /* Workaround for potential 82544 hang in PCI-X.
2708 * Avoid terminating buffers within evenly-aligned
2709 * dwords. */
96838a40 2710 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2711 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2712 size > 4))
2713 size -= 4;
2714
2715 buffer_info->length = size;
2716 buffer_info->dma =
2717 pci_map_page(adapter->pdev,
2718 frag->page,
2719 offset,
2720 size,
2721 PCI_DMA_TODEVICE);
2722 buffer_info->time_stamp = jiffies;
2723
2724 len -= size;
2725 offset += size;
2726 count++;
96838a40 2727 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2728 }
2729 }
2730
2731 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2732 tx_ring->buffer_info[i].skb = skb;
2733 tx_ring->buffer_info[first].next_to_watch = i;
2734
2735 return count;
2736}
2737
e619d523 2738static void
581d708e
MC		 2739e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2740 int tx_flags, int count)
1da177e4 2741{
1da177e4
LT		 2742 struct e1000_tx_desc *tx_desc = NULL;
2743 struct e1000_buffer *buffer_info;
2744 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2745 unsigned int i;
2746
96838a40 2747 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 2748 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2749 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2750 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2751
96838a40 2752 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 2753 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2754 }
2755
96838a40 2756 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 2757 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2758 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2759 }
2760
96838a40 2761 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 2762 txd_lower |= E1000_TXD_CMD_VLE;
2763 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2764 }
2765
2766 i = tx_ring->next_to_use;
2767
96838a40 2768 while (count--) {
1da177e4
LT		 2769 buffer_info = &tx_ring->buffer_info[i];
2770 tx_desc = E1000_TX_DESC(*tx_ring, i);
2771 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2772 tx_desc->lower.data =
2773 cpu_to_le32(txd_lower | buffer_info->length);
2774 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 2775 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2776 }
2777
2778 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2779
2780 /* Force memory writes to complete before letting h/w
2781 * know there are new descriptors to fetch. (Only
2782 * applicable for weak-ordered memory model archs,
2783 * such as IA-64). */
2784 wmb();
2785
2786 tx_ring->next_to_use = i;
581d708e 2787 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2788}
2789
2790/**
2791 * 82547 workaround to avoid controller hang in half-duplex environment.
2792 * The workaround is to avoid queuing a large packet that would span
2793 * the internal Tx FIFO ring boundary by notifying the stack to resend
2794 * the packet at a later time. This gives the Tx FIFO an opportunity to
2795 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2796 * to the beginning of the Tx FIFO.
2797 **/
2798
2799#define E1000_FIFO_HDR 0x10
2800#define E1000_82547_PAD_LEN 0x3E0
2801
e619d523 2802static int
1da177e4
LT		 2803e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2804{
2805 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2806 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2807
2808 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2809
96838a40 2810 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 2811 goto no_fifo_stall_required;
2812
96838a40 2813 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 2814 return 1;
2815
96838a40 2816 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 2817 atomic_set(&adapter->tx_fifo_stall, 1);
2818 return 1;
2819 }
2820
2821no_fifo_stall_required:
2822 adapter->tx_fifo_head += skb_fifo_len;
96838a40 2823 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 2824 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2825 return 0;
2826}
2827
2d7edb92 2828#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 2829static int
2d7edb92
MC		 2830e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2831{
2832 struct e1000_hw *hw = &adapter->hw;
2833 uint16_t length, offset;
96838a40
JB		 2834 if (vlan_tx_tag_present(skb)) {
2835 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 2836 ( adapter->hw.mng_cookie.status &
2837 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2838 return 0;
2839 }
20a44028 2840 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 2841 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 2842 if ((htons(ETH_P_IP) == eth->h_proto)) {
2843 const struct iphdr *ip =
2d7edb92 2844 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 2845 if (IPPROTO_UDP == ip->protocol) {
2846 struct udphdr *udp =
2847 (struct udphdr *)((uint8_t *)ip +
2d7edb92 2848 (ip->ihl << 2));
96838a40 2849 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 2850 offset = (uint8_t *)udp + 8 - skb->data;
2851 length = skb->len - offset;
2852
2853 return e1000_mng_write_dhcp_info(hw,
96838a40 2854 (uint8_t *)udp + 8,
2d7edb92
MC		 2855 length);
2856 }
2857 }
2858 }
2859 }
2860 return 0;
2861}
2862
1da177e4
LT		 2863#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2864static int
2865e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2866{
60490fe0 2867 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2868 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2869 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2870 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2871 unsigned int tx_flags = 0;
2872 unsigned int len = skb->len;
2873 unsigned long flags;
2874 unsigned int nr_frags = 0;
2875 unsigned int mss = 0;
2876 int count = 0;
76c224bc 2877 int tso;
1da177e4
LT		 2878 unsigned int f;
2879 len -= skb->data_len;
2880
581d708e 2881 tx_ring = adapter->tx_ring;
24025e4e 2882
581d708e 2883 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2884 dev_kfree_skb_any(skb);
2885 return NETDEV_TX_OK;
2886 }
2887
2888#ifdef NETIF_F_TSO
7967168c 2889 mss = skb_shinfo(skb)->gso_size;
76c224bc 2890 /* The controller does a simple calculation to
1da177e4
LT		 2891 * make sure there is enough room in the FIFO before
2892 * initiating the DMA for each buffer. The calc is:
2893 * 4 = ceil(buffer len/mss). To make sure we don't
2894 * overrun the FIFO, adjust the max buffer len if mss
2895 * drops. */
96838a40 2896 if (mss) {
9a3056da 2897 uint8_t hdr_len;
1da177e4
LT		 2898 max_per_txd = min(mss << 2, max_per_txd);
2899 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 2900
9f687888 2901 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
9a3056da
JK		 2902 * points to just header, pull a few bytes of payload from
2903 * frags into skb->data */
2904 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
9f687888
JK		 2905 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
2906 switch (adapter->hw.mac_type) {
2907 unsigned int pull_size;
2908 case e1000_82571:
2909 case e1000_82572:
2910 case e1000_82573:
cd94dd0b 2911 case e1000_ich8lan:
9f687888
JK		 2912 pull_size = min((unsigned int)4, skb->data_len);
2913 if (!__pskb_pull_tail(skb, pull_size)) {
a5eafce2 2914 DPRINTK(DRV, ERR,
9f687888
JK		 2915 "__pskb_pull_tail failed.\n");
2916 dev_kfree_skb_any(skb);
749dfc70 2917 return NETDEV_TX_OK;
9f687888
JK		 2918 }
2919 len = skb->len - skb->data_len;
2920 break;
2921 default:
2922 /* do nothing */
2923 break;
d74bbd3b 2924 }
9a3056da 2925 }
1da177e4
LT		 2926 }
2927
9a3056da 2928 /* reserve a descriptor for the offload context */
96838a40 2929 if ((mss) || (skb->ip_summed == CHECKSUM_HW))
1da177e4 2930 count++;
2648345f 2931 count++;
1da177e4 2932#else
96838a40 2933 if (skb->ip_summed == CHECKSUM_HW)
1da177e4
LT		 2934 count++;
2935#endif
fd803241
JK		 2936
2937#ifdef NETIF_F_TSO
2938 /* Controller Erratum workaround */
89114afd 2939 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
fd803241
JK		 2940 count++;
2941#endif
2942
1da177e4
LT		 2943 count += TXD_USE_COUNT(len, max_txd_pwr);
2944
96838a40 2945 if (adapter->pcix_82544)
1da177e4
LT		 2946 count++;
2947
96838a40 2948 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 2949 * in PCI-X mode, so add one more descriptor to the count
2950 */
96838a40 2951 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2952 (len > 2015)))
2953 count++;
2954
1da177e4 2955 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 2956 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 2957 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2958 max_txd_pwr);
96838a40 2959 if (adapter->pcix_82544)
1da177e4
LT		 2960 count += nr_frags;
2961
0f15a8fa
JK		 2962
2963 if (adapter->hw.tx_pkt_filtering &&
2964 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 2965 e1000_transfer_dhcp_info(adapter, skb);
2966
581d708e
MC		 2967 local_irq_save(flags);
2968 if (!spin_trylock(&tx_ring->tx_lock)) {
2969 /* Collision - tell upper layer to requeue */
2970 local_irq_restore(flags);
2971 return NETDEV_TX_LOCKED;
2972 }
1da177e4
LT		 2973
2974 /* need: count + 2 desc gap to keep tail from touching
2975 * head, otherwise try next time */
581d708e 2976 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2977 netif_stop_queue(netdev);
581d708e 2978 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2979 return NETDEV_TX_BUSY;
2980 }
2981
96838a40
JB		 2982 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
2983 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4
LT		 2984 netif_stop_queue(netdev);
2985 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2986 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2987 return NETDEV_TX_BUSY;
2988 }
2989 }
2990
96838a40 2991 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 2992 tx_flags |= E1000_TX_FLAGS_VLAN;
2993 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2994 }
2995
581d708e 2996 first = tx_ring->next_to_use;
96838a40 2997
581d708e 2998 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2999 if (tso < 0) {
3000 dev_kfree_skb_any(skb);
581d708e 3001 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3002 return NETDEV_TX_OK;
3003 }
3004
fd803241
JK		 3005 if (likely(tso)) {
3006 tx_ring->last_tx_tso = 1;
1da177e4 3007 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 3008 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 3009 tx_flags |= E1000_TX_FLAGS_CSUM;
3010
2d7edb92 3011 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 3012 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 3013 * no longer assume, we must. */
60828236 3014 if (likely(skb->protocol == htons(ETH_P_IP)))
2d7edb92
MC		 3015 tx_flags |= E1000_TX_FLAGS_IPV4;
3016
581d708e
MC		 3017 e1000_tx_queue(adapter, tx_ring, tx_flags,
3018 e1000_tx_map(adapter, tx_ring, skb, first,
3019 max_per_txd, nr_frags, mss));
1da177e4
LT		 3020
3021 netdev->trans_start = jiffies;
3022
3023 /* Make sure there is space in the ring for the next send. */
581d708e 3024 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 3025 netif_stop_queue(netdev);
3026
581d708e 3027 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3028 return NETDEV_TX_OK;
3029}
3030
3031/**
3032 * e1000_tx_timeout - Respond to a Tx Hang
3033 * @netdev: network interface device structure
3034 **/
3035
3036static void
3037e1000_tx_timeout(struct net_device *netdev)
3038{
60490fe0 3039 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3040
3041 /* Do the reset outside of interrupt context */
87041639
JK		 3042 adapter->tx_timeout_count++;
3043 schedule_work(&adapter->reset_task);
1da177e4
LT		 3044}
3045
3046static void
87041639 3047e1000_reset_task(struct net_device *netdev)
1da177e4 3048{
60490fe0 3049 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3050
2db10a08 3051 e1000_reinit_locked(adapter);
1da177e4
LT		 3052}
3053
3054/**
3055 * e1000_get_stats - Get System Network Statistics
3056 * @netdev: network interface device structure
3057 *
3058 * Returns the address of the device statistics structure.
3059 * The statistics are actually updated from the timer callback.
3060 **/
3061
3062static struct net_device_stats *
3063e1000_get_stats(struct net_device *netdev)
3064{
60490fe0 3065 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3066
6b7660cd 3067 /* only return the current stats */
1da177e4
LT		 3068 return &adapter->net_stats;
3069}
3070
3071/**
3072 * e1000_change_mtu - Change the Maximum Transfer Unit
3073 * @netdev: network interface device structure
3074 * @new_mtu: new value for maximum frame size
3075 *
3076 * Returns 0 on success, negative on failure
3077 **/
3078
3079static int
3080e1000_change_mtu(struct net_device *netdev, int new_mtu)
3081{
60490fe0 3082 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3083 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 3084 uint16_t eeprom_data = 0;
1da177e4 3085
96838a40
JB		 3086 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3087 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3088 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3089 return -EINVAL;
2d7edb92 3090 }
1da177e4 3091
997f5cbd
JK		 3092 /* Adapter-specific max frame size limits. */
3093 switch (adapter->hw.mac_type) {
9e2feace 3094 case e1000_undefined ... e1000_82542_rev2_1:
cd94dd0b 3095 case e1000_ich8lan:
997f5cbd
JK		 3096 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3097 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3098 return -EINVAL;
2d7edb92 3099 }
997f5cbd 3100 break;
85b22eb6
JK		 3101 case e1000_82573:
3102 /* only enable jumbo frames if ASPM is disabled completely
3103 * this means both bits must be zero in 0x1A bits 3:2 */
3104 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
3105 &eeprom_data);
3106 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
3107 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3108 DPRINTK(PROBE, ERR,
3109 "Jumbo Frames not supported.\n");
3110 return -EINVAL;
3111 }
3112 break;
3113 }
3114 /* fall through to get support */
997f5cbd
JK		 3115 case e1000_82571:
3116 case e1000_82572:
87041639 3117 case e1000_80003es2lan:
997f5cbd
JK		 3118#define MAX_STD_JUMBO_FRAME_SIZE 9234
3119 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3120 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3121 return -EINVAL;
3122 }
3123 break;
3124 default:
3125 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3126 break;
1da177e4
LT		 3127 }
3128
87f5032e 3129 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
9e2feace
AK		 3130 * means we reserve 2 more, this pushes us to allocate from the next
3131 * larger slab size
3132 * i.e. RXBUFFER_2048 --> size-4096 slab */
3133
3134 if (max_frame <= E1000_RXBUFFER_256)
3135 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3136 else if (max_frame <= E1000_RXBUFFER_512)
3137 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3138 else if (max_frame <= E1000_RXBUFFER_1024)
3139 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3140 else if (max_frame <= E1000_RXBUFFER_2048)
3141 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3142 else if (max_frame <= E1000_RXBUFFER_4096)
3143 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3144 else if (max_frame <= E1000_RXBUFFER_8192)
3145 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3146 else if (max_frame <= E1000_RXBUFFER_16384)
3147 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3148
3149 /* adjust allocation if LPE protects us, and we aren't using SBP */
9e2feace
AK		 3150 if (!adapter->hw.tbi_compatibility_on &&
3151 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3152 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3153 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3154
2d7edb92
MC		 3155 netdev->mtu = new_mtu;
3156
2db10a08
AK		 3157 if (netif_running(netdev))
3158 e1000_reinit_locked(adapter);
1da177e4 3159
1da177e4
LT		 3160 adapter->hw.max_frame_size = max_frame;
3161
3162 return 0;
3163}
3164
3165/**
3166 * e1000_update_stats - Update the board statistics counters
3167 * @adapter: board private structure
3168 **/
3169
3170void
3171e1000_update_stats(struct e1000_adapter *adapter)
3172{
3173 struct e1000_hw *hw = &adapter->hw;
282f33c9 3174 struct pci_dev *pdev = adapter->pdev;
1da177e4
LT		 3175 unsigned long flags;
3176 uint16_t phy_tmp;
3177
3178#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3179
282f33c9
LV		 3180 /*
3181 * Prevent stats update while adapter is being reset, or if the pci
3182 * connection is down.
3183 */
9026729b 3184 if (adapter->link_speed == 0)
282f33c9
LV		 3185 return;
3186 if (pdev->error_state && pdev->error_state != pci_channel_io_normal)
9026729b
AK		 3187 return;
3188
1da177e4
LT		 3189 spin_lock_irqsave(&adapter->stats_lock, flags);
3190
3191 /* these counters are modified from e1000_adjust_tbi_stats,
3192 * called from the interrupt context, so they must only
3193 * be written while holding adapter->stats_lock
3194 */
3195
3196 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3197 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3198 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3199 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3200 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3201 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3202 adapter->stats.roc += E1000_READ_REG(hw, ROC);
cd94dd0b
AK		 3203
3204 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 3205 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3206 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3207 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3208 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3209 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3210 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
cd94dd0b 3211 }
1da177e4
LT		 3212
3213 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3214 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3215 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3216 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3217 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3218 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3219 adapter->stats.dc += E1000_READ_REG(hw, DC);
3220 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3221 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3222 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3223 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3224 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3225 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3226 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3227 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3228 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3229 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3230 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3231 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3232 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3233 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3234 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3235 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3236 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3237 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3238 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
cd94dd0b
AK		 3239
3240 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 3241 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3242 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3243 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3244 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3245 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3246 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 3247 }
3248
1da177e4
LT		 3249 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3250 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3251
3252 /* used for adaptive IFS */
3253
3254 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3255 adapter->stats.tpt += hw->tx_packet_delta;
3256 hw->collision_delta = E1000_READ_REG(hw, COLC);
3257 adapter->stats.colc += hw->collision_delta;
3258
96838a40 3259 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3260 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3261 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3262 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3263 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3264 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3265 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3266 }
96838a40 3267 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3268 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3269 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 3270
3271 if (adapter->hw.mac_type != e1000_ich8lan) {
2d7edb92
MC		 3272 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3273 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3274 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3275 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3276 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3277 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3278 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
cd94dd0b 3279 }
2d7edb92 3280 }
1da177e4
LT		 3281
3282 /* Fill out the OS statistics structure */
3283
3284 adapter->net_stats.rx_packets = adapter->stats.gprc;
3285 adapter->net_stats.tx_packets = adapter->stats.gptc;
3286 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3287 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3288 adapter->net_stats.multicast = adapter->stats.mprc;
3289 adapter->net_stats.collisions = adapter->stats.colc;
3290
3291 /* Rx Errors */
3292
87041639
JK		 3293 /* RLEC on some newer hardware can be incorrect so build
3294 * our own version based on RUC and ROC */
1da177e4
LT		 3295 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3296 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3297 adapter->stats.ruc + adapter->stats.roc +
3298 adapter->stats.cexterr;
87041639
JK		 3299 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3300 adapter->stats.roc;
1da177e4
LT		 3301 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3302 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3303 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3304
3305 /* Tx Errors */
3306
3307 adapter->net_stats.tx_errors = adapter->stats.ecol +
3308 adapter->stats.latecol;
3309 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3310 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3311 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3312
3313 /* Tx Dropped needs to be maintained elsewhere */
3314
3315 /* Phy Stats */
3316
96838a40
JB		 3317 if (hw->media_type == e1000_media_type_copper) {
3318 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3319 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3320 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3321 adapter->phy_stats.idle_errors += phy_tmp;
3322 }
3323
96838a40 3324 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3325 (hw->phy_type == e1000_phy_m88) &&
3326 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3327 adapter->phy_stats.receive_errors += phy_tmp;
3328 }
3329
3330 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3331}
3332
3333/**
3334 * e1000_intr - Interrupt Handler
3335 * @irq: interrupt number
3336 * @data: pointer to a network interface device structure
3337 * @pt_regs: CPU registers structure
3338 **/
3339
3340static irqreturn_t
3341e1000_intr(int irq, void *data, struct pt_regs *regs)
3342{
3343 struct net_device *netdev = data;
60490fe0 3344 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3345 struct e1000_hw *hw = &adapter->hw;
87041639 3346 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3347#ifndef CONFIG_E1000_NAPI
581d708e 3348 int i;
1e613fd9
JK		 3349#else
3350 /* Interrupt Auto-Mask...upon reading ICR,
3351 * interrupts are masked. No need for the
3352 * IMC write, but it does mean we should
3353 * account for it ASAP. */
3354 if (likely(hw->mac_type >= e1000_82571))
3355 atomic_inc(&adapter->irq_sem);
be2b28ed 3356#endif
1da177e4 3357
1e613fd9
JK		 3358 if (unlikely(!icr)) {
3359#ifdef CONFIG_E1000_NAPI
3360 if (hw->mac_type >= e1000_82571)
3361 e1000_irq_enable(adapter);
3362#endif
1da177e4 3363 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3364 }
1da177e4 3365
96838a40 3366 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3367 hw->get_link_status = 1;
87041639
JK		 3368 /* 80003ES2LAN workaround--
3369 * For packet buffer work-around on link down event;
3370 * disable receives here in the ISR and
3371 * reset adapter in watchdog
3372 */
3373 if (netif_carrier_ok(netdev) &&
3374 (adapter->hw.mac_type == e1000_80003es2lan)) {
3375 /* disable receives */
3376 rctl = E1000_READ_REG(hw, RCTL);
3377 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3378 }
1da177e4
LT		 3379 mod_timer(&adapter->watchdog_timer, jiffies);
3380 }
3381
3382#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3383 if (unlikely(hw->mac_type < e1000_82571)) {
3384 atomic_inc(&adapter->irq_sem);
3385 E1000_WRITE_REG(hw, IMC, ~0);
3386 E1000_WRITE_FLUSH(hw);
3387 }
d3d9e484
AK		 3388 if (likely(netif_rx_schedule_prep(netdev)))
3389 __netif_rx_schedule(netdev);
581d708e
MC		 3390 else
3391 e1000_irq_enable(adapter);
c1605eb3 3392#else
1da177e4 3393 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3394 * Due to Hub Link bus being occupied, an interrupt
3395 * de-assertion message is not able to be sent.
3396 * When an interrupt assertion message is generated later,
3397 * two messages are re-ordered and sent out.
3398 * That causes APIC to think 82547 is in de-assertion
3399 * state, while 82547 is in assertion state, resulting
3400 * in dead lock. Writing IMC forces 82547 into
3401 * de-assertion state.
3402 */
3403 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3404 atomic_inc(&adapter->irq_sem);
2648345f 3405 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3406 }
3407
96838a40
JB		 3408 for (i = 0; i < E1000_MAX_INTR; i++)
3409 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
581d708e 3410 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3411 break;
3412
96838a40 3413 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3414 e1000_irq_enable(adapter);
581d708e 3415
c1605eb3 3416#endif
1da177e4
LT		 3417
3418 return IRQ_HANDLED;
3419}
3420
3421#ifdef CONFIG_E1000_NAPI
3422/**
3423 * e1000_clean - NAPI Rx polling callback
3424 * @adapter: board private structure
3425 **/
3426
3427static int
581d708e 3428e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3429{
581d708e
MC		 3430 struct e1000_adapter *adapter;
3431 int work_to_do = min(*budget, poll_dev->quota);
d3d9e484 3432 int tx_cleaned = 0, work_done = 0;
581d708e
MC		 3433
3434 /* Must NOT use netdev_priv macro here. */
3435 adapter = poll_dev->priv;
3436
3437 /* Keep link state information with original netdev */
d3d9e484 3438 if (!netif_carrier_ok(poll_dev))
581d708e 3439 goto quit_polling;
2648345f 3440
d3d9e484
AK		 3441 /* e1000_clean is called per-cpu. This lock protects
3442 * tx_ring[0] from being cleaned by multiple cpus
3443 * simultaneously. A failure obtaining the lock means
3444 * tx_ring[0] is currently being cleaned anyway. */
3445 if (spin_trylock(&adapter->tx_queue_lock)) {
3446 tx_cleaned = e1000_clean_tx_irq(adapter,
3447 &adapter->tx_ring[0]);
3448 spin_unlock(&adapter->tx_queue_lock);
581d708e
MC		 3449 }
3450
d3d9e484 3451 adapter->clean_rx(adapter, &adapter->rx_ring[0],
581d708e 3452 &work_done, work_to_do);
1da177e4
LT		 3453
3454 *budget -= work_done;
581d708e 3455 poll_dev->quota -= work_done;
96838a40 3456
2b02893e 3457 /* If no Tx and not enough Rx work done, exit the polling mode */
96838a40 3458 if ((!tx_cleaned && (work_done == 0)) ||
d3d9e484 3459 !netif_running(poll_dev)) {
581d708e
MC		 3460quit_polling:
3461 netif_rx_complete(poll_dev);
1da177e4
LT		 3462 e1000_irq_enable(adapter);
3463 return 0;
3464 }
3465
3466 return 1;
3467}
3468
3469#endif
3470/**
3471 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3472 * @adapter: board private structure
3473 **/
3474
3475static boolean_t
581d708e
MC		 3476e1000_clean_tx_irq(struct e1000_adapter *adapter,
3477 struct e1000_tx_ring *tx_ring)
1da177e4 3478{
1da177e4
LT		 3479 struct net_device *netdev = adapter->netdev;
3480 struct e1000_tx_desc *tx_desc, *eop_desc;
3481 struct e1000_buffer *buffer_info;
3482 unsigned int i, eop;
2a1af5d7
JK		 3483#ifdef CONFIG_E1000_NAPI
3484 unsigned int count = 0;
3485#endif
1da177e4
LT		 3486 boolean_t cleaned = FALSE;
3487
3488 i = tx_ring->next_to_clean;
3489 eop = tx_ring->buffer_info[i].next_to_watch;
3490 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3491
581d708e 3492 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3493 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3494 tx_desc = E1000_TX_DESC(*tx_ring, i);
3495 buffer_info = &tx_ring->buffer_info[i];
3496 cleaned = (i == eop);
3497
fd803241 3498 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
8241e35e 3499 memset(tx_desc, 0, sizeof(struct e1000_tx_desc));
1da177e4 3500
96838a40 3501 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3502 }
581d708e 3503
7bfa4816 3504
1da177e4
LT		 3505 eop = tx_ring->buffer_info[i].next_to_watch;
3506 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 3507#ifdef CONFIG_E1000_NAPI
3508#define E1000_TX_WEIGHT 64
3509 /* weight of a sort for tx, to avoid endless transmit cleanup */
3510 if (count++ == E1000_TX_WEIGHT) break;
3511#endif
1da177e4
LT		 3512 }
3513
3514 tx_ring->next_to_clean = i;
3515
77b2aad5 3516#define TX_WAKE_THRESHOLD 32
96838a40 3517 if (unlikely(cleaned && netif_queue_stopped(netdev) &&
77b2aad5
AK		 3518 netif_carrier_ok(netdev))) {
3519 spin_lock(&tx_ring->tx_lock);
3520 if (netif_queue_stopped(netdev) &&
3521 (E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))
3522 netif_wake_queue(netdev);
3523 spin_unlock(&tx_ring->tx_lock);
3524 }
2648345f 3525
581d708e 3526 if (adapter->detect_tx_hung) {
2648345f 3527 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3528 * check with the clearing of time_stamp and movement of i */
3529 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3530 if (tx_ring->buffer_info[eop].dma &&
3531 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 3532 (adapter->tx_timeout_factor * HZ))
70b8f1e1 3533 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3534 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3535
3536 /* detected Tx unit hang */
c6963ef5 3537 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3538 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3539 " TDH <%x>\n"
3540 " TDT <%x>\n"
3541 " next_to_use <%x>\n"
3542 " next_to_clean <%x>\n"
3543 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3544 " time_stamp <%lx>\n"
3545 " next_to_watch <%x>\n"
3546 " jiffies <%lx>\n"
3547 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3548 (unsigned long)((tx_ring - adapter->tx_ring) /
3549 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3550 readl(adapter->hw.hw_addr + tx_ring->tdh),
3551 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3552 tx_ring->next_to_use,
392137fa
JK		 3553 tx_ring->next_to_clean,
3554 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3555 eop,
3556 jiffies,
3557 eop_desc->upper.fields.status);
1da177e4 3558 netif_stop_queue(netdev);
70b8f1e1 3559 }
1da177e4 3560 }
1da177e4
LT		 3561 return cleaned;
3562}
3563
3564/**
3565 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3566 * @adapter: board private structure
3567 * @status_err: receive descriptor status and error fields
3568 * @csum: receive descriptor csum field
3569 * @sk_buff: socket buffer with received data
1da177e4
LT		 3570 **/
3571
e619d523 3572static void
1da177e4 3573e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3574 uint32_t status_err, uint32_t csum,
3575 struct sk_buff *skb)
1da177e4 3576{
2d7edb92
MC		 3577 uint16_t status = (uint16_t)status_err;
3578 uint8_t errors = (uint8_t)(status_err >> 24);
3579 skb->ip_summed = CHECKSUM_NONE;
3580
1da177e4 3581 /* 82543 or newer only */
96838a40 3582 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3583 /* Ignore Checksum bit is set */
96838a40 3584 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 3585 /* TCP/UDP checksum error bit is set */
96838a40 3586 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3587 /* let the stack verify checksum errors */
1da177e4 3588 adapter->hw_csum_err++;
2d7edb92
MC		 3589 return;
3590 }
3591 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 3592 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
3593 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 3594 return;
1da177e4 3595 } else {
96838a40 3596 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 3597 return;
3598 }
3599 /* It must be a TCP or UDP packet with a valid checksum */
3600 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3601 /* TCP checksum is good */
3602 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3603 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3604 /* IP fragment with UDP payload */
3605 /* Hardware complements the payload checksum, so we undo it
3606 * and then put the value in host order for further stack use.
3607 */
3608 csum = ntohl(csum ^ 0xFFFF);
3609 skb->csum = csum;
3610 skb->ip_summed = CHECKSUM_HW;
1da177e4 3611 }
2d7edb92 3612 adapter->hw_csum_good++;
1da177e4
LT		 3613}
3614
3615/**
2d7edb92 3616 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3617 * @adapter: board private structure
3618 **/
3619
3620static boolean_t
3621#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3622e1000_clean_rx_irq(struct e1000_adapter *adapter,
3623 struct e1000_rx_ring *rx_ring,
3624 int *work_done, int work_to_do)
1da177e4 3625#else
581d708e
MC		 3626e1000_clean_rx_irq(struct e1000_adapter *adapter,
3627 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3628#endif
3629{
1da177e4
LT		 3630 struct net_device *netdev = adapter->netdev;
3631 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 3632 struct e1000_rx_desc *rx_desc, *next_rxd;
3633 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 3634 unsigned long flags;
3635 uint32_t length;
3636 uint8_t last_byte;
3637 unsigned int i;
72d64a43 3638 int cleaned_count = 0;
a1415ee6 3639 boolean_t cleaned = FALSE;
1da177e4
LT		 3640
3641 i = rx_ring->next_to_clean;
3642 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 3643 buffer_info = &rx_ring->buffer_info[i];
1da177e4 3644
b92ff8ee 3645 while (rx_desc->status & E1000_RXD_STAT_DD) {
24f476ee 3646 struct sk_buff *skb;
a292ca6e 3647 u8 status;
1da177e4 3648#ifdef CONFIG_E1000_NAPI
96838a40 3649 if (*work_done >= work_to_do)
1da177e4
LT		 3650 break;
3651 (*work_done)++;
3652#endif
a292ca6e 3653 status = rx_desc->status;
b92ff8ee 3654 skb = buffer_info->skb;
86c3d59f
JB		 3655 buffer_info->skb = NULL;
3656
30320be8
JK		 3657 prefetch(skb->data - NET_IP_ALIGN);
3658
86c3d59f
JB		 3659 if (++i == rx_ring->count) i = 0;
3660 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 3661 prefetch(next_rxd);
3662
86c3d59f 3663 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 3664
72d64a43
JK		 3665 cleaned = TRUE;
3666 cleaned_count++;
a292ca6e
JK		 3667 pci_unmap_single(pdev,
3668 buffer_info->dma,
3669 buffer_info->length,
1da177e4
LT		 3670 PCI_DMA_FROMDEVICE);
3671
1da177e4
LT		 3672 length = le16_to_cpu(rx_desc->length);
3673
f235a2ab
AK		 3674 /* adjust length to remove Ethernet CRC */
3675 length -= 4;
3676
a1415ee6
JK		 3677 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
3678 /* All receives must fit into a single buffer */
3679 E1000_DBG("%s: Receive packet consumed multiple"
3680 " buffers\n", netdev->name);
864c4e45 3681 /* recycle */
8fc897b0 3682 buffer_info->skb = skb;
1da177e4
LT		 3683 goto next_desc;
3684 }
3685
96838a40 3686 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 3687 last_byte = *(skb->data + length - 1);
b92ff8ee 3688 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 3689 rx_desc->errors, length, last_byte)) {
3690 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 3691 e1000_tbi_adjust_stats(&adapter->hw,
3692 &adapter->stats,
1da177e4
LT		 3693 length, skb->data);
3694 spin_unlock_irqrestore(&adapter->stats_lock,
3695 flags);
3696 length--;
3697 } else {
9e2feace
AK		 3698 /* recycle */
3699 buffer_info->skb = skb;
1da177e4
LT		 3700 goto next_desc;
3701 }
1cb5821f 3702 }
1da177e4 3703
a292ca6e
JK		 3704 /* code added for copybreak, this should improve
3705 * performance for small packets with large amounts
3706 * of reassembly being done in the stack */
3707#define E1000_CB_LENGTH 256
a1415ee6 3708 if (length < E1000_CB_LENGTH) {
a292ca6e 3709 struct sk_buff *new_skb =
87f5032e 3710 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
a292ca6e
JK		 3711 if (new_skb) {
3712 skb_reserve(new_skb, NET_IP_ALIGN);
3713 new_skb->dev = netdev;
3714 memcpy(new_skb->data - NET_IP_ALIGN,
3715 skb->data - NET_IP_ALIGN,
3716 length + NET_IP_ALIGN);
3717 /* save the skb in buffer_info as good */
3718 buffer_info->skb = skb;
3719 skb = new_skb;
3720 skb_put(skb, length);
3721 }
a1415ee6
JK		 3722 } else
3723 skb_put(skb, length);
a292ca6e
JK		 3724
3725 /* end copybreak code */
1da177e4
LT		 3726
3727 /* Receive Checksum Offload */
a292ca6e
JK		 3728 e1000_rx_checksum(adapter,
3729 (uint32_t)(status) |
2d7edb92 3730 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 3731 le16_to_cpu(rx_desc->csum), skb);
96838a40 3732
1da177e4
LT		 3733 skb->protocol = eth_type_trans(skb, netdev);
3734#ifdef CONFIG_E1000_NAPI
96838a40 3735 if (unlikely(adapter->vlgrp &&
a292ca6e 3736 (status & E1000_RXD_STAT_VP))) {
1da177e4 3737 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3738 le16_to_cpu(rx_desc->special) &
3739 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3740 } else {
3741 netif_receive_skb(skb);
3742 }
3743#else /* CONFIG_E1000_NAPI */
96838a40 3744 if (unlikely(adapter->vlgrp &&
b92ff8ee 3745 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 3746 vlan_hwaccel_rx(skb, adapter->vlgrp,
3747 le16_to_cpu(rx_desc->special) &
3748 E1000_RXD_SPC_VLAN_MASK);
3749 } else {
3750 netif_rx(skb);
3751 }
3752#endif /* CONFIG_E1000_NAPI */
3753 netdev->last_rx = jiffies;
3754
3755next_desc:
3756 rx_desc->status = 0;
1da177e4 3757
72d64a43
JK		 3758 /* return some buffers to hardware, one at a time is too slow */
3759 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3760 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3761 cleaned_count = 0;
3762 }
3763
30320be8 3764 /* use prefetched values */
86c3d59f
JB		 3765 rx_desc = next_rxd;
3766 buffer_info = next_buffer;
1da177e4 3767 }
1da177e4 3768 rx_ring->next_to_clean = i;
72d64a43
JK		 3769
3770 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3771 if (cleaned_count)
3772 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92
MC		 3773
3774 return cleaned;
3775}
3776
3777/**
3778 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3779 * @adapter: board private structure
3780 **/
3781
3782static boolean_t
3783#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3784e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3785 struct e1000_rx_ring *rx_ring,
3786 int *work_done, int work_to_do)
2d7edb92 3787#else
581d708e
MC		 3788e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3789 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3790#endif
3791{
86c3d59f 3792 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 3793 struct net_device *netdev = adapter->netdev;
3794 struct pci_dev *pdev = adapter->pdev;
86c3d59f 3795 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 3796 struct e1000_ps_page *ps_page;
3797 struct e1000_ps_page_dma *ps_page_dma;
24f476ee 3798 struct sk_buff *skb;
2d7edb92
MC		 3799 unsigned int i, j;
3800 uint32_t length, staterr;
72d64a43 3801 int cleaned_count = 0;
2d7edb92
MC		 3802 boolean_t cleaned = FALSE;
3803
3804 i = rx_ring->next_to_clean;
3805 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3806 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 3807 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 3808
96838a40 3809 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 3810 ps_page = &rx_ring->ps_page[i];
3811 ps_page_dma = &rx_ring->ps_page_dma[i];
3812#ifdef CONFIG_E1000_NAPI
96838a40 3813 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 3814 break;
3815 (*work_done)++;
3816#endif
86c3d59f
JB		 3817 skb = buffer_info->skb;
3818
30320be8
JK		 3819 /* in the packet split case this is header only */
3820 prefetch(skb->data - NET_IP_ALIGN);
3821
86c3d59f
JB		 3822 if (++i == rx_ring->count) i = 0;
3823 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 3824 prefetch(next_rxd);
3825
86c3d59f 3826 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 3827
2d7edb92 3828 cleaned = TRUE;
72d64a43 3829 cleaned_count++;
2d7edb92
MC		 3830 pci_unmap_single(pdev, buffer_info->dma,
3831 buffer_info->length,
3832 PCI_DMA_FROMDEVICE);
3833
96838a40 3834 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 3835 E1000_DBG("%s: Packet Split buffers didn't pick up"
3836 " the full packet\n", netdev->name);
3837 dev_kfree_skb_irq(skb);
3838 goto next_desc;
3839 }
1da177e4 3840
96838a40 3841 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 3842 dev_kfree_skb_irq(skb);
3843 goto next_desc;
3844 }
3845
3846 length = le16_to_cpu(rx_desc->wb.middle.length0);
3847
96838a40 3848 if (unlikely(!length)) {
2d7edb92
MC		 3849 E1000_DBG("%s: Last part of the packet spanning"
3850 " multiple descriptors\n", netdev->name);
3851 dev_kfree_skb_irq(skb);
3852 goto next_desc;
3853 }
3854
3855 /* Good Receive */
3856 skb_put(skb, length);
3857
dc7c6add
JK		 3858 {
3859 /* this looks ugly, but it seems compiler issues make it
3860 more efficient than reusing j */
3861 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
3862
3863 /* page alloc/put takes too long and effects small packet
3864 * throughput, so unsplit small packets and save the alloc/put*/
9e2feace 3865 if (l1 && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add 3866 u8 *vaddr;
76c224bc 3867 /* there is no documentation about how to call
dc7c6add
JK		 3868 * kmap_atomic, so we can't hold the mapping
3869 * very long */
3870 pci_dma_sync_single_for_cpu(pdev,
3871 ps_page_dma->ps_page_dma[0],
3872 PAGE_SIZE,
3873 PCI_DMA_FROMDEVICE);
3874 vaddr = kmap_atomic(ps_page->ps_page[0],
3875 KM_SKB_DATA_SOFTIRQ);
3876 memcpy(skb->tail, vaddr, l1);
3877 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
3878 pci_dma_sync_single_for_device(pdev,
3879 ps_page_dma->ps_page_dma[0],
3880 PAGE_SIZE, PCI_DMA_FROMDEVICE);
f235a2ab
AK		 3881 /* remove the CRC */
3882 l1 -= 4;
dc7c6add 3883 skb_put(skb, l1);
dc7c6add
JK		 3884 goto copydone;
3885 } /* if */
3886 }
3887
96838a40 3888 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 3889 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 3890 break;
2d7edb92
MC		 3891 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3892 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3893 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 3894 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
3895 length);
2d7edb92 3896 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 3897 skb->len += length;
3898 skb->data_len += length;
5d51b80f 3899 skb->truesize += length;
2d7edb92
MC		 3900 }
3901
f235a2ab
AK		 3902 /* strip the ethernet crc, problem is we're using pages now so
3903 * this whole operation can get a little cpu intensive */
3904 pskb_trim(skb, skb->len - 4);
3905
dc7c6add 3906copydone:
2d7edb92 3907 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 3908 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 3909 skb->protocol = eth_type_trans(skb, netdev);
3910
96838a40 3911 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 3912 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 3913 adapter->rx_hdr_split++;
2d7edb92 3914#ifdef CONFIG_E1000_NAPI
96838a40 3915 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3916 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3917 le16_to_cpu(rx_desc->wb.middle.vlan) &
3918 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3919 } else {
3920 netif_receive_skb(skb);
3921 }
3922#else /* CONFIG_E1000_NAPI */
96838a40 3923 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3924 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3925 le16_to_cpu(rx_desc->wb.middle.vlan) &
3926 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3927 } else {
3928 netif_rx(skb);
3929 }
3930#endif /* CONFIG_E1000_NAPI */
3931 netdev->last_rx = jiffies;
3932
3933next_desc:
c3d7a3a4 3934 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 3935 buffer_info->skb = NULL;
2d7edb92 3936
72d64a43
JK		 3937 /* return some buffers to hardware, one at a time is too slow */
3938 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3939 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3940 cleaned_count = 0;
3941 }
3942
30320be8 3943 /* use prefetched values */
86c3d59f
JB		 3944 rx_desc = next_rxd;
3945 buffer_info = next_buffer;
3946
683a38f3 3947 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3948 }
3949 rx_ring->next_to_clean = i;
72d64a43
JK		 3950
3951 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3952 if (cleaned_count)
3953 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4
LT		 3954
3955 return cleaned;
3956}
3957
3958/**
2d7edb92 3959 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3960 * @adapter: address of board private structure
3961 **/
3962
3963static void
581d708e 3964e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 3965 struct e1000_rx_ring *rx_ring,
a292ca6e 3966 int cleaned_count)
1da177e4 3967{
1da177e4
LT		 3968 struct net_device *netdev = adapter->netdev;
3969 struct pci_dev *pdev = adapter->pdev;
3970 struct e1000_rx_desc *rx_desc;
3971 struct e1000_buffer *buffer_info;
3972 struct sk_buff *skb;
2648345f
MC		 3973 unsigned int i;
3974 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3975
3976 i = rx_ring->next_to_use;
3977 buffer_info = &rx_ring->buffer_info[i];
3978
a292ca6e
JK		 3979 while (cleaned_count--) {
3980 if (!(skb = buffer_info->skb))
87f5032e 3981 skb = netdev_alloc_skb(netdev, bufsz);
a292ca6e
JK		 3982 else {
3983 skb_trim(skb, 0);
3984 goto map_skb;
3985 }
3986
96838a40 3987 if (unlikely(!skb)) {
1da177e4 3988 /* Better luck next round */
72d64a43 3989 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 3990 break;
3991 }
3992
2648345f 3993 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3994 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3995 struct sk_buff *oldskb = skb;
2648345f
MC		 3996 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3997 "at %p\n", bufsz, skb->data);
3998 /* Try again, without freeing the previous */
87f5032e 3999 skb = netdev_alloc_skb(netdev, bufsz);
2648345f 4000 /* Failed allocation, critical failure */
1da177e4
LT		 4001 if (!skb) {
4002 dev_kfree_skb(oldskb);
4003 break;
4004 }
2648345f 4005
1da177e4
LT		 4006 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4007 /* give up */
4008 dev_kfree_skb(skb);
4009 dev_kfree_skb(oldskb);
4010 break; /* while !buffer_info->skb */
4011 } else {
2648345f 4012 /* Use new allocation */
1da177e4
LT		 4013 dev_kfree_skb(oldskb);
4014 }
4015 }
1da177e4
LT		 4016 /* Make buffer alignment 2 beyond a 16 byte boundary
4017 * this will result in a 16 byte aligned IP header after
4018 * the 14 byte MAC header is removed
4019 */
4020 skb_reserve(skb, NET_IP_ALIGN);
4021
4022 skb->dev = netdev;
4023
4024 buffer_info->skb = skb;
4025 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 4026map_skb:
1da177e4
LT		 4027 buffer_info->dma = pci_map_single(pdev,
4028 skb->data,
4029 adapter->rx_buffer_len,
4030 PCI_DMA_FROMDEVICE);
4031
2648345f
MC		 4032 /* Fix for errata 23, can't cross 64kB boundary */
4033 if (!e1000_check_64k_bound(adapter,
4034 (void *)(unsigned long)buffer_info->dma,
4035 adapter->rx_buffer_len)) {
4036 DPRINTK(RX_ERR, ERR,
4037 "dma align check failed: %u bytes at %p\n",
4038 adapter->rx_buffer_len,
4039 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 4040 dev_kfree_skb(skb);
4041 buffer_info->skb = NULL;
4042
2648345f 4043 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 4044 adapter->rx_buffer_len,
4045 PCI_DMA_FROMDEVICE);
4046
4047 break; /* while !buffer_info->skb */
4048 }
1da177e4
LT		 4049 rx_desc = E1000_RX_DESC(*rx_ring, i);
4050 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4051
96838a40
JB		 4052 if (unlikely(++i == rx_ring->count))
4053 i = 0;
1da177e4
LT		 4054 buffer_info = &rx_ring->buffer_info[i];
4055 }
4056
b92ff8ee
JB		 4057 if (likely(rx_ring->next_to_use != i)) {
4058 rx_ring->next_to_use = i;
4059 if (unlikely(i-- == 0))
4060 i = (rx_ring->count - 1);
4061
4062 /* Force memory writes to complete before letting h/w
4063 * know there are new descriptors to fetch. (Only
4064 * applicable for weak-ordered memory model archs,
4065 * such as IA-64). */
4066 wmb();
4067 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4068 }
1da177e4
LT		 4069}
4070
2d7edb92
MC		 4071/**
4072 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
4073 * @adapter: address of board private structure
4074 **/
4075
4076static void
581d708e 4077e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 4078 struct e1000_rx_ring *rx_ring,
4079 int cleaned_count)
2d7edb92 4080{
2d7edb92
MC		 4081 struct net_device *netdev = adapter->netdev;
4082 struct pci_dev *pdev = adapter->pdev;
4083 union e1000_rx_desc_packet_split *rx_desc;
4084 struct e1000_buffer *buffer_info;
4085 struct e1000_ps_page *ps_page;
4086 struct e1000_ps_page_dma *ps_page_dma;
4087 struct sk_buff *skb;
4088 unsigned int i, j;
4089
4090 i = rx_ring->next_to_use;
4091 buffer_info = &rx_ring->buffer_info[i];
4092 ps_page = &rx_ring->ps_page[i];
4093 ps_page_dma = &rx_ring->ps_page_dma[i];
4094
72d64a43 4095 while (cleaned_count--) {
2d7edb92
MC		 4096 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4097
96838a40 4098 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4099 if (j < adapter->rx_ps_pages) {
4100 if (likely(!ps_page->ps_page[j])) {
4101 ps_page->ps_page[j] =
4102 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4103 if (unlikely(!ps_page->ps_page[j])) {
4104 adapter->alloc_rx_buff_failed++;
e4c811c9 4105 goto no_buffers;
b92ff8ee 4106 }
e4c811c9
MC		 4107 ps_page_dma->ps_page_dma[j] =
4108 pci_map_page(pdev,
4109 ps_page->ps_page[j],
4110 0, PAGE_SIZE,
4111 PCI_DMA_FROMDEVICE);
4112 }
4113 /* Refresh the desc even if buffer_addrs didn't
96838a40 4114 * change because each write-back erases
e4c811c9
MC		 4115 * this info.
4116 */
4117 rx_desc->read.buffer_addr[j+1] =
4118 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4119 } else
4120 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4121 }
4122
87f5032e
DM		 4123 skb = netdev_alloc_skb(netdev,
4124 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
2d7edb92 4125
b92ff8ee
JB		 4126 if (unlikely(!skb)) {
4127 adapter->alloc_rx_buff_failed++;
2d7edb92 4128 break;
b92ff8ee 4129 }
2d7edb92
MC		 4130
4131 /* Make buffer alignment 2 beyond a 16 byte boundary
4132 * this will result in a 16 byte aligned IP header after
4133 * the 14 byte MAC header is removed
4134 */
4135 skb_reserve(skb, NET_IP_ALIGN);
4136
4137 skb->dev = netdev;
4138
4139 buffer_info->skb = skb;
4140 buffer_info->length = adapter->rx_ps_bsize0;
4141 buffer_info->dma = pci_map_single(pdev, skb->data,
4142 adapter->rx_ps_bsize0,
4143 PCI_DMA_FROMDEVICE);
4144
4145 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4146
96838a40 4147 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4148 buffer_info = &rx_ring->buffer_info[i];
4149 ps_page = &rx_ring->ps_page[i];
4150 ps_page_dma = &rx_ring->ps_page_dma[i];
4151 }
4152
4153no_buffers:
b92ff8ee
JB		 4154 if (likely(rx_ring->next_to_use != i)) {
4155 rx_ring->next_to_use = i;
4156 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4157
4158 /* Force memory writes to complete before letting h/w
4159 * know there are new descriptors to fetch. (Only
4160 * applicable for weak-ordered memory model archs,
4161 * such as IA-64). */
4162 wmb();
4163 /* Hardware increments by 16 bytes, but packet split
4164 * descriptors are 32 bytes...so we increment tail
4165 * twice as much.
4166 */
4167 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4168 }
2d7edb92
MC		 4169}
4170
1da177e4
LT		 4171/**
4172 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4173 * @adapter:
4174 **/
4175
4176static void
4177e1000_smartspeed(struct e1000_adapter *adapter)
4178{
4179 uint16_t phy_status;
4180 uint16_t phy_ctrl;
4181
96838a40 4182 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4183 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4184 return;
4185
96838a40 4186 if (adapter->smartspeed == 0) {
1da177e4
LT		 4187 /* If Master/Slave config fault is asserted twice,
4188 * we assume back-to-back */
4189 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4190 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4191 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4192 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4193 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4194 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4195 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4196 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4197 phy_ctrl);
4198 adapter->smartspeed++;
96838a40 4199 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4200 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4201 &phy_ctrl)) {
4202 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4203 MII_CR_RESTART_AUTO_NEG);
4204 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4205 phy_ctrl);
4206 }
4207 }
4208 return;
96838a40 4209 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4210 /* If still no link, perhaps using 2/3 pair cable */
4211 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4212 phy_ctrl |= CR_1000T_MS_ENABLE;
4213 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4214 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4215 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4216 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4217 MII_CR_RESTART_AUTO_NEG);
4218 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4219 }
4220 }
4221 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4222 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4223 adapter->smartspeed = 0;
4224}
4225
4226/**
4227 * e1000_ioctl -
4228 * @netdev:
4229 * @ifreq:
4230 * @cmd:
4231 **/
4232
4233static int
4234e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4235{
4236 switch (cmd) {
4237 case SIOCGMIIPHY:
4238 case SIOCGMIIREG:
4239 case SIOCSMIIREG:
4240 return e1000_mii_ioctl(netdev, ifr, cmd);
4241 default:
4242 return -EOPNOTSUPP;
4243 }
4244}
4245
4246/**
4247 * e1000_mii_ioctl -
4248 * @netdev:
4249 * @ifreq:
4250 * @cmd:
4251 **/
4252
4253static int
4254e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4255{
60490fe0 4256 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4257 struct mii_ioctl_data *data = if_mii(ifr);
4258 int retval;
4259 uint16_t mii_reg;
4260 uint16_t spddplx;
97876fc6 4261 unsigned long flags;
1da177e4 4262
96838a40 4263 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4264 return -EOPNOTSUPP;
4265
4266 switch (cmd) {
4267 case SIOCGMIIPHY:
4268 data->phy_id = adapter->hw.phy_addr;
4269 break;
4270 case SIOCGMIIREG:
96838a40 4271 if (!capable(CAP_NET_ADMIN))
1da177e4 4272 return -EPERM;
97876fc6 4273 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4274 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4275 &data->val_out)) {
4276 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4277 return -EIO;
97876fc6
MC		 4278 }
4279 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4280 break;
4281 case SIOCSMIIREG:
96838a40 4282 if (!capable(CAP_NET_ADMIN))
1da177e4 4283 return -EPERM;
96838a40 4284 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4285 return -EFAULT;
4286 mii_reg = data->val_in;
97876fc6 4287 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4288 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4289 mii_reg)) {
4290 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4291 return -EIO;
97876fc6 4292 }
dc86d32a 4293 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4294 switch (data->reg_num) {
4295 case PHY_CTRL:
96838a40 4296 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4297 break;
96838a40 4298 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4299 adapter->hw.autoneg = 1;
4300 adapter->hw.autoneg_advertised = 0x2F;
4301 } else {
4302 if (mii_reg & 0x40)
4303 spddplx = SPEED_1000;
4304 else if (mii_reg & 0x2000)
4305 spddplx = SPEED_100;
4306 else
4307 spddplx = SPEED_10;
4308 spddplx += (mii_reg & 0x100)
cb764326
JK		 4309 ? DUPLEX_FULL :
4310 DUPLEX_HALF;
1da177e4
LT		 4311 retval = e1000_set_spd_dplx(adapter,
4312 spddplx);
96838a40 4313 if (retval) {
97876fc6 4314 spin_unlock_irqrestore(
96838a40 4315 &adapter->stats_lock,
97876fc6 4316 flags);
1da177e4 4317 return retval;
97876fc6 4318 }
1da177e4 4319 }
2db10a08
AK		 4320 if (netif_running(adapter->netdev))
4321 e1000_reinit_locked(adapter);
4322 else
1da177e4
LT		 4323 e1000_reset(adapter);
4324 break;
4325 case M88E1000_PHY_SPEC_CTRL:
4326 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4327 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4328 spin_unlock_irqrestore(
4329 &adapter->stats_lock, flags);
1da177e4 4330 return -EIO;
97876fc6 4331 }
1da177e4
LT		 4332 break;
4333 }
4334 } else {
4335 switch (data->reg_num) {
4336 case PHY_CTRL:
96838a40 4337 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4338 break;
2db10a08
AK		 4339 if (netif_running(adapter->netdev))
4340 e1000_reinit_locked(adapter);
4341 else
1da177e4
LT		 4342 e1000_reset(adapter);
4343 break;
4344 }
4345 }
97876fc6 4346 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4347 break;
4348 default:
4349 return -EOPNOTSUPP;
4350 }
4351 return E1000_SUCCESS;
4352}
4353
4354void
4355e1000_pci_set_mwi(struct e1000_hw *hw)
4356{
4357 struct e1000_adapter *adapter = hw->back;
2648345f 4358 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4359
96838a40 4360 if (ret_val)
2648345f 4361 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4362}
4363
4364void
4365e1000_pci_clear_mwi(struct e1000_hw *hw)
4366{
4367 struct e1000_adapter *adapter = hw->back;
4368
4369 pci_clear_mwi(adapter->pdev);
4370}
4371
4372void
4373e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4374{
4375 struct e1000_adapter *adapter = hw->back;
4376
4377 pci_read_config_word(adapter->pdev, reg, value);
4378}
4379
4380void
4381e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4382{
4383 struct e1000_adapter *adapter = hw->back;
4384
4385 pci_write_config_word(adapter->pdev, reg, *value);
4386}
4387
e4c780b1 4388#if 0
1da177e4
LT		 4389uint32_t
4390e1000_io_read(struct e1000_hw *hw, unsigned long port)
4391{
4392 return inl(port);
4393}
e4c780b1 4394#endif /* 0 */
1da177e4
LT		 4395
4396void
4397e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4398{
4399 outl(value, port);
4400}
4401
4402static void
4403e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4404{
60490fe0 4405 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4406 uint32_t ctrl, rctl;
4407
4408 e1000_irq_disable(adapter);
4409 adapter->vlgrp = grp;
4410
96838a40 4411 if (grp) {
1da177e4
LT		 4412 /* enable VLAN tag insert/strip */
4413 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4414 ctrl |= E1000_CTRL_VME;
4415 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4416
cd94dd0b 4417 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 4418 /* enable VLAN receive filtering */
4419 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4420 rctl |= E1000_RCTL_VFE;
4421 rctl &= ~E1000_RCTL_CFIEN;
4422 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4423 e1000_update_mng_vlan(adapter);
cd94dd0b 4424 }
1da177e4
LT		 4425 } else {
4426 /* disable VLAN tag insert/strip */
4427 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4428 ctrl &= ~E1000_CTRL_VME;
4429 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4430
cd94dd0b 4431 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 4432 /* disable VLAN filtering */
4433 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4434 rctl &= ~E1000_RCTL_VFE;
4435 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
96838a40 4436 if (adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
2d7edb92
MC		 4437 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4438 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4439 }
cd94dd0b 4440 }
1da177e4
LT		 4441 }
4442
4443 e1000_irq_enable(adapter);
4444}
4445
4446static void
4447e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4448{
60490fe0 4449 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4450 uint32_t vfta, index;
96838a40
JB		 4451
4452 if ((adapter->hw.mng_cookie.status &
4453 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4454 (vid == adapter->mng_vlan_id))
2d7edb92 4455 return;
1da177e4
LT		 4456 /* add VID to filter table */
4457 index = (vid >> 5) & 0x7F;
4458 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4459 vfta |= (1 << (vid & 0x1F));
4460 e1000_write_vfta(&adapter->hw, index, vfta);
4461}
4462
4463static void
4464e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4465{
60490fe0 4466 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4467 uint32_t vfta, index;
4468
4469 e1000_irq_disable(adapter);
4470
96838a40 4471 if (adapter->vlgrp)
1da177e4
LT		 4472 adapter->vlgrp->vlan_devices[vid] = NULL;
4473
4474 e1000_irq_enable(adapter);
4475
96838a40
JB		 4476 if ((adapter->hw.mng_cookie.status &
4477 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4478 (vid == adapter->mng_vlan_id)) {
4479 /* release control to f/w */
4480 e1000_release_hw_control(adapter);
2d7edb92 4481 return;
ff147013
JK		 4482 }
4483
1da177e4
LT		 4484 /* remove VID from filter table */
4485 index = (vid >> 5) & 0x7F;
4486 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4487 vfta &= ~(1 << (vid & 0x1F));
4488 e1000_write_vfta(&adapter->hw, index, vfta);
4489}
4490
4491static void
4492e1000_restore_vlan(struct e1000_adapter *adapter)
4493{
4494 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4495
96838a40 4496 if (adapter->vlgrp) {
1da177e4 4497 uint16_t vid;
96838a40
JB		 4498 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4499 if (!adapter->vlgrp->vlan_devices[vid])
1da177e4
LT		 4500 continue;
4501 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4502 }
4503 }
4504}
4505
4506int
4507e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4508{
4509 adapter->hw.autoneg = 0;
4510
6921368f 4511 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 4512 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 4513 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4514 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4515 return -EINVAL;
4516 }
4517
96838a40 4518 switch (spddplx) {
1da177e4
LT		 4519 case SPEED_10 + DUPLEX_HALF:
4520 adapter->hw.forced_speed_duplex = e1000_10_half;
4521 break;
4522 case SPEED_10 + DUPLEX_FULL:
4523 adapter->hw.forced_speed_duplex = e1000_10_full;
4524 break;
4525 case SPEED_100 + DUPLEX_HALF:
4526 adapter->hw.forced_speed_duplex = e1000_100_half;
4527 break;
4528 case SPEED_100 + DUPLEX_FULL:
4529 adapter->hw.forced_speed_duplex = e1000_100_full;
4530 break;
4531 case SPEED_1000 + DUPLEX_FULL:
4532 adapter->hw.autoneg = 1;
4533 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4534 break;
4535 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4536 default:
2648345f 4537 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4538 return -EINVAL;
4539 }
4540 return 0;
4541}
4542
b6a1d5f8 4543#ifdef CONFIG_PM
0f15a8fa
JK		 4544/* Save/restore 16 or 64 dwords of PCI config space depending on which
4545 * bus we're on (PCI(X) vs. PCI-E)
2f82665f
JB		 4546 */
4547#define PCIE_CONFIG_SPACE_LEN 256
4548#define PCI_CONFIG_SPACE_LEN 64
4549static int
4550e1000_pci_save_state(struct e1000_adapter *adapter)
4551{
4552 struct pci_dev *dev = adapter->pdev;
4553 int size;
4554 int i;
0f15a8fa 4555
2f82665f
JB		 4556 if (adapter->hw.mac_type >= e1000_82571)
4557 size = PCIE_CONFIG_SPACE_LEN;
4558 else
4559 size = PCI_CONFIG_SPACE_LEN;
4560
4561 WARN_ON(adapter->config_space != NULL);
4562
4563 adapter->config_space = kmalloc(size, GFP_KERNEL);
4564 if (!adapter->config_space) {
4565 DPRINTK(PROBE, ERR, "unable to allocate %d bytes\n", size);
4566 return -ENOMEM;
4567 }
4568 for (i = 0; i < (size / 4); i++)
4569 pci_read_config_dword(dev, i * 4, &adapter->config_space[i]);
4570 return 0;
4571}
4572
4573static void
4574e1000_pci_restore_state(struct e1000_adapter *adapter)
4575{
4576 struct pci_dev *dev = adapter->pdev;
4577 int size;
4578 int i;
0f15a8fa 4579
2f82665f
JB		 4580 if (adapter->config_space == NULL)
4581 return;
0f15a8fa 4582
2f82665f
JB		 4583 if (adapter->hw.mac_type >= e1000_82571)
4584 size = PCIE_CONFIG_SPACE_LEN;
4585 else
4586 size = PCI_CONFIG_SPACE_LEN;
4587 for (i = 0; i < (size / 4); i++)
4588 pci_write_config_dword(dev, i * 4, adapter->config_space[i]);
4589 kfree(adapter->config_space);
4590 adapter->config_space = NULL;
4591 return;
4592}
4593#endif /* CONFIG_PM */
4594
1da177e4 4595static int
829ca9a3 4596e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4597{
4598 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4599 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4600 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4 4601 uint32_t wufc = adapter->wol;
6fdfef16 4602#ifdef CONFIG_PM
240b1710 4603 int retval = 0;
6fdfef16 4604#endif
1da177e4
LT		 4605
4606 netif_device_detach(netdev);
4607
2db10a08
AK		 4608 if (netif_running(netdev)) {
4609 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 4610 e1000_down(adapter);
2db10a08 4611 }
1da177e4 4612
2f82665f 4613#ifdef CONFIG_PM
0f15a8fa
JK		 4614 /* Implement our own version of pci_save_state(pdev) because pci-
4615 * express adapters have 256-byte config spaces. */
2f82665f
JB		 4616 retval = e1000_pci_save_state(adapter);
4617 if (retval)
4618 return retval;
4619#endif
4620
1da177e4 4621 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 4622 if (status & E1000_STATUS_LU)
1da177e4
LT		 4623 wufc &= ~E1000_WUFC_LNKC;
4624
96838a40 4625 if (wufc) {
1da177e4
LT		 4626 e1000_setup_rctl(adapter);
4627 e1000_set_multi(netdev);
4628
4629 /* turn on all-multi mode if wake on multicast is enabled */
96838a40 4630 if (adapter->wol & E1000_WUFC_MC) {
1da177e4
LT		 4631 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4632 rctl |= E1000_RCTL_MPE;
4633 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4634 }
4635
96838a40 4636 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 4637 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4638 /* advertise wake from D3Cold */
4639 #define E1000_CTRL_ADVD3WUC 0x00100000
4640 /* phy power management enable */
4641 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4642 ctrl |= E1000_CTRL_ADVD3WUC |
4643 E1000_CTRL_EN_PHY_PWR_MGMT;
4644 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4645 }
4646
96838a40 4647 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 4648 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4649 /* keep the laser running in D3 */
4650 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4651 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4652 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4653 }
4654
2d7edb92
MC		 4655 /* Allow time for pending master requests to run */
4656 e1000_disable_pciex_master(&adapter->hw);
4657
1da177e4
LT		 4658 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4659 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 4660 pci_enable_wake(pdev, PCI_D3hot, 1);
4661 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4662 } else {
4663 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4664 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 4665 pci_enable_wake(pdev, PCI_D3hot, 0);
4666 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4667 }
4668
cd94dd0b 4669 /* FIXME: this code is incorrect for PCI Express */
96838a40 4670 if (adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 4671 adapter->hw.mac_type != e1000_ich8lan &&
1da177e4
LT		 4672 adapter->hw.media_type == e1000_media_type_copper) {
4673 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 4674 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 4675 manc |= E1000_MANC_ARP_EN;
4676 E1000_WRITE_REG(&adapter->hw, MANC, manc);
d0e027db
AK		 4677 pci_enable_wake(pdev, PCI_D3hot, 1);
4678 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4679 }
4680 }
4681
cd94dd0b
AK		 4682 if (adapter->hw.phy_type == e1000_phy_igp_3)
4683 e1000_phy_powerdown_workaround(&adapter->hw);
4684
b55ccb35
JK		 4685 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4686 * would have already happened in close and is redundant. */
4687 e1000_release_hw_control(adapter);
2d7edb92 4688
1da177e4 4689 pci_disable_device(pdev);
240b1710 4690
d0e027db 4691 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4692
4693 return 0;
4694}
4695
2f82665f 4696#ifdef CONFIG_PM
1da177e4
LT		 4697static int
4698e1000_resume(struct pci_dev *pdev)
4699{
4700 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4701 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4702 uint32_t manc, ret_val;
1da177e4 4703
d0e027db 4704 pci_set_power_state(pdev, PCI_D0);
2f82665f 4705 e1000_pci_restore_state(adapter);
2b02893e 4706 ret_val = pci_enable_device(pdev);
a4cb847d 4707 pci_set_master(pdev);
1da177e4 4708
d0e027db
AK		 4709 pci_enable_wake(pdev, PCI_D3hot, 0);
4710 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4711
4712 e1000_reset(adapter);
4713 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4714
96838a40 4715 if (netif_running(netdev))
1da177e4
LT		 4716 e1000_up(adapter);
4717
4718 netif_device_attach(netdev);
4719
cd94dd0b 4720 /* FIXME: this code is incorrect for PCI Express */
96838a40 4721 if (adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 4722 adapter->hw.mac_type != e1000_ich8lan &&
1da177e4
LT		 4723 adapter->hw.media_type == e1000_media_type_copper) {
4724 manc = E1000_READ_REG(&adapter->hw, MANC);
4725 manc &= ~(E1000_MANC_ARP_EN);
4726 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4727 }
4728
b55ccb35
JK		 4729 /* If the controller is 82573 and f/w is AMT, do not set
4730 * DRV_LOAD until the interface is up. For all other cases,
4731 * let the f/w know that the h/w is now under the control
4732 * of the driver. */
4733 if (adapter->hw.mac_type != e1000_82573 ||
4734 !e1000_check_mng_mode(&adapter->hw))
4735 e1000_get_hw_control(adapter);
2d7edb92 4736
1da177e4
LT		 4737 return 0;
4738}
4739#endif
c653e635
AK		 4740
4741static void e1000_shutdown(struct pci_dev *pdev)
4742{
4743 e1000_suspend(pdev, PMSG_SUSPEND);
4744}
4745
1da177e4
LT		 4746#ifdef CONFIG_NET_POLL_CONTROLLER
4747/*
4748 * Polling 'interrupt' - used by things like netconsole to send skbs
4749 * without having to re-enable interrupts. It's not called while
4750 * the interrupt routine is executing.
4751 */
4752static void
2648345f 4753e1000_netpoll(struct net_device *netdev)
1da177e4 4754{
60490fe0 4755 struct e1000_adapter *adapter = netdev_priv(netdev);
d3d9e484 4756
1da177e4
LT		 4757 disable_irq(adapter->pdev->irq);
4758 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4759 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4760#ifndef CONFIG_E1000_NAPI
4761 adapter->clean_rx(adapter, adapter->rx_ring);
4762#endif
1da177e4
LT		 4763 enable_irq(adapter->pdev->irq);
4764}
4765#endif
4766
9026729b
AK		 4767/**
4768 * e1000_io_error_detected - called when PCI error is detected
4769 * @pdev: Pointer to PCI device
4770 * @state: The current pci conneection state
4771 *
4772 * This function is called after a PCI bus error affecting
4773 * this device has been detected.
4774 */
4775static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4776{
4777 struct net_device *netdev = pci_get_drvdata(pdev);
4778 struct e1000_adapter *adapter = netdev->priv;
4779
4780 netif_device_detach(netdev);
4781
4782 if (netif_running(netdev))
4783 e1000_down(adapter);
4784
4785 /* Request a slot slot reset. */
4786 return PCI_ERS_RESULT_NEED_RESET;
4787}
4788
4789/**
4790 * e1000_io_slot_reset - called after the pci bus has been reset.
4791 * @pdev: Pointer to PCI device
4792 *
4793 * Restart the card from scratch, as if from a cold-boot. Implementation
4794 * resembles the first-half of the e1000_resume routine.
4795 */
4796static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
4797{
4798 struct net_device *netdev = pci_get_drvdata(pdev);
4799 struct e1000_adapter *adapter = netdev->priv;
4800
4801 if (pci_enable_device(pdev)) {
4802 printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n");
4803 return PCI_ERS_RESULT_DISCONNECT;
4804 }
4805 pci_set_master(pdev);
4806
4807 pci_enable_wake(pdev, 3, 0);
4808 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
4809
4810 /* Perform card reset only on one instance of the card */
4811 if (PCI_FUNC (pdev->devfn) != 0)
4812 return PCI_ERS_RESULT_RECOVERED;
4813
4814 e1000_reset(adapter);
4815 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4816
4817 return PCI_ERS_RESULT_RECOVERED;
4818}
4819
4820/**
4821 * e1000_io_resume - called when traffic can start flowing again.
4822 * @pdev: Pointer to PCI device
4823 *
4824 * This callback is called when the error recovery driver tells us that
4825 * its OK to resume normal operation. Implementation resembles the
4826 * second-half of the e1000_resume routine.
4827 */
4828static void e1000_io_resume(struct pci_dev *pdev)
4829{
4830 struct net_device *netdev = pci_get_drvdata(pdev);
4831 struct e1000_adapter *adapter = netdev->priv;
4832 uint32_t manc, swsm;
4833
4834 if (netif_running(netdev)) {
4835 if (e1000_up(adapter)) {
4836 printk("e1000: can't bring device back up after reset\n");
4837 return;
4838 }
4839 }
4840
4841 netif_device_attach(netdev);
4842
4843 if (adapter->hw.mac_type >= e1000_82540 &&
4844 adapter->hw.media_type == e1000_media_type_copper) {
4845 manc = E1000_READ_REG(&adapter->hw, MANC);
4846 manc &= ~(E1000_MANC_ARP_EN);
4847 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4848 }
4849
4850 switch (adapter->hw.mac_type) {
4851 case e1000_82573:
4852 swsm = E1000_READ_REG(&adapter->hw, SWSM);
4853 E1000_WRITE_REG(&adapter->hw, SWSM,
4854 swsm | E1000_SWSM_DRV_LOAD);
4855 break;
4856 default:
4857 break;
4858 }
4859
4860 if (netif_running(netdev))
4861 mod_timer(&adapter->watchdog_timer, jiffies);
4862}
4863
1da177e4 4864/* e1000_main.c */
Linux kernel - Deliverables
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