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net/ipv4/tcp.c: Fix use of PULLHUP instead of POLLHUP in comments.
[deliverable/linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
d0bb53e1 30#include <net/ip6_checksum.h>
1da177e4 31
1da177e4 32char e1000_driver_name[] = "e1000";
3ad2cc67 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 34#ifndef CONFIG_E1000_NAPI
35#define DRIVERNAPI
36#else
37#define DRIVERNAPI "-NAPI"
38#endif
7e721579 39#define DRV_VERSION "7.3.20-k2"DRIVERNAPI
abec42a4
SH		 40const char e1000_driver_version[] = DRV_VERSION;
41static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
1da177e4
LT		 42
43/* e1000_pci_tbl - PCI Device ID Table
44 *
45 * Last entry must be all 0s
46 *
47 * Macro expands to...
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */
50static struct pci_device_id e1000_pci_tbl[] = {
51 INTEL_E1000_ETHERNET_DEVICE(0x1000),
52 INTEL_E1000_ETHERNET_DEVICE(0x1001),
53 INTEL_E1000_ETHERNET_DEVICE(0x1004),
54 INTEL_E1000_ETHERNET_DEVICE(0x1008),
55 INTEL_E1000_ETHERNET_DEVICE(0x1009),
56 INTEL_E1000_ETHERNET_DEVICE(0x100C),
57 INTEL_E1000_ETHERNET_DEVICE(0x100D),
58 INTEL_E1000_ETHERNET_DEVICE(0x100E),
59 INTEL_E1000_ETHERNET_DEVICE(0x100F),
60 INTEL_E1000_ETHERNET_DEVICE(0x1010),
61 INTEL_E1000_ETHERNET_DEVICE(0x1011),
62 INTEL_E1000_ETHERNET_DEVICE(0x1012),
63 INTEL_E1000_ETHERNET_DEVICE(0x1013),
64 INTEL_E1000_ETHERNET_DEVICE(0x1014),
65 INTEL_E1000_ETHERNET_DEVICE(0x1015),
66 INTEL_E1000_ETHERNET_DEVICE(0x1016),
67 INTEL_E1000_ETHERNET_DEVICE(0x1017),
68 INTEL_E1000_ETHERNET_DEVICE(0x1018),
69 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 70 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 71 INTEL_E1000_ETHERNET_DEVICE(0x101D),
72 INTEL_E1000_ETHERNET_DEVICE(0x101E),
73 INTEL_E1000_ETHERNET_DEVICE(0x1026),
74 INTEL_E1000_ETHERNET_DEVICE(0x1027),
75 INTEL_E1000_ETHERNET_DEVICE(0x1028),
76 INTEL_E1000_ETHERNET_DEVICE(0x1075),
77 INTEL_E1000_ETHERNET_DEVICE(0x1076),
78 INTEL_E1000_ETHERNET_DEVICE(0x1077),
79 INTEL_E1000_ETHERNET_DEVICE(0x1078),
80 INTEL_E1000_ETHERNET_DEVICE(0x1079),
81 INTEL_E1000_ETHERNET_DEVICE(0x107A),
82 INTEL_E1000_ETHERNET_DEVICE(0x107B),
83 INTEL_E1000_ETHERNET_DEVICE(0x107C),
84 INTEL_E1000_ETHERNET_DEVICE(0x108A),
b7ee49db 85 INTEL_E1000_ETHERNET_DEVICE(0x1099),
b7ee49db 86 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
1da177e4
LT		 87 /* required last entry */
88 {0,}
89};
90
91MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
92
35574764
NN		 93int e1000_up(struct e1000_adapter *adapter);
94void e1000_down(struct e1000_adapter *adapter);
95void e1000_reinit_locked(struct e1000_adapter *adapter);
96void e1000_reset(struct e1000_adapter *adapter);
406874a7 97int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx);
35574764
NN		 98int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
99int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
100void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
101void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67 102static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
35574764 103 struct e1000_tx_ring *txdr);
3ad2cc67 104static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
35574764 105 struct e1000_rx_ring *rxdr);
3ad2cc67 106static void e1000_free_tx_resources(struct e1000_adapter *adapter,
35574764 107 struct e1000_tx_ring *tx_ring);
3ad2cc67 108static void e1000_free_rx_resources(struct e1000_adapter *adapter,
35574764
NN		 109 struct e1000_rx_ring *rx_ring);
110void e1000_update_stats(struct e1000_adapter *adapter);
1da177e4
LT		 111
112static int e1000_init_module(void);
113static void e1000_exit_module(void);
114static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
115static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 116static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 117static int e1000_sw_init(struct e1000_adapter *adapter);
118static int e1000_open(struct net_device *netdev);
119static int e1000_close(struct net_device *netdev);
120static void e1000_configure_tx(struct e1000_adapter *adapter);
121static void e1000_configure_rx(struct e1000_adapter *adapter);
122static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 123static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
124static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
125static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
126 struct e1000_tx_ring *tx_ring);
127static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
128 struct e1000_rx_ring *rx_ring);
db0ce50d 129static void e1000_set_rx_mode(struct net_device *netdev);
1da177e4
LT		 130static void e1000_update_phy_info(unsigned long data);
131static void e1000_watchdog(unsigned long data);
1da177e4
LT		 132static void e1000_82547_tx_fifo_stall(unsigned long data);
133static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
134static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
135static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
136static int e1000_set_mac(struct net_device *netdev, void *p);
7d12e780 137static irqreturn_t e1000_intr(int irq, void *data);
9ac98284 138static irqreturn_t e1000_intr_msi(int irq, void *data);
c3033b01
JP		 139static bool e1000_clean_tx_irq(struct e1000_adapter *adapter,
140 struct e1000_tx_ring *tx_ring);
1da177e4 141#ifdef CONFIG_E1000_NAPI
bea3348e 142static int e1000_clean(struct napi_struct *napi, int budget);
c3033b01
JP		 143static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
144 struct e1000_rx_ring *rx_ring,
145 int *work_done, int work_to_do);
146static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
147 struct e1000_rx_ring *rx_ring,
148 int *work_done, int work_to_do);
1da177e4 149#else
c3033b01
JP		 150static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
151 struct e1000_rx_ring *rx_ring);
152static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
153 struct e1000_rx_ring *rx_ring);
1da177e4 154#endif
581d708e 155static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 156 struct e1000_rx_ring *rx_ring,
157 int cleaned_count);
581d708e 158static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 159 struct e1000_rx_ring *rx_ring,
160 int cleaned_count);
1da177e4
LT		 161static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
162static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
163 int cmd);
1da177e4
LT		 164static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
165static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
166static void e1000_tx_timeout(struct net_device *dev);
65f27f38 167static void e1000_reset_task(struct work_struct *work);
1da177e4 168static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 169static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
170 struct sk_buff *skb);
1da177e4
LT		 171
172static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
406874a7
JP		 173static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid);
174static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid);
1da177e4
LT		 175static void e1000_restore_vlan(struct e1000_adapter *adapter);
176
977e74b5 177static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
6fdfef16 178#ifdef CONFIG_PM
1da177e4
LT		 179static int e1000_resume(struct pci_dev *pdev);
180#endif
c653e635 181static void e1000_shutdown(struct pci_dev *pdev);
1da177e4
LT		 182
183#ifdef CONFIG_NET_POLL_CONTROLLER
184/* for netdump / net console */
185static void e1000_netpoll (struct net_device *netdev);
186#endif
187
1f753861
JB		 188#define COPYBREAK_DEFAULT 256
189static unsigned int copybreak __read_mostly = COPYBREAK_DEFAULT;
190module_param(copybreak, uint, 0644);
191MODULE_PARM_DESC(copybreak,
192 "Maximum size of packet that is copied to a new buffer on receive");
193
9026729b
AK		 194static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
195 pci_channel_state_t state);
196static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
197static void e1000_io_resume(struct pci_dev *pdev);
198
199static struct pci_error_handlers e1000_err_handler = {
200 .error_detected = e1000_io_error_detected,
201 .slot_reset = e1000_io_slot_reset,
202 .resume = e1000_io_resume,
203};
24025e4e 204
1da177e4
LT		 205static struct pci_driver e1000_driver = {
206 .name = e1000_driver_name,
207 .id_table = e1000_pci_tbl,
208 .probe = e1000_probe,
209 .remove = __devexit_p(e1000_remove),
c4e24f01 210#ifdef CONFIG_PM
1da177e4 211 /* Power Managment Hooks */
1da177e4 212 .suspend = e1000_suspend,
c653e635 213 .resume = e1000_resume,
1da177e4 214#endif
9026729b
AK		 215 .shutdown = e1000_shutdown,
216 .err_handler = &e1000_err_handler
1da177e4
LT		 217};
218
219MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
220MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
221MODULE_LICENSE("GPL");
222MODULE_VERSION(DRV_VERSION);
223
224static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
225module_param(debug, int, 0);
226MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
227
228/**
229 * e1000_init_module - Driver Registration Routine
230 *
231 * e1000_init_module is the first routine called when the driver is
232 * loaded. All it does is register with the PCI subsystem.
233 **/
234
235static int __init
236e1000_init_module(void)
237{
238 int ret;
239 printk(KERN_INFO "%s - version %s\n",
240 e1000_driver_string, e1000_driver_version);
241
242 printk(KERN_INFO "%s\n", e1000_copyright);
243
29917620 244 ret = pci_register_driver(&e1000_driver);
1f753861
JB		 245 if (copybreak != COPYBREAK_DEFAULT) {
246 if (copybreak == 0)
247 printk(KERN_INFO "e1000: copybreak disabled\n");
248 else
249 printk(KERN_INFO "e1000: copybreak enabled for "
250 "packets <= %u bytes\n", copybreak);
251 }
1da177e4
LT		 252 return ret;
253}
254
255module_init(e1000_init_module);
256
257/**
258 * e1000_exit_module - Driver Exit Cleanup Routine
259 *
260 * e1000_exit_module is called just before the driver is removed
261 * from memory.
262 **/
263
264static void __exit
265e1000_exit_module(void)
266{
1da177e4
LT		 267 pci_unregister_driver(&e1000_driver);
268}
269
270module_exit(e1000_exit_module);
271
2db10a08
AK		 272static int e1000_request_irq(struct e1000_adapter *adapter)
273{
274 struct net_device *netdev = adapter->netdev;
3e18826c 275 irq_handler_t handler = e1000_intr;
e94bd23f
AK		 276 int irq_flags = IRQF_SHARED;
277 int err;
2db10a08 278
9ac98284 279 if (adapter->hw.mac_type >= e1000_82571) {
e94bd23f
AK		 280 adapter->have_msi = !pci_enable_msi(adapter->pdev);
281 if (adapter->have_msi) {
3e18826c 282 handler = e1000_intr_msi;
e94bd23f 283 irq_flags = 0;
2db10a08
AK		 284 }
285 }
e94bd23f
AK		 286
287 err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name,
288 netdev);
289 if (err) {
290 if (adapter->have_msi)
291 pci_disable_msi(adapter->pdev);
2db10a08
AK		 292 DPRINTK(PROBE, ERR,
293 "Unable to allocate interrupt Error: %d\n", err);
e94bd23f 294 }
2db10a08
AK		 295
296 return err;
297}
298
299static void e1000_free_irq(struct e1000_adapter *adapter)
300{
301 struct net_device *netdev = adapter->netdev;
302
303 free_irq(adapter->pdev->irq, netdev);
304
2db10a08
AK		 305 if (adapter->have_msi)
306 pci_disable_msi(adapter->pdev);
2db10a08
AK		 307}
308
1da177e4
LT		 309/**
310 * e1000_irq_disable - Mask off interrupt generation on the NIC
311 * @adapter: board private structure
312 **/
313
e619d523 314static void
1da177e4
LT		 315e1000_irq_disable(struct e1000_adapter *adapter)
316{
1da177e4
LT		 317 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
318 E1000_WRITE_FLUSH(&adapter->hw);
319 synchronize_irq(adapter->pdev->irq);
320}
321
322/**
323 * e1000_irq_enable - Enable default interrupt generation settings
324 * @adapter: board private structure
325 **/
326
e619d523 327static void
1da177e4
LT		 328e1000_irq_enable(struct e1000_adapter *adapter)
329{
9150b76a
JB		 330 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
331 E1000_WRITE_FLUSH(&adapter->hw);
1da177e4 332}
3ad2cc67
AB		 333
334static void
2d7edb92
MC		 335e1000_update_mng_vlan(struct e1000_adapter *adapter)
336{
337 struct net_device *netdev = adapter->netdev;
406874a7
JP		 338 u16 vid = adapter->hw.mng_cookie.vlan_id;
339 u16 old_vid = adapter->mng_vlan_id;
96838a40 340 if (adapter->vlgrp) {
5c15bdec 341 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
96838a40 342 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 343 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
344 e1000_vlan_rx_add_vid(netdev, vid);
345 adapter->mng_vlan_id = vid;
346 } else
347 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 348
406874a7 349 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) &&
96838a40 350 (vid != old_vid) &&
5c15bdec 351 !vlan_group_get_device(adapter->vlgrp, old_vid))
2d7edb92 352 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 353 } else
354 adapter->mng_vlan_id = vid;
2d7edb92
MC		 355 }
356}
b55ccb35
JK		 357
358/**
359 * e1000_release_hw_control - release control of the h/w to f/w
360 * @adapter: address of board private structure
361 *
362 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
363 * For ASF and Pass Through versions of f/w this means that the
364 * driver is no longer loaded. For AMT version (only with 82573) i
90fb5135 365 * of the f/w this means that the network i/f is closed.
76c224bc 366 *
b55ccb35
JK		 367 **/
368
e619d523 369static void
b55ccb35
JK		 370e1000_release_hw_control(struct e1000_adapter *adapter)
371{
406874a7
JP		 372 u32 ctrl_ext;
373 u32 swsm;
b55ccb35
JK		 374
375 /* Let firmware taken over control of h/w */
376 switch (adapter->hw.mac_type) {
b55ccb35
JK		 377 case e1000_82573:
378 swsm = E1000_READ_REG(&adapter->hw, SWSM);
379 E1000_WRITE_REG(&adapter->hw, SWSM,
380 swsm & ~E1000_SWSM_DRV_LOAD);
31d76442
BA		 381 break;
382 case e1000_82571:
383 case e1000_82572:
384 case e1000_80003es2lan:
cd94dd0b 385 case e1000_ich8lan:
31d76442 386 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
cd94dd0b 387 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
31d76442 388 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
cd94dd0b 389 break;
b55ccb35
JK		 390 default:
391 break;
392 }
393}
394
395/**
396 * e1000_get_hw_control - get control of the h/w from f/w
397 * @adapter: address of board private structure
398 *
399 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
76c224bc
AK		 400 * For ASF and Pass Through versions of f/w this means that
401 * the driver is loaded. For AMT version (only with 82573)
90fb5135 402 * of the f/w this means that the network i/f is open.
76c224bc 403 *
b55ccb35
JK		 404 **/
405
e619d523 406static void
b55ccb35
JK		 407e1000_get_hw_control(struct e1000_adapter *adapter)
408{
406874a7
JP		 409 u32 ctrl_ext;
410 u32 swsm;
90fb5135 411
b55ccb35
JK		 412 /* Let firmware know the driver has taken over */
413 switch (adapter->hw.mac_type) {
b55ccb35
JK		 414 case e1000_82573:
415 swsm = E1000_READ_REG(&adapter->hw, SWSM);
416 E1000_WRITE_REG(&adapter->hw, SWSM,
417 swsm | E1000_SWSM_DRV_LOAD);
418 break;
31d76442
BA		 419 case e1000_82571:
420 case e1000_82572:
421 case e1000_80003es2lan:
cd94dd0b 422 case e1000_ich8lan:
31d76442
BA		 423 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
424 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
425 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
cd94dd0b 426 break;
b55ccb35
JK		 427 default:
428 break;
429 }
430}
431
0fccd0e9
JG		 432static void
433e1000_init_manageability(struct e1000_adapter *adapter)
434{
435 if (adapter->en_mng_pt) {
406874a7 436 u32 manc = E1000_READ_REG(&adapter->hw, MANC);
0fccd0e9
JG		 437
438 /* disable hardware interception of ARP */
439 manc &= ~(E1000_MANC_ARP_EN);
440
441 /* enable receiving management packets to the host */
442 /* this will probably generate destination unreachable messages
443 * from the host OS, but the packets will be handled on SMBUS */
444 if (adapter->hw.has_manc2h) {
406874a7 445 u32 manc2h = E1000_READ_REG(&adapter->hw, MANC2H);
0fccd0e9
JG		 446
447 manc |= E1000_MANC_EN_MNG2HOST;
448#define E1000_MNG2HOST_PORT_623 (1 << 5)
449#define E1000_MNG2HOST_PORT_664 (1 << 6)
450 manc2h |= E1000_MNG2HOST_PORT_623;
451 manc2h |= E1000_MNG2HOST_PORT_664;
452 E1000_WRITE_REG(&adapter->hw, MANC2H, manc2h);
453 }
454
455 E1000_WRITE_REG(&adapter->hw, MANC, manc);
456 }
457}
458
459static void
460e1000_release_manageability(struct e1000_adapter *adapter)
461{
462 if (adapter->en_mng_pt) {
406874a7 463 u32 manc = E1000_READ_REG(&adapter->hw, MANC);
0fccd0e9
JG		 464
465 /* re-enable hardware interception of ARP */
466 manc |= E1000_MANC_ARP_EN;
467
468 if (adapter->hw.has_manc2h)
469 manc &= ~E1000_MANC_EN_MNG2HOST;
470
471 /* don't explicitly have to mess with MANC2H since
472 * MANC has an enable disable that gates MANC2H */
473
474 E1000_WRITE_REG(&adapter->hw, MANC, manc);
475 }
476}
477
e0aac5a2
AK		 478/**
479 * e1000_configure - configure the hardware for RX and TX
480 * @adapter = private board structure
481 **/
482static void e1000_configure(struct e1000_adapter *adapter)
1da177e4
LT		 483{
484 struct net_device *netdev = adapter->netdev;
2db10a08 485 int i;
1da177e4 486
db0ce50d 487 e1000_set_rx_mode(netdev);
1da177e4
LT		 488
489 e1000_restore_vlan(adapter);
0fccd0e9 490 e1000_init_manageability(adapter);
1da177e4
LT		 491
492 e1000_configure_tx(adapter);
493 e1000_setup_rctl(adapter);
494 e1000_configure_rx(adapter);
72d64a43
JK		 495 /* call E1000_DESC_UNUSED which always leaves
496 * at least 1 descriptor unused to make sure
497 * next_to_use != next_to_clean */
f56799ea 498 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 499 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 500 adapter->alloc_rx_buf(adapter, ring,
501 E1000_DESC_UNUSED(ring));
f56799ea 502 }
1da177e4 503
7bfa4816 504 adapter->tx_queue_len = netdev->tx_queue_len;
e0aac5a2
AK		 505}
506
507int e1000_up(struct e1000_adapter *adapter)
508{
509 /* hardware has been reset, we need to reload some things */
510 e1000_configure(adapter);
511
512 clear_bit(__E1000_DOWN, &adapter->flags);
7bfa4816 513
1da177e4 514#ifdef CONFIG_E1000_NAPI
bea3348e 515 napi_enable(&adapter->napi);
1da177e4 516#endif
5de55624
MC		 517 e1000_irq_enable(adapter);
518
79f3d399
JB		 519 /* fire a link change interrupt to start the watchdog */
520 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1da177e4
LT		 521 return 0;
522}
523
79f05bf0
AK		 524/**
525 * e1000_power_up_phy - restore link in case the phy was powered down
526 * @adapter: address of board private structure
527 *
528 * The phy may be powered down to save power and turn off link when the
529 * driver is unloaded and wake on lan is not enabled (among others)
530 * *** this routine MUST be followed by a call to e1000_reset ***
531 *
532 **/
533
d658266e 534void e1000_power_up_phy(struct e1000_adapter *adapter)
79f05bf0 535{
406874a7 536 u16 mii_reg = 0;
79f05bf0
AK		 537
538 /* Just clear the power down bit to wake the phy back up */
539 if (adapter->hw.media_type == e1000_media_type_copper) {
540 /* according to the manual, the phy will retain its
541 * settings across a power-down/up cycle */
542 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
543 mii_reg &= ~MII_CR_POWER_DOWN;
544 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
545 }
546}
547
548static void e1000_power_down_phy(struct e1000_adapter *adapter)
549{
61c2505f 550 /* Power down the PHY so no link is implied when interface is down *
c3033b01 551 * The PHY cannot be powered down if any of the following is true *
79f05bf0
AK		 552 * (a) WoL is enabled
553 * (b) AMT is active
554 * (c) SoL/IDER session is active */
555 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
61c2505f 556 adapter->hw.media_type == e1000_media_type_copper) {
406874a7 557 u16 mii_reg = 0;
61c2505f
BA		 558
559 switch (adapter->hw.mac_type) {
560 case e1000_82540:
561 case e1000_82545:
562 case e1000_82545_rev_3:
563 case e1000_82546:
564 case e1000_82546_rev_3:
565 case e1000_82541:
566 case e1000_82541_rev_2:
567 case e1000_82547:
568 case e1000_82547_rev_2:
569 if (E1000_READ_REG(&adapter->hw, MANC) &
570 E1000_MANC_SMBUS_EN)
571 goto out;
572 break;
573 case e1000_82571:
574 case e1000_82572:
575 case e1000_82573:
576 case e1000_80003es2lan:
577 case e1000_ich8lan:
578 if (e1000_check_mng_mode(&adapter->hw) ||
579 e1000_check_phy_reset_block(&adapter->hw))
580 goto out;
581 break;
582 default:
583 goto out;
584 }
79f05bf0
AK		 585 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
586 mii_reg |= MII_CR_POWER_DOWN;
587 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
588 mdelay(1);
589 }
61c2505f
BA		 590out:
591 return;
79f05bf0
AK		 592}
593
1da177e4
LT		 594void
595e1000_down(struct e1000_adapter *adapter)
596{
597 struct net_device *netdev = adapter->netdev;
598
1314bbf3
AK		 599 /* signal that we're down so the interrupt handler does not
600 * reschedule our watchdog timer */
601 set_bit(__E1000_DOWN, &adapter->flags);
602
e0aac5a2 603#ifdef CONFIG_E1000_NAPI
bea3348e 604 napi_disable(&adapter->napi);
e0aac5a2 605#endif
1da177e4 606 e1000_irq_disable(adapter);
c1605eb3 607
1da177e4
LT		 608 del_timer_sync(&adapter->tx_fifo_stall_timer);
609 del_timer_sync(&adapter->watchdog_timer);
610 del_timer_sync(&adapter->phy_info_timer);
611
7bfa4816 612 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 613 adapter->link_speed = 0;
614 adapter->link_duplex = 0;
615 netif_carrier_off(netdev);
616 netif_stop_queue(netdev);
617
618 e1000_reset(adapter);
581d708e
MC		 619 e1000_clean_all_tx_rings(adapter);
620 e1000_clean_all_rx_rings(adapter);
1da177e4 621}
1da177e4 622
2db10a08
AK		 623void
624e1000_reinit_locked(struct e1000_adapter *adapter)
625{
626 WARN_ON(in_interrupt());
627 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
628 msleep(1);
629 e1000_down(adapter);
630 e1000_up(adapter);
631 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 632}
633
634void
635e1000_reset(struct e1000_adapter *adapter)
636{
406874a7
JP		 637 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
638 u16 fc_high_water_mark = E1000_FC_HIGH_DIFF;
c3033b01 639 bool legacy_pba_adjust = false;
1da177e4
LT		 640
641 /* Repartition Pba for greater than 9k mtu
642 * To take effect CTRL.RST is required.
643 */
644
2d7edb92 645 switch (adapter->hw.mac_type) {
018ea44e
BA		 646 case e1000_82542_rev2_0:
647 case e1000_82542_rev2_1:
648 case e1000_82543:
649 case e1000_82544:
650 case e1000_82540:
651 case e1000_82541:
652 case e1000_82541_rev_2:
c3033b01 653 legacy_pba_adjust = true;
018ea44e
BA		 654 pba = E1000_PBA_48K;
655 break;
656 case e1000_82545:
657 case e1000_82545_rev_3:
658 case e1000_82546:
659 case e1000_82546_rev_3:
660 pba = E1000_PBA_48K;
661 break;
2d7edb92 662 case e1000_82547:
0e6ef3e0 663 case e1000_82547_rev_2:
c3033b01 664 legacy_pba_adjust = true;
2d7edb92
MC		 665 pba = E1000_PBA_30K;
666 break;
868d5309
MC		 667 case e1000_82571:
668 case e1000_82572:
6418ecc6 669 case e1000_80003es2lan:
868d5309
MC		 670 pba = E1000_PBA_38K;
671 break;
2d7edb92 672 case e1000_82573:
018ea44e 673 pba = E1000_PBA_20K;
2d7edb92 674 break;
cd94dd0b
AK		 675 case e1000_ich8lan:
676 pba = E1000_PBA_8K;
018ea44e
BA		 677 case e1000_undefined:
678 case e1000_num_macs:
2d7edb92
MC		 679 break;
680 }
681
c3033b01 682 if (legacy_pba_adjust) {
018ea44e
BA		 683 if (adapter->netdev->mtu > E1000_RXBUFFER_8192)
684 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92 685
018ea44e
BA		 686 if (adapter->hw.mac_type == e1000_82547) {
687 adapter->tx_fifo_head = 0;
688 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
689 adapter->tx_fifo_size =
690 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
691 atomic_set(&adapter->tx_fifo_stall, 0);
692 }
693 } else if (adapter->hw.max_frame_size > MAXIMUM_ETHERNET_FRAME_SIZE) {
694 /* adjust PBA for jumbo frames */
695 E1000_WRITE_REG(&adapter->hw, PBA, pba);
696
697 /* To maintain wire speed transmits, the Tx FIFO should be
698 * large enough to accomodate two full transmit packets,
699 * rounded up to the next 1KB and expressed in KB. Likewise,
700 * the Rx FIFO should be large enough to accomodate at least
701 * one full receive packet and is similarly rounded up and
702 * expressed in KB. */
703 pba = E1000_READ_REG(&adapter->hw, PBA);
704 /* upper 16 bits has Tx packet buffer allocation size in KB */
705 tx_space = pba >> 16;
706 /* lower 16 bits has Rx packet buffer allocation size in KB */
707 pba &= 0xffff;
708 /* don't include ethernet FCS because hardware appends/strips */
709 min_rx_space = adapter->netdev->mtu + ENET_HEADER_SIZE +
710 VLAN_TAG_SIZE;
711 min_tx_space = min_rx_space;
712 min_tx_space *= 2;
9099cfb9 713 min_tx_space = ALIGN(min_tx_space, 1024);
018ea44e 714 min_tx_space >>= 10;
9099cfb9 715 min_rx_space = ALIGN(min_rx_space, 1024);
018ea44e
BA		 716 min_rx_space >>= 10;
717
718 /* If current Tx allocation is less than the min Tx FIFO size,
719 * and the min Tx FIFO size is less than the current Rx FIFO
720 * allocation, take space away from current Rx allocation */
721 if (tx_space < min_tx_space &&
722 ((min_tx_space - tx_space) < pba)) {
723 pba = pba - (min_tx_space - tx_space);
724
725 /* PCI/PCIx hardware has PBA alignment constraints */
726 switch (adapter->hw.mac_type) {
727 case e1000_82545 ... e1000_82546_rev_3:
728 pba &= ~(E1000_PBA_8K - 1);
729 break;
730 default:
731 break;
732 }
733
734 /* if short on rx space, rx wins and must trump tx
735 * adjustment or use Early Receive if available */
736 if (pba < min_rx_space) {
737 switch (adapter->hw.mac_type) {
738 case e1000_82573:
739 /* ERT enabled in e1000_configure_rx */
740 break;
741 default:
742 pba = min_rx_space;
743 break;
744 }
745 }
746 }
1da177e4 747 }
2d7edb92 748
1da177e4
LT		 749 E1000_WRITE_REG(&adapter->hw, PBA, pba);
750
751 /* flow control settings */
f11b7f85
JK		 752 /* Set the FC high water mark to 90% of the FIFO size.
753 * Required to clear last 3 LSB */
754 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
cd94dd0b
AK		 755 /* We can't use 90% on small FIFOs because the remainder
756 * would be less than 1 full frame. In this case, we size
757 * it to allow at least a full frame above the high water
758 * mark. */
759 if (pba < E1000_PBA_16K)
760 fc_high_water_mark = (pba * 1024) - 1600;
f11b7f85
JK		 761
762 adapter->hw.fc_high_water = fc_high_water_mark;
763 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 764 if (adapter->hw.mac_type == e1000_80003es2lan)
765 adapter->hw.fc_pause_time = 0xFFFF;
766 else
767 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 768 adapter->hw.fc_send_xon = 1;
769 adapter->hw.fc = adapter->hw.original_fc;
770
2d7edb92 771 /* Allow time for pending master requests to run */
1da177e4 772 e1000_reset_hw(&adapter->hw);
96838a40 773 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 774 E1000_WRITE_REG(&adapter->hw, WUC, 0);
09ae3e88 775
96838a40 776 if (e1000_init_hw(&adapter->hw))
1da177e4 777 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 778 e1000_update_mng_vlan(adapter);
3d5460a0
JB		 779
780 /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */
781 if (adapter->hw.mac_type >= e1000_82544 &&
782 adapter->hw.mac_type <= e1000_82547_rev_2 &&
783 adapter->hw.autoneg == 1 &&
784 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) {
406874a7 785 u32 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3d5460a0
JB		 786 /* clear phy power management bit if we are in gig only mode,
787 * which if enabled will attempt negotiation to 100Mb, which
788 * can cause a loss of link at power off or driver unload */
789 ctrl &= ~E1000_CTRL_SWDPIN3;
790 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
791 }
792
1da177e4
LT		 793 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
794 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
795
796 e1000_reset_adaptive(&adapter->hw);
797 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
9a53a202
AK		 798
799 if (!adapter->smart_power_down &&
800 (adapter->hw.mac_type == e1000_82571 ||
801 adapter->hw.mac_type == e1000_82572)) {
406874a7 802 u16 phy_data = 0;
9a53a202
AK		 803 /* speed up time to link by disabling smart power down, ignore
804 * the return value of this function because there is nothing
805 * different we would do if it failed */
806 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
807 &phy_data);
808 phy_data &= ~IGP02E1000_PM_SPD;
809 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
810 phy_data);
811 }
812
0fccd0e9 813 e1000_release_manageability(adapter);
1da177e4
LT		 814}
815
67b3c27c
AK		 816/**
817 * Dump the eeprom for users having checksum issues
818 **/
b4ea895d 819static void e1000_dump_eeprom(struct e1000_adapter *adapter)
67b3c27c
AK		 820{
821 struct net_device *netdev = adapter->netdev;
822 struct ethtool_eeprom eeprom;
823 const struct ethtool_ops *ops = netdev->ethtool_ops;
824 u8 *data;
825 int i;
826 u16 csum_old, csum_new = 0;
827
828 eeprom.len = ops->get_eeprom_len(netdev);
829 eeprom.offset = 0;
830
831 data = kmalloc(eeprom.len, GFP_KERNEL);
832 if (!data) {
833 printk(KERN_ERR "Unable to allocate memory to dump EEPROM"
834 " data\n");
835 return;
836 }
837
838 ops->get_eeprom(netdev, &eeprom, data);
839
840 csum_old = (data[EEPROM_CHECKSUM_REG * 2]) +
841 (data[EEPROM_CHECKSUM_REG * 2 + 1] << 8);
842 for (i = 0; i < EEPROM_CHECKSUM_REG * 2; i += 2)
843 csum_new += data[i] + (data[i + 1] << 8);
844 csum_new = EEPROM_SUM - csum_new;
845
846 printk(KERN_ERR "/*********************/\n");
847 printk(KERN_ERR "Current EEPROM Checksum : 0x%04x\n", csum_old);
848 printk(KERN_ERR "Calculated : 0x%04x\n", csum_new);
849
850 printk(KERN_ERR "Offset Values\n");
851 printk(KERN_ERR "======== ======\n");
852 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_OFFSET, 16, 1, data, 128, 0);
853
854 printk(KERN_ERR "Include this output when contacting your support "
855 "provider.\n");
856 printk(KERN_ERR "This is not a software error! Something bad "
857 "happened to your hardware or\n");
858 printk(KERN_ERR "EEPROM image. Ignoring this "
859 "problem could result in further problems,\n");
860 printk(KERN_ERR "possibly loss of data, corruption or system hangs!\n");
861 printk(KERN_ERR "The MAC Address will be reset to 00:00:00:00:00:00, "
862 "which is invalid\n");
863 printk(KERN_ERR "and requires you to set the proper MAC "
864 "address manually before continuing\n");
865 printk(KERN_ERR "to enable this network device.\n");
866 printk(KERN_ERR "Please inspect the EEPROM dump and report the issue "
867 "to your hardware vendor\n");
868 printk(KERN_ERR "or Intel Customer Support: linux-nics@intel.com\n");
869 printk(KERN_ERR "/*********************/\n");
870
871 kfree(data);
872}
873
1da177e4
LT		 874/**
875 * e1000_probe - Device Initialization Routine
876 * @pdev: PCI device information struct
877 * @ent: entry in e1000_pci_tbl
878 *
879 * Returns 0 on success, negative on failure
880 *
881 * e1000_probe initializes an adapter identified by a pci_dev structure.
882 * The OS initialization, configuring of the adapter private structure,
883 * and a hardware reset occur.
884 **/
885
886static int __devinit
887e1000_probe(struct pci_dev *pdev,
888 const struct pci_device_id *ent)
889{
890 struct net_device *netdev;
891 struct e1000_adapter *adapter;
2d7edb92 892
1da177e4 893 static int cards_found = 0;
120cd576 894 static int global_quad_port_a = 0; /* global ksp3 port a indication */
2d7edb92 895 int i, err, pci_using_dac;
406874a7
JP		 896 u16 eeprom_data = 0;
897 u16 eeprom_apme_mask = E1000_EEPROM_APME;
0795af57
JP		 898 DECLARE_MAC_BUF(mac);
899
96838a40 900 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 901 return err;
902
cd94dd0b
AK		 903 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
904 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 905 pci_using_dac = 1;
906 } else {
cd94dd0b
AK		 907 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
908 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4 909 E1000_ERR("No usable DMA configuration, aborting\n");
6dd62ab0 910 goto err_dma;
1da177e4
LT		 911 }
912 pci_using_dac = 0;
913 }
914
96838a40 915 if ((err = pci_request_regions(pdev, e1000_driver_name)))
6dd62ab0 916 goto err_pci_reg;
1da177e4
LT		 917
918 pci_set_master(pdev);
919
6dd62ab0 920 err = -ENOMEM;
1da177e4 921 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6dd62ab0 922 if (!netdev)
1da177e4 923 goto err_alloc_etherdev;
1da177e4 924
1da177e4
LT		 925 SET_NETDEV_DEV(netdev, &pdev->dev);
926
927 pci_set_drvdata(pdev, netdev);
60490fe0 928 adapter = netdev_priv(netdev);
1da177e4
LT		 929 adapter->netdev = netdev;
930 adapter->pdev = pdev;
931 adapter->hw.back = adapter;
932 adapter->msg_enable = (1 << debug) - 1;
933
6dd62ab0 934 err = -EIO;
3c34ac36
BH		 935 adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, BAR_0),
936 pci_resource_len(pdev, BAR_0));
6dd62ab0 937 if (!adapter->hw.hw_addr)
1da177e4 938 goto err_ioremap;
1da177e4 939
96838a40
JB		 940 for (i = BAR_1; i <= BAR_5; i++) {
941 if (pci_resource_len(pdev, i) == 0)
1da177e4 942 continue;
96838a40 943 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 944 adapter->hw.io_base = pci_resource_start(pdev, i);
945 break;
946 }
947 }
948
949 netdev->open = &e1000_open;
950 netdev->stop = &e1000_close;
951 netdev->hard_start_xmit = &e1000_xmit_frame;
952 netdev->get_stats = &e1000_get_stats;
db0ce50d 953 netdev->set_rx_mode = &e1000_set_rx_mode;
1da177e4
LT		 954 netdev->set_mac_address = &e1000_set_mac;
955 netdev->change_mtu = &e1000_change_mtu;
956 netdev->do_ioctl = &e1000_ioctl;
957 e1000_set_ethtool_ops(netdev);
958 netdev->tx_timeout = &e1000_tx_timeout;
959 netdev->watchdog_timeo = 5 * HZ;
960#ifdef CONFIG_E1000_NAPI
bea3348e 961 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
1da177e4
LT		 962#endif
963 netdev->vlan_rx_register = e1000_vlan_rx_register;
964 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
965 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
966#ifdef CONFIG_NET_POLL_CONTROLLER
967 netdev->poll_controller = e1000_netpoll;
968#endif
0eb5a34c 969 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1da177e4 970
1da177e4
LT		 971 adapter->bd_number = cards_found;
972
973 /* setup the private structure */
974
96838a40 975 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 976 goto err_sw_init;
977
6dd62ab0 978 err = -EIO;
cd94dd0b
AK		 979 /* Flash BAR mapping must happen after e1000_sw_init
980 * because it depends on mac_type */
981 if ((adapter->hw.mac_type == e1000_ich8lan) &&
982 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
3c34ac36
BH		 983 adapter->hw.flash_address =
984 ioremap(pci_resource_start(pdev, 1),
985 pci_resource_len(pdev, 1));
6dd62ab0 986 if (!adapter->hw.flash_address)
cd94dd0b 987 goto err_flashmap;
cd94dd0b
AK		 988 }
989
6dd62ab0 990 if (e1000_check_phy_reset_block(&adapter->hw))
2d7edb92
MC		 991 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
992
96838a40 993 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 994 netdev->features = NETIF_F_SG |
995 NETIF_F_HW_CSUM |
996 NETIF_F_HW_VLAN_TX |
997 NETIF_F_HW_VLAN_RX |
998 NETIF_F_HW_VLAN_FILTER;
cd94dd0b
AK		 999 if (adapter->hw.mac_type == e1000_ich8lan)
1000 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
1da177e4
LT		 1001 }
1002
96838a40 1003 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 1004 (adapter->hw.mac_type != e1000_82547))
1005 netdev->features |= NETIF_F_TSO;
2d7edb92 1006
96838a40 1007 if (adapter->hw.mac_type > e1000_82547_rev_2)
87ca4e5b 1008 netdev->features |= NETIF_F_TSO6;
96838a40 1009 if (pci_using_dac)
1da177e4
LT		 1010 netdev->features |= NETIF_F_HIGHDMA;
1011
76c224bc
AK		 1012 netdev->features |= NETIF_F_LLTX;
1013
2d7edb92
MC		 1014 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
1015
cd94dd0b 1016 /* initialize eeprom parameters */
cd94dd0b
AK		 1017 if (e1000_init_eeprom_params(&adapter->hw)) {
1018 E1000_ERR("EEPROM initialization failed\n");
6dd62ab0 1019 goto err_eeprom;
cd94dd0b
AK		 1020 }
1021
96838a40 1022 /* before reading the EEPROM, reset the controller to
1da177e4 1023 * put the device in a known good starting state */
96838a40 1024
1da177e4
LT		 1025 e1000_reset_hw(&adapter->hw);
1026
1027 /* make sure the EEPROM is good */
96838a40 1028 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4 1029 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
67b3c27c
AK		 1030 e1000_dump_eeprom(adapter);
1031 /*
1032 * set MAC address to all zeroes to invalidate and temporary
1033 * disable this device for the user. This blocks regular
1034 * traffic while still permitting ethtool ioctls from reaching
1035 * the hardware as well as allowing the user to run the
1036 * interface after manually setting a hw addr using
1037 * `ip set address`
1038 */
1039 memset(adapter->hw.mac_addr, 0, netdev->addr_len);
1040 } else {
1041 /* copy the MAC address out of the EEPROM */
1042 if (e1000_read_mac_addr(&adapter->hw))
1043 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
1da177e4 1044 }
67b3c27c 1045 /* don't block initalization here due to bad MAC address */
1da177e4 1046 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 1047 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 1048
67b3c27c 1049 if (!is_valid_ether_addr(netdev->perm_addr))
1da177e4 1050 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
1da177e4 1051
1da177e4
LT		 1052 e1000_get_bus_info(&adapter->hw);
1053
1054 init_timer(&adapter->tx_fifo_stall_timer);
1055 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
1056 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
1057
1058 init_timer(&adapter->watchdog_timer);
1059 adapter->watchdog_timer.function = &e1000_watchdog;
1060 adapter->watchdog_timer.data = (unsigned long) adapter;
1061
1da177e4
LT		 1062 init_timer(&adapter->phy_info_timer);
1063 adapter->phy_info_timer.function = &e1000_update_phy_info;
1064 adapter->phy_info_timer.data = (unsigned long) adapter;
1065
65f27f38 1066 INIT_WORK(&adapter->reset_task, e1000_reset_task);
1da177e4 1067
1da177e4
LT		 1068 e1000_check_options(adapter);
1069
1070 /* Initial Wake on LAN setting
1071 * If APM wake is enabled in the EEPROM,
1072 * enable the ACPI Magic Packet filter
1073 */
1074
96838a40 1075 switch (adapter->hw.mac_type) {
1da177e4
LT		 1076 case e1000_82542_rev2_0:
1077 case e1000_82542_rev2_1:
1078 case e1000_82543:
1079 break;
1080 case e1000_82544:
1081 e1000_read_eeprom(&adapter->hw,
1082 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1083 eeprom_apme_mask = E1000_EEPROM_82544_APM;
1084 break;
cd94dd0b
AK		 1085 case e1000_ich8lan:
1086 e1000_read_eeprom(&adapter->hw,
1087 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
1088 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
1089 break;
1da177e4
LT		 1090 case e1000_82546:
1091 case e1000_82546_rev_3:
fd803241 1092 case e1000_82571:
6418ecc6 1093 case e1000_80003es2lan:
96838a40 1094 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 1095 e1000_read_eeprom(&adapter->hw,
1096 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1097 break;
1098 }
1099 /* Fall Through */
1100 default:
1101 e1000_read_eeprom(&adapter->hw,
1102 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1103 break;
1104 }
96838a40 1105 if (eeprom_data & eeprom_apme_mask)
120cd576
JB		 1106 adapter->eeprom_wol |= E1000_WUFC_MAG;
1107
1108 /* now that we have the eeprom settings, apply the special cases
1109 * where the eeprom may be wrong or the board simply won't support
1110 * wake on lan on a particular port */
1111 switch (pdev->device) {
1112 case E1000_DEV_ID_82546GB_PCIE:
1113 adapter->eeprom_wol = 0;
1114 break;
1115 case E1000_DEV_ID_82546EB_FIBER:
1116 case E1000_DEV_ID_82546GB_FIBER:
1117 case E1000_DEV_ID_82571EB_FIBER:
1118 /* Wake events only supported on port A for dual fiber
1119 * regardless of eeprom setting */
1120 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
1121 adapter->eeprom_wol = 0;
1122 break;
1123 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
5881cde8 1124 case E1000_DEV_ID_82571EB_QUAD_COPPER:
ce57a02c 1125 case E1000_DEV_ID_82571EB_QUAD_FIBER:
fc2307d0 1126 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
f4ec7f98 1127 case E1000_DEV_ID_82571PT_QUAD_COPPER:
120cd576
JB		 1128 /* if quad port adapter, disable WoL on all but port A */
1129 if (global_quad_port_a != 0)
1130 adapter->eeprom_wol = 0;
1131 else
1132 adapter->quad_port_a = 1;
1133 /* Reset for multiple quad port adapters */
1134 if (++global_quad_port_a == 4)
1135 global_quad_port_a = 0;
1136 break;
1137 }
1138
1139 /* initialize the wol settings based on the eeprom settings */
1140 adapter->wol = adapter->eeprom_wol;
1da177e4 1141
fb3d47d4
JK		 1142 /* print bus type/speed/width info */
1143 {
1144 struct e1000_hw *hw = &adapter->hw;
1145 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
1146 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
1147 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
1148 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
1149 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
1150 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
1151 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
1152 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
1153 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
1154 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
1155 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
1156 "32-bit"));
1157 }
1158
0795af57 1159 printk("%s\n", print_mac(mac, netdev->dev_addr));
fb3d47d4 1160
14782ca8
AK		 1161 if (adapter->hw.bus_type == e1000_bus_type_pci_express) {
1162 DPRINTK(PROBE, WARNING, "This device (id %04x:%04x) will no "
1163 "longer be supported by this driver in the future.\n",
1164 pdev->vendor, pdev->device);
1165 DPRINTK(PROBE, WARNING, "please use the \"e1000e\" "
1166 "driver instead.\n");
1167 }
1168
1da177e4
LT		 1169 /* reset the hardware with the new settings */
1170 e1000_reset(adapter);
1171
b55ccb35
JK		 1172 /* If the controller is 82573 and f/w is AMT, do not set
1173 * DRV_LOAD until the interface is up. For all other cases,
1174 * let the f/w know that the h/w is now under the control
1175 * of the driver. */
1176 if (adapter->hw.mac_type != e1000_82573 ||
1177 !e1000_check_mng_mode(&adapter->hw))
1178 e1000_get_hw_control(adapter);
2d7edb92 1179
1314bbf3
AK		 1180 /* tell the stack to leave us alone until e1000_open() is called */
1181 netif_carrier_off(netdev);
1182 netif_stop_queue(netdev);
416b5d10
AK		 1183
1184 strcpy(netdev->name, "eth%d");
1185 if ((err = register_netdev(netdev)))
1186 goto err_register;
1314bbf3 1187
1da177e4
LT		 1188 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
1189
1190 cards_found++;
1191 return 0;
1192
1193err_register:
6dd62ab0
VA		 1194 e1000_release_hw_control(adapter);
1195err_eeprom:
1196 if (!e1000_check_phy_reset_block(&adapter->hw))
1197 e1000_phy_hw_reset(&adapter->hw);
1198
cd94dd0b
AK		 1199 if (adapter->hw.flash_address)
1200 iounmap(adapter->hw.flash_address);
1201err_flashmap:
6dd62ab0
VA		 1202#ifdef CONFIG_E1000_NAPI
1203 for (i = 0; i < adapter->num_rx_queues; i++)
1204 dev_put(&adapter->polling_netdev[i]);
1205#endif
1206
1207 kfree(adapter->tx_ring);
1208 kfree(adapter->rx_ring);
1209#ifdef CONFIG_E1000_NAPI
1210 kfree(adapter->polling_netdev);
1211#endif
1da177e4 1212err_sw_init:
1da177e4
LT		 1213 iounmap(adapter->hw.hw_addr);
1214err_ioremap:
1215 free_netdev(netdev);
1216err_alloc_etherdev:
1217 pci_release_regions(pdev);
6dd62ab0
VA		 1218err_pci_reg:
1219err_dma:
1220 pci_disable_device(pdev);
1da177e4
LT		 1221 return err;
1222}
1223
1224/**
1225 * e1000_remove - Device Removal Routine
1226 * @pdev: PCI device information struct
1227 *
1228 * e1000_remove is called by the PCI subsystem to alert the driver
1229 * that it should release a PCI device. The could be caused by a
1230 * Hot-Plug event, or because the driver is going to be removed from
1231 * memory.
1232 **/
1233
1234static void __devexit
1235e1000_remove(struct pci_dev *pdev)
1236{
1237 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 1238 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e
MC		 1239#ifdef CONFIG_E1000_NAPI
1240 int i;
1241#endif
1da177e4 1242
28e53bdd 1243 cancel_work_sync(&adapter->reset_task);
be2b28ed 1244
0fccd0e9 1245 e1000_release_manageability(adapter);
1da177e4 1246
b55ccb35
JK		 1247 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1248 * would have already happened in close and is redundant. */
1249 e1000_release_hw_control(adapter);
2d7edb92 1250
581d708e 1251#ifdef CONFIG_E1000_NAPI
f56799ea 1252 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 1253 dev_put(&adapter->polling_netdev[i]);
581d708e 1254#endif
1da177e4 1255
bea3348e
SH		 1256 unregister_netdev(netdev);
1257
96838a40 1258 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 1259 e1000_phy_hw_reset(&adapter->hw);
1da177e4 1260
24025e4e
MC		 1261 kfree(adapter->tx_ring);
1262 kfree(adapter->rx_ring);
1263#ifdef CONFIG_E1000_NAPI
1264 kfree(adapter->polling_netdev);
1265#endif
1266
1da177e4 1267 iounmap(adapter->hw.hw_addr);
cd94dd0b
AK		 1268 if (adapter->hw.flash_address)
1269 iounmap(adapter->hw.flash_address);
1da177e4
LT		 1270 pci_release_regions(pdev);
1271
1272 free_netdev(netdev);
1273
1274 pci_disable_device(pdev);
1275}
1276
1277/**
1278 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
1279 * @adapter: board private structure to initialize
1280 *
1281 * e1000_sw_init initializes the Adapter private data structure.
1282 * Fields are initialized based on PCI device information and
1283 * OS network device settings (MTU size).
1284 **/
1285
1286static int __devinit
1287e1000_sw_init(struct e1000_adapter *adapter)
1288{
1289 struct e1000_hw *hw = &adapter->hw;
1290 struct net_device *netdev = adapter->netdev;
1291 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 1292#ifdef CONFIG_E1000_NAPI
1293 int i;
1294#endif
1da177e4
LT		 1295
1296 /* PCI config space info */
1297
1298 hw->vendor_id = pdev->vendor;
1299 hw->device_id = pdev->device;
1300 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1301 hw->subsystem_id = pdev->subsystem_device;
44c10138 1302 hw->revision_id = pdev->revision;
1da177e4
LT		 1303
1304 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
1305
eb0f8054 1306 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9e2feace 1307 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 1308 hw->max_frame_size = netdev->mtu +
1309 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1310 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
1311
1312 /* identify the MAC */
1313
96838a40 1314 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 1315 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
1316 return -EIO;
1317 }
1318
96838a40 1319 switch (hw->mac_type) {
1da177e4
LT		 1320 default:
1321 break;
1322 case e1000_82541:
1323 case e1000_82547:
1324 case e1000_82541_rev_2:
1325 case e1000_82547_rev_2:
1326 hw->phy_init_script = 1;
1327 break;
1328 }
1329
1330 e1000_set_media_type(hw);
1331
c3033b01
JP		 1332 hw->wait_autoneg_complete = false;
1333 hw->tbi_compatibility_en = true;
1334 hw->adaptive_ifs = true;
1da177e4
LT		 1335
1336 /* Copper options */
1337
96838a40 1338 if (hw->media_type == e1000_media_type_copper) {
1da177e4 1339 hw->mdix = AUTO_ALL_MODES;
c3033b01 1340 hw->disable_polarity_correction = false;
1da177e4
LT		 1341 hw->master_slave = E1000_MASTER_SLAVE;
1342 }
1343
f56799ea
JK		 1344 adapter->num_tx_queues = 1;
1345 adapter->num_rx_queues = 1;
581d708e
MC		 1346
1347 if (e1000_alloc_queues(adapter)) {
1348 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1349 return -ENOMEM;
1350 }
1351
1352#ifdef CONFIG_E1000_NAPI
f56799ea 1353 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e 1354 adapter->polling_netdev[i].priv = adapter;
581d708e
MC		 1355 dev_hold(&adapter->polling_netdev[i]);
1356 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1357 }
7bfa4816 1358 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1359#endif
1360
47313054 1361 /* Explicitly disable IRQ since the NIC can be in any state. */
47313054
HX		 1362 e1000_irq_disable(adapter);
1363
1da177e4 1364 spin_lock_init(&adapter->stats_lock);
1da177e4 1365
1314bbf3
AK		 1366 set_bit(__E1000_DOWN, &adapter->flags);
1367
1da177e4
LT		 1368 return 0;
1369}
1370
581d708e
MC		 1371/**
1372 * e1000_alloc_queues - Allocate memory for all rings
1373 * @adapter: board private structure to initialize
1374 *
1375 * We allocate one ring per queue at run-time since we don't know the
1376 * number of queues at compile-time. The polling_netdev array is
1377 * intended for Multiqueue, but should work fine with a single queue.
1378 **/
1379
1380static int __devinit
1381e1000_alloc_queues(struct e1000_adapter *adapter)
1382{
1c7e5b12
YB		 1383 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1384 sizeof(struct e1000_tx_ring), GFP_KERNEL);
581d708e
MC		 1385 if (!adapter->tx_ring)
1386 return -ENOMEM;
581d708e 1387
1c7e5b12
YB		 1388 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1389 sizeof(struct e1000_rx_ring), GFP_KERNEL);
581d708e
MC		 1390 if (!adapter->rx_ring) {
1391 kfree(adapter->tx_ring);
1392 return -ENOMEM;
1393 }
581d708e
MC		 1394
1395#ifdef CONFIG_E1000_NAPI
1c7e5b12
YB		 1396 adapter->polling_netdev = kcalloc(adapter->num_rx_queues,
1397 sizeof(struct net_device),
1398 GFP_KERNEL);
581d708e
MC		 1399 if (!adapter->polling_netdev) {
1400 kfree(adapter->tx_ring);
1401 kfree(adapter->rx_ring);
1402 return -ENOMEM;
1403 }
581d708e
MC		 1404#endif
1405
1406 return E1000_SUCCESS;
1407}
1408
1da177e4
LT		 1409/**
1410 * e1000_open - Called when a network interface is made active
1411 * @netdev: network interface device structure
1412 *
1413 * Returns 0 on success, negative value on failure
1414 *
1415 * The open entry point is called when a network interface is made
1416 * active by the system (IFF_UP). At this point all resources needed
1417 * for transmit and receive operations are allocated, the interrupt
1418 * handler is registered with the OS, the watchdog timer is started,
1419 * and the stack is notified that the interface is ready.
1420 **/
1421
1422static int
1423e1000_open(struct net_device *netdev)
1424{
60490fe0 1425 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1426 int err;
1427
2db10a08 1428 /* disallow open during test */
1314bbf3 1429 if (test_bit(__E1000_TESTING, &adapter->flags))
2db10a08
AK		 1430 return -EBUSY;
1431
1da177e4 1432 /* allocate transmit descriptors */
e0aac5a2
AK		 1433 err = e1000_setup_all_tx_resources(adapter);
1434 if (err)
1da177e4
LT		 1435 goto err_setup_tx;
1436
1437 /* allocate receive descriptors */
e0aac5a2 1438 err = e1000_setup_all_rx_resources(adapter);
b5bf28cd 1439 if (err)
e0aac5a2 1440 goto err_setup_rx;
b5bf28cd 1441
79f05bf0
AK		 1442 e1000_power_up_phy(adapter);
1443
2d7edb92 1444 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1445 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1446 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1447 e1000_update_mng_vlan(adapter);
1448 }
1da177e4 1449
b55ccb35
JK		 1450 /* If AMT is enabled, let the firmware know that the network
1451 * interface is now open */
1452 if (adapter->hw.mac_type == e1000_82573 &&
1453 e1000_check_mng_mode(&adapter->hw))
1454 e1000_get_hw_control(adapter);
1455
e0aac5a2
AK		 1456 /* before we allocate an interrupt, we must be ready to handle it.
1457 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1458 * as soon as we call pci_request_irq, so we have to setup our
1459 * clean_rx handler before we do so. */
1460 e1000_configure(adapter);
1461
1462 err = e1000_request_irq(adapter);
1463 if (err)
1464 goto err_req_irq;
1465
1466 /* From here on the code is the same as e1000_up() */
1467 clear_bit(__E1000_DOWN, &adapter->flags);
1468
47313054 1469#ifdef CONFIG_E1000_NAPI
bea3348e 1470 napi_enable(&adapter->napi);
47313054
HX		 1471#endif
1472
e0aac5a2
AK		 1473 e1000_irq_enable(adapter);
1474
1475 /* fire a link status change interrupt to start the watchdog */
1476 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1477
1da177e4
LT		 1478 return E1000_SUCCESS;
1479
b5bf28cd 1480err_req_irq:
e0aac5a2
AK		 1481 e1000_release_hw_control(adapter);
1482 e1000_power_down_phy(adapter);
581d708e 1483 e1000_free_all_rx_resources(adapter);
1da177e4 1484err_setup_rx:
581d708e 1485 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1486err_setup_tx:
1487 e1000_reset(adapter);
1488
1489 return err;
1490}
1491
1492/**
1493 * e1000_close - Disables a network interface
1494 * @netdev: network interface device structure
1495 *
1496 * Returns 0, this is not allowed to fail
1497 *
1498 * The close entry point is called when an interface is de-activated
1499 * by the OS. The hardware is still under the drivers control, but
1500 * needs to be disabled. A global MAC reset is issued to stop the
1501 * hardware, and all transmit and receive resources are freed.
1502 **/
1503
1504static int
1505e1000_close(struct net_device *netdev)
1506{
60490fe0 1507 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 1508
2db10a08 1509 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 1510 e1000_down(adapter);
79f05bf0 1511 e1000_power_down_phy(adapter);
2db10a08 1512 e1000_free_irq(adapter);
1da177e4 1513
581d708e
MC		 1514 e1000_free_all_tx_resources(adapter);
1515 e1000_free_all_rx_resources(adapter);
1da177e4 1516
4666560a
BA		 1517 /* kill manageability vlan ID if supported, but not if a vlan with
1518 * the same ID is registered on the host OS (let 8021q kill it) */
96838a40 1519 if ((adapter->hw.mng_cookie.status &
4666560a
BA		 1520 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
1521 !(adapter->vlgrp &&
5c15bdec 1522 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) {
2d7edb92
MC		 1523 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1524 }
b55ccb35
JK		 1525
1526 /* If AMT is enabled, let the firmware know that the network
1527 * interface is now closed */
1528 if (adapter->hw.mac_type == e1000_82573 &&
1529 e1000_check_mng_mode(&adapter->hw))
1530 e1000_release_hw_control(adapter);
1531
1da177e4
LT		 1532 return 0;
1533}
1534
1535/**
1536 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1537 * @adapter: address of board private structure
2d7edb92
MC		 1538 * @start: address of beginning of memory
1539 * @len: length of memory
1da177e4 1540 **/
c3033b01 1541static bool
1da177e4
LT		 1542e1000_check_64k_bound(struct e1000_adapter *adapter,
1543 void *start, unsigned long len)
1544{
1545 unsigned long begin = (unsigned long) start;
1546 unsigned long end = begin + len;
1547
2648345f
MC		 1548 /* First rev 82545 and 82546 need to not allow any memory
1549 * write location to cross 64k boundary due to errata 23 */
1da177e4 1550 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1551 adapter->hw.mac_type == e1000_82546) {
c3033b01 1552 return ((begin ^ (end - 1)) >> 16) != 0 ? false : true;
1da177e4
LT		 1553 }
1554
c3033b01 1555 return true;
1da177e4
LT		 1556}
1557
1558/**
1559 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1560 * @adapter: board private structure
581d708e 1561 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1562 *
1563 * Return 0 on success, negative on failure
1564 **/
1565
3ad2cc67 1566static int
581d708e
MC		 1567e1000_setup_tx_resources(struct e1000_adapter *adapter,
1568 struct e1000_tx_ring *txdr)
1da177e4 1569{
1da177e4
LT		 1570 struct pci_dev *pdev = adapter->pdev;
1571 int size;
1572
1573 size = sizeof(struct e1000_buffer) * txdr->count;
cd94dd0b 1574 txdr->buffer_info = vmalloc(size);
96838a40 1575 if (!txdr->buffer_info) {
2648345f
MC		 1576 DPRINTK(PROBE, ERR,
1577 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1578 return -ENOMEM;
1579 }
1580 memset(txdr->buffer_info, 0, size);
1581
1582 /* round up to nearest 4K */
1583
1584 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
9099cfb9 1585 txdr->size = ALIGN(txdr->size, 4096);
1da177e4
LT		 1586
1587 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1588 if (!txdr->desc) {
1da177e4 1589setup_tx_desc_die:
1da177e4 1590 vfree(txdr->buffer_info);
2648345f
MC		 1591 DPRINTK(PROBE, ERR,
1592 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1593 return -ENOMEM;
1594 }
1595
2648345f 1596 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1597 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1598 void *olddesc = txdr->desc;
1599 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1600 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1601 "at %p\n", txdr->size, txdr->desc);
1602 /* Try again, without freeing the previous */
1da177e4 1603 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1604 /* Failed allocation, critical failure */
96838a40 1605 if (!txdr->desc) {
1da177e4
LT		 1606 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1607 goto setup_tx_desc_die;
1608 }
1609
1610 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1611 /* give up */
2648345f
MC		 1612 pci_free_consistent(pdev, txdr->size, txdr->desc,
1613 txdr->dma);
1da177e4
LT		 1614 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1615 DPRINTK(PROBE, ERR,
2648345f
MC		 1616 "Unable to allocate aligned memory "
1617 "for the transmit descriptor ring\n");
1da177e4
LT		 1618 vfree(txdr->buffer_info);
1619 return -ENOMEM;
1620 } else {
2648345f 1621 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1622 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1623 }
1624 }
1625 memset(txdr->desc, 0, txdr->size);
1626
1627 txdr->next_to_use = 0;
1628 txdr->next_to_clean = 0;
2ae76d98 1629 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1630
1631 return 0;
1632}
1633
581d708e
MC		 1634/**
1635 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1636 * (Descriptors) for all queues
1637 * @adapter: board private structure
1638 *
581d708e
MC		 1639 * Return 0 on success, negative on failure
1640 **/
1641
1642int
1643e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1644{
1645 int i, err = 0;
1646
f56799ea 1647 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1648 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1649 if (err) {
1650 DPRINTK(PROBE, ERR,
1651 "Allocation for Tx Queue %u failed\n", i);
3fbbc72e
VA		 1652 for (i-- ; i >= 0; i--)
1653 e1000_free_tx_resources(adapter,
1654 &adapter->tx_ring[i]);
581d708e
MC		 1655 break;
1656 }
1657 }
1658
1659 return err;
1660}
1661
1da177e4
LT		 1662/**
1663 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1664 * @adapter: board private structure
1665 *
1666 * Configure the Tx unit of the MAC after a reset.
1667 **/
1668
1669static void
1670e1000_configure_tx(struct e1000_adapter *adapter)
1671{
406874a7 1672 u64 tdba;
581d708e 1673 struct e1000_hw *hw = &adapter->hw;
406874a7
JP		 1674 u32 tdlen, tctl, tipg, tarc;
1675 u32 ipgr1, ipgr2;
1da177e4
LT		 1676
1677 /* Setup the HW Tx Head and Tail descriptor pointers */
1678
f56799ea 1679 switch (adapter->num_tx_queues) {
24025e4e
MC		 1680 case 1:
1681 default:
581d708e
MC		 1682 tdba = adapter->tx_ring[0].dma;
1683 tdlen = adapter->tx_ring[0].count *
1684 sizeof(struct e1000_tx_desc);
581d708e 1685 E1000_WRITE_REG(hw, TDLEN, tdlen);
4ca213a6
AK		 1686 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1687 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
581d708e 1688 E1000_WRITE_REG(hw, TDT, 0);
4ca213a6 1689 E1000_WRITE_REG(hw, TDH, 0);
6a951698
AK		 1690 adapter->tx_ring[0].tdh = ((hw->mac_type >= e1000_82543) ? E1000_TDH : E1000_82542_TDH);
1691 adapter->tx_ring[0].tdt = ((hw->mac_type >= e1000_82543) ? E1000_TDT : E1000_82542_TDT);
24025e4e
MC		 1692 break;
1693 }
1da177e4
LT		 1694
1695 /* Set the default values for the Tx Inter Packet Gap timer */
d89b6c67
JB		 1696 if (adapter->hw.mac_type <= e1000_82547_rev_2 &&
1697 (hw->media_type == e1000_media_type_fiber ||
1698 hw->media_type == e1000_media_type_internal_serdes))
0fadb059
JK		 1699 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1700 else
1701 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1702
581d708e 1703 switch (hw->mac_type) {
1da177e4
LT		 1704 case e1000_82542_rev2_0:
1705 case e1000_82542_rev2_1:
1706 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1707 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1708 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1709 break;
87041639
JK		 1710 case e1000_80003es2lan:
1711 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1712 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1713 break;
1da177e4 1714 default:
0fadb059
JK		 1715 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1716 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1717 break;
1da177e4 1718 }
0fadb059
JK		 1719 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1720 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1721 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1722
1723 /* Set the Tx Interrupt Delay register */
1724
581d708e
MC		 1725 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1726 if (hw->mac_type >= e1000_82540)
1727 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1728
1729 /* Program the Transmit Control Register */
1730
581d708e 1731 tctl = E1000_READ_REG(hw, TCTL);
1da177e4 1732 tctl &= ~E1000_TCTL_CT;
7e6c9861 1733 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1734 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1735
2ae76d98
MC		 1736 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1737 tarc = E1000_READ_REG(hw, TARC0);
90fb5135
AK		 1738 /* set the speed mode bit, we'll clear it if we're not at
1739 * gigabit link later */
09ae3e88 1740 tarc |= (1 << 21);
2ae76d98 1741 E1000_WRITE_REG(hw, TARC0, tarc);
87041639
JK		 1742 } else if (hw->mac_type == e1000_80003es2lan) {
1743 tarc = E1000_READ_REG(hw, TARC0);
1744 tarc |= 1;
87041639
JK		 1745 E1000_WRITE_REG(hw, TARC0, tarc);
1746 tarc = E1000_READ_REG(hw, TARC1);
1747 tarc |= 1;
1748 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1749 }
1750
581d708e 1751 e1000_config_collision_dist(hw);
1da177e4
LT		 1752
1753 /* Setup Transmit Descriptor Settings for eop descriptor */
6a042dab
JB		 1754 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
1755
1756 /* only set IDE if we are delaying interrupts using the timers */
1757 if (adapter->tx_int_delay)
1758 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
1da177e4 1759
581d708e 1760 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1761 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1762 else
1763 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1764
1765 /* Cache if we're 82544 running in PCI-X because we'll
1766 * need this to apply a workaround later in the send path. */
581d708e
MC		 1767 if (hw->mac_type == e1000_82544 &&
1768 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1769 adapter->pcix_82544 = 1;
7e6c9861
JK		 1770
1771 E1000_WRITE_REG(hw, TCTL, tctl);
1772
1da177e4
LT		 1773}
1774
1775/**
1776 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1777 * @adapter: board private structure
581d708e 1778 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1779 *
1780 * Returns 0 on success, negative on failure
1781 **/
1782
3ad2cc67 1783static int
581d708e
MC		 1784e1000_setup_rx_resources(struct e1000_adapter *adapter,
1785 struct e1000_rx_ring *rxdr)
1da177e4 1786{
1da177e4 1787 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1788 int size, desc_len;
1da177e4
LT		 1789
1790 size = sizeof(struct e1000_buffer) * rxdr->count;
cd94dd0b 1791 rxdr->buffer_info = vmalloc(size);
581d708e 1792 if (!rxdr->buffer_info) {
2648345f
MC		 1793 DPRINTK(PROBE, ERR,
1794 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1795 return -ENOMEM;
1796 }
1797 memset(rxdr->buffer_info, 0, size);
1798
1c7e5b12
YB		 1799 rxdr->ps_page = kcalloc(rxdr->count, sizeof(struct e1000_ps_page),
1800 GFP_KERNEL);
96838a40 1801 if (!rxdr->ps_page) {
2d7edb92
MC		 1802 vfree(rxdr->buffer_info);
1803 DPRINTK(PROBE, ERR,
1804 "Unable to allocate memory for the receive descriptor ring\n");
1805 return -ENOMEM;
1806 }
2d7edb92 1807
1c7e5b12
YB		 1808 rxdr->ps_page_dma = kcalloc(rxdr->count,
1809 sizeof(struct e1000_ps_page_dma),
1810 GFP_KERNEL);
96838a40 1811 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1812 vfree(rxdr->buffer_info);
1813 kfree(rxdr->ps_page);
1814 DPRINTK(PROBE, ERR,
1815 "Unable to allocate memory for the receive descriptor ring\n");
1816 return -ENOMEM;
1817 }
2d7edb92 1818
96838a40 1819 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1820 desc_len = sizeof(struct e1000_rx_desc);
1821 else
1822 desc_len = sizeof(union e1000_rx_desc_packet_split);
1823
1da177e4
LT		 1824 /* Round up to nearest 4K */
1825
2d7edb92 1826 rxdr->size = rxdr->count * desc_len;
9099cfb9 1827 rxdr->size = ALIGN(rxdr->size, 4096);
1da177e4
LT		 1828
1829 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1830
581d708e
MC		 1831 if (!rxdr->desc) {
1832 DPRINTK(PROBE, ERR,
1833 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1834setup_rx_desc_die:
1da177e4 1835 vfree(rxdr->buffer_info);
2d7edb92
MC		 1836 kfree(rxdr->ps_page);
1837 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1838 return -ENOMEM;
1839 }
1840
2648345f 1841 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1842 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1843 void *olddesc = rxdr->desc;
1844 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1845 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1846 "at %p\n", rxdr->size, rxdr->desc);
1847 /* Try again, without freeing the previous */
1da177e4 1848 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1849 /* Failed allocation, critical failure */
581d708e 1850 if (!rxdr->desc) {
1da177e4 1851 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1852 DPRINTK(PROBE, ERR,
1853 "Unable to allocate memory "
1854 "for the receive descriptor ring\n");
1da177e4
LT		 1855 goto setup_rx_desc_die;
1856 }
1857
1858 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1859 /* give up */
2648345f
MC		 1860 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1861 rxdr->dma);
1da177e4 1862 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1863 DPRINTK(PROBE, ERR,
1864 "Unable to allocate aligned memory "
1865 "for the receive descriptor ring\n");
581d708e 1866 goto setup_rx_desc_die;
1da177e4 1867 } else {
2648345f 1868 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1869 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1870 }
1871 }
1872 memset(rxdr->desc, 0, rxdr->size);
1873
1874 rxdr->next_to_clean = 0;
1875 rxdr->next_to_use = 0;
1876
1877 return 0;
1878}
1879
581d708e
MC		 1880/**
1881 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1882 * (Descriptors) for all queues
1883 * @adapter: board private structure
1884 *
581d708e
MC		 1885 * Return 0 on success, negative on failure
1886 **/
1887
1888int
1889e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1890{
1891 int i, err = 0;
1892
f56799ea 1893 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1894 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1895 if (err) {
1896 DPRINTK(PROBE, ERR,
1897 "Allocation for Rx Queue %u failed\n", i);
3fbbc72e
VA		 1898 for (i-- ; i >= 0; i--)
1899 e1000_free_rx_resources(adapter,
1900 &adapter->rx_ring[i]);
581d708e
MC		 1901 break;
1902 }
1903 }
1904
1905 return err;
1906}
1907
1da177e4 1908/**
2648345f 1909 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1910 * @adapter: Board private structure
1911 **/
e4c811c9
MC		 1912#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1913 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1914static void
1915e1000_setup_rctl(struct e1000_adapter *adapter)
1916{
406874a7
JP		 1917 u32 rctl, rfctl;
1918 u32 psrctl = 0;
35ec56bb 1919#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
406874a7 1920 u32 pages = 0;
e4c811c9 1921#endif
1da177e4
LT		 1922
1923 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1924
1925 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1926
1927 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1928 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1929 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1930
0fadb059 1931 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1932 rctl |= E1000_RCTL_SBP;
1933 else
1934 rctl &= ~E1000_RCTL_SBP;
1935
2d7edb92
MC		 1936 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1937 rctl &= ~E1000_RCTL_LPE;
1938 else
1939 rctl |= E1000_RCTL_LPE;
1940
1da177e4 1941 /* Setup buffer sizes */
9e2feace
AK		 1942 rctl &= ~E1000_RCTL_SZ_4096;
1943 rctl |= E1000_RCTL_BSEX;
1944 switch (adapter->rx_buffer_len) {
1945 case E1000_RXBUFFER_256:
1946 rctl |= E1000_RCTL_SZ_256;
1947 rctl &= ~E1000_RCTL_BSEX;
1948 break;
1949 case E1000_RXBUFFER_512:
1950 rctl |= E1000_RCTL_SZ_512;
1951 rctl &= ~E1000_RCTL_BSEX;
1952 break;
1953 case E1000_RXBUFFER_1024:
1954 rctl |= E1000_RCTL_SZ_1024;
1955 rctl &= ~E1000_RCTL_BSEX;
1956 break;
a1415ee6
JK		 1957 case E1000_RXBUFFER_2048:
1958 default:
1959 rctl |= E1000_RCTL_SZ_2048;
1960 rctl &= ~E1000_RCTL_BSEX;
1961 break;
1962 case E1000_RXBUFFER_4096:
1963 rctl |= E1000_RCTL_SZ_4096;
1964 break;
1965 case E1000_RXBUFFER_8192:
1966 rctl |= E1000_RCTL_SZ_8192;
1967 break;
1968 case E1000_RXBUFFER_16384:
1969 rctl |= E1000_RCTL_SZ_16384;
1970 break;
2d7edb92
MC		 1971 }
1972
35ec56bb 1973#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1974 /* 82571 and greater support packet-split where the protocol
1975 * header is placed in skb->data and the packet data is
1976 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1977 * In the case of a non-split, skb->data is linearly filled,
1978 * followed by the page buffers. Therefore, skb->data is
1979 * sized to hold the largest protocol header.
1980 */
e64d7d02
JB		 1981 /* allocations using alloc_page take too long for regular MTU
1982 * so only enable packet split for jumbo frames */
e4c811c9 1983 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
e64d7d02
JB		 1984 if ((adapter->hw.mac_type >= e1000_82571) && (pages <= 3) &&
1985 PAGE_SIZE <= 16384 && (rctl & E1000_RCTL_LPE))
e4c811c9
MC		 1986 adapter->rx_ps_pages = pages;
1987 else
1988 adapter->rx_ps_pages = 0;
2d7edb92 1989#endif
e4c811c9 1990 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1991 /* Configure extra packet-split registers */
1992 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1993 rfctl |= E1000_RFCTL_EXTEN;
87ca4e5b
AK		 1994 /* disable packet split support for IPv6 extension headers,
1995 * because some malformed IPv6 headers can hang the RX */
1996 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
1997 E1000_RFCTL_NEW_IPV6_EXT_DIS);
1998
2d7edb92
MC		 1999 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
2000
7dfee0cb 2001 rctl |= E1000_RCTL_DTYP_PS;
96838a40 2002
2d7edb92
MC		 2003 psrctl |= adapter->rx_ps_bsize0 >>
2004 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 2005
2006 switch (adapter->rx_ps_pages) {
2007 case 3:
2008 psrctl |= PAGE_SIZE <<
2009 E1000_PSRCTL_BSIZE3_SHIFT;
2010 case 2:
2011 psrctl |= PAGE_SIZE <<
2012 E1000_PSRCTL_BSIZE2_SHIFT;
2013 case 1:
2014 psrctl |= PAGE_SIZE >>
2015 E1000_PSRCTL_BSIZE1_SHIFT;
2016 break;
2017 }
2d7edb92
MC		 2018
2019 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 2020 }
2021
2022 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2023}
2024
2025/**
2026 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
2027 * @adapter: board private structure
2028 *
2029 * Configure the Rx unit of the MAC after a reset.
2030 **/
2031
2032static void
2033e1000_configure_rx(struct e1000_adapter *adapter)
2034{
406874a7 2035 u64 rdba;
581d708e 2036 struct e1000_hw *hw = &adapter->hw;
406874a7 2037 u32 rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 2038
e4c811c9 2039 if (adapter->rx_ps_pages) {
0f15a8fa 2040 /* this is a 32 byte descriptor */
581d708e 2041 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 2042 sizeof(union e1000_rx_desc_packet_split);
2043 adapter->clean_rx = e1000_clean_rx_irq_ps;
2044 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
2045 } else {
581d708e
MC		 2046 rdlen = adapter->rx_ring[0].count *
2047 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 2048 adapter->clean_rx = e1000_clean_rx_irq;
2049 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
2050 }
1da177e4
LT		 2051
2052 /* disable receives while setting up the descriptors */
581d708e
MC		 2053 rctl = E1000_READ_REG(hw, RCTL);
2054 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 2055
2056 /* set the Receive Delay Timer Register */
581d708e 2057 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 2058
581d708e
MC		 2059 if (hw->mac_type >= e1000_82540) {
2060 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
835bb129 2061 if (adapter->itr_setting != 0)
581d708e 2062 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 2063 1000000000 / (adapter->itr * 256));
2064 }
2065
2ae76d98 2066 if (hw->mac_type >= e1000_82571) {
2ae76d98 2067 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 2068 /* Reset delay timers after every interrupt */
6fc7a7ec 2069 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9 2070#ifdef CONFIG_E1000_NAPI
835bb129 2071 /* Auto-Mask interrupts upon ICR access */
1e613fd9 2072 ctrl_ext |= E1000_CTRL_EXT_IAME;
835bb129 2073 E1000_WRITE_REG(hw, IAM, 0xffffffff);
1e613fd9 2074#endif
2ae76d98
MC		 2075 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2076 E1000_WRITE_FLUSH(hw);
2077 }
2078
581d708e
MC		 2079 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2080 * the Base and Length of the Rx Descriptor Ring */
f56799ea 2081 switch (adapter->num_rx_queues) {
24025e4e
MC		 2082 case 1:
2083 default:
581d708e 2084 rdba = adapter->rx_ring[0].dma;
581d708e 2085 E1000_WRITE_REG(hw, RDLEN, rdlen);
4ca213a6
AK		 2086 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
2087 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
581d708e 2088 E1000_WRITE_REG(hw, RDT, 0);
4ca213a6 2089 E1000_WRITE_REG(hw, RDH, 0);
6a951698
AK		 2090 adapter->rx_ring[0].rdh = ((hw->mac_type >= e1000_82543) ? E1000_RDH : E1000_82542_RDH);
2091 adapter->rx_ring[0].rdt = ((hw->mac_type >= e1000_82543) ? E1000_RDT : E1000_82542_RDT);
581d708e 2092 break;
24025e4e
MC		 2093 }
2094
1da177e4 2095 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 2096 if (hw->mac_type >= e1000_82543) {
2097 rxcsum = E1000_READ_REG(hw, RXCSUM);
c3033b01 2098 if (adapter->rx_csum) {
2d7edb92
MC		 2099 rxcsum |= E1000_RXCSUM_TUOFL;
2100
868d5309 2101 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 2102 * Must be used in conjunction with packet-split. */
96838a40
JB		 2103 if ((hw->mac_type >= e1000_82571) &&
2104 (adapter->rx_ps_pages)) {
2d7edb92
MC		 2105 rxcsum |= E1000_RXCSUM_IPPCSE;
2106 }
2107 } else {
2108 rxcsum &= ~E1000_RXCSUM_TUOFL;
2109 /* don't need to clear IPPCSE as it defaults to 0 */
2110 }
581d708e 2111 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 2112 }
2113
21c4d5e0
AK		 2114 /* enable early receives on 82573, only takes effect if using > 2048
2115 * byte total frame size. for example only for jumbo frames */
2116#define E1000_ERT_2048 0x100
2117 if (hw->mac_type == e1000_82573)
2118 E1000_WRITE_REG(hw, ERT, E1000_ERT_2048);
2119
1da177e4 2120 /* Enable Receives */
581d708e 2121 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 2122}
2123
2124/**
581d708e 2125 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 2126 * @adapter: board private structure
581d708e 2127 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 2128 *
2129 * Free all transmit software resources
2130 **/
2131
3ad2cc67 2132static void
581d708e
MC		 2133e1000_free_tx_resources(struct e1000_adapter *adapter,
2134 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 2135{
2136 struct pci_dev *pdev = adapter->pdev;
2137
581d708e 2138 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 2139
581d708e
MC		 2140 vfree(tx_ring->buffer_info);
2141 tx_ring->buffer_info = NULL;
1da177e4 2142
581d708e 2143 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 2144
581d708e
MC		 2145 tx_ring->desc = NULL;
2146}
2147
2148/**
2149 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
2150 * @adapter: board private structure
2151 *
2152 * Free all transmit software resources
2153 **/
2154
2155void
2156e1000_free_all_tx_resources(struct e1000_adapter *adapter)
2157{
2158 int i;
2159
f56799ea 2160 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2161 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2162}
2163
e619d523 2164static void
1da177e4
LT		 2165e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
2166 struct e1000_buffer *buffer_info)
2167{
96838a40 2168 if (buffer_info->dma) {
2648345f
MC		 2169 pci_unmap_page(adapter->pdev,
2170 buffer_info->dma,
2171 buffer_info->length,
2172 PCI_DMA_TODEVICE);
a9ebadd6 2173 buffer_info->dma = 0;
1da177e4 2174 }
a9ebadd6 2175 if (buffer_info->skb) {
1da177e4 2176 dev_kfree_skb_any(buffer_info->skb);
a9ebadd6
JB		 2177 buffer_info->skb = NULL;
2178 }
2179 /* buffer_info must be completely set up in the transmit path */
1da177e4
LT		 2180}
2181
2182/**
2183 * e1000_clean_tx_ring - Free Tx Buffers
2184 * @adapter: board private structure
581d708e 2185 * @tx_ring: ring to be cleaned
1da177e4
LT		 2186 **/
2187
2188static void
581d708e
MC		 2189e1000_clean_tx_ring(struct e1000_adapter *adapter,
2190 struct e1000_tx_ring *tx_ring)
1da177e4 2191{
1da177e4
LT		 2192 struct e1000_buffer *buffer_info;
2193 unsigned long size;
2194 unsigned int i;
2195
2196 /* Free all the Tx ring sk_buffs */
2197
96838a40 2198 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 2199 buffer_info = &tx_ring->buffer_info[i];
2200 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
2201 }
2202
2203 size = sizeof(struct e1000_buffer) * tx_ring->count;
2204 memset(tx_ring->buffer_info, 0, size);
2205
2206 /* Zero out the descriptor ring */
2207
2208 memset(tx_ring->desc, 0, tx_ring->size);
2209
2210 tx_ring->next_to_use = 0;
2211 tx_ring->next_to_clean = 0;
fd803241 2212 tx_ring->last_tx_tso = 0;
1da177e4 2213
581d708e
MC		 2214 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
2215 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
2216}
2217
2218/**
2219 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
2220 * @adapter: board private structure
2221 **/
2222
2223static void
2224e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
2225{
2226 int i;
2227
f56799ea 2228 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2229 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2230}
2231
2232/**
2233 * e1000_free_rx_resources - Free Rx Resources
2234 * @adapter: board private structure
581d708e 2235 * @rx_ring: ring to clean the resources from
1da177e4
LT		 2236 *
2237 * Free all receive software resources
2238 **/
2239
3ad2cc67 2240static void
581d708e
MC		 2241e1000_free_rx_resources(struct e1000_adapter *adapter,
2242 struct e1000_rx_ring *rx_ring)
1da177e4 2243{
1da177e4
LT		 2244 struct pci_dev *pdev = adapter->pdev;
2245
581d708e 2246 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 2247
2248 vfree(rx_ring->buffer_info);
2249 rx_ring->buffer_info = NULL;
2d7edb92
MC		 2250 kfree(rx_ring->ps_page);
2251 rx_ring->ps_page = NULL;
2252 kfree(rx_ring->ps_page_dma);
2253 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 2254
2255 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2256
2257 rx_ring->desc = NULL;
2258}
2259
2260/**
581d708e 2261 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2262 * @adapter: board private structure
581d708e
MC		 2263 *
2264 * Free all receive software resources
2265 **/
2266
2267void
2268e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2269{
2270 int i;
2271
f56799ea 2272 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2273 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2274}
2275
2276/**
2277 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2278 * @adapter: board private structure
2279 * @rx_ring: ring to free buffers from
1da177e4
LT		 2280 **/
2281
2282static void
581d708e
MC		 2283e1000_clean_rx_ring(struct e1000_adapter *adapter,
2284 struct e1000_rx_ring *rx_ring)
1da177e4 2285{
1da177e4 2286 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2287 struct e1000_ps_page *ps_page;
2288 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2289 struct pci_dev *pdev = adapter->pdev;
2290 unsigned long size;
2d7edb92 2291 unsigned int i, j;
1da177e4
LT		 2292
2293 /* Free all the Rx ring sk_buffs */
96838a40 2294 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2295 buffer_info = &rx_ring->buffer_info[i];
96838a40 2296 if (buffer_info->skb) {
1da177e4
LT		 2297 pci_unmap_single(pdev,
2298 buffer_info->dma,
2299 buffer_info->length,
2300 PCI_DMA_FROMDEVICE);
2301
2302 dev_kfree_skb(buffer_info->skb);
2303 buffer_info->skb = NULL;
997f5cbd
JK		 2304 }
2305 ps_page = &rx_ring->ps_page[i];
2306 ps_page_dma = &rx_ring->ps_page_dma[i];
2307 for (j = 0; j < adapter->rx_ps_pages; j++) {
2308 if (!ps_page->ps_page[j]) break;
2309 pci_unmap_page(pdev,
2310 ps_page_dma->ps_page_dma[j],
2311 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2312 ps_page_dma->ps_page_dma[j] = 0;
2313 put_page(ps_page->ps_page[j]);
2314 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2315 }
2316 }
2317
2318 size = sizeof(struct e1000_buffer) * rx_ring->count;
2319 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2320 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2321 memset(rx_ring->ps_page, 0, size);
2322 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2323 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2324
2325 /* Zero out the descriptor ring */
2326
2327 memset(rx_ring->desc, 0, rx_ring->size);
2328
2329 rx_ring->next_to_clean = 0;
2330 rx_ring->next_to_use = 0;
2331
581d708e
MC		 2332 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2333 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2334}
2335
2336/**
2337 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2338 * @adapter: board private structure
2339 **/
2340
2341static void
2342e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2343{
2344 int i;
2345
f56799ea 2346 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2347 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2348}
2349
2350/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2351 * and memory write and invalidate disabled for certain operations
2352 */
2353static void
2354e1000_enter_82542_rst(struct e1000_adapter *adapter)
2355{
2356 struct net_device *netdev = adapter->netdev;
406874a7 2357 u32 rctl;
1da177e4
LT		 2358
2359 e1000_pci_clear_mwi(&adapter->hw);
2360
2361 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2362 rctl |= E1000_RCTL_RST;
2363 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2364 E1000_WRITE_FLUSH(&adapter->hw);
2365 mdelay(5);
2366
96838a40 2367 if (netif_running(netdev))
581d708e 2368 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2369}
2370
2371static void
2372e1000_leave_82542_rst(struct e1000_adapter *adapter)
2373{
2374 struct net_device *netdev = adapter->netdev;
406874a7 2375 u32 rctl;
1da177e4
LT		 2376
2377 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2378 rctl &= ~E1000_RCTL_RST;
2379 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2380 E1000_WRITE_FLUSH(&adapter->hw);
2381 mdelay(5);
2382
96838a40 2383 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2384 e1000_pci_set_mwi(&adapter->hw);
2385
96838a40 2386 if (netif_running(netdev)) {
72d64a43
JK		 2387 /* No need to loop, because 82542 supports only 1 queue */
2388 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2389 e1000_configure_rx(adapter);
72d64a43 2390 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2391 }
2392}
2393
2394/**
2395 * e1000_set_mac - Change the Ethernet Address of the NIC
2396 * @netdev: network interface device structure
2397 * @p: pointer to an address structure
2398 *
2399 * Returns 0 on success, negative on failure
2400 **/
2401
2402static int
2403e1000_set_mac(struct net_device *netdev, void *p)
2404{
60490fe0 2405 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2406 struct sockaddr *addr = p;
2407
96838a40 2408 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2409 return -EADDRNOTAVAIL;
2410
2411 /* 82542 2.0 needs to be in reset to write receive address registers */
2412
96838a40 2413 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2414 e1000_enter_82542_rst(adapter);
2415
2416 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2417 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2418
2419 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2420
868d5309
MC		 2421 /* With 82571 controllers, LAA may be overwritten (with the default)
2422 * due to controller reset from the other port. */
2423 if (adapter->hw.mac_type == e1000_82571) {
2424 /* activate the work around */
2425 adapter->hw.laa_is_present = 1;
2426
96838a40
JB		 2427 /* Hold a copy of the LAA in RAR[14] This is done so that
2428 * between the time RAR[0] gets clobbered and the time it
2429 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2430 * of the RARs and no incoming packets directed to this port
96838a40 2431 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2432 * RAR[14] */
96838a40 2433 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2434 E1000_RAR_ENTRIES - 1);
2435 }
2436
96838a40 2437 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2438 e1000_leave_82542_rst(adapter);
2439
2440 return 0;
2441}
2442
2443/**
db0ce50d 2444 * e1000_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
1da177e4
LT		 2445 * @netdev: network interface device structure
2446 *
db0ce50d
PM		 2447 * The set_rx_mode entry point is called whenever the unicast or multicast
2448 * address lists or the network interface flags are updated. This routine is
2449 * responsible for configuring the hardware for proper unicast, multicast,
1da177e4
LT		 2450 * promiscuous mode, and all-multi behavior.
2451 **/
2452
2453static void
db0ce50d 2454e1000_set_rx_mode(struct net_device *netdev)
1da177e4 2455{
60490fe0 2456 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2457 struct e1000_hw *hw = &adapter->hw;
db0ce50d
PM		 2458 struct dev_addr_list *uc_ptr;
2459 struct dev_addr_list *mc_ptr;
406874a7
JP		 2460 u32 rctl;
2461 u32 hash_value;
868d5309 2462 int i, rar_entries = E1000_RAR_ENTRIES;
cd94dd0b
AK		 2463 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2464 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2465 E1000_NUM_MTA_REGISTERS;
2466
2467 if (adapter->hw.mac_type == e1000_ich8lan)
2468 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
1da177e4 2469
868d5309
MC		 2470 /* reserve RAR[14] for LAA over-write work-around */
2471 if (adapter->hw.mac_type == e1000_82571)
2472 rar_entries--;
1da177e4 2473
2648345f
MC		 2474 /* Check for Promiscuous and All Multicast modes */
2475
1da177e4
LT		 2476 rctl = E1000_READ_REG(hw, RCTL);
2477
96838a40 2478 if (netdev->flags & IFF_PROMISC) {
1da177e4 2479 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2480 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4 2481 rctl |= E1000_RCTL_MPE;
1da177e4 2482 } else {
db0ce50d
PM		 2483 rctl &= ~E1000_RCTL_MPE;
2484 }
2485
2486 uc_ptr = NULL;
2487 if (netdev->uc_count > rar_entries - 1) {
2488 rctl |= E1000_RCTL_UPE;
2489 } else if (!(netdev->flags & IFF_PROMISC)) {
2490 rctl &= ~E1000_RCTL_UPE;
2491 uc_ptr = netdev->uc_list;
1da177e4
LT		 2492 }
2493
2494 E1000_WRITE_REG(hw, RCTL, rctl);
2495
2496 /* 82542 2.0 needs to be in reset to write receive address registers */
2497
96838a40 2498 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2499 e1000_enter_82542_rst(adapter);
2500
db0ce50d
PM		 2501 /* load the first 14 addresses into the exact filters 1-14. Unicast
2502 * addresses take precedence to avoid disabling unicast filtering
2503 * when possible.
2504 *
1da177e4
LT		 2505 * RAR 0 is used for the station MAC adddress
2506 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2507 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2508 */
2509 mc_ptr = netdev->mc_list;
2510
96838a40 2511 for (i = 1; i < rar_entries; i++) {
db0ce50d
PM		 2512 if (uc_ptr) {
2513 e1000_rar_set(hw, uc_ptr->da_addr, i);
2514 uc_ptr = uc_ptr->next;
2515 } else if (mc_ptr) {
2516 e1000_rar_set(hw, mc_ptr->da_addr, i);
1da177e4
LT		 2517 mc_ptr = mc_ptr->next;
2518 } else {
2519 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
4ca213a6 2520 E1000_WRITE_FLUSH(hw);
1da177e4 2521 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
4ca213a6 2522 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 2523 }
2524 }
db0ce50d 2525 WARN_ON(uc_ptr != NULL);
1da177e4
LT		 2526
2527 /* clear the old settings from the multicast hash table */
2528
cd94dd0b 2529 for (i = 0; i < mta_reg_count; i++) {
1da177e4 2530 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 2531 E1000_WRITE_FLUSH(hw);
2532 }
1da177e4
LT		 2533
2534 /* load any remaining addresses into the hash table */
2535
96838a40 2536 for (; mc_ptr; mc_ptr = mc_ptr->next) {
db0ce50d 2537 hash_value = e1000_hash_mc_addr(hw, mc_ptr->da_addr);
1da177e4
LT		 2538 e1000_mta_set(hw, hash_value);
2539 }
2540
96838a40 2541 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2542 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2543}
2544
2545/* Need to wait a few seconds after link up to get diagnostic information from
2546 * the phy */
2547
2548static void
2549e1000_update_phy_info(unsigned long data)
2550{
2551 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2552 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2553}
2554
2555/**
2556 * e1000_82547_tx_fifo_stall - Timer Call-back
2557 * @data: pointer to adapter cast into an unsigned long
2558 **/
2559
2560static void
2561e1000_82547_tx_fifo_stall(unsigned long data)
2562{
2563 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2564 struct net_device *netdev = adapter->netdev;
406874a7 2565 u32 tctl;
1da177e4 2566
96838a40
JB		 2567 if (atomic_read(&adapter->tx_fifo_stall)) {
2568 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2569 E1000_READ_REG(&adapter->hw, TDH)) &&
2570 (E1000_READ_REG(&adapter->hw, TDFT) ==
2571 E1000_READ_REG(&adapter->hw, TDFH)) &&
2572 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2573 E1000_READ_REG(&adapter->hw, TDFHS))) {
2574 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2575 E1000_WRITE_REG(&adapter->hw, TCTL,
2576 tctl & ~E1000_TCTL_EN);
2577 E1000_WRITE_REG(&adapter->hw, TDFT,
2578 adapter->tx_head_addr);
2579 E1000_WRITE_REG(&adapter->hw, TDFH,
2580 adapter->tx_head_addr);
2581 E1000_WRITE_REG(&adapter->hw, TDFTS,
2582 adapter->tx_head_addr);
2583 E1000_WRITE_REG(&adapter->hw, TDFHS,
2584 adapter->tx_head_addr);
2585 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2586 E1000_WRITE_FLUSH(&adapter->hw);
2587
2588 adapter->tx_fifo_head = 0;
2589 atomic_set(&adapter->tx_fifo_stall, 0);
2590 netif_wake_queue(netdev);
2591 } else {
2592 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2593 }
2594 }
2595}
2596
2597/**
2598 * e1000_watchdog - Timer Call-back
2599 * @data: pointer to adapter cast into an unsigned long
2600 **/
2601static void
2602e1000_watchdog(unsigned long data)
2603{
2604 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1da177e4 2605 struct net_device *netdev = adapter->netdev;
545c67c0 2606 struct e1000_tx_ring *txdr = adapter->tx_ring;
406874a7
JP		 2607 u32 link, tctl;
2608 s32 ret_val;
cd94dd0b
AK		 2609
2610 ret_val = e1000_check_for_link(&adapter->hw);
2611 if ((ret_val == E1000_ERR_PHY) &&
2612 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2613 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2614 /* See e1000_kumeran_lock_loss_workaround() */
2615 DPRINTK(LINK, INFO,
2616 "Gigabit has been disabled, downgrading speed\n");
2617 }
90fb5135 2618
2d7edb92
MC		 2619 if (adapter->hw.mac_type == e1000_82573) {
2620 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2621 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2622 e1000_update_mng_vlan(adapter);
96838a40 2623 }
1da177e4 2624
96838a40 2625 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2626 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2627 link = !adapter->hw.serdes_link_down;
2628 else
2629 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2630
96838a40
JB		 2631 if (link) {
2632 if (!netif_carrier_ok(netdev)) {
406874a7 2633 u32 ctrl;
c3033b01 2634 bool txb2b = true;
1da177e4
LT		 2635 e1000_get_speed_and_duplex(&adapter->hw,
2636 &adapter->link_speed,
2637 &adapter->link_duplex);
2638
9669f53b
AK		 2639 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
2640 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s, "
2641 "Flow Control: %s\n",
2642 adapter->link_speed,
2643 adapter->link_duplex == FULL_DUPLEX ?
2644 "Full Duplex" : "Half Duplex",
2645 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2646 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2647 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2648 E1000_CTRL_TFCE) ? "TX" : "None" )));
1da177e4 2649
7e6c9861
JK		 2650 /* tweak tx_queue_len according to speed/duplex
2651 * and adjust the timeout factor */
66a2b0a3
JK		 2652 netdev->tx_queue_len = adapter->tx_queue_len;
2653 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2654 switch (adapter->link_speed) {
2655 case SPEED_10:
c3033b01 2656 txb2b = false;
7e6c9861
JK		 2657 netdev->tx_queue_len = 10;
2658 adapter->tx_timeout_factor = 8;
2659 break;
2660 case SPEED_100:
c3033b01 2661 txb2b = false;
7e6c9861
JK		 2662 netdev->tx_queue_len = 100;
2663 /* maybe add some timeout factor ? */
2664 break;
2665 }
2666
fe7fe28e 2667 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2668 adapter->hw.mac_type == e1000_82572) &&
c3033b01 2669 !txb2b) {
406874a7 2670 u32 tarc0;
7e6c9861 2671 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
90fb5135 2672 tarc0 &= ~(1 << 21);
7e6c9861
JK		 2673 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2674 }
90fb5135 2675
7e6c9861
JK		 2676 /* disable TSO for pcie and 10/100 speeds, to avoid
2677 * some hardware issues */
2678 if (!adapter->tso_force &&
2679 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2680 switch (adapter->link_speed) {
2681 case SPEED_10:
66a2b0a3 2682 case SPEED_100:
7e6c9861
JK		 2683 DPRINTK(PROBE,INFO,
2684 "10/100 speed: disabling TSO\n");
2685 netdev->features &= ~NETIF_F_TSO;
87ca4e5b 2686 netdev->features &= ~NETIF_F_TSO6;
7e6c9861
JK		 2687 break;
2688 case SPEED_1000:
2689 netdev->features |= NETIF_F_TSO;
87ca4e5b 2690 netdev->features |= NETIF_F_TSO6;
7e6c9861
JK		 2691 break;
2692 default:
2693 /* oops */
66a2b0a3
JK		 2694 break;
2695 }
2696 }
7e6c9861
JK		 2697
2698 /* enable transmits in the hardware, need to do this
2699 * after setting TARC0 */
2700 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2701 tctl |= E1000_TCTL_EN;
2702 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2703
1da177e4
LT		 2704 netif_carrier_on(netdev);
2705 netif_wake_queue(netdev);
56e1393f 2706 mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ));
1da177e4 2707 adapter->smartspeed = 0;
bb8e3311
JG		 2708 } else {
2709 /* make sure the receive unit is started */
2710 if (adapter->hw.rx_needs_kicking) {
2711 struct e1000_hw *hw = &adapter->hw;
406874a7 2712 u32 rctl = E1000_READ_REG(hw, RCTL);
bb8e3311
JG		 2713 E1000_WRITE_REG(hw, RCTL, rctl | E1000_RCTL_EN);
2714 }
1da177e4
LT		 2715 }
2716 } else {
96838a40 2717 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2718 adapter->link_speed = 0;
2719 adapter->link_duplex = 0;
2720 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2721 netif_carrier_off(netdev);
2722 netif_stop_queue(netdev);
56e1393f 2723 mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ));
87041639
JK		 2724
2725 /* 80003ES2LAN workaround--
2726 * For packet buffer work-around on link down event;
2727 * disable receives in the ISR and
2728 * reset device here in the watchdog
2729 */
8fc897b0 2730 if (adapter->hw.mac_type == e1000_80003es2lan)
87041639
JK		 2731 /* reset device */
2732 schedule_work(&adapter->reset_task);
1da177e4
LT		 2733 }
2734
2735 e1000_smartspeed(adapter);
2736 }
2737
2738 e1000_update_stats(adapter);
2739
2740 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2741 adapter->tpt_old = adapter->stats.tpt;
2742 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2743 adapter->colc_old = adapter->stats.colc;
2744
2745 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2746 adapter->gorcl_old = adapter->stats.gorcl;
2747 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2748 adapter->gotcl_old = adapter->stats.gotcl;
2749
2750 e1000_update_adaptive(&adapter->hw);
2751
f56799ea 2752 if (!netif_carrier_ok(netdev)) {
581d708e 2753 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2754 /* We've lost link, so the controller stops DMA,
2755 * but we've got queued Tx work that's never going
2756 * to get done, so reset controller to flush Tx.
2757 * (Do the reset outside of interrupt context). */
87041639
JK		 2758 adapter->tx_timeout_count++;
2759 schedule_work(&adapter->reset_task);
1da177e4
LT		 2760 }
2761 }
2762
1da177e4
LT		 2763 /* Cause software interrupt to ensure rx ring is cleaned */
2764 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2765
2648345f 2766 /* Force detection of hung controller every watchdog period */
c3033b01 2767 adapter->detect_tx_hung = true;
1da177e4 2768
96838a40 2769 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2770 * reset from the other port. Set the appropriate LAA in RAR[0] */
2771 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2772 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2773
1da177e4 2774 /* Reset the timer */
56e1393f 2775 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
1da177e4
LT		 2776}
2777
835bb129
JB		 2778enum latency_range {
2779 lowest_latency = 0,
2780 low_latency = 1,
2781 bulk_latency = 2,
2782 latency_invalid = 255
2783};
2784
2785/**
2786 * e1000_update_itr - update the dynamic ITR value based on statistics
2787 * Stores a new ITR value based on packets and byte
2788 * counts during the last interrupt. The advantage of per interrupt
2789 * computation is faster updates and more accurate ITR for the current
2790 * traffic pattern. Constants in this function were computed
2791 * based on theoretical maximum wire speed and thresholds were set based
2792 * on testing data as well as attempting to minimize response time
2793 * while increasing bulk throughput.
2794 * this functionality is controlled by the InterruptThrottleRate module
2795 * parameter (see e1000_param.c)
2796 * @adapter: pointer to adapter
2797 * @itr_setting: current adapter->itr
2798 * @packets: the number of packets during this measurement interval
2799 * @bytes: the number of bytes during this measurement interval
2800 **/
2801static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
406874a7 2802 u16 itr_setting,
835bb129
JB		 2803 int packets,
2804 int bytes)
2805{
2806 unsigned int retval = itr_setting;
2807 struct e1000_hw *hw = &adapter->hw;
2808
2809 if (unlikely(hw->mac_type < e1000_82540))
2810 goto update_itr_done;
2811
2812 if (packets == 0)
2813 goto update_itr_done;
2814
835bb129
JB		 2815 switch (itr_setting) {
2816 case lowest_latency:
2b65326e
JB		 2817 /* jumbo frames get bulk treatment*/
2818 if (bytes/packets > 8000)
2819 retval = bulk_latency;
2820 else if ((packets < 5) && (bytes > 512))
835bb129
JB		 2821 retval = low_latency;
2822 break;
2823 case low_latency: /* 50 usec aka 20000 ints/s */
2824 if (bytes > 10000) {
2b65326e
JB		 2825 /* jumbo frames need bulk latency setting */
2826 if (bytes/packets > 8000)
2827 retval = bulk_latency;
2828 else if ((packets < 10) || ((bytes/packets) > 1200))
835bb129
JB		 2829 retval = bulk_latency;
2830 else if ((packets > 35))
2831 retval = lowest_latency;
2b65326e
JB		 2832 } else if (bytes/packets > 2000)
2833 retval = bulk_latency;
2834 else if (packets <= 2 && bytes < 512)
835bb129
JB		 2835 retval = lowest_latency;
2836 break;
2837 case bulk_latency: /* 250 usec aka 4000 ints/s */
2838 if (bytes > 25000) {
2839 if (packets > 35)
2840 retval = low_latency;
2b65326e
JB		 2841 } else if (bytes < 6000) {
2842 retval = low_latency;
835bb129
JB		 2843 }
2844 break;
2845 }
2846
2847update_itr_done:
2848 return retval;
2849}
2850
2851static void e1000_set_itr(struct e1000_adapter *adapter)
2852{
2853 struct e1000_hw *hw = &adapter->hw;
406874a7
JP		 2854 u16 current_itr;
2855 u32 new_itr = adapter->itr;
835bb129
JB		 2856
2857 if (unlikely(hw->mac_type < e1000_82540))
2858 return;
2859
2860 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2861 if (unlikely(adapter->link_speed != SPEED_1000)) {
2862 current_itr = 0;
2863 new_itr = 4000;
2864 goto set_itr_now;
2865 }
2866
2867 adapter->tx_itr = e1000_update_itr(adapter,
2868 adapter->tx_itr,
2869 adapter->total_tx_packets,
2870 adapter->total_tx_bytes);
2b65326e
JB		 2871 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2872 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2873 adapter->tx_itr = low_latency;
2874
835bb129
JB		 2875 adapter->rx_itr = e1000_update_itr(adapter,
2876 adapter->rx_itr,
2877 adapter->total_rx_packets,
2878 adapter->total_rx_bytes);
2b65326e
JB		 2879 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2880 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2881 adapter->rx_itr = low_latency;
835bb129
JB		 2882
2883 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2884
835bb129
JB		 2885 switch (current_itr) {
2886 /* counts and packets in update_itr are dependent on these numbers */
2887 case lowest_latency:
2888 new_itr = 70000;
2889 break;
2890 case low_latency:
2891 new_itr = 20000; /* aka hwitr = ~200 */
2892 break;
2893 case bulk_latency:
2894 new_itr = 4000;
2895 break;
2896 default:
2897 break;
2898 }
2899
2900set_itr_now:
2901 if (new_itr != adapter->itr) {
2902 /* this attempts to bias the interrupt rate towards Bulk
2903 * by adding intermediate steps when interrupt rate is
2904 * increasing */
2905 new_itr = new_itr > adapter->itr ?
2906 min(adapter->itr + (new_itr >> 2), new_itr) :
2907 new_itr;
2908 adapter->itr = new_itr;
2909 E1000_WRITE_REG(hw, ITR, 1000000000 / (new_itr * 256));
2910 }
2911
2912 return;
2913}
2914
1da177e4
LT		 2915#define E1000_TX_FLAGS_CSUM 0x00000001
2916#define E1000_TX_FLAGS_VLAN 0x00000002
2917#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2918#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2919#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2920#define E1000_TX_FLAGS_VLAN_SHIFT 16
2921
e619d523 2922static int
581d708e
MC		 2923e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2924 struct sk_buff *skb)
1da177e4 2925{
1da177e4 2926 struct e1000_context_desc *context_desc;
545c67c0 2927 struct e1000_buffer *buffer_info;
1da177e4 2928 unsigned int i;
406874a7
JP		 2929 u32 cmd_length = 0;
2930 u16 ipcse = 0, tucse, mss;
2931 u8 ipcss, ipcso, tucss, tucso, hdr_len;
1da177e4
LT		 2932 int err;
2933
89114afd 2934 if (skb_is_gso(skb)) {
1da177e4
LT		 2935 if (skb_header_cloned(skb)) {
2936 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2937 if (err)
2938 return err;
2939 }
2940
ab6a5bb6 2941 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
7967168c 2942 mss = skb_shinfo(skb)->gso_size;
60828236 2943 if (skb->protocol == htons(ETH_P_IP)) {
eddc9ec5
ACM		 2944 struct iphdr *iph = ip_hdr(skb);
2945 iph->tot_len = 0;
2946 iph->check = 0;
aa8223c7
ACM		 2947 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2948 iph->daddr, 0,
2949 IPPROTO_TCP,
2950 0);
2d7edb92 2951 cmd_length = E1000_TXD_CMD_IP;
ea2ae17d 2952 ipcse = skb_transport_offset(skb) - 1;
e15fdd03 2953 } else if (skb->protocol == htons(ETH_P_IPV6)) {
0660e03f 2954 ipv6_hdr(skb)->payload_len = 0;
aa8223c7 2955 tcp_hdr(skb)->check =
0660e03f
ACM		 2956 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2957 &ipv6_hdr(skb)->daddr,
2958 0, IPPROTO_TCP, 0);
2d7edb92 2959 ipcse = 0;
2d7edb92 2960 }
bbe735e4 2961 ipcss = skb_network_offset(skb);
eddc9ec5 2962 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
ea2ae17d 2963 tucss = skb_transport_offset(skb);
aa8223c7 2964 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
1da177e4
LT		 2965 tucse = 0;
2966
2967 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2968 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2969
581d708e
MC		 2970 i = tx_ring->next_to_use;
2971 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2972 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2973
2974 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2975 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2976 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2977 context_desc->upper_setup.tcp_fields.tucss = tucss;
2978 context_desc->upper_setup.tcp_fields.tucso = tucso;
2979 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2980 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2981 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2982 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2983
545c67c0 2984 buffer_info->time_stamp = jiffies;
a9ebadd6 2985 buffer_info->next_to_watch = i;
545c67c0 2986
581d708e
MC		 2987 if (++i == tx_ring->count) i = 0;
2988 tx_ring->next_to_use = i;
1da177e4 2989
c3033b01 2990 return true;
1da177e4 2991 }
c3033b01 2992 return false;
1da177e4
LT		 2993}
2994
c3033b01 2995static bool
581d708e
MC		 2996e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2997 struct sk_buff *skb)
1da177e4
LT		 2998{
2999 struct e1000_context_desc *context_desc;
545c67c0 3000 struct e1000_buffer *buffer_info;
1da177e4 3001 unsigned int i;
406874a7 3002 u8 css;
1da177e4 3003
84fa7933 3004 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 3005 css = skb_transport_offset(skb);
1da177e4 3006
581d708e 3007 i = tx_ring->next_to_use;
545c67c0 3008 buffer_info = &tx_ring->buffer_info[i];
581d708e 3009 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4 3010
f6c57baf 3011 context_desc->lower_setup.ip_config = 0;
1da177e4 3012 context_desc->upper_setup.tcp_fields.tucss = css;
628592cc
HX		 3013 context_desc->upper_setup.tcp_fields.tucso =
3014 css + skb->csum_offset;
1da177e4
LT		 3015 context_desc->upper_setup.tcp_fields.tucse = 0;
3016 context_desc->tcp_seg_setup.data = 0;
3017 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
3018
545c67c0 3019 buffer_info->time_stamp = jiffies;
a9ebadd6 3020 buffer_info->next_to_watch = i;
545c67c0 3021
581d708e
MC		 3022 if (unlikely(++i == tx_ring->count)) i = 0;
3023 tx_ring->next_to_use = i;
1da177e4 3024
c3033b01 3025 return true;
1da177e4
LT		 3026 }
3027
c3033b01 3028 return false;
1da177e4
LT		 3029}
3030
3031#define E1000_MAX_TXD_PWR 12
3032#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
3033
e619d523 3034static int
581d708e
MC		 3035e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
3036 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
3037 unsigned int nr_frags, unsigned int mss)
1da177e4 3038{
1da177e4
LT		 3039 struct e1000_buffer *buffer_info;
3040 unsigned int len = skb->len;
3041 unsigned int offset = 0, size, count = 0, i;
3042 unsigned int f;
3043 len -= skb->data_len;
3044
3045 i = tx_ring->next_to_use;
3046
96838a40 3047 while (len) {
1da177e4
LT		 3048 buffer_info = &tx_ring->buffer_info[i];
3049 size = min(len, max_per_txd);
fd803241
JK		 3050 /* Workaround for Controller erratum --
3051 * descriptor for non-tso packet in a linear SKB that follows a
3052 * tso gets written back prematurely before the data is fully
0f15a8fa 3053 * DMA'd to the controller */
fd803241 3054 if (!skb->data_len && tx_ring->last_tx_tso &&
89114afd 3055 !skb_is_gso(skb)) {
fd803241
JK		 3056 tx_ring->last_tx_tso = 0;
3057 size -= 4;
3058 }
3059
1da177e4
LT		 3060 /* Workaround for premature desc write-backs
3061 * in TSO mode. Append 4-byte sentinel desc */
96838a40 3062 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4 3063 size -= 4;
97338bde
MC		 3064 /* work-around for errata 10 and it applies
3065 * to all controllers in PCI-X mode
3066 * The fix is to make sure that the first descriptor of a
3067 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
3068 */
96838a40 3069 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3070 (size > 2015) && count == 0))
3071 size = 2015;
96838a40 3072
1da177e4
LT		 3073 /* Workaround for potential 82544 hang in PCI-X. Avoid
3074 * terminating buffers within evenly-aligned dwords. */
96838a40 3075 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 3076 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
3077 size > 4))
3078 size -= 4;
3079
3080 buffer_info->length = size;
3081 buffer_info->dma =
3082 pci_map_single(adapter->pdev,
3083 skb->data + offset,
3084 size,
3085 PCI_DMA_TODEVICE);
3086 buffer_info->time_stamp = jiffies;
a9ebadd6 3087 buffer_info->next_to_watch = i;
1da177e4
LT		 3088
3089 len -= size;
3090 offset += size;
3091 count++;
96838a40 3092 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3093 }
3094
96838a40 3095 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 3096 struct skb_frag_struct *frag;
3097
3098 frag = &skb_shinfo(skb)->frags[f];
3099 len = frag->size;
3100 offset = frag->page_offset;
3101
96838a40 3102 while (len) {
1da177e4
LT		 3103 buffer_info = &tx_ring->buffer_info[i];
3104 size = min(len, max_per_txd);
1da177e4
LT		 3105 /* Workaround for premature desc write-backs
3106 * in TSO mode. Append 4-byte sentinel desc */
96838a40 3107 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4 3108 size -= 4;
1da177e4
LT		 3109 /* Workaround for potential 82544 hang in PCI-X.
3110 * Avoid terminating buffers within evenly-aligned
3111 * dwords. */
96838a40 3112 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 3113 !((unsigned long)(frag->page+offset+size-1) & 4) &&
3114 size > 4))
3115 size -= 4;
3116
3117 buffer_info->length = size;
3118 buffer_info->dma =
3119 pci_map_page(adapter->pdev,
3120 frag->page,
3121 offset,
3122 size,
3123 PCI_DMA_TODEVICE);
3124 buffer_info->time_stamp = jiffies;
a9ebadd6 3125 buffer_info->next_to_watch = i;
1da177e4
LT		 3126
3127 len -= size;
3128 offset += size;
3129 count++;
96838a40 3130 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3131 }
3132 }
3133
3134 i = (i == 0) ? tx_ring->count - 1 : i - 1;
3135 tx_ring->buffer_info[i].skb = skb;
3136 tx_ring->buffer_info[first].next_to_watch = i;
3137
3138 return count;
3139}
3140
e619d523 3141static void
581d708e
MC		 3142e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
3143 int tx_flags, int count)
1da177e4 3144{
1da177e4
LT		 3145 struct e1000_tx_desc *tx_desc = NULL;
3146 struct e1000_buffer *buffer_info;
406874a7 3147 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
1da177e4
LT		 3148 unsigned int i;
3149
96838a40 3150 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 3151 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
3152 E1000_TXD_CMD_TSE;
2d7edb92
MC		 3153 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
3154
96838a40 3155 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 3156 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 3157 }
3158
96838a40 3159 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 3160 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
3161 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
3162 }
3163
96838a40 3164 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 3165 txd_lower |= E1000_TXD_CMD_VLE;
3166 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
3167 }
3168
3169 i = tx_ring->next_to_use;
3170
96838a40 3171 while (count--) {
1da177e4
LT		 3172 buffer_info = &tx_ring->buffer_info[i];
3173 tx_desc = E1000_TX_DESC(*tx_ring, i);
3174 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3175 tx_desc->lower.data =
3176 cpu_to_le32(txd_lower | buffer_info->length);
3177 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 3178 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3179 }
3180
3181 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
3182
3183 /* Force memory writes to complete before letting h/w
3184 * know there are new descriptors to fetch. (Only
3185 * applicable for weak-ordered memory model archs,
3186 * such as IA-64). */
3187 wmb();
3188
3189 tx_ring->next_to_use = i;
581d708e 3190 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
2ce9047f
JB		 3191 /* we need this if more than one processor can write to our tail
3192 * at a time, it syncronizes IO on IA64/Altix systems */
3193 mmiowb();
1da177e4
LT		 3194}
3195
3196/**
3197 * 82547 workaround to avoid controller hang in half-duplex environment.
3198 * The workaround is to avoid queuing a large packet that would span
3199 * the internal Tx FIFO ring boundary by notifying the stack to resend
3200 * the packet at a later time. This gives the Tx FIFO an opportunity to
3201 * flush all packets. When that occurs, we reset the Tx FIFO pointers
3202 * to the beginning of the Tx FIFO.
3203 **/
3204
3205#define E1000_FIFO_HDR 0x10
3206#define E1000_82547_PAD_LEN 0x3E0
3207
e619d523 3208static int
1da177e4
LT		 3209e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
3210{
406874a7
JP		 3211 u32 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
3212 u32 skb_fifo_len = skb->len + E1000_FIFO_HDR;
1da177e4 3213
9099cfb9 3214 skb_fifo_len = ALIGN(skb_fifo_len, E1000_FIFO_HDR);
1da177e4 3215
96838a40 3216 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 3217 goto no_fifo_stall_required;
3218
96838a40 3219 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 3220 return 1;
3221
96838a40 3222 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 3223 atomic_set(&adapter->tx_fifo_stall, 1);
3224 return 1;
3225 }
3226
3227no_fifo_stall_required:
3228 adapter->tx_fifo_head += skb_fifo_len;
96838a40 3229 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 3230 adapter->tx_fifo_head -= adapter->tx_fifo_size;
3231 return 0;
3232}
3233
2d7edb92 3234#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 3235static int
2d7edb92
MC		 3236e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
3237{
3238 struct e1000_hw *hw = &adapter->hw;
406874a7 3239 u16 length, offset;
96838a40
JB		 3240 if (vlan_tx_tag_present(skb)) {
3241 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 3242 ( adapter->hw.mng_cookie.status &
3243 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
3244 return 0;
3245 }
20a44028 3246 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 3247 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 3248 if ((htons(ETH_P_IP) == eth->h_proto)) {
3249 const struct iphdr *ip =
406874a7 3250 (struct iphdr *)((u8 *)skb->data+14);
96838a40
JB		 3251 if (IPPROTO_UDP == ip->protocol) {
3252 struct udphdr *udp =
406874a7 3253 (struct udphdr *)((u8 *)ip +
2d7edb92 3254 (ip->ihl << 2));
96838a40 3255 if (ntohs(udp->dest) == 67) {
406874a7 3256 offset = (u8 *)udp + 8 - skb->data;
2d7edb92
MC		 3257 length = skb->len - offset;
3258
3259 return e1000_mng_write_dhcp_info(hw,
406874a7 3260 (u8 *)udp + 8,
2d7edb92
MC		 3261 length);
3262 }
3263 }
3264 }
3265 }
3266 return 0;
3267}
3268
65c7973f
JB		 3269static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
3270{
3271 struct e1000_adapter *adapter = netdev_priv(netdev);
3272 struct e1000_tx_ring *tx_ring = adapter->tx_ring;
3273
3274 netif_stop_queue(netdev);
3275 /* Herbert's original patch had:
3276 * smp_mb__after_netif_stop_queue();
3277 * but since that doesn't exist yet, just open code it. */
3278 smp_mb();
3279
3280 /* We need to check again in a case another CPU has just
3281 * made room available. */
3282 if (likely(E1000_DESC_UNUSED(tx_ring) < size))
3283 return -EBUSY;
3284
3285 /* A reprieve! */
3286 netif_start_queue(netdev);
fcfb1224 3287 ++adapter->restart_queue;
65c7973f
JB		 3288 return 0;
3289}
3290
3291static int e1000_maybe_stop_tx(struct net_device *netdev,
3292 struct e1000_tx_ring *tx_ring, int size)
3293{
3294 if (likely(E1000_DESC_UNUSED(tx_ring) >= size))
3295 return 0;
3296 return __e1000_maybe_stop_tx(netdev, size);
3297}
3298
1da177e4
LT		 3299#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
3300static int
3301e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3302{
60490fe0 3303 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 3304 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 3305 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
3306 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
3307 unsigned int tx_flags = 0;
6d1e3aa7 3308 unsigned int len = skb->len - skb->data_len;
1da177e4 3309 unsigned long flags;
6d1e3aa7
KK		 3310 unsigned int nr_frags;
3311 unsigned int mss;
1da177e4 3312 int count = 0;
76c224bc 3313 int tso;
1da177e4 3314 unsigned int f;
1da177e4 3315
65c7973f
JB		 3316 /* This goes back to the question of how to logically map a tx queue
3317 * to a flow. Right now, performance is impacted slightly negatively
3318 * if using multiple tx queues. If the stack breaks away from a
3319 * single qdisc implementation, we can look at this again. */
581d708e 3320 tx_ring = adapter->tx_ring;
24025e4e 3321
581d708e 3322 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 3323 dev_kfree_skb_any(skb);
3324 return NETDEV_TX_OK;
3325 }
3326
032fe6e9
JB		 3327 /* 82571 and newer doesn't need the workaround that limited descriptor
3328 * length to 4kB */
3329 if (adapter->hw.mac_type >= e1000_82571)
3330 max_per_txd = 8192;
3331
7967168c 3332 mss = skb_shinfo(skb)->gso_size;
76c224bc 3333 /* The controller does a simple calculation to
1da177e4
LT		 3334 * make sure there is enough room in the FIFO before
3335 * initiating the DMA for each buffer. The calc is:
3336 * 4 = ceil(buffer len/mss). To make sure we don't
3337 * overrun the FIFO, adjust the max buffer len if mss
3338 * drops. */
96838a40 3339 if (mss) {
406874a7 3340 u8 hdr_len;
1da177e4
LT		 3341 max_per_txd = min(mss << 2, max_per_txd);
3342 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 3343
90fb5135
AK		 3344 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
3345 * points to just header, pull a few bytes of payload from
3346 * frags into skb->data */
ab6a5bb6 3347 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
6d1e3aa7 3348 if (skb->data_len && hdr_len == len) {
9f687888
JK		 3349 switch (adapter->hw.mac_type) {
3350 unsigned int pull_size;
683a2aa3
HX		 3351 case e1000_82544:
3352 /* Make sure we have room to chop off 4 bytes,
3353 * and that the end alignment will work out to
3354 * this hardware's requirements
3355 * NOTE: this is a TSO only workaround
3356 * if end byte alignment not correct move us
3357 * into the next dword */
27a884dc 3358 if ((unsigned long)(skb_tail_pointer(skb) - 1) & 4)
683a2aa3
HX		 3359 break;
3360 /* fall through */
9f687888
JK		 3361 case e1000_82571:
3362 case e1000_82572:
3363 case e1000_82573:
cd94dd0b 3364 case e1000_ich8lan:
9f687888
JK		 3365 pull_size = min((unsigned int)4, skb->data_len);
3366 if (!__pskb_pull_tail(skb, pull_size)) {
a5eafce2 3367 DPRINTK(DRV, ERR,
9f687888
JK		 3368 "__pskb_pull_tail failed.\n");
3369 dev_kfree_skb_any(skb);
749dfc70 3370 return NETDEV_TX_OK;
9f687888
JK		 3371 }
3372 len = skb->len - skb->data_len;
3373 break;
3374 default:
3375 /* do nothing */
3376 break;
d74bbd3b 3377 }
9a3056da 3378 }
1da177e4
LT		 3379 }
3380
9a3056da 3381 /* reserve a descriptor for the offload context */
84fa7933 3382 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
1da177e4 3383 count++;
2648345f 3384 count++;
fd803241 3385
fd803241 3386 /* Controller Erratum workaround */
89114afd 3387 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
fd803241 3388 count++;
fd803241 3389
1da177e4
LT		 3390 count += TXD_USE_COUNT(len, max_txd_pwr);
3391
96838a40 3392 if (adapter->pcix_82544)
1da177e4
LT		 3393 count++;
3394
96838a40 3395 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 3396 * in PCI-X mode, so add one more descriptor to the count
3397 */
96838a40 3398 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3399 (len > 2015)))
3400 count++;
3401
1da177e4 3402 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 3403 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 3404 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
3405 max_txd_pwr);
96838a40 3406 if (adapter->pcix_82544)
1da177e4
LT		 3407 count += nr_frags;
3408
0f15a8fa
JK		 3409
3410 if (adapter->hw.tx_pkt_filtering &&
3411 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 3412 e1000_transfer_dhcp_info(adapter, skb);
3413
f50393fe 3414 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags))
581d708e 3415 /* Collision - tell upper layer to requeue */
581d708e 3416 return NETDEV_TX_LOCKED;
1da177e4
LT		 3417
3418 /* need: count + 2 desc gap to keep tail from touching
3419 * head, otherwise try next time */
65c7973f 3420 if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2))) {
581d708e 3421 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3422 return NETDEV_TX_BUSY;
3423 }
3424
96838a40
JB		 3425 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
3426 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4 3427 netif_stop_queue(netdev);
1314bbf3 3428 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
581d708e 3429 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3430 return NETDEV_TX_BUSY;
3431 }
3432 }
3433
96838a40 3434 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 3435 tx_flags |= E1000_TX_FLAGS_VLAN;
3436 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
3437 }
3438
581d708e 3439 first = tx_ring->next_to_use;
96838a40 3440
581d708e 3441 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 3442 if (tso < 0) {
3443 dev_kfree_skb_any(skb);
581d708e 3444 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3445 return NETDEV_TX_OK;
3446 }
3447
fd803241
JK		 3448 if (likely(tso)) {
3449 tx_ring->last_tx_tso = 1;
1da177e4 3450 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 3451 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 3452 tx_flags |= E1000_TX_FLAGS_CSUM;
3453
2d7edb92 3454 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 3455 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 3456 * no longer assume, we must. */
60828236 3457 if (likely(skb->protocol == htons(ETH_P_IP)))
2d7edb92
MC		 3458 tx_flags |= E1000_TX_FLAGS_IPV4;
3459
581d708e
MC		 3460 e1000_tx_queue(adapter, tx_ring, tx_flags,
3461 e1000_tx_map(adapter, tx_ring, skb, first,
3462 max_per_txd, nr_frags, mss));
1da177e4
LT		 3463
3464 netdev->trans_start = jiffies;
3465
3466 /* Make sure there is space in the ring for the next send. */
65c7973f 3467 e1000_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 2);
1da177e4 3468
581d708e 3469 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3470 return NETDEV_TX_OK;
3471}
3472
3473/**
3474 * e1000_tx_timeout - Respond to a Tx Hang
3475 * @netdev: network interface device structure
3476 **/
3477
3478static void
3479e1000_tx_timeout(struct net_device *netdev)
3480{
60490fe0 3481 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3482
3483 /* Do the reset outside of interrupt context */
87041639
JK		 3484 adapter->tx_timeout_count++;
3485 schedule_work(&adapter->reset_task);
1da177e4
LT		 3486}
3487
3488static void
65f27f38 3489e1000_reset_task(struct work_struct *work)
1da177e4 3490{
65f27f38
DH		 3491 struct e1000_adapter *adapter =
3492 container_of(work, struct e1000_adapter, reset_task);
1da177e4 3493
2db10a08 3494 e1000_reinit_locked(adapter);
1da177e4
LT		 3495}
3496
3497/**
3498 * e1000_get_stats - Get System Network Statistics
3499 * @netdev: network interface device structure
3500 *
3501 * Returns the address of the device statistics structure.
3502 * The statistics are actually updated from the timer callback.
3503 **/
3504
3505static struct net_device_stats *
3506e1000_get_stats(struct net_device *netdev)
3507{
60490fe0 3508 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3509
6b7660cd 3510 /* only return the current stats */
1da177e4
LT		 3511 return &adapter->net_stats;
3512}
3513
3514/**
3515 * e1000_change_mtu - Change the Maximum Transfer Unit
3516 * @netdev: network interface device structure
3517 * @new_mtu: new value for maximum frame size
3518 *
3519 * Returns 0 on success, negative on failure
3520 **/
3521
3522static int
3523e1000_change_mtu(struct net_device *netdev, int new_mtu)
3524{
60490fe0 3525 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3526 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
406874a7 3527 u16 eeprom_data = 0;
1da177e4 3528
96838a40
JB		 3529 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3530 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3531 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3532 return -EINVAL;
2d7edb92 3533 }
1da177e4 3534
997f5cbd
JK		 3535 /* Adapter-specific max frame size limits. */
3536 switch (adapter->hw.mac_type) {
9e2feace 3537 case e1000_undefined ... e1000_82542_rev2_1:
cd94dd0b 3538 case e1000_ich8lan:
997f5cbd
JK		 3539 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3540 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3541 return -EINVAL;
2d7edb92 3542 }
997f5cbd 3543 break;
85b22eb6 3544 case e1000_82573:
249d71d6
BA		 3545 /* Jumbo Frames not supported if:
3546 * - this is not an 82573L device
3547 * - ASPM is enabled in any way (0x1A bits 3:2) */
85b22eb6
JK		 3548 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
3549 &eeprom_data);
249d71d6
BA		 3550 if ((adapter->hw.device_id != E1000_DEV_ID_82573L) ||
3551 (eeprom_data & EEPROM_WORD1A_ASPM_MASK)) {
85b22eb6
JK		 3552 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3553 DPRINTK(PROBE, ERR,
3554 "Jumbo Frames not supported.\n");
3555 return -EINVAL;
3556 }
3557 break;
3558 }
249d71d6
BA		 3559 /* ERT will be enabled later to enable wire speed receives */
3560
85b22eb6 3561 /* fall through to get support */
997f5cbd
JK		 3562 case e1000_82571:
3563 case e1000_82572:
87041639 3564 case e1000_80003es2lan:
997f5cbd
JK		 3565#define MAX_STD_JUMBO_FRAME_SIZE 9234
3566 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3567 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3568 return -EINVAL;
3569 }
3570 break;
3571 default:
3572 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3573 break;
1da177e4
LT		 3574 }
3575
87f5032e 3576 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
9e2feace
AK		 3577 * means we reserve 2 more, this pushes us to allocate from the next
3578 * larger slab size
3579 * i.e. RXBUFFER_2048 --> size-4096 slab */
3580
3581 if (max_frame <= E1000_RXBUFFER_256)
3582 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3583 else if (max_frame <= E1000_RXBUFFER_512)
3584 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3585 else if (max_frame <= E1000_RXBUFFER_1024)
3586 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3587 else if (max_frame <= E1000_RXBUFFER_2048)
3588 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3589 else if (max_frame <= E1000_RXBUFFER_4096)
3590 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3591 else if (max_frame <= E1000_RXBUFFER_8192)
3592 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3593 else if (max_frame <= E1000_RXBUFFER_16384)
3594 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3595
3596 /* adjust allocation if LPE protects us, and we aren't using SBP */
9e2feace
AK		 3597 if (!adapter->hw.tbi_compatibility_on &&
3598 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3599 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3600 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3601
2d7edb92 3602 netdev->mtu = new_mtu;
83cd8279 3603 adapter->hw.max_frame_size = max_frame;
2d7edb92 3604
2db10a08
AK		 3605 if (netif_running(netdev))
3606 e1000_reinit_locked(adapter);
1da177e4 3607
1da177e4
LT		 3608 return 0;
3609}
3610
3611/**
3612 * e1000_update_stats - Update the board statistics counters
3613 * @adapter: board private structure
3614 **/
3615
3616void
3617e1000_update_stats(struct e1000_adapter *adapter)
3618{
3619 struct e1000_hw *hw = &adapter->hw;
282f33c9 3620 struct pci_dev *pdev = adapter->pdev;
1da177e4 3621 unsigned long flags;
406874a7 3622 u16 phy_tmp;
1da177e4
LT		 3623
3624#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3625
282f33c9
LV		 3626 /*
3627 * Prevent stats update while adapter is being reset, or if the pci
3628 * connection is down.
3629 */
9026729b 3630 if (adapter->link_speed == 0)
282f33c9 3631 return;
81b1955e 3632 if (pci_channel_offline(pdev))
9026729b
AK		 3633 return;
3634
1da177e4
LT		 3635 spin_lock_irqsave(&adapter->stats_lock, flags);
3636
828d055f 3637 /* these counters are modified from e1000_tbi_adjust_stats,
1da177e4
LT		 3638 * called from the interrupt context, so they must only
3639 * be written while holding adapter->stats_lock
3640 */
3641
3642 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3643 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3644 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3645 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3646 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3647 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3648 adapter->stats.roc += E1000_READ_REG(hw, ROC);
cd94dd0b
AK		 3649
3650 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3651 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3652 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3653 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3654 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3655 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3656 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
cd94dd0b 3657 }
1da177e4
LT		 3658
3659 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3660 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3661 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3662 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3663 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3664 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3665 adapter->stats.dc += E1000_READ_REG(hw, DC);
3666 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3667 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3668 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3669 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3670 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3671 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3672 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3673 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3674 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3675 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3676 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3677 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3678 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3679 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3680 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3681 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3682 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3683 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3684 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
cd94dd0b
AK		 3685
3686 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3687 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3688 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3689 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3690 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3691 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3692 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 3693 }
3694
1da177e4
LT		 3695 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3696 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3697
3698 /* used for adaptive IFS */
3699
3700 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3701 adapter->stats.tpt += hw->tx_packet_delta;
3702 hw->collision_delta = E1000_READ_REG(hw, COLC);
3703 adapter->stats.colc += hw->collision_delta;
3704
96838a40 3705 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3706 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3707 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3708 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3709 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3710 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3711 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3712 }
96838a40 3713 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3714 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3715 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 3716
3717 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3718 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3719 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3720 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3721 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3722 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3723 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3724 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
cd94dd0b 3725 }
2d7edb92 3726 }
1da177e4
LT		 3727
3728 /* Fill out the OS statistics structure */
1da177e4
LT		 3729 adapter->net_stats.multicast = adapter->stats.mprc;
3730 adapter->net_stats.collisions = adapter->stats.colc;
3731
3732 /* Rx Errors */
3733
87041639
JK		 3734 /* RLEC on some newer hardware can be incorrect so build
3735 * our own version based on RUC and ROC */
1da177e4
LT		 3736 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3737 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3738 adapter->stats.ruc + adapter->stats.roc +
3739 adapter->stats.cexterr;
49559854
MW		 3740 adapter->stats.rlerrc = adapter->stats.ruc + adapter->stats.roc;
3741 adapter->net_stats.rx_length_errors = adapter->stats.rlerrc;
1da177e4
LT		 3742 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3743 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3744 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3745
3746 /* Tx Errors */
49559854
MW		 3747 adapter->stats.txerrc = adapter->stats.ecol + adapter->stats.latecol;
3748 adapter->net_stats.tx_errors = adapter->stats.txerrc;
1da177e4
LT		 3749 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3750 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3751 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
167fb284
JG		 3752 if (adapter->hw.bad_tx_carr_stats_fd &&
3753 adapter->link_duplex == FULL_DUPLEX) {
3754 adapter->net_stats.tx_carrier_errors = 0;
3755 adapter->stats.tncrs = 0;
3756 }
1da177e4
LT		 3757
3758 /* Tx Dropped needs to be maintained elsewhere */
3759
3760 /* Phy Stats */
96838a40
JB		 3761 if (hw->media_type == e1000_media_type_copper) {
3762 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3763 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3764 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3765 adapter->phy_stats.idle_errors += phy_tmp;
3766 }
3767
96838a40 3768 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3769 (hw->phy_type == e1000_phy_m88) &&
3770 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3771 adapter->phy_stats.receive_errors += phy_tmp;
3772 }
3773
15e376b4
JG		 3774 /* Management Stats */
3775 if (adapter->hw.has_smbus) {
3776 adapter->stats.mgptc += E1000_READ_REG(hw, MGTPTC);
3777 adapter->stats.mgprc += E1000_READ_REG(hw, MGTPRC);
3778 adapter->stats.mgpdc += E1000_READ_REG(hw, MGTPDC);
3779 }
3780
1da177e4
LT		 3781 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3782}
9ac98284
JB		 3783
3784/**
3785 * e1000_intr_msi - Interrupt Handler
3786 * @irq: interrupt number
3787 * @data: pointer to a network interface device structure
3788 **/
3789
b5fc8f0c
JB		 3790static irqreturn_t
3791e1000_intr_msi(int irq, void *data)
9ac98284
JB		 3792{
3793 struct net_device *netdev = data;
3794 struct e1000_adapter *adapter = netdev_priv(netdev);
3795 struct e1000_hw *hw = &adapter->hw;
3796#ifndef CONFIG_E1000_NAPI
3797 int i;
3798#endif
406874a7 3799 u32 icr = E1000_READ_REG(hw, ICR);
9ac98284 3800
9150b76a
JB		 3801 /* in NAPI mode read ICR disables interrupts using IAM */
3802
b5fc8f0c
JB		 3803 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3804 hw->get_link_status = 1;
3805 /* 80003ES2LAN workaround-- For packet buffer work-around on
3806 * link down event; disable receives here in the ISR and reset
3807 * adapter in watchdog */
3808 if (netif_carrier_ok(netdev) &&
3809 (adapter->hw.mac_type == e1000_80003es2lan)) {
3810 /* disable receives */
406874a7 3811 u32 rctl = E1000_READ_REG(hw, RCTL);
b5fc8f0c 3812 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
9ac98284 3813 }
b5fc8f0c
JB		 3814 /* guard against interrupt when we're going down */
3815 if (!test_bit(__E1000_DOWN, &adapter->flags))
3816 mod_timer(&adapter->watchdog_timer, jiffies + 1);
9ac98284
JB		 3817 }
3818
3819#ifdef CONFIG_E1000_NAPI
bea3348e 3820 if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) {
835bb129
JB		 3821 adapter->total_tx_bytes = 0;
3822 adapter->total_tx_packets = 0;
3823 adapter->total_rx_bytes = 0;
3824 adapter->total_rx_packets = 0;
bea3348e 3825 __netif_rx_schedule(netdev, &adapter->napi);
835bb129 3826 } else
9ac98284
JB		 3827 e1000_irq_enable(adapter);
3828#else
835bb129
JB		 3829 adapter->total_tx_bytes = 0;
3830 adapter->total_rx_bytes = 0;
3831 adapter->total_tx_packets = 0;
3832 adapter->total_rx_packets = 0;
3833
9ac98284
JB		 3834 for (i = 0; i < E1000_MAX_INTR; i++)
3835 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
46fcc86d 3836 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
9ac98284 3837 break;
835bb129
JB		 3838
3839 if (likely(adapter->itr_setting & 3))
3840 e1000_set_itr(adapter);
9ac98284
JB		 3841#endif
3842
3843 return IRQ_HANDLED;
3844}
1da177e4
LT		 3845
3846/**
3847 * e1000_intr - Interrupt Handler
3848 * @irq: interrupt number
3849 * @data: pointer to a network interface device structure
1da177e4
LT		 3850 **/
3851
3852static irqreturn_t
7d12e780 3853e1000_intr(int irq, void *data)
1da177e4
LT		 3854{
3855 struct net_device *netdev = data;
60490fe0 3856 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3857 struct e1000_hw *hw = &adapter->hw;
406874a7 3858 u32 rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3859#ifndef CONFIG_E1000_NAPI
581d708e 3860 int i;
835bb129
JB		 3861#endif
3862 if (unlikely(!icr))
3863 return IRQ_NONE; /* Not our interrupt */
3864
3865#ifdef CONFIG_E1000_NAPI
3866 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3867 * not set, then the adapter didn't send an interrupt */
3868 if (unlikely(hw->mac_type >= e1000_82571 &&
3869 !(icr & E1000_ICR_INT_ASSERTED)))
3870 return IRQ_NONE;
3871
9150b76a
JB		 3872 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3873 * need for the IMC write */
be2b28ed 3874#endif
1da177e4 3875
96838a40 3876 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3877 hw->get_link_status = 1;
87041639
JK		 3878 /* 80003ES2LAN workaround--
3879 * For packet buffer work-around on link down event;
3880 * disable receives here in the ISR and
3881 * reset adapter in watchdog
3882 */
3883 if (netif_carrier_ok(netdev) &&
3884 (adapter->hw.mac_type == e1000_80003es2lan)) {
3885 /* disable receives */
3886 rctl = E1000_READ_REG(hw, RCTL);
3887 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3888 }
1314bbf3
AK		 3889 /* guard against interrupt when we're going down */
3890 if (!test_bit(__E1000_DOWN, &adapter->flags))
3891 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1da177e4
LT		 3892 }
3893
3894#ifdef CONFIG_E1000_NAPI
1e613fd9 3895 if (unlikely(hw->mac_type < e1000_82571)) {
835bb129 3896 /* disable interrupts, without the synchronize_irq bit */
1e613fd9
JK		 3897 E1000_WRITE_REG(hw, IMC, ~0);
3898 E1000_WRITE_FLUSH(hw);
3899 }
bea3348e 3900 if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) {
835bb129
JB		 3901 adapter->total_tx_bytes = 0;
3902 adapter->total_tx_packets = 0;
3903 adapter->total_rx_bytes = 0;
3904 adapter->total_rx_packets = 0;
bea3348e 3905 __netif_rx_schedule(netdev, &adapter->napi);
835bb129 3906 } else
90fb5135
AK		 3907 /* this really should not happen! if it does it is basically a
3908 * bug, but not a hard error, so enable ints and continue */
581d708e 3909 e1000_irq_enable(adapter);
c1605eb3 3910#else
1da177e4 3911 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3912 * Due to Hub Link bus being occupied, an interrupt
3913 * de-assertion message is not able to be sent.
3914 * When an interrupt assertion message is generated later,
3915 * two messages are re-ordered and sent out.
3916 * That causes APIC to think 82547 is in de-assertion
3917 * state, while 82547 is in assertion state, resulting
3918 * in dead lock. Writing IMC forces 82547 into
3919 * de-assertion state.
3920 */
9150b76a 3921 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
2648345f 3922 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4 3923
835bb129
JB		 3924 adapter->total_tx_bytes = 0;
3925 adapter->total_rx_bytes = 0;
3926 adapter->total_tx_packets = 0;
3927 adapter->total_rx_packets = 0;
3928
96838a40
JB		 3929 for (i = 0; i < E1000_MAX_INTR; i++)
3930 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
46fcc86d 3931 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3932 break;
3933
835bb129
JB		 3934 if (likely(adapter->itr_setting & 3))
3935 e1000_set_itr(adapter);
3936
96838a40 3937 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3938 e1000_irq_enable(adapter);
581d708e 3939
c1605eb3 3940#endif
1da177e4
LT		 3941 return IRQ_HANDLED;
3942}
3943
3944#ifdef CONFIG_E1000_NAPI
3945/**
3946 * e1000_clean - NAPI Rx polling callback
3947 * @adapter: board private structure
3948 **/
3949
3950static int
bea3348e 3951e1000_clean(struct napi_struct *napi, int budget)
1da177e4 3952{
bea3348e
SH		 3953 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
3954 struct net_device *poll_dev = adapter->netdev;
d2c7ddd6 3955 int tx_cleaned = 0, work_done = 0;
581d708e
MC		 3956
3957 /* Must NOT use netdev_priv macro here. */
3958 adapter = poll_dev->priv;
3959
d3d9e484
AK		 3960 /* e1000_clean is called per-cpu. This lock protects
3961 * tx_ring[0] from being cleaned by multiple cpus
3962 * simultaneously. A failure obtaining the lock means
3963 * tx_ring[0] is currently being cleaned anyway. */
3964 if (spin_trylock(&adapter->tx_queue_lock)) {
d2c7ddd6
DM		 3965 tx_cleaned = e1000_clean_tx_irq(adapter,
3966 &adapter->tx_ring[0]);
d3d9e484 3967 spin_unlock(&adapter->tx_queue_lock);
581d708e
MC		 3968 }
3969
d3d9e484 3970 adapter->clean_rx(adapter, &adapter->rx_ring[0],
bea3348e 3971 &work_done, budget);
96838a40 3972
d2c7ddd6
DM		 3973 if (tx_cleaned)
3974 work_done = budget;
3975
53e52c72
DM		 3976 /* If budget not fully consumed, exit the polling mode */
3977 if (work_done < budget) {
835bb129
JB		 3978 if (likely(adapter->itr_setting & 3))
3979 e1000_set_itr(adapter);
bea3348e 3980 netif_rx_complete(poll_dev, napi);
1da177e4 3981 e1000_irq_enable(adapter);
1da177e4
LT		 3982 }
3983
bea3348e 3984 return work_done;
1da177e4
LT		 3985}
3986
3987#endif
3988/**
3989 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3990 * @adapter: board private structure
3991 **/
3992
c3033b01 3993static bool
581d708e
MC		 3994e1000_clean_tx_irq(struct e1000_adapter *adapter,
3995 struct e1000_tx_ring *tx_ring)
1da177e4 3996{
1da177e4
LT		 3997 struct net_device *netdev = adapter->netdev;
3998 struct e1000_tx_desc *tx_desc, *eop_desc;
3999 struct e1000_buffer *buffer_info;
4000 unsigned int i, eop;
2a1af5d7
JK		 4001#ifdef CONFIG_E1000_NAPI
4002 unsigned int count = 0;
4003#endif
c3033b01 4004 bool cleaned = false;
835bb129 4005 unsigned int total_tx_bytes=0, total_tx_packets=0;
1da177e4
LT		 4006
4007 i = tx_ring->next_to_clean;
4008 eop = tx_ring->buffer_info[i].next_to_watch;
4009 eop_desc = E1000_TX_DESC(*tx_ring, eop);
4010
581d708e 4011 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
c3033b01 4012 for (cleaned = false; !cleaned; ) {
1da177e4
LT		 4013 tx_desc = E1000_TX_DESC(*tx_ring, i);
4014 buffer_info = &tx_ring->buffer_info[i];
4015 cleaned = (i == eop);
4016
835bb129 4017 if (cleaned) {
2b65326e 4018 struct sk_buff *skb = buffer_info->skb;
7753b171
JB		 4019 unsigned int segs, bytecount;
4020 segs = skb_shinfo(skb)->gso_segs ?: 1;
4021 /* multiply data chunks by size of headers */
4022 bytecount = ((segs - 1) * skb_headlen(skb)) +
4023 skb->len;
2b65326e 4024 total_tx_packets += segs;
7753b171 4025 total_tx_bytes += bytecount;
835bb129 4026 }
fd803241 4027 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
a9ebadd6 4028 tx_desc->upper.data = 0;
1da177e4 4029
96838a40 4030 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 4031 }
581d708e 4032
1da177e4
LT		 4033 eop = tx_ring->buffer_info[i].next_to_watch;
4034 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 4035#ifdef CONFIG_E1000_NAPI
4036#define E1000_TX_WEIGHT 64
4037 /* weight of a sort for tx, to avoid endless transmit cleanup */
46fcc86d 4038 if (count++ == E1000_TX_WEIGHT) break;
2a1af5d7 4039#endif
1da177e4
LT		 4040 }
4041
4042 tx_ring->next_to_clean = i;
4043
77b2aad5 4044#define TX_WAKE_THRESHOLD 32
65c7973f
JB		 4045 if (unlikely(cleaned && netif_carrier_ok(netdev) &&
4046 E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
4047 /* Make sure that anybody stopping the queue after this
4048 * sees the new next_to_clean.
4049 */
4050 smp_mb();
fcfb1224 4051 if (netif_queue_stopped(netdev)) {
77b2aad5 4052 netif_wake_queue(netdev);
fcfb1224
JB		 4053 ++adapter->restart_queue;
4054 }
77b2aad5 4055 }
2648345f 4056
581d708e 4057 if (adapter->detect_tx_hung) {
2648345f 4058 /* Detect a transmit hang in hardware, this serializes the
1da177e4 4059 * check with the clearing of time_stamp and movement of i */
c3033b01 4060 adapter->detect_tx_hung = false;
392137fa
JK		 4061 if (tx_ring->buffer_info[eop].dma &&
4062 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 4063 (adapter->tx_timeout_factor * HZ))
70b8f1e1 4064 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 4065 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 4066
4067 /* detected Tx unit hang */
c6963ef5 4068 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 4069 " Tx Queue <%lu>\n"
70b8f1e1
MC		 4070 " TDH <%x>\n"
4071 " TDT <%x>\n"
4072 " next_to_use <%x>\n"
4073 " next_to_clean <%x>\n"
4074 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 4075 " time_stamp <%lx>\n"
4076 " next_to_watch <%x>\n"
4077 " jiffies <%lx>\n"
4078 " next_to_watch.status <%x>\n",
7bfa4816
JK		 4079 (unsigned long)((tx_ring - adapter->tx_ring) /
4080 sizeof(struct e1000_tx_ring)),
581d708e
MC		 4081 readl(adapter->hw.hw_addr + tx_ring->tdh),
4082 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 4083 tx_ring->next_to_use,
392137fa
JK		 4084 tx_ring->next_to_clean,
4085 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 4086 eop,
4087 jiffies,
4088 eop_desc->upper.fields.status);
1da177e4 4089 netif_stop_queue(netdev);
70b8f1e1 4090 }
1da177e4 4091 }
835bb129
JB		 4092 adapter->total_tx_bytes += total_tx_bytes;
4093 adapter->total_tx_packets += total_tx_packets;
ef90e4ec
AK		 4094 adapter->net_stats.tx_bytes += total_tx_bytes;
4095 adapter->net_stats.tx_packets += total_tx_packets;
1da177e4
LT		 4096 return cleaned;
4097}
4098
4099/**
4100 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 4101 * @adapter: board private structure
4102 * @status_err: receive descriptor status and error fields
4103 * @csum: receive descriptor csum field
4104 * @sk_buff: socket buffer with received data
1da177e4
LT		 4105 **/
4106
e619d523 4107static void
1da177e4 4108e1000_rx_checksum(struct e1000_adapter *adapter,
406874a7 4109 u32 status_err, u32 csum,
2d7edb92 4110 struct sk_buff *skb)
1da177e4 4111{
406874a7
JP		 4112 u16 status = (u16)status_err;
4113 u8 errors = (u8)(status_err >> 24);
2d7edb92
MC		 4114 skb->ip_summed = CHECKSUM_NONE;
4115
1da177e4 4116 /* 82543 or newer only */
96838a40 4117 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 4118 /* Ignore Checksum bit is set */
96838a40 4119 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 4120 /* TCP/UDP checksum error bit is set */
96838a40 4121 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 4122 /* let the stack verify checksum errors */
1da177e4 4123 adapter->hw_csum_err++;
2d7edb92
MC		 4124 return;
4125 }
4126 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 4127 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
4128 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 4129 return;
1da177e4 4130 } else {
96838a40 4131 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 4132 return;
4133 }
4134 /* It must be a TCP or UDP packet with a valid checksum */
4135 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 4136 /* TCP checksum is good */
4137 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 4138 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
4139 /* IP fragment with UDP payload */
4140 /* Hardware complements the payload checksum, so we undo it
4141 * and then put the value in host order for further stack use.
4142 */
3e18826c
AV		 4143 __sum16 sum = (__force __sum16)htons(csum);
4144 skb->csum = csum_unfold(~sum);
84fa7933 4145 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 4146 }
2d7edb92 4147 adapter->hw_csum_good++;
1da177e4
LT		 4148}
4149
4150/**
2d7edb92 4151 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 4152 * @adapter: board private structure
4153 **/
4154
c3033b01 4155static bool
1da177e4 4156#ifdef CONFIG_E1000_NAPI
581d708e
MC		 4157e1000_clean_rx_irq(struct e1000_adapter *adapter,
4158 struct e1000_rx_ring *rx_ring,
4159 int *work_done, int work_to_do)
1da177e4 4160#else
581d708e
MC		 4161e1000_clean_rx_irq(struct e1000_adapter *adapter,
4162 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 4163#endif
4164{
1da177e4
LT		 4165 struct net_device *netdev = adapter->netdev;
4166 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 4167 struct e1000_rx_desc *rx_desc, *next_rxd;
4168 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4 4169 unsigned long flags;
406874a7
JP		 4170 u32 length;
4171 u8 last_byte;
1da177e4 4172 unsigned int i;
72d64a43 4173 int cleaned_count = 0;
c3033b01 4174 bool cleaned = false;
835bb129 4175 unsigned int total_rx_bytes=0, total_rx_packets=0;
1da177e4
LT		 4176
4177 i = rx_ring->next_to_clean;
4178 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 4179 buffer_info = &rx_ring->buffer_info[i];
1da177e4 4180
b92ff8ee 4181 while (rx_desc->status & E1000_RXD_STAT_DD) {
24f476ee 4182 struct sk_buff *skb;
a292ca6e 4183 u8 status;
90fb5135 4184
1da177e4 4185#ifdef CONFIG_E1000_NAPI
96838a40 4186 if (*work_done >= work_to_do)
1da177e4
LT		 4187 break;
4188 (*work_done)++;
4189#endif
a292ca6e 4190 status = rx_desc->status;
b92ff8ee 4191 skb = buffer_info->skb;
86c3d59f
JB		 4192 buffer_info->skb = NULL;
4193
30320be8
JK		 4194 prefetch(skb->data - NET_IP_ALIGN);
4195
86c3d59f
JB		 4196 if (++i == rx_ring->count) i = 0;
4197 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 4198 prefetch(next_rxd);
4199
86c3d59f 4200 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 4201
c3033b01 4202 cleaned = true;
72d64a43 4203 cleaned_count++;
a292ca6e
JK		 4204 pci_unmap_single(pdev,
4205 buffer_info->dma,
4206 buffer_info->length,
1da177e4
LT		 4207 PCI_DMA_FROMDEVICE);
4208
1da177e4
LT		 4209 length = le16_to_cpu(rx_desc->length);
4210
a1415ee6
JK		 4211 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
4212 /* All receives must fit into a single buffer */
4213 E1000_DBG("%s: Receive packet consumed multiple"
4214 " buffers\n", netdev->name);
864c4e45 4215 /* recycle */
8fc897b0 4216 buffer_info->skb = skb;
1da177e4
LT		 4217 goto next_desc;
4218 }
4219
96838a40 4220 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 4221 last_byte = *(skb->data + length - 1);
b92ff8ee 4222 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 4223 rx_desc->errors, length, last_byte)) {
4224 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 4225 e1000_tbi_adjust_stats(&adapter->hw,
4226 &adapter->stats,
1da177e4
LT		 4227 length, skb->data);
4228 spin_unlock_irqrestore(&adapter->stats_lock,
4229 flags);
4230 length--;
4231 } else {
9e2feace
AK		 4232 /* recycle */
4233 buffer_info->skb = skb;
1da177e4
LT		 4234 goto next_desc;
4235 }
1cb5821f 4236 }
1da177e4 4237
d2a1e213
JB		 4238 /* adjust length to remove Ethernet CRC, this must be
4239 * done after the TBI_ACCEPT workaround above */
4240 length -= 4;
4241
835bb129
JB		 4242 /* probably a little skewed due to removing CRC */
4243 total_rx_bytes += length;
4244 total_rx_packets++;
4245
a292ca6e
JK		 4246 /* code added for copybreak, this should improve
4247 * performance for small packets with large amounts
4248 * of reassembly being done in the stack */
1f753861 4249 if (length < copybreak) {
a292ca6e 4250 struct sk_buff *new_skb =
87f5032e 4251 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
a292ca6e
JK		 4252 if (new_skb) {
4253 skb_reserve(new_skb, NET_IP_ALIGN);
27d7ff46
ACM		 4254 skb_copy_to_linear_data_offset(new_skb,
4255 -NET_IP_ALIGN,
4256 (skb->data -
4257 NET_IP_ALIGN),
4258 (length +
4259 NET_IP_ALIGN));
a292ca6e
JK		 4260 /* save the skb in buffer_info as good */
4261 buffer_info->skb = skb;
4262 skb = new_skb;
a292ca6e 4263 }
996695de
AK		 4264 /* else just continue with the old one */
4265 }
a292ca6e 4266 /* end copybreak code */
996695de 4267 skb_put(skb, length);
1da177e4
LT		 4268
4269 /* Receive Checksum Offload */
a292ca6e 4270 e1000_rx_checksum(adapter,
406874a7
JP		 4271 (u32)(status) |
4272 ((u32)(rx_desc->errors) << 24),
c3d7a3a4 4273 le16_to_cpu(rx_desc->csum), skb);
96838a40 4274
1da177e4
LT		 4275 skb->protocol = eth_type_trans(skb, netdev);
4276#ifdef CONFIG_E1000_NAPI
96838a40 4277 if (unlikely(adapter->vlgrp &&
a292ca6e 4278 (status & E1000_RXD_STAT_VP))) {
1da177e4 4279 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
38b22195 4280 le16_to_cpu(rx_desc->special));
1da177e4
LT		 4281 } else {
4282 netif_receive_skb(skb);
4283 }
4284#else /* CONFIG_E1000_NAPI */
96838a40 4285 if (unlikely(adapter->vlgrp &&
b92ff8ee 4286 (status & E1000_RXD_STAT_VP))) {
1da177e4 4287 vlan_hwaccel_rx(skb, adapter->vlgrp,
38b22195 4288 le16_to_cpu(rx_desc->special));
1da177e4
LT		 4289 } else {
4290 netif_rx(skb);
4291 }
4292#endif /* CONFIG_E1000_NAPI */
4293 netdev->last_rx = jiffies;
4294
4295next_desc:
4296 rx_desc->status = 0;
1da177e4 4297
72d64a43
JK		 4298 /* return some buffers to hardware, one at a time is too slow */
4299 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4300 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4301 cleaned_count = 0;
4302 }
4303
30320be8 4304 /* use prefetched values */
86c3d59f
JB		 4305 rx_desc = next_rxd;
4306 buffer_info = next_buffer;
1da177e4 4307 }
1da177e4 4308 rx_ring->next_to_clean = i;
72d64a43
JK		 4309
4310 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4311 if (cleaned_count)
4312 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92 4313
835bb129
JB		 4314 adapter->total_rx_packets += total_rx_packets;
4315 adapter->total_rx_bytes += total_rx_bytes;
ef90e4ec
AK		 4316 adapter->net_stats.rx_bytes += total_rx_bytes;
4317 adapter->net_stats.rx_packets += total_rx_packets;
2d7edb92
MC		 4318 return cleaned;
4319}
4320
4321/**
4322 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
4323 * @adapter: board private structure
4324 **/
4325
c3033b01 4326static bool
2d7edb92 4327#ifdef CONFIG_E1000_NAPI
581d708e
MC		 4328e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4329 struct e1000_rx_ring *rx_ring,
4330 int *work_done, int work_to_do)
2d7edb92 4331#else
581d708e
MC		 4332e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4333 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 4334#endif
4335{
86c3d59f 4336 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 4337 struct net_device *netdev = adapter->netdev;
4338 struct pci_dev *pdev = adapter->pdev;
86c3d59f 4339 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 4340 struct e1000_ps_page *ps_page;
4341 struct e1000_ps_page_dma *ps_page_dma;
24f476ee 4342 struct sk_buff *skb;
2d7edb92 4343 unsigned int i, j;
406874a7 4344 u32 length, staterr;
72d64a43 4345 int cleaned_count = 0;
c3033b01 4346 bool cleaned = false;
835bb129 4347 unsigned int total_rx_bytes=0, total_rx_packets=0;
2d7edb92
MC		 4348
4349 i = rx_ring->next_to_clean;
4350 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 4351 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 4352 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 4353
96838a40 4354 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 4355 ps_page = &rx_ring->ps_page[i];
4356 ps_page_dma = &rx_ring->ps_page_dma[i];
4357#ifdef CONFIG_E1000_NAPI
96838a40 4358 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 4359 break;
4360 (*work_done)++;
4361#endif
86c3d59f
JB		 4362 skb = buffer_info->skb;
4363
30320be8
JK		 4364 /* in the packet split case this is header only */
4365 prefetch(skb->data - NET_IP_ALIGN);
4366
86c3d59f
JB		 4367 if (++i == rx_ring->count) i = 0;
4368 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 4369 prefetch(next_rxd);
4370
86c3d59f 4371 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 4372
c3033b01 4373 cleaned = true;
72d64a43 4374 cleaned_count++;
2d7edb92
MC		 4375 pci_unmap_single(pdev, buffer_info->dma,
4376 buffer_info->length,
4377 PCI_DMA_FROMDEVICE);
4378
96838a40 4379 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 4380 E1000_DBG("%s: Packet Split buffers didn't pick up"
4381 " the full packet\n", netdev->name);
4382 dev_kfree_skb_irq(skb);
4383 goto next_desc;
4384 }
1da177e4 4385
96838a40 4386 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 4387 dev_kfree_skb_irq(skb);
4388 goto next_desc;
4389 }
4390
4391 length = le16_to_cpu(rx_desc->wb.middle.length0);
4392
96838a40 4393 if (unlikely(!length)) {
2d7edb92
MC		 4394 E1000_DBG("%s: Last part of the packet spanning"
4395 " multiple descriptors\n", netdev->name);
4396 dev_kfree_skb_irq(skb);
4397 goto next_desc;
4398 }
4399
4400 /* Good Receive */
4401 skb_put(skb, length);
4402
dc7c6add
JK		 4403 {
4404 /* this looks ugly, but it seems compiler issues make it
4405 more efficient than reusing j */
4406 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
4407
4408 /* page alloc/put takes too long and effects small packet
4409 * throughput, so unsplit small packets and save the alloc/put*/
1f753861 4410 if (l1 && (l1 <= copybreak) && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add 4411 u8 *vaddr;
76c224bc 4412 /* there is no documentation about how to call
dc7c6add
JK		 4413 * kmap_atomic, so we can't hold the mapping
4414 * very long */
4415 pci_dma_sync_single_for_cpu(pdev,
4416 ps_page_dma->ps_page_dma[0],
4417 PAGE_SIZE,
4418 PCI_DMA_FROMDEVICE);
4419 vaddr = kmap_atomic(ps_page->ps_page[0],
4420 KM_SKB_DATA_SOFTIRQ);
27a884dc 4421 memcpy(skb_tail_pointer(skb), vaddr, l1);
dc7c6add
JK		 4422 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
4423 pci_dma_sync_single_for_device(pdev,
4424 ps_page_dma->ps_page_dma[0],
4425 PAGE_SIZE, PCI_DMA_FROMDEVICE);
f235a2ab
AK		 4426 /* remove the CRC */
4427 l1 -= 4;
dc7c6add 4428 skb_put(skb, l1);
dc7c6add
JK		 4429 goto copydone;
4430 } /* if */
4431 }
90fb5135 4432
96838a40 4433 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 4434 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 4435 break;
2d7edb92
MC		 4436 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
4437 PAGE_SIZE, PCI_DMA_FROMDEVICE);
4438 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 4439 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
4440 length);
2d7edb92 4441 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 4442 skb->len += length;
4443 skb->data_len += length;
5d51b80f 4444 skb->truesize += length;
2d7edb92
MC		 4445 }
4446
f235a2ab
AK		 4447 /* strip the ethernet crc, problem is we're using pages now so
4448 * this whole operation can get a little cpu intensive */
4449 pskb_trim(skb, skb->len - 4);
4450
dc7c6add 4451copydone:
835bb129
JB		 4452 total_rx_bytes += skb->len;
4453 total_rx_packets++;
4454
2d7edb92 4455 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 4456 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 4457 skb->protocol = eth_type_trans(skb, netdev);
4458
96838a40 4459 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 4460 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 4461 adapter->rx_hdr_split++;
2d7edb92 4462#ifdef CONFIG_E1000_NAPI
96838a40 4463 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4464 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
38b22195 4465 le16_to_cpu(rx_desc->wb.middle.vlan));
2d7edb92
MC		 4466 } else {
4467 netif_receive_skb(skb);
4468 }
4469#else /* CONFIG_E1000_NAPI */
96838a40 4470 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4471 vlan_hwaccel_rx(skb, adapter->vlgrp,
38b22195 4472 le16_to_cpu(rx_desc->wb.middle.vlan));
2d7edb92
MC		 4473 } else {
4474 netif_rx(skb);
4475 }
4476#endif /* CONFIG_E1000_NAPI */
4477 netdev->last_rx = jiffies;
4478
4479next_desc:
c3d7a3a4 4480 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 4481 buffer_info->skb = NULL;
2d7edb92 4482
72d64a43
JK		 4483 /* return some buffers to hardware, one at a time is too slow */
4484 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4485 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4486 cleaned_count = 0;
4487 }
4488
30320be8 4489 /* use prefetched values */
86c3d59f
JB		 4490 rx_desc = next_rxd;
4491 buffer_info = next_buffer;
4492
683a38f3 4493 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 4494 }
4495 rx_ring->next_to_clean = i;
72d64a43
JK		 4496
4497 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4498 if (cleaned_count)
4499 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4 4500
835bb129
JB		 4501 adapter->total_rx_packets += total_rx_packets;
4502 adapter->total_rx_bytes += total_rx_bytes;
ef90e4ec
AK		 4503 adapter->net_stats.rx_bytes += total_rx_bytes;
4504 adapter->net_stats.rx_packets += total_rx_packets;
1da177e4
LT		 4505 return cleaned;
4506}
4507
4508/**
2d7edb92 4509 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 4510 * @adapter: address of board private structure
4511 **/
4512
4513static void
581d708e 4514e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 4515 struct e1000_rx_ring *rx_ring,
a292ca6e 4516 int cleaned_count)
1da177e4 4517{
1da177e4
LT		 4518 struct net_device *netdev = adapter->netdev;
4519 struct pci_dev *pdev = adapter->pdev;
4520 struct e1000_rx_desc *rx_desc;
4521 struct e1000_buffer *buffer_info;
4522 struct sk_buff *skb;
2648345f
MC		 4523 unsigned int i;
4524 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 4525
4526 i = rx_ring->next_to_use;
4527 buffer_info = &rx_ring->buffer_info[i];
4528
a292ca6e 4529 while (cleaned_count--) {
ca6f7224
CH		 4530 skb = buffer_info->skb;
4531 if (skb) {
a292ca6e
JK		 4532 skb_trim(skb, 0);
4533 goto map_skb;
4534 }
4535
ca6f7224 4536 skb = netdev_alloc_skb(netdev, bufsz);
96838a40 4537 if (unlikely(!skb)) {
1da177e4 4538 /* Better luck next round */
72d64a43 4539 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 4540 break;
4541 }
4542
2648345f 4543 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 4544 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4545 struct sk_buff *oldskb = skb;
2648345f
MC		 4546 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
4547 "at %p\n", bufsz, skb->data);
4548 /* Try again, without freeing the previous */
87f5032e 4549 skb = netdev_alloc_skb(netdev, bufsz);
2648345f 4550 /* Failed allocation, critical failure */
1da177e4
LT		 4551 if (!skb) {
4552 dev_kfree_skb(oldskb);
4553 break;
4554 }
2648345f 4555
1da177e4
LT		 4556 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4557 /* give up */
4558 dev_kfree_skb(skb);
4559 dev_kfree_skb(oldskb);
4560 break; /* while !buffer_info->skb */
1da177e4 4561 }
ca6f7224
CH		 4562
4563 /* Use new allocation */
4564 dev_kfree_skb(oldskb);
1da177e4 4565 }
1da177e4
LT		 4566 /* Make buffer alignment 2 beyond a 16 byte boundary
4567 * this will result in a 16 byte aligned IP header after
4568 * the 14 byte MAC header is removed
4569 */
4570 skb_reserve(skb, NET_IP_ALIGN);
4571
1da177e4
LT		 4572 buffer_info->skb = skb;
4573 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 4574map_skb:
1da177e4
LT		 4575 buffer_info->dma = pci_map_single(pdev,
4576 skb->data,
4577 adapter->rx_buffer_len,
4578 PCI_DMA_FROMDEVICE);
4579
2648345f
MC		 4580 /* Fix for errata 23, can't cross 64kB boundary */
4581 if (!e1000_check_64k_bound(adapter,
4582 (void *)(unsigned long)buffer_info->dma,
4583 adapter->rx_buffer_len)) {
4584 DPRINTK(RX_ERR, ERR,
4585 "dma align check failed: %u bytes at %p\n",
4586 adapter->rx_buffer_len,
4587 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 4588 dev_kfree_skb(skb);
4589 buffer_info->skb = NULL;
4590
2648345f 4591 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 4592 adapter->rx_buffer_len,
4593 PCI_DMA_FROMDEVICE);
4594
4595 break; /* while !buffer_info->skb */
4596 }
1da177e4
LT		 4597 rx_desc = E1000_RX_DESC(*rx_ring, i);
4598 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4599
96838a40
JB		 4600 if (unlikely(++i == rx_ring->count))
4601 i = 0;
1da177e4
LT		 4602 buffer_info = &rx_ring->buffer_info[i];
4603 }
4604
b92ff8ee
JB		 4605 if (likely(rx_ring->next_to_use != i)) {
4606 rx_ring->next_to_use = i;
4607 if (unlikely(i-- == 0))
4608 i = (rx_ring->count - 1);
4609
4610 /* Force memory writes to complete before letting h/w
4611 * know there are new descriptors to fetch. (Only
4612 * applicable for weak-ordered memory model archs,
4613 * such as IA-64). */
4614 wmb();
4615 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4616 }
1da177e4
LT		 4617}
4618
2d7edb92
MC		 4619/**
4620 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
4621 * @adapter: address of board private structure
4622 **/
4623
4624static void
581d708e 4625e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 4626 struct e1000_rx_ring *rx_ring,
4627 int cleaned_count)
2d7edb92 4628{
2d7edb92
MC		 4629 struct net_device *netdev = adapter->netdev;
4630 struct pci_dev *pdev = adapter->pdev;
4631 union e1000_rx_desc_packet_split *rx_desc;
4632 struct e1000_buffer *buffer_info;
4633 struct e1000_ps_page *ps_page;
4634 struct e1000_ps_page_dma *ps_page_dma;
4635 struct sk_buff *skb;
4636 unsigned int i, j;
4637
4638 i = rx_ring->next_to_use;
4639 buffer_info = &rx_ring->buffer_info[i];
4640 ps_page = &rx_ring->ps_page[i];
4641 ps_page_dma = &rx_ring->ps_page_dma[i];
4642
72d64a43 4643 while (cleaned_count--) {
2d7edb92
MC		 4644 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4645
96838a40 4646 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4647 if (j < adapter->rx_ps_pages) {
4648 if (likely(!ps_page->ps_page[j])) {
4649 ps_page->ps_page[j] =
4650 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4651 if (unlikely(!ps_page->ps_page[j])) {
4652 adapter->alloc_rx_buff_failed++;
e4c811c9 4653 goto no_buffers;
b92ff8ee 4654 }
e4c811c9
MC		 4655 ps_page_dma->ps_page_dma[j] =
4656 pci_map_page(pdev,
4657 ps_page->ps_page[j],
4658 0, PAGE_SIZE,
4659 PCI_DMA_FROMDEVICE);
4660 }
4661 /* Refresh the desc even if buffer_addrs didn't
96838a40 4662 * change because each write-back erases
e4c811c9
MC		 4663 * this info.
4664 */
4665 rx_desc->read.buffer_addr[j+1] =
4666 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4667 } else
3e18826c 4668 rx_desc->read.buffer_addr[j+1] = ~cpu_to_le64(0);
2d7edb92
MC		 4669 }
4670
87f5032e 4671 skb = netdev_alloc_skb(netdev,
90fb5135 4672 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
2d7edb92 4673
b92ff8ee
JB		 4674 if (unlikely(!skb)) {
4675 adapter->alloc_rx_buff_failed++;
2d7edb92 4676 break;
b92ff8ee 4677 }
2d7edb92
MC		 4678
4679 /* Make buffer alignment 2 beyond a 16 byte boundary
4680 * this will result in a 16 byte aligned IP header after
4681 * the 14 byte MAC header is removed
4682 */
4683 skb_reserve(skb, NET_IP_ALIGN);
4684
2d7edb92
MC		 4685 buffer_info->skb = skb;
4686 buffer_info->length = adapter->rx_ps_bsize0;
4687 buffer_info->dma = pci_map_single(pdev, skb->data,
4688 adapter->rx_ps_bsize0,
4689 PCI_DMA_FROMDEVICE);
4690
4691 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4692
96838a40 4693 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4694 buffer_info = &rx_ring->buffer_info[i];
4695 ps_page = &rx_ring->ps_page[i];
4696 ps_page_dma = &rx_ring->ps_page_dma[i];
4697 }
4698
4699no_buffers:
b92ff8ee
JB		 4700 if (likely(rx_ring->next_to_use != i)) {
4701 rx_ring->next_to_use = i;
4702 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4703
4704 /* Force memory writes to complete before letting h/w
4705 * know there are new descriptors to fetch. (Only
4706 * applicable for weak-ordered memory model archs,
4707 * such as IA-64). */
4708 wmb();
4709 /* Hardware increments by 16 bytes, but packet split
4710 * descriptors are 32 bytes...so we increment tail
4711 * twice as much.
4712 */
4713 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4714 }
2d7edb92
MC		 4715}
4716
1da177e4
LT		 4717/**
4718 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4719 * @adapter:
4720 **/
4721
4722static void
4723e1000_smartspeed(struct e1000_adapter *adapter)
4724{
406874a7
JP		 4725 u16 phy_status;
4726 u16 phy_ctrl;
1da177e4 4727
96838a40 4728 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4729 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4730 return;
4731
96838a40 4732 if (adapter->smartspeed == 0) {
1da177e4
LT		 4733 /* If Master/Slave config fault is asserted twice,
4734 * we assume back-to-back */
4735 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4736 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4737 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4738 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4739 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4740 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4741 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4742 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4743 phy_ctrl);
4744 adapter->smartspeed++;
96838a40 4745 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4746 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4747 &phy_ctrl)) {
4748 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4749 MII_CR_RESTART_AUTO_NEG);
4750 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4751 phy_ctrl);
4752 }
4753 }
4754 return;
96838a40 4755 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4756 /* If still no link, perhaps using 2/3 pair cable */
4757 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4758 phy_ctrl |= CR_1000T_MS_ENABLE;
4759 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4760 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4761 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4762 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4763 MII_CR_RESTART_AUTO_NEG);
4764 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4765 }
4766 }
4767 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4768 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4769 adapter->smartspeed = 0;
4770}
4771
4772/**
4773 * e1000_ioctl -
4774 * @netdev:
4775 * @ifreq:
4776 * @cmd:
4777 **/
4778
4779static int
4780e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4781{
4782 switch (cmd) {
4783 case SIOCGMIIPHY:
4784 case SIOCGMIIREG:
4785 case SIOCSMIIREG:
4786 return e1000_mii_ioctl(netdev, ifr, cmd);
4787 default:
4788 return -EOPNOTSUPP;
4789 }
4790}
4791
4792/**
4793 * e1000_mii_ioctl -
4794 * @netdev:
4795 * @ifreq:
4796 * @cmd:
4797 **/
4798
4799static int
4800e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4801{
60490fe0 4802 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4803 struct mii_ioctl_data *data = if_mii(ifr);
4804 int retval;
406874a7
JP		 4805 u16 mii_reg;
4806 u16 spddplx;
97876fc6 4807 unsigned long flags;
1da177e4 4808
96838a40 4809 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4810 return -EOPNOTSUPP;
4811
4812 switch (cmd) {
4813 case SIOCGMIIPHY:
4814 data->phy_id = adapter->hw.phy_addr;
4815 break;
4816 case SIOCGMIIREG:
96838a40 4817 if (!capable(CAP_NET_ADMIN))
1da177e4 4818 return -EPERM;
97876fc6 4819 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4820 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4821 &data->val_out)) {
4822 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4823 return -EIO;
97876fc6
MC		 4824 }
4825 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4826 break;
4827 case SIOCSMIIREG:
96838a40 4828 if (!capable(CAP_NET_ADMIN))
1da177e4 4829 return -EPERM;
96838a40 4830 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4831 return -EFAULT;
4832 mii_reg = data->val_in;
97876fc6 4833 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4834 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4835 mii_reg)) {
4836 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4837 return -EIO;
97876fc6 4838 }
f0163ac4 4839 spin_unlock_irqrestore(&adapter->stats_lock, flags);
dc86d32a 4840 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4841 switch (data->reg_num) {
4842 case PHY_CTRL:
96838a40 4843 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4844 break;
96838a40 4845 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4846 adapter->hw.autoneg = 1;
4847 adapter->hw.autoneg_advertised = 0x2F;
4848 } else {
4849 if (mii_reg & 0x40)
4850 spddplx = SPEED_1000;
4851 else if (mii_reg & 0x2000)
4852 spddplx = SPEED_100;
4853 else
4854 spddplx = SPEED_10;
4855 spddplx += (mii_reg & 0x100)
cb764326
JK		 4856 ? DUPLEX_FULL :
4857 DUPLEX_HALF;
1da177e4
LT		 4858 retval = e1000_set_spd_dplx(adapter,
4859 spddplx);
f0163ac4 4860 if (retval)
1da177e4
LT		 4861 return retval;
4862 }
2db10a08
AK		 4863 if (netif_running(adapter->netdev))
4864 e1000_reinit_locked(adapter);
4865 else
1da177e4
LT		 4866 e1000_reset(adapter);
4867 break;
4868 case M88E1000_PHY_SPEC_CTRL:
4869 case M88E1000_EXT_PHY_SPEC_CTRL:
f0163ac4 4870 if (e1000_phy_reset(&adapter->hw))
1da177e4
LT		 4871 return -EIO;
4872 break;
4873 }
4874 } else {
4875 switch (data->reg_num) {
4876 case PHY_CTRL:
96838a40 4877 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4878 break;
2db10a08
AK		 4879 if (netif_running(adapter->netdev))
4880 e1000_reinit_locked(adapter);
4881 else
1da177e4
LT		 4882 e1000_reset(adapter);
4883 break;
4884 }
4885 }
4886 break;
4887 default:
4888 return -EOPNOTSUPP;
4889 }
4890 return E1000_SUCCESS;
4891}
4892
4893void
4894e1000_pci_set_mwi(struct e1000_hw *hw)
4895{
4896 struct e1000_adapter *adapter = hw->back;
2648345f 4897 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4898
96838a40 4899 if (ret_val)
2648345f 4900 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4901}
4902
4903void
4904e1000_pci_clear_mwi(struct e1000_hw *hw)
4905{
4906 struct e1000_adapter *adapter = hw->back;
4907
4908 pci_clear_mwi(adapter->pdev);
4909}
4910
007755eb
PO		 4911int
4912e1000_pcix_get_mmrbc(struct e1000_hw *hw)
4913{
4914 struct e1000_adapter *adapter = hw->back;
4915 return pcix_get_mmrbc(adapter->pdev);
4916}
4917
4918void
4919e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc)
4920{
4921 struct e1000_adapter *adapter = hw->back;
4922 pcix_set_mmrbc(adapter->pdev, mmrbc);
4923}
4924
406874a7
JP		 4925s32
4926e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
caeccb68
JK		 4927{
4928 struct e1000_adapter *adapter = hw->back;
406874a7 4929 u16 cap_offset;
caeccb68
JK		 4930
4931 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
4932 if (!cap_offset)
4933 return -E1000_ERR_CONFIG;
4934
4935 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
4936
4937 return E1000_SUCCESS;
4938}
4939
1da177e4 4940void
406874a7 4941e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value)
1da177e4
LT		 4942{
4943 outl(value, port);
4944}
4945
4946static void
4947e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4948{
60490fe0 4949 struct e1000_adapter *adapter = netdev_priv(netdev);
406874a7 4950 u32 ctrl, rctl;
1da177e4 4951
9150b76a
JB		 4952 if (!test_bit(__E1000_DOWN, &adapter->flags))
4953 e1000_irq_disable(adapter);
1da177e4
LT		 4954 adapter->vlgrp = grp;
4955
96838a40 4956 if (grp) {
1da177e4
LT		 4957 /* enable VLAN tag insert/strip */
4958 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4959 ctrl |= E1000_CTRL_VME;
4960 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4961
cd94dd0b 4962 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4963 /* enable VLAN receive filtering */
4964 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4965 rctl |= E1000_RCTL_VFE;
4966 rctl &= ~E1000_RCTL_CFIEN;
4967 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4968 e1000_update_mng_vlan(adapter);
cd94dd0b 4969 }
1da177e4
LT		 4970 } else {
4971 /* disable VLAN tag insert/strip */
4972 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4973 ctrl &= ~E1000_CTRL_VME;
4974 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4975
cd94dd0b 4976 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4977 /* disable VLAN filtering */
4978 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4979 rctl &= ~E1000_RCTL_VFE;
4980 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4981 if (adapter->mng_vlan_id !=
406874a7 4982 (u16)E1000_MNG_VLAN_NONE) {
90fb5135
AK		 4983 e1000_vlan_rx_kill_vid(netdev,
4984 adapter->mng_vlan_id);
4985 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4986 }
cd94dd0b 4987 }
1da177e4
LT		 4988 }
4989
9150b76a
JB		 4990 if (!test_bit(__E1000_DOWN, &adapter->flags))
4991 e1000_irq_enable(adapter);
1da177e4
LT		 4992}
4993
4994static void
406874a7 4995e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1da177e4 4996{
60490fe0 4997 struct e1000_adapter *adapter = netdev_priv(netdev);
406874a7 4998 u32 vfta, index;
96838a40
JB		 4999
5000 if ((adapter->hw.mng_cookie.status &
5001 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
5002 (vid == adapter->mng_vlan_id))
2d7edb92 5003 return;
1da177e4
LT		 5004 /* add VID to filter table */
5005 index = (vid >> 5) & 0x7F;
5006 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
5007 vfta |= (1 << (vid & 0x1F));
5008 e1000_write_vfta(&adapter->hw, index, vfta);
5009}
5010
5011static void
406874a7 5012e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1da177e4 5013{
60490fe0 5014 struct e1000_adapter *adapter = netdev_priv(netdev);
406874a7 5015 u32 vfta, index;
1da177e4 5016
9150b76a
JB		 5017 if (!test_bit(__E1000_DOWN, &adapter->flags))
5018 e1000_irq_disable(adapter);
5c15bdec 5019 vlan_group_set_device(adapter->vlgrp, vid, NULL);
9150b76a
JB		 5020 if (!test_bit(__E1000_DOWN, &adapter->flags))
5021 e1000_irq_enable(adapter);
1da177e4 5022
96838a40
JB		 5023 if ((adapter->hw.mng_cookie.status &
5024 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 5025 (vid == adapter->mng_vlan_id)) {
5026 /* release control to f/w */
5027 e1000_release_hw_control(adapter);
2d7edb92 5028 return;
ff147013
JK		 5029 }
5030
1da177e4
LT		 5031 /* remove VID from filter table */
5032 index = (vid >> 5) & 0x7F;
5033 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
5034 vfta &= ~(1 << (vid & 0x1F));
5035 e1000_write_vfta(&adapter->hw, index, vfta);
5036}
5037
5038static void
5039e1000_restore_vlan(struct e1000_adapter *adapter)
5040{
5041 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5042
96838a40 5043 if (adapter->vlgrp) {
406874a7 5044 u16 vid;
96838a40 5045 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5c15bdec 5046 if (!vlan_group_get_device(adapter->vlgrp, vid))
1da177e4
LT		 5047 continue;
5048 e1000_vlan_rx_add_vid(adapter->netdev, vid);
5049 }
5050 }
5051}
5052
5053int
406874a7 5054e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx)
1da177e4
LT		 5055{
5056 adapter->hw.autoneg = 0;
5057
6921368f 5058 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 5059 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 5060 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5061 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
5062 return -EINVAL;
5063 }
5064
96838a40 5065 switch (spddplx) {
1da177e4
LT		 5066 case SPEED_10 + DUPLEX_HALF:
5067 adapter->hw.forced_speed_duplex = e1000_10_half;
5068 break;
5069 case SPEED_10 + DUPLEX_FULL:
5070 adapter->hw.forced_speed_duplex = e1000_10_full;
5071 break;
5072 case SPEED_100 + DUPLEX_HALF:
5073 adapter->hw.forced_speed_duplex = e1000_100_half;
5074 break;
5075 case SPEED_100 + DUPLEX_FULL:
5076 adapter->hw.forced_speed_duplex = e1000_100_full;
5077 break;
5078 case SPEED_1000 + DUPLEX_FULL:
5079 adapter->hw.autoneg = 1;
5080 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
5081 break;
5082 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5083 default:
2648345f 5084 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 5085 return -EINVAL;
5086 }
5087 return 0;
5088}
5089
1da177e4 5090static int
829ca9a3 5091e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 5092{
5093 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 5094 struct e1000_adapter *adapter = netdev_priv(netdev);
406874a7
JP		 5095 u32 ctrl, ctrl_ext, rctl, status;
5096 u32 wufc = adapter->wol;
6fdfef16 5097#ifdef CONFIG_PM
240b1710 5098 int retval = 0;
6fdfef16 5099#endif
1da177e4
LT		 5100
5101 netif_device_detach(netdev);
5102
2db10a08
AK		 5103 if (netif_running(netdev)) {
5104 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 5105 e1000_down(adapter);
2db10a08 5106 }
1da177e4 5107
2f82665f 5108#ifdef CONFIG_PM
1d33e9c6 5109 retval = pci_save_state(pdev);
2f82665f
JB		 5110 if (retval)
5111 return retval;
5112#endif
5113
1da177e4 5114 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 5115 if (status & E1000_STATUS_LU)
1da177e4
LT		 5116 wufc &= ~E1000_WUFC_LNKC;
5117
96838a40 5118 if (wufc) {
1da177e4 5119 e1000_setup_rctl(adapter);
db0ce50d 5120 e1000_set_rx_mode(netdev);
1da177e4
LT		 5121
5122 /* turn on all-multi mode if wake on multicast is enabled */
120cd576 5123 if (wufc & E1000_WUFC_MC) {
1da177e4
LT		 5124 rctl = E1000_READ_REG(&adapter->hw, RCTL);
5125 rctl |= E1000_RCTL_MPE;
5126 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
5127 }
5128
96838a40 5129 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 5130 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
5131 /* advertise wake from D3Cold */
5132 #define E1000_CTRL_ADVD3WUC 0x00100000
5133 /* phy power management enable */
5134 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5135 ctrl |= E1000_CTRL_ADVD3WUC |
5136 E1000_CTRL_EN_PHY_PWR_MGMT;
5137 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
5138 }
5139
96838a40 5140 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 5141 adapter->hw.media_type == e1000_media_type_internal_serdes) {
5142 /* keep the laser running in D3 */
5143 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
5144 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
5145 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
5146 }
5147
2d7edb92
MC		 5148 /* Allow time for pending master requests to run */
5149 e1000_disable_pciex_master(&adapter->hw);
5150
1da177e4
LT		 5151 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
5152 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 5153 pci_enable_wake(pdev, PCI_D3hot, 1);
5154 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 5155 } else {
5156 E1000_WRITE_REG(&adapter->hw, WUC, 0);
5157 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 5158 pci_enable_wake(pdev, PCI_D3hot, 0);
5159 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 5160 }
5161
0fccd0e9
JG		 5162 e1000_release_manageability(adapter);
5163
5164 /* make sure adapter isn't asleep if manageability is enabled */
5165 if (adapter->en_mng_pt) {
5166 pci_enable_wake(pdev, PCI_D3hot, 1);
5167 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 5168 }
5169
cd94dd0b
AK		 5170 if (adapter->hw.phy_type == e1000_phy_igp_3)
5171 e1000_phy_powerdown_workaround(&adapter->hw);
5172
edd106fc
AK		 5173 if (netif_running(netdev))
5174 e1000_free_irq(adapter);
5175
b55ccb35
JK		 5176 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5177 * would have already happened in close and is redundant. */
5178 e1000_release_hw_control(adapter);
2d7edb92 5179
1da177e4 5180 pci_disable_device(pdev);
240b1710 5181
d0e027db 5182 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 5183
5184 return 0;
5185}
5186
2f82665f 5187#ifdef CONFIG_PM
1da177e4
LT		 5188static int
5189e1000_resume(struct pci_dev *pdev)
5190{
5191 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 5192 struct e1000_adapter *adapter = netdev_priv(netdev);
406874a7 5193 u32 err;
1da177e4 5194
d0e027db 5195 pci_set_power_state(pdev, PCI_D0);
1d33e9c6 5196 pci_restore_state(pdev);
3d1dd8cb
AK		 5197 if ((err = pci_enable_device(pdev))) {
5198 printk(KERN_ERR "e1000: Cannot enable PCI device from suspend\n");
5199 return err;
5200 }
a4cb847d 5201 pci_set_master(pdev);
1da177e4 5202
d0e027db
AK		 5203 pci_enable_wake(pdev, PCI_D3hot, 0);
5204 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4 5205
edd106fc
AK		 5206 if (netif_running(netdev) && (err = e1000_request_irq(adapter)))
5207 return err;
5208
5209 e1000_power_up_phy(adapter);
1da177e4
LT		 5210 e1000_reset(adapter);
5211 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
5212
0fccd0e9
JG		 5213 e1000_init_manageability(adapter);
5214
96838a40 5215 if (netif_running(netdev))
1da177e4
LT		 5216 e1000_up(adapter);
5217
5218 netif_device_attach(netdev);
5219
b55ccb35
JK		 5220 /* If the controller is 82573 and f/w is AMT, do not set
5221 * DRV_LOAD until the interface is up. For all other cases,
5222 * let the f/w know that the h/w is now under the control
5223 * of the driver. */
5224 if (adapter->hw.mac_type != e1000_82573 ||
5225 !e1000_check_mng_mode(&adapter->hw))
5226 e1000_get_hw_control(adapter);
2d7edb92 5227
1da177e4
LT		 5228 return 0;
5229}
5230#endif
c653e635
AK		 5231
5232static void e1000_shutdown(struct pci_dev *pdev)
5233{
5234 e1000_suspend(pdev, PMSG_SUSPEND);
5235}
5236
1da177e4
LT		 5237#ifdef CONFIG_NET_POLL_CONTROLLER
5238/*
5239 * Polling 'interrupt' - used by things like netconsole to send skbs
5240 * without having to re-enable interrupts. It's not called while
5241 * the interrupt routine is executing.
5242 */
5243static void
2648345f 5244e1000_netpoll(struct net_device *netdev)
1da177e4 5245{
60490fe0 5246 struct e1000_adapter *adapter = netdev_priv(netdev);
d3d9e484 5247
1da177e4 5248 disable_irq(adapter->pdev->irq);
7d12e780 5249 e1000_intr(adapter->pdev->irq, netdev);
e8da8be1
JK		 5250#ifndef CONFIG_E1000_NAPI
5251 adapter->clean_rx(adapter, adapter->rx_ring);
5252#endif
1da177e4
LT		 5253 enable_irq(adapter->pdev->irq);
5254}
5255#endif
5256
9026729b
AK		 5257/**
5258 * e1000_io_error_detected - called when PCI error is detected
5259 * @pdev: Pointer to PCI device
5260 * @state: The current pci conneection state
5261 *
5262 * This function is called after a PCI bus error affecting
5263 * this device has been detected.
5264 */
5265static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5266{
5267 struct net_device *netdev = pci_get_drvdata(pdev);
5268 struct e1000_adapter *adapter = netdev->priv;
5269
5270 netif_device_detach(netdev);
5271
5272 if (netif_running(netdev))
5273 e1000_down(adapter);
72e8d6bb 5274 pci_disable_device(pdev);
9026729b
AK		 5275
5276 /* Request a slot slot reset. */
5277 return PCI_ERS_RESULT_NEED_RESET;
5278}
5279
5280/**
5281 * e1000_io_slot_reset - called after the pci bus has been reset.
5282 * @pdev: Pointer to PCI device
5283 *
5284 * Restart the card from scratch, as if from a cold-boot. Implementation
5285 * resembles the first-half of the e1000_resume routine.
5286 */
5287static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5288{
5289 struct net_device *netdev = pci_get_drvdata(pdev);
5290 struct e1000_adapter *adapter = netdev->priv;
5291
5292 if (pci_enable_device(pdev)) {
5293 printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n");
5294 return PCI_ERS_RESULT_DISCONNECT;
5295 }
5296 pci_set_master(pdev);
5297
dbf38c94
LV		 5298 pci_enable_wake(pdev, PCI_D3hot, 0);
5299 pci_enable_wake(pdev, PCI_D3cold, 0);
9026729b 5300
9026729b
AK		 5301 e1000_reset(adapter);
5302 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
5303
5304 return PCI_ERS_RESULT_RECOVERED;
5305}
5306
5307/**
5308 * e1000_io_resume - called when traffic can start flowing again.
5309 * @pdev: Pointer to PCI device
5310 *
5311 * This callback is called when the error recovery driver tells us that
5312 * its OK to resume normal operation. Implementation resembles the
5313 * second-half of the e1000_resume routine.
5314 */
5315static void e1000_io_resume(struct pci_dev *pdev)
5316{
5317 struct net_device *netdev = pci_get_drvdata(pdev);
5318 struct e1000_adapter *adapter = netdev->priv;
0fccd0e9
JG		 5319
5320 e1000_init_manageability(adapter);
9026729b
AK		 5321
5322 if (netif_running(netdev)) {
5323 if (e1000_up(adapter)) {
5324 printk("e1000: can't bring device back up after reset\n");
5325 return;
5326 }
5327 }
5328
5329 netif_device_attach(netdev);
5330
0fccd0e9
JG		 5331 /* If the controller is 82573 and f/w is AMT, do not set
5332 * DRV_LOAD until the interface is up. For all other cases,
5333 * let the f/w know that the h/w is now under the control
5334 * of the driver. */
5335 if (adapter->hw.mac_type != e1000_82573 ||
5336 !e1000_check_mng_mode(&adapter->hw))
5337 e1000_get_hw_control(adapter);
9026729b 5338
9026729b
AK		 5339}
5340
1da177e4 5341/* e1000_main.c */
Linux kernel - Deliverables
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