projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] S2io: MSI/MSI-X support (runtime configurable)
[deliverable/linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
2b02893e
MC		 32 * 6.0.58 4/20/05
33 * o Accepted ethtool cleanup patch from Stephen Hemminger
2648345f
MC		 34 * 6.0.44+ 2/15/05
35 * o applied Anton's patch to resolve tx hang in hardware
36 * o Applied Andrew Mortons patch - e1000 stops working after resume
1da177e4
LT		 37 */
38
39char e1000_driver_name[] = "e1000";
40char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
41#ifndef CONFIG_E1000_NAPI
42#define DRIVERNAPI
43#else
44#define DRIVERNAPI "-NAPI"
45#endif
2b02893e 46#define DRV_VERSION "6.0.60-k2"DRIVERNAPI
1da177e4 47char e1000_driver_version[] = DRV_VERSION;
2b02893e 48char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
1da177e4
LT		 49
50/* e1000_pci_tbl - PCI Device ID Table
51 *
52 * Last entry must be all 0s
53 *
54 * Macro expands to...
55 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
56 */
57static struct pci_device_id e1000_pci_tbl[] = {
58 INTEL_E1000_ETHERNET_DEVICE(0x1000),
59 INTEL_E1000_ETHERNET_DEVICE(0x1001),
60 INTEL_E1000_ETHERNET_DEVICE(0x1004),
61 INTEL_E1000_ETHERNET_DEVICE(0x1008),
62 INTEL_E1000_ETHERNET_DEVICE(0x1009),
63 INTEL_E1000_ETHERNET_DEVICE(0x100C),
64 INTEL_E1000_ETHERNET_DEVICE(0x100D),
65 INTEL_E1000_ETHERNET_DEVICE(0x100E),
66 INTEL_E1000_ETHERNET_DEVICE(0x100F),
67 INTEL_E1000_ETHERNET_DEVICE(0x1010),
68 INTEL_E1000_ETHERNET_DEVICE(0x1011),
69 INTEL_E1000_ETHERNET_DEVICE(0x1012),
70 INTEL_E1000_ETHERNET_DEVICE(0x1013),
71 INTEL_E1000_ETHERNET_DEVICE(0x1014),
72 INTEL_E1000_ETHERNET_DEVICE(0x1015),
73 INTEL_E1000_ETHERNET_DEVICE(0x1016),
74 INTEL_E1000_ETHERNET_DEVICE(0x1017),
75 INTEL_E1000_ETHERNET_DEVICE(0x1018),
76 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 77 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 78 INTEL_E1000_ETHERNET_DEVICE(0x101D),
79 INTEL_E1000_ETHERNET_DEVICE(0x101E),
80 INTEL_E1000_ETHERNET_DEVICE(0x1026),
81 INTEL_E1000_ETHERNET_DEVICE(0x1027),
82 INTEL_E1000_ETHERNET_DEVICE(0x1028),
83 INTEL_E1000_ETHERNET_DEVICE(0x1075),
84 INTEL_E1000_ETHERNET_DEVICE(0x1076),
85 INTEL_E1000_ETHERNET_DEVICE(0x1077),
86 INTEL_E1000_ETHERNET_DEVICE(0x1078),
87 INTEL_E1000_ETHERNET_DEVICE(0x1079),
88 INTEL_E1000_ETHERNET_DEVICE(0x107A),
89 INTEL_E1000_ETHERNET_DEVICE(0x107B),
90 INTEL_E1000_ETHERNET_DEVICE(0x107C),
91 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 92 INTEL_E1000_ETHERNET_DEVICE(0x108B),
93 INTEL_E1000_ETHERNET_DEVICE(0x108C),
94 INTEL_E1000_ETHERNET_DEVICE(0x1099),
1da177e4
LT		 95 /* required last entry */
96 {0,}
97};
98
99MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
100
101int e1000_up(struct e1000_adapter *adapter);
102void e1000_down(struct e1000_adapter *adapter);
103void e1000_reset(struct e1000_adapter *adapter);
104int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
105int e1000_setup_tx_resources(struct e1000_adapter *adapter);
106int e1000_setup_rx_resources(struct e1000_adapter *adapter);
107void e1000_free_tx_resources(struct e1000_adapter *adapter);
108void e1000_free_rx_resources(struct e1000_adapter *adapter);
109void e1000_update_stats(struct e1000_adapter *adapter);
110
111/* Local Function Prototypes */
112
113static int e1000_init_module(void);
114static void e1000_exit_module(void);
115static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
116static void __devexit e1000_remove(struct pci_dev *pdev);
117static int e1000_sw_init(struct e1000_adapter *adapter);
118static int e1000_open(struct net_device *netdev);
119static int e1000_close(struct net_device *netdev);
120static void e1000_configure_tx(struct e1000_adapter *adapter);
121static void e1000_configure_rx(struct e1000_adapter *adapter);
122static void e1000_setup_rctl(struct e1000_adapter *adapter);
123static void e1000_clean_tx_ring(struct e1000_adapter *adapter);
124static void e1000_clean_rx_ring(struct e1000_adapter *adapter);
125static void e1000_set_multi(struct net_device *netdev);
126static void e1000_update_phy_info(unsigned long data);
127static void e1000_watchdog(unsigned long data);
128static void e1000_watchdog_task(struct e1000_adapter *adapter);
129static void e1000_82547_tx_fifo_stall(unsigned long data);
130static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
131static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
132static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
133static int e1000_set_mac(struct net_device *netdev, void *p);
134static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
135static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter);
136#ifdef CONFIG_E1000_NAPI
137static int e1000_clean(struct net_device *netdev, int *budget);
138static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
139 int *work_done, int work_to_do);
2d7edb92
MC		 140static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
141 int *work_done, int work_to_do);
1da177e4
LT		 142#else
143static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter);
2d7edb92 144static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter);
1da177e4
LT		 145#endif
146static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter);
2d7edb92 147static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter);
1da177e4
LT		 148static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
149static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
150 int cmd);
151void e1000_set_ethtool_ops(struct net_device *netdev);
152static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
153static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
154static void e1000_tx_timeout(struct net_device *dev);
155static void e1000_tx_timeout_task(struct net_device *dev);
156static void e1000_smartspeed(struct e1000_adapter *adapter);
157static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
158 struct sk_buff *skb);
159
160static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
161static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
162static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
163static void e1000_restore_vlan(struct e1000_adapter *adapter);
164
829ca9a3 165static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 166#ifdef CONFIG_PM
167static int e1000_resume(struct pci_dev *pdev);
168#endif
169
170#ifdef CONFIG_NET_POLL_CONTROLLER
171/* for netdump / net console */
172static void e1000_netpoll (struct net_device *netdev);
173#endif
174
1da177e4
LT		 175/* Exported from other modules */
176
177extern void e1000_check_options(struct e1000_adapter *adapter);
178
179static struct pci_driver e1000_driver = {
180 .name = e1000_driver_name,
181 .id_table = e1000_pci_tbl,
182 .probe = e1000_probe,
183 .remove = __devexit_p(e1000_remove),
184 /* Power Managment Hooks */
185#ifdef CONFIG_PM
186 .suspend = e1000_suspend,
187 .resume = e1000_resume
188#endif
189};
190
191MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
192MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
193MODULE_LICENSE("GPL");
194MODULE_VERSION(DRV_VERSION);
195
196static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
197module_param(debug, int, 0);
198MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
199
200/**
201 * e1000_init_module - Driver Registration Routine
202 *
203 * e1000_init_module is the first routine called when the driver is
204 * loaded. All it does is register with the PCI subsystem.
205 **/
206
207static int __init
208e1000_init_module(void)
209{
210 int ret;
211 printk(KERN_INFO "%s - version %s\n",
212 e1000_driver_string, e1000_driver_version);
213
214 printk(KERN_INFO "%s\n", e1000_copyright);
215
216 ret = pci_module_init(&e1000_driver);
8b378def 217
1da177e4
LT		 218 return ret;
219}
220
221module_init(e1000_init_module);
222
223/**
224 * e1000_exit_module - Driver Exit Cleanup Routine
225 *
226 * e1000_exit_module is called just before the driver is removed
227 * from memory.
228 **/
229
230static void __exit
231e1000_exit_module(void)
232{
1da177e4
LT		 233 pci_unregister_driver(&e1000_driver);
234}
235
236module_exit(e1000_exit_module);
237
238/**
239 * e1000_irq_disable - Mask off interrupt generation on the NIC
240 * @adapter: board private structure
241 **/
242
243static inline void
244e1000_irq_disable(struct e1000_adapter *adapter)
245{
246 atomic_inc(&adapter->irq_sem);
247 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
248 E1000_WRITE_FLUSH(&adapter->hw);
249 synchronize_irq(adapter->pdev->irq);
250}
251
252/**
253 * e1000_irq_enable - Enable default interrupt generation settings
254 * @adapter: board private structure
255 **/
256
257static inline void
258e1000_irq_enable(struct e1000_adapter *adapter)
259{
260 if(likely(atomic_dec_and_test(&adapter->irq_sem))) {
261 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
262 E1000_WRITE_FLUSH(&adapter->hw);
263 }
264}
2d7edb92
MC		 265void
266e1000_update_mng_vlan(struct e1000_adapter *adapter)
267{
268 struct net_device *netdev = adapter->netdev;
269 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
270 uint16_t old_vid = adapter->mng_vlan_id;
271 if(adapter->vlgrp) {
272 if(!adapter->vlgrp->vlan_devices[vid]) {
273 if(adapter->hw.mng_cookie.status &
274 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
275 e1000_vlan_rx_add_vid(netdev, vid);
276 adapter->mng_vlan_id = vid;
277 } else
278 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
279
280 if((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
281 (vid != old_vid) &&
282 !adapter->vlgrp->vlan_devices[old_vid])
283 e1000_vlan_rx_kill_vid(netdev, old_vid);
284 }
285 }
286}
287
1da177e4
LT		 288int
289e1000_up(struct e1000_adapter *adapter)
290{
291 struct net_device *netdev = adapter->netdev;
292 int err;
293
294 /* hardware has been reset, we need to reload some things */
295
296 /* Reset the PHY if it was previously powered down */
297 if(adapter->hw.media_type == e1000_media_type_copper) {
298 uint16_t mii_reg;
299 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
300 if(mii_reg & MII_CR_POWER_DOWN)
301 e1000_phy_reset(&adapter->hw);
302 }
303
304 e1000_set_multi(netdev);
305
306 e1000_restore_vlan(adapter);
307
308 e1000_configure_tx(adapter);
309 e1000_setup_rctl(adapter);
310 e1000_configure_rx(adapter);
2d7edb92 311 adapter->alloc_rx_buf(adapter);
1da177e4 312
fa4f7ef3
MC		 313#ifdef CONFIG_PCI_MSI
314 if(adapter->hw.mac_type > e1000_82547_rev_2) {
315 adapter->have_msi = TRUE;
316 if((err = pci_enable_msi(adapter->pdev))) {
317 DPRINTK(PROBE, ERR,
318 "Unable to allocate MSI interrupt Error: %d\n", err);
319 adapter->have_msi = FALSE;
320 }
321 }
322#endif
1da177e4
LT		 323 if((err = request_irq(adapter->pdev->irq, &e1000_intr,
324 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 325 netdev->name, netdev))) {
326 DPRINTK(PROBE, ERR,
327 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 328 return err;
2648345f 329 }
1da177e4
LT		 330
331 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 332
333#ifdef CONFIG_E1000_NAPI
334 netif_poll_enable(netdev);
335#endif
5de55624
MC		 336 e1000_irq_enable(adapter);
337
1da177e4
LT		 338 return 0;
339}
340
341void
342e1000_down(struct e1000_adapter *adapter)
343{
344 struct net_device *netdev = adapter->netdev;
345
346 e1000_irq_disable(adapter);
347 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3
MC		 348#ifdef CONFIG_PCI_MSI
349 if(adapter->hw.mac_type > e1000_82547_rev_2 &&
350 adapter->have_msi == TRUE)
351 pci_disable_msi(adapter->pdev);
352#endif
1da177e4
LT		 353 del_timer_sync(&adapter->tx_fifo_stall_timer);
354 del_timer_sync(&adapter->watchdog_timer);
355 del_timer_sync(&adapter->phy_info_timer);
356
357#ifdef CONFIG_E1000_NAPI
358 netif_poll_disable(netdev);
359#endif
360 adapter->link_speed = 0;
361 adapter->link_duplex = 0;
362 netif_carrier_off(netdev);
363 netif_stop_queue(netdev);
364
365 e1000_reset(adapter);
366 e1000_clean_tx_ring(adapter);
367 e1000_clean_rx_ring(adapter);
368
369 /* If WoL is not enabled
2d7edb92 370 * and management mode is not IAMT
1da177e4 371 * Power down the PHY so no link is implied when interface is down */
2d7edb92
MC		 372 if(!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
373 adapter->hw.media_type == e1000_media_type_copper &&
374 !e1000_check_mng_mode(&adapter->hw) &&
375 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN)) {
1da177e4
LT		 376 uint16_t mii_reg;
377 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
378 mii_reg |= MII_CR_POWER_DOWN;
379 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 380 mdelay(1);
1da177e4
LT		 381 }
382}
383
384void
385e1000_reset(struct e1000_adapter *adapter)
386{
1125ecbc 387 struct net_device *netdev = adapter->netdev;
2d7edb92 388 uint32_t pba, manc;
1125ecbc
MC		 389 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
390 uint16_t fc_low_water_mark = E1000_FC_LOW_DIFF;
1da177e4
LT		 391
392 /* Repartition Pba for greater than 9k mtu
393 * To take effect CTRL.RST is required.
394 */
395
2d7edb92
MC		 396 switch (adapter->hw.mac_type) {
397 case e1000_82547:
0e6ef3e0 398 case e1000_82547_rev_2:
2d7edb92
MC		 399 pba = E1000_PBA_30K;
400 break;
401 case e1000_82573:
402 pba = E1000_PBA_12K;
403 break;
404 default:
405 pba = E1000_PBA_48K;
406 break;
407 }
408
1125ecbc
MC		 409 if((adapter->hw.mac_type != e1000_82573) &&
410 (adapter->rx_buffer_len > E1000_RXBUFFER_8192)) {
411 pba -= 8; /* allocate more FIFO for Tx */
412 /* send an XOFF when there is enough space in the
413 * Rx FIFO to hold one extra full size Rx packet
414 */
415 fc_high_water_mark = netdev->mtu + ENET_HEADER_SIZE +
416 ETHERNET_FCS_SIZE + 1;
417 fc_low_water_mark = fc_high_water_mark + 8;
418 }
2d7edb92
MC		 419
420
421 if(adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 422 adapter->tx_fifo_head = 0;
423 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
424 adapter->tx_fifo_size =
425 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
426 atomic_set(&adapter->tx_fifo_stall, 0);
427 }
2d7edb92 428
1da177e4
LT		 429 E1000_WRITE_REG(&adapter->hw, PBA, pba);
430
431 /* flow control settings */
432 adapter->hw.fc_high_water = (pba << E1000_PBA_BYTES_SHIFT) -
1125ecbc 433 fc_high_water_mark;
1da177e4 434 adapter->hw.fc_low_water = (pba << E1000_PBA_BYTES_SHIFT) -
1125ecbc 435 fc_low_water_mark;
1da177e4
LT		 436 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
437 adapter->hw.fc_send_xon = 1;
438 adapter->hw.fc = adapter->hw.original_fc;
439
2d7edb92 440 /* Allow time for pending master requests to run */
1da177e4
LT		 441 e1000_reset_hw(&adapter->hw);
442 if(adapter->hw.mac_type >= e1000_82544)
443 E1000_WRITE_REG(&adapter->hw, WUC, 0);
444 if(e1000_init_hw(&adapter->hw))
445 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 446 e1000_update_mng_vlan(adapter);
1da177e4
LT		 447 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
448 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
449
450 e1000_reset_adaptive(&adapter->hw);
451 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 452 if (adapter->en_mng_pt) {
453 manc = E1000_READ_REG(&adapter->hw, MANC);
454 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
455 E1000_WRITE_REG(&adapter->hw, MANC, manc);
456 }
1da177e4
LT		 457}
458
459/**
460 * e1000_probe - Device Initialization Routine
461 * @pdev: PCI device information struct
462 * @ent: entry in e1000_pci_tbl
463 *
464 * Returns 0 on success, negative on failure
465 *
466 * e1000_probe initializes an adapter identified by a pci_dev structure.
467 * The OS initialization, configuring of the adapter private structure,
468 * and a hardware reset occur.
469 **/
470
471static int __devinit
472e1000_probe(struct pci_dev *pdev,
473 const struct pci_device_id *ent)
474{
475 struct net_device *netdev;
476 struct e1000_adapter *adapter;
2d7edb92
MC		 477 unsigned long mmio_start, mmio_len;
478 uint32_t swsm;
479
1da177e4 480 static int cards_found = 0;
2d7edb92 481 int i, err, pci_using_dac;
1da177e4
LT		 482 uint16_t eeprom_data;
483 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
1da177e4
LT		 484 if((err = pci_enable_device(pdev)))
485 return err;
486
487 if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
488 pci_using_dac = 1;
489 } else {
490 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
491 E1000_ERR("No usable DMA configuration, aborting\n");
492 return err;
493 }
494 pci_using_dac = 0;
495 }
496
497 if((err = pci_request_regions(pdev, e1000_driver_name)))
498 return err;
499
500 pci_set_master(pdev);
501
502 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
503 if(!netdev) {
504 err = -ENOMEM;
505 goto err_alloc_etherdev;
506 }
507
508 SET_MODULE_OWNER(netdev);
509 SET_NETDEV_DEV(netdev, &pdev->dev);
510
511 pci_set_drvdata(pdev, netdev);
60490fe0 512 adapter = netdev_priv(netdev);
1da177e4
LT		 513 adapter->netdev = netdev;
514 adapter->pdev = pdev;
515 adapter->hw.back = adapter;
516 adapter->msg_enable = (1 << debug) - 1;
517
518 mmio_start = pci_resource_start(pdev, BAR_0);
519 mmio_len = pci_resource_len(pdev, BAR_0);
520
521 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
522 if(!adapter->hw.hw_addr) {
523 err = -EIO;
524 goto err_ioremap;
525 }
526
527 for(i = BAR_1; i <= BAR_5; i++) {
528 if(pci_resource_len(pdev, i) == 0)
529 continue;
530 if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
531 adapter->hw.io_base = pci_resource_start(pdev, i);
532 break;
533 }
534 }
535
536 netdev->open = &e1000_open;
537 netdev->stop = &e1000_close;
538 netdev->hard_start_xmit = &e1000_xmit_frame;
539 netdev->get_stats = &e1000_get_stats;
540 netdev->set_multicast_list = &e1000_set_multi;
541 netdev->set_mac_address = &e1000_set_mac;
542 netdev->change_mtu = &e1000_change_mtu;
543 netdev->do_ioctl = &e1000_ioctl;
544 e1000_set_ethtool_ops(netdev);
545 netdev->tx_timeout = &e1000_tx_timeout;
546 netdev->watchdog_timeo = 5 * HZ;
547#ifdef CONFIG_E1000_NAPI
548 netdev->poll = &e1000_clean;
549 netdev->weight = 64;
550#endif
551 netdev->vlan_rx_register = e1000_vlan_rx_register;
552 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
553 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
554#ifdef CONFIG_NET_POLL_CONTROLLER
555 netdev->poll_controller = e1000_netpoll;
556#endif
557 strcpy(netdev->name, pci_name(pdev));
558
559 netdev->mem_start = mmio_start;
560 netdev->mem_end = mmio_start + mmio_len;
561 netdev->base_addr = adapter->hw.io_base;
562
563 adapter->bd_number = cards_found;
564
565 /* setup the private structure */
566
567 if((err = e1000_sw_init(adapter)))
568 goto err_sw_init;
569
2d7edb92
MC		 570 if((err = e1000_check_phy_reset_block(&adapter->hw)))
571 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
572
1da177e4
LT		 573 if(adapter->hw.mac_type >= e1000_82543) {
574 netdev->features = NETIF_F_SG |
575 NETIF_F_HW_CSUM |
576 NETIF_F_HW_VLAN_TX |
577 NETIF_F_HW_VLAN_RX |
578 NETIF_F_HW_VLAN_FILTER;
579 }
580
581#ifdef NETIF_F_TSO
582 if((adapter->hw.mac_type >= e1000_82544) &&
583 (adapter->hw.mac_type != e1000_82547))
584 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 585
586#ifdef NETIF_F_TSO_IPV6
587 if(adapter->hw.mac_type > e1000_82547_rev_2)
588 netdev->features |= NETIF_F_TSO_IPV6;
589#endif
1da177e4
LT		 590#endif
591 if(pci_using_dac)
592 netdev->features |= NETIF_F_HIGHDMA;
593
594 /* hard_start_xmit is safe against parallel locking */
595 netdev->features |= NETIF_F_LLTX;
596
2d7edb92
MC		 597 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
598
1da177e4
LT		 599 /* before reading the EEPROM, reset the controller to
600 * put the device in a known good starting state */
601
602 e1000_reset_hw(&adapter->hw);
603
604 /* make sure the EEPROM is good */
605
606 if(e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
607 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
608 err = -EIO;
609 goto err_eeprom;
610 }
611
612 /* copy the MAC address out of the EEPROM */
613
2648345f 614 if(e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 615 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
616 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 617 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 618
9beb0ac1 619 if(!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 620 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
621 err = -EIO;
622 goto err_eeprom;
623 }
624
625 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
626
627 e1000_get_bus_info(&adapter->hw);
628
629 init_timer(&adapter->tx_fifo_stall_timer);
630 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
631 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
632
633 init_timer(&adapter->watchdog_timer);
634 adapter->watchdog_timer.function = &e1000_watchdog;
635 adapter->watchdog_timer.data = (unsigned long) adapter;
636
637 INIT_WORK(&adapter->watchdog_task,
638 (void (*)(void *))e1000_watchdog_task, adapter);
639
640 init_timer(&adapter->phy_info_timer);
641 adapter->phy_info_timer.function = &e1000_update_phy_info;
642 adapter->phy_info_timer.data = (unsigned long) adapter;
643
644 INIT_WORK(&adapter->tx_timeout_task,
645 (void (*)(void *))e1000_tx_timeout_task, netdev);
646
647 /* we're going to reset, so assume we have no link for now */
648
649 netif_carrier_off(netdev);
650 netif_stop_queue(netdev);
651
652 e1000_check_options(adapter);
653
654 /* Initial Wake on LAN setting
655 * If APM wake is enabled in the EEPROM,
656 * enable the ACPI Magic Packet filter
657 */
658
659 switch(adapter->hw.mac_type) {
660 case e1000_82542_rev2_0:
661 case e1000_82542_rev2_1:
662 case e1000_82543:
663 break;
664 case e1000_82544:
665 e1000_read_eeprom(&adapter->hw,
666 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
667 eeprom_apme_mask = E1000_EEPROM_82544_APM;
668 break;
669 case e1000_82546:
670 case e1000_82546_rev_3:
671 if((E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
672 && (adapter->hw.media_type == e1000_media_type_copper)) {
673 e1000_read_eeprom(&adapter->hw,
674 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
675 break;
676 }
677 /* Fall Through */
678 default:
679 e1000_read_eeprom(&adapter->hw,
680 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
681 break;
682 }
683 if(eeprom_data & eeprom_apme_mask)
684 adapter->wol |= E1000_WUFC_MAG;
685
686 /* reset the hardware with the new settings */
687 e1000_reset(adapter);
688
2d7edb92
MC		 689 /* Let firmware know the driver has taken over */
690 switch(adapter->hw.mac_type) {
691 case e1000_82573:
692 swsm = E1000_READ_REG(&adapter->hw, SWSM);
693 E1000_WRITE_REG(&adapter->hw, SWSM,
694 swsm | E1000_SWSM_DRV_LOAD);
695 break;
696 default:
697 break;
698 }
699
1da177e4
LT		 700 strcpy(netdev->name, "eth%d");
701 if((err = register_netdev(netdev)))
702 goto err_register;
703
704 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
705
706 cards_found++;
707 return 0;
708
709err_register:
710err_sw_init:
711err_eeprom:
712 iounmap(adapter->hw.hw_addr);
713err_ioremap:
714 free_netdev(netdev);
715err_alloc_etherdev:
716 pci_release_regions(pdev);
717 return err;
718}
719
720/**
721 * e1000_remove - Device Removal Routine
722 * @pdev: PCI device information struct
723 *
724 * e1000_remove is called by the PCI subsystem to alert the driver
725 * that it should release a PCI device. The could be caused by a
726 * Hot-Plug event, or because the driver is going to be removed from
727 * memory.
728 **/
729
730static void __devexit
731e1000_remove(struct pci_dev *pdev)
732{
733 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 734 struct e1000_adapter *adapter = netdev_priv(netdev);
2d7edb92 735 uint32_t manc, swsm;
1da177e4
LT		 736
737 flush_scheduled_work();
738
739 if(adapter->hw.mac_type >= e1000_82540 &&
740 adapter->hw.media_type == e1000_media_type_copper) {
741 manc = E1000_READ_REG(&adapter->hw, MANC);
742 if(manc & E1000_MANC_SMBUS_EN) {
743 manc |= E1000_MANC_ARP_EN;
744 E1000_WRITE_REG(&adapter->hw, MANC, manc);
745 }
746 }
747
2d7edb92
MC		 748 switch(adapter->hw.mac_type) {
749 case e1000_82573:
750 swsm = E1000_READ_REG(&adapter->hw, SWSM);
751 E1000_WRITE_REG(&adapter->hw, SWSM,
752 swsm & ~E1000_SWSM_DRV_LOAD);
753 break;
754
755 default:
756 break;
757 }
758
1da177e4
LT		 759 unregister_netdev(netdev);
760
2d7edb92
MC		 761 if(!e1000_check_phy_reset_block(&adapter->hw))
762 e1000_phy_hw_reset(&adapter->hw);
1da177e4
LT		 763
764 iounmap(adapter->hw.hw_addr);
765 pci_release_regions(pdev);
766
767 free_netdev(netdev);
768
769 pci_disable_device(pdev);
770}
771
772/**
773 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
774 * @adapter: board private structure to initialize
775 *
776 * e1000_sw_init initializes the Adapter private data structure.
777 * Fields are initialized based on PCI device information and
778 * OS network device settings (MTU size).
779 **/
780
781static int __devinit
782e1000_sw_init(struct e1000_adapter *adapter)
783{
784 struct e1000_hw *hw = &adapter->hw;
785 struct net_device *netdev = adapter->netdev;
786 struct pci_dev *pdev = adapter->pdev;
787
788 /* PCI config space info */
789
790 hw->vendor_id = pdev->vendor;
791 hw->device_id = pdev->device;
792 hw->subsystem_vendor_id = pdev->subsystem_vendor;
793 hw->subsystem_id = pdev->subsystem_device;
794
795 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
796
797 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
798
799 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2d7edb92 800 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
1da177e4
LT		 801 hw->max_frame_size = netdev->mtu +
802 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
803 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
804
805 /* identify the MAC */
806
807 if(e1000_set_mac_type(hw)) {
808 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
809 return -EIO;
810 }
811
812 /* initialize eeprom parameters */
813
2d7edb92
MC		 814 if(e1000_init_eeprom_params(hw)) {
815 E1000_ERR("EEPROM initialization failed\n");
816 return -EIO;
817 }
1da177e4
LT		 818
819 switch(hw->mac_type) {
820 default:
821 break;
822 case e1000_82541:
823 case e1000_82547:
824 case e1000_82541_rev_2:
825 case e1000_82547_rev_2:
826 hw->phy_init_script = 1;
827 break;
828 }
829
830 e1000_set_media_type(hw);
831
832 hw->wait_autoneg_complete = FALSE;
833 hw->tbi_compatibility_en = TRUE;
834 hw->adaptive_ifs = TRUE;
835
836 /* Copper options */
837
838 if(hw->media_type == e1000_media_type_copper) {
839 hw->mdix = AUTO_ALL_MODES;
840 hw->disable_polarity_correction = FALSE;
841 hw->master_slave = E1000_MASTER_SLAVE;
842 }
843
844 atomic_set(&adapter->irq_sem, 1);
845 spin_lock_init(&adapter->stats_lock);
846 spin_lock_init(&adapter->tx_lock);
847
848 return 0;
849}
850
851/**
852 * e1000_open - Called when a network interface is made active
853 * @netdev: network interface device structure
854 *
855 * Returns 0 on success, negative value on failure
856 *
857 * The open entry point is called when a network interface is made
858 * active by the system (IFF_UP). At this point all resources needed
859 * for transmit and receive operations are allocated, the interrupt
860 * handler is registered with the OS, the watchdog timer is started,
861 * and the stack is notified that the interface is ready.
862 **/
863
864static int
865e1000_open(struct net_device *netdev)
866{
60490fe0 867 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 868 int err;
869
870 /* allocate transmit descriptors */
871
872 if((err = e1000_setup_tx_resources(adapter)))
873 goto err_setup_tx;
874
875 /* allocate receive descriptors */
876
877 if((err = e1000_setup_rx_resources(adapter)))
878 goto err_setup_rx;
879
880 if((err = e1000_up(adapter)))
881 goto err_up;
2d7edb92
MC		 882 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
883 if((adapter->hw.mng_cookie.status &
884 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
885 e1000_update_mng_vlan(adapter);
886 }
1da177e4
LT		 887
888 return E1000_SUCCESS;
889
890err_up:
891 e1000_free_rx_resources(adapter);
892err_setup_rx:
893 e1000_free_tx_resources(adapter);
894err_setup_tx:
895 e1000_reset(adapter);
896
897 return err;
898}
899
900/**
901 * e1000_close - Disables a network interface
902 * @netdev: network interface device structure
903 *
904 * Returns 0, this is not allowed to fail
905 *
906 * The close entry point is called when an interface is de-activated
907 * by the OS. The hardware is still under the drivers control, but
908 * needs to be disabled. A global MAC reset is issued to stop the
909 * hardware, and all transmit and receive resources are freed.
910 **/
911
912static int
913e1000_close(struct net_device *netdev)
914{
60490fe0 915 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 916
917 e1000_down(adapter);
918
919 e1000_free_tx_resources(adapter);
920 e1000_free_rx_resources(adapter);
921
2d7edb92
MC		 922 if((adapter->hw.mng_cookie.status &
923 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
924 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
925 }
1da177e4
LT		 926 return 0;
927}
928
929/**
930 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
931 * @adapter: address of board private structure
2d7edb92
MC		 932 * @start: address of beginning of memory
933 * @len: length of memory
1da177e4
LT		 934 **/
935static inline boolean_t
936e1000_check_64k_bound(struct e1000_adapter *adapter,
937 void *start, unsigned long len)
938{
939 unsigned long begin = (unsigned long) start;
940 unsigned long end = begin + len;
941
2648345f
MC		 942 /* First rev 82545 and 82546 need to not allow any memory
943 * write location to cross 64k boundary due to errata 23 */
1da177e4 944 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 945 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 946 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
947 }
948
949 return TRUE;
950}
951
952/**
953 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
954 * @adapter: board private structure
955 *
956 * Return 0 on success, negative on failure
957 **/
958
959int
960e1000_setup_tx_resources(struct e1000_adapter *adapter)
961{
962 struct e1000_desc_ring *txdr = &adapter->tx_ring;
963 struct pci_dev *pdev = adapter->pdev;
964 int size;
965
966 size = sizeof(struct e1000_buffer) * txdr->count;
967 txdr->buffer_info = vmalloc(size);
968 if(!txdr->buffer_info) {
2648345f
MC		 969 DPRINTK(PROBE, ERR,
970 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 971 return -ENOMEM;
972 }
973 memset(txdr->buffer_info, 0, size);
974
975 /* round up to nearest 4K */
976
977 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
978 E1000_ROUNDUP(txdr->size, 4096);
979
980 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
981 if(!txdr->desc) {
982setup_tx_desc_die:
1da177e4 983 vfree(txdr->buffer_info);
2648345f
MC		 984 DPRINTK(PROBE, ERR,
985 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 986 return -ENOMEM;
987 }
988
2648345f 989 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 990 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
991 void *olddesc = txdr->desc;
992 dma_addr_t olddma = txdr->dma;
2648345f
MC		 993 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
994 "at %p\n", txdr->size, txdr->desc);
995 /* Try again, without freeing the previous */
1da177e4 996 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1da177e4 997 if(!txdr->desc) {
2648345f 998 /* Failed allocation, critical failure */
1da177e4
LT		 999 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1000 goto setup_tx_desc_die;
1001 }
1002
1003 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1004 /* give up */
2648345f
MC		 1005 pci_free_consistent(pdev, txdr->size, txdr->desc,
1006 txdr->dma);
1da177e4
LT		 1007 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1008 DPRINTK(PROBE, ERR,
2648345f
MC		 1009 "Unable to allocate aligned memory "
1010 "for the transmit descriptor ring\n");
1da177e4
LT		 1011 vfree(txdr->buffer_info);
1012 return -ENOMEM;
1013 } else {
2648345f 1014 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1015 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1016 }
1017 }
1018 memset(txdr->desc, 0, txdr->size);
1019
1020 txdr->next_to_use = 0;
1021 txdr->next_to_clean = 0;
1022
1023 return 0;
1024}
1025
1026/**
1027 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1028 * @adapter: board private structure
1029 *
1030 * Configure the Tx unit of the MAC after a reset.
1031 **/
1032
1033static void
1034e1000_configure_tx(struct e1000_adapter *adapter)
1035{
1036 uint64_t tdba = adapter->tx_ring.dma;
1037 uint32_t tdlen = adapter->tx_ring.count * sizeof(struct e1000_tx_desc);
1038 uint32_t tctl, tipg;
1039
1040 E1000_WRITE_REG(&adapter->hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1041 E1000_WRITE_REG(&adapter->hw, TDBAH, (tdba >> 32));
1042
1043 E1000_WRITE_REG(&adapter->hw, TDLEN, tdlen);
1044
1045 /* Setup the HW Tx Head and Tail descriptor pointers */
1046
1047 E1000_WRITE_REG(&adapter->hw, TDH, 0);
1048 E1000_WRITE_REG(&adapter->hw, TDT, 0);
1049
1050 /* Set the default values for the Tx Inter Packet Gap timer */
1051
1052 switch (adapter->hw.mac_type) {
1053 case e1000_82542_rev2_0:
1054 case e1000_82542_rev2_1:
1055 tipg = DEFAULT_82542_TIPG_IPGT;
1056 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
1057 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
1058 break;
1059 default:
1060 if(adapter->hw.media_type == e1000_media_type_fiber ||
1061 adapter->hw.media_type == e1000_media_type_internal_serdes)
1062 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1063 else
1064 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1065 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
1066 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
1067 }
1068 E1000_WRITE_REG(&adapter->hw, TIPG, tipg);
1069
1070 /* Set the Tx Interrupt Delay register */
1071
1072 E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay);
1073 if(adapter->hw.mac_type >= e1000_82540)
1074 E1000_WRITE_REG(&adapter->hw, TADV, adapter->tx_abs_int_delay);
1075
1076 /* Program the Transmit Control Register */
1077
1078 tctl = E1000_READ_REG(&adapter->hw, TCTL);
1079
1080 tctl &= ~E1000_TCTL_CT;
1081 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
1082 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1083
1084 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
1085
1086 e1000_config_collision_dist(&adapter->hw);
1087
1088 /* Setup Transmit Descriptor Settings for eop descriptor */
1089 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1090 E1000_TXD_CMD_IFCS;
1091
1092 if(adapter->hw.mac_type < e1000_82543)
1093 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1094 else
1095 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1096
1097 /* Cache if we're 82544 running in PCI-X because we'll
1098 * need this to apply a workaround later in the send path. */
1099 if(adapter->hw.mac_type == e1000_82544 &&
1100 adapter->hw.bus_type == e1000_bus_type_pcix)
1101 adapter->pcix_82544 = 1;
1102}
1103
1104/**
1105 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1106 * @adapter: board private structure
1107 *
1108 * Returns 0 on success, negative on failure
1109 **/
1110
1111int
1112e1000_setup_rx_resources(struct e1000_adapter *adapter)
1113{
1114 struct e1000_desc_ring *rxdr = &adapter->rx_ring;
1115 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1116 int size, desc_len;
1da177e4
LT		 1117
1118 size = sizeof(struct e1000_buffer) * rxdr->count;
1119 rxdr->buffer_info = vmalloc(size);
1120 if(!rxdr->buffer_info) {
2648345f
MC		 1121 DPRINTK(PROBE, ERR,
1122 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1123 return -ENOMEM;
1124 }
1125 memset(rxdr->buffer_info, 0, size);
1126
2d7edb92
MC		 1127 size = sizeof(struct e1000_ps_page) * rxdr->count;
1128 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
1129 if(!rxdr->ps_page) {
1130 vfree(rxdr->buffer_info);
1131 DPRINTK(PROBE, ERR,
1132 "Unable to allocate memory for the receive descriptor ring\n");
1133 return -ENOMEM;
1134 }
1135 memset(rxdr->ps_page, 0, size);
1136
1137 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1138 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
1139 if(!rxdr->ps_page_dma) {
1140 vfree(rxdr->buffer_info);
1141 kfree(rxdr->ps_page);
1142 DPRINTK(PROBE, ERR,
1143 "Unable to allocate memory for the receive descriptor ring\n");
1144 return -ENOMEM;
1145 }
1146 memset(rxdr->ps_page_dma, 0, size);
1147
1148 if(adapter->hw.mac_type <= e1000_82547_rev_2)
1149 desc_len = sizeof(struct e1000_rx_desc);
1150 else
1151 desc_len = sizeof(union e1000_rx_desc_packet_split);
1152
1da177e4
LT		 1153 /* Round up to nearest 4K */
1154
2d7edb92 1155 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1156 E1000_ROUNDUP(rxdr->size, 4096);
1157
1158 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1159
1160 if(!rxdr->desc) {
1161setup_rx_desc_die:
1da177e4 1162 vfree(rxdr->buffer_info);
2d7edb92
MC		 1163 kfree(rxdr->ps_page);
1164 kfree(rxdr->ps_page_dma);
2648345f
MC		 1165 DPRINTK(PROBE, ERR,
1166 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1167 return -ENOMEM;
1168 }
1169
2648345f 1170 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1171 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1172 void *olddesc = rxdr->desc;
1173 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1174 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1175 "at %p\n", rxdr->size, rxdr->desc);
1176 /* Try again, without freeing the previous */
1da177e4 1177 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1da177e4 1178 if(!rxdr->desc) {
2648345f 1179 /* Failed allocation, critical failure */
1da177e4
LT		 1180 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1181 goto setup_rx_desc_die;
1182 }
1183
1184 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1185 /* give up */
2648345f
MC		 1186 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1187 rxdr->dma);
1da177e4 1188 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1189 DPRINTK(PROBE, ERR,
1190 "Unable to allocate aligned memory "
1191 "for the receive descriptor ring\n");
1da177e4 1192 vfree(rxdr->buffer_info);
2d7edb92
MC		 1193 kfree(rxdr->ps_page);
1194 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1195 return -ENOMEM;
1196 } else {
2648345f 1197 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1198 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1199 }
1200 }
1201 memset(rxdr->desc, 0, rxdr->size);
1202
1203 rxdr->next_to_clean = 0;
1204 rxdr->next_to_use = 0;
1205
1206 return 0;
1207}
1208
1209/**
2648345f 1210 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1211 * @adapter: Board private structure
1212 **/
1213
1214static void
1215e1000_setup_rctl(struct e1000_adapter *adapter)
1216{
2d7edb92
MC		 1217 uint32_t rctl, rfctl;
1218 uint32_t psrctl = 0;
1da177e4
LT		 1219
1220 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1221
1222 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1223
1224 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1225 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1226 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1227
1228 if(adapter->hw.tbi_compatibility_on == 1)
1229 rctl |= E1000_RCTL_SBP;
1230 else
1231 rctl &= ~E1000_RCTL_SBP;
1232
2d7edb92
MC		 1233 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1234 rctl &= ~E1000_RCTL_LPE;
1235 else
1236 rctl |= E1000_RCTL_LPE;
1237
1da177e4 1238 /* Setup buffer sizes */
2d7edb92
MC		 1239 if(adapter->hw.mac_type == e1000_82573) {
1240 /* We can now specify buffers in 1K increments.
1241 * BSIZE and BSEX are ignored in this case. */
1242 rctl |= adapter->rx_buffer_len << 0x11;
1243 } else {
1244 rctl &= ~E1000_RCTL_SZ_4096;
1245 rctl |= E1000_RCTL_BSEX;
1246 switch (adapter->rx_buffer_len) {
1247 case E1000_RXBUFFER_2048:
1248 default:
1249 rctl |= E1000_RCTL_SZ_2048;
1250 rctl &= ~E1000_RCTL_BSEX;
1251 break;
1252 case E1000_RXBUFFER_4096:
1253 rctl |= E1000_RCTL_SZ_4096;
1254 break;
1255 case E1000_RXBUFFER_8192:
1256 rctl |= E1000_RCTL_SZ_8192;
1257 break;
1258 case E1000_RXBUFFER_16384:
1259 rctl |= E1000_RCTL_SZ_16384;
1260 break;
1261 }
1262 }
1263
1264#ifdef CONFIG_E1000_PACKET_SPLIT
1265 /* 82571 and greater support packet-split where the protocol
1266 * header is placed in skb->data and the packet data is
1267 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1268 * In the case of a non-split, skb->data is linearly filled,
1269 * followed by the page buffers. Therefore, skb->data is
1270 * sized to hold the largest protocol header.
1271 */
1272 adapter->rx_ps = (adapter->hw.mac_type > e1000_82547_rev_2)
1273 && (adapter->netdev->mtu
1274 < ((3 * PAGE_SIZE) + adapter->rx_ps_bsize0));
1275#endif
1276 if(adapter->rx_ps) {
1277 /* Configure extra packet-split registers */
1278 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1279 rfctl |= E1000_RFCTL_EXTEN;
1280 /* disable IPv6 packet split support */
1281 rfctl |= E1000_RFCTL_IPV6_DIS;
1282 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1283
1284 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
1285
1286 psrctl |= adapter->rx_ps_bsize0 >>
1287 E1000_PSRCTL_BSIZE0_SHIFT;
1288 psrctl |= PAGE_SIZE >>
1289 E1000_PSRCTL_BSIZE1_SHIFT;
1290 psrctl |= PAGE_SIZE <<
1291 E1000_PSRCTL_BSIZE2_SHIFT;
1292 psrctl |= PAGE_SIZE <<
1293 E1000_PSRCTL_BSIZE3_SHIFT;
1294
1295 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1296 }
1297
1298 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1299}
1300
1301/**
1302 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1303 * @adapter: board private structure
1304 *
1305 * Configure the Rx unit of the MAC after a reset.
1306 **/
1307
1308static void
1309e1000_configure_rx(struct e1000_adapter *adapter)
1310{
1311 uint64_t rdba = adapter->rx_ring.dma;
2d7edb92
MC		 1312 uint32_t rdlen, rctl, rxcsum;
1313
1314 if(adapter->rx_ps) {
1315 rdlen = adapter->rx_ring.count *
1316 sizeof(union e1000_rx_desc_packet_split);
1317 adapter->clean_rx = e1000_clean_rx_irq_ps;
1318 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1319 } else {
1320 rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc);
1321 adapter->clean_rx = e1000_clean_rx_irq;
1322 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1323 }
1da177e4
LT		 1324
1325 /* disable receives while setting up the descriptors */
1326 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1327 E1000_WRITE_REG(&adapter->hw, RCTL, rctl & ~E1000_RCTL_EN);
1328
1329 /* set the Receive Delay Timer Register */
1330 E1000_WRITE_REG(&adapter->hw, RDTR, adapter->rx_int_delay);
1331
1332 if(adapter->hw.mac_type >= e1000_82540) {
1333 E1000_WRITE_REG(&adapter->hw, RADV, adapter->rx_abs_int_delay);
1334 if(adapter->itr > 1)
1335 E1000_WRITE_REG(&adapter->hw, ITR,
1336 1000000000 / (adapter->itr * 256));
1337 }
1338
1339 /* Setup the Base and Length of the Rx Descriptor Ring */
1340 E1000_WRITE_REG(&adapter->hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1341 E1000_WRITE_REG(&adapter->hw, RDBAH, (rdba >> 32));
1342
1343 E1000_WRITE_REG(&adapter->hw, RDLEN, rdlen);
1344
1345 /* Setup the HW Rx Head and Tail Descriptor Pointers */
1346 E1000_WRITE_REG(&adapter->hw, RDH, 0);
1347 E1000_WRITE_REG(&adapter->hw, RDT, 0);
1348
1349 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
2d7edb92 1350 if(adapter->hw.mac_type >= e1000_82543) {
1da177e4 1351 rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
2d7edb92
MC		 1352 if(adapter->rx_csum == TRUE) {
1353 rxcsum |= E1000_RXCSUM_TUOFL;
1354
1355 /* Enable 82573 IPv4 payload checksum for UDP fragments
1356 * Must be used in conjunction with packet-split. */
1357 if((adapter->hw.mac_type > e1000_82547_rev_2) &&
1358 (adapter->rx_ps)) {
1359 rxcsum |= E1000_RXCSUM_IPPCSE;
1360 }
1361 } else {
1362 rxcsum &= ~E1000_RXCSUM_TUOFL;
1363 /* don't need to clear IPPCSE as it defaults to 0 */
1364 }
1da177e4
LT		 1365 E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum);
1366 }
1367
2d7edb92
MC		 1368 if (adapter->hw.mac_type == e1000_82573)
1369 E1000_WRITE_REG(&adapter->hw, ERT, 0x0100);
1370
1da177e4
LT		 1371 /* Enable Receives */
1372 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1373}
1374
1375/**
1376 * e1000_free_tx_resources - Free Tx Resources
1377 * @adapter: board private structure
1378 *
1379 * Free all transmit software resources
1380 **/
1381
1382void
1383e1000_free_tx_resources(struct e1000_adapter *adapter)
1384{
1385 struct pci_dev *pdev = adapter->pdev;
1386
1387 e1000_clean_tx_ring(adapter);
1388
1389 vfree(adapter->tx_ring.buffer_info);
1390 adapter->tx_ring.buffer_info = NULL;
1391
1392 pci_free_consistent(pdev, adapter->tx_ring.size,
1393 adapter->tx_ring.desc, adapter->tx_ring.dma);
1394
1395 adapter->tx_ring.desc = NULL;
1396}
1397
1398static inline void
1399e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1400 struct e1000_buffer *buffer_info)
1401{
1da177e4 1402 if(buffer_info->dma) {
2648345f
MC		 1403 pci_unmap_page(adapter->pdev,
1404 buffer_info->dma,
1405 buffer_info->length,
1406 PCI_DMA_TODEVICE);
1da177e4
LT		 1407 buffer_info->dma = 0;
1408 }
1409 if(buffer_info->skb) {
1410 dev_kfree_skb_any(buffer_info->skb);
1411 buffer_info->skb = NULL;
1412 }
1413}
1414
1415/**
1416 * e1000_clean_tx_ring - Free Tx Buffers
1417 * @adapter: board private structure
1418 **/
1419
1420static void
1421e1000_clean_tx_ring(struct e1000_adapter *adapter)
1422{
1423 struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
1424 struct e1000_buffer *buffer_info;
1425 unsigned long size;
1426 unsigned int i;
1427
1428 /* Free all the Tx ring sk_buffs */
1429
1430 if (likely(adapter->previous_buffer_info.skb != NULL)) {
2648345f 1431 e1000_unmap_and_free_tx_resource(adapter,
1da177e4
LT		 1432 &adapter->previous_buffer_info);
1433 }
1434
1435 for(i = 0; i < tx_ring->count; i++) {
1436 buffer_info = &tx_ring->buffer_info[i];
1437 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1438 }
1439
1440 size = sizeof(struct e1000_buffer) * tx_ring->count;
1441 memset(tx_ring->buffer_info, 0, size);
1442
1443 /* Zero out the descriptor ring */
1444
1445 memset(tx_ring->desc, 0, tx_ring->size);
1446
1447 tx_ring->next_to_use = 0;
1448 tx_ring->next_to_clean = 0;
1449
1450 E1000_WRITE_REG(&adapter->hw, TDH, 0);
1451 E1000_WRITE_REG(&adapter->hw, TDT, 0);
1452}
1453
1454/**
1455 * e1000_free_rx_resources - Free Rx Resources
1456 * @adapter: board private structure
1457 *
1458 * Free all receive software resources
1459 **/
1460
1461void
1462e1000_free_rx_resources(struct e1000_adapter *adapter)
1463{
1464 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
1465 struct pci_dev *pdev = adapter->pdev;
1466
1467 e1000_clean_rx_ring(adapter);
1468
1469 vfree(rx_ring->buffer_info);
1470 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1471 kfree(rx_ring->ps_page);
1472 rx_ring->ps_page = NULL;
1473 kfree(rx_ring->ps_page_dma);
1474 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1475
1476 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1477
1478 rx_ring->desc = NULL;
1479}
1480
1481/**
1482 * e1000_clean_rx_ring - Free Rx Buffers
1483 * @adapter: board private structure
1484 **/
1485
1486static void
1487e1000_clean_rx_ring(struct e1000_adapter *adapter)
1488{
1489 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
1490 struct e1000_buffer *buffer_info;
2d7edb92
MC		 1491 struct e1000_ps_page *ps_page;
1492 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 1493 struct pci_dev *pdev = adapter->pdev;
1494 unsigned long size;
2d7edb92 1495 unsigned int i, j;
1da177e4
LT		 1496
1497 /* Free all the Rx ring sk_buffs */
1498
1499 for(i = 0; i < rx_ring->count; i++) {
1500 buffer_info = &rx_ring->buffer_info[i];
1501 if(buffer_info->skb) {
2d7edb92
MC		 1502 ps_page = &rx_ring->ps_page[i];
1503 ps_page_dma = &rx_ring->ps_page_dma[i];
1da177e4
LT		 1504 pci_unmap_single(pdev,
1505 buffer_info->dma,
1506 buffer_info->length,
1507 PCI_DMA_FROMDEVICE);
1508
1509 dev_kfree_skb(buffer_info->skb);
1510 buffer_info->skb = NULL;
2d7edb92
MC		 1511
1512 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
1513 if(!ps_page->ps_page[j]) break;
1514 pci_unmap_single(pdev,
1515 ps_page_dma->ps_page_dma[j],
1516 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1517 ps_page_dma->ps_page_dma[j] = 0;
1518 put_page(ps_page->ps_page[j]);
1519 ps_page->ps_page[j] = NULL;
1520 }
1da177e4
LT		 1521 }
1522 }
1523
1524 size = sizeof(struct e1000_buffer) * rx_ring->count;
1525 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 1526 size = sizeof(struct e1000_ps_page) * rx_ring->count;
1527 memset(rx_ring->ps_page, 0, size);
1528 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
1529 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 1530
1531 /* Zero out the descriptor ring */
1532
1533 memset(rx_ring->desc, 0, rx_ring->size);
1534
1535 rx_ring->next_to_clean = 0;
1536 rx_ring->next_to_use = 0;
1537
1538 E1000_WRITE_REG(&adapter->hw, RDH, 0);
1539 E1000_WRITE_REG(&adapter->hw, RDT, 0);
1540}
1541
1542/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
1543 * and memory write and invalidate disabled for certain operations
1544 */
1545static void
1546e1000_enter_82542_rst(struct e1000_adapter *adapter)
1547{
1548 struct net_device *netdev = adapter->netdev;
1549 uint32_t rctl;
1550
1551 e1000_pci_clear_mwi(&adapter->hw);
1552
1553 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1554 rctl |= E1000_RCTL_RST;
1555 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1556 E1000_WRITE_FLUSH(&adapter->hw);
1557 mdelay(5);
1558
1559 if(netif_running(netdev))
1560 e1000_clean_rx_ring(adapter);
1561}
1562
1563static void
1564e1000_leave_82542_rst(struct e1000_adapter *adapter)
1565{
1566 struct net_device *netdev = adapter->netdev;
1567 uint32_t rctl;
1568
1569 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1570 rctl &= ~E1000_RCTL_RST;
1571 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1572 E1000_WRITE_FLUSH(&adapter->hw);
1573 mdelay(5);
1574
1575 if(adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1576 e1000_pci_set_mwi(&adapter->hw);
1577
1578 if(netif_running(netdev)) {
1579 e1000_configure_rx(adapter);
1580 e1000_alloc_rx_buffers(adapter);
1581 }
1582}
1583
1584/**
1585 * e1000_set_mac - Change the Ethernet Address of the NIC
1586 * @netdev: network interface device structure
1587 * @p: pointer to an address structure
1588 *
1589 * Returns 0 on success, negative on failure
1590 **/
1591
1592static int
1593e1000_set_mac(struct net_device *netdev, void *p)
1594{
60490fe0 1595 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1596 struct sockaddr *addr = p;
1597
1598 if(!is_valid_ether_addr(addr->sa_data))
1599 return -EADDRNOTAVAIL;
1600
1601 /* 82542 2.0 needs to be in reset to write receive address registers */
1602
1603 if(adapter->hw.mac_type == e1000_82542_rev2_0)
1604 e1000_enter_82542_rst(adapter);
1605
1606 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1607 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
1608
1609 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
1610
1611 if(adapter->hw.mac_type == e1000_82542_rev2_0)
1612 e1000_leave_82542_rst(adapter);
1613
1614 return 0;
1615}
1616
1617/**
1618 * e1000_set_multi - Multicast and Promiscuous mode set
1619 * @netdev: network interface device structure
1620 *
1621 * The set_multi entry point is called whenever the multicast address
1622 * list or the network interface flags are updated. This routine is
1623 * responsible for configuring the hardware for proper multicast,
1624 * promiscuous mode, and all-multi behavior.
1625 **/
1626
1627static void
1628e1000_set_multi(struct net_device *netdev)
1629{
60490fe0 1630 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1631 struct e1000_hw *hw = &adapter->hw;
1632 struct dev_mc_list *mc_ptr;
2648345f 1633 unsigned long flags;
1da177e4
LT		 1634 uint32_t rctl;
1635 uint32_t hash_value;
1636 int i;
1da177e4
LT		 1637
1638 spin_lock_irqsave(&adapter->tx_lock, flags);
1639
2648345f
MC		 1640 /* Check for Promiscuous and All Multicast modes */
1641
1da177e4
LT		 1642 rctl = E1000_READ_REG(hw, RCTL);
1643
1644 if(netdev->flags & IFF_PROMISC) {
1645 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1646 } else if(netdev->flags & IFF_ALLMULTI) {
1647 rctl |= E1000_RCTL_MPE;
1648 rctl &= ~E1000_RCTL_UPE;
1649 } else {
1650 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
1651 }
1652
1653 E1000_WRITE_REG(hw, RCTL, rctl);
1654
1655 /* 82542 2.0 needs to be in reset to write receive address registers */
1656
1657 if(hw->mac_type == e1000_82542_rev2_0)
1658 e1000_enter_82542_rst(adapter);
1659
1660 /* load the first 14 multicast address into the exact filters 1-14
1661 * RAR 0 is used for the station MAC adddress
1662 * if there are not 14 addresses, go ahead and clear the filters
1663 */
1664 mc_ptr = netdev->mc_list;
1665
1666 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
1667 if(mc_ptr) {
1668 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
1669 mc_ptr = mc_ptr->next;
1670 } else {
1671 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
1672 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
1673 }
1674 }
1675
1676 /* clear the old settings from the multicast hash table */
1677
1678 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
1679 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1680
1681 /* load any remaining addresses into the hash table */
1682
1683 for(; mc_ptr; mc_ptr = mc_ptr->next) {
1684 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
1685 e1000_mta_set(hw, hash_value);
1686 }
1687
1688 if(hw->mac_type == e1000_82542_rev2_0)
1689 e1000_leave_82542_rst(adapter);
1690
1691 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1692}
1693
1694/* Need to wait a few seconds after link up to get diagnostic information from
1695 * the phy */
1696
1697static void
1698e1000_update_phy_info(unsigned long data)
1699{
1700 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1701 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
1702}
1703
1704/**
1705 * e1000_82547_tx_fifo_stall - Timer Call-back
1706 * @data: pointer to adapter cast into an unsigned long
1707 **/
1708
1709static void
1710e1000_82547_tx_fifo_stall(unsigned long data)
1711{
1712 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1713 struct net_device *netdev = adapter->netdev;
1714 uint32_t tctl;
1715
1716 if(atomic_read(&adapter->tx_fifo_stall)) {
1717 if((E1000_READ_REG(&adapter->hw, TDT) ==
1718 E1000_READ_REG(&adapter->hw, TDH)) &&
1719 (E1000_READ_REG(&adapter->hw, TDFT) ==
1720 E1000_READ_REG(&adapter->hw, TDFH)) &&
1721 (E1000_READ_REG(&adapter->hw, TDFTS) ==
1722 E1000_READ_REG(&adapter->hw, TDFHS))) {
1723 tctl = E1000_READ_REG(&adapter->hw, TCTL);
1724 E1000_WRITE_REG(&adapter->hw, TCTL,
1725 tctl & ~E1000_TCTL_EN);
1726 E1000_WRITE_REG(&adapter->hw, TDFT,
1727 adapter->tx_head_addr);
1728 E1000_WRITE_REG(&adapter->hw, TDFH,
1729 adapter->tx_head_addr);
1730 E1000_WRITE_REG(&adapter->hw, TDFTS,
1731 adapter->tx_head_addr);
1732 E1000_WRITE_REG(&adapter->hw, TDFHS,
1733 adapter->tx_head_addr);
1734 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
1735 E1000_WRITE_FLUSH(&adapter->hw);
1736
1737 adapter->tx_fifo_head = 0;
1738 atomic_set(&adapter->tx_fifo_stall, 0);
1739 netif_wake_queue(netdev);
1740 } else {
1741 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
1742 }
1743 }
1744}
1745
1746/**
1747 * e1000_watchdog - Timer Call-back
1748 * @data: pointer to adapter cast into an unsigned long
1749 **/
1750static void
1751e1000_watchdog(unsigned long data)
1752{
1753 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1754
1755 /* Do the rest outside of interrupt context */
1756 schedule_work(&adapter->watchdog_task);
1757}
1758
1759static void
1760e1000_watchdog_task(struct e1000_adapter *adapter)
1761{
1762 struct net_device *netdev = adapter->netdev;
1763 struct e1000_desc_ring *txdr = &adapter->tx_ring;
1764 uint32_t link;
1765
1766 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 1767 if (adapter->hw.mac_type == e1000_82573) {
1768 e1000_enable_tx_pkt_filtering(&adapter->hw);
1769 if(adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
1770 e1000_update_mng_vlan(adapter);
1771 }
1da177e4
LT		 1772
1773 if((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1774 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
1775 link = !adapter->hw.serdes_link_down;
1776 else
1777 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
1778
1779 if(link) {
1780 if(!netif_carrier_ok(netdev)) {
1781 e1000_get_speed_and_duplex(&adapter->hw,
1782 &adapter->link_speed,
1783 &adapter->link_duplex);
1784
1785 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
1786 adapter->link_speed,
1787 adapter->link_duplex == FULL_DUPLEX ?
1788 "Full Duplex" : "Half Duplex");
1789
1790 netif_carrier_on(netdev);
1791 netif_wake_queue(netdev);
1792 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
1793 adapter->smartspeed = 0;
1794 }
1795 } else {
1796 if(netif_carrier_ok(netdev)) {
1797 adapter->link_speed = 0;
1798 adapter->link_duplex = 0;
1799 DPRINTK(LINK, INFO, "NIC Link is Down\n");
1800 netif_carrier_off(netdev);
1801 netif_stop_queue(netdev);
1802 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
1803 }
1804
1805 e1000_smartspeed(adapter);
1806 }
1807
1808 e1000_update_stats(adapter);
1809
1810 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
1811 adapter->tpt_old = adapter->stats.tpt;
1812 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
1813 adapter->colc_old = adapter->stats.colc;
1814
1815 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
1816 adapter->gorcl_old = adapter->stats.gorcl;
1817 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
1818 adapter->gotcl_old = adapter->stats.gotcl;
1819
1820 e1000_update_adaptive(&adapter->hw);
1821
1822 if(!netif_carrier_ok(netdev)) {
1823 if(E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1824 /* We've lost link, so the controller stops DMA,
1825 * but we've got queued Tx work that's never going
1826 * to get done, so reset controller to flush Tx.
1827 * (Do the reset outside of interrupt context). */
1828 schedule_work(&adapter->tx_timeout_task);
1829 }
1830 }
1831
1832 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
1833 if(adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1834 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
1835 * asymmetrical Tx or Rx gets ITR=8000; everyone
1836 * else is between 2000-8000. */
1837 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
1838 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1839 adapter->gotcl - adapter->gorcl :
1840 adapter->gorcl - adapter->gotcl) / 10000;
1841 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
1842 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
1843 }
1844
1845 /* Cause software interrupt to ensure rx ring is cleaned */
1846 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
1847
2648345f 1848 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 1849 adapter->detect_tx_hung = TRUE;
1850
1851 /* Reset the timer */
1852 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
1853}
1854
1855#define E1000_TX_FLAGS_CSUM 0x00000001
1856#define E1000_TX_FLAGS_VLAN 0x00000002
1857#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 1858#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 1859#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
1860#define E1000_TX_FLAGS_VLAN_SHIFT 16
1861
1862static inline int
1863e1000_tso(struct e1000_adapter *adapter, struct sk_buff *skb)
1864{
1865#ifdef NETIF_F_TSO
1866 struct e1000_context_desc *context_desc;
1867 unsigned int i;
1868 uint32_t cmd_length = 0;
2d7edb92 1869 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 1870 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
1871 int err;
1872
1873 if(skb_shinfo(skb)->tso_size) {
1874 if (skb_header_cloned(skb)) {
1875 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1876 if (err)
1877 return err;
1878 }
1879
1880 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
1881 mss = skb_shinfo(skb)->tso_size;
2d7edb92
MC		 1882 if(skb->protocol == ntohs(ETH_P_IP)) {
1883 skb->nh.iph->tot_len = 0;
1884 skb->nh.iph->check = 0;
1885 skb->h.th->check =
1886 ~csum_tcpudp_magic(skb->nh.iph->saddr,
1887 skb->nh.iph->daddr,
1888 0,
1889 IPPROTO_TCP,
1890 0);
1891 cmd_length = E1000_TXD_CMD_IP;
1892 ipcse = skb->h.raw - skb->data - 1;
1893#ifdef NETIF_F_TSO_IPV6
1894 } else if(skb->protocol == ntohs(ETH_P_IPV6)) {
1895 skb->nh.ipv6h->payload_len = 0;
1896 skb->h.th->check =
1897 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
1898 &skb->nh.ipv6h->daddr,
1899 0,
1900 IPPROTO_TCP,
1901 0);
1902 ipcse = 0;
1903#endif
1904 }
1da177e4
LT		 1905 ipcss = skb->nh.raw - skb->data;
1906 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 1907 tucss = skb->h.raw - skb->data;
1908 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
1909 tucse = 0;
1910
1911 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 1912 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4
LT		 1913
1914 i = adapter->tx_ring.next_to_use;
1915 context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i);
1916
1917 context_desc->lower_setup.ip_fields.ipcss = ipcss;
1918 context_desc->lower_setup.ip_fields.ipcso = ipcso;
1919 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
1920 context_desc->upper_setup.tcp_fields.tucss = tucss;
1921 context_desc->upper_setup.tcp_fields.tucso = tucso;
1922 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
1923 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
1924 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
1925 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
1926
1927 if(++i == adapter->tx_ring.count) i = 0;
1928 adapter->tx_ring.next_to_use = i;
1929
1930 return 1;
1931 }
1932#endif
1933
1934 return 0;
1935}
1936
1937static inline boolean_t
1938e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb)
1939{
1940 struct e1000_context_desc *context_desc;
1941 unsigned int i;
1942 uint8_t css;
1943
1944 if(likely(skb->ip_summed == CHECKSUM_HW)) {
1945 css = skb->h.raw - skb->data;
1946
1947 i = adapter->tx_ring.next_to_use;
1948 context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i);
1949
1950 context_desc->upper_setup.tcp_fields.tucss = css;
1951 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
1952 context_desc->upper_setup.tcp_fields.tucse = 0;
1953 context_desc->tcp_seg_setup.data = 0;
1954 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
1955
1956 if(unlikely(++i == adapter->tx_ring.count)) i = 0;
1957 adapter->tx_ring.next_to_use = i;
1958
1959 return TRUE;
1960 }
1961
1962 return FALSE;
1963}
1964
1965#define E1000_MAX_TXD_PWR 12
1966#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
1967
1968static inline int
1969e1000_tx_map(struct e1000_adapter *adapter, struct sk_buff *skb,
1970 unsigned int first, unsigned int max_per_txd,
1971 unsigned int nr_frags, unsigned int mss)
1972{
1973 struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
1974 struct e1000_buffer *buffer_info;
1975 unsigned int len = skb->len;
1976 unsigned int offset = 0, size, count = 0, i;
1977 unsigned int f;
1978 len -= skb->data_len;
1979
1980 i = tx_ring->next_to_use;
1981
1982 while(len) {
1983 buffer_info = &tx_ring->buffer_info[i];
1984 size = min(len, max_per_txd);
1985#ifdef NETIF_F_TSO
1986 /* Workaround for premature desc write-backs
1987 * in TSO mode. Append 4-byte sentinel desc */
1988 if(unlikely(mss && !nr_frags && size == len && size > 8))
1989 size -= 4;
1990#endif
97338bde
MC		 1991 /* work-around for errata 10 and it applies
1992 * to all controllers in PCI-X mode
1993 * The fix is to make sure that the first descriptor of a
1994 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
1995 */
1996 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
1997 (size > 2015) && count == 0))
1998 size = 2015;
1999
1da177e4
LT		 2000 /* Workaround for potential 82544 hang in PCI-X. Avoid
2001 * terminating buffers within evenly-aligned dwords. */
2002 if(unlikely(adapter->pcix_82544 &&
2003 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2004 size > 4))
2005 size -= 4;
2006
2007 buffer_info->length = size;
2008 buffer_info->dma =
2009 pci_map_single(adapter->pdev,
2010 skb->data + offset,
2011 size,
2012 PCI_DMA_TODEVICE);
2013 buffer_info->time_stamp = jiffies;
2014
2015 len -= size;
2016 offset += size;
2017 count++;
2018 if(unlikely(++i == tx_ring->count)) i = 0;
2019 }
2020
2021 for(f = 0; f < nr_frags; f++) {
2022 struct skb_frag_struct *frag;
2023
2024 frag = &skb_shinfo(skb)->frags[f];
2025 len = frag->size;
2026 offset = frag->page_offset;
2027
2028 while(len) {
2029 buffer_info = &tx_ring->buffer_info[i];
2030 size = min(len, max_per_txd);
2031#ifdef NETIF_F_TSO
2032 /* Workaround for premature desc write-backs
2033 * in TSO mode. Append 4-byte sentinel desc */
2034 if(unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
2035 size -= 4;
2036#endif
2037 /* Workaround for potential 82544 hang in PCI-X.
2038 * Avoid terminating buffers within evenly-aligned
2039 * dwords. */
2040 if(unlikely(adapter->pcix_82544 &&
2041 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2042 size > 4))
2043 size -= 4;
2044
2045 buffer_info->length = size;
2046 buffer_info->dma =
2047 pci_map_page(adapter->pdev,
2048 frag->page,
2049 offset,
2050 size,
2051 PCI_DMA_TODEVICE);
2052 buffer_info->time_stamp = jiffies;
2053
2054 len -= size;
2055 offset += size;
2056 count++;
2057 if(unlikely(++i == tx_ring->count)) i = 0;
2058 }
2059 }
2060
2061 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2062 tx_ring->buffer_info[i].skb = skb;
2063 tx_ring->buffer_info[first].next_to_watch = i;
2064
2065 return count;
2066}
2067
2068static inline void
2069e1000_tx_queue(struct e1000_adapter *adapter, int count, int tx_flags)
2070{
2071 struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
2072 struct e1000_tx_desc *tx_desc = NULL;
2073 struct e1000_buffer *buffer_info;
2074 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2075 unsigned int i;
2076
2077 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) {
2078 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2079 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2080 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2081
2082 if(likely(tx_flags & E1000_TX_FLAGS_IPV4))
2083 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2084 }
2085
2086 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
2087 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2088 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2089 }
2090
2091 if(unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
2092 txd_lower |= E1000_TXD_CMD_VLE;
2093 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2094 }
2095
2096 i = tx_ring->next_to_use;
2097
2098 while(count--) {
2099 buffer_info = &tx_ring->buffer_info[i];
2100 tx_desc = E1000_TX_DESC(*tx_ring, i);
2101 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2102 tx_desc->lower.data =
2103 cpu_to_le32(txd_lower | buffer_info->length);
2104 tx_desc->upper.data = cpu_to_le32(txd_upper);
2105 if(unlikely(++i == tx_ring->count)) i = 0;
2106 }
2107
2108 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2109
2110 /* Force memory writes to complete before letting h/w
2111 * know there are new descriptors to fetch. (Only
2112 * applicable for weak-ordered memory model archs,
2113 * such as IA-64). */
2114 wmb();
2115
2116 tx_ring->next_to_use = i;
2117 E1000_WRITE_REG(&adapter->hw, TDT, i);
2118}
2119
2120/**
2121 * 82547 workaround to avoid controller hang in half-duplex environment.
2122 * The workaround is to avoid queuing a large packet that would span
2123 * the internal Tx FIFO ring boundary by notifying the stack to resend
2124 * the packet at a later time. This gives the Tx FIFO an opportunity to
2125 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2126 * to the beginning of the Tx FIFO.
2127 **/
2128
2129#define E1000_FIFO_HDR 0x10
2130#define E1000_82547_PAD_LEN 0x3E0
2131
2132static inline int
2133e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2134{
2135 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2136 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2137
2138 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2139
2140 if(adapter->link_duplex != HALF_DUPLEX)
2141 goto no_fifo_stall_required;
2142
2143 if(atomic_read(&adapter->tx_fifo_stall))
2144 return 1;
2145
2146 if(skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
2147 atomic_set(&adapter->tx_fifo_stall, 1);
2148 return 1;
2149 }
2150
2151no_fifo_stall_required:
2152 adapter->tx_fifo_head += skb_fifo_len;
2153 if(adapter->tx_fifo_head >= adapter->tx_fifo_size)
2154 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2155 return 0;
2156}
2157
2d7edb92
MC		 2158#define MINIMUM_DHCP_PACKET_SIZE 282
2159static inline int
2160e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2161{
2162 struct e1000_hw *hw = &adapter->hw;
2163 uint16_t length, offset;
2164 if(vlan_tx_tag_present(skb)) {
2165 if(!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2166 ( adapter->hw.mng_cookie.status &
2167 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2168 return 0;
2169 }
2170 if(htons(ETH_P_IP) == skb->protocol) {
2171 const struct iphdr *ip = skb->nh.iph;
2172 if(IPPROTO_UDP == ip->protocol) {
2173 struct udphdr *udp = (struct udphdr *)(skb->h.uh);
2174 if(ntohs(udp->dest) == 67) {
2175 offset = (uint8_t *)udp + 8 - skb->data;
2176 length = skb->len - offset;
2177
2178 return e1000_mng_write_dhcp_info(hw,
2179 (uint8_t *)udp + 8, length);
2180 }
2181 }
2182 } else if((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
2183 struct ethhdr *eth = (struct ethhdr *) skb->data;
2184 if((htons(ETH_P_IP) == eth->h_proto)) {
2185 const struct iphdr *ip =
2186 (struct iphdr *)((uint8_t *)skb->data+14);
2187 if(IPPROTO_UDP == ip->protocol) {
2188 struct udphdr *udp =
2189 (struct udphdr *)((uint8_t *)ip +
2190 (ip->ihl << 2));
2191 if(ntohs(udp->dest) == 67) {
2192 offset = (uint8_t *)udp + 8 - skb->data;
2193 length = skb->len - offset;
2194
2195 return e1000_mng_write_dhcp_info(hw,
2196 (uint8_t *)udp + 8,
2197 length);
2198 }
2199 }
2200 }
2201 }
2202 return 0;
2203}
2204
1da177e4
LT		 2205#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2206static int
2207e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2208{
60490fe0 2209 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2210 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2211 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2212 unsigned int tx_flags = 0;
2213 unsigned int len = skb->len;
2214 unsigned long flags;
2215 unsigned int nr_frags = 0;
2216 unsigned int mss = 0;
2217 int count = 0;
2218 int tso;
2219 unsigned int f;
2220 len -= skb->data_len;
2221
2222 if(unlikely(skb->len <= 0)) {
2223 dev_kfree_skb_any(skb);
2224 return NETDEV_TX_OK;
2225 }
2226
2227#ifdef NETIF_F_TSO
2228 mss = skb_shinfo(skb)->tso_size;
2648345f 2229 /* The controller does a simple calculation to
1da177e4
LT		 2230 * make sure there is enough room in the FIFO before
2231 * initiating the DMA for each buffer. The calc is:
2232 * 4 = ceil(buffer len/mss). To make sure we don't
2233 * overrun the FIFO, adjust the max buffer len if mss
2234 * drops. */
2235 if(mss) {
2236 max_per_txd = min(mss << 2, max_per_txd);
2237 max_txd_pwr = fls(max_per_txd) - 1;
2238 }
2239
2240 if((mss) || (skb->ip_summed == CHECKSUM_HW))
2241 count++;
2648345f 2242 count++;
1da177e4
LT		 2243#else
2244 if(skb->ip_summed == CHECKSUM_HW)
2245 count++;
2246#endif
2247 count += TXD_USE_COUNT(len, max_txd_pwr);
2248
2249 if(adapter->pcix_82544)
2250 count++;
2251
97338bde
MC		 2252 /* work-around for errata 10 and it applies to all controllers
2253 * in PCI-X mode, so add one more descriptor to the count
2254 */
2255 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2256 (len > 2015)))
2257 count++;
2258
1da177e4
LT		 2259 nr_frags = skb_shinfo(skb)->nr_frags;
2260 for(f = 0; f < nr_frags; f++)
2261 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2262 max_txd_pwr);
2263 if(adapter->pcix_82544)
2264 count += nr_frags;
2265
2266 local_irq_save(flags);
2267 if (!spin_trylock(&adapter->tx_lock)) {
2268 /* Collision - tell upper layer to requeue */
2269 local_irq_restore(flags);
2270 return NETDEV_TX_LOCKED;
2271 }
2d7edb92
MC		 2272 if(adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
2273 e1000_transfer_dhcp_info(adapter, skb);
2274
1da177e4
LT		 2275
2276 /* need: count + 2 desc gap to keep tail from touching
2277 * head, otherwise try next time */
2278 if(unlikely(E1000_DESC_UNUSED(&adapter->tx_ring) < count + 2)) {
2279 netif_stop_queue(netdev);
2280 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2281 return NETDEV_TX_BUSY;
2282 }
2283
2284 if(unlikely(adapter->hw.mac_type == e1000_82547)) {
2285 if(unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
2286 netif_stop_queue(netdev);
2287 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
2288 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2289 return NETDEV_TX_BUSY;
2290 }
2291 }
2292
2293 if(unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
2294 tx_flags |= E1000_TX_FLAGS_VLAN;
2295 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2296 }
2297
2298 first = adapter->tx_ring.next_to_use;
2299
2300 tso = e1000_tso(adapter, skb);
2301 if (tso < 0) {
2302 dev_kfree_skb_any(skb);
b2b3d824 2303 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1da177e4
LT		 2304 return NETDEV_TX_OK;
2305 }
2306
2307 if (likely(tso))
2308 tx_flags |= E1000_TX_FLAGS_TSO;
2309 else if(likely(e1000_tx_csum(adapter, skb)))
2310 tx_flags |= E1000_TX_FLAGS_CSUM;
2311
2d7edb92
MC		 2312 /* Old method was to assume IPv4 packet by default if TSO was enabled.
2313 * 82573 hardware supports TSO capabilities for IPv6 as well...
2314 * no longer assume, we must. */
2315 if(likely(skb->protocol == ntohs(ETH_P_IP)))
2316 tx_flags |= E1000_TX_FLAGS_IPV4;
2317
1da177e4
LT		 2318 e1000_tx_queue(adapter,
2319 e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss),
2320 tx_flags);
2321
2322 netdev->trans_start = jiffies;
2323
2324 /* Make sure there is space in the ring for the next send. */
2325 if(unlikely(E1000_DESC_UNUSED(&adapter->tx_ring) < MAX_SKB_FRAGS + 2))
2326 netif_stop_queue(netdev);
2327
2328 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2329 return NETDEV_TX_OK;
2330}
2331
2332/**
2333 * e1000_tx_timeout - Respond to a Tx Hang
2334 * @netdev: network interface device structure
2335 **/
2336
2337static void
2338e1000_tx_timeout(struct net_device *netdev)
2339{
60490fe0 2340 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2341
2342 /* Do the reset outside of interrupt context */
2343 schedule_work(&adapter->tx_timeout_task);
2344}
2345
2346static void
2347e1000_tx_timeout_task(struct net_device *netdev)
2348{
60490fe0 2349 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2350
2351 e1000_down(adapter);
2352 e1000_up(adapter);
2353}
2354
2355/**
2356 * e1000_get_stats - Get System Network Statistics
2357 * @netdev: network interface device structure
2358 *
2359 * Returns the address of the device statistics structure.
2360 * The statistics are actually updated from the timer callback.
2361 **/
2362
2363static struct net_device_stats *
2364e1000_get_stats(struct net_device *netdev)
2365{
60490fe0 2366 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2367
2368 e1000_update_stats(adapter);
2369 return &adapter->net_stats;
2370}
2371
2372/**
2373 * e1000_change_mtu - Change the Maximum Transfer Unit
2374 * @netdev: network interface device structure
2375 * @new_mtu: new value for maximum frame size
2376 *
2377 * Returns 0 on success, negative on failure
2378 **/
2379
2380static int
2381e1000_change_mtu(struct net_device *netdev, int new_mtu)
2382{
60490fe0 2383 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2384 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
2385
2386 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
2387 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2388 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
2389 return -EINVAL;
2390 }
2391
2d7edb92
MC		 2392#define MAX_STD_JUMBO_FRAME_SIZE 9216
2393 /* might want this to be bigger enum check... */
2394 if (adapter->hw.mac_type == e1000_82573 &&
2395 max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2396 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2397 "on 82573\n");
1da177e4 2398 return -EINVAL;
2d7edb92 2399 }
1da177e4 2400
2d7edb92
MC		 2401 if(adapter->hw.mac_type > e1000_82547_rev_2) {
2402 adapter->rx_buffer_len = max_frame;
2403 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
1da177e4 2404 } else {
2d7edb92
MC		 2405 if(unlikely((adapter->hw.mac_type < e1000_82543) &&
2406 (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE))) {
2407 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2408 "on 82542\n");
2409 return -EINVAL;
2410
2411 } else {
2412 if(max_frame <= E1000_RXBUFFER_2048) {
2413 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2414 } else if(max_frame <= E1000_RXBUFFER_4096) {
2415 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
2416 } else if(max_frame <= E1000_RXBUFFER_8192) {
2417 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
2418 } else if(max_frame <= E1000_RXBUFFER_16384) {
2419 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
2420 }
2421 }
1da177e4
LT		 2422 }
2423
2d7edb92
MC		 2424 netdev->mtu = new_mtu;
2425
2426 if(netif_running(netdev)) {
1da177e4
LT		 2427 e1000_down(adapter);
2428 e1000_up(adapter);
2429 }
2430
1da177e4
LT		 2431 adapter->hw.max_frame_size = max_frame;
2432
2433 return 0;
2434}
2435
2436/**
2437 * e1000_update_stats - Update the board statistics counters
2438 * @adapter: board private structure
2439 **/
2440
2441void
2442e1000_update_stats(struct e1000_adapter *adapter)
2443{
2444 struct e1000_hw *hw = &adapter->hw;
2445 unsigned long flags;
2446 uint16_t phy_tmp;
2447
2448#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2449
2450 spin_lock_irqsave(&adapter->stats_lock, flags);
2451
2452 /* these counters are modified from e1000_adjust_tbi_stats,
2453 * called from the interrupt context, so they must only
2454 * be written while holding adapter->stats_lock
2455 */
2456
2457 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
2458 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
2459 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
2460 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
2461 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
2462 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
2463 adapter->stats.roc += E1000_READ_REG(hw, ROC);
2464 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
2465 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
2466 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
2467 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
2468 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
2469 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
2470
2471 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
2472 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
2473 adapter->stats.scc += E1000_READ_REG(hw, SCC);
2474 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
2475 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
2476 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
2477 adapter->stats.dc += E1000_READ_REG(hw, DC);
2478 adapter->stats.sec += E1000_READ_REG(hw, SEC);
2479 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
2480 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
2481 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
2482 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
2483 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
2484 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
2485 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
2486 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
2487 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
2488 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
2489 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
2490 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
2491 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
2492 adapter->stats.torl += E1000_READ_REG(hw, TORL);
2493 adapter->stats.torh += E1000_READ_REG(hw, TORH);
2494 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
2495 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
2496 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
2497 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
2498 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
2499 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
2500 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
2501 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
2502 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
2503 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
2504 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
2505
2506 /* used for adaptive IFS */
2507
2508 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
2509 adapter->stats.tpt += hw->tx_packet_delta;
2510 hw->collision_delta = E1000_READ_REG(hw, COLC);
2511 adapter->stats.colc += hw->collision_delta;
2512
2513 if(hw->mac_type >= e1000_82543) {
2514 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
2515 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
2516 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
2517 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
2518 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
2519 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
2520 }
2d7edb92
MC		 2521 if(hw->mac_type > e1000_82547_rev_2) {
2522 adapter->stats.iac += E1000_READ_REG(hw, IAC);
2523 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
2524 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
2525 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
2526 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
2527 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
2528 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
2529 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
2530 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
2531 }
1da177e4
LT		 2532
2533 /* Fill out the OS statistics structure */
2534
2535 adapter->net_stats.rx_packets = adapter->stats.gprc;
2536 adapter->net_stats.tx_packets = adapter->stats.gptc;
2537 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
2538 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
2539 adapter->net_stats.multicast = adapter->stats.mprc;
2540 adapter->net_stats.collisions = adapter->stats.colc;
2541
2542 /* Rx Errors */
2543
2544 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
2545 adapter->stats.crcerrs + adapter->stats.algnerrc +
6d915757
MC		 2546 adapter->stats.rlec + adapter->stats.mpc +
2547 adapter->stats.cexterr;
1da177e4
LT		 2548 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2549 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
2550 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
2551 adapter->net_stats.rx_fifo_errors = adapter->stats.mpc;
2552 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
2553
2554 /* Tx Errors */
2555
2556 adapter->net_stats.tx_errors = adapter->stats.ecol +
2557 adapter->stats.latecol;
2558 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
2559 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
2560 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
2561
2562 /* Tx Dropped needs to be maintained elsewhere */
2563
2564 /* Phy Stats */
2565
2566 if(hw->media_type == e1000_media_type_copper) {
2567 if((adapter->link_speed == SPEED_1000) &&
2568 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
2569 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
2570 adapter->phy_stats.idle_errors += phy_tmp;
2571 }
2572
2573 if((hw->mac_type <= e1000_82546) &&
2574 (hw->phy_type == e1000_phy_m88) &&
2575 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
2576 adapter->phy_stats.receive_errors += phy_tmp;
2577 }
2578
2579 spin_unlock_irqrestore(&adapter->stats_lock, flags);
2580}
2581
2582/**
2583 * e1000_intr - Interrupt Handler
2584 * @irq: interrupt number
2585 * @data: pointer to a network interface device structure
2586 * @pt_regs: CPU registers structure
2587 **/
2588
2589static irqreturn_t
2590e1000_intr(int irq, void *data, struct pt_regs *regs)
2591{
2592 struct net_device *netdev = data;
60490fe0 2593 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2594 struct e1000_hw *hw = &adapter->hw;
2595 uint32_t icr = E1000_READ_REG(hw, ICR);
2596#ifndef CONFIG_E1000_NAPI
2597 unsigned int i;
2598#endif
2599
2600 if(unlikely(!icr))
2601 return IRQ_NONE; /* Not our interrupt */
2602
2603 if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
2604 hw->get_link_status = 1;
2605 mod_timer(&adapter->watchdog_timer, jiffies);
2606 }
2607
2608#ifdef CONFIG_E1000_NAPI
2609 if(likely(netif_rx_schedule_prep(netdev))) {
2610
2611 /* Disable interrupts and register for poll. The flush
2612 of the posted write is intentionally left out.
2613 */
2614
2615 atomic_inc(&adapter->irq_sem);
2616 E1000_WRITE_REG(hw, IMC, ~0);
2617 __netif_rx_schedule(netdev);
2618 }
2619#else
2620 /* Writing IMC and IMS is needed for 82547.
2621 Due to Hub Link bus being occupied, an interrupt
2622 de-assertion message is not able to be sent.
2623 When an interrupt assertion message is generated later,
2624 two messages are re-ordered and sent out.
2625 That causes APIC to think 82547 is in de-assertion
2626 state, while 82547 is in assertion state, resulting
2627 in dead lock. Writing IMC forces 82547 into
2628 de-assertion state.
2629 */
2630 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){
2631 atomic_inc(&adapter->irq_sem);
2648345f 2632 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 2633 }
2634
2635 for(i = 0; i < E1000_MAX_INTR; i++)
2d7edb92 2636 if(unlikely(!adapter->clean_rx(adapter) &
1da177e4
LT		 2637 !e1000_clean_tx_irq(adapter)))
2638 break;
2639
2640 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
2641 e1000_irq_enable(adapter);
2642#endif
2643
2644 return IRQ_HANDLED;
2645}
2646
2647#ifdef CONFIG_E1000_NAPI
2648/**
2649 * e1000_clean - NAPI Rx polling callback
2650 * @adapter: board private structure
2651 **/
2652
2653static int
2654e1000_clean(struct net_device *netdev, int *budget)
2655{
60490fe0 2656 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2657 int work_to_do = min(*budget, netdev->quota);
2658 int tx_cleaned;
2659 int work_done = 0;
2648345f 2660
1da177e4 2661 tx_cleaned = e1000_clean_tx_irq(adapter);
2d7edb92 2662 adapter->clean_rx(adapter, &work_done, work_to_do);
1da177e4
LT		 2663
2664 *budget -= work_done;
2665 netdev->quota -= work_done;
2666
f0d11ed0 2667 if ((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
2b02893e 2668 /* If no Tx and not enough Rx work done, exit the polling mode */
1da177e4
LT		 2669 netif_rx_complete(netdev);
2670 e1000_irq_enable(adapter);
2671 return 0;
2672 }
2673
2674 return 1;
2675}
2676
2677#endif
2678/**
2679 * e1000_clean_tx_irq - Reclaim resources after transmit completes
2680 * @adapter: board private structure
2681 **/
2682
2683static boolean_t
2684e1000_clean_tx_irq(struct e1000_adapter *adapter)
2685{
2686 struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
2687 struct net_device *netdev = adapter->netdev;
2688 struct e1000_tx_desc *tx_desc, *eop_desc;
2689 struct e1000_buffer *buffer_info;
2690 unsigned int i, eop;
2691 boolean_t cleaned = FALSE;
2692
2693 i = tx_ring->next_to_clean;
2694 eop = tx_ring->buffer_info[i].next_to_watch;
2695 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2696
2697 while(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
2701234f
MC		 2698 /* Premature writeback of Tx descriptors clear (free buffers
2699 * and unmap pci_mapping) previous_buffer_info */
1da177e4 2700 if (likely(adapter->previous_buffer_info.skb != NULL)) {
2701234f 2701 e1000_unmap_and_free_tx_resource(adapter,
1da177e4
LT		 2702 &adapter->previous_buffer_info);
2703 }
2704
2705 for(cleaned = FALSE; !cleaned; ) {
2706 tx_desc = E1000_TX_DESC(*tx_ring, i);
2707 buffer_info = &tx_ring->buffer_info[i];
2708 cleaned = (i == eop);
2709
2701234f
MC		 2710#ifdef NETIF_F_TSO
2711 if (!(netdev->features & NETIF_F_TSO)) {
2712#endif
2713 e1000_unmap_and_free_tx_resource(adapter,
2714 buffer_info);
2715#ifdef NETIF_F_TSO
1da177e4 2716 } else {
2701234f
MC		 2717 if (cleaned) {
2718 memcpy(&adapter->previous_buffer_info,
2719 buffer_info,
2720 sizeof(struct e1000_buffer));
2721 memset(buffer_info, 0,
2722 sizeof(struct e1000_buffer));
2723 } else {
2724 e1000_unmap_and_free_tx_resource(
2725 adapter, buffer_info);
2726 }
1da177e4 2727 }
2701234f 2728#endif
1da177e4
LT		 2729
2730 tx_desc->buffer_addr = 0;
2731 tx_desc->lower.data = 0;
2732 tx_desc->upper.data = 0;
2733
1da177e4
LT		 2734 if(unlikely(++i == tx_ring->count)) i = 0;
2735 }
2736
2737 eop = tx_ring->buffer_info[i].next_to_watch;
2738 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2739 }
2740
2741 tx_ring->next_to_clean = i;
2742
2743 spin_lock(&adapter->tx_lock);
2744
2745 if(unlikely(cleaned && netif_queue_stopped(netdev) &&
2746 netif_carrier_ok(netdev)))
2747 netif_wake_queue(netdev);
2748
2749 spin_unlock(&adapter->tx_lock);
1da177e4 2750 if(adapter->detect_tx_hung) {
2648345f
MC		 2751
2752 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 2753 * check with the clearing of time_stamp and movement of i */
2754 adapter->detect_tx_hung = FALSE;
70b8f1e1
MC		 2755 if (tx_ring->buffer_info[i].dma &&
2756 time_after(jiffies, tx_ring->buffer_info[i].time_stamp + HZ)
2757 && !(E1000_READ_REG(&adapter->hw, STATUS) &
2758 E1000_STATUS_TXOFF)) {
2759
2760 /* detected Tx unit hang */
2761 i = tx_ring->next_to_clean;
2762 eop = tx_ring->buffer_info[i].next_to_watch;
2763 eop_desc = E1000_TX_DESC(*tx_ring, eop);
c6963ef5 2764 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
70b8f1e1
MC		 2765 " TDH <%x>\n"
2766 " TDT <%x>\n"
2767 " next_to_use <%x>\n"
2768 " next_to_clean <%x>\n"
2769 "buffer_info[next_to_clean]\n"
b4ee21f4 2770 " dma <%llx>\n"
70b8f1e1
MC		 2771 " time_stamp <%lx>\n"
2772 " next_to_watch <%x>\n"
2773 " jiffies <%lx>\n"
2774 " next_to_watch.status <%x>\n",
2775 E1000_READ_REG(&adapter->hw, TDH),
2776 E1000_READ_REG(&adapter->hw, TDT),
2777 tx_ring->next_to_use,
2778 i,
b4ee21f4 2779 (unsigned long long)tx_ring->buffer_info[i].dma,
70b8f1e1
MC		 2780 tx_ring->buffer_info[i].time_stamp,
2781 eop,
2782 jiffies,
2783 eop_desc->upper.fields.status);
1da177e4 2784 netif_stop_queue(netdev);
70b8f1e1 2785 }
1da177e4 2786 }
2701234f
MC		 2787#ifdef NETIF_F_TSO
2788
2789 if( unlikely(!(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
2790 time_after(jiffies, adapter->previous_buffer_info.time_stamp + HZ)))
2791 e1000_unmap_and_free_tx_resource(
2792 adapter, &adapter->previous_buffer_info);
1da177e4 2793
2701234f 2794#endif
1da177e4
LT		 2795 return cleaned;
2796}
2797
2798/**
2799 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 2800 * @adapter: board private structure
2801 * @status_err: receive descriptor status and error fields
2802 * @csum: receive descriptor csum field
2803 * @sk_buff: socket buffer with received data
1da177e4
LT		 2804 **/
2805
2806static inline void
2807e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 2808 uint32_t status_err, uint32_t csum,
2809 struct sk_buff *skb)
1da177e4 2810{
2d7edb92
MC		 2811 uint16_t status = (uint16_t)status_err;
2812 uint8_t errors = (uint8_t)(status_err >> 24);
2813 skb->ip_summed = CHECKSUM_NONE;
2814
1da177e4 2815 /* 82543 or newer only */
2d7edb92 2816 if(unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 2817 /* Ignore Checksum bit is set */
2d7edb92
MC		 2818 if(unlikely(status & E1000_RXD_STAT_IXSM)) return;
2819 /* TCP/UDP checksum error bit is set */
2820 if(unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 2821 /* let the stack verify checksum errors */
1da177e4 2822 adapter->hw_csum_err++;
2d7edb92
MC		 2823 return;
2824 }
2825 /* TCP/UDP Checksum has not been calculated */
2826 if(adapter->hw.mac_type <= e1000_82547_rev_2) {
2827 if(!(status & E1000_RXD_STAT_TCPCS))
2828 return;
1da177e4 2829 } else {
2d7edb92
MC		 2830 if(!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2831 return;
2832 }
2833 /* It must be a TCP or UDP packet with a valid checksum */
2834 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 2835 /* TCP checksum is good */
2836 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 2837 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
2838 /* IP fragment with UDP payload */
2839 /* Hardware complements the payload checksum, so we undo it
2840 * and then put the value in host order for further stack use.
2841 */
2842 csum = ntohl(csum ^ 0xFFFF);
2843 skb->csum = csum;
2844 skb->ip_summed = CHECKSUM_HW;
1da177e4 2845 }
2d7edb92 2846 adapter->hw_csum_good++;
1da177e4
LT		 2847}
2848
2849/**
2d7edb92 2850 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 2851 * @adapter: board private structure
2852 **/
2853
2854static boolean_t
2855#ifdef CONFIG_E1000_NAPI
2856e1000_clean_rx_irq(struct e1000_adapter *adapter, int *work_done,
2857 int work_to_do)
2858#else
2859e1000_clean_rx_irq(struct e1000_adapter *adapter)
2860#endif
2861{
2862 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
2863 struct net_device *netdev = adapter->netdev;
2864 struct pci_dev *pdev = adapter->pdev;
2865 struct e1000_rx_desc *rx_desc;
2866 struct e1000_buffer *buffer_info;
2867 struct sk_buff *skb;
2868 unsigned long flags;
2869 uint32_t length;
2870 uint8_t last_byte;
2871 unsigned int i;
2872 boolean_t cleaned = FALSE;
2873
2874 i = rx_ring->next_to_clean;
2875 rx_desc = E1000_RX_DESC(*rx_ring, i);
2876
2877 while(rx_desc->status & E1000_RXD_STAT_DD) {
2878 buffer_info = &rx_ring->buffer_info[i];
2879#ifdef CONFIG_E1000_NAPI
2880 if(*work_done >= work_to_do)
2881 break;
2882 (*work_done)++;
2883#endif
2884 cleaned = TRUE;
2885
2886 pci_unmap_single(pdev,
2887 buffer_info->dma,
2888 buffer_info->length,
2889 PCI_DMA_FROMDEVICE);
2890
2891 skb = buffer_info->skb;
2892 length = le16_to_cpu(rx_desc->length);
2893
2894 if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) {
2895 /* All receives must fit into a single buffer */
2896 E1000_DBG("%s: Receive packet consumed multiple"
2648345f 2897 " buffers\n", netdev->name);
1da177e4
LT		 2898 dev_kfree_skb_irq(skb);
2899 goto next_desc;
2900 }
2901
2902 if(unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
2903 last_byte = *(skb->data + length - 1);
2904 if(TBI_ACCEPT(&adapter->hw, rx_desc->status,
2905 rx_desc->errors, length, last_byte)) {
2906 spin_lock_irqsave(&adapter->stats_lock, flags);
2907 e1000_tbi_adjust_stats(&adapter->hw,
2908 &adapter->stats,
2909 length, skb->data);
2910 spin_unlock_irqrestore(&adapter->stats_lock,
2911 flags);
2912 length--;
2913 } else {
2914 dev_kfree_skb_irq(skb);
2915 goto next_desc;
2916 }
2917 }
2918
2919 /* Good Receive */
2920 skb_put(skb, length - ETHERNET_FCS_SIZE);
2921
2922 /* Receive Checksum Offload */
2d7edb92
MC		 2923 e1000_rx_checksum(adapter,
2924 (uint32_t)(rx_desc->status) |
2925 ((uint32_t)(rx_desc->errors) << 24),
2926 rx_desc->csum, skb);
1da177e4
LT		 2927 skb->protocol = eth_type_trans(skb, netdev);
2928#ifdef CONFIG_E1000_NAPI
2929 if(unlikely(adapter->vlgrp &&
2930 (rx_desc->status & E1000_RXD_STAT_VP))) {
2931 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 2932 le16_to_cpu(rx_desc->special) &
2933 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 2934 } else {
2935 netif_receive_skb(skb);
2936 }
2937#else /* CONFIG_E1000_NAPI */
2938 if(unlikely(adapter->vlgrp &&
2939 (rx_desc->status & E1000_RXD_STAT_VP))) {
2940 vlan_hwaccel_rx(skb, adapter->vlgrp,
2941 le16_to_cpu(rx_desc->special) &
2942 E1000_RXD_SPC_VLAN_MASK);
2943 } else {
2944 netif_rx(skb);
2945 }
2946#endif /* CONFIG_E1000_NAPI */
2947 netdev->last_rx = jiffies;
2948
2949next_desc:
2950 rx_desc->status = 0;
2951 buffer_info->skb = NULL;
2952 if(unlikely(++i == rx_ring->count)) i = 0;
2953
2954 rx_desc = E1000_RX_DESC(*rx_ring, i);
2955 }
1da177e4 2956 rx_ring->next_to_clean = i;
2d7edb92
MC		 2957 adapter->alloc_rx_buf(adapter);
2958
2959 return cleaned;
2960}
2961
2962/**
2963 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
2964 * @adapter: board private structure
2965 **/
2966
2967static boolean_t
2968#ifdef CONFIG_E1000_NAPI
2969e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, int *work_done,
2970 int work_to_do)
2971#else
2972e1000_clean_rx_irq_ps(struct e1000_adapter *adapter)
2973#endif
2974{
2975 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
2976 union e1000_rx_desc_packet_split *rx_desc;
2977 struct net_device *netdev = adapter->netdev;
2978 struct pci_dev *pdev = adapter->pdev;
2979 struct e1000_buffer *buffer_info;
2980 struct e1000_ps_page *ps_page;
2981 struct e1000_ps_page_dma *ps_page_dma;
2982 struct sk_buff *skb;
2983 unsigned int i, j;
2984 uint32_t length, staterr;
2985 boolean_t cleaned = FALSE;
2986
2987 i = rx_ring->next_to_clean;
2988 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 2989 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 2990
2991 while(staterr & E1000_RXD_STAT_DD) {
2992 buffer_info = &rx_ring->buffer_info[i];
2993 ps_page = &rx_ring->ps_page[i];
2994 ps_page_dma = &rx_ring->ps_page_dma[i];
2995#ifdef CONFIG_E1000_NAPI
2996 if(unlikely(*work_done >= work_to_do))
2997 break;
2998 (*work_done)++;
2999#endif
3000 cleaned = TRUE;
3001 pci_unmap_single(pdev, buffer_info->dma,
3002 buffer_info->length,
3003 PCI_DMA_FROMDEVICE);
3004
3005 skb = buffer_info->skb;
3006
3007 if(unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
3008 E1000_DBG("%s: Packet Split buffers didn't pick up"
3009 " the full packet\n", netdev->name);
3010 dev_kfree_skb_irq(skb);
3011 goto next_desc;
3012 }
1da177e4 3013
2d7edb92
MC		 3014 if(unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3015 dev_kfree_skb_irq(skb);
3016 goto next_desc;
3017 }
3018
3019 length = le16_to_cpu(rx_desc->wb.middle.length0);
3020
3021 if(unlikely(!length)) {
3022 E1000_DBG("%s: Last part of the packet spanning"
3023 " multiple descriptors\n", netdev->name);
3024 dev_kfree_skb_irq(skb);
3025 goto next_desc;
3026 }
3027
3028 /* Good Receive */
3029 skb_put(skb, length);
3030
3031 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
3032 if(!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
3033 break;
3034
3035 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3036 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3037 ps_page_dma->ps_page_dma[j] = 0;
3038 skb_shinfo(skb)->frags[j].page =
3039 ps_page->ps_page[j];
3040 ps_page->ps_page[j] = NULL;
3041 skb_shinfo(skb)->frags[j].page_offset = 0;
3042 skb_shinfo(skb)->frags[j].size = length;
3043 skb_shinfo(skb)->nr_frags++;
3044 skb->len += length;
3045 skb->data_len += length;
3046 }
3047
3048 e1000_rx_checksum(adapter, staterr,
3049 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
3050 skb->protocol = eth_type_trans(skb, netdev);
3051
3052#ifdef HAVE_RX_ZERO_COPY
3053 if(likely(rx_desc->wb.upper.header_status &
3054 E1000_RXDPS_HDRSTAT_HDRSP))
3055 skb_shinfo(skb)->zero_copy = TRUE;
3056#endif
3057#ifdef CONFIG_E1000_NAPI
3058 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3059 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3060 le16_to_cpu(rx_desc->wb.middle.vlan) &
3061 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3062 } else {
3063 netif_receive_skb(skb);
3064 }
3065#else /* CONFIG_E1000_NAPI */
3066 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3067 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3068 le16_to_cpu(rx_desc->wb.middle.vlan) &
3069 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3070 } else {
3071 netif_rx(skb);
3072 }
3073#endif /* CONFIG_E1000_NAPI */
3074 netdev->last_rx = jiffies;
3075
3076next_desc:
3077 rx_desc->wb.middle.status_error &= ~0xFF;
3078 buffer_info->skb = NULL;
3079 if(unlikely(++i == rx_ring->count)) i = 0;
3080
3081 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3082 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3083 }
3084 rx_ring->next_to_clean = i;
3085 adapter->alloc_rx_buf(adapter);
1da177e4
LT		 3086
3087 return cleaned;
3088}
3089
3090/**
2d7edb92 3091 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3092 * @adapter: address of board private structure
3093 **/
3094
3095static void
3096e1000_alloc_rx_buffers(struct e1000_adapter *adapter)
3097{
3098 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
3099 struct net_device *netdev = adapter->netdev;
3100 struct pci_dev *pdev = adapter->pdev;
3101 struct e1000_rx_desc *rx_desc;
3102 struct e1000_buffer *buffer_info;
3103 struct sk_buff *skb;
2648345f
MC		 3104 unsigned int i;
3105 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3106
3107 i = rx_ring->next_to_use;
3108 buffer_info = &rx_ring->buffer_info[i];
3109
3110 while(!buffer_info->skb) {
1da177e4 3111 skb = dev_alloc_skb(bufsz);
2648345f 3112
1da177e4
LT		 3113 if(unlikely(!skb)) {
3114 /* Better luck next round */
3115 break;
3116 }
3117
2648345f 3118 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3119 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3120 struct sk_buff *oldskb = skb;
2648345f
MC		 3121 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3122 "at %p\n", bufsz, skb->data);
3123 /* Try again, without freeing the previous */
1da177e4 3124 skb = dev_alloc_skb(bufsz);
2648345f 3125 /* Failed allocation, critical failure */
1da177e4
LT		 3126 if (!skb) {
3127 dev_kfree_skb(oldskb);
3128 break;
3129 }
2648345f 3130
1da177e4
LT		 3131 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3132 /* give up */
3133 dev_kfree_skb(skb);
3134 dev_kfree_skb(oldskb);
3135 break; /* while !buffer_info->skb */
3136 } else {
2648345f 3137 /* Use new allocation */
1da177e4
LT		 3138 dev_kfree_skb(oldskb);
3139 }
3140 }
1da177e4
LT		 3141 /* Make buffer alignment 2 beyond a 16 byte boundary
3142 * this will result in a 16 byte aligned IP header after
3143 * the 14 byte MAC header is removed
3144 */
3145 skb_reserve(skb, NET_IP_ALIGN);
3146
3147 skb->dev = netdev;
3148
3149 buffer_info->skb = skb;
3150 buffer_info->length = adapter->rx_buffer_len;
3151 buffer_info->dma = pci_map_single(pdev,
3152 skb->data,
3153 adapter->rx_buffer_len,
3154 PCI_DMA_FROMDEVICE);
3155
2648345f
MC		 3156 /* Fix for errata 23, can't cross 64kB boundary */
3157 if (!e1000_check_64k_bound(adapter,
3158 (void *)(unsigned long)buffer_info->dma,
3159 adapter->rx_buffer_len)) {
3160 DPRINTK(RX_ERR, ERR,
3161 "dma align check failed: %u bytes at %p\n",
3162 adapter->rx_buffer_len,
3163 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 3164 dev_kfree_skb(skb);
3165 buffer_info->skb = NULL;
3166
2648345f 3167 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 3168 adapter->rx_buffer_len,
3169 PCI_DMA_FROMDEVICE);
3170
3171 break; /* while !buffer_info->skb */
3172 }
1da177e4
LT		 3173 rx_desc = E1000_RX_DESC(*rx_ring, i);
3174 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3175
3176 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3177 /* Force memory writes to complete before letting h/w
3178 * know there are new descriptors to fetch. (Only
3179 * applicable for weak-ordered memory model archs,
3180 * such as IA-64). */
3181 wmb();
1da177e4
LT		 3182 E1000_WRITE_REG(&adapter->hw, RDT, i);
3183 }
3184
3185 if(unlikely(++i == rx_ring->count)) i = 0;
3186 buffer_info = &rx_ring->buffer_info[i];
3187 }
3188
3189 rx_ring->next_to_use = i;
3190}
3191
2d7edb92
MC		 3192/**
3193 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3194 * @adapter: address of board private structure
3195 **/
3196
3197static void
3198e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter)
3199{
3200 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
3201 struct net_device *netdev = adapter->netdev;
3202 struct pci_dev *pdev = adapter->pdev;
3203 union e1000_rx_desc_packet_split *rx_desc;
3204 struct e1000_buffer *buffer_info;
3205 struct e1000_ps_page *ps_page;
3206 struct e1000_ps_page_dma *ps_page_dma;
3207 struct sk_buff *skb;
3208 unsigned int i, j;
3209
3210 i = rx_ring->next_to_use;
3211 buffer_info = &rx_ring->buffer_info[i];
3212 ps_page = &rx_ring->ps_page[i];
3213 ps_page_dma = &rx_ring->ps_page_dma[i];
3214
3215 while(!buffer_info->skb) {
3216 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3217
3218 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
3219 if(unlikely(!ps_page->ps_page[j])) {
3220 ps_page->ps_page[j] =
3221 alloc_page(GFP_ATOMIC);
3222 if(unlikely(!ps_page->ps_page[j]))
3223 goto no_buffers;
3224 ps_page_dma->ps_page_dma[j] =
3225 pci_map_page(pdev,
3226 ps_page->ps_page[j],
3227 0, PAGE_SIZE,
3228 PCI_DMA_FROMDEVICE);
3229 }
3230 /* Refresh the desc even if buffer_addrs didn't
3231 * change because each write-back erases this info.
3232 */
3233 rx_desc->read.buffer_addr[j+1] =
3234 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
3235 }
3236
3237 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3238
3239 if(unlikely(!skb))
3240 break;
3241
3242 /* Make buffer alignment 2 beyond a 16 byte boundary
3243 * this will result in a 16 byte aligned IP header after
3244 * the 14 byte MAC header is removed
3245 */
3246 skb_reserve(skb, NET_IP_ALIGN);
3247
3248 skb->dev = netdev;
3249
3250 buffer_info->skb = skb;
3251 buffer_info->length = adapter->rx_ps_bsize0;
3252 buffer_info->dma = pci_map_single(pdev, skb->data,
3253 adapter->rx_ps_bsize0,
3254 PCI_DMA_FROMDEVICE);
3255
3256 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
3257
3258 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3259 /* Force memory writes to complete before letting h/w
3260 * know there are new descriptors to fetch. (Only
3261 * applicable for weak-ordered memory model archs,
3262 * such as IA-64). */
3263 wmb();
3264 /* Hardware increments by 16 bytes, but packet split
3265 * descriptors are 32 bytes...so we increment tail
3266 * twice as much.
3267 */
3268 E1000_WRITE_REG(&adapter->hw, RDT, i<<1);
3269 }
3270
3271 if(unlikely(++i == rx_ring->count)) i = 0;
3272 buffer_info = &rx_ring->buffer_info[i];
3273 ps_page = &rx_ring->ps_page[i];
3274 ps_page_dma = &rx_ring->ps_page_dma[i];
3275 }
3276
3277no_buffers:
3278 rx_ring->next_to_use = i;
3279}
3280
1da177e4
LT		 3281/**
3282 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
3283 * @adapter:
3284 **/
3285
3286static void
3287e1000_smartspeed(struct e1000_adapter *adapter)
3288{
3289 uint16_t phy_status;
3290 uint16_t phy_ctrl;
3291
3292 if((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
3293 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
3294 return;
3295
3296 if(adapter->smartspeed == 0) {
3297 /* If Master/Slave config fault is asserted twice,
3298 * we assume back-to-back */
3299 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
3300 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
3301 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
3302 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
3303 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
3304 if(phy_ctrl & CR_1000T_MS_ENABLE) {
3305 phy_ctrl &= ~CR_1000T_MS_ENABLE;
3306 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
3307 phy_ctrl);
3308 adapter->smartspeed++;
3309 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
3310 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
3311 &phy_ctrl)) {
3312 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
3313 MII_CR_RESTART_AUTO_NEG);
3314 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
3315 phy_ctrl);
3316 }
3317 }
3318 return;
3319 } else if(adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
3320 /* If still no link, perhaps using 2/3 pair cable */
3321 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
3322 phy_ctrl |= CR_1000T_MS_ENABLE;
3323 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
3324 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
3325 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
3326 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
3327 MII_CR_RESTART_AUTO_NEG);
3328 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
3329 }
3330 }
3331 /* Restart process after E1000_SMARTSPEED_MAX iterations */
3332 if(adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
3333 adapter->smartspeed = 0;
3334}
3335
3336/**
3337 * e1000_ioctl -
3338 * @netdev:
3339 * @ifreq:
3340 * @cmd:
3341 **/
3342
3343static int
3344e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3345{
3346 switch (cmd) {
3347 case SIOCGMIIPHY:
3348 case SIOCGMIIREG:
3349 case SIOCSMIIREG:
3350 return e1000_mii_ioctl(netdev, ifr, cmd);
3351 default:
3352 return -EOPNOTSUPP;
3353 }
3354}
3355
3356/**
3357 * e1000_mii_ioctl -
3358 * @netdev:
3359 * @ifreq:
3360 * @cmd:
3361 **/
3362
3363static int
3364e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3365{
60490fe0 3366 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3367 struct mii_ioctl_data *data = if_mii(ifr);
3368 int retval;
3369 uint16_t mii_reg;
3370 uint16_t spddplx;
97876fc6 3371 unsigned long flags;
1da177e4
LT		 3372
3373 if(adapter->hw.media_type != e1000_media_type_copper)
3374 return -EOPNOTSUPP;
3375
3376 switch (cmd) {
3377 case SIOCGMIIPHY:
3378 data->phy_id = adapter->hw.phy_addr;
3379 break;
3380 case SIOCGMIIREG:
97876fc6 3381 if(!capable(CAP_NET_ADMIN))
1da177e4 3382 return -EPERM;
97876fc6
MC		 3383 spin_lock_irqsave(&adapter->stats_lock, flags);
3384 if(e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
3385 &data->val_out)) {
3386 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 3387 return -EIO;
97876fc6
MC		 3388 }
3389 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 3390 break;
3391 case SIOCSMIIREG:
97876fc6 3392 if(!capable(CAP_NET_ADMIN))
1da177e4 3393 return -EPERM;
97876fc6 3394 if(data->reg_num & ~(0x1F))
1da177e4
LT		 3395 return -EFAULT;
3396 mii_reg = data->val_in;
97876fc6
MC		 3397 spin_lock_irqsave(&adapter->stats_lock, flags);
3398 if(e1000_write_phy_reg(&adapter->hw, data->reg_num,
3399 mii_reg)) {
3400 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 3401 return -EIO;
97876fc6
MC		 3402 }
3403 if(adapter->hw.phy_type == e1000_phy_m88) {
1da177e4
LT		 3404 switch (data->reg_num) {
3405 case PHY_CTRL:
3406 if(mii_reg & MII_CR_POWER_DOWN)
3407 break;
3408 if(mii_reg & MII_CR_AUTO_NEG_EN) {
3409 adapter->hw.autoneg = 1;
3410 adapter->hw.autoneg_advertised = 0x2F;
3411 } else {
3412 if (mii_reg & 0x40)
3413 spddplx = SPEED_1000;
3414 else if (mii_reg & 0x2000)
3415 spddplx = SPEED_100;
3416 else
3417 spddplx = SPEED_10;
3418 spddplx += (mii_reg & 0x100)
3419 ? FULL_DUPLEX :
3420 HALF_DUPLEX;
3421 retval = e1000_set_spd_dplx(adapter,
3422 spddplx);
97876fc6
MC		 3423 if(retval) {
3424 spin_unlock_irqrestore(
3425 &adapter->stats_lock,
3426 flags);
1da177e4 3427 return retval;
97876fc6 3428 }
1da177e4
LT		 3429 }
3430 if(netif_running(adapter->netdev)) {
3431 e1000_down(adapter);
3432 e1000_up(adapter);
3433 } else
3434 e1000_reset(adapter);
3435 break;
3436 case M88E1000_PHY_SPEC_CTRL:
3437 case M88E1000_EXT_PHY_SPEC_CTRL:
97876fc6
MC		 3438 if(e1000_phy_reset(&adapter->hw)) {
3439 spin_unlock_irqrestore(
3440 &adapter->stats_lock, flags);
1da177e4 3441 return -EIO;
97876fc6 3442 }
1da177e4
LT		 3443 break;
3444 }
3445 } else {
3446 switch (data->reg_num) {
3447 case PHY_CTRL:
3448 if(mii_reg & MII_CR_POWER_DOWN)
3449 break;
3450 if(netif_running(adapter->netdev)) {
3451 e1000_down(adapter);
3452 e1000_up(adapter);
3453 } else
3454 e1000_reset(adapter);
3455 break;
3456 }
3457 }
97876fc6 3458 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 3459 break;
3460 default:
3461 return -EOPNOTSUPP;
3462 }
3463 return E1000_SUCCESS;
3464}
3465
3466void
3467e1000_pci_set_mwi(struct e1000_hw *hw)
3468{
3469 struct e1000_adapter *adapter = hw->back;
2648345f 3470 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 3471
2648345f
MC		 3472 if(ret_val)
3473 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 3474}
3475
3476void
3477e1000_pci_clear_mwi(struct e1000_hw *hw)
3478{
3479 struct e1000_adapter *adapter = hw->back;
3480
3481 pci_clear_mwi(adapter->pdev);
3482}
3483
3484void
3485e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
3486{
3487 struct e1000_adapter *adapter = hw->back;
3488
3489 pci_read_config_word(adapter->pdev, reg, value);
3490}
3491
3492void
3493e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
3494{
3495 struct e1000_adapter *adapter = hw->back;
3496
3497 pci_write_config_word(adapter->pdev, reg, *value);
3498}
3499
3500uint32_t
3501e1000_io_read(struct e1000_hw *hw, unsigned long port)
3502{
3503 return inl(port);
3504}
3505
3506void
3507e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
3508{
3509 outl(value, port);
3510}
3511
3512static void
3513e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
3514{
60490fe0 3515 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3516 uint32_t ctrl, rctl;
3517
3518 e1000_irq_disable(adapter);
3519 adapter->vlgrp = grp;
3520
3521 if(grp) {
3522 /* enable VLAN tag insert/strip */
3523 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3524 ctrl |= E1000_CTRL_VME;
3525 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3526
3527 /* enable VLAN receive filtering */
3528 rctl = E1000_READ_REG(&adapter->hw, RCTL);
3529 rctl |= E1000_RCTL_VFE;
3530 rctl &= ~E1000_RCTL_CFIEN;
3531 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 3532 e1000_update_mng_vlan(adapter);
1da177e4
LT		 3533 } else {
3534 /* disable VLAN tag insert/strip */
3535 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3536 ctrl &= ~E1000_CTRL_VME;
3537 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3538
3539 /* disable VLAN filtering */
3540 rctl = E1000_READ_REG(&adapter->hw, RCTL);
3541 rctl &= ~E1000_RCTL_VFE;
3542 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92
MC		 3543 if(adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
3544 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3545 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3546 }
1da177e4
LT		 3547 }
3548
3549 e1000_irq_enable(adapter);
3550}
3551
3552static void
3553e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
3554{
60490fe0 3555 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3556 uint32_t vfta, index;
2d7edb92
MC		 3557 if((adapter->hw.mng_cookie.status &
3558 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
3559 (vid == adapter->mng_vlan_id))
3560 return;
1da177e4
LT		 3561 /* add VID to filter table */
3562 index = (vid >> 5) & 0x7F;
3563 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
3564 vfta |= (1 << (vid & 0x1F));
3565 e1000_write_vfta(&adapter->hw, index, vfta);
3566}
3567
3568static void
3569e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
3570{
60490fe0 3571 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3572 uint32_t vfta, index;
3573
3574 e1000_irq_disable(adapter);
3575
3576 if(adapter->vlgrp)
3577 adapter->vlgrp->vlan_devices[vid] = NULL;
3578
3579 e1000_irq_enable(adapter);
3580
2d7edb92
MC		 3581 if((adapter->hw.mng_cookie.status &
3582 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
3583 (vid == adapter->mng_vlan_id))
3584 return;
1da177e4
LT		 3585 /* remove VID from filter table */
3586 index = (vid >> 5) & 0x7F;
3587 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
3588 vfta &= ~(1 << (vid & 0x1F));
3589 e1000_write_vfta(&adapter->hw, index, vfta);
3590}
3591
3592static void
3593e1000_restore_vlan(struct e1000_adapter *adapter)
3594{
3595 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3596
3597 if(adapter->vlgrp) {
3598 uint16_t vid;
3599 for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3600 if(!adapter->vlgrp->vlan_devices[vid])
3601 continue;
3602 e1000_vlan_rx_add_vid(adapter->netdev, vid);
3603 }
3604 }
3605}
3606
3607int
3608e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
3609{
3610 adapter->hw.autoneg = 0;
3611
6921368f
MC		 3612 /* Fiber NICs only allow 1000 gbps Full duplex */
3613 if((adapter->hw.media_type == e1000_media_type_fiber) &&
3614 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3615 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
3616 return -EINVAL;
3617 }
3618
1da177e4
LT		 3619 switch(spddplx) {
3620 case SPEED_10 + DUPLEX_HALF:
3621 adapter->hw.forced_speed_duplex = e1000_10_half;
3622 break;
3623 case SPEED_10 + DUPLEX_FULL:
3624 adapter->hw.forced_speed_duplex = e1000_10_full;
3625 break;
3626 case SPEED_100 + DUPLEX_HALF:
3627 adapter->hw.forced_speed_duplex = e1000_100_half;
3628 break;
3629 case SPEED_100 + DUPLEX_FULL:
3630 adapter->hw.forced_speed_duplex = e1000_100_full;
3631 break;
3632 case SPEED_1000 + DUPLEX_FULL:
3633 adapter->hw.autoneg = 1;
3634 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
3635 break;
3636 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3637 default:
2648345f 3638 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 3639 return -EINVAL;
3640 }
3641 return 0;
3642}
3643
1da177e4 3644static int
829ca9a3 3645e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 3646{
3647 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 3648 struct e1000_adapter *adapter = netdev_priv(netdev);
2d7edb92 3649 uint32_t ctrl, ctrl_ext, rctl, manc, status, swsm;
1da177e4
LT		 3650 uint32_t wufc = adapter->wol;
3651
3652 netif_device_detach(netdev);
3653
3654 if(netif_running(netdev))
3655 e1000_down(adapter);
3656
3657 status = E1000_READ_REG(&adapter->hw, STATUS);
3658 if(status & E1000_STATUS_LU)
3659 wufc &= ~E1000_WUFC_LNKC;
3660
3661 if(wufc) {
3662 e1000_setup_rctl(adapter);
3663 e1000_set_multi(netdev);
3664
3665 /* turn on all-multi mode if wake on multicast is enabled */
3666 if(adapter->wol & E1000_WUFC_MC) {
3667 rctl = E1000_READ_REG(&adapter->hw, RCTL);
3668 rctl |= E1000_RCTL_MPE;
3669 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
3670 }
3671
3672 if(adapter->hw.mac_type >= e1000_82540) {
3673 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3674 /* advertise wake from D3Cold */
3675 #define E1000_CTRL_ADVD3WUC 0x00100000
3676 /* phy power management enable */
3677 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3678 ctrl |= E1000_CTRL_ADVD3WUC |
3679 E1000_CTRL_EN_PHY_PWR_MGMT;
3680 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3681 }
3682
3683 if(adapter->hw.media_type == e1000_media_type_fiber ||
3684 adapter->hw.media_type == e1000_media_type_internal_serdes) {
3685 /* keep the laser running in D3 */
3686 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
3687 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3688 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
3689 }
3690
2d7edb92
MC		 3691 /* Allow time for pending master requests to run */
3692 e1000_disable_pciex_master(&adapter->hw);
3693
1da177e4
LT		 3694 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
3695 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
3696 pci_enable_wake(pdev, 3, 1);
3697 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
3698 } else {
3699 E1000_WRITE_REG(&adapter->hw, WUC, 0);
3700 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
3701 pci_enable_wake(pdev, 3, 0);
3702 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
3703 }
3704
3705 pci_save_state(pdev);
3706
3707 if(adapter->hw.mac_type >= e1000_82540 &&
3708 adapter->hw.media_type == e1000_media_type_copper) {
3709 manc = E1000_READ_REG(&adapter->hw, MANC);
3710 if(manc & E1000_MANC_SMBUS_EN) {
3711 manc |= E1000_MANC_ARP_EN;
3712 E1000_WRITE_REG(&adapter->hw, MANC, manc);
3713 pci_enable_wake(pdev, 3, 1);
3714 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
3715 }
3716 }
3717
2d7edb92
MC		 3718 switch(adapter->hw.mac_type) {
3719 case e1000_82573:
3720 swsm = E1000_READ_REG(&adapter->hw, SWSM);
3721 E1000_WRITE_REG(&adapter->hw, SWSM,
3722 swsm & ~E1000_SWSM_DRV_LOAD);
3723 break;
3724 default:
3725 break;
3726 }
3727
1da177e4 3728 pci_disable_device(pdev);
829ca9a3 3729 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 3730
3731 return 0;
3732}
3733
3734#ifdef CONFIG_PM
3735static int
3736e1000_resume(struct pci_dev *pdev)
3737{
3738 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 3739 struct e1000_adapter *adapter = netdev_priv(netdev);
2b02893e 3740 uint32_t manc, ret_val, swsm;
1da177e4 3741
829ca9a3 3742 pci_set_power_state(pdev, PCI_D0);
1da177e4 3743 pci_restore_state(pdev);
2b02893e 3744 ret_val = pci_enable_device(pdev);
a4cb847d 3745 pci_set_master(pdev);
1da177e4 3746
829ca9a3
PM		 3747 pci_enable_wake(pdev, PCI_D3hot, 0);
3748 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 3749
3750 e1000_reset(adapter);
3751 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
3752
3753 if(netif_running(netdev))
3754 e1000_up(adapter);
3755
3756 netif_device_attach(netdev);
3757
3758 if(adapter->hw.mac_type >= e1000_82540 &&
3759 adapter->hw.media_type == e1000_media_type_copper) {
3760 manc = E1000_READ_REG(&adapter->hw, MANC);
3761 manc &= ~(E1000_MANC_ARP_EN);
3762 E1000_WRITE_REG(&adapter->hw, MANC, manc);
3763 }
3764
2d7edb92
MC		 3765 switch(adapter->hw.mac_type) {
3766 case e1000_82573:
3767 swsm = E1000_READ_REG(&adapter->hw, SWSM);
3768 E1000_WRITE_REG(&adapter->hw, SWSM,
3769 swsm | E1000_SWSM_DRV_LOAD);
3770 break;
3771 default:
3772 break;
3773 }
3774
1da177e4
LT		 3775 return 0;
3776}
3777#endif
1da177e4
LT		 3778#ifdef CONFIG_NET_POLL_CONTROLLER
3779/*
3780 * Polling 'interrupt' - used by things like netconsole to send skbs
3781 * without having to re-enable interrupts. It's not called while
3782 * the interrupt routine is executing.
3783 */
3784static void
2648345f 3785e1000_netpoll(struct net_device *netdev)
1da177e4 3786{
60490fe0 3787 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3788 disable_irq(adapter->pdev->irq);
3789 e1000_intr(adapter->pdev->irq, netdev, NULL);
6b0b3157 3790 e1000_clean_tx_irq(adapter);
1da177e4
LT		 3791 enable_irq(adapter->pdev->irq);
3792}
3793#endif
3794
3795/* e1000_main.c */
Linux kernel - Deliverables
This page took 0.238119 seconds and 5 git commands to generate.