projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] e1000: Fix flow control water marks
[deliverable/linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
2b02893e
MC		 32 * 6.0.58 4/20/05
33 * o Accepted ethtool cleanup patch from Stephen Hemminger
2648345f
MC		 34 * 6.0.44+ 2/15/05
35 * o applied Anton's patch to resolve tx hang in hardware
36 * o Applied Andrew Mortons patch - e1000 stops working after resume
1da177e4
LT		 37 */
38
39char e1000_driver_name[] = "e1000";
3ad2cc67 40static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 41#ifndef CONFIG_E1000_NAPI
42#define DRIVERNAPI
43#else
44#define DRIVERNAPI "-NAPI"
45#endif
4ee9c020 46#define DRV_VERSION "6.3.9-k2"DRIVERNAPI
1da177e4 47char e1000_driver_version[] = DRV_VERSION;
3ad2cc67 48static char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
1da177e4
LT		 49
50/* e1000_pci_tbl - PCI Device ID Table
51 *
52 * Last entry must be all 0s
53 *
54 * Macro expands to...
55 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
56 */
57static struct pci_device_id e1000_pci_tbl[] = {
58 INTEL_E1000_ETHERNET_DEVICE(0x1000),
59 INTEL_E1000_ETHERNET_DEVICE(0x1001),
60 INTEL_E1000_ETHERNET_DEVICE(0x1004),
61 INTEL_E1000_ETHERNET_DEVICE(0x1008),
62 INTEL_E1000_ETHERNET_DEVICE(0x1009),
63 INTEL_E1000_ETHERNET_DEVICE(0x100C),
64 INTEL_E1000_ETHERNET_DEVICE(0x100D),
65 INTEL_E1000_ETHERNET_DEVICE(0x100E),
66 INTEL_E1000_ETHERNET_DEVICE(0x100F),
67 INTEL_E1000_ETHERNET_DEVICE(0x1010),
68 INTEL_E1000_ETHERNET_DEVICE(0x1011),
69 INTEL_E1000_ETHERNET_DEVICE(0x1012),
70 INTEL_E1000_ETHERNET_DEVICE(0x1013),
71 INTEL_E1000_ETHERNET_DEVICE(0x1014),
72 INTEL_E1000_ETHERNET_DEVICE(0x1015),
73 INTEL_E1000_ETHERNET_DEVICE(0x1016),
74 INTEL_E1000_ETHERNET_DEVICE(0x1017),
75 INTEL_E1000_ETHERNET_DEVICE(0x1018),
76 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 77 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 78 INTEL_E1000_ETHERNET_DEVICE(0x101D),
79 INTEL_E1000_ETHERNET_DEVICE(0x101E),
80 INTEL_E1000_ETHERNET_DEVICE(0x1026),
81 INTEL_E1000_ETHERNET_DEVICE(0x1027),
82 INTEL_E1000_ETHERNET_DEVICE(0x1028),
07b8fede
MC		 83 INTEL_E1000_ETHERNET_DEVICE(0x105E),
84 INTEL_E1000_ETHERNET_DEVICE(0x105F),
85 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 86 INTEL_E1000_ETHERNET_DEVICE(0x1075),
87 INTEL_E1000_ETHERNET_DEVICE(0x1076),
88 INTEL_E1000_ETHERNET_DEVICE(0x1077),
89 INTEL_E1000_ETHERNET_DEVICE(0x1078),
90 INTEL_E1000_ETHERNET_DEVICE(0x1079),
91 INTEL_E1000_ETHERNET_DEVICE(0x107A),
92 INTEL_E1000_ETHERNET_DEVICE(0x107B),
93 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 94 INTEL_E1000_ETHERNET_DEVICE(0x107D),
95 INTEL_E1000_ETHERNET_DEVICE(0x107E),
96 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 97 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 98 INTEL_E1000_ETHERNET_DEVICE(0x108B),
99 INTEL_E1000_ETHERNET_DEVICE(0x108C),
07b8fede 100 INTEL_E1000_ETHERNET_DEVICE(0x109A),
1da177e4
LT		 101 /* required last entry */
102 {0,}
103};
104
105MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
106
107int e1000_up(struct e1000_adapter *adapter);
108void e1000_down(struct e1000_adapter *adapter);
109void e1000_reset(struct e1000_adapter *adapter);
110int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
581d708e
MC		 111int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
112int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
113void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
114void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67
AB		 115static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
116 struct e1000_tx_ring *txdr);
117static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
118 struct e1000_rx_ring *rxdr);
119static void e1000_free_tx_resources(struct e1000_adapter *adapter,
120 struct e1000_tx_ring *tx_ring);
121static void e1000_free_rx_resources(struct e1000_adapter *adapter,
122 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 123void e1000_update_stats(struct e1000_adapter *adapter);
124
125/* Local Function Prototypes */
126
127static int e1000_init_module(void);
128static void e1000_exit_module(void);
129static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
130static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e
MC		 131static int e1000_alloc_queues(struct e1000_adapter *adapter);
132#ifdef CONFIG_E1000_MQ
133static void e1000_setup_queue_mapping(struct e1000_adapter *adapter);
134#endif
1da177e4
LT		 135static int e1000_sw_init(struct e1000_adapter *adapter);
136static int e1000_open(struct net_device *netdev);
137static int e1000_close(struct net_device *netdev);
138static void e1000_configure_tx(struct e1000_adapter *adapter);
139static void e1000_configure_rx(struct e1000_adapter *adapter);
140static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 141static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
142static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
143static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
144 struct e1000_tx_ring *tx_ring);
145static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
146 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 147static void e1000_set_multi(struct net_device *netdev);
148static void e1000_update_phy_info(unsigned long data);
149static void e1000_watchdog(unsigned long data);
150static void e1000_watchdog_task(struct e1000_adapter *adapter);
151static void e1000_82547_tx_fifo_stall(unsigned long data);
152static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
153static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
154static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
155static int e1000_set_mac(struct net_device *netdev, void *p);
156static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 157static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
158 struct e1000_tx_ring *tx_ring);
1da177e4 159#ifdef CONFIG_E1000_NAPI
581d708e 160static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 161static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 162 struct e1000_rx_ring *rx_ring,
1da177e4 163 int *work_done, int work_to_do);
2d7edb92 164static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 165 struct e1000_rx_ring *rx_ring,
2d7edb92 166 int *work_done, int work_to_do);
1da177e4 167#else
581d708e
MC		 168static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
169 struct e1000_rx_ring *rx_ring);
170static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
171 struct e1000_rx_ring *rx_ring);
1da177e4 172#endif
581d708e
MC		 173static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
174 struct e1000_rx_ring *rx_ring);
175static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
176 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 177static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
178static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
179 int cmd);
180void e1000_set_ethtool_ops(struct net_device *netdev);
181static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
182static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
183static void e1000_tx_timeout(struct net_device *dev);
184static void e1000_tx_timeout_task(struct net_device *dev);
185static void e1000_smartspeed(struct e1000_adapter *adapter);
186static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
187 struct sk_buff *skb);
188
189static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
190static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
191static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
192static void e1000_restore_vlan(struct e1000_adapter *adapter);
193
1da177e4 194#ifdef CONFIG_PM
977e74b5 195static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 196static int e1000_resume(struct pci_dev *pdev);
197#endif
198
199#ifdef CONFIG_NET_POLL_CONTROLLER
200/* for netdump / net console */
201static void e1000_netpoll (struct net_device *netdev);
202#endif
203
24025e4e
MC		 204#ifdef CONFIG_E1000_MQ
205/* for multiple Rx queues */
206void e1000_rx_schedule(void *data);
207#endif
208
1da177e4
LT		 209/* Exported from other modules */
210
211extern void e1000_check_options(struct e1000_adapter *adapter);
212
213static struct pci_driver e1000_driver = {
214 .name = e1000_driver_name,
215 .id_table = e1000_pci_tbl,
216 .probe = e1000_probe,
217 .remove = __devexit_p(e1000_remove),
218 /* Power Managment Hooks */
219#ifdef CONFIG_PM
220 .suspend = e1000_suspend,
221 .resume = e1000_resume
222#endif
223};
224
225MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
226MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
227MODULE_LICENSE("GPL");
228MODULE_VERSION(DRV_VERSION);
229
230static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
231module_param(debug, int, 0);
232MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
233
234/**
235 * e1000_init_module - Driver Registration Routine
236 *
237 * e1000_init_module is the first routine called when the driver is
238 * loaded. All it does is register with the PCI subsystem.
239 **/
240
241static int __init
242e1000_init_module(void)
243{
244 int ret;
245 printk(KERN_INFO "%s - version %s\n",
246 e1000_driver_string, e1000_driver_version);
247
248 printk(KERN_INFO "%s\n", e1000_copyright);
249
250 ret = pci_module_init(&e1000_driver);
8b378def 251
1da177e4
LT		 252 return ret;
253}
254
255module_init(e1000_init_module);
256
257/**
258 * e1000_exit_module - Driver Exit Cleanup Routine
259 *
260 * e1000_exit_module is called just before the driver is removed
261 * from memory.
262 **/
263
264static void __exit
265e1000_exit_module(void)
266{
1da177e4
LT		 267 pci_unregister_driver(&e1000_driver);
268}
269
270module_exit(e1000_exit_module);
271
272/**
273 * e1000_irq_disable - Mask off interrupt generation on the NIC
274 * @adapter: board private structure
275 **/
276
277static inline void
278e1000_irq_disable(struct e1000_adapter *adapter)
279{
280 atomic_inc(&adapter->irq_sem);
281 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
282 E1000_WRITE_FLUSH(&adapter->hw);
283 synchronize_irq(adapter->pdev->irq);
284}
285
286/**
287 * e1000_irq_enable - Enable default interrupt generation settings
288 * @adapter: board private structure
289 **/
290
291static inline void
292e1000_irq_enable(struct e1000_adapter *adapter)
293{
294 if(likely(atomic_dec_and_test(&adapter->irq_sem))) {
295 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
296 E1000_WRITE_FLUSH(&adapter->hw);
297 }
298}
3ad2cc67
AB		 299
300static void
2d7edb92
MC		 301e1000_update_mng_vlan(struct e1000_adapter *adapter)
302{
303 struct net_device *netdev = adapter->netdev;
304 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
305 uint16_t old_vid = adapter->mng_vlan_id;
306 if(adapter->vlgrp) {
307 if(!adapter->vlgrp->vlan_devices[vid]) {
308 if(adapter->hw.mng_cookie.status &
309 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
310 e1000_vlan_rx_add_vid(netdev, vid);
311 adapter->mng_vlan_id = vid;
312 } else
313 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
314
315 if((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
316 (vid != old_vid) &&
317 !adapter->vlgrp->vlan_devices[old_vid])
318 e1000_vlan_rx_kill_vid(netdev, old_vid);
319 }
320 }
321}
b55ccb35
JK		 322
323/**
324 * e1000_release_hw_control - release control of the h/w to f/w
325 * @adapter: address of board private structure
326 *
327 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
328 * For ASF and Pass Through versions of f/w this means that the
329 * driver is no longer loaded. For AMT version (only with 82573) i
330 * of the f/w this means that the netowrk i/f is closed.
331 *
332 **/
333
334static inline void
335e1000_release_hw_control(struct e1000_adapter *adapter)
336{
337 uint32_t ctrl_ext;
338 uint32_t swsm;
339
340 /* Let firmware taken over control of h/w */
341 switch (adapter->hw.mac_type) {
342 case e1000_82571:
343 case e1000_82572:
344 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
345 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
346 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
347 break;
348 case e1000_82573:
349 swsm = E1000_READ_REG(&adapter->hw, SWSM);
350 E1000_WRITE_REG(&adapter->hw, SWSM,
351 swsm & ~E1000_SWSM_DRV_LOAD);
352 default:
353 break;
354 }
355}
356
357/**
358 * e1000_get_hw_control - get control of the h/w from f/w
359 * @adapter: address of board private structure
360 *
361 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
362 * For ASF and Pass Through versions of f/w this means that
363 * the driver is loaded. For AMT version (only with 82573)
364 * of the f/w this means that the netowrk i/f is open.
365 *
366 **/
367
368static inline void
369e1000_get_hw_control(struct e1000_adapter *adapter)
370{
371 uint32_t ctrl_ext;
372 uint32_t swsm;
373 /* Let firmware know the driver has taken over */
374 switch (adapter->hw.mac_type) {
375 case e1000_82571:
376 case e1000_82572:
377 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
378 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
379 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
380 break;
381 case e1000_82573:
382 swsm = E1000_READ_REG(&adapter->hw, SWSM);
383 E1000_WRITE_REG(&adapter->hw, SWSM,
384 swsm | E1000_SWSM_DRV_LOAD);
385 break;
386 default:
387 break;
388 }
389}
390
1da177e4
LT		 391int
392e1000_up(struct e1000_adapter *adapter)
393{
394 struct net_device *netdev = adapter->netdev;
581d708e 395 int i, err;
1da177e4
LT		 396
397 /* hardware has been reset, we need to reload some things */
398
399 /* Reset the PHY if it was previously powered down */
400 if(adapter->hw.media_type == e1000_media_type_copper) {
401 uint16_t mii_reg;
402 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
403 if(mii_reg & MII_CR_POWER_DOWN)
404 e1000_phy_reset(&adapter->hw);
405 }
406
407 e1000_set_multi(netdev);
408
409 e1000_restore_vlan(adapter);
410
411 e1000_configure_tx(adapter);
412 e1000_setup_rctl(adapter);
413 e1000_configure_rx(adapter);
f56799ea 414 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e 415 adapter->alloc_rx_buf(adapter, &adapter->rx_ring[i]);
f56799ea 416 }
1da177e4 417
fa4f7ef3
MC		 418#ifdef CONFIG_PCI_MSI
419 if(adapter->hw.mac_type > e1000_82547_rev_2) {
420 adapter->have_msi = TRUE;
421 if((err = pci_enable_msi(adapter->pdev))) {
422 DPRINTK(PROBE, ERR,
423 "Unable to allocate MSI interrupt Error: %d\n", err);
424 adapter->have_msi = FALSE;
425 }
426 }
427#endif
1da177e4
LT		 428 if((err = request_irq(adapter->pdev->irq, &e1000_intr,
429 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 430 netdev->name, netdev))) {
431 DPRINTK(PROBE, ERR,
432 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 433 return err;
2648345f 434 }
1da177e4 435
7bfa4816
JK		 436#ifdef CONFIG_E1000_MQ
437 e1000_setup_queue_mapping(adapter);
438#endif
439
440 adapter->tx_queue_len = netdev->tx_queue_len;
441
1da177e4 442 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 443
444#ifdef CONFIG_E1000_NAPI
445 netif_poll_enable(netdev);
446#endif
5de55624
MC		 447 e1000_irq_enable(adapter);
448
1da177e4
LT		 449 return 0;
450}
451
452void
453e1000_down(struct e1000_adapter *adapter)
454{
455 struct net_device *netdev = adapter->netdev;
57128197
JK		 456 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
457 e1000_check_mng_mode(&adapter->hw);
1da177e4
LT		 458
459 e1000_irq_disable(adapter);
24025e4e
MC		 460#ifdef CONFIG_E1000_MQ
461 while (atomic_read(&adapter->rx_sched_call_data.count) != 0);
462#endif
1da177e4 463 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3
MC		 464#ifdef CONFIG_PCI_MSI
465 if(adapter->hw.mac_type > e1000_82547_rev_2 &&
466 adapter->have_msi == TRUE)
467 pci_disable_msi(adapter->pdev);
468#endif
1da177e4
LT		 469 del_timer_sync(&adapter->tx_fifo_stall_timer);
470 del_timer_sync(&adapter->watchdog_timer);
471 del_timer_sync(&adapter->phy_info_timer);
472
473#ifdef CONFIG_E1000_NAPI
474 netif_poll_disable(netdev);
475#endif
7bfa4816 476 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 477 adapter->link_speed = 0;
478 adapter->link_duplex = 0;
479 netif_carrier_off(netdev);
480 netif_stop_queue(netdev);
481
482 e1000_reset(adapter);
581d708e
MC		 483 e1000_clean_all_tx_rings(adapter);
484 e1000_clean_all_rx_rings(adapter);
1da177e4 485
57128197
JK		 486 /* Power down the PHY so no link is implied when interface is down *
487 * The PHY cannot be powered down if any of the following is TRUE *
488 * (a) WoL is enabled
489 * (b) AMT is active
490 * (c) SoL/IDER session is active */
491 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
2d7edb92 492 adapter->hw.media_type == e1000_media_type_copper &&
57128197
JK		 493 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
494 !mng_mode_enabled &&
495 !e1000_check_phy_reset_block(&adapter->hw)) {
1da177e4
LT		 496 uint16_t mii_reg;
497 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
498 mii_reg |= MII_CR_POWER_DOWN;
499 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 500 mdelay(1);
1da177e4
LT		 501 }
502}
503
504void
505e1000_reset(struct e1000_adapter *adapter)
506{
2d7edb92 507 uint32_t pba, manc;
1125ecbc 508 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 509
510 /* Repartition Pba for greater than 9k mtu
511 * To take effect CTRL.RST is required.
512 */
513
2d7edb92
MC		 514 switch (adapter->hw.mac_type) {
515 case e1000_82547:
0e6ef3e0 516 case e1000_82547_rev_2:
2d7edb92
MC		 517 pba = E1000_PBA_30K;
518 break;
868d5309
MC		 519 case e1000_82571:
520 case e1000_82572:
521 pba = E1000_PBA_38K;
522 break;
2d7edb92
MC		 523 case e1000_82573:
524 pba = E1000_PBA_12K;
525 break;
526 default:
527 pba = E1000_PBA_48K;
528 break;
529 }
530
1125ecbc 531 if((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 532 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 533 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 534
535
536 if(adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 537 adapter->tx_fifo_head = 0;
538 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
539 adapter->tx_fifo_size =
540 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
541 atomic_set(&adapter->tx_fifo_stall, 0);
542 }
2d7edb92 543
1da177e4
LT		 544 E1000_WRITE_REG(&adapter->hw, PBA, pba);
545
546 /* flow control settings */
f11b7f85
JK		 547 /* Set the FC high water mark to 90% of the FIFO size.
548 * Required to clear last 3 LSB */
549 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
550
551 adapter->hw.fc_high_water = fc_high_water_mark;
552 adapter->hw.fc_low_water = fc_high_water_mark - 8;
1da177e4
LT		 553 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
554 adapter->hw.fc_send_xon = 1;
555 adapter->hw.fc = adapter->hw.original_fc;
556
2d7edb92 557 /* Allow time for pending master requests to run */
1da177e4
LT		 558 e1000_reset_hw(&adapter->hw);
559 if(adapter->hw.mac_type >= e1000_82544)
560 E1000_WRITE_REG(&adapter->hw, WUC, 0);
561 if(e1000_init_hw(&adapter->hw))
562 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 563 e1000_update_mng_vlan(adapter);
1da177e4
LT		 564 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
565 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
566
567 e1000_reset_adaptive(&adapter->hw);
568 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 569 if (adapter->en_mng_pt) {
570 manc = E1000_READ_REG(&adapter->hw, MANC);
571 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
572 E1000_WRITE_REG(&adapter->hw, MANC, manc);
573 }
1da177e4
LT		 574}
575
576/**
577 * e1000_probe - Device Initialization Routine
578 * @pdev: PCI device information struct
579 * @ent: entry in e1000_pci_tbl
580 *
581 * Returns 0 on success, negative on failure
582 *
583 * e1000_probe initializes an adapter identified by a pci_dev structure.
584 * The OS initialization, configuring of the adapter private structure,
585 * and a hardware reset occur.
586 **/
587
588static int __devinit
589e1000_probe(struct pci_dev *pdev,
590 const struct pci_device_id *ent)
591{
592 struct net_device *netdev;
593 struct e1000_adapter *adapter;
2d7edb92 594 unsigned long mmio_start, mmio_len;
2d7edb92 595
1da177e4 596 static int cards_found = 0;
2d7edb92 597 int i, err, pci_using_dac;
1da177e4
LT		 598 uint16_t eeprom_data;
599 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
1da177e4
LT		 600 if((err = pci_enable_device(pdev)))
601 return err;
602
603 if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
604 pci_using_dac = 1;
605 } else {
606 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
607 E1000_ERR("No usable DMA configuration, aborting\n");
608 return err;
609 }
610 pci_using_dac = 0;
611 }
612
613 if((err = pci_request_regions(pdev, e1000_driver_name)))
614 return err;
615
616 pci_set_master(pdev);
617
618 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
619 if(!netdev) {
620 err = -ENOMEM;
621 goto err_alloc_etherdev;
622 }
623
624 SET_MODULE_OWNER(netdev);
625 SET_NETDEV_DEV(netdev, &pdev->dev);
626
627 pci_set_drvdata(pdev, netdev);
60490fe0 628 adapter = netdev_priv(netdev);
1da177e4
LT		 629 adapter->netdev = netdev;
630 adapter->pdev = pdev;
631 adapter->hw.back = adapter;
632 adapter->msg_enable = (1 << debug) - 1;
633
634 mmio_start = pci_resource_start(pdev, BAR_0);
635 mmio_len = pci_resource_len(pdev, BAR_0);
636
637 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
638 if(!adapter->hw.hw_addr) {
639 err = -EIO;
640 goto err_ioremap;
641 }
642
643 for(i = BAR_1; i <= BAR_5; i++) {
644 if(pci_resource_len(pdev, i) == 0)
645 continue;
646 if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
647 adapter->hw.io_base = pci_resource_start(pdev, i);
648 break;
649 }
650 }
651
652 netdev->open = &e1000_open;
653 netdev->stop = &e1000_close;
654 netdev->hard_start_xmit = &e1000_xmit_frame;
655 netdev->get_stats = &e1000_get_stats;
656 netdev->set_multicast_list = &e1000_set_multi;
657 netdev->set_mac_address = &e1000_set_mac;
658 netdev->change_mtu = &e1000_change_mtu;
659 netdev->do_ioctl = &e1000_ioctl;
660 e1000_set_ethtool_ops(netdev);
661 netdev->tx_timeout = &e1000_tx_timeout;
662 netdev->watchdog_timeo = 5 * HZ;
663#ifdef CONFIG_E1000_NAPI
664 netdev->poll = &e1000_clean;
665 netdev->weight = 64;
666#endif
667 netdev->vlan_rx_register = e1000_vlan_rx_register;
668 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
669 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
670#ifdef CONFIG_NET_POLL_CONTROLLER
671 netdev->poll_controller = e1000_netpoll;
672#endif
673 strcpy(netdev->name, pci_name(pdev));
674
675 netdev->mem_start = mmio_start;
676 netdev->mem_end = mmio_start + mmio_len;
677 netdev->base_addr = adapter->hw.io_base;
678
679 adapter->bd_number = cards_found;
680
681 /* setup the private structure */
682
683 if((err = e1000_sw_init(adapter)))
684 goto err_sw_init;
685
2d7edb92
MC		 686 if((err = e1000_check_phy_reset_block(&adapter->hw)))
687 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
688
1da177e4
LT		 689 if(adapter->hw.mac_type >= e1000_82543) {
690 netdev->features = NETIF_F_SG |
691 NETIF_F_HW_CSUM |
692 NETIF_F_HW_VLAN_TX |
693 NETIF_F_HW_VLAN_RX |
694 NETIF_F_HW_VLAN_FILTER;
695 }
696
697#ifdef NETIF_F_TSO
698 if((adapter->hw.mac_type >= e1000_82544) &&
699 (adapter->hw.mac_type != e1000_82547))
700 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 701
702#ifdef NETIF_F_TSO_IPV6
703 if(adapter->hw.mac_type > e1000_82547_rev_2)
704 netdev->features |= NETIF_F_TSO_IPV6;
705#endif
1da177e4
LT		 706#endif
707 if(pci_using_dac)
708 netdev->features |= NETIF_F_HIGHDMA;
709
710 /* hard_start_xmit is safe against parallel locking */
711 netdev->features |= NETIF_F_LLTX;
712
2d7edb92
MC		 713 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
714
1da177e4
LT		 715 /* before reading the EEPROM, reset the controller to
716 * put the device in a known good starting state */
717
718 e1000_reset_hw(&adapter->hw);
719
720 /* make sure the EEPROM is good */
721
722 if(e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
723 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
724 err = -EIO;
725 goto err_eeprom;
726 }
727
728 /* copy the MAC address out of the EEPROM */
729
2648345f 730 if(e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 731 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
732 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 733 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 734
9beb0ac1 735 if(!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 736 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
737 err = -EIO;
738 goto err_eeprom;
739 }
740
741 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
742
743 e1000_get_bus_info(&adapter->hw);
744
745 init_timer(&adapter->tx_fifo_stall_timer);
746 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
747 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
748
749 init_timer(&adapter->watchdog_timer);
750 adapter->watchdog_timer.function = &e1000_watchdog;
751 adapter->watchdog_timer.data = (unsigned long) adapter;
752
753 INIT_WORK(&adapter->watchdog_task,
754 (void (*)(void *))e1000_watchdog_task, adapter);
755
756 init_timer(&adapter->phy_info_timer);
757 adapter->phy_info_timer.function = &e1000_update_phy_info;
758 adapter->phy_info_timer.data = (unsigned long) adapter;
759
760 INIT_WORK(&adapter->tx_timeout_task,
761 (void (*)(void *))e1000_tx_timeout_task, netdev);
762
763 /* we're going to reset, so assume we have no link for now */
764
765 netif_carrier_off(netdev);
766 netif_stop_queue(netdev);
767
768 e1000_check_options(adapter);
769
770 /* Initial Wake on LAN setting
771 * If APM wake is enabled in the EEPROM,
772 * enable the ACPI Magic Packet filter
773 */
774
775 switch(adapter->hw.mac_type) {
776 case e1000_82542_rev2_0:
777 case e1000_82542_rev2_1:
778 case e1000_82543:
779 break;
780 case e1000_82544:
781 e1000_read_eeprom(&adapter->hw,
782 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
783 eeprom_apme_mask = E1000_EEPROM_82544_APM;
784 break;
785 case e1000_82546:
786 case e1000_82546_rev_3:
fd803241 787 case e1000_82571:
1da177e4
LT		 788 if((E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
789 && (adapter->hw.media_type == e1000_media_type_copper)) {
790 e1000_read_eeprom(&adapter->hw,
791 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
792 break;
793 }
794 /* Fall Through */
795 default:
796 e1000_read_eeprom(&adapter->hw,
797 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
798 break;
799 }
800 if(eeprom_data & eeprom_apme_mask)
801 adapter->wol |= E1000_WUFC_MAG;
802
803 /* reset the hardware with the new settings */
804 e1000_reset(adapter);
805
b55ccb35
JK		 806 /* If the controller is 82573 and f/w is AMT, do not set
807 * DRV_LOAD until the interface is up. For all other cases,
808 * let the f/w know that the h/w is now under the control
809 * of the driver. */
810 if (adapter->hw.mac_type != e1000_82573 ||
811 !e1000_check_mng_mode(&adapter->hw))
812 e1000_get_hw_control(adapter);
2d7edb92 813
1da177e4
LT		 814 strcpy(netdev->name, "eth%d");
815 if((err = register_netdev(netdev)))
816 goto err_register;
817
818 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
819
820 cards_found++;
821 return 0;
822
823err_register:
824err_sw_init:
825err_eeprom:
826 iounmap(adapter->hw.hw_addr);
827err_ioremap:
828 free_netdev(netdev);
829err_alloc_etherdev:
830 pci_release_regions(pdev);
831 return err;
832}
833
834/**
835 * e1000_remove - Device Removal Routine
836 * @pdev: PCI device information struct
837 *
838 * e1000_remove is called by the PCI subsystem to alert the driver
839 * that it should release a PCI device. The could be caused by a
840 * Hot-Plug event, or because the driver is going to be removed from
841 * memory.
842 **/
843
844static void __devexit
845e1000_remove(struct pci_dev *pdev)
846{
847 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 848 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 849 uint32_t manc;
581d708e
MC		 850#ifdef CONFIG_E1000_NAPI
851 int i;
852#endif
1da177e4 853
be2b28ed
JG		 854 flush_scheduled_work();
855
1da177e4
LT		 856 if(adapter->hw.mac_type >= e1000_82540 &&
857 adapter->hw.media_type == e1000_media_type_copper) {
858 manc = E1000_READ_REG(&adapter->hw, MANC);
859 if(manc & E1000_MANC_SMBUS_EN) {
860 manc |= E1000_MANC_ARP_EN;
861 E1000_WRITE_REG(&adapter->hw, MANC, manc);
862 }
863 }
864
b55ccb35
JK		 865 /* Release control of h/w to f/w. If f/w is AMT enabled, this
866 * would have already happened in close and is redundant. */
867 e1000_release_hw_control(adapter);
2d7edb92 868
1da177e4 869 unregister_netdev(netdev);
581d708e 870#ifdef CONFIG_E1000_NAPI
f56799ea 871 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 872 __dev_put(&adapter->polling_netdev[i]);
873#endif
1da177e4 874
2d7edb92
MC		 875 if(!e1000_check_phy_reset_block(&adapter->hw))
876 e1000_phy_hw_reset(&adapter->hw);
1da177e4 877
24025e4e
MC		 878 kfree(adapter->tx_ring);
879 kfree(adapter->rx_ring);
880#ifdef CONFIG_E1000_NAPI
881 kfree(adapter->polling_netdev);
882#endif
883
1da177e4
LT		 884 iounmap(adapter->hw.hw_addr);
885 pci_release_regions(pdev);
886
24025e4e
MC		 887#ifdef CONFIG_E1000_MQ
888 free_percpu(adapter->cpu_netdev);
889 free_percpu(adapter->cpu_tx_ring);
890#endif
1da177e4
LT		 891 free_netdev(netdev);
892
893 pci_disable_device(pdev);
894}
895
896/**
897 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
898 * @adapter: board private structure to initialize
899 *
900 * e1000_sw_init initializes the Adapter private data structure.
901 * Fields are initialized based on PCI device information and
902 * OS network device settings (MTU size).
903 **/
904
905static int __devinit
906e1000_sw_init(struct e1000_adapter *adapter)
907{
908 struct e1000_hw *hw = &adapter->hw;
909 struct net_device *netdev = adapter->netdev;
910 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 911#ifdef CONFIG_E1000_NAPI
912 int i;
913#endif
1da177e4
LT		 914
915 /* PCI config space info */
916
917 hw->vendor_id = pdev->vendor;
918 hw->device_id = pdev->device;
919 hw->subsystem_vendor_id = pdev->subsystem_vendor;
920 hw->subsystem_id = pdev->subsystem_device;
921
922 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
923
924 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
925
926 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2d7edb92 927 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
1da177e4
LT		 928 hw->max_frame_size = netdev->mtu +
929 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
930 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
931
932 /* identify the MAC */
933
934 if(e1000_set_mac_type(hw)) {
935 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
936 return -EIO;
937 }
938
939 /* initialize eeprom parameters */
940
2d7edb92
MC		 941 if(e1000_init_eeprom_params(hw)) {
942 E1000_ERR("EEPROM initialization failed\n");
943 return -EIO;
944 }
1da177e4
LT		 945
946 switch(hw->mac_type) {
947 default:
948 break;
949 case e1000_82541:
950 case e1000_82547:
951 case e1000_82541_rev_2:
952 case e1000_82547_rev_2:
953 hw->phy_init_script = 1;
954 break;
955 }
956
957 e1000_set_media_type(hw);
958
959 hw->wait_autoneg_complete = FALSE;
960 hw->tbi_compatibility_en = TRUE;
961 hw->adaptive_ifs = TRUE;
962
963 /* Copper options */
964
965 if(hw->media_type == e1000_media_type_copper) {
966 hw->mdix = AUTO_ALL_MODES;
967 hw->disable_polarity_correction = FALSE;
968 hw->master_slave = E1000_MASTER_SLAVE;
969 }
970
24025e4e
MC		 971#ifdef CONFIG_E1000_MQ
972 /* Number of supported queues */
973 switch (hw->mac_type) {
974 case e1000_82571:
975 case e1000_82572:
f56799ea
JK		 976 /* These controllers support 2 tx queues, but with a single
977 * qdisc implementation, multiple tx queues aren't quite as
978 * interesting. If we can find a logical way of mapping
979 * flows to a queue, then perhaps we can up the num_tx_queue
980 * count back to its default. Until then, we run the risk of
981 * terrible performance due to SACK overload. */
982 adapter->num_tx_queues = 1;
983 adapter->num_rx_queues = 2;
24025e4e
MC		 984 break;
985 default:
f56799ea
JK		 986 adapter->num_tx_queues = 1;
987 adapter->num_rx_queues = 1;
24025e4e
MC		 988 break;
989 }
f56799ea
JK		 990 adapter->num_rx_queues = min(adapter->num_rx_queues, num_online_cpus());
991 adapter->num_tx_queues = min(adapter->num_tx_queues, num_online_cpus());
7bfa4816
JK		 992 DPRINTK(DRV, INFO, "Multiqueue Enabled: Rx Queue count = %u %s\n",
993 adapter->num_rx_queues,
994 ((adapter->num_rx_queues == 1)
995 ? ((num_online_cpus() > 1)
996 ? "(due to unsupported feature in current adapter)"
997 : "(due to unsupported system configuration)")
998 : ""));
999 DPRINTK(DRV, INFO, "Multiqueue Enabled: Tx Queue count = %u\n",
1000 adapter->num_tx_queues);
24025e4e 1001#else
f56799ea
JK		 1002 adapter->num_tx_queues = 1;
1003 adapter->num_rx_queues = 1;
24025e4e 1004#endif
581d708e
MC		 1005
1006 if (e1000_alloc_queues(adapter)) {
1007 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1008 return -ENOMEM;
1009 }
1010
1011#ifdef CONFIG_E1000_NAPI
f56799ea 1012 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1013 adapter->polling_netdev[i].priv = adapter;
1014 adapter->polling_netdev[i].poll = &e1000_clean;
1015 adapter->polling_netdev[i].weight = 64;
1016 dev_hold(&adapter->polling_netdev[i]);
1017 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1018 }
7bfa4816 1019 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1020#endif
1021
1da177e4
LT		 1022 atomic_set(&adapter->irq_sem, 1);
1023 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1024
1025 return 0;
1026}
1027
581d708e
MC		 1028/**
1029 * e1000_alloc_queues - Allocate memory for all rings
1030 * @adapter: board private structure to initialize
1031 *
1032 * We allocate one ring per queue at run-time since we don't know the
1033 * number of queues at compile-time. The polling_netdev array is
1034 * intended for Multiqueue, but should work fine with a single queue.
1035 **/
1036
1037static int __devinit
1038e1000_alloc_queues(struct e1000_adapter *adapter)
1039{
1040 int size;
1041
f56799ea 1042 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1043 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1044 if (!adapter->tx_ring)
1045 return -ENOMEM;
1046 memset(adapter->tx_ring, 0, size);
1047
f56799ea 1048 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1049 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1050 if (!adapter->rx_ring) {
1051 kfree(adapter->tx_ring);
1052 return -ENOMEM;
1053 }
1054 memset(adapter->rx_ring, 0, size);
1055
1056#ifdef CONFIG_E1000_NAPI
f56799ea 1057 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1058 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1059 if (!adapter->polling_netdev) {
1060 kfree(adapter->tx_ring);
1061 kfree(adapter->rx_ring);
1062 return -ENOMEM;
1063 }
1064 memset(adapter->polling_netdev, 0, size);
1065#endif
1066
7bfa4816
JK		 1067#ifdef CONFIG_E1000_MQ
1068 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1069 adapter->rx_sched_call_data.info = adapter->netdev;
1070
1071 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1072 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1073#endif
1074
581d708e
MC		 1075 return E1000_SUCCESS;
1076}
1077
24025e4e
MC		 1078#ifdef CONFIG_E1000_MQ
1079static void __devinit
1080e1000_setup_queue_mapping(struct e1000_adapter *adapter)
1081{
1082 int i, cpu;
1083
1084 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1085 adapter->rx_sched_call_data.info = adapter->netdev;
1086 cpus_clear(adapter->rx_sched_call_data.cpumask);
1087
1088 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1089 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1090
1091 lock_cpu_hotplug();
1092 i = 0;
1093 for_each_online_cpu(cpu) {
f56799ea 1094 *per_cpu_ptr(adapter->cpu_tx_ring, cpu) = &adapter->tx_ring[i % adapter->num_tx_queues];
24025e4e
MC		 1095 /* This is incomplete because we'd like to assign separate
1096 * physical cpus to these netdev polling structures and
1097 * avoid saturating a subset of cpus.
1098 */
f56799ea 1099 if (i < adapter->num_rx_queues) {
24025e4e 1100 *per_cpu_ptr(adapter->cpu_netdev, cpu) = &adapter->polling_netdev[i];
7bfa4816
JK		 1101 adapter->rx_ring[i].cpu = cpu;
1102 cpu_set(cpu, adapter->cpumask);
24025e4e
MC		 1103 } else
1104 *per_cpu_ptr(adapter->cpu_netdev, cpu) = NULL;
1105
1106 i++;
1107 }
1108 unlock_cpu_hotplug();
1109}
1110#endif
1111
1da177e4
LT		 1112/**
1113 * e1000_open - Called when a network interface is made active
1114 * @netdev: network interface device structure
1115 *
1116 * Returns 0 on success, negative value on failure
1117 *
1118 * The open entry point is called when a network interface is made
1119 * active by the system (IFF_UP). At this point all resources needed
1120 * for transmit and receive operations are allocated, the interrupt
1121 * handler is registered with the OS, the watchdog timer is started,
1122 * and the stack is notified that the interface is ready.
1123 **/
1124
1125static int
1126e1000_open(struct net_device *netdev)
1127{
60490fe0 1128 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1129 int err;
1130
1131 /* allocate transmit descriptors */
1132
581d708e 1133 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1134 goto err_setup_tx;
1135
1136 /* allocate receive descriptors */
1137
581d708e 1138 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1139 goto err_setup_rx;
1140
1141 if((err = e1000_up(adapter)))
1142 goto err_up;
2d7edb92
MC		 1143 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
1144 if((adapter->hw.mng_cookie.status &
1145 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1146 e1000_update_mng_vlan(adapter);
1147 }
1da177e4 1148
b55ccb35
JK		 1149 /* If AMT is enabled, let the firmware know that the network
1150 * interface is now open */
1151 if (adapter->hw.mac_type == e1000_82573 &&
1152 e1000_check_mng_mode(&adapter->hw))
1153 e1000_get_hw_control(adapter);
1154
1da177e4
LT		 1155 return E1000_SUCCESS;
1156
1157err_up:
581d708e 1158 e1000_free_all_rx_resources(adapter);
1da177e4 1159err_setup_rx:
581d708e 1160 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1161err_setup_tx:
1162 e1000_reset(adapter);
1163
1164 return err;
1165}
1166
1167/**
1168 * e1000_close - Disables a network interface
1169 * @netdev: network interface device structure
1170 *
1171 * Returns 0, this is not allowed to fail
1172 *
1173 * The close entry point is called when an interface is de-activated
1174 * by the OS. The hardware is still under the drivers control, but
1175 * needs to be disabled. A global MAC reset is issued to stop the
1176 * hardware, and all transmit and receive resources are freed.
1177 **/
1178
1179static int
1180e1000_close(struct net_device *netdev)
1181{
60490fe0 1182 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1183
1184 e1000_down(adapter);
1185
581d708e
MC		 1186 e1000_free_all_tx_resources(adapter);
1187 e1000_free_all_rx_resources(adapter);
1da177e4 1188
2d7edb92
MC		 1189 if((adapter->hw.mng_cookie.status &
1190 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1191 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1192 }
b55ccb35
JK		 1193
1194 /* If AMT is enabled, let the firmware know that the network
1195 * interface is now closed */
1196 if (adapter->hw.mac_type == e1000_82573 &&
1197 e1000_check_mng_mode(&adapter->hw))
1198 e1000_release_hw_control(adapter);
1199
1da177e4
LT		 1200 return 0;
1201}
1202
1203/**
1204 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1205 * @adapter: address of board private structure
2d7edb92
MC		 1206 * @start: address of beginning of memory
1207 * @len: length of memory
1da177e4
LT		 1208 **/
1209static inline boolean_t
1210e1000_check_64k_bound(struct e1000_adapter *adapter,
1211 void *start, unsigned long len)
1212{
1213 unsigned long begin = (unsigned long) start;
1214 unsigned long end = begin + len;
1215
2648345f
MC		 1216 /* First rev 82545 and 82546 need to not allow any memory
1217 * write location to cross 64k boundary due to errata 23 */
1da177e4 1218 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1219 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1220 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1221 }
1222
1223 return TRUE;
1224}
1225
1226/**
1227 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1228 * @adapter: board private structure
581d708e 1229 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1230 *
1231 * Return 0 on success, negative on failure
1232 **/
1233
3ad2cc67 1234static int
581d708e
MC		 1235e1000_setup_tx_resources(struct e1000_adapter *adapter,
1236 struct e1000_tx_ring *txdr)
1da177e4 1237{
1da177e4
LT		 1238 struct pci_dev *pdev = adapter->pdev;
1239 int size;
1240
1241 size = sizeof(struct e1000_buffer) * txdr->count;
a7ec15da
RT		 1242
1243 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
1da177e4 1244 if(!txdr->buffer_info) {
2648345f
MC		 1245 DPRINTK(PROBE, ERR,
1246 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1247 return -ENOMEM;
1248 }
1249 memset(txdr->buffer_info, 0, size);
1250
1251 /* round up to nearest 4K */
1252
1253 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1254 E1000_ROUNDUP(txdr->size, 4096);
1255
1256 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1257 if(!txdr->desc) {
1258setup_tx_desc_die:
1da177e4 1259 vfree(txdr->buffer_info);
2648345f
MC		 1260 DPRINTK(PROBE, ERR,
1261 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1262 return -ENOMEM;
1263 }
1264
2648345f 1265 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1266 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1267 void *olddesc = txdr->desc;
1268 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1269 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1270 "at %p\n", txdr->size, txdr->desc);
1271 /* Try again, without freeing the previous */
1da177e4 1272 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1da177e4 1273 if(!txdr->desc) {
2648345f 1274 /* Failed allocation, critical failure */
1da177e4
LT		 1275 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1276 goto setup_tx_desc_die;
1277 }
1278
1279 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1280 /* give up */
2648345f
MC		 1281 pci_free_consistent(pdev, txdr->size, txdr->desc,
1282 txdr->dma);
1da177e4
LT		 1283 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1284 DPRINTK(PROBE, ERR,
2648345f
MC		 1285 "Unable to allocate aligned memory "
1286 "for the transmit descriptor ring\n");
1da177e4
LT		 1287 vfree(txdr->buffer_info);
1288 return -ENOMEM;
1289 } else {
2648345f 1290 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1291 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1292 }
1293 }
1294 memset(txdr->desc, 0, txdr->size);
1295
1296 txdr->next_to_use = 0;
1297 txdr->next_to_clean = 0;
2ae76d98 1298 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1299
1300 return 0;
1301}
1302
581d708e
MC		 1303/**
1304 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1305 * (Descriptors) for all queues
1306 * @adapter: board private structure
1307 *
1308 * If this function returns with an error, then it's possible one or
1309 * more of the rings is populated (while the rest are not). It is the
1310 * callers duty to clean those orphaned rings.
1311 *
1312 * Return 0 on success, negative on failure
1313 **/
1314
1315int
1316e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1317{
1318 int i, err = 0;
1319
f56799ea 1320 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1321 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1322 if (err) {
1323 DPRINTK(PROBE, ERR,
1324 "Allocation for Tx Queue %u failed\n", i);
1325 break;
1326 }
1327 }
1328
1329 return err;
1330}
1331
1da177e4
LT		 1332/**
1333 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1334 * @adapter: board private structure
1335 *
1336 * Configure the Tx unit of the MAC after a reset.
1337 **/
1338
1339static void
1340e1000_configure_tx(struct e1000_adapter *adapter)
1341{
581d708e
MC		 1342 uint64_t tdba;
1343 struct e1000_hw *hw = &adapter->hw;
1344 uint32_t tdlen, tctl, tipg, tarc;
1da177e4
LT		 1345
1346 /* Setup the HW Tx Head and Tail descriptor pointers */
1347
f56799ea 1348 switch (adapter->num_tx_queues) {
24025e4e
MC		 1349 case 2:
1350 tdba = adapter->tx_ring[1].dma;
1351 tdlen = adapter->tx_ring[1].count *
1352 sizeof(struct e1000_tx_desc);
1353 E1000_WRITE_REG(hw, TDBAL1, (tdba & 0x00000000ffffffffULL));
1354 E1000_WRITE_REG(hw, TDBAH1, (tdba >> 32));
1355 E1000_WRITE_REG(hw, TDLEN1, tdlen);
1356 E1000_WRITE_REG(hw, TDH1, 0);
1357 E1000_WRITE_REG(hw, TDT1, 0);
1358 adapter->tx_ring[1].tdh = E1000_TDH1;
1359 adapter->tx_ring[1].tdt = E1000_TDT1;
1360 /* Fall Through */
1361 case 1:
1362 default:
581d708e
MC		 1363 tdba = adapter->tx_ring[0].dma;
1364 tdlen = adapter->tx_ring[0].count *
1365 sizeof(struct e1000_tx_desc);
1366 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1367 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1368 E1000_WRITE_REG(hw, TDLEN, tdlen);
1369 E1000_WRITE_REG(hw, TDH, 0);
1370 E1000_WRITE_REG(hw, TDT, 0);
1371 adapter->tx_ring[0].tdh = E1000_TDH;
1372 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1373 break;
1374 }
1da177e4
LT		 1375
1376 /* Set the default values for the Tx Inter Packet Gap timer */
1377
581d708e 1378 switch (hw->mac_type) {
1da177e4
LT		 1379 case e1000_82542_rev2_0:
1380 case e1000_82542_rev2_1:
1381 tipg = DEFAULT_82542_TIPG_IPGT;
1382 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
1383 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
1384 break;
1385 default:
581d708e
MC		 1386 if (hw->media_type == e1000_media_type_fiber ||
1387 hw->media_type == e1000_media_type_internal_serdes)
1da177e4
LT		 1388 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1389 else
1390 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1391 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
1392 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
1393 }
581d708e 1394 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1395
1396 /* Set the Tx Interrupt Delay register */
1397
581d708e
MC		 1398 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1399 if (hw->mac_type >= e1000_82540)
1400 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1401
1402 /* Program the Transmit Control Register */
1403
581d708e 1404 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1405
1406 tctl &= ~E1000_TCTL_CT;
24025e4e 1407 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1408 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1409
581d708e 1410 E1000_WRITE_REG(hw, TCTL, tctl);
1da177e4 1411
2ae76d98
MC		 1412 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1413 tarc = E1000_READ_REG(hw, TARC0);
1414 tarc |= ((1 << 25) | (1 << 21));
1415 E1000_WRITE_REG(hw, TARC0, tarc);
1416 tarc = E1000_READ_REG(hw, TARC1);
1417 tarc |= (1 << 25);
1418 if (tctl & E1000_TCTL_MULR)
1419 tarc &= ~(1 << 28);
1420 else
1421 tarc |= (1 << 28);
1422 E1000_WRITE_REG(hw, TARC1, tarc);
1423 }
1424
581d708e 1425 e1000_config_collision_dist(hw);
1da177e4
LT		 1426
1427 /* Setup Transmit Descriptor Settings for eop descriptor */
1428 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1429 E1000_TXD_CMD_IFCS;
1430
581d708e 1431 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1432 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1433 else
1434 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1435
1436 /* Cache if we're 82544 running in PCI-X because we'll
1437 * need this to apply a workaround later in the send path. */
581d708e
MC		 1438 if (hw->mac_type == e1000_82544 &&
1439 hw->bus_type == e1000_bus_type_pcix)
1da177e4
LT		 1440 adapter->pcix_82544 = 1;
1441}
1442
1443/**
1444 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1445 * @adapter: board private structure
581d708e 1446 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1447 *
1448 * Returns 0 on success, negative on failure
1449 **/
1450
3ad2cc67 1451static int
581d708e
MC		 1452e1000_setup_rx_resources(struct e1000_adapter *adapter,
1453 struct e1000_rx_ring *rxdr)
1da177e4 1454{
1da177e4 1455 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1456 int size, desc_len;
1da177e4
LT		 1457
1458 size = sizeof(struct e1000_buffer) * rxdr->count;
a7ec15da 1459 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
581d708e 1460 if (!rxdr->buffer_info) {
2648345f
MC		 1461 DPRINTK(PROBE, ERR,
1462 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1463 return -ENOMEM;
1464 }
1465 memset(rxdr->buffer_info, 0, size);
1466
2d7edb92
MC		 1467 size = sizeof(struct e1000_ps_page) * rxdr->count;
1468 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
1469 if(!rxdr->ps_page) {
1470 vfree(rxdr->buffer_info);
1471 DPRINTK(PROBE, ERR,
1472 "Unable to allocate memory for the receive descriptor ring\n");
1473 return -ENOMEM;
1474 }
1475 memset(rxdr->ps_page, 0, size);
1476
1477 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1478 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
1479 if(!rxdr->ps_page_dma) {
1480 vfree(rxdr->buffer_info);
1481 kfree(rxdr->ps_page);
1482 DPRINTK(PROBE, ERR,
1483 "Unable to allocate memory for the receive descriptor ring\n");
1484 return -ENOMEM;
1485 }
1486 memset(rxdr->ps_page_dma, 0, size);
1487
1488 if(adapter->hw.mac_type <= e1000_82547_rev_2)
1489 desc_len = sizeof(struct e1000_rx_desc);
1490 else
1491 desc_len = sizeof(union e1000_rx_desc_packet_split);
1492
1da177e4
LT		 1493 /* Round up to nearest 4K */
1494
2d7edb92 1495 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1496 E1000_ROUNDUP(rxdr->size, 4096);
1497
1498 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1499
581d708e
MC		 1500 if (!rxdr->desc) {
1501 DPRINTK(PROBE, ERR,
1502 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1503setup_rx_desc_die:
1da177e4 1504 vfree(rxdr->buffer_info);
2d7edb92
MC		 1505 kfree(rxdr->ps_page);
1506 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1507 return -ENOMEM;
1508 }
1509
2648345f 1510 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1511 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1512 void *olddesc = rxdr->desc;
1513 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1514 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1515 "at %p\n", rxdr->size, rxdr->desc);
1516 /* Try again, without freeing the previous */
1da177e4 1517 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1518 /* Failed allocation, critical failure */
581d708e 1519 if (!rxdr->desc) {
1da177e4 1520 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1521 DPRINTK(PROBE, ERR,
1522 "Unable to allocate memory "
1523 "for the receive descriptor ring\n");
1da177e4
LT		 1524 goto setup_rx_desc_die;
1525 }
1526
1527 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1528 /* give up */
2648345f
MC		 1529 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1530 rxdr->dma);
1da177e4 1531 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1532 DPRINTK(PROBE, ERR,
1533 "Unable to allocate aligned memory "
1534 "for the receive descriptor ring\n");
581d708e 1535 goto setup_rx_desc_die;
1da177e4 1536 } else {
2648345f 1537 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1538 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1539 }
1540 }
1541 memset(rxdr->desc, 0, rxdr->size);
1542
1543 rxdr->next_to_clean = 0;
1544 rxdr->next_to_use = 0;
1545
1546 return 0;
1547}
1548
581d708e
MC		 1549/**
1550 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1551 * (Descriptors) for all queues
1552 * @adapter: board private structure
1553 *
1554 * If this function returns with an error, then it's possible one or
1555 * more of the rings is populated (while the rest are not). It is the
1556 * callers duty to clean those orphaned rings.
1557 *
1558 * Return 0 on success, negative on failure
1559 **/
1560
1561int
1562e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1563{
1564 int i, err = 0;
1565
f56799ea 1566 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1567 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1568 if (err) {
1569 DPRINTK(PROBE, ERR,
1570 "Allocation for Rx Queue %u failed\n", i);
1571 break;
1572 }
1573 }
1574
1575 return err;
1576}
1577
1da177e4 1578/**
2648345f 1579 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1580 * @adapter: Board private structure
1581 **/
e4c811c9
MC		 1582#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1583 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1584static void
1585e1000_setup_rctl(struct e1000_adapter *adapter)
1586{
2d7edb92
MC		 1587 uint32_t rctl, rfctl;
1588 uint32_t psrctl = 0;
e4c811c9
MC		 1589#ifdef CONFIG_E1000_PACKET_SPLIT
1590 uint32_t pages = 0;
1591#endif
1da177e4
LT		 1592
1593 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1594
1595 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1596
1597 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1598 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1599 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1600
1601 if(adapter->hw.tbi_compatibility_on == 1)
1602 rctl |= E1000_RCTL_SBP;
1603 else
1604 rctl &= ~E1000_RCTL_SBP;
1605
2d7edb92
MC		 1606 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1607 rctl &= ~E1000_RCTL_LPE;
1608 else
1609 rctl |= E1000_RCTL_LPE;
1610
1da177e4 1611 /* Setup buffer sizes */
868d5309 1612 if(adapter->hw.mac_type >= e1000_82571) {
2d7edb92
MC		 1613 /* We can now specify buffers in 1K increments.
1614 * BSIZE and BSEX are ignored in this case. */
1615 rctl |= adapter->rx_buffer_len << 0x11;
1616 } else {
1617 rctl &= ~E1000_RCTL_SZ_4096;
1618 rctl |= E1000_RCTL_BSEX;
1619 switch (adapter->rx_buffer_len) {
1620 case E1000_RXBUFFER_2048:
1621 default:
1622 rctl |= E1000_RCTL_SZ_2048;
1623 rctl &= ~E1000_RCTL_BSEX;
1624 break;
1625 case E1000_RXBUFFER_4096:
1626 rctl |= E1000_RCTL_SZ_4096;
1627 break;
1628 case E1000_RXBUFFER_8192:
1629 rctl |= E1000_RCTL_SZ_8192;
1630 break;
1631 case E1000_RXBUFFER_16384:
1632 rctl |= E1000_RCTL_SZ_16384;
1633 break;
1634 }
1635 }
1636
1637#ifdef CONFIG_E1000_PACKET_SPLIT
1638 /* 82571 and greater support packet-split where the protocol
1639 * header is placed in skb->data and the packet data is
1640 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1641 * In the case of a non-split, skb->data is linearly filled,
1642 * followed by the page buffers. Therefore, skb->data is
1643 * sized to hold the largest protocol header.
1644 */
e4c811c9
MC		 1645 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1646 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1647 PAGE_SIZE <= 16384)
1648 adapter->rx_ps_pages = pages;
1649 else
1650 adapter->rx_ps_pages = 0;
2d7edb92 1651#endif
e4c811c9 1652 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1653 /* Configure extra packet-split registers */
1654 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1655 rfctl |= E1000_RFCTL_EXTEN;
1656 /* disable IPv6 packet split support */
1657 rfctl |= E1000_RFCTL_IPV6_DIS;
1658 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1659
1660 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
1661
1662 psrctl |= adapter->rx_ps_bsize0 >>
1663 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1664
1665 switch (adapter->rx_ps_pages) {
1666 case 3:
1667 psrctl |= PAGE_SIZE <<
1668 E1000_PSRCTL_BSIZE3_SHIFT;
1669 case 2:
1670 psrctl |= PAGE_SIZE <<
1671 E1000_PSRCTL_BSIZE2_SHIFT;
1672 case 1:
1673 psrctl |= PAGE_SIZE >>
1674 E1000_PSRCTL_BSIZE1_SHIFT;
1675 break;
1676 }
2d7edb92
MC		 1677
1678 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1679 }
1680
1681 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1682}
1683
1684/**
1685 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1686 * @adapter: board private structure
1687 *
1688 * Configure the Rx unit of the MAC after a reset.
1689 **/
1690
1691static void
1692e1000_configure_rx(struct e1000_adapter *adapter)
1693{
581d708e
MC		 1694 uint64_t rdba;
1695 struct e1000_hw *hw = &adapter->hw;
1696 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
1697#ifdef CONFIG_E1000_MQ
1698 uint32_t reta, mrqc;
1699 int i;
1700#endif
2d7edb92 1701
e4c811c9 1702 if (adapter->rx_ps_pages) {
581d708e 1703 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1704 sizeof(union e1000_rx_desc_packet_split);
1705 adapter->clean_rx = e1000_clean_rx_irq_ps;
1706 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1707 } else {
581d708e
MC		 1708 rdlen = adapter->rx_ring[0].count *
1709 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1710 adapter->clean_rx = e1000_clean_rx_irq;
1711 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1712 }
1da177e4
LT		 1713
1714 /* disable receives while setting up the descriptors */
581d708e
MC		 1715 rctl = E1000_READ_REG(hw, RCTL);
1716 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1717
1718 /* set the Receive Delay Timer Register */
581d708e 1719 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1720
581d708e
MC		 1721 if (hw->mac_type >= e1000_82540) {
1722 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
1da177e4 1723 if(adapter->itr > 1)
581d708e 1724 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1725 1000000000 / (adapter->itr * 256));
1726 }
1727
2ae76d98
MC		 1728 if (hw->mac_type >= e1000_82571) {
1729 /* Reset delay timers after every interrupt */
1730 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1731 ctrl_ext |= E1000_CTRL_EXT_CANC;
1732 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1733 E1000_WRITE_FLUSH(hw);
1734 }
1735
581d708e
MC		 1736 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1737 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1738 switch (adapter->num_rx_queues) {
24025e4e
MC		 1739#ifdef CONFIG_E1000_MQ
1740 case 2:
1741 rdba = adapter->rx_ring[1].dma;
1742 E1000_WRITE_REG(hw, RDBAL1, (rdba & 0x00000000ffffffffULL));
1743 E1000_WRITE_REG(hw, RDBAH1, (rdba >> 32));
1744 E1000_WRITE_REG(hw, RDLEN1, rdlen);
1745 E1000_WRITE_REG(hw, RDH1, 0);
1746 E1000_WRITE_REG(hw, RDT1, 0);
1747 adapter->rx_ring[1].rdh = E1000_RDH1;
1748 adapter->rx_ring[1].rdt = E1000_RDT1;
1749 /* Fall Through */
1750#endif
1751 case 1:
1752 default:
581d708e
MC		 1753 rdba = adapter->rx_ring[0].dma;
1754 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1755 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1756 E1000_WRITE_REG(hw, RDLEN, rdlen);
1757 E1000_WRITE_REG(hw, RDH, 0);
1758 E1000_WRITE_REG(hw, RDT, 0);
1759 adapter->rx_ring[0].rdh = E1000_RDH;
1760 adapter->rx_ring[0].rdt = E1000_RDT;
1761 break;
24025e4e
MC		 1762 }
1763
1764#ifdef CONFIG_E1000_MQ
f56799ea 1765 if (adapter->num_rx_queues > 1) {
24025e4e
MC		 1766 uint32_t random[10];
1767
1768 get_random_bytes(&random[0], 40);
1769
1770 if (hw->mac_type <= e1000_82572) {
1771 E1000_WRITE_REG(hw, RSSIR, 0);
1772 E1000_WRITE_REG(hw, RSSIM, 0);
1773 }
1774
f56799ea 1775 switch (adapter->num_rx_queues) {
24025e4e
MC		 1776 case 2:
1777 default:
1778 reta = 0x00800080;
1779 mrqc = E1000_MRQC_ENABLE_RSS_2Q;
1780 break;
1781 }
1782
1783 /* Fill out redirection table */
1784 for (i = 0; i < 32; i++)
1785 E1000_WRITE_REG_ARRAY(hw, RETA, i, reta);
1786 /* Fill out hash function seeds */
1787 for (i = 0; i < 10; i++)
1788 E1000_WRITE_REG_ARRAY(hw, RSSRK, i, random[i]);
1789
1790 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1791 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1792 E1000_WRITE_REG(hw, MRQC, mrqc);
1793 }
1794
1795 /* Multiqueue and packet checksumming are mutually exclusive. */
1796 if (hw->mac_type >= e1000_82571) {
1797 rxcsum = E1000_READ_REG(hw, RXCSUM);
1798 rxcsum |= E1000_RXCSUM_PCSD;
1799 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1800 }
1801
1802#else
1da177e4
LT		 1803
1804 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1805 if (hw->mac_type >= e1000_82543) {
1806 rxcsum = E1000_READ_REG(hw, RXCSUM);
2d7edb92
MC		 1807 if(adapter->rx_csum == TRUE) {
1808 rxcsum |= E1000_RXCSUM_TUOFL;
1809
868d5309 1810 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1811 * Must be used in conjunction with packet-split. */
e4c811c9
MC		 1812 if ((hw->mac_type >= e1000_82571) &&
1813 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1814 rxcsum |= E1000_RXCSUM_IPPCSE;
1815 }
1816 } else {
1817 rxcsum &= ~E1000_RXCSUM_TUOFL;
1818 /* don't need to clear IPPCSE as it defaults to 0 */
1819 }
581d708e 1820 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4 1821 }
24025e4e 1822#endif /* CONFIG_E1000_MQ */
1da177e4 1823
581d708e
MC		 1824 if (hw->mac_type == e1000_82573)
1825 E1000_WRITE_REG(hw, ERT, 0x0100);
2d7edb92 1826
1da177e4 1827 /* Enable Receives */
581d708e 1828 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1829}
1830
1831/**
581d708e 1832 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1833 * @adapter: board private structure
581d708e 1834 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1835 *
1836 * Free all transmit software resources
1837 **/
1838
3ad2cc67 1839static void
581d708e
MC		 1840e1000_free_tx_resources(struct e1000_adapter *adapter,
1841 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1842{
1843 struct pci_dev *pdev = adapter->pdev;
1844
581d708e 1845 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1846
581d708e
MC		 1847 vfree(tx_ring->buffer_info);
1848 tx_ring->buffer_info = NULL;
1da177e4 1849
581d708e 1850 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1851
581d708e
MC		 1852 tx_ring->desc = NULL;
1853}
1854
1855/**
1856 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1857 * @adapter: board private structure
1858 *
1859 * Free all transmit software resources
1860 **/
1861
1862void
1863e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1864{
1865 int i;
1866
f56799ea 1867 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1868 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1869}
1870
1871static inline void
1872e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1873 struct e1000_buffer *buffer_info)
1874{
1da177e4 1875 if(buffer_info->dma) {
2648345f
MC		 1876 pci_unmap_page(adapter->pdev,
1877 buffer_info->dma,
1878 buffer_info->length,
1879 PCI_DMA_TODEVICE);
1da177e4
LT		 1880 buffer_info->dma = 0;
1881 }
1882 if(buffer_info->skb) {
1883 dev_kfree_skb_any(buffer_info->skb);
1884 buffer_info->skb = NULL;
1885 }
1886}
1887
1888/**
1889 * e1000_clean_tx_ring - Free Tx Buffers
1890 * @adapter: board private structure
581d708e 1891 * @tx_ring: ring to be cleaned
1da177e4
LT		 1892 **/
1893
1894static void
581d708e
MC		 1895e1000_clean_tx_ring(struct e1000_adapter *adapter,
1896 struct e1000_tx_ring *tx_ring)
1da177e4 1897{
1da177e4
LT		 1898 struct e1000_buffer *buffer_info;
1899 unsigned long size;
1900 unsigned int i;
1901
1902 /* Free all the Tx ring sk_buffs */
1903
1da177e4
LT		 1904 for(i = 0; i < tx_ring->count; i++) {
1905 buffer_info = &tx_ring->buffer_info[i];
1906 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1907 }
1908
1909 size = sizeof(struct e1000_buffer) * tx_ring->count;
1910 memset(tx_ring->buffer_info, 0, size);
1911
1912 /* Zero out the descriptor ring */
1913
1914 memset(tx_ring->desc, 0, tx_ring->size);
1915
1916 tx_ring->next_to_use = 0;
1917 tx_ring->next_to_clean = 0;
fd803241 1918 tx_ring->last_tx_tso = 0;
1da177e4 1919
581d708e
MC		 1920 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1921 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1922}
1923
1924/**
1925 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1926 * @adapter: board private structure
1927 **/
1928
1929static void
1930e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1931{
1932 int i;
1933
f56799ea 1934 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1935 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1936}
1937
1938/**
1939 * e1000_free_rx_resources - Free Rx Resources
1940 * @adapter: board private structure
581d708e 1941 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1942 *
1943 * Free all receive software resources
1944 **/
1945
3ad2cc67 1946static void
581d708e
MC		 1947e1000_free_rx_resources(struct e1000_adapter *adapter,
1948 struct e1000_rx_ring *rx_ring)
1da177e4 1949{
1da177e4
LT		 1950 struct pci_dev *pdev = adapter->pdev;
1951
581d708e 1952 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1953
1954 vfree(rx_ring->buffer_info);
1955 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1956 kfree(rx_ring->ps_page);
1957 rx_ring->ps_page = NULL;
1958 kfree(rx_ring->ps_page_dma);
1959 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1960
1961 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1962
1963 rx_ring->desc = NULL;
1964}
1965
1966/**
581d708e 1967 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 1968 * @adapter: board private structure
581d708e
MC		 1969 *
1970 * Free all receive software resources
1971 **/
1972
1973void
1974e1000_free_all_rx_resources(struct e1000_adapter *adapter)
1975{
1976 int i;
1977
f56799ea 1978 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 1979 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
1980}
1981
1982/**
1983 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1984 * @adapter: board private structure
1985 * @rx_ring: ring to free buffers from
1da177e4
LT		 1986 **/
1987
1988static void
581d708e
MC		 1989e1000_clean_rx_ring(struct e1000_adapter *adapter,
1990 struct e1000_rx_ring *rx_ring)
1da177e4 1991{
1da177e4 1992 struct e1000_buffer *buffer_info;
2d7edb92
MC		 1993 struct e1000_ps_page *ps_page;
1994 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 1995 struct pci_dev *pdev = adapter->pdev;
1996 unsigned long size;
2d7edb92 1997 unsigned int i, j;
1da177e4
LT		 1998
1999 /* Free all the Rx ring sk_buffs */
2000
2001 for(i = 0; i < rx_ring->count; i++) {
2002 buffer_info = &rx_ring->buffer_info[i];
2003 if(buffer_info->skb) {
2d7edb92
MC		 2004 ps_page = &rx_ring->ps_page[i];
2005 ps_page_dma = &rx_ring->ps_page_dma[i];
1da177e4
LT		 2006 pci_unmap_single(pdev,
2007 buffer_info->dma,
2008 buffer_info->length,
2009 PCI_DMA_FROMDEVICE);
2010
2011 dev_kfree_skb(buffer_info->skb);
2012 buffer_info->skb = NULL;
2d7edb92 2013
e4c811c9 2014 for(j = 0; j < adapter->rx_ps_pages; j++) {
2d7edb92
MC		 2015 if(!ps_page->ps_page[j]) break;
2016 pci_unmap_single(pdev,
2017 ps_page_dma->ps_page_dma[j],
2018 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2019 ps_page_dma->ps_page_dma[j] = 0;
2020 put_page(ps_page->ps_page[j]);
2021 ps_page->ps_page[j] = NULL;
2022 }
1da177e4
LT		 2023 }
2024 }
2025
2026 size = sizeof(struct e1000_buffer) * rx_ring->count;
2027 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2028 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2029 memset(rx_ring->ps_page, 0, size);
2030 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2031 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2032
2033 /* Zero out the descriptor ring */
2034
2035 memset(rx_ring->desc, 0, rx_ring->size);
2036
2037 rx_ring->next_to_clean = 0;
2038 rx_ring->next_to_use = 0;
2039
581d708e
MC		 2040 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2041 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2042}
2043
2044/**
2045 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2046 * @adapter: board private structure
2047 **/
2048
2049static void
2050e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2051{
2052 int i;
2053
f56799ea 2054 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2055 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2056}
2057
2058/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2059 * and memory write and invalidate disabled for certain operations
2060 */
2061static void
2062e1000_enter_82542_rst(struct e1000_adapter *adapter)
2063{
2064 struct net_device *netdev = adapter->netdev;
2065 uint32_t rctl;
2066
2067 e1000_pci_clear_mwi(&adapter->hw);
2068
2069 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2070 rctl |= E1000_RCTL_RST;
2071 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2072 E1000_WRITE_FLUSH(&adapter->hw);
2073 mdelay(5);
2074
2075 if(netif_running(netdev))
581d708e 2076 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2077}
2078
2079static void
2080e1000_leave_82542_rst(struct e1000_adapter *adapter)
2081{
2082 struct net_device *netdev = adapter->netdev;
2083 uint32_t rctl;
2084
2085 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2086 rctl &= ~E1000_RCTL_RST;
2087 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2088 E1000_WRITE_FLUSH(&adapter->hw);
2089 mdelay(5);
2090
2091 if(adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
2092 e1000_pci_set_mwi(&adapter->hw);
2093
2094 if(netif_running(netdev)) {
2095 e1000_configure_rx(adapter);
581d708e 2096 e1000_alloc_rx_buffers(adapter, &adapter->rx_ring[0]);
1da177e4
LT		 2097 }
2098}
2099
2100/**
2101 * e1000_set_mac - Change the Ethernet Address of the NIC
2102 * @netdev: network interface device structure
2103 * @p: pointer to an address structure
2104 *
2105 * Returns 0 on success, negative on failure
2106 **/
2107
2108static int
2109e1000_set_mac(struct net_device *netdev, void *p)
2110{
60490fe0 2111 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2112 struct sockaddr *addr = p;
2113
2114 if(!is_valid_ether_addr(addr->sa_data))
2115 return -EADDRNOTAVAIL;
2116
2117 /* 82542 2.0 needs to be in reset to write receive address registers */
2118
2119 if(adapter->hw.mac_type == e1000_82542_rev2_0)
2120 e1000_enter_82542_rst(adapter);
2121
2122 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2123 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2124
2125 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2126
868d5309
MC		 2127 /* With 82571 controllers, LAA may be overwritten (with the default)
2128 * due to controller reset from the other port. */
2129 if (adapter->hw.mac_type == e1000_82571) {
2130 /* activate the work around */
2131 adapter->hw.laa_is_present = 1;
2132
2133 /* Hold a copy of the LAA in RAR[14] This is done so that
2134 * between the time RAR[0] gets clobbered and the time it
2135 * gets fixed (in e1000_watchdog), the actual LAA is in one
2136 * of the RARs and no incoming packets directed to this port
2137 * are dropped. Eventaully the LAA will be in RAR[0] and
2138 * RAR[14] */
2139 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
2140 E1000_RAR_ENTRIES - 1);
2141 }
2142
1da177e4
LT		 2143 if(adapter->hw.mac_type == e1000_82542_rev2_0)
2144 e1000_leave_82542_rst(adapter);
2145
2146 return 0;
2147}
2148
2149/**
2150 * e1000_set_multi - Multicast and Promiscuous mode set
2151 * @netdev: network interface device structure
2152 *
2153 * The set_multi entry point is called whenever the multicast address
2154 * list or the network interface flags are updated. This routine is
2155 * responsible for configuring the hardware for proper multicast,
2156 * promiscuous mode, and all-multi behavior.
2157 **/
2158
2159static void
2160e1000_set_multi(struct net_device *netdev)
2161{
60490fe0 2162 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2163 struct e1000_hw *hw = &adapter->hw;
2164 struct dev_mc_list *mc_ptr;
2165 uint32_t rctl;
2166 uint32_t hash_value;
868d5309 2167 int i, rar_entries = E1000_RAR_ENTRIES;
1da177e4 2168
868d5309
MC		 2169 /* reserve RAR[14] for LAA over-write work-around */
2170 if (adapter->hw.mac_type == e1000_82571)
2171 rar_entries--;
1da177e4 2172
2648345f
MC		 2173 /* Check for Promiscuous and All Multicast modes */
2174
1da177e4
LT		 2175 rctl = E1000_READ_REG(hw, RCTL);
2176
2177 if(netdev->flags & IFF_PROMISC) {
2178 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2179 } else if(netdev->flags & IFF_ALLMULTI) {
2180 rctl |= E1000_RCTL_MPE;
2181 rctl &= ~E1000_RCTL_UPE;
2182 } else {
2183 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2184 }
2185
2186 E1000_WRITE_REG(hw, RCTL, rctl);
2187
2188 /* 82542 2.0 needs to be in reset to write receive address registers */
2189
2190 if(hw->mac_type == e1000_82542_rev2_0)
2191 e1000_enter_82542_rst(adapter);
2192
2193 /* load the first 14 multicast address into the exact filters 1-14
2194 * RAR 0 is used for the station MAC adddress
2195 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2196 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2197 */
2198 mc_ptr = netdev->mc_list;
2199
868d5309
MC		 2200 for(i = 1; i < rar_entries; i++) {
2201 if (mc_ptr) {
1da177e4
LT		 2202 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2203 mc_ptr = mc_ptr->next;
2204 } else {
2205 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2206 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2207 }
2208 }
2209
2210 /* clear the old settings from the multicast hash table */
2211
2212 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
2213 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2214
2215 /* load any remaining addresses into the hash table */
2216
2217 for(; mc_ptr; mc_ptr = mc_ptr->next) {
2218 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2219 e1000_mta_set(hw, hash_value);
2220 }
2221
2222 if(hw->mac_type == e1000_82542_rev2_0)
2223 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2224}
2225
2226/* Need to wait a few seconds after link up to get diagnostic information from
2227 * the phy */
2228
2229static void
2230e1000_update_phy_info(unsigned long data)
2231{
2232 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2233 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2234}
2235
2236/**
2237 * e1000_82547_tx_fifo_stall - Timer Call-back
2238 * @data: pointer to adapter cast into an unsigned long
2239 **/
2240
2241static void
2242e1000_82547_tx_fifo_stall(unsigned long data)
2243{
2244 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2245 struct net_device *netdev = adapter->netdev;
2246 uint32_t tctl;
2247
2248 if(atomic_read(&adapter->tx_fifo_stall)) {
2249 if((E1000_READ_REG(&adapter->hw, TDT) ==
2250 E1000_READ_REG(&adapter->hw, TDH)) &&
2251 (E1000_READ_REG(&adapter->hw, TDFT) ==
2252 E1000_READ_REG(&adapter->hw, TDFH)) &&
2253 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2254 E1000_READ_REG(&adapter->hw, TDFHS))) {
2255 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2256 E1000_WRITE_REG(&adapter->hw, TCTL,
2257 tctl & ~E1000_TCTL_EN);
2258 E1000_WRITE_REG(&adapter->hw, TDFT,
2259 adapter->tx_head_addr);
2260 E1000_WRITE_REG(&adapter->hw, TDFH,
2261 adapter->tx_head_addr);
2262 E1000_WRITE_REG(&adapter->hw, TDFTS,
2263 adapter->tx_head_addr);
2264 E1000_WRITE_REG(&adapter->hw, TDFHS,
2265 adapter->tx_head_addr);
2266 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2267 E1000_WRITE_FLUSH(&adapter->hw);
2268
2269 adapter->tx_fifo_head = 0;
2270 atomic_set(&adapter->tx_fifo_stall, 0);
2271 netif_wake_queue(netdev);
2272 } else {
2273 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2274 }
2275 }
2276}
2277
2278/**
2279 * e1000_watchdog - Timer Call-back
2280 * @data: pointer to adapter cast into an unsigned long
2281 **/
2282static void
2283e1000_watchdog(unsigned long data)
2284{
2285 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2286
2287 /* Do the rest outside of interrupt context */
2288 schedule_work(&adapter->watchdog_task);
2289}
2290
2291static void
2292e1000_watchdog_task(struct e1000_adapter *adapter)
2293{
2294 struct net_device *netdev = adapter->netdev;
545c67c0 2295 struct e1000_tx_ring *txdr = adapter->tx_ring;
1da177e4
LT		 2296 uint32_t link;
2297
2298 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 2299 if (adapter->hw.mac_type == e1000_82573) {
2300 e1000_enable_tx_pkt_filtering(&adapter->hw);
2301 if(adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2302 e1000_update_mng_vlan(adapter);
2303 }
1da177e4
LT		 2304
2305 if((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
2306 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2307 link = !adapter->hw.serdes_link_down;
2308 else
2309 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2310
2311 if(link) {
2312 if(!netif_carrier_ok(netdev)) {
2313 e1000_get_speed_and_duplex(&adapter->hw,
2314 &adapter->link_speed,
2315 &adapter->link_duplex);
2316
2317 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2318 adapter->link_speed,
2319 adapter->link_duplex == FULL_DUPLEX ?
2320 "Full Duplex" : "Half Duplex");
2321
2322 netif_carrier_on(netdev);
2323 netif_wake_queue(netdev);
2324 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2325 adapter->smartspeed = 0;
2326 }
2327 } else {
2328 if(netif_carrier_ok(netdev)) {
2329 adapter->link_speed = 0;
2330 adapter->link_duplex = 0;
2331 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2332 netif_carrier_off(netdev);
2333 netif_stop_queue(netdev);
2334 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2335 }
2336
2337 e1000_smartspeed(adapter);
2338 }
2339
2340 e1000_update_stats(adapter);
2341
2342 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2343 adapter->tpt_old = adapter->stats.tpt;
2344 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2345 adapter->colc_old = adapter->stats.colc;
2346
2347 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2348 adapter->gorcl_old = adapter->stats.gorcl;
2349 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2350 adapter->gotcl_old = adapter->stats.gotcl;
2351
2352 e1000_update_adaptive(&adapter->hw);
2353
f56799ea
JK		 2354#ifdef CONFIG_E1000_MQ
2355 txdr = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2356#endif
2357 if (!netif_carrier_ok(netdev)) {
581d708e 2358 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2359 /* We've lost link, so the controller stops DMA,
2360 * but we've got queued Tx work that's never going
2361 * to get done, so reset controller to flush Tx.
2362 * (Do the reset outside of interrupt context). */
2363 schedule_work(&adapter->tx_timeout_task);
2364 }
2365 }
2366
2367 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
2368 if(adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
2369 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2370 * asymmetrical Tx or Rx gets ITR=8000; everyone
2371 * else is between 2000-8000. */
2372 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
2373 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
2374 adapter->gotcl - adapter->gorcl :
2375 adapter->gorcl - adapter->gotcl) / 10000;
2376 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2377 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2378 }
2379
2380 /* Cause software interrupt to ensure rx ring is cleaned */
2381 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2382
2648345f 2383 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2384 adapter->detect_tx_hung = TRUE;
2385
868d5309
MC		 2386 /* With 82571 controllers, LAA may be overwritten due to controller
2387 * reset from the other port. Set the appropriate LAA in RAR[0] */
2388 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2389 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2390
1da177e4
LT		 2391 /* Reset the timer */
2392 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2393}
2394
2395#define E1000_TX_FLAGS_CSUM 0x00000001
2396#define E1000_TX_FLAGS_VLAN 0x00000002
2397#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2398#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2399#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2400#define E1000_TX_FLAGS_VLAN_SHIFT 16
2401
2402static inline int
581d708e
MC		 2403e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2404 struct sk_buff *skb)
1da177e4
LT		 2405{
2406#ifdef NETIF_F_TSO
2407 struct e1000_context_desc *context_desc;
545c67c0 2408 struct e1000_buffer *buffer_info;
1da177e4
LT		 2409 unsigned int i;
2410 uint32_t cmd_length = 0;
2d7edb92 2411 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2412 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2413 int err;
2414
2415 if(skb_shinfo(skb)->tso_size) {
2416 if (skb_header_cloned(skb)) {
2417 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2418 if (err)
2419 return err;
2420 }
2421
2422 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2423 mss = skb_shinfo(skb)->tso_size;
2d7edb92
MC		 2424 if(skb->protocol == ntohs(ETH_P_IP)) {
2425 skb->nh.iph->tot_len = 0;
2426 skb->nh.iph->check = 0;
2427 skb->h.th->check =
2428 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2429 skb->nh.iph->daddr,
2430 0,
2431 IPPROTO_TCP,
2432 0);
2433 cmd_length = E1000_TXD_CMD_IP;
2434 ipcse = skb->h.raw - skb->data - 1;
2435#ifdef NETIF_F_TSO_IPV6
2436 } else if(skb->protocol == ntohs(ETH_P_IPV6)) {
2437 skb->nh.ipv6h->payload_len = 0;
2438 skb->h.th->check =
2439 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2440 &skb->nh.ipv6h->daddr,
2441 0,
2442 IPPROTO_TCP,
2443 0);
2444 ipcse = 0;
2445#endif
2446 }
1da177e4
LT		 2447 ipcss = skb->nh.raw - skb->data;
2448 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2449 tucss = skb->h.raw - skb->data;
2450 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2451 tucse = 0;
2452
2453 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2454 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2455
581d708e
MC		 2456 i = tx_ring->next_to_use;
2457 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2458 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2459
2460 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2461 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2462 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2463 context_desc->upper_setup.tcp_fields.tucss = tucss;
2464 context_desc->upper_setup.tcp_fields.tucso = tucso;
2465 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2466 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2467 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2468 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2469
545c67c0
JK		 2470 buffer_info->time_stamp = jiffies;
2471
581d708e
MC		 2472 if (++i == tx_ring->count) i = 0;
2473 tx_ring->next_to_use = i;
1da177e4
LT		 2474
2475 return 1;
2476 }
2477#endif
2478
2479 return 0;
2480}
2481
2482static inline boolean_t
581d708e
MC		 2483e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2484 struct sk_buff *skb)
1da177e4
LT		 2485{
2486 struct e1000_context_desc *context_desc;
545c67c0 2487 struct e1000_buffer *buffer_info;
1da177e4
LT		 2488 unsigned int i;
2489 uint8_t css;
2490
2491 if(likely(skb->ip_summed == CHECKSUM_HW)) {
2492 css = skb->h.raw - skb->data;
2493
581d708e 2494 i = tx_ring->next_to_use;
545c67c0 2495 buffer_info = &tx_ring->buffer_info[i];
581d708e 2496 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2497
2498 context_desc->upper_setup.tcp_fields.tucss = css;
2499 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2500 context_desc->upper_setup.tcp_fields.tucse = 0;
2501 context_desc->tcp_seg_setup.data = 0;
2502 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2503
545c67c0
JK		 2504 buffer_info->time_stamp = jiffies;
2505
581d708e
MC		 2506 if (unlikely(++i == tx_ring->count)) i = 0;
2507 tx_ring->next_to_use = i;
1da177e4
LT		 2508
2509 return TRUE;
2510 }
2511
2512 return FALSE;
2513}
2514
2515#define E1000_MAX_TXD_PWR 12
2516#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2517
2518static inline int
581d708e
MC		 2519e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2520 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2521 unsigned int nr_frags, unsigned int mss)
1da177e4 2522{
1da177e4
LT		 2523 struct e1000_buffer *buffer_info;
2524 unsigned int len = skb->len;
2525 unsigned int offset = 0, size, count = 0, i;
2526 unsigned int f;
2527 len -= skb->data_len;
2528
2529 i = tx_ring->next_to_use;
2530
2531 while(len) {
2532 buffer_info = &tx_ring->buffer_info[i];
2533 size = min(len, max_per_txd);
2534#ifdef NETIF_F_TSO
fd803241
JK		 2535 /* Workaround for Controller erratum --
2536 * descriptor for non-tso packet in a linear SKB that follows a
2537 * tso gets written back prematurely before the data is fully
2538 * DMAd to the controller */
2539 if (!skb->data_len && tx_ring->last_tx_tso &&
2540 !skb_shinfo(skb)->tso_size) {
2541 tx_ring->last_tx_tso = 0;
2542 size -= 4;
2543 }
2544
1da177e4
LT		 2545 /* Workaround for premature desc write-backs
2546 * in TSO mode. Append 4-byte sentinel desc */
2547 if(unlikely(mss && !nr_frags && size == len && size > 8))
2548 size -= 4;
2549#endif
97338bde
MC		 2550 /* work-around for errata 10 and it applies
2551 * to all controllers in PCI-X mode
2552 * The fix is to make sure that the first descriptor of a
2553 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2554 */
2555 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2556 (size > 2015) && count == 0))
2557 size = 2015;
2558
1da177e4
LT		 2559 /* Workaround for potential 82544 hang in PCI-X. Avoid
2560 * terminating buffers within evenly-aligned dwords. */
2561 if(unlikely(adapter->pcix_82544 &&
2562 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2563 size > 4))
2564 size -= 4;
2565
2566 buffer_info->length = size;
2567 buffer_info->dma =
2568 pci_map_single(adapter->pdev,
2569 skb->data + offset,
2570 size,
2571 PCI_DMA_TODEVICE);
2572 buffer_info->time_stamp = jiffies;
2573
2574 len -= size;
2575 offset += size;
2576 count++;
2577 if(unlikely(++i == tx_ring->count)) i = 0;
2578 }
2579
2580 for(f = 0; f < nr_frags; f++) {
2581 struct skb_frag_struct *frag;
2582
2583 frag = &skb_shinfo(skb)->frags[f];
2584 len = frag->size;
2585 offset = frag->page_offset;
2586
2587 while(len) {
2588 buffer_info = &tx_ring->buffer_info[i];
2589 size = min(len, max_per_txd);
2590#ifdef NETIF_F_TSO
2591 /* Workaround for premature desc write-backs
2592 * in TSO mode. Append 4-byte sentinel desc */
2593 if(unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
2594 size -= 4;
2595#endif
2596 /* Workaround for potential 82544 hang in PCI-X.
2597 * Avoid terminating buffers within evenly-aligned
2598 * dwords. */
2599 if(unlikely(adapter->pcix_82544 &&
2600 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2601 size > 4))
2602 size -= 4;
2603
2604 buffer_info->length = size;
2605 buffer_info->dma =
2606 pci_map_page(adapter->pdev,
2607 frag->page,
2608 offset,
2609 size,
2610 PCI_DMA_TODEVICE);
2611 buffer_info->time_stamp = jiffies;
2612
2613 len -= size;
2614 offset += size;
2615 count++;
2616 if(unlikely(++i == tx_ring->count)) i = 0;
2617 }
2618 }
2619
2620 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2621 tx_ring->buffer_info[i].skb = skb;
2622 tx_ring->buffer_info[first].next_to_watch = i;
2623
2624 return count;
2625}
2626
2627static inline void
581d708e
MC		 2628e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2629 int tx_flags, int count)
1da177e4 2630{
1da177e4
LT		 2631 struct e1000_tx_desc *tx_desc = NULL;
2632 struct e1000_buffer *buffer_info;
2633 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2634 unsigned int i;
2635
2636 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) {
2637 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2638 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2639 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2640
2641 if(likely(tx_flags & E1000_TX_FLAGS_IPV4))
2642 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2643 }
2644
2645 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
2646 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2647 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2648 }
2649
2650 if(unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
2651 txd_lower |= E1000_TXD_CMD_VLE;
2652 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2653 }
2654
2655 i = tx_ring->next_to_use;
2656
2657 while(count--) {
2658 buffer_info = &tx_ring->buffer_info[i];
2659 tx_desc = E1000_TX_DESC(*tx_ring, i);
2660 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2661 tx_desc->lower.data =
2662 cpu_to_le32(txd_lower | buffer_info->length);
2663 tx_desc->upper.data = cpu_to_le32(txd_upper);
2664 if(unlikely(++i == tx_ring->count)) i = 0;
2665 }
2666
2667 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2668
2669 /* Force memory writes to complete before letting h/w
2670 * know there are new descriptors to fetch. (Only
2671 * applicable for weak-ordered memory model archs,
2672 * such as IA-64). */
2673 wmb();
2674
2675 tx_ring->next_to_use = i;
581d708e 2676 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2677}
2678
2679/**
2680 * 82547 workaround to avoid controller hang in half-duplex environment.
2681 * The workaround is to avoid queuing a large packet that would span
2682 * the internal Tx FIFO ring boundary by notifying the stack to resend
2683 * the packet at a later time. This gives the Tx FIFO an opportunity to
2684 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2685 * to the beginning of the Tx FIFO.
2686 **/
2687
2688#define E1000_FIFO_HDR 0x10
2689#define E1000_82547_PAD_LEN 0x3E0
2690
2691static inline int
2692e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2693{
2694 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2695 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2696
2697 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2698
2699 if(adapter->link_duplex != HALF_DUPLEX)
2700 goto no_fifo_stall_required;
2701
2702 if(atomic_read(&adapter->tx_fifo_stall))
2703 return 1;
2704
2705 if(skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
2706 atomic_set(&adapter->tx_fifo_stall, 1);
2707 return 1;
2708 }
2709
2710no_fifo_stall_required:
2711 adapter->tx_fifo_head += skb_fifo_len;
2712 if(adapter->tx_fifo_head >= adapter->tx_fifo_size)
2713 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2714 return 0;
2715}
2716
2d7edb92
MC		 2717#define MINIMUM_DHCP_PACKET_SIZE 282
2718static inline int
2719e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2720{
2721 struct e1000_hw *hw = &adapter->hw;
2722 uint16_t length, offset;
2723 if(vlan_tx_tag_present(skb)) {
2724 if(!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2725 ( adapter->hw.mng_cookie.status &
2726 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2727 return 0;
2728 }
a174fd88 2729 if ((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
2d7edb92
MC		 2730 struct ethhdr *eth = (struct ethhdr *) skb->data;
2731 if((htons(ETH_P_IP) == eth->h_proto)) {
2732 const struct iphdr *ip =
2733 (struct iphdr *)((uint8_t *)skb->data+14);
2734 if(IPPROTO_UDP == ip->protocol) {
2735 struct udphdr *udp =
2736 (struct udphdr *)((uint8_t *)ip +
2737 (ip->ihl << 2));
2738 if(ntohs(udp->dest) == 67) {
2739 offset = (uint8_t *)udp + 8 - skb->data;
2740 length = skb->len - offset;
2741
2742 return e1000_mng_write_dhcp_info(hw,
2743 (uint8_t *)udp + 8,
2744 length);
2745 }
2746 }
2747 }
2748 }
2749 return 0;
2750}
2751
1da177e4
LT		 2752#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2753static int
2754e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2755{
60490fe0 2756 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2757 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2758 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2759 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2760 unsigned int tx_flags = 0;
2761 unsigned int len = skb->len;
2762 unsigned long flags;
2763 unsigned int nr_frags = 0;
2764 unsigned int mss = 0;
2765 int count = 0;
2766 int tso;
2767 unsigned int f;
2768 len -= skb->data_len;
2769
24025e4e
MC		 2770#ifdef CONFIG_E1000_MQ
2771 tx_ring = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2772#else
581d708e 2773 tx_ring = adapter->tx_ring;
24025e4e
MC		 2774#endif
2775
581d708e 2776 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2777 dev_kfree_skb_any(skb);
2778 return NETDEV_TX_OK;
2779 }
2780
2781#ifdef NETIF_F_TSO
2782 mss = skb_shinfo(skb)->tso_size;
2648345f 2783 /* The controller does a simple calculation to
1da177e4
LT		 2784 * make sure there is enough room in the FIFO before
2785 * initiating the DMA for each buffer. The calc is:
2786 * 4 = ceil(buffer len/mss). To make sure we don't
2787 * overrun the FIFO, adjust the max buffer len if mss
2788 * drops. */
2789 if(mss) {
9a3056da 2790 uint8_t hdr_len;
1da177e4
LT		 2791 max_per_txd = min(mss << 2, max_per_txd);
2792 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da
JK		 2793
2794 /* TSO Workaround for 82571/2 Controllers -- if skb->data
2795 * points to just header, pull a few bytes of payload from
2796 * frags into skb->data */
2797 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2798 if (skb->data_len && (hdr_len == (skb->len - skb->data_len)) &&
2799 (adapter->hw.mac_type == e1000_82571 ||
2800 adapter->hw.mac_type == e1000_82572)) {
2801 len = skb->len - skb->data_len;
2802 }
1da177e4
LT		 2803 }
2804
2805 if((mss) || (skb->ip_summed == CHECKSUM_HW))
9a3056da 2806 /* reserve a descriptor for the offload context */
1da177e4 2807 count++;
2648345f 2808 count++;
1da177e4
LT		 2809#else
2810 if(skb->ip_summed == CHECKSUM_HW)
2811 count++;
2812#endif
fd803241
JK		 2813
2814#ifdef NETIF_F_TSO
2815 /* Controller Erratum workaround */
2816 if (!skb->data_len && tx_ring->last_tx_tso &&
2817 !skb_shinfo(skb)->tso_size)
2818 count++;
2819#endif
2820
1da177e4
LT		 2821 count += TXD_USE_COUNT(len, max_txd_pwr);
2822
2823 if(adapter->pcix_82544)
2824 count++;
2825
97338bde
MC		 2826 /* work-around for errata 10 and it applies to all controllers
2827 * in PCI-X mode, so add one more descriptor to the count
2828 */
2829 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2830 (len > 2015)))
2831 count++;
2832
1da177e4
LT		 2833 nr_frags = skb_shinfo(skb)->nr_frags;
2834 for(f = 0; f < nr_frags; f++)
2835 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2836 max_txd_pwr);
2837 if(adapter->pcix_82544)
2838 count += nr_frags;
2839
9a3056da
JK		 2840 unsigned int pull_size;
2841 pull_size = min((unsigned int)4, skb->data_len);
2842 if (!__pskb_pull_tail(skb, pull_size)) {
2843 printk(KERN_ERR "__pskb_pull_tail failed.\n");
2844 dev_kfree_skb_any(skb);
2845 return -EFAULT;
868d5309 2846 }
868d5309 2847
2d7edb92
MC		 2848 if(adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
2849 e1000_transfer_dhcp_info(adapter, skb);
2850
581d708e
MC		 2851 local_irq_save(flags);
2852 if (!spin_trylock(&tx_ring->tx_lock)) {
2853 /* Collision - tell upper layer to requeue */
2854 local_irq_restore(flags);
2855 return NETDEV_TX_LOCKED;
2856 }
1da177e4
LT		 2857
2858 /* need: count + 2 desc gap to keep tail from touching
2859 * head, otherwise try next time */
581d708e 2860 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2861 netif_stop_queue(netdev);
581d708e 2862 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2863 return NETDEV_TX_BUSY;
2864 }
2865
2866 if(unlikely(adapter->hw.mac_type == e1000_82547)) {
2867 if(unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
2868 netif_stop_queue(netdev);
2869 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2870 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2871 return NETDEV_TX_BUSY;
2872 }
2873 }
2874
2875 if(unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
2876 tx_flags |= E1000_TX_FLAGS_VLAN;
2877 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2878 }
2879
581d708e 2880 first = tx_ring->next_to_use;
1da177e4 2881
581d708e 2882 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2883 if (tso < 0) {
2884 dev_kfree_skb_any(skb);
581d708e 2885 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2886 return NETDEV_TX_OK;
2887 }
2888
fd803241
JK		 2889 if (likely(tso)) {
2890 tx_ring->last_tx_tso = 1;
1da177e4 2891 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 2892 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 2893 tx_flags |= E1000_TX_FLAGS_CSUM;
2894
2d7edb92 2895 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 2896 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 2897 * no longer assume, we must. */
581d708e 2898 if (likely(skb->protocol == ntohs(ETH_P_IP)))
2d7edb92
MC		 2899 tx_flags |= E1000_TX_FLAGS_IPV4;
2900
581d708e
MC		 2901 e1000_tx_queue(adapter, tx_ring, tx_flags,
2902 e1000_tx_map(adapter, tx_ring, skb, first,
2903 max_per_txd, nr_frags, mss));
1da177e4
LT		 2904
2905 netdev->trans_start = jiffies;
2906
2907 /* Make sure there is space in the ring for the next send. */
581d708e 2908 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 2909 netif_stop_queue(netdev);
2910
581d708e 2911 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2912 return NETDEV_TX_OK;
2913}
2914
2915/**
2916 * e1000_tx_timeout - Respond to a Tx Hang
2917 * @netdev: network interface device structure
2918 **/
2919
2920static void
2921e1000_tx_timeout(struct net_device *netdev)
2922{
60490fe0 2923 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2924
2925 /* Do the reset outside of interrupt context */
2926 schedule_work(&adapter->tx_timeout_task);
2927}
2928
2929static void
2930e1000_tx_timeout_task(struct net_device *netdev)
2931{
60490fe0 2932 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2933
6b7660cd 2934 adapter->tx_timeout_count++;
1da177e4
LT		 2935 e1000_down(adapter);
2936 e1000_up(adapter);
2937}
2938
2939/**
2940 * e1000_get_stats - Get System Network Statistics
2941 * @netdev: network interface device structure
2942 *
2943 * Returns the address of the device statistics structure.
2944 * The statistics are actually updated from the timer callback.
2945 **/
2946
2947static struct net_device_stats *
2948e1000_get_stats(struct net_device *netdev)
2949{
60490fe0 2950 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2951
6b7660cd 2952 /* only return the current stats */
1da177e4
LT		 2953 return &adapter->net_stats;
2954}
2955
2956/**
2957 * e1000_change_mtu - Change the Maximum Transfer Unit
2958 * @netdev: network interface device structure
2959 * @new_mtu: new value for maximum frame size
2960 *
2961 * Returns 0 on success, negative on failure
2962 **/
2963
2964static int
2965e1000_change_mtu(struct net_device *netdev, int new_mtu)
2966{
60490fe0 2967 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2968 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
2969
2970 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
2971 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2972 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
2973 return -EINVAL;
2974 }
2975
868d5309 2976#define MAX_STD_JUMBO_FRAME_SIZE 9234
2d7edb92 2977 /* might want this to be bigger enum check... */
868d5309
MC		 2978 /* 82571 controllers limit jumbo frame size to 10500 bytes */
2979 if ((adapter->hw.mac_type == e1000_82571 ||
2980 adapter->hw.mac_type == e1000_82572) &&
2981 max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2982 DPRINTK(PROBE, ERR, "MTU > 9216 bytes not supported "
2983 "on 82571 and 82572 controllers.\n");
2984 return -EINVAL;
2985 }
2986
2987 if(adapter->hw.mac_type == e1000_82573 &&
2d7edb92
MC		 2988 max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2989 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2990 "on 82573\n");
1da177e4 2991 return -EINVAL;
2d7edb92 2992 }
1da177e4 2993
2d7edb92
MC		 2994 if(adapter->hw.mac_type > e1000_82547_rev_2) {
2995 adapter->rx_buffer_len = max_frame;
2996 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
1da177e4 2997 } else {
2d7edb92
MC		 2998 if(unlikely((adapter->hw.mac_type < e1000_82543) &&
2999 (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE))) {
3000 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
3001 "on 82542\n");
3002 return -EINVAL;
3003
3004 } else {
3005 if(max_frame <= E1000_RXBUFFER_2048) {
3006 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3007 } else if(max_frame <= E1000_RXBUFFER_4096) {
3008 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3009 } else if(max_frame <= E1000_RXBUFFER_8192) {
3010 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3011 } else if(max_frame <= E1000_RXBUFFER_16384) {
3012 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3013 }
3014 }
1da177e4
LT		 3015 }
3016
2d7edb92
MC		 3017 netdev->mtu = new_mtu;
3018
3019 if(netif_running(netdev)) {
1da177e4
LT		 3020 e1000_down(adapter);
3021 e1000_up(adapter);
3022 }
3023
1da177e4
LT		 3024 adapter->hw.max_frame_size = max_frame;
3025
3026 return 0;
3027}
3028
3029/**
3030 * e1000_update_stats - Update the board statistics counters
3031 * @adapter: board private structure
3032 **/
3033
3034void
3035e1000_update_stats(struct e1000_adapter *adapter)
3036{
3037 struct e1000_hw *hw = &adapter->hw;
3038 unsigned long flags;
3039 uint16_t phy_tmp;
3040
3041#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3042
3043 spin_lock_irqsave(&adapter->stats_lock, flags);
3044
3045 /* these counters are modified from e1000_adjust_tbi_stats,
3046 * called from the interrupt context, so they must only
3047 * be written while holding adapter->stats_lock
3048 */
3049
3050 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3051 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3052 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3053 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3054 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3055 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3056 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3057 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3058 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3059 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3060 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3061 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3062 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3063
3064 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3065 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3066 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3067 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3068 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3069 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3070 adapter->stats.dc += E1000_READ_REG(hw, DC);
3071 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3072 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3073 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3074 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3075 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3076 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3077 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3078 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3079 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3080 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3081 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3082 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3083 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3084 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3085 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3086 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3087 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3088 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3089 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3090 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3091 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3092 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3093 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3094 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3095 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3096 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3097 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3098
3099 /* used for adaptive IFS */
3100
3101 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3102 adapter->stats.tpt += hw->tx_packet_delta;
3103 hw->collision_delta = E1000_READ_REG(hw, COLC);
3104 adapter->stats.colc += hw->collision_delta;
3105
3106 if(hw->mac_type >= e1000_82543) {
3107 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3108 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3109 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3110 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3111 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3112 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3113 }
2d7edb92
MC		 3114 if(hw->mac_type > e1000_82547_rev_2) {
3115 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3116 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3117 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3118 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3119 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3120 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3121 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3122 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3123 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3124 }
1da177e4
LT		 3125
3126 /* Fill out the OS statistics structure */
3127
3128 adapter->net_stats.rx_packets = adapter->stats.gprc;
3129 adapter->net_stats.tx_packets = adapter->stats.gptc;
3130 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3131 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3132 adapter->net_stats.multicast = adapter->stats.mprc;
3133 adapter->net_stats.collisions = adapter->stats.colc;
3134
3135 /* Rx Errors */
3136
3137 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3138 adapter->stats.crcerrs + adapter->stats.algnerrc +
6b7660cd
JK		 3139 adapter->stats.rlec + adapter->stats.cexterr;
3140 adapter->net_stats.rx_dropped = 0;
1da177e4
LT		 3141 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3142 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3143 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3144 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3145
3146 /* Tx Errors */
3147
3148 adapter->net_stats.tx_errors = adapter->stats.ecol +
3149 adapter->stats.latecol;
3150 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3151 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3152 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3153
3154 /* Tx Dropped needs to be maintained elsewhere */
3155
3156 /* Phy Stats */
3157
3158 if(hw->media_type == e1000_media_type_copper) {
3159 if((adapter->link_speed == SPEED_1000) &&
3160 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3161 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3162 adapter->phy_stats.idle_errors += phy_tmp;
3163 }
3164
3165 if((hw->mac_type <= e1000_82546) &&
3166 (hw->phy_type == e1000_phy_m88) &&
3167 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3168 adapter->phy_stats.receive_errors += phy_tmp;
3169 }
3170
3171 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3172}
3173
24025e4e
MC		 3174#ifdef CONFIG_E1000_MQ
3175void
3176e1000_rx_schedule(void *data)
3177{
3178 struct net_device *poll_dev, *netdev = data;
3179 struct e1000_adapter *adapter = netdev->priv;
3180 int this_cpu = get_cpu();
3181
3182 poll_dev = *per_cpu_ptr(adapter->cpu_netdev, this_cpu);
3183 if (poll_dev == NULL) {
3184 put_cpu();
3185 return;
3186 }
3187
3188 if (likely(netif_rx_schedule_prep(poll_dev)))
3189 __netif_rx_schedule(poll_dev);
3190 else
3191 e1000_irq_enable(adapter);
3192
3193 put_cpu();
3194}
3195#endif
3196
1da177e4
LT		 3197/**
3198 * e1000_intr - Interrupt Handler
3199 * @irq: interrupt number
3200 * @data: pointer to a network interface device structure
3201 * @pt_regs: CPU registers structure
3202 **/
3203
3204static irqreturn_t
3205e1000_intr(int irq, void *data, struct pt_regs *regs)
3206{
3207 struct net_device *netdev = data;
60490fe0 3208 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3209 struct e1000_hw *hw = &adapter->hw;
3210 uint32_t icr = E1000_READ_REG(hw, ICR);
166d823d 3211#if defined(CONFIG_E1000_NAPI) && defined(CONFIG_E1000_MQ) || !defined(CONFIG_E1000_NAPI)
581d708e 3212 int i;
be2b28ed 3213#endif
1da177e4
LT		 3214
3215 if(unlikely(!icr))
3216 return IRQ_NONE; /* Not our interrupt */
3217
3218 if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
3219 hw->get_link_status = 1;
3220 mod_timer(&adapter->watchdog_timer, jiffies);
3221 }
3222
3223#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3224 atomic_inc(&adapter->irq_sem);
3225 E1000_WRITE_REG(hw, IMC, ~0);
3226 E1000_WRITE_FLUSH(hw);
24025e4e
MC		 3227#ifdef CONFIG_E1000_MQ
3228 if (atomic_read(&adapter->rx_sched_call_data.count) == 0) {
f56799ea
JK		 3229 /* We must setup the cpumask once count == 0 since
3230 * each cpu bit is cleared when the work is done. */
3231 adapter->rx_sched_call_data.cpumask = adapter->cpumask;
3232 atomic_add(adapter->num_rx_queues - 1, &adapter->irq_sem);
3233 atomic_set(&adapter->rx_sched_call_data.count,
3234 adapter->num_rx_queues);
24025e4e
MC		 3235 smp_call_async_mask(&adapter->rx_sched_call_data);
3236 } else {
3237 printk("call_data.count == %u\n", atomic_read(&adapter->rx_sched_call_data.count));
1da177e4 3238 }
be2b28ed 3239#else /* if !CONFIG_E1000_MQ */
581d708e
MC		 3240 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
3241 __netif_rx_schedule(&adapter->polling_netdev[0]);
3242 else
3243 e1000_irq_enable(adapter);
be2b28ed
JG		 3244#endif /* CONFIG_E1000_MQ */
3245
3246#else /* if !CONFIG_E1000_NAPI */
1da177e4
LT		 3247 /* Writing IMC and IMS is needed for 82547.
3248 Due to Hub Link bus being occupied, an interrupt
3249 de-assertion message is not able to be sent.
3250 When an interrupt assertion message is generated later,
3251 two messages are re-ordered and sent out.
3252 That causes APIC to think 82547 is in de-assertion
3253 state, while 82547 is in assertion state, resulting
3254 in dead lock. Writing IMC forces 82547 into
3255 de-assertion state.
3256 */
3257 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){
3258 atomic_inc(&adapter->irq_sem);
2648345f 3259 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3260 }
3261
3262 for(i = 0; i < E1000_MAX_INTR; i++)
581d708e
MC		 3263 if(unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
3264 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3265 break;
3266
3267 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
3268 e1000_irq_enable(adapter);
581d708e 3269
be2b28ed 3270#endif /* CONFIG_E1000_NAPI */
1da177e4
LT		 3271
3272 return IRQ_HANDLED;
3273}
3274
3275#ifdef CONFIG_E1000_NAPI
3276/**
3277 * e1000_clean - NAPI Rx polling callback
3278 * @adapter: board private structure
3279 **/
3280
3281static int
581d708e 3282e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3283{
581d708e
MC		 3284 struct e1000_adapter *adapter;
3285 int work_to_do = min(*budget, poll_dev->quota);
3286 int tx_cleaned, i = 0, work_done = 0;
3287
3288 /* Must NOT use netdev_priv macro here. */
3289 adapter = poll_dev->priv;
3290
3291 /* Keep link state information with original netdev */
3292 if (!netif_carrier_ok(adapter->netdev))
3293 goto quit_polling;
2648345f 3294
581d708e
MC		 3295 while (poll_dev != &adapter->polling_netdev[i]) {
3296 i++;
f56799ea 3297 if (unlikely(i == adapter->num_rx_queues))
581d708e
MC		 3298 BUG();
3299 }
3300
3301 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3302 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3303 &work_done, work_to_do);
1da177e4
LT		 3304
3305 *budget -= work_done;
581d708e 3306 poll_dev->quota -= work_done;
1da177e4 3307
2b02893e 3308 /* If no Tx and not enough Rx work done, exit the polling mode */
581d708e
MC		 3309 if((!tx_cleaned && (work_done == 0)) ||
3310 !netif_running(adapter->netdev)) {
3311quit_polling:
3312 netif_rx_complete(poll_dev);
1da177e4
LT		 3313 e1000_irq_enable(adapter);
3314 return 0;
3315 }
3316
3317 return 1;
3318}
3319
3320#endif
3321/**
3322 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3323 * @adapter: board private structure
3324 **/
3325
3326static boolean_t
581d708e
MC		 3327e1000_clean_tx_irq(struct e1000_adapter *adapter,
3328 struct e1000_tx_ring *tx_ring)
1da177e4 3329{
1da177e4
LT		 3330 struct net_device *netdev = adapter->netdev;
3331 struct e1000_tx_desc *tx_desc, *eop_desc;
3332 struct e1000_buffer *buffer_info;
3333 unsigned int i, eop;
3334 boolean_t cleaned = FALSE;
3335
3336 i = tx_ring->next_to_clean;
3337 eop = tx_ring->buffer_info[i].next_to_watch;
3338 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3339
581d708e 3340 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
1da177e4
LT		 3341 for(cleaned = FALSE; !cleaned; ) {
3342 tx_desc = E1000_TX_DESC(*tx_ring, i);
3343 buffer_info = &tx_ring->buffer_info[i];
3344 cleaned = (i == eop);
3345
fd803241 3346 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1da177e4
LT		 3347
3348 tx_desc->buffer_addr = 0;
3349 tx_desc->lower.data = 0;
3350 tx_desc->upper.data = 0;
3351
1da177e4
LT		 3352 if(unlikely(++i == tx_ring->count)) i = 0;
3353 }
581d708e 3354
7bfa4816
JK		 3355#ifdef CONFIG_E1000_MQ
3356 tx_ring->tx_stats.packets++;
3357#endif
3358
1da177e4
LT		 3359 eop = tx_ring->buffer_info[i].next_to_watch;
3360 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3361 }
3362
3363 tx_ring->next_to_clean = i;
3364
581d708e 3365 spin_lock(&tx_ring->tx_lock);
1da177e4
LT		 3366
3367 if(unlikely(cleaned && netif_queue_stopped(netdev) &&
3368 netif_carrier_ok(netdev)))
3369 netif_wake_queue(netdev);
3370
581d708e 3371 spin_unlock(&tx_ring->tx_lock);
2648345f 3372
581d708e 3373 if (adapter->detect_tx_hung) {
2648345f 3374 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3375 * check with the clearing of time_stamp and movement of i */
3376 adapter->detect_tx_hung = FALSE;
70b8f1e1
MC		 3377 if (tx_ring->buffer_info[i].dma &&
3378 time_after(jiffies, tx_ring->buffer_info[i].time_stamp + HZ)
3379 && !(E1000_READ_REG(&adapter->hw, STATUS) &
3380 E1000_STATUS_TXOFF)) {
3381
3382 /* detected Tx unit hang */
3383 i = tx_ring->next_to_clean;
3384 eop = tx_ring->buffer_info[i].next_to_watch;
3385 eop_desc = E1000_TX_DESC(*tx_ring, eop);
c6963ef5 3386 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3387 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3388 " TDH <%x>\n"
3389 " TDT <%x>\n"
3390 " next_to_use <%x>\n"
3391 " next_to_clean <%x>\n"
3392 "buffer_info[next_to_clean]\n"
b4ee21f4 3393 " dma <%llx>\n"
70b8f1e1
MC		 3394 " time_stamp <%lx>\n"
3395 " next_to_watch <%x>\n"
3396 " jiffies <%lx>\n"
3397 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3398 (unsigned long)((tx_ring - adapter->tx_ring) /
3399 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3400 readl(adapter->hw.hw_addr + tx_ring->tdh),
3401 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1
MC		 3402 tx_ring->next_to_use,
3403 i,
b4ee21f4 3404 (unsigned long long)tx_ring->buffer_info[i].dma,
70b8f1e1
MC		 3405 tx_ring->buffer_info[i].time_stamp,
3406 eop,
3407 jiffies,
3408 eop_desc->upper.fields.status);
1da177e4 3409 netif_stop_queue(netdev);
70b8f1e1 3410 }
1da177e4 3411 }
1da177e4
LT		 3412 return cleaned;
3413}
3414
3415/**
3416 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3417 * @adapter: board private structure
3418 * @status_err: receive descriptor status and error fields
3419 * @csum: receive descriptor csum field
3420 * @sk_buff: socket buffer with received data
1da177e4
LT		 3421 **/
3422
3423static inline void
3424e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3425 uint32_t status_err, uint32_t csum,
3426 struct sk_buff *skb)
1da177e4 3427{
2d7edb92
MC		 3428 uint16_t status = (uint16_t)status_err;
3429 uint8_t errors = (uint8_t)(status_err >> 24);
3430 skb->ip_summed = CHECKSUM_NONE;
3431
1da177e4 3432 /* 82543 or newer only */
2d7edb92 3433 if(unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3434 /* Ignore Checksum bit is set */
2d7edb92
MC		 3435 if(unlikely(status & E1000_RXD_STAT_IXSM)) return;
3436 /* TCP/UDP checksum error bit is set */
3437 if(unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3438 /* let the stack verify checksum errors */
1da177e4 3439 adapter->hw_csum_err++;
2d7edb92
MC		 3440 return;
3441 }
3442 /* TCP/UDP Checksum has not been calculated */
3443 if(adapter->hw.mac_type <= e1000_82547_rev_2) {
3444 if(!(status & E1000_RXD_STAT_TCPCS))
3445 return;
1da177e4 3446 } else {
2d7edb92
MC		 3447 if(!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
3448 return;
3449 }
3450 /* It must be a TCP or UDP packet with a valid checksum */
3451 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3452 /* TCP checksum is good */
3453 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3454 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3455 /* IP fragment with UDP payload */
3456 /* Hardware complements the payload checksum, so we undo it
3457 * and then put the value in host order for further stack use.
3458 */
3459 csum = ntohl(csum ^ 0xFFFF);
3460 skb->csum = csum;
3461 skb->ip_summed = CHECKSUM_HW;
1da177e4 3462 }
2d7edb92 3463 adapter->hw_csum_good++;
1da177e4
LT		 3464}
3465
3466/**
2d7edb92 3467 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3468 * @adapter: board private structure
3469 **/
3470
3471static boolean_t
3472#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3473e1000_clean_rx_irq(struct e1000_adapter *adapter,
3474 struct e1000_rx_ring *rx_ring,
3475 int *work_done, int work_to_do)
1da177e4 3476#else
581d708e
MC		 3477e1000_clean_rx_irq(struct e1000_adapter *adapter,
3478 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3479#endif
3480{
1da177e4
LT		 3481 struct net_device *netdev = adapter->netdev;
3482 struct pci_dev *pdev = adapter->pdev;
3483 struct e1000_rx_desc *rx_desc;
3484 struct e1000_buffer *buffer_info;
3485 struct sk_buff *skb;
3486 unsigned long flags;
3487 uint32_t length;
3488 uint8_t last_byte;
3489 unsigned int i;
3490 boolean_t cleaned = FALSE;
3491
3492 i = rx_ring->next_to_clean;
3493 rx_desc = E1000_RX_DESC(*rx_ring, i);
3494
3495 while(rx_desc->status & E1000_RXD_STAT_DD) {
3496 buffer_info = &rx_ring->buffer_info[i];
3497#ifdef CONFIG_E1000_NAPI
3498 if(*work_done >= work_to_do)
3499 break;
3500 (*work_done)++;
3501#endif
3502 cleaned = TRUE;
3503
3504 pci_unmap_single(pdev,
3505 buffer_info->dma,
3506 buffer_info->length,
3507 PCI_DMA_FROMDEVICE);
3508
3509 skb = buffer_info->skb;
3510 length = le16_to_cpu(rx_desc->length);
3511
3512 if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) {
3513 /* All receives must fit into a single buffer */
3514 E1000_DBG("%s: Receive packet consumed multiple"
2648345f 3515 " buffers\n", netdev->name);
1da177e4
LT		 3516 dev_kfree_skb_irq(skb);
3517 goto next_desc;
3518 }
3519
3520 if(unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
3521 last_byte = *(skb->data + length - 1);
3522 if(TBI_ACCEPT(&adapter->hw, rx_desc->status,
3523 rx_desc->errors, length, last_byte)) {
3524 spin_lock_irqsave(&adapter->stats_lock, flags);
3525 e1000_tbi_adjust_stats(&adapter->hw,
3526 &adapter->stats,
3527 length, skb->data);
3528 spin_unlock_irqrestore(&adapter->stats_lock,
3529 flags);
3530 length--;
3531 } else {
3532 dev_kfree_skb_irq(skb);
3533 goto next_desc;
3534 }
3535 }
3536
3537 /* Good Receive */
3538 skb_put(skb, length - ETHERNET_FCS_SIZE);
3539
3540 /* Receive Checksum Offload */
2d7edb92
MC		 3541 e1000_rx_checksum(adapter,
3542 (uint32_t)(rx_desc->status) |
3543 ((uint32_t)(rx_desc->errors) << 24),
3544 rx_desc->csum, skb);
1da177e4
LT		 3545 skb->protocol = eth_type_trans(skb, netdev);
3546#ifdef CONFIG_E1000_NAPI
3547 if(unlikely(adapter->vlgrp &&
3548 (rx_desc->status & E1000_RXD_STAT_VP))) {
3549 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3550 le16_to_cpu(rx_desc->special) &
3551 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3552 } else {
3553 netif_receive_skb(skb);
3554 }
3555#else /* CONFIG_E1000_NAPI */
3556 if(unlikely(adapter->vlgrp &&
3557 (rx_desc->status & E1000_RXD_STAT_VP))) {
3558 vlan_hwaccel_rx(skb, adapter->vlgrp,
3559 le16_to_cpu(rx_desc->special) &
3560 E1000_RXD_SPC_VLAN_MASK);
3561 } else {
3562 netif_rx(skb);
3563 }
3564#endif /* CONFIG_E1000_NAPI */
3565 netdev->last_rx = jiffies;
7bfa4816
JK		 3566#ifdef CONFIG_E1000_MQ
3567 rx_ring->rx_stats.packets++;
3568 rx_ring->rx_stats.bytes += length;
3569#endif
1da177e4
LT		 3570
3571next_desc:
3572 rx_desc->status = 0;
3573 buffer_info->skb = NULL;
3574 if(unlikely(++i == rx_ring->count)) i = 0;
3575
3576 rx_desc = E1000_RX_DESC(*rx_ring, i);
3577 }
1da177e4 3578 rx_ring->next_to_clean = i;
581d708e 3579 adapter->alloc_rx_buf(adapter, rx_ring);
2d7edb92
MC		 3580
3581 return cleaned;
3582}
3583
3584/**
3585 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3586 * @adapter: board private structure
3587 **/
3588
3589static boolean_t
3590#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3591e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3592 struct e1000_rx_ring *rx_ring,
3593 int *work_done, int work_to_do)
2d7edb92 3594#else
581d708e
MC		 3595e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3596 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3597#endif
3598{
2d7edb92
MC		 3599 union e1000_rx_desc_packet_split *rx_desc;
3600 struct net_device *netdev = adapter->netdev;
3601 struct pci_dev *pdev = adapter->pdev;
3602 struct e1000_buffer *buffer_info;
3603 struct e1000_ps_page *ps_page;
3604 struct e1000_ps_page_dma *ps_page_dma;
3605 struct sk_buff *skb;
3606 unsigned int i, j;
3607 uint32_t length, staterr;
3608 boolean_t cleaned = FALSE;
3609
3610 i = rx_ring->next_to_clean;
3611 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3612 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3613
3614 while(staterr & E1000_RXD_STAT_DD) {
3615 buffer_info = &rx_ring->buffer_info[i];
3616 ps_page = &rx_ring->ps_page[i];
3617 ps_page_dma = &rx_ring->ps_page_dma[i];
3618#ifdef CONFIG_E1000_NAPI
3619 if(unlikely(*work_done >= work_to_do))
3620 break;
3621 (*work_done)++;
3622#endif
3623 cleaned = TRUE;
3624 pci_unmap_single(pdev, buffer_info->dma,
3625 buffer_info->length,
3626 PCI_DMA_FROMDEVICE);
3627
3628 skb = buffer_info->skb;
3629
3630 if(unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
3631 E1000_DBG("%s: Packet Split buffers didn't pick up"
3632 " the full packet\n", netdev->name);
3633 dev_kfree_skb_irq(skb);
3634 goto next_desc;
3635 }
1da177e4 3636
2d7edb92
MC		 3637 if(unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3638 dev_kfree_skb_irq(skb);
3639 goto next_desc;
3640 }
3641
3642 length = le16_to_cpu(rx_desc->wb.middle.length0);
3643
3644 if(unlikely(!length)) {
3645 E1000_DBG("%s: Last part of the packet spanning"
3646 " multiple descriptors\n", netdev->name);
3647 dev_kfree_skb_irq(skb);
3648 goto next_desc;
3649 }
3650
3651 /* Good Receive */
3652 skb_put(skb, length);
3653
e4c811c9 3654 for(j = 0; j < adapter->rx_ps_pages; j++) {
2d7edb92
MC		 3655 if(!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
3656 break;
3657
3658 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3659 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3660 ps_page_dma->ps_page_dma[j] = 0;
3661 skb_shinfo(skb)->frags[j].page =
3662 ps_page->ps_page[j];
3663 ps_page->ps_page[j] = NULL;
3664 skb_shinfo(skb)->frags[j].page_offset = 0;
3665 skb_shinfo(skb)->frags[j].size = length;
3666 skb_shinfo(skb)->nr_frags++;
3667 skb->len += length;
3668 skb->data_len += length;
3669 }
3670
3671 e1000_rx_checksum(adapter, staterr,
3672 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
3673 skb->protocol = eth_type_trans(skb, netdev);
3674
2d7edb92 3675 if(likely(rx_desc->wb.upper.header_status &
e4c811c9
MC		 3676 E1000_RXDPS_HDRSTAT_HDRSP)) {
3677 adapter->rx_hdr_split++;
3678#ifdef HAVE_RX_ZERO_COPY
2d7edb92
MC		 3679 skb_shinfo(skb)->zero_copy = TRUE;
3680#endif
e4c811c9 3681 }
2d7edb92
MC		 3682#ifdef CONFIG_E1000_NAPI
3683 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3684 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3685 le16_to_cpu(rx_desc->wb.middle.vlan) &
3686 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3687 } else {
3688 netif_receive_skb(skb);
3689 }
3690#else /* CONFIG_E1000_NAPI */
3691 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3692 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3693 le16_to_cpu(rx_desc->wb.middle.vlan) &
3694 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3695 } else {
3696 netif_rx(skb);
3697 }
3698#endif /* CONFIG_E1000_NAPI */
3699 netdev->last_rx = jiffies;
7bfa4816
JK		 3700#ifdef CONFIG_E1000_MQ
3701 rx_ring->rx_stats.packets++;
3702 rx_ring->rx_stats.bytes += length;
3703#endif
2d7edb92
MC		 3704
3705next_desc:
3706 rx_desc->wb.middle.status_error &= ~0xFF;
3707 buffer_info->skb = NULL;
3708 if(unlikely(++i == rx_ring->count)) i = 0;
3709
3710 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3711 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3712 }
3713 rx_ring->next_to_clean = i;
581d708e 3714 adapter->alloc_rx_buf(adapter, rx_ring);
1da177e4
LT		 3715
3716 return cleaned;
3717}
3718
3719/**
2d7edb92 3720 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3721 * @adapter: address of board private structure
3722 **/
3723
3724static void
581d708e
MC		 3725e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3726 struct e1000_rx_ring *rx_ring)
1da177e4 3727{
1da177e4
LT		 3728 struct net_device *netdev = adapter->netdev;
3729 struct pci_dev *pdev = adapter->pdev;
3730 struct e1000_rx_desc *rx_desc;
3731 struct e1000_buffer *buffer_info;
3732 struct sk_buff *skb;
2648345f
MC		 3733 unsigned int i;
3734 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3735
3736 i = rx_ring->next_to_use;
3737 buffer_info = &rx_ring->buffer_info[i];
3738
3739 while(!buffer_info->skb) {
1da177e4 3740 skb = dev_alloc_skb(bufsz);
2648345f 3741
1da177e4
LT		 3742 if(unlikely(!skb)) {
3743 /* Better luck next round */
3744 break;
3745 }
3746
2648345f 3747 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3748 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3749 struct sk_buff *oldskb = skb;
2648345f
MC		 3750 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3751 "at %p\n", bufsz, skb->data);
3752 /* Try again, without freeing the previous */
1da177e4 3753 skb = dev_alloc_skb(bufsz);
2648345f 3754 /* Failed allocation, critical failure */
1da177e4
LT		 3755 if (!skb) {
3756 dev_kfree_skb(oldskb);
3757 break;
3758 }
2648345f 3759
1da177e4
LT		 3760 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3761 /* give up */
3762 dev_kfree_skb(skb);
3763 dev_kfree_skb(oldskb);
3764 break; /* while !buffer_info->skb */
3765 } else {
2648345f 3766 /* Use new allocation */
1da177e4
LT		 3767 dev_kfree_skb(oldskb);
3768 }
3769 }
1da177e4
LT		 3770 /* Make buffer alignment 2 beyond a 16 byte boundary
3771 * this will result in a 16 byte aligned IP header after
3772 * the 14 byte MAC header is removed
3773 */
3774 skb_reserve(skb, NET_IP_ALIGN);
3775
3776 skb->dev = netdev;
3777
3778 buffer_info->skb = skb;
3779 buffer_info->length = adapter->rx_buffer_len;
3780 buffer_info->dma = pci_map_single(pdev,
3781 skb->data,
3782 adapter->rx_buffer_len,
3783 PCI_DMA_FROMDEVICE);
3784
2648345f
MC		 3785 /* Fix for errata 23, can't cross 64kB boundary */
3786 if (!e1000_check_64k_bound(adapter,
3787 (void *)(unsigned long)buffer_info->dma,
3788 adapter->rx_buffer_len)) {
3789 DPRINTK(RX_ERR, ERR,
3790 "dma align check failed: %u bytes at %p\n",
3791 adapter->rx_buffer_len,
3792 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 3793 dev_kfree_skb(skb);
3794 buffer_info->skb = NULL;
3795
2648345f 3796 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 3797 adapter->rx_buffer_len,
3798 PCI_DMA_FROMDEVICE);
3799
3800 break; /* while !buffer_info->skb */
3801 }
1da177e4
LT		 3802 rx_desc = E1000_RX_DESC(*rx_ring, i);
3803 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3804
3805 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3806 /* Force memory writes to complete before letting h/w
3807 * know there are new descriptors to fetch. (Only
3808 * applicable for weak-ordered memory model archs,
3809 * such as IA-64). */
3810 wmb();
581d708e 3811 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
1da177e4
LT		 3812 }
3813
3814 if(unlikely(++i == rx_ring->count)) i = 0;
3815 buffer_info = &rx_ring->buffer_info[i];
3816 }
3817
3818 rx_ring->next_to_use = i;
3819}
3820
2d7edb92
MC		 3821/**
3822 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3823 * @adapter: address of board private structure
3824 **/
3825
3826static void
581d708e
MC		 3827e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
3828 struct e1000_rx_ring *rx_ring)
2d7edb92 3829{
2d7edb92
MC		 3830 struct net_device *netdev = adapter->netdev;
3831 struct pci_dev *pdev = adapter->pdev;
3832 union e1000_rx_desc_packet_split *rx_desc;
3833 struct e1000_buffer *buffer_info;
3834 struct e1000_ps_page *ps_page;
3835 struct e1000_ps_page_dma *ps_page_dma;
3836 struct sk_buff *skb;
3837 unsigned int i, j;
3838
3839 i = rx_ring->next_to_use;
3840 buffer_info = &rx_ring->buffer_info[i];
3841 ps_page = &rx_ring->ps_page[i];
3842 ps_page_dma = &rx_ring->ps_page_dma[i];
3843
3844 while(!buffer_info->skb) {
3845 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3846
3847 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 3848 if (j < adapter->rx_ps_pages) {
3849 if (likely(!ps_page->ps_page[j])) {
3850 ps_page->ps_page[j] =
3851 alloc_page(GFP_ATOMIC);
3852 if (unlikely(!ps_page->ps_page[j]))
3853 goto no_buffers;
3854 ps_page_dma->ps_page_dma[j] =
3855 pci_map_page(pdev,
3856 ps_page->ps_page[j],
3857 0, PAGE_SIZE,
3858 PCI_DMA_FROMDEVICE);
3859 }
3860 /* Refresh the desc even if buffer_addrs didn't
3861 * change because each write-back erases
3862 * this info.
3863 */
3864 rx_desc->read.buffer_addr[j+1] =
3865 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
3866 } else
3867 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 3868 }
3869
3870 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3871
3872 if(unlikely(!skb))
3873 break;
3874
3875 /* Make buffer alignment 2 beyond a 16 byte boundary
3876 * this will result in a 16 byte aligned IP header after
3877 * the 14 byte MAC header is removed
3878 */
3879 skb_reserve(skb, NET_IP_ALIGN);
3880
3881 skb->dev = netdev;
3882
3883 buffer_info->skb = skb;
3884 buffer_info->length = adapter->rx_ps_bsize0;
3885 buffer_info->dma = pci_map_single(pdev, skb->data,
3886 adapter->rx_ps_bsize0,
3887 PCI_DMA_FROMDEVICE);
3888
3889 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
3890
3891 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3892 /* Force memory writes to complete before letting h/w
3893 * know there are new descriptors to fetch. (Only
3894 * applicable for weak-ordered memory model archs,
3895 * such as IA-64). */
3896 wmb();
3897 /* Hardware increments by 16 bytes, but packet split
3898 * descriptors are 32 bytes...so we increment tail
3899 * twice as much.
3900 */
581d708e 3901 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
2d7edb92
MC		 3902 }
3903
3904 if(unlikely(++i == rx_ring->count)) i = 0;
3905 buffer_info = &rx_ring->buffer_info[i];
3906 ps_page = &rx_ring->ps_page[i];
3907 ps_page_dma = &rx_ring->ps_page_dma[i];
3908 }
3909
3910no_buffers:
3911 rx_ring->next_to_use = i;
3912}
3913
1da177e4
LT		 3914/**
3915 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
3916 * @adapter:
3917 **/
3918
3919static void
3920e1000_smartspeed(struct e1000_adapter *adapter)
3921{
3922 uint16_t phy_status;
3923 uint16_t phy_ctrl;
3924
3925 if((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
3926 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
3927 return;
3928
3929 if(adapter->smartspeed == 0) {
3930 /* If Master/Slave config fault is asserted twice,
3931 * we assume back-to-back */
3932 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
3933 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
3934 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
3935 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
3936 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
3937 if(phy_ctrl & CR_1000T_MS_ENABLE) {
3938 phy_ctrl &= ~CR_1000T_MS_ENABLE;
3939 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
3940 phy_ctrl);
3941 adapter->smartspeed++;
3942 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
3943 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
3944 &phy_ctrl)) {
3945 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
3946 MII_CR_RESTART_AUTO_NEG);
3947 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
3948 phy_ctrl);
3949 }
3950 }
3951 return;
3952 } else if(adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
3953 /* If still no link, perhaps using 2/3 pair cable */
3954 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
3955 phy_ctrl |= CR_1000T_MS_ENABLE;
3956 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
3957 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
3958 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
3959 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
3960 MII_CR_RESTART_AUTO_NEG);
3961 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
3962 }
3963 }
3964 /* Restart process after E1000_SMARTSPEED_MAX iterations */
3965 if(adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
3966 adapter->smartspeed = 0;
3967}
3968
3969/**
3970 * e1000_ioctl -
3971 * @netdev:
3972 * @ifreq:
3973 * @cmd:
3974 **/
3975
3976static int
3977e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3978{
3979 switch (cmd) {
3980 case SIOCGMIIPHY:
3981 case SIOCGMIIREG:
3982 case SIOCSMIIREG:
3983 return e1000_mii_ioctl(netdev, ifr, cmd);
3984 default:
3985 return -EOPNOTSUPP;
3986 }
3987}
3988
3989/**
3990 * e1000_mii_ioctl -
3991 * @netdev:
3992 * @ifreq:
3993 * @cmd:
3994 **/
3995
3996static int
3997e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3998{
60490fe0 3999 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4000 struct mii_ioctl_data *data = if_mii(ifr);
4001 int retval;
4002 uint16_t mii_reg;
4003 uint16_t spddplx;
97876fc6 4004 unsigned long flags;
1da177e4
LT		 4005
4006 if(adapter->hw.media_type != e1000_media_type_copper)
4007 return -EOPNOTSUPP;
4008
4009 switch (cmd) {
4010 case SIOCGMIIPHY:
4011 data->phy_id = adapter->hw.phy_addr;
4012 break;
4013 case SIOCGMIIREG:
97876fc6 4014 if(!capable(CAP_NET_ADMIN))
1da177e4 4015 return -EPERM;
97876fc6
MC		 4016 spin_lock_irqsave(&adapter->stats_lock, flags);
4017 if(e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4018 &data->val_out)) {
4019 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4020 return -EIO;
97876fc6
MC		 4021 }
4022 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4023 break;
4024 case SIOCSMIIREG:
97876fc6 4025 if(!capable(CAP_NET_ADMIN))
1da177e4 4026 return -EPERM;
97876fc6 4027 if(data->reg_num & ~(0x1F))
1da177e4
LT		 4028 return -EFAULT;
4029 mii_reg = data->val_in;
97876fc6
MC		 4030 spin_lock_irqsave(&adapter->stats_lock, flags);
4031 if(e1000_write_phy_reg(&adapter->hw, data->reg_num,
4032 mii_reg)) {
4033 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4034 return -EIO;
97876fc6
MC		 4035 }
4036 if(adapter->hw.phy_type == e1000_phy_m88) {
1da177e4
LT		 4037 switch (data->reg_num) {
4038 case PHY_CTRL:
4039 if(mii_reg & MII_CR_POWER_DOWN)
4040 break;
4041 if(mii_reg & MII_CR_AUTO_NEG_EN) {
4042 adapter->hw.autoneg = 1;
4043 adapter->hw.autoneg_advertised = 0x2F;
4044 } else {
4045 if (mii_reg & 0x40)
4046 spddplx = SPEED_1000;
4047 else if (mii_reg & 0x2000)
4048 spddplx = SPEED_100;
4049 else
4050 spddplx = SPEED_10;
4051 spddplx += (mii_reg & 0x100)
4052 ? FULL_DUPLEX :
4053 HALF_DUPLEX;
4054 retval = e1000_set_spd_dplx(adapter,
4055 spddplx);
97876fc6
MC		 4056 if(retval) {
4057 spin_unlock_irqrestore(
4058 &adapter->stats_lock,
4059 flags);
1da177e4 4060 return retval;
97876fc6 4061 }
1da177e4
LT		 4062 }
4063 if(netif_running(adapter->netdev)) {
4064 e1000_down(adapter);
4065 e1000_up(adapter);
4066 } else
4067 e1000_reset(adapter);
4068 break;
4069 case M88E1000_PHY_SPEC_CTRL:
4070 case M88E1000_EXT_PHY_SPEC_CTRL:
97876fc6
MC		 4071 if(e1000_phy_reset(&adapter->hw)) {
4072 spin_unlock_irqrestore(
4073 &adapter->stats_lock, flags);
1da177e4 4074 return -EIO;
97876fc6 4075 }
1da177e4
LT		 4076 break;
4077 }
4078 } else {
4079 switch (data->reg_num) {
4080 case PHY_CTRL:
4081 if(mii_reg & MII_CR_POWER_DOWN)
4082 break;
4083 if(netif_running(adapter->netdev)) {
4084 e1000_down(adapter);
4085 e1000_up(adapter);
4086 } else
4087 e1000_reset(adapter);
4088 break;
4089 }
4090 }
97876fc6 4091 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4092 break;
4093 default:
4094 return -EOPNOTSUPP;
4095 }
4096 return E1000_SUCCESS;
4097}
4098
4099void
4100e1000_pci_set_mwi(struct e1000_hw *hw)
4101{
4102 struct e1000_adapter *adapter = hw->back;
2648345f 4103 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4104
2648345f
MC		 4105 if(ret_val)
4106 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4107}
4108
4109void
4110e1000_pci_clear_mwi(struct e1000_hw *hw)
4111{
4112 struct e1000_adapter *adapter = hw->back;
4113
4114 pci_clear_mwi(adapter->pdev);
4115}
4116
4117void
4118e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4119{
4120 struct e1000_adapter *adapter = hw->back;
4121
4122 pci_read_config_word(adapter->pdev, reg, value);
4123}
4124
4125void
4126e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4127{
4128 struct e1000_adapter *adapter = hw->back;
4129
4130 pci_write_config_word(adapter->pdev, reg, *value);
4131}
4132
4133uint32_t
4134e1000_io_read(struct e1000_hw *hw, unsigned long port)
4135{
4136 return inl(port);
4137}
4138
4139void
4140e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4141{
4142 outl(value, port);
4143}
4144
4145static void
4146e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4147{
60490fe0 4148 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4149 uint32_t ctrl, rctl;
4150
4151 e1000_irq_disable(adapter);
4152 adapter->vlgrp = grp;
4153
4154 if(grp) {
4155 /* enable VLAN tag insert/strip */
4156 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4157 ctrl |= E1000_CTRL_VME;
4158 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4159
4160 /* enable VLAN receive filtering */
4161 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4162 rctl |= E1000_RCTL_VFE;
4163 rctl &= ~E1000_RCTL_CFIEN;
4164 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4165 e1000_update_mng_vlan(adapter);
1da177e4
LT		 4166 } else {
4167 /* disable VLAN tag insert/strip */
4168 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4169 ctrl &= ~E1000_CTRL_VME;
4170 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4171
4172 /* disable VLAN filtering */
4173 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4174 rctl &= ~E1000_RCTL_VFE;
4175 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92
MC		 4176 if(adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
4177 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4178 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4179 }
1da177e4
LT		 4180 }
4181
4182 e1000_irq_enable(adapter);
4183}
4184
4185static void
4186e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4187{
60490fe0 4188 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4189 uint32_t vfta, index;
2d7edb92
MC		 4190 if((adapter->hw.mng_cookie.status &
4191 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4192 (vid == adapter->mng_vlan_id))
4193 return;
1da177e4
LT		 4194 /* add VID to filter table */
4195 index = (vid >> 5) & 0x7F;
4196 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4197 vfta |= (1 << (vid & 0x1F));
4198 e1000_write_vfta(&adapter->hw, index, vfta);
4199}
4200
4201static void
4202e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4203{
60490fe0 4204 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4205 uint32_t vfta, index;
4206
4207 e1000_irq_disable(adapter);
4208
4209 if(adapter->vlgrp)
4210 adapter->vlgrp->vlan_devices[vid] = NULL;
4211
4212 e1000_irq_enable(adapter);
4213
2d7edb92
MC		 4214 if((adapter->hw.mng_cookie.status &
4215 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4216 (vid == adapter->mng_vlan_id))
4217 return;
1da177e4
LT		 4218 /* remove VID from filter table */
4219 index = (vid >> 5) & 0x7F;
4220 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4221 vfta &= ~(1 << (vid & 0x1F));
4222 e1000_write_vfta(&adapter->hw, index, vfta);
4223}
4224
4225static void
4226e1000_restore_vlan(struct e1000_adapter *adapter)
4227{
4228 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4229
4230 if(adapter->vlgrp) {
4231 uint16_t vid;
4232 for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4233 if(!adapter->vlgrp->vlan_devices[vid])
4234 continue;
4235 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4236 }
4237 }
4238}
4239
4240int
4241e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4242{
4243 adapter->hw.autoneg = 0;
4244
6921368f
MC		 4245 /* Fiber NICs only allow 1000 gbps Full duplex */
4246 if((adapter->hw.media_type == e1000_media_type_fiber) &&
4247 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4248 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4249 return -EINVAL;
4250 }
4251
1da177e4
LT		 4252 switch(spddplx) {
4253 case SPEED_10 + DUPLEX_HALF:
4254 adapter->hw.forced_speed_duplex = e1000_10_half;
4255 break;
4256 case SPEED_10 + DUPLEX_FULL:
4257 adapter->hw.forced_speed_duplex = e1000_10_full;
4258 break;
4259 case SPEED_100 + DUPLEX_HALF:
4260 adapter->hw.forced_speed_duplex = e1000_100_half;
4261 break;
4262 case SPEED_100 + DUPLEX_FULL:
4263 adapter->hw.forced_speed_duplex = e1000_100_full;
4264 break;
4265 case SPEED_1000 + DUPLEX_FULL:
4266 adapter->hw.autoneg = 1;
4267 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4268 break;
4269 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4270 default:
2648345f 4271 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4272 return -EINVAL;
4273 }
4274 return 0;
4275}
4276
b6a1d5f8 4277#ifdef CONFIG_PM
1da177e4 4278static int
829ca9a3 4279e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4280{
4281 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4282 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4283 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4
LT		 4284 uint32_t wufc = adapter->wol;
4285
4286 netif_device_detach(netdev);
4287
4288 if(netif_running(netdev))
4289 e1000_down(adapter);
4290
4291 status = E1000_READ_REG(&adapter->hw, STATUS);
4292 if(status & E1000_STATUS_LU)
4293 wufc &= ~E1000_WUFC_LNKC;
4294
4295 if(wufc) {
4296 e1000_setup_rctl(adapter);
4297 e1000_set_multi(netdev);
4298
4299 /* turn on all-multi mode if wake on multicast is enabled */
4300 if(adapter->wol & E1000_WUFC_MC) {
4301 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4302 rctl |= E1000_RCTL_MPE;
4303 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4304 }
4305
4306 if(adapter->hw.mac_type >= e1000_82540) {
4307 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4308 /* advertise wake from D3Cold */
4309 #define E1000_CTRL_ADVD3WUC 0x00100000
4310 /* phy power management enable */
4311 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4312 ctrl |= E1000_CTRL_ADVD3WUC |
4313 E1000_CTRL_EN_PHY_PWR_MGMT;
4314 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4315 }
4316
4317 if(adapter->hw.media_type == e1000_media_type_fiber ||
4318 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4319 /* keep the laser running in D3 */
4320 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4321 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4322 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4323 }
4324
2d7edb92
MC		 4325 /* Allow time for pending master requests to run */
4326 e1000_disable_pciex_master(&adapter->hw);
4327
1da177e4
LT		 4328 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4329 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
4330 pci_enable_wake(pdev, 3, 1);
4331 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
4332 } else {
4333 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4334 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
4335 pci_enable_wake(pdev, 3, 0);
4336 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
4337 }
4338
4339 pci_save_state(pdev);
4340
4341 if(adapter->hw.mac_type >= e1000_82540 &&
4342 adapter->hw.media_type == e1000_media_type_copper) {
4343 manc = E1000_READ_REG(&adapter->hw, MANC);
4344 if(manc & E1000_MANC_SMBUS_EN) {
4345 manc |= E1000_MANC_ARP_EN;
4346 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4347 pci_enable_wake(pdev, 3, 1);
4348 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
4349 }
4350 }
4351
b55ccb35
JK		 4352 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4353 * would have already happened in close and is redundant. */
4354 e1000_release_hw_control(adapter);
2d7edb92 4355
1da177e4 4356 pci_disable_device(pdev);
829ca9a3 4357 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4358
4359 return 0;
4360}
4361
1da177e4
LT		 4362static int
4363e1000_resume(struct pci_dev *pdev)
4364{
4365 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4366 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4367 uint32_t manc, ret_val;
1da177e4 4368
829ca9a3 4369 pci_set_power_state(pdev, PCI_D0);
1da177e4 4370 pci_restore_state(pdev);
2b02893e 4371 ret_val = pci_enable_device(pdev);
a4cb847d 4372 pci_set_master(pdev);
1da177e4 4373
829ca9a3
PM		 4374 pci_enable_wake(pdev, PCI_D3hot, 0);
4375 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4376
4377 e1000_reset(adapter);
4378 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4379
4380 if(netif_running(netdev))
4381 e1000_up(adapter);
4382
4383 netif_device_attach(netdev);
4384
4385 if(adapter->hw.mac_type >= e1000_82540 &&
4386 adapter->hw.media_type == e1000_media_type_copper) {
4387 manc = E1000_READ_REG(&adapter->hw, MANC);
4388 manc &= ~(E1000_MANC_ARP_EN);
4389 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4390 }
4391
b55ccb35
JK		 4392 /* If the controller is 82573 and f/w is AMT, do not set
4393 * DRV_LOAD until the interface is up. For all other cases,
4394 * let the f/w know that the h/w is now under the control
4395 * of the driver. */
4396 if (adapter->hw.mac_type != e1000_82573 ||
4397 !e1000_check_mng_mode(&adapter->hw))
4398 e1000_get_hw_control(adapter);
2d7edb92 4399
1da177e4
LT		 4400 return 0;
4401}
4402#endif
1da177e4
LT		 4403#ifdef CONFIG_NET_POLL_CONTROLLER
4404/*
4405 * Polling 'interrupt' - used by things like netconsole to send skbs
4406 * without having to re-enable interrupts. It's not called while
4407 * the interrupt routine is executing.
4408 */
4409static void
2648345f 4410e1000_netpoll(struct net_device *netdev)
1da177e4 4411{
60490fe0 4412 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4413 disable_irq(adapter->pdev->irq);
4414 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4415 e1000_clean_tx_irq(adapter, adapter->tx_ring);
1da177e4
LT		 4416 enable_irq(adapter->pdev->irq);
4417}
4418#endif
4419
4420/* e1000_main.c */
Linux kernel - Deliverables
This page took 0.313688 seconds and 5 git commands to generate.