[deliverable/linux.git] / drivers / net / ethernet / apm / xgene / xgene_enet_xgmac.c

/* Applied Micro X-Gene SoC Ethernet Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Authors: Iyappan Subramanian <isubramanian@apm.com>
 *	    Keyur Chudgar <kchudgar@apm.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/of_gpio.h>
#include <linux/gpio.h>
#include "xgene_enet_main.h"
#include "xgene_enet_hw.h"
#include "xgene_enet_xgmac.h"

static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
			      u32 offset, u32 val)
{
	void __iomem *addr = pdata->eth_csr_addr + offset;

	iowrite32(val, addr);
}

static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
				  u32 offset, u32 val)
{
	void __iomem *addr = pdata->eth_ring_if_addr + offset;

	iowrite32(val, addr);
}

static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
				   u32 offset, u32 val)
{
	void __iomem *addr = pdata->eth_diag_csr_addr + offset;

	iowrite32(val, addr);
}

static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
				   void __iomem *cmd, void __iomem *cmd_done,
				   u32 wr_addr, u32 wr_data)
{
	u32 done;
	u8 wait = 10;

	iowrite32(wr_addr, addr);
	iowrite32(wr_data, wr);
	iowrite32(XGENE_ENET_WR_CMD, cmd);

	/* wait for write command to complete */
	while (!(done = ioread32(cmd_done)) && wait--)
		udelay(1);

	if (!done)
		return false;

	iowrite32(0, cmd);

	return true;
}

static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata,
			      u32 wr_addr, u32 wr_data)
{
	void __iomem *addr, *wr, *cmd, *cmd_done;

	addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
	wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
	cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
	cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;

	if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
		netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
			   wr_addr);
}

static void xgene_enet_wr_pcs(struct xgene_enet_pdata *pdata,
			      u32 wr_addr, u32 wr_data)
{
	void __iomem *addr, *wr, *cmd, *cmd_done;

	addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET;
	wr = pdata->pcs_addr + PCS_WRITE_REG_OFFSET;
	cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET;
	cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET;

	if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
		netdev_err(pdata->ndev, "PCS write failed, addr: %04x\n",
			   wr_addr);
}

static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
			      u32 offset, u32 *val)
{
	void __iomem *addr = pdata->eth_csr_addr + offset;

	*val = ioread32(addr);
}

static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
				   u32 offset, u32 *val)
{
	void __iomem *addr = pdata->eth_diag_csr_addr + offset;

	*val = ioread32(addr);
}

static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
				   void __iomem *cmd, void __iomem *cmd_done,
				   u32 rd_addr, u32 *rd_data)
{
	u32 done;
	u8 wait = 10;

	iowrite32(rd_addr, addr);
	iowrite32(XGENE_ENET_RD_CMD, cmd);

	/* wait for read command to complete */
	while (!(done = ioread32(cmd_done)) && wait--)
		udelay(1);

	if (!done)
		return false;

	*rd_data = ioread32(rd);
	iowrite32(0, cmd);

	return true;
}

static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,
			      u32 rd_addr, u32 *rd_data)
{
	void __iomem *addr, *rd, *cmd, *cmd_done;

	addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
	rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
	cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
	cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;

	if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
		netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
			   rd_addr);
}

static bool xgene_enet_rd_pcs(struct xgene_enet_pdata *pdata,
			      u32 rd_addr, u32 *rd_data)
{
	void __iomem *addr, *rd, *cmd, *cmd_done;
	bool success;

	addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET;
	rd = pdata->pcs_addr + PCS_READ_REG_OFFSET;
	cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET;
	cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET;

	success = xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data);
	if (!success)
		netdev_err(pdata->ndev, "PCS read failed, addr: %04x\n",
			   rd_addr);

	return success;
}

static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
{
	struct net_device *ndev = pdata->ndev;
	u32 data;
	u8 wait = 10;

	xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
	do {
		usleep_range(100, 110);
		xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
	} while ((data != 0xffffffff) && wait--);

	if (data != 0xffffffff) {
		netdev_err(ndev, "Failed to release memory from shutdown\n");
		return -ENODEV;
	}

	return 0;
}

static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
{
	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0);
	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0);
	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0);
	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0);
}

static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata)
{
	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST);
	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0);
}

static void xgene_pcs_reset(struct xgene_enet_pdata *pdata)
{
	u32 data;

	if (!xgene_enet_rd_pcs(pdata, PCS_CONTROL_1, &data))
		return;

	xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data | PCS_CTRL_PCS_RST);
	xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data & ~PCS_CTRL_PCS_RST);
}

static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)
{
	u32 addr0, addr1;
	u8 *dev_addr = pdata->ndev->dev_addr;

	addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
		(dev_addr[1] << 8) | dev_addr[0];
	addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);

	xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0);
	xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1);
}

static void xgene_xgmac_set_mss(struct xgene_enet_pdata *pdata)
{
	xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR, pdata->mss);
}

static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata)
{
	u32 data;

	xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data);

	return data;
}

static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)
{
	u32 data;

	xgene_xgmac_reset(pdata);

	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
	data |= HSTPPEN;
	data &= ~HSTLENCHK;
	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);

	xgene_xgmac_set_mac_addr(pdata);
	xgene_xgmac_set_mss(pdata);

	xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);
	data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
	xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);

	xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data);
	data |= BIT(12);
	xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);
	xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82);
	xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0);
	xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX);
}

static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata)
{
	u32 data;

	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN);
}

static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata)
{
	u32 data;

	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN);
}

static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata)
{
	u32 data;

	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN);
}

static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata)
{
	u32 data;

	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN);
}

static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
{
	struct device *dev = &pdata->pdev->dev;

	if (!xgene_ring_mgr_init(pdata))
		return -ENODEV;

	if (dev->of_node) {
		clk_prepare_enable(pdata->clk);
		udelay(5);
		clk_disable_unprepare(pdata->clk);
		udelay(5);
		clk_prepare_enable(pdata->clk);
		udelay(5);
	} else {
#ifdef CONFIG_ACPI
		if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev), "_RST")) {
			acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
					     "_RST", NULL, NULL);
		} else if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev),
					   "_INI")) {
			acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
					     "_INI", NULL, NULL);
		}
#endif
	}

	xgene_enet_ecc_init(pdata);
	xgene_enet_config_ring_if_assoc(pdata);

	return 0;
}

static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata,
				    u32 dst_ring_num, u16 bufpool_id)
{
	u32 cb, fpsel;

	xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb);
	cb |= CFG_CLE_BYPASS_EN0;
	CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
	xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb);

	fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
	xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb);
	CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
	CFG_CLE_FPSEL0_SET(&cb, fpsel);
	xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb);
}

static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)
{
	struct device *dev = &pdata->pdev->dev;
	struct xgene_enet_desc_ring *ring;
	u32 pb, val;
	int i;

	pb = 0;
	for (i = 0; i < pdata->rxq_cnt; i++) {
		ring = pdata->rx_ring[i]->buf_pool;

		val = xgene_enet_ring_bufnum(ring->id);
		pb |= BIT(val - 0x20);
	}
	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb);

	pb = 0;
	for (i = 0; i < pdata->txq_cnt; i++) {
		ring = pdata->tx_ring[i];

		val = xgene_enet_ring_bufnum(ring->id);
		pb |= BIT(val);
	}
	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQRESET_ADDR, pb);

	if (dev->of_node) {
		if (!IS_ERR(pdata->clk))
			clk_disable_unprepare(pdata->clk);
	}
}

static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
			     struct xgene_enet_desc_ring *ring)
{
	u32 addr, val, data;

	val = xgene_enet_ring_bufnum(ring->id);

	if (xgene_enet_is_bufpool(ring->id)) {
		addr = ENET_CFGSSQMIFPRESET_ADDR;
		data = BIT(val - 0x20);
	} else {
		addr = ENET_CFGSSQMIWQRESET_ADDR;
		data = BIT(val);
	}

	xgene_enet_wr_ring_if(pdata, addr, data);
}

static void xgene_enet_link_state(struct work_struct *work)
{
	struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work),
					 struct xgene_enet_pdata, link_work);
	struct gpio_desc *sfp_rdy = pdata->sfp_rdy;
	struct net_device *ndev = pdata->ndev;
	u32 link_status, poll_interval;

	link_status = xgene_enet_link_status(pdata);
	if (link_status && !IS_ERR(sfp_rdy) && !gpiod_get_value(sfp_rdy))
		link_status = 0;

	if (link_status) {
		if (!netif_carrier_ok(ndev)) {
			netif_carrier_on(ndev);
			xgene_xgmac_rx_enable(pdata);
			xgene_xgmac_tx_enable(pdata);
			netdev_info(ndev, "Link is Up - 10Gbps\n");
		}
		poll_interval = PHY_POLL_LINK_ON;
	} else {
		if (netif_carrier_ok(ndev)) {
			xgene_xgmac_rx_disable(pdata);
			xgene_xgmac_tx_disable(pdata);
			netif_carrier_off(ndev);
			netdev_info(ndev, "Link is Down\n");
		}
		poll_interval = PHY_POLL_LINK_OFF;

		xgene_pcs_reset(pdata);
	}

	schedule_delayed_work(&pdata->link_work, poll_interval);
}

const struct xgene_mac_ops xgene_xgmac_ops = {
	.init = xgene_xgmac_init,
	.reset = xgene_xgmac_reset,
	.rx_enable = xgene_xgmac_rx_enable,
	.tx_enable = xgene_xgmac_tx_enable,
	.rx_disable = xgene_xgmac_rx_disable,
	.tx_disable = xgene_xgmac_tx_disable,
	.set_mac_addr = xgene_xgmac_set_mac_addr,
	.set_mss = xgene_xgmac_set_mss,
	.link_state = xgene_enet_link_state
};

const struct xgene_port_ops xgene_xgport_ops = {
	.reset = xgene_enet_reset,
	.clear = xgene_enet_clear,
	.cle_bypass = xgene_enet_xgcle_bypass,
	.shutdown = xgene_enet_shutdown,
};
Commit	Line	Data
0148d38d IS	1	/* Applied Micro X-Gene SoC Ethernet Driver
	2	*
	3	* Copyright (c) 2014, Applied Micro Circuits Corporation
	4	* Authors: Iyappan Subramanian <isubramanian@apm.com>
	5	* Keyur Chudgar <kchudgar@apm.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
27ecf87c IS	21	#include <linux/of_gpio.h>
27ecf87c IS	22	#include <linux/gpio.h>
0148d38d IS	23	#include "xgene_enet_main.h"
	24	#include "xgene_enet_hw.h"
	25	#include "xgene_enet_xgmac.h"
	26
	27	static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
	28	u32 offset, u32 val)
	29	{
	30	void __iomem *addr = pdata->eth_csr_addr + offset;
	31
	32	iowrite32(val, addr);
	33	}
	34
	35	static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
	36	u32 offset, u32 val)
	37	{
	38	void __iomem *addr = pdata->eth_ring_if_addr + offset;
	39
	40	iowrite32(val, addr);
	41	}
	42
	43	static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
	44	u32 offset, u32 val)
	45	{
	46	void __iomem *addr = pdata->eth_diag_csr_addr + offset;
	47
	48	iowrite32(val, addr);
	49	}
	50
	51	static bool xgene_enet_wr_indirect(void __iomem addr, void __iomem wr,
	52	void __iomem cmd, void __iomem cmd_done,
	53	u32 wr_addr, u32 wr_data)
	54	{
	55	u32 done;
	56	u8 wait = 10;
	57
	58	iowrite32(wr_addr, addr);
	59	iowrite32(wr_data, wr);
	60	iowrite32(XGENE_ENET_WR_CMD, cmd);
	61
	62	/* wait for write command to complete */
	63	while (!(done = ioread32(cmd_done)) && wait--)
	64	udelay(1);
	65
	66	if (!done)
	67	return false;
	68
	69	iowrite32(0, cmd);
	70
	71	return true;
	72	}
	73
	74	static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata,
	75	u32 wr_addr, u32 wr_data)
	76	{
	77	void __iomem addr, wr, cmd, cmd_done;
	78
	79	addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
	80	wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
	81	cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
	82	cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
	83
	84	if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
	85	netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
	86	wr_addr);
87	}
88
3eb7cb9d IS	89	static void xgene_enet_wr_pcs(struct xgene_enet_pdata *pdata,
	90	u32 wr_addr, u32 wr_data)
	91	{
	92	void __iomem addr, wr, cmd, cmd_done;
	93
	94	addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET;
	95	wr = pdata->pcs_addr + PCS_WRITE_REG_OFFSET;
	96	cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET;
	97	cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET;
	98
	99	if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
	100	netdev_err(pdata->ndev, "PCS write failed, addr: %04x\n",
	101	wr_addr);
	102	}
	103
0148d38d IS	104	static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
	105	u32 offset, u32 *val)
	106	{
	107	void __iomem *addr = pdata->eth_csr_addr + offset;
	108
	109	*val = ioread32(addr);
	110	}
	111
	112	static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
	113	u32 offset, u32 *val)
	114	{
	115	void __iomem *addr = pdata->eth_diag_csr_addr + offset;
	116
	117	*val = ioread32(addr);
	118	}
	119
	120	static bool xgene_enet_rd_indirect(void __iomem addr, void __iomem rd,
	121	void __iomem cmd, void __iomem cmd_done,
	122	u32 rd_addr, u32 *rd_data)
	123	{
	124	u32 done;
	125	u8 wait = 10;
	126
	127	iowrite32(rd_addr, addr);
	128	iowrite32(XGENE_ENET_RD_CMD, cmd);
	129
	130	/* wait for read command to complete */
	131	while (!(done = ioread32(cmd_done)) && wait--)
	132	udelay(1);
	133
	134	if (!done)
	135	return false;
	136
	137	*rd_data = ioread32(rd);
	138	iowrite32(0, cmd);
	139
	140	return true;
	141	}
3eb7cb9d	142
0148d38d IS	143	static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,
	144	u32 rd_addr, u32 *rd_data)
	145	{
	146	void __iomem addr, rd, cmd, cmd_done;
	147
	148	addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
	149	rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
	150	cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
	151	cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
	152
	153	if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
	154	netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
	155	rd_addr);
	156	}
	157
f9dc7074	158	static bool xgene_enet_rd_pcs(struct xgene_enet_pdata *pdata,
3eb7cb9d IS	159	u32 rd_addr, u32 *rd_data)
	160	{
	161	void __iomem addr, rd, cmd, cmd_done;
f9dc7074	162	bool success;
3eb7cb9d IS	163
	164	addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET;
	165	rd = pdata->pcs_addr + PCS_READ_REG_OFFSET;
	166	cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET;
	167	cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET;
	168
f9dc7074 AB	169	success = xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data);
f9dc7074 AB	170	if (!success)
3eb7cb9d IS	171	netdev_err(pdata->ndev, "PCS read failed, addr: %04x\n",
3eb7cb9d IS	172	rd_addr);
f9dc7074 AB	173
f9dc7074 AB	174	return success;
3eb7cb9d IS	175	}
3eb7cb9d IS	176
0148d38d IS	177	static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
	178	{
	179	struct net_device *ndev = pdata->ndev;
	180	u32 data;
	181	u8 wait = 10;
	182
	183	xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
	184	do {
	185	usleep_range(100, 110);
	186	xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
	187	} while ((data != 0xffffffff) && wait--);
	188
	189	if (data != 0xffffffff) {
	190	netdev_err(ndev, "Failed to release memory from shutdown\n");
	191	return -ENODEV;
	192	}
	193
	194	return 0;
	195	}
	196
	197	static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
	198	{
	199	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0);
	200	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0);
	201	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0);
	202	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0);
	203	}
	204
	205	static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata)
	206	{
	207	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST);
	208	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0);
	209	}
	210
3eb7cb9d IS	211	static void xgene_pcs_reset(struct xgene_enet_pdata *pdata)
	212	{
	213	u32 data;
	214
f9dc7074 AB	215	if (!xgene_enet_rd_pcs(pdata, PCS_CONTROL_1, &data))
	216	return;
	217
3eb7cb9d IS	218	xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data \| PCS_CTRL_PCS_RST);
	219	xgene_enet_wr_pcs(pdata, PCS_CONTROL_1, data & ~PCS_CTRL_PCS_RST);
	220	}
	221
0148d38d IS	222	static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)
	223	{
	224	u32 addr0, addr1;
	225	u8 *dev_addr = pdata->ndev->dev_addr;
	226
	227	addr0 = (dev_addr[3] << 24) \| (dev_addr[2] << 16) \|
	228	(dev_addr[1] << 8) \| dev_addr[0];
	229	addr1 = (dev_addr[5] << 24) \| (dev_addr[4] << 16);
	230
	231	xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0);
	232	xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1);
	233	}
	234
9b00eb49 IS	235	static void xgene_xgmac_set_mss(struct xgene_enet_pdata *pdata)
	236	{
	237	xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR, pdata->mss);
	238	}
	239
0148d38d IS	240	static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata)
	241	{
	242	u32 data;
	243
	244	xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data);
	245
	246	return data;
	247	}
	248
	249	static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)
	250	{
	251	u32 data;
	252
	253	xgene_xgmac_reset(pdata);
	254
	255	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
	256	data \|= HSTPPEN;
	257	data &= ~HSTLENCHK;
	258	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);
	259
0148d38d	260	xgene_xgmac_set_mac_addr(pdata);
9b00eb49	261	xgene_xgmac_set_mss(pdata);
0148d38d IS	262
	263	xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);
	264	data \|= CFG_RSIF_FPBUFF_TIMEOUT_EN;
	265	xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);
	266
0148d38d IS	267	xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data);
	268	data \|= BIT(12);
	269	xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);
	270	xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82);
4f1c8d81 IS	271	xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0);
4f1c8d81 IS	272	xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX);
0148d38d IS	273	}
	274
	275	static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata)
	276	{
	277	u32 data;
	278
	279	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
	280	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data \| HSTRFEN);
	281	}
	282
	283	static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata)
	284	{
	285	u32 data;
	286
	287	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
	288	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data \| HSTTFEN);
	289	}
	290
	291	static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata)
	292	{
	293	u32 data;
	294
	295	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
	296	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN);
	297	}
	298
	299	static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata)
	300	{
	301	u32 data;
	302
	303	xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
	304	xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN);
	305	}
	306
c3f4465d	307	static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
0148d38d	308	{
bc61167a IS	309	struct device *dev = &pdata->pdev->dev;
bc61167a IS	310
c3f4465d IS	311	if (!xgene_ring_mgr_init(pdata))
	312	return -ENODEV;
	313
bc61167a	314	if (dev->of_node) {
c2d33bdc	315	clk_prepare_enable(pdata->clk);
bc61167a	316	udelay(5);
c2d33bdc	317	clk_disable_unprepare(pdata->clk);
bc61167a	318	udelay(5);
c2d33bdc	319	clk_prepare_enable(pdata->clk);
bc61167a IS	320	udelay(5);
	321	} else {
	322	#ifdef CONFIG_ACPI
	323	if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev), "_RST")) {
	324	acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
	325	"_RST", NULL, NULL);
	326	} else if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev),
	327	"_INI")) {
	328	acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
	329	"_INI", NULL, NULL);
	330	}
	331	#endif
c2d33bdc	332	}
0148d38d IS	333
	334	xgene_enet_ecc_init(pdata);
	335	xgene_enet_config_ring_if_assoc(pdata);
c3f4465d IS	336
c3f4465d IS	337	return 0;
0148d38d IS	338	}
	339
	340	static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata,
	341	u32 dst_ring_num, u16 bufpool_id)
	342	{
	343	u32 cb, fpsel;
	344
	345	xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb);
	346	cb \|= CFG_CLE_BYPASS_EN0;
	347	CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
	348	xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb);
	349
	350	fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
	351	xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb);
	352	CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
	353	CFG_CLE_FPSEL0_SET(&cb, fpsel);
	354	xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb);
	355	}
	356
	357	static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)
	358	{
bc61167a	359	struct device *dev = &pdata->pdev->dev;
cb11c062 IS	360	struct xgene_enet_desc_ring *ring;
	361	u32 pb, val;
	362	int i;
	363
	364	pb = 0;
	365	for (i = 0; i < pdata->rxq_cnt; i++) {
	366	ring = pdata->rx_ring[i]->buf_pool;
	367
	368	val = xgene_enet_ring_bufnum(ring->id);
	369	pb \|= BIT(val - 0x20);
	370	}
	371	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb);
	372
	373	pb = 0;
	374	for (i = 0; i < pdata->txq_cnt; i++) {
	375	ring = pdata->tx_ring[i];
	376
	377	val = xgene_enet_ring_bufnum(ring->id);
	378	pb \|= BIT(val);
	379	}
	380	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQRESET_ADDR, pb);
bc61167a IS	381
	382	if (dev->of_node) {
	383	if (!IS_ERR(pdata->clk))
	384	clk_disable_unprepare(pdata->clk);
	385	}
cb11c062 IS	386	}
	387
	388	static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
	389	struct xgene_enet_desc_ring *ring)
	390	{
	391	u32 addr, val, data;
	392
	393	val = xgene_enet_ring_bufnum(ring->id);
	394
	395	if (xgene_enet_is_bufpool(ring->id)) {
	396	addr = ENET_CFGSSQMIFPRESET_ADDR;
	397	data = BIT(val - 0x20);
	398	} else {
	399	addr = ENET_CFGSSQMIWQRESET_ADDR;
	400	data = BIT(val);
	401	}
	402
	403	xgene_enet_wr_ring_if(pdata, addr, data);
0148d38d IS	404	}
0148d38d IS	405
dc8385f0	406	static void xgene_enet_link_state(struct work_struct *work)
0148d38d IS	407	{
	408	struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work),
	409	struct xgene_enet_pdata, link_work);
27ecf87c	410	struct gpio_desc *sfp_rdy = pdata->sfp_rdy;
0148d38d IS	411	struct net_device *ndev = pdata->ndev;
	412	u32 link_status, poll_interval;
	413
	414	link_status = xgene_enet_link_status(pdata);
27ecf87c IS	415	if (link_status && !IS_ERR(sfp_rdy) && !gpiod_get_value(sfp_rdy))
	416	link_status = 0;
	417
0148d38d IS	418	if (link_status) {
	419	if (!netif_carrier_ok(ndev)) {
	420	netif_carrier_on(ndev);
0148d38d IS	421	xgene_xgmac_rx_enable(pdata);
	422	xgene_xgmac_tx_enable(pdata);
	423	netdev_info(ndev, "Link is Up - 10Gbps\n");
	424	}
	425	poll_interval = PHY_POLL_LINK_ON;
	426	} else {
	427	if (netif_carrier_ok(ndev)) {
	428	xgene_xgmac_rx_disable(pdata);
	429	xgene_xgmac_tx_disable(pdata);
	430	netif_carrier_off(ndev);
	431	netdev_info(ndev, "Link is Down\n");
	432	}
	433	poll_interval = PHY_POLL_LINK_OFF;
3eb7cb9d IS	434
3eb7cb9d IS	435	xgene_pcs_reset(pdata);
0148d38d IS	436	}
	437
	438	schedule_delayed_work(&pdata->link_work, poll_interval);
	439	}
	440
3cdb7309	441	const struct xgene_mac_ops xgene_xgmac_ops = {
0148d38d IS	442	.init = xgene_xgmac_init,
	443	.reset = xgene_xgmac_reset,
	444	.rx_enable = xgene_xgmac_rx_enable,
	445	.tx_enable = xgene_xgmac_tx_enable,
	446	.rx_disable = xgene_xgmac_rx_disable,
	447	.tx_disable = xgene_xgmac_tx_disable,
	448	.set_mac_addr = xgene_xgmac_set_mac_addr,
9b00eb49	449	.set_mss = xgene_xgmac_set_mss,
dc8385f0	450	.link_state = xgene_enet_link_state
0148d38d IS	451	};
0148d38d IS	452
3cdb7309	453	const struct xgene_port_ops xgene_xgport_ops = {
0148d38d	454	.reset = xgene_enet_reset,
cb11c062	455	.clear = xgene_enet_clear,
0148d38d IS	456	.cle_bypass = xgene_enet_xgcle_bypass,
	457	.shutdown = xgene_enet_shutdown,
	458	};