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Merge remote-tracking branch 'ftrace/for-next'
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
4ad79e13 1/* bnx2x_main.c: QLogic Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
4ad79e13
YM		 4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
a2fbb9ea
ET		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
08f6dd89 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
24e3fcef 12 * Written by: Eliezer Tamir
a2fbb9ea
ET		 13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 15 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 16 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 17 *
18 */
19
f1deab50
JP		 20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
a2fbb9ea
ET		 22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/kernel.h>
25#include <linux/device.h> /* for dev_info() */
26#include <linux/timer.h>
27#include <linux/errno.h>
28#include <linux/ioport.h>
29#include <linux/slab.h>
a2fbb9ea
ET		 30#include <linux/interrupt.h>
31#include <linux/pci.h>
33d8e6a5 32#include <linux/aer.h>
a2fbb9ea
ET		 33#include <linux/init.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/dma-mapping.h>
38#include <linux/bitops.h>
39#include <linux/irq.h>
40#include <linux/delay.h>
41#include <asm/byteorder.h>
42#include <linux/time.h>
43#include <linux/ethtool.h>
44#include <linux/mii.h>
0c6671b0 45#include <linux/if_vlan.h>
c9931896 46#include <linux/crash_dump.h>
a2fbb9ea 47#include <net/ip.h>
619c5cb6 48#include <net/ipv6.h>
a2fbb9ea 49#include <net/tcp.h>
51de7bb9 50#include <net/vxlan.h>
a2fbb9ea 51#include <net/checksum.h>
34f80b04 52#include <net/ip6_checksum.h>
a2fbb9ea
ET		 53#include <linux/workqueue.h>
54#include <linux/crc32.h>
34f80b04 55#include <linux/crc32c.h>
a2fbb9ea
ET		 56#include <linux/prefetch.h>
57#include <linux/zlib.h>
a2fbb9ea 58#include <linux/io.h>
452427b0 59#include <linux/semaphore.h>
45229b42 60#include <linux/stringify.h>
7ab24bfd 61#include <linux/vmalloc.h>
a2fbb9ea
ET		 62#include "bnx2x.h"
63#include "bnx2x_init.h"
94a78b79 64#include "bnx2x_init_ops.h"
9f6c9258 65#include "bnx2x_cmn.h"
1ab4434c 66#include "bnx2x_vfpf.h"
e4901dde 67#include "bnx2x_dcb.h"
042181f5 68#include "bnx2x_sp.h"
94a78b79
VZ		 69#include <linux/firmware.h>
70#include "bnx2x_fw_file_hdr.h"
71/* FW files */
45229b42
BH		 72#define FW_FILE_VERSION \
73 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
74 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
75 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
76 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 77#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
78#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 79#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 80
34f80b04
EG		 81/* Time in jiffies before concluding the transmitter is hung */
82#define TX_TIMEOUT (5*HZ)
a2fbb9ea 83
0329aba1 84static char version[] =
4ad79e13 85 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 86 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
87
24e3fcef 88MODULE_AUTHOR("Eliezer Tamir");
4ad79e13 89MODULE_DESCRIPTION("QLogic "
619c5cb6
VZ		 90 "BCM57710/57711/57711E/"
91 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
92 "57840/57840_MF Driver");
a2fbb9ea
ET		 93MODULE_LICENSE("GPL");
94MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 95MODULE_FIRMWARE(FW_FILE_NAME_E1);
96MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 97MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 98
a8f47eb7 99int bnx2x_num_queues;
1c8bb760 100module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
96305234
DK		 101MODULE_PARM_DESC(num_queues,
102 " Set number of queues (default is as a number of CPUs)");
555f6c78 103
19680c48 104static int disable_tpa;
1c8bb760 105module_param(disable_tpa, int, S_IRUGO);
9898f86d 106MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 107
a8f47eb7 108static int int_mode;
1c8bb760 109module_param(int_mode, int, S_IRUGO);
619c5cb6 110MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 111 "(1 INT#x; 2 MSI)");
8badd27a 112
a18f5128 113static int dropless_fc;
1c8bb760 114module_param(dropless_fc, int, S_IRUGO);
a18f5128
EG		 115MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116
8d5726c4 117static int mrrs = -1;
1c8bb760 118module_param(mrrs, int, S_IRUGO);
8d5726c4
EG		 119MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
120
9898f86d 121static int debug;
1c8bb760 122module_param(debug, int, S_IRUGO);
9898f86d
EG		 123MODULE_PARM_DESC(debug, " Default debug msglevel");
124
370d4a26
YM		 125static struct workqueue_struct *bnx2x_wq;
126struct workqueue_struct *bnx2x_iov_wq;
ec6ba945 127
1ef1d45a
BW		 128struct bnx2x_mac_vals {
129 u32 xmac_addr;
130 u32 xmac_val;
131 u32 emac_addr;
132 u32 emac_val;
3d6b7253
YM		 133 u32 umac_addr[2];
134 u32 umac_val[2];
1ef1d45a
BW		 135 u32 bmac_addr;
136 u32 bmac_val[2];
137};
138
a2fbb9ea
ET		 139enum bnx2x_board_type {
140 BCM57710 = 0,
619c5cb6
VZ		 141 BCM57711,
142 BCM57711E,
143 BCM57712,
144 BCM57712_MF,
1ab4434c 145 BCM57712_VF,
619c5cb6
VZ		 146 BCM57800,
147 BCM57800_MF,
1ab4434c 148 BCM57800_VF,
619c5cb6
VZ		 149 BCM57810,
150 BCM57810_MF,
1ab4434c 151 BCM57810_VF,
c3def943
YM		 152 BCM57840_4_10,
153 BCM57840_2_20,
7e8e02df 154 BCM57840_MF,
1ab4434c 155 BCM57840_VF,
7e8e02df 156 BCM57811,
1ab4434c
AE		 157 BCM57811_MF,
158 BCM57840_O,
159 BCM57840_MFO,
160 BCM57811_VF
a2fbb9ea
ET		 161};
162
34f80b04 163/* indexed by board_type, above */
53a10565 164static struct {
a2fbb9ea 165 char *name;
0329aba1 166} board_info[] = {
4ad79e13
YM		 167 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
168 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" },
169 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" },
170 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" },
171 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
172 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
173 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" },
174 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
175 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
176 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" },
177 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
178 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
179 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
180 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
181 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
182 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
183 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" },
184 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
185 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
186 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
187 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 188};
189
619c5cb6
VZ		 190#ifndef PCI_DEVICE_ID_NX2_57710
191#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
192#endif
193#ifndef PCI_DEVICE_ID_NX2_57711
194#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
195#endif
196#ifndef PCI_DEVICE_ID_NX2_57711E
197#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
198#endif
199#ifndef PCI_DEVICE_ID_NX2_57712
200#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
201#endif
202#ifndef PCI_DEVICE_ID_NX2_57712_MF
203#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
204#endif
8395be5e
AE		 205#ifndef PCI_DEVICE_ID_NX2_57712_VF
206#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
207#endif
619c5cb6
VZ		 208#ifndef PCI_DEVICE_ID_NX2_57800
209#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
210#endif
211#ifndef PCI_DEVICE_ID_NX2_57800_MF
212#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
213#endif
8395be5e
AE		 214#ifndef PCI_DEVICE_ID_NX2_57800_VF
215#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
216#endif
619c5cb6
VZ		 217#ifndef PCI_DEVICE_ID_NX2_57810
218#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
219#endif
220#ifndef PCI_DEVICE_ID_NX2_57810_MF
221#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
222#endif
c3def943
YM		 223#ifndef PCI_DEVICE_ID_NX2_57840_O
224#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
225#endif
8395be5e
AE		 226#ifndef PCI_DEVICE_ID_NX2_57810_VF
227#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
228#endif
c3def943
YM		 229#ifndef PCI_DEVICE_ID_NX2_57840_4_10
230#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
231#endif
232#ifndef PCI_DEVICE_ID_NX2_57840_2_20
233#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
234#endif
235#ifndef PCI_DEVICE_ID_NX2_57840_MFO
236#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 237#endif
238#ifndef PCI_DEVICE_ID_NX2_57840_MF
239#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
240#endif
8395be5e
AE		 241#ifndef PCI_DEVICE_ID_NX2_57840_VF
242#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
243#endif
7e8e02df
BW		 244#ifndef PCI_DEVICE_ID_NX2_57811
245#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
246#endif
247#ifndef PCI_DEVICE_ID_NX2_57811_MF
248#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
249#endif
8395be5e
AE		 250#ifndef PCI_DEVICE_ID_NX2_57811_VF
251#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
252#endif
253
9baa3c34 254static const struct pci_device_id bnx2x_pci_tbl[] = {
e4ed7113
EG		 255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
9c9a6524 268 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
c3def943 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
9c9a6524 273 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
9c9a6524 275 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 276 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 279 { 0 }
280};
281
282MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
283
452427b0
YM		 284/* Global resources for unloading a previously loaded device */
285#define BNX2X_PREV_WAIT_NEEDED 1
286static DEFINE_SEMAPHORE(bnx2x_prev_sem);
287static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 288
289/* Forward declaration */
290static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
291static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
292static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
293
a2fbb9ea
ET		 294/****************************************************************************
295* General service functions
296****************************************************************************/
297
eeed018c
MK		 298static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
299
1191cb83 300static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 301 u32 addr, dma_addr_t mapping)
302{
303 REG_WR(bp, addr, U64_LO(mapping));
304 REG_WR(bp, addr + 4, U64_HI(mapping));
305}
306
1191cb83
ED		 307static void storm_memset_spq_addr(struct bnx2x *bp,
308 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 309{
310 u32 addr = XSEM_REG_FAST_MEMORY +
311 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
312
313 __storm_memset_dma_mapping(bp, addr, mapping);
314}
315
1191cb83
ED		 316static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
317 u16 pf_id)
523224a3 318{
619c5cb6
VZ		 319 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
320 pf_id);
321 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
322 pf_id);
323 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
324 pf_id);
325 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
326 pf_id);
523224a3
DK		 327}
328
1191cb83
ED		 329static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
330 u8 enable)
619c5cb6
VZ		 331{
332 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
333 enable);
334 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
335 enable);
336 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
337 enable);
338 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
339 enable);
340}
523224a3 341
1191cb83
ED		 342static void storm_memset_eq_data(struct bnx2x *bp,
343 struct event_ring_data *eq_data,
523224a3
DK		 344 u16 pfid)
345{
346 size_t size = sizeof(struct event_ring_data);
347
348 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
349
350 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
351}
352
1191cb83
ED		 353static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
354 u16 pfid)
523224a3
DK		 355{
356 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
357 REG_WR16(bp, addr, eq_prod);
358}
359
a2fbb9ea
ET		 360/* used only at init
361 * locking is done by mcp
362 */
8d96286a 363static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 364{
365 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
366 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
368 PCICFG_VENDOR_ID_OFFSET);
369}
370
a2fbb9ea
ET		 371static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
372{
373 u32 val;
374
375 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
376 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
377 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
378 PCICFG_VENDOR_ID_OFFSET);
379
380 return val;
381}
a2fbb9ea 382
f2e0899f
DK		 383#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
384#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
385#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
386#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
387#define DMAE_DP_DST_NONE "dst_addr [none]"
388
6bf07b8e
YM		 389static void bnx2x_dp_dmae(struct bnx2x *bp,
390 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 391{
392 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 393 int i;
fd1fc79d
AE		 394
395 switch (dmae->opcode & DMAE_COMMAND_DST) {
396 case DMAE_CMD_DST_PCI:
397 if (src_type == DMAE_CMD_SRC_PCI)
398 DP(msglvl, "DMAE: opcode 0x%08x\n"
399 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
400 "comp_addr [%x:%08x], comp_val 0x%08x\n",
401 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
402 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
403 dmae->comp_addr_hi, dmae->comp_addr_lo,
404 dmae->comp_val);
405 else
406 DP(msglvl, "DMAE: opcode 0x%08x\n"
407 "src [%08x], len [%d*4], dst [%x:%08x]\n"
408 "comp_addr [%x:%08x], comp_val 0x%08x\n",
409 dmae->opcode, dmae->src_addr_lo >> 2,
410 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
411 dmae->comp_addr_hi, dmae->comp_addr_lo,
412 dmae->comp_val);
413 break;
414 case DMAE_CMD_DST_GRC:
415 if (src_type == DMAE_CMD_SRC_PCI)
416 DP(msglvl, "DMAE: opcode 0x%08x\n"
417 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
418 "comp_addr [%x:%08x], comp_val 0x%08x\n",
419 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
420 dmae->len, dmae->dst_addr_lo >> 2,
421 dmae->comp_addr_hi, dmae->comp_addr_lo,
422 dmae->comp_val);
423 else
424 DP(msglvl, "DMAE: opcode 0x%08x\n"
425 "src [%08x], len [%d*4], dst [%08x]\n"
426 "comp_addr [%x:%08x], comp_val 0x%08x\n",
427 dmae->opcode, dmae->src_addr_lo >> 2,
428 dmae->len, dmae->dst_addr_lo >> 2,
429 dmae->comp_addr_hi, dmae->comp_addr_lo,
430 dmae->comp_val);
431 break;
432 default:
433 if (src_type == DMAE_CMD_SRC_PCI)
434 DP(msglvl, "DMAE: opcode 0x%08x\n"
435 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
436 "comp_addr [%x:%08x] comp_val 0x%08x\n",
437 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
438 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
439 dmae->comp_val);
440 else
441 DP(msglvl, "DMAE: opcode 0x%08x\n"
442 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
443 "comp_addr [%x:%08x] comp_val 0x%08x\n",
444 dmae->opcode, dmae->src_addr_lo >> 2,
445 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
446 dmae->comp_val);
447 break;
448 }
6bf07b8e
YM		 449
450 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
451 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
452 i, *(((u32 *)dmae) + i));
fd1fc79d 453}
f2e0899f 454
a2fbb9ea 455/* copy command into DMAE command memory and set DMAE command go */
6c719d00 456void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 457{
458 u32 cmd_offset;
459 int i;
460
461 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
462 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
463 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 464 }
465 REG_WR(bp, dmae_reg_go_c[idx], 1);
466}
467
f2e0899f 468u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 469{
f2e0899f
DK		 470 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
471 DMAE_CMD_C_ENABLE);
472}
ad8d3948 473
f2e0899f
DK		 474u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
475{
476 return opcode & ~DMAE_CMD_SRC_RESET;
477}
ad8d3948 478
f2e0899f
DK		 479u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
480 bool with_comp, u8 comp_type)
481{
482 u32 opcode = 0;
483
484 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
485 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 486
f2e0899f
DK		 487 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
488
489 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 490 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
491 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 492 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 493
a2fbb9ea 494#ifdef __BIG_ENDIAN
f2e0899f 495 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 496#else
f2e0899f 497 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 498#endif
f2e0899f
DK		 499 if (with_comp)
500 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
501 return opcode;
502}
503
fd1fc79d 504void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 505 struct dmae_command *dmae,
506 u8 src_type, u8 dst_type)
f2e0899f
DK		 507{
508 memset(dmae, 0, sizeof(struct dmae_command));
509
510 /* set the opcode */
511 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
512 true, DMAE_COMP_PCI);
513
514 /* fill in the completion parameters */
515 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
516 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
517 dmae->comp_val = DMAE_COMP_VAL;
518}
519
fd1fc79d 520/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 521int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
522 u32 *comp)
f2e0899f 523{
5e374b5a 524 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 525 int rc = 0;
526
6bf07b8e
YM		 527 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
528
529 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 530 * as long as this code is called both from syscall context and
531 * from ndo_set_rx_mode() flow that may be called from BH.
532 */
eeed018c 533
6e30dd4e 534 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 535
f2e0899f 536 /* reset completion */
32316a46 537 *comp = 0;
a2fbb9ea 538
f2e0899f
DK		 539 /* post the command on the channel used for initializations */
540 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 541
f2e0899f 542 /* wait for completion */
a2fbb9ea 543 udelay(5);
32316a46 544 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 545
95c6c616
AE		 546 if (!cnt ||
547 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
548 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 549 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 550 rc = DMAE_TIMEOUT;
551 goto unlock;
a2fbb9ea 552 }
ad8d3948 553 cnt--;
f2e0899f 554 udelay(50);
a2fbb9ea 555 }
32316a46 556 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 557 BNX2X_ERR("DMAE PCI error!\n");
558 rc = DMAE_PCI_ERROR;
559 }
560
f2e0899f 561unlock:
eeed018c 562
6e30dd4e 563 spin_unlock_bh(&bp->dmae_lock);
eeed018c 564
f2e0899f
DK		 565 return rc;
566}
567
568void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
569 u32 len32)
570{
6bf07b8e 571 int rc;
f2e0899f
DK		 572 struct dmae_command dmae;
573
574 if (!bp->dmae_ready) {
575 u32 *data = bnx2x_sp(bp, wb_data[0]);
576
127a425e
AE		 577 if (CHIP_IS_E1(bp))
578 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
579 else
580 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 581 return;
582 }
583
584 /* set opcode and fixed command fields */
585 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
586
587 /* fill in addresses and len */
588 dmae.src_addr_lo = U64_LO(dma_addr);
589 dmae.src_addr_hi = U64_HI(dma_addr);
590 dmae.dst_addr_lo = dst_addr >> 2;
591 dmae.dst_addr_hi = 0;
592 dmae.len = len32;
593
f2e0899f 594 /* issue the command and wait for completion */
32316a46 595 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 596 if (rc) {
597 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 598#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 599 bnx2x_panic();
9dcd9acd 600#endif
6bf07b8e 601 }
a2fbb9ea
ET		 602}
603
c18487ee 604void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 605{
6bf07b8e 606 int rc;
5ff7b6d4 607 struct dmae_command dmae;
ad8d3948
EG		 608
609 if (!bp->dmae_ready) {
610 u32 *data = bnx2x_sp(bp, wb_data[0]);
611 int i;
612
51c1a580 613 if (CHIP_IS_E1(bp))
127a425e
AE		 614 for (i = 0; i < len32; i++)
615 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 616 else
127a425e
AE		 617 for (i = 0; i < len32; i++)
618 data[i] = REG_RD(bp, src_addr + i*4);
619
ad8d3948
EG		 620 return;
621 }
622
f2e0899f
DK		 623 /* set opcode and fixed command fields */
624 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 625
f2e0899f 626 /* fill in addresses and len */
5ff7b6d4
EG		 627 dmae.src_addr_lo = src_addr >> 2;
628 dmae.src_addr_hi = 0;
629 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
630 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
631 dmae.len = len32;
ad8d3948 632
f2e0899f 633 /* issue the command and wait for completion */
32316a46 634 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 635 if (rc) {
636 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 637#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 638 bnx2x_panic();
9dcd9acd 639#endif
c957d09f 640 }
ad8d3948
EG		 641}
642
8d96286a 643static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
644 u32 addr, u32 len)
573f2035 645{
02e3c6cb 646 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 647 int offset = 0;
648
02e3c6cb 649 while (len > dmae_wr_max) {
573f2035 650 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 651 addr + offset, dmae_wr_max);
652 offset += dmae_wr_max * 4;
653 len -= dmae_wr_max;
573f2035
EG		 654 }
655
656 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
657}
658
97539f1e
AE		 659enum storms {
660 XSTORM,
661 TSTORM,
662 CSTORM,
663 USTORM,
664 MAX_STORMS
665};
34f80b04 666
97539f1e
AE		 667#define STORMS_NUM 4
668#define REGS_IN_ENTRY 4
34f80b04 669
97539f1e
AE		 670static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
671 enum storms storm,
672 int entry)
673{
674 switch (storm) {
675 case XSTORM:
676 return XSTORM_ASSERT_LIST_OFFSET(entry);
677 case TSTORM:
678 return TSTORM_ASSERT_LIST_OFFSET(entry);
679 case CSTORM:
680 return CSTORM_ASSERT_LIST_OFFSET(entry);
681 case USTORM:
682 return USTORM_ASSERT_LIST_OFFSET(entry);
683 case MAX_STORMS:
684 default:
685 BNX2X_ERR("unknown storm\n");
34f80b04 686 }
97539f1e
AE		 687 return -EINVAL;
688}
34f80b04 689
97539f1e
AE		 690static int bnx2x_mc_assert(struct bnx2x *bp)
691{
692 char last_idx;
693 int i, j, rc = 0;
694 enum storms storm;
695 u32 regs[REGS_IN_ENTRY];
696 u32 bar_storm_intmem[STORMS_NUM] = {
697 BAR_XSTRORM_INTMEM,
698 BAR_TSTRORM_INTMEM,
699 BAR_CSTRORM_INTMEM,
700 BAR_USTRORM_INTMEM
701 };
702 u32 storm_assert_list_index[STORMS_NUM] = {
703 XSTORM_ASSERT_LIST_INDEX_OFFSET,
704 TSTORM_ASSERT_LIST_INDEX_OFFSET,
705 CSTORM_ASSERT_LIST_INDEX_OFFSET,
706 USTORM_ASSERT_LIST_INDEX_OFFSET
707 };
708 char *storms_string[STORMS_NUM] = {
709 "XSTORM",
710 "TSTORM",
711 "CSTORM",
712 "USTORM"
713 };
714
715 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
716 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
717 storm_assert_list_index[storm]);
718 if (last_idx)
719 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
720 storms_string[storm], last_idx);
721
722 /* print the asserts */
723 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
724 /* read a single assert entry */
725 for (j = 0; j < REGS_IN_ENTRY; j++)
726 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
727 bnx2x_get_assert_list_entry(bp,
728 storm,
729 i) +
730 sizeof(u32) * j);
731
732 /* log entry if it contains a valid assert */
733 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
734 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
735 storms_string[storm], i, regs[3],
736 regs[2], regs[1], regs[0]);
737 rc++;
738 } else {
739 break;
740 }
a2fbb9ea
ET		 741 }
742 }
34f80b04 743
97539f1e
AE		 744 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
745 CHIP_IS_E1(bp) ? "everest1" :
746 CHIP_IS_E1H(bp) ? "everest1h" :
747 CHIP_IS_E2(bp) ? "everest2" : "everest3",
748 BCM_5710_FW_MAJOR_VERSION,
749 BCM_5710_FW_MINOR_VERSION,
750 BCM_5710_FW_REVISION_VERSION);
751
a2fbb9ea
ET		 752 return rc;
753}
c14423fe 754
1a6974b2
YM		 755#define MCPR_TRACE_BUFFER_SIZE (0x800)
756#define SCRATCH_BUFFER_SIZE(bp) \
757 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
758
7a25cc73 759void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 760{
7a25cc73 761 u32 addr, val;
a2fbb9ea 762 u32 mark, offset;
4781bfad 763 __be32 data[9];
a2fbb9ea 764 int word;
f2e0899f 765 u32 trace_shmem_base;
2145a920
VZ		 766 if (BP_NOMCP(bp)) {
767 BNX2X_ERR("NO MCP - can not dump\n");
768 return;
769 }
7a25cc73
DK		 770 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
771 (bp->common.bc_ver & 0xff0000) >> 16,
772 (bp->common.bc_ver & 0xff00) >> 8,
773 (bp->common.bc_ver & 0xff));
774
b44e108b
GP		 775 if (pci_channel_offline(bp->pdev)) {
776 BNX2X_ERR("Cannot dump MCP info while in PCI error\n");
777 return;
778 }
779
7a25cc73
DK		 780 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
781 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 782 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 783
f2e0899f
DK		 784 if (BP_PATH(bp) == 0)
785 trace_shmem_base = bp->common.shmem_base;
786 else
787 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 788
789 /* sanity */
790 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
791 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
792 SCRATCH_BUFFER_SIZE(bp)) {
793 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
794 trace_shmem_base);
795 return;
796 }
797
798 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 799
800 /* validate TRCB signature */
801 mark = REG_RD(bp, addr);
802 if (mark != MFW_TRACE_SIGNATURE) {
803 BNX2X_ERR("Trace buffer signature is missing.");
804 return ;
805 }
806
807 /* read cyclic buffer pointer */
808 addr += 4;
cdaa7cb8 809 mark = REG_RD(bp, addr);
1a6974b2
YM		 810 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
811 if (mark >= trace_shmem_base || mark < addr + 4) {
812 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
813 return;
814 }
7a25cc73 815 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 816
7a25cc73 817 printk("%s", lvl);
2de67439
YM		 818
819 /* dump buffer after the mark */
1a6974b2 820 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 821 for (word = 0; word < 8; word++)
cdaa7cb8 822 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 823 data[8] = 0x0;
7995c64e 824 pr_cont("%s", (char *)data);
a2fbb9ea 825 }
2de67439
YM		 826
827 /* dump buffer before the mark */
cdaa7cb8 828 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 829 for (word = 0; word < 8; word++)
cdaa7cb8 830 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 831 data[8] = 0x0;
7995c64e 832 pr_cont("%s", (char *)data);
a2fbb9ea 833 }
7a25cc73
DK		 834 printk("%s" "end of fw dump\n", lvl);
835}
836
1191cb83 837static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 838{
839 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 840}
841
823e1d90
YM		 842static void bnx2x_hc_int_disable(struct bnx2x *bp)
843{
844 int port = BP_PORT(bp);
845 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
846 u32 val = REG_RD(bp, addr);
847
848 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 849 * MSI/MSIX capability
850 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 851 */
852 if (CHIP_IS_E1(bp)) {
853 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
854 * Use mask register to prevent from HC sending interrupts
855 * after we exit the function
856 */
857 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
858
859 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
860 HC_CONFIG_0_REG_INT_LINE_EN_0 |
861 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
862 } else
863 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
864 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
865 HC_CONFIG_0_REG_INT_LINE_EN_0 |
866 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
867
868 DP(NETIF_MSG_IFDOWN,
869 "write %x to HC %d (addr 0x%x)\n",
870 val, port, addr);
871
872 /* flush all outstanding writes */
873 mmiowb();
874
875 REG_WR(bp, addr, val);
876 if (REG_RD(bp, addr) != val)
6bf07b8e 877 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 878}
879
880static void bnx2x_igu_int_disable(struct bnx2x *bp)
881{
882 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
883
884 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
885 IGU_PF_CONF_INT_LINE_EN |
886 IGU_PF_CONF_ATTN_BIT_EN);
887
888 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
889
890 /* flush all outstanding writes */
891 mmiowb();
892
893 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
894 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 895 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 896}
897
898static void bnx2x_int_disable(struct bnx2x *bp)
899{
900 if (bp->common.int_block == INT_BLOCK_HC)
901 bnx2x_hc_int_disable(bp);
902 else
903 bnx2x_igu_int_disable(bp);
904}
905
906void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 907{
908 int i;
523224a3
DK		 909 u16 j;
910 struct hc_sp_status_block_data sp_sb_data;
911 int func = BP_FUNC(bp);
912#ifdef BNX2X_STOP_ON_ERROR
913 u16 start = 0, end = 0;
6383c0b3 914 u8 cos;
523224a3 915#endif
0155a27c 916 if (IS_PF(bp) && disable_int)
823e1d90 917 bnx2x_int_disable(bp);
a2fbb9ea 918
66e855f3 919 bp->stats_state = STATS_STATE_DISABLED;
7a752993 920 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 921 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
922
a2fbb9ea
ET		 923 BNX2X_ERR("begin crash dump -----------------\n");
924
8440d2b6
EG		 925 /* Indices */
926 /* Common */
0155a27c
YM		 927 if (IS_PF(bp)) {
928 struct host_sp_status_block *def_sb = bp->def_status_blk;
929 int data_size, cstorm_offset;
930
931 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
932 bp->def_idx, bp->def_att_idx, bp->attn_state,
933 bp->spq_prod_idx, bp->stats_counter);
934 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
935 def_sb->atten_status_block.attn_bits,
936 def_sb->atten_status_block.attn_bits_ack,
937 def_sb->atten_status_block.status_block_id,
938 def_sb->atten_status_block.attn_bits_index);
939 BNX2X_ERR(" def (");
940 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
941 pr_cont("0x%x%s",
942 def_sb->sp_sb.index_values[i],
943 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
944
945 data_size = sizeof(struct hc_sp_status_block_data) /
946 sizeof(u32);
947 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
948 for (i = 0; i < data_size; i++)
949 *((u32 *)&sp_sb_data + i) =
950 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
951 i * sizeof(u32));
952
953 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
954 sp_sb_data.igu_sb_id,
955 sp_sb_data.igu_seg_id,
956 sp_sb_data.p_func.pf_id,
957 sp_sb_data.p_func.vnic_id,
958 sp_sb_data.p_func.vf_id,
959 sp_sb_data.p_func.vf_valid,
960 sp_sb_data.state);
961 }
523224a3 962
ec6ba945 963 for_each_eth_queue(bp, i) {
a2fbb9ea 964 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 965 int loop;
f2e0899f 966 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 967 struct hc_status_block_data_e1x sb_data_e1x;
968 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 969 CHIP_IS_E1x(bp) ?
970 sb_data_e1x.common.state_machine :
971 sb_data_e2.common.state_machine;
523224a3 972 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 973 CHIP_IS_E1x(bp) ?
974 sb_data_e1x.index_data :
975 sb_data_e2.index_data;
6383c0b3 976 u8 data_size, cos;
523224a3 977 u32 *sb_data_p;
6383c0b3 978 struct bnx2x_fp_txdata txdata;
523224a3 979
e2611998
YM		 980 if (!bp->fp)
981 break;
982
983 if (!fp->rx_cons_sb)
984 continue;
985
523224a3 986 /* Rx */
51c1a580 987 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 988 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 989 fp->rx_comp_prod,
66e855f3 990 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 991 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 992 fp->rx_sge_prod, fp->last_max_sge,
523224a3 993 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 994
523224a3 995 /* Tx */
6383c0b3
AE		 996 for_each_cos_in_tx_queue(fp, cos)
997 {
1fc3de94 998 if (!fp->txdata_ptr[cos])
e2611998
YM		 999 break;
1000
65565884 1001 txdata = *fp->txdata_ptr[cos];
e2611998
YM		 1002
1003 if (!txdata.tx_cons_sb)
1004 continue;
1005
51c1a580 1006 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 1007 i, txdata.tx_pkt_prod,
1008 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1009 txdata.tx_bd_cons,
1010 le16_to_cpu(*txdata.tx_cons_sb));
1011 }
523224a3 1012
619c5cb6
VZ		 1013 loop = CHIP_IS_E1x(bp) ?
1014 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1015
1016 /* host sb data */
1017
ec6ba945
VZ		 1018 if (IS_FCOE_FP(fp))
1019 continue;
55c11941 1020
523224a3
DK		 1021 BNX2X_ERR(" run indexes (");
1022 for (j = 0; j < HC_SB_MAX_SM; j++)
1023 pr_cont("0x%x%s",
1024 fp->sb_running_index[j],
1025 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1026
1027 BNX2X_ERR(" indexes (");
1028 for (j = 0; j < loop; j++)
1029 pr_cont("0x%x%s",
1030 fp->sb_index_values[j],
1031 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1032
1033 /* VF cannot access FW refelection for status block */
1034 if (IS_VF(bp))
1035 continue;
1036
523224a3 1037 /* fw sb data */
619c5cb6
VZ		 1038 data_size = CHIP_IS_E1x(bp) ?
1039 sizeof(struct hc_status_block_data_e1x) :
1040 sizeof(struct hc_status_block_data_e2);
523224a3 1041 data_size /= sizeof(u32);
619c5cb6
VZ		 1042 sb_data_p = CHIP_IS_E1x(bp) ?
1043 (u32 *)&sb_data_e1x :
1044 (u32 *)&sb_data_e2;
523224a3
DK		 1045 /* copy sb data in here */
1046 for (j = 0; j < data_size; j++)
1047 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1048 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1049 j * sizeof(u32));
1050
619c5cb6 1051 if (!CHIP_IS_E1x(bp)) {
51c1a580 1052 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1053 sb_data_e2.common.p_func.pf_id,
1054 sb_data_e2.common.p_func.vf_id,
1055 sb_data_e2.common.p_func.vf_valid,
1056 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1057 sb_data_e2.common.same_igu_sb_1b,
1058 sb_data_e2.common.state);
f2e0899f 1059 } else {
51c1a580 1060 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1061 sb_data_e1x.common.p_func.pf_id,
1062 sb_data_e1x.common.p_func.vf_id,
1063 sb_data_e1x.common.p_func.vf_valid,
1064 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1065 sb_data_e1x.common.same_igu_sb_1b,
1066 sb_data_e1x.common.state);
f2e0899f 1067 }
523224a3
DK		 1068
1069 /* SB_SMs data */
1070 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1071 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1072 j, hc_sm_p[j].__flags,
1073 hc_sm_p[j].igu_sb_id,
1074 hc_sm_p[j].igu_seg_id,
1075 hc_sm_p[j].time_to_expire,
1076 hc_sm_p[j].timer_value);
523224a3
DK		 1077 }
1078
16a5fd92 1079 /* Indices data */
523224a3 1080 for (j = 0; j < loop; j++) {
51c1a580 1081 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1082 hc_index_p[j].flags,
1083 hc_index_p[j].timeout);
1084 }
8440d2b6 1085 }
a2fbb9ea 1086
523224a3 1087#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1088 if (IS_PF(bp)) {
1089 /* event queue */
1090 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1091 for (i = 0; i < NUM_EQ_DESC; i++) {
1092 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1093
1094 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1095 i, bp->eq_ring[i].message.opcode,
1096 bp->eq_ring[i].message.error);
1097 BNX2X_ERR("data: %x %x %x\n",
1098 data[0], data[1], data[2]);
1099 }
04c46736
YM		 1100 }
1101
8440d2b6
EG		 1102 /* Rings */
1103 /* Rx */
55c11941 1104 for_each_valid_rx_queue(bp, i) {
8440d2b6 1105 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1106
e2611998
YM		 1107 if (!bp->fp)
1108 break;
1109
1110 if (!fp->rx_cons_sb)
1111 continue;
1112
a2fbb9ea
ET		 1113 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1114 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1115 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1116 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1117 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1118
c3eefaf6 1119 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1120 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1121 }
1122
3196a88a
EG		 1123 start = RX_SGE(fp->rx_sge_prod);
1124 end = RX_SGE(fp->last_max_sge);
8440d2b6 1125 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1126 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1127 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1128
c3eefaf6
EG		 1129 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1130 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1131 }
1132
a2fbb9ea
ET		 1133 start = RCQ_BD(fp->rx_comp_cons - 10);
1134 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1135 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1136 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1137
c3eefaf6
EG		 1138 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1139 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1140 }
1141 }
1142
8440d2b6 1143 /* Tx */
55c11941 1144 for_each_valid_tx_queue(bp, i) {
8440d2b6 1145 struct bnx2x_fastpath *fp = &bp->fp[i];
e2611998
YM		 1146
1147 if (!bp->fp)
1148 break;
1149
6383c0b3 1150 for_each_cos_in_tx_queue(fp, cos) {
65565884 1151 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3 1152
1fc3de94 1153 if (!fp->txdata_ptr[cos])
e2611998
YM		 1154 break;
1155
ea36475a 1156 if (!txdata->tx_cons_sb)
e2611998
YM		 1157 continue;
1158
6383c0b3
AE		 1159 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1160 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1161 for (j = start; j != end; j = TX_BD(j + 1)) {
1162 struct sw_tx_bd *sw_bd =
1163 &txdata->tx_buf_ring[j];
1164
51c1a580 1165 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1166 i, cos, j, sw_bd->skb,
1167 sw_bd->first_bd);
1168 }
8440d2b6 1169
6383c0b3
AE		 1170 start = TX_BD(txdata->tx_bd_cons - 10);
1171 end = TX_BD(txdata->tx_bd_cons + 254);
1172 for (j = start; j != end; j = TX_BD(j + 1)) {
1173 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1174
51c1a580 1175 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1176 i, cos, j, tx_bd[0], tx_bd[1],
1177 tx_bd[2], tx_bd[3]);
1178 }
8440d2b6
EG		 1179 }
1180 }
523224a3 1181#endif
0155a27c
YM		 1182 if (IS_PF(bp)) {
1183 bnx2x_fw_dump(bp);
1184 bnx2x_mc_assert(bp);
1185 }
a2fbb9ea 1186 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1187}
1188
619c5cb6
VZ		 1189/*
1190 * FLR Support for E2
1191 *
1192 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1193 * initialization.
1194 */
16a5fd92 1195#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1196#define FLR_WAIT_INTERVAL 50 /* usec */
1197#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1198
1199struct pbf_pN_buf_regs {
1200 int pN;
1201 u32 init_crd;
1202 u32 crd;
1203 u32 crd_freed;
1204};
1205
1206struct pbf_pN_cmd_regs {
1207 int pN;
1208 u32 lines_occup;
1209 u32 lines_freed;
1210};
1211
1212static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1213 struct pbf_pN_buf_regs *regs,
1214 u32 poll_count)
1215{
1216 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1217 u32 cur_cnt = poll_count;
1218
1219 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1220 crd = crd_start = REG_RD(bp, regs->crd);
1221 init_crd = REG_RD(bp, regs->init_crd);
1222
1223 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1224 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1225 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1226
1227 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1228 (init_crd - crd_start))) {
1229 if (cur_cnt--) {
89db4ad8 1230 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1231 crd = REG_RD(bp, regs->crd);
1232 crd_freed = REG_RD(bp, regs->crd_freed);
1233 } else {
1234 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1235 regs->pN);
1236 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1237 regs->pN, crd);
1238 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1239 regs->pN, crd_freed);
1240 break;
1241 }
1242 }
1243 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1244 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1245}
1246
1247static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1248 struct pbf_pN_cmd_regs *regs,
1249 u32 poll_count)
1250{
1251 u32 occup, to_free, freed, freed_start;
1252 u32 cur_cnt = poll_count;
1253
1254 occup = to_free = REG_RD(bp, regs->lines_occup);
1255 freed = freed_start = REG_RD(bp, regs->lines_freed);
1256
1257 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1258 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1259
1260 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1261 if (cur_cnt--) {
89db4ad8 1262 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1263 occup = REG_RD(bp, regs->lines_occup);
1264 freed = REG_RD(bp, regs->lines_freed);
1265 } else {
1266 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1267 regs->pN);
1268 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1269 regs->pN, occup);
1270 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1271 regs->pN, freed);
1272 break;
1273 }
1274 }
1275 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1276 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1277}
1278
1191cb83
ED		 1279static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1280 u32 expected, u32 poll_count)
619c5cb6
VZ		 1281{
1282 u32 cur_cnt = poll_count;
1283 u32 val;
1284
1285 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1286 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1287
1288 return val;
1289}
1290
d16132ce
AE		 1291int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1292 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1293{
1294 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1295 if (val != 0) {
1296 BNX2X_ERR("%s usage count=%d\n", msg, val);
1297 return 1;
1298 }
1299 return 0;
1300}
1301
d16132ce
AE		 1302/* Common routines with VF FLR cleanup */
1303u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1304{
1305 /* adjust polling timeout */
1306 if (CHIP_REV_IS_EMUL(bp))
1307 return FLR_POLL_CNT * 2000;
1308
1309 if (CHIP_REV_IS_FPGA(bp))
1310 return FLR_POLL_CNT * 120;
1311
1312 return FLR_POLL_CNT;
1313}
1314
d16132ce 1315void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1316{
1317 struct pbf_pN_cmd_regs cmd_regs[] = {
1318 {0, (CHIP_IS_E3B0(bp)) ?
1319 PBF_REG_TQ_OCCUPANCY_Q0 :
1320 PBF_REG_P0_TQ_OCCUPANCY,
1321 (CHIP_IS_E3B0(bp)) ?
1322 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1323 PBF_REG_P0_TQ_LINES_FREED_CNT},
1324 {1, (CHIP_IS_E3B0(bp)) ?
1325 PBF_REG_TQ_OCCUPANCY_Q1 :
1326 PBF_REG_P1_TQ_OCCUPANCY,
1327 (CHIP_IS_E3B0(bp)) ?
1328 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1329 PBF_REG_P1_TQ_LINES_FREED_CNT},
1330 {4, (CHIP_IS_E3B0(bp)) ?
1331 PBF_REG_TQ_OCCUPANCY_LB_Q :
1332 PBF_REG_P4_TQ_OCCUPANCY,
1333 (CHIP_IS_E3B0(bp)) ?
1334 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1335 PBF_REG_P4_TQ_LINES_FREED_CNT}
1336 };
1337
1338 struct pbf_pN_buf_regs buf_regs[] = {
1339 {0, (CHIP_IS_E3B0(bp)) ?
1340 PBF_REG_INIT_CRD_Q0 :
1341 PBF_REG_P0_INIT_CRD ,
1342 (CHIP_IS_E3B0(bp)) ?
1343 PBF_REG_CREDIT_Q0 :
1344 PBF_REG_P0_CREDIT,
1345 (CHIP_IS_E3B0(bp)) ?
1346 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1347 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1348 {1, (CHIP_IS_E3B0(bp)) ?
1349 PBF_REG_INIT_CRD_Q1 :
1350 PBF_REG_P1_INIT_CRD,
1351 (CHIP_IS_E3B0(bp)) ?
1352 PBF_REG_CREDIT_Q1 :
1353 PBF_REG_P1_CREDIT,
1354 (CHIP_IS_E3B0(bp)) ?
1355 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1356 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1357 {4, (CHIP_IS_E3B0(bp)) ?
1358 PBF_REG_INIT_CRD_LB_Q :
1359 PBF_REG_P4_INIT_CRD,
1360 (CHIP_IS_E3B0(bp)) ?
1361 PBF_REG_CREDIT_LB_Q :
1362 PBF_REG_P4_CREDIT,
1363 (CHIP_IS_E3B0(bp)) ?
1364 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1365 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1366 };
1367
1368 int i;
1369
1370 /* Verify the command queues are flushed P0, P1, P4 */
1371 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1372 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1373
619c5cb6
VZ		 1374 /* Verify the transmission buffers are flushed P0, P1, P4 */
1375 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1376 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1377}
1378
1379#define OP_GEN_PARAM(param) \
1380 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1381
1382#define OP_GEN_TYPE(type) \
1383 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1384
1385#define OP_GEN_AGG_VECT(index) \
1386 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1387
d16132ce 1388int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1389{
86564c3f 1390 u32 op_gen_command = 0;
619c5cb6
VZ		 1391 u32 comp_addr = BAR_CSTRORM_INTMEM +
1392 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1393 int ret = 0;
1394
1395 if (REG_RD(bp, comp_addr)) {
89db4ad8 1396 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1397 return 1;
1398 }
1399
86564c3f
YM		 1400 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1401 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1402 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1403 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1404
89db4ad8 1405 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1406 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1407
1408 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1409 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1410 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1411 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1412 bnx2x_panic();
1413 return 1;
619c5cb6 1414 }
16a5fd92 1415 /* Zero completion for next FLR */
619c5cb6
VZ		 1416 REG_WR(bp, comp_addr, 0);
1417
1418 return ret;
1419}
1420
b56e9670 1421u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1422{
619c5cb6
VZ		 1423 u16 status;
1424
2a80eebc 1425 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1426 return status & PCI_EXP_DEVSTA_TRPND;
1427}
1428
1429/* PF FLR specific routines
1430*/
1431static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1432{
619c5cb6
VZ		 1433 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1434 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1435 CFC_REG_NUM_LCIDS_INSIDE_PF,
1436 "CFC PF usage counter timed out",
1437 poll_cnt))
1438 return 1;
1439
619c5cb6
VZ		 1440 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1441 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1442 DORQ_REG_PF_USAGE_CNT,
1443 "DQ PF usage counter timed out",
1444 poll_cnt))
1445 return 1;
1446
1447 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1448 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1449 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1450 "QM PF usage counter timed out",
1451 poll_cnt))
1452 return 1;
1453
1454 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1455 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1456 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1457 "Timers VNIC usage counter timed out",
1458 poll_cnt))
1459 return 1;
1460 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1461 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1462 "Timers NUM_SCANS usage counter timed out",
1463 poll_cnt))
1464 return 1;
1465
1466 /* Wait DMAE PF usage counter to zero */
1467 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1468 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1469 "DMAE command register timed out",
619c5cb6
VZ		 1470 poll_cnt))
1471 return 1;
1472
1473 return 0;
1474}
1475
1476static void bnx2x_hw_enable_status(struct bnx2x *bp)
1477{
1478 u32 val;
1479
1480 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1481 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1482
1483 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1484 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1485
1486 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1487 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1488
1489 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1490 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1491
1492 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1493 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1494
1495 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1496 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1497
1498 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1499 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1500
1501 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1502 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1503 val);
1504}
1505
1506static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1507{
1508 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1509
1510 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1511
1512 /* Re-enable PF target read access */
1513 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1514
1515 /* Poll HW usage counters */
89db4ad8 1516 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1517 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1518 return -EBUSY;
1519
1520 /* Zero the igu 'trailing edge' and 'leading edge' */
1521
1522 /* Send the FW cleanup command */
1523 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1524 return -EBUSY;
1525
1526 /* ATC cleanup */
1527
1528 /* Verify TX hw is flushed */
1529 bnx2x_tx_hw_flushed(bp, poll_cnt);
1530
1531 /* Wait 100ms (not adjusted according to platform) */
1532 msleep(100);
1533
1534 /* Verify no pending pci transactions */
1535 if (bnx2x_is_pcie_pending(bp->pdev))
1536 BNX2X_ERR("PCIE Transactions still pending\n");
1537
1538 /* Debug */
1539 bnx2x_hw_enable_status(bp);
1540
1541 /*
1542 * Master enable - Due to WB DMAE writes performed before this
1543 * register is re-initialized as part of the regular function init
1544 */
1545 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1546
1547 return 0;
1548}
1549
f2e0899f 1550static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1551{
34f80b04 1552 int port = BP_PORT(bp);
a2fbb9ea
ET		 1553 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1554 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1555 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1556 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1557 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1558
1559 if (msix) {
8badd27a
EG		 1560 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1561 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1562 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1563 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1564 if (single_msix)
1565 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1566 } else if (msi) {
1567 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1568 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1569 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1570 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1571 } else {
1572 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1573 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1574 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1575 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1576
a0fd065c 1577 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1578 DP(NETIF_MSG_IFUP,
1579 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1580
a0fd065c 1581 REG_WR(bp, addr, val);
615f8fd9 1582
a0fd065c
DK		 1583 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1584 }
a2fbb9ea
ET		 1585 }
1586
a0fd065c
DK		 1587 if (CHIP_IS_E1(bp))
1588 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1589
51c1a580
MS		 1590 DP(NETIF_MSG_IFUP,
1591 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1592 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1593
1594 REG_WR(bp, addr, val);
37dbbf32
EG		 1595 /*
1596 * Ensure that HC_CONFIG is written before leading/trailing edge config
1597 */
1598 mmiowb();
1599 barrier();
34f80b04 1600
f2e0899f 1601 if (!CHIP_IS_E1(bp)) {
34f80b04 1602 /* init leading/trailing edge */
fb3bff17 1603 if (IS_MF(bp)) {
3395a033 1604 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1605 if (bp->port.pmf)
4acac6a5
EG		 1606 /* enable nig and gpio3 attention */
1607 val |= 0x1100;
34f80b04
EG		 1608 } else
1609 val = 0xffff;
1610
1611 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1612 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1613 }
37dbbf32
EG		 1614
1615 /* Make sure that interrupts are indeed enabled from here on */
1616 mmiowb();
a2fbb9ea
ET		 1617}
1618
f2e0899f
DK		 1619static void bnx2x_igu_int_enable(struct bnx2x *bp)
1620{
1621 u32 val;
30a5de77
DK		 1622 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1623 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1624 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1625
1626 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1627
1628 if (msix) {
1629 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1630 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1631 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1632 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1633
1634 if (single_msix)
1635 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1636 } else if (msi) {
1637 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1638 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1639 IGU_PF_CONF_ATTN_BIT_EN |
1640 IGU_PF_CONF_SINGLE_ISR_EN);
1641 } else {
1642 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1643 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1644 IGU_PF_CONF_ATTN_BIT_EN |
1645 IGU_PF_CONF_SINGLE_ISR_EN);
1646 }
1647
ebe61d80
YM		 1648 /* Clean previous status - need to configure igu prior to ack*/
1649 if ((!msix) || single_msix) {
1650 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1651 bnx2x_ack_int(bp);
1652 }
1653
1654 val |= IGU_PF_CONF_FUNC_EN;
1655
51c1a580 1656 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1657 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1658
1659 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1660
79a8557a
YM		 1661 if (val & IGU_PF_CONF_INT_LINE_EN)
1662 pci_intx(bp->pdev, true);
1663
f2e0899f
DK		 1664 barrier();
1665
1666 /* init leading/trailing edge */
1667 if (IS_MF(bp)) {
3395a033 1668 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1669 if (bp->port.pmf)
1670 /* enable nig and gpio3 attention */
1671 val |= 0x1100;
1672 } else
1673 val = 0xffff;
1674
1675 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1676 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1677
1678 /* Make sure that interrupts are indeed enabled from here on */
1679 mmiowb();
1680}
1681
1682void bnx2x_int_enable(struct bnx2x *bp)
1683{
1684 if (bp->common.int_block == INT_BLOCK_HC)
1685 bnx2x_hc_int_enable(bp);
1686 else
1687 bnx2x_igu_int_enable(bp);
1688}
1689
9f6c9258 1690void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1691{
a2fbb9ea 1692 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1693 int i, offset;
a2fbb9ea 1694
f8ef6e44
YG		 1695 if (disable_hw)
1696 /* prevent the HW from sending interrupts */
1697 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1698
1699 /* make sure all ISRs are done */
1700 if (msix) {
8badd27a
EG		 1701 synchronize_irq(bp->msix_table[0].vector);
1702 offset = 1;
55c11941
MS		 1703 if (CNIC_SUPPORT(bp))
1704 offset++;
ec6ba945 1705 for_each_eth_queue(bp, i)
754a2f52 1706 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1707 } else
1708 synchronize_irq(bp->pdev->irq);
1709
1710 /* make sure sp_task is not running */
1cf167f2 1711 cancel_delayed_work(&bp->sp_task);
3deb8167 1712 cancel_delayed_work(&bp->period_task);
1cf167f2 1713 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1714}
1715
34f80b04 1716/* fast path */
a2fbb9ea
ET		 1717
1718/*
34f80b04 1719 * General service functions
a2fbb9ea
ET		 1720 */
1721
72fd0718
VZ		 1722/* Return true if succeeded to acquire the lock */
1723static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1724{
1725 u32 lock_status;
1726 u32 resource_bit = (1 << resource);
1727 int func = BP_FUNC(bp);
1728 u32 hw_lock_control_reg;
1729
51c1a580
MS		 1730 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1731 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1732
1733 /* Validating that the resource is within range */
1734 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1735 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1736 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1737 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1738 return false;
72fd0718
VZ		 1739 }
1740
1741 if (func <= 5)
1742 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1743 else
1744 hw_lock_control_reg =
1745 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1746
1747 /* Try to acquire the lock */
1748 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1749 lock_status = REG_RD(bp, hw_lock_control_reg);
1750 if (lock_status & resource_bit)
1751 return true;
1752
51c1a580
MS		 1753 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1754 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1755 return false;
1756}
1757
c9ee9206
VZ		 1758/**
1759 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1760 *
1761 * @bp: driver handle
1762 *
1763 * Returns the recovery leader resource id according to the engine this function
1764 * belongs to. Currently only only 2 engines is supported.
1765 */
1191cb83 1766static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1767{
1768 if (BP_PATH(bp))
1769 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1770 else
1771 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1772}
1773
1774/**
2de67439 1775 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1776 *
1777 * @bp: driver handle
1778 *
2de67439 1779 * Tries to acquire a leader lock for current engine.
c9ee9206 1780 */
1191cb83 1781static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1782{
1783 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1784}
1785
619c5cb6 1786static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1787
fd1fc79d
AE		 1788/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1789static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1790{
1791 /* Set the interrupt occurred bit for the sp-task to recognize it
1792 * must ack the interrupt and transition according to the IGU
1793 * state machine.
1794 */
1795 atomic_set(&bp->interrupt_occurred, 1);
1796
1797 /* The sp_task must execute only after this bit
1798 * is set, otherwise we will get out of sync and miss all
1799 * further interrupts. Hence, the barrier.
1800 */
1801 smp_wmb();
1802
1803 /* schedule sp_task to workqueue */
1804 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1805}
3196a88a 1806
619c5cb6 1807void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1808{
1809 struct bnx2x *bp = fp->bp;
1810 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1811 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1812 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1813 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1814
34f80b04 1815 DP(BNX2X_MSG_SP,
a2fbb9ea 1816 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1817 fp->index, cid, command, bp->state,
34f80b04 1818 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1819
fd1fc79d
AE		 1820 /* If cid is within VF range, replace the slowpath object with the
1821 * one corresponding to this VF
1822 */
1823 if (cid >= BNX2X_FIRST_VF_CID &&
1824 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1825 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1826
619c5cb6
VZ		 1827 switch (command) {
1828 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1829 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1830 drv_cmd = BNX2X_Q_CMD_UPDATE;
1831 break;
d6cae238 1832
619c5cb6 1833 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1834 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1835 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1836 break;
1837
6383c0b3 1838 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1839 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1840 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1841 break;
1842
619c5cb6 1843 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1844 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1845 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1846 break;
1847
619c5cb6 1848 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1849 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1850 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1851 break;
1852
619c5cb6 1853 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1854 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1855 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1856 break;
619c5cb6 1857
14a94ebd
MK		 1858 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1859 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1860 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1861 break;
1862
619c5cb6
VZ		 1863 default:
1864 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1865 command, fp->index);
1866 return;
523224a3 1867 }
3196a88a 1868
619c5cb6
VZ		 1869 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1870 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1871 /* q_obj->complete_cmd() failure means that this was
1872 * an unexpected completion.
1873 *
1874 * In this case we don't want to increase the bp->spq_left
1875 * because apparently we haven't sent this command the first
1876 * place.
1877 */
1878#ifdef BNX2X_STOP_ON_ERROR
1879 bnx2x_panic();
1880#else
1881 return;
1882#endif
1883
4e857c58 1884 smp_mb__before_atomic();
6e30dd4e 1885 atomic_inc(&bp->cq_spq_left);
619c5cb6 1886 /* push the change in bp->spq_left and towards the memory */
4e857c58 1887 smp_mb__after_atomic();
49d66772 1888
d6cae238
VZ		 1889 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1890
a3348722
BW		 1891 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1892 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1893 /* if Q update ramrod is completed for last Q in AFEX vif set
1894 * flow, then ACK MCP at the end
1895 *
1896 * mark pending ACK to MCP bit.
1897 * prevent case that both bits are cleared.
1898 * At the end of load/unload driver checks that
2de67439 1899 * sp_state is cleared, and this order prevents
a3348722
BW		 1900 * races
1901 */
4e857c58 1902 smp_mb__before_atomic();
a3348722
BW		 1903 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1904 wmb();
1905 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 1906 smp_mb__after_atomic();
a3348722 1907
fd1fc79d
AE		 1908 /* schedule the sp task as mcp ack is required */
1909 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1910 }
1911
523224a3 1912 return;
a2fbb9ea
ET		 1913}
1914
9f6c9258 1915irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1916{
555f6c78 1917 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1918 u16 status = bnx2x_ack_int(bp);
34f80b04 1919 u16 mask;
ca00392c 1920 int i;
6383c0b3 1921 u8 cos;
a2fbb9ea 1922
34f80b04 1923 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1924 if (unlikely(status == 0)) {
1925 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1926 return IRQ_NONE;
1927 }
f5372251 1928 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1929
3196a88a
EG		 1930#ifdef BNX2X_STOP_ON_ERROR
1931 if (unlikely(bp->panic))
1932 return IRQ_HANDLED;
1933#endif
1934
ec6ba945 1935 for_each_eth_queue(bp, i) {
ca00392c 1936 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1937
55c11941 1938 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1939 if (status & mask) {
619c5cb6 1940 /* Handle Rx or Tx according to SB id */
6383c0b3 1941 for_each_cos_in_tx_queue(fp, cos)
65565884 1942 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1943 prefetch(&fp->sb_running_index[SM_RX_ID]);
f5fbf115 1944 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1945 status &= ~mask;
1946 }
a2fbb9ea
ET		 1947 }
1948
55c11941
MS		 1949 if (CNIC_SUPPORT(bp)) {
1950 mask = 0x2;
1951 if (status & (mask | 0x1)) {
1952 struct cnic_ops *c_ops = NULL;
993ac7b5 1953
ad9b4359
MC		 1954 rcu_read_lock();
1955 c_ops = rcu_dereference(bp->cnic_ops);
1956 if (c_ops && (bp->cnic_eth_dev.drv_state &
1957 CNIC_DRV_STATE_HANDLES_IRQ))
1958 c_ops->cnic_handler(bp->cnic_data, NULL);
1959 rcu_read_unlock();
993ac7b5 1960
55c11941
MS		 1961 status &= ~mask;
1962 }
993ac7b5 1963 }
a2fbb9ea 1964
34f80b04 1965 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1966
1967 /* schedule sp task to perform default status block work, ack
1968 * attentions and enable interrupts.
1969 */
1970 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1971
1972 status &= ~0x1;
1973 if (!status)
1974 return IRQ_HANDLED;
1975 }
1976
cdaa7cb8
VZ		 1977 if (unlikely(status))
1978 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1979 status);
a2fbb9ea 1980
c18487ee 1981 return IRQ_HANDLED;
a2fbb9ea
ET		 1982}
1983
c18487ee
YR		 1984/* Link */
1985
1986/*
1987 * General service functions
1988 */
a2fbb9ea 1989
9f6c9258 1990int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1991{
1992 u32 lock_status;
1993 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1994 int func = BP_FUNC(bp);
1995 u32 hw_lock_control_reg;
c18487ee 1996 int cnt;
a2fbb9ea 1997
c18487ee
YR		 1998 /* Validating that the resource is within range */
1999 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2000 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2001 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2002 return -EINVAL;
2003 }
a2fbb9ea 2004
4a37fb66
YG		 2005 if (func <= 5) {
2006 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2007 } else {
2008 hw_lock_control_reg =
2009 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2010 }
2011
c18487ee 2012 /* Validating that the resource is not already taken */
4a37fb66 2013 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2014 if (lock_status & resource_bit) {
51c1a580 2015 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 2016 lock_status, resource_bit);
2017 return -EEXIST;
2018 }
a2fbb9ea 2019
46230476
EG		 2020 /* Try for 5 second every 5ms */
2021 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 2022 /* Try to acquire the lock */
4a37fb66
YG		 2023 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2024 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2025 if (lock_status & resource_bit)
2026 return 0;
a2fbb9ea 2027
639d65b8 2028 usleep_range(5000, 10000);
a2fbb9ea 2029 }
51c1a580 2030 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2031 return -EAGAIN;
2032}
a2fbb9ea 2033
c9ee9206
VZ		 2034int bnx2x_release_leader_lock(struct bnx2x *bp)
2035{
2036 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2037}
2038
9f6c9258 2039int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2040{
2041 u32 lock_status;
2042 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2043 int func = BP_FUNC(bp);
2044 u32 hw_lock_control_reg;
a2fbb9ea 2045
c18487ee
YR		 2046 /* Validating that the resource is within range */
2047 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2048 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2049 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2050 return -EINVAL;
2051 }
2052
4a37fb66
YG		 2053 if (func <= 5) {
2054 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2055 } else {
2056 hw_lock_control_reg =
2057 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2058 }
2059
c18487ee 2060 /* Validating that the resource is currently taken */
4a37fb66 2061 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2062 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2063 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2064 lock_status, resource_bit);
c18487ee 2065 return -EFAULT;
a2fbb9ea
ET		 2066 }
2067
9f6c9258
DK		 2068 REG_WR(bp, hw_lock_control_reg, resource_bit);
2069 return 0;
c18487ee 2070}
a2fbb9ea 2071
4acac6a5
EG		 2072int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2073{
2074 /* The GPIO should be swapped if swap register is set and active */
2075 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2076 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2077 int gpio_shift = gpio_num +
2078 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2079 u32 gpio_mask = (1 << gpio_shift);
2080 u32 gpio_reg;
2081 int value;
2082
2083 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2084 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2085 return -EINVAL;
2086 }
2087
2088 /* read GPIO value */
2089 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2090
2091 /* get the requested pin value */
2092 if ((gpio_reg & gpio_mask) == gpio_mask)
2093 value = 1;
2094 else
2095 value = 0;
2096
4acac6a5
EG		 2097 return value;
2098}
2099
17de50b7 2100int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2101{
2102 /* The GPIO should be swapped if swap register is set and active */
2103 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2104 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2105 int gpio_shift = gpio_num +
2106 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2107 u32 gpio_mask = (1 << gpio_shift);
2108 u32 gpio_reg;
a2fbb9ea 2109
c18487ee
YR		 2110 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2111 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2112 return -EINVAL;
2113 }
a2fbb9ea 2114
4a37fb66 2115 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2116 /* read GPIO and mask except the float bits */
2117 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2118
c18487ee
YR		 2119 switch (mode) {
2120 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2121 DP(NETIF_MSG_LINK,
2122 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2123 gpio_num, gpio_shift);
2124 /* clear FLOAT and set CLR */
2125 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2126 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2127 break;
a2fbb9ea 2128
c18487ee 2129 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2130 DP(NETIF_MSG_LINK,
2131 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2132 gpio_num, gpio_shift);
2133 /* clear FLOAT and set SET */
2134 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2135 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2136 break;
a2fbb9ea 2137
17de50b7 2138 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2139 DP(NETIF_MSG_LINK,
2140 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2141 gpio_num, gpio_shift);
2142 /* set FLOAT */
2143 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2144 break;
a2fbb9ea 2145
c18487ee
YR		 2146 default:
2147 break;
a2fbb9ea
ET		 2148 }
2149
c18487ee 2150 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2151 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2152
c18487ee 2153 return 0;
a2fbb9ea
ET		 2154}
2155
0d40f0d4
YR		 2156int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2157{
2158 u32 gpio_reg = 0;
2159 int rc = 0;
2160
2161 /* Any port swapping should be handled by caller. */
2162
2163 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2164 /* read GPIO and mask except the float bits */
2165 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2166 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2167 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2168 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2169
2170 switch (mode) {
2171 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2172 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2173 /* set CLR */
2174 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2175 break;
2176
2177 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2178 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2179 /* set SET */
2180 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2181 break;
2182
2183 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2184 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2185 /* set FLOAT */
2186 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2187 break;
2188
2189 default:
2190 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2191 rc = -EINVAL;
2192 break;
2193 }
2194
2195 if (rc == 0)
2196 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2197
2198 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2199
2200 return rc;
2201}
2202
4acac6a5
EG		 2203int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2204{
2205 /* The GPIO should be swapped if swap register is set and active */
2206 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2207 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2208 int gpio_shift = gpio_num +
2209 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2210 u32 gpio_mask = (1 << gpio_shift);
2211 u32 gpio_reg;
2212
2213 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2214 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2215 return -EINVAL;
2216 }
2217
2218 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2219 /* read GPIO int */
2220 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2221
2222 switch (mode) {
2223 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2224 DP(NETIF_MSG_LINK,
2225 "Clear GPIO INT %d (shift %d) -> output low\n",
2226 gpio_num, gpio_shift);
4acac6a5
EG		 2227 /* clear SET and set CLR */
2228 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2230 break;
2231
2232 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2233 DP(NETIF_MSG_LINK,
2234 "Set GPIO INT %d (shift %d) -> output high\n",
2235 gpio_num, gpio_shift);
4acac6a5
EG		 2236 /* clear CLR and set SET */
2237 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2238 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2239 break;
2240
2241 default:
2242 break;
2243 }
2244
2245 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2246 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2247
2248 return 0;
2249}
2250
d6d99a3f 2251static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2252{
c18487ee 2253 u32 spio_reg;
a2fbb9ea 2254
d6d99a3f
YM		 2255 /* Only 2 SPIOs are configurable */
2256 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2257 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2258 return -EINVAL;
a2fbb9ea
ET		 2259 }
2260
4a37fb66 2261 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2262 /* read SPIO and mask except the float bits */
d6d99a3f 2263 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2264
c18487ee 2265 switch (mode) {
d6d99a3f
YM		 2266 case MISC_SPIO_OUTPUT_LOW:
2267 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2268 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2269 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2270 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2271 break;
a2fbb9ea 2272
d6d99a3f
YM		 2273 case MISC_SPIO_OUTPUT_HIGH:
2274 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2275 /* clear FLOAT and set SET */
d6d99a3f
YM		 2276 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2277 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2278 break;
a2fbb9ea 2279
d6d99a3f
YM		 2280 case MISC_SPIO_INPUT_HI_Z:
2281 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2282 /* set FLOAT */
d6d99a3f 2283 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2284 break;
a2fbb9ea 2285
c18487ee
YR		 2286 default:
2287 break;
a2fbb9ea
ET		 2288 }
2289
c18487ee 2290 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2291 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2292
a2fbb9ea
ET		 2293 return 0;
2294}
2295
9f6c9258 2296void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2297{
a22f0788 2298 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1359d73c
YM		 2299
2300 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2301 ADVERTISED_Pause);
ad33ea3a
EG		 2302 switch (bp->link_vars.ieee_fc &
2303 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2304 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2305 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2306 ADVERTISED_Pause);
c18487ee 2307 break;
356e2385 2308
c18487ee 2309 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2310 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2311 break;
356e2385 2312
c18487ee 2313 default:
c18487ee
YR		 2314 break;
2315 }
2316}
f1410647 2317
cd1dfce2 2318static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2319{
cd1dfce2
YM		 2320 /* Initialize link parameters structure variables
2321 * It is recommended to turn off RX FC for jumbo frames
2322 * for better performance
2323 */
2324 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2325 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2326 else
2327 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2328}
a2fbb9ea 2329
9156b30b
DK		 2330static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2331{
2332 u32 pause_enabled = 0;
2333
2334 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2335 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2336 pause_enabled = 1;
2337
2338 REG_WR(bp, BAR_USTRORM_INTMEM +
2339 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2340 pause_enabled);
2341 }
2342
2343 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2344 pause_enabled ? "enabled" : "disabled");
2345}
2346
cd1dfce2
YM		 2347int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2348{
2349 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2350 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2351
2352 if (!BP_NOMCP(bp)) {
2353 bnx2x_set_requested_fc(bp);
4a37fb66 2354 bnx2x_acquire_phy_lock(bp);
b5bf9068 2355
a22f0788 2356 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2357 struct link_params *lp = &bp->link_params;
2358 lp->loopback_mode = LOOPBACK_XGXS;
2f43b821
YM		 2359 /* Prefer doing PHY loopback at highest speed */
2360 if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
1cb0c788 2361 if (lp->speed_cap_mask[cfx_idx] &
2f43b821 2362 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
1cb0c788 2363 lp->req_line_speed[cfx_idx] =
2f43b821
YM		 2364 SPEED_20000;
2365 else if (lp->speed_cap_mask[cfx_idx] &
2366 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2367 lp->req_line_speed[cfx_idx] =
2368 SPEED_10000;
1cb0c788
YR		 2369 else
2370 lp->req_line_speed[cfx_idx] =
2371 SPEED_1000;
2372 }
a22f0788 2373 }
b5bf9068 2374
8970b2e4
MS		 2375 if (load_mode == LOAD_LOOPBACK_EXT) {
2376 struct link_params *lp = &bp->link_params;
2377 lp->loopback_mode = LOOPBACK_EXT;
2378 }
2379
19680c48 2380 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2381
4a37fb66 2382 bnx2x_release_phy_lock(bp);
a2fbb9ea 2383
9156b30b
DK		 2384 bnx2x_init_dropless_fc(bp);
2385
3c96c68b
EG		 2386 bnx2x_calc_fc_adv(bp);
2387
cd1dfce2 2388 if (bp->link_vars.link_up) {
b5bf9068 2389 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2390 bnx2x_link_report(bp);
cd1dfce2
YM		 2391 }
2392 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2393 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2394 return rc;
2395 }
f5372251 2396 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2397 return -EINVAL;
a2fbb9ea
ET		 2398}
2399
9f6c9258 2400void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2401{
19680c48 2402 if (!BP_NOMCP(bp)) {
4a37fb66 2403 bnx2x_acquire_phy_lock(bp);
19680c48 2404 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2405 bnx2x_release_phy_lock(bp);
a2fbb9ea 2406
9156b30b
DK		 2407 bnx2x_init_dropless_fc(bp);
2408
19680c48
EG		 2409 bnx2x_calc_fc_adv(bp);
2410 } else
f5372251 2411 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2412}
a2fbb9ea 2413
c18487ee
YR		 2414static void bnx2x__link_reset(struct bnx2x *bp)
2415{
19680c48 2416 if (!BP_NOMCP(bp)) {
4a37fb66 2417 bnx2x_acquire_phy_lock(bp);
5d07d868 2418 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2419 bnx2x_release_phy_lock(bp);
19680c48 2420 } else
f5372251 2421 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2422}
a2fbb9ea 2423
5d07d868
YM		 2424void bnx2x_force_link_reset(struct bnx2x *bp)
2425{
2426 bnx2x_acquire_phy_lock(bp);
2427 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2428 bnx2x_release_phy_lock(bp);
2429}
2430
a22f0788 2431u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2432{
2145a920 2433 u8 rc = 0;
a2fbb9ea 2434
2145a920
VZ		 2435 if (!BP_NOMCP(bp)) {
2436 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2437 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2438 is_serdes);
2145a920
VZ		 2439 bnx2x_release_phy_lock(bp);
2440 } else
2441 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2442
c18487ee
YR		 2443 return rc;
2444}
a2fbb9ea 2445
2691d51d
EG		 2446/* Calculates the sum of vn_min_rates.
2447 It's needed for further normalizing of the min_rates.
2448 Returns:
2449 sum of vn_min_rates.
2450 or
2451 0 - if all the min_rates are 0.
16a5fd92 2452 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2453 If not all min_rates are zero then those that are zeroes will be set to 1.
2454 */
b475d78f
YM		 2455static void bnx2x_calc_vn_min(struct bnx2x *bp,
2456 struct cmng_init_input *input)
2691d51d
EG		 2457{
2458 int all_zero = 1;
2691d51d
EG		 2459 int vn;
2460
3395a033 2461 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2462 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2463 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2464 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2465
2466 /* Skip hidden vns */
2467 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2468 vn_min_rate = 0;
2691d51d 2469 /* If min rate is zero - set it to 1 */
b475d78f 2470 else if (!vn_min_rate)
2691d51d
EG		 2471 vn_min_rate = DEF_MIN_RATE;
2472 else
2473 all_zero = 0;
2474
b475d78f 2475 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2476 }
2477
30ae438b
DK		 2478 /* if ETS or all min rates are zeros - disable fairness */
2479 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2480 input->flags.cmng_enables &=
30ae438b
DK		 2481 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2482 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2483 } else if (all_zero) {
b475d78f 2484 input->flags.cmng_enables &=
b015e3d1 2485 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2486 DP(NETIF_MSG_IFUP,
2487 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2488 } else
b475d78f 2489 input->flags.cmng_enables |=
b015e3d1 2490 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2491}
2492
b475d78f
YM		 2493static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2494 struct cmng_init_input *input)
34f80b04 2495{
b475d78f 2496 u16 vn_max_rate;
f2e0899f 2497 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2498
b475d78f 2499 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2500 vn_max_rate = 0;
b475d78f 2501 else {
faa6fcbb
DK		 2502 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2503
da3cc2da 2504 if (IS_MF_PERCENT_BW(bp)) {
faa6fcbb
DK		 2505 /* maxCfg in percents of linkspeed */
2506 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2507 } else /* SD modes */
faa6fcbb
DK		 2508 /* maxCfg is absolute in 100Mb units */
2509 vn_max_rate = maxCfg * 100;
34f80b04 2510 }
f85582f8 2511
b475d78f 2512 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2513
b475d78f 2514 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2515}
f85582f8 2516
523224a3
DK		 2517static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2518{
2519 if (CHIP_REV_IS_SLOW(bp))
2520 return CMNG_FNS_NONE;
fb3bff17 2521 if (IS_MF(bp))
523224a3
DK		 2522 return CMNG_FNS_MINMAX;
2523
2524 return CMNG_FNS_NONE;
2525}
2526
2ae17f66 2527void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2528{
0793f83f 2529 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2530
2531 if (BP_NOMCP(bp))
16a5fd92 2532 return; /* what should be the default value in this case */
523224a3 2533
0793f83f
DK		 2534 /* For 2 port configuration the absolute function number formula
2535 * is:
2536 * abs_func = 2 * vn + BP_PORT + BP_PATH
2537 *
2538 * and there are 4 functions per port
2539 *
2540 * For 4 port configuration it is
2541 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2542 *
2543 * and there are 2 functions per port
2544 */
3395a033 2545 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2546 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2547
2548 if (func >= E1H_FUNC_MAX)
2549 break;
2550
f2e0899f 2551 bp->mf_config[vn] =
523224a3
DK		 2552 MF_CFG_RD(bp, func_mf_config[func].config);
2553 }
a3348722
BW		 2554 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2555 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2556 bp->flags |= MF_FUNC_DIS;
2557 } else {
2558 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2559 bp->flags &= ~MF_FUNC_DIS;
2560 }
523224a3
DK		 2561}
2562
2563static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2564{
b475d78f
YM		 2565 struct cmng_init_input input;
2566 memset(&input, 0, sizeof(struct cmng_init_input));
2567
2568 input.port_rate = bp->link_vars.line_speed;
523224a3 2569
568e2426 2570 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2571 int vn;
2572
523224a3
DK		 2573 /* read mf conf from shmem */
2574 if (read_cfg)
2575 bnx2x_read_mf_cfg(bp);
2576
523224a3 2577 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2578 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2579
2580 /* calculate and set min-max rate for each vn */
c4154f25 2581 if (bp->port.pmf)
3395a033 2582 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2583 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2584
2585 /* always enable rate shaping and fairness */
b475d78f 2586 input.flags.cmng_enables |=
523224a3 2587 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2588
2589 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2590 return;
2591 }
2592
2593 /* rate shaping and fairness are disabled */
2594 DP(NETIF_MSG_IFUP,
2595 "rate shaping and fairness are disabled\n");
2596}
34f80b04 2597
1191cb83
ED		 2598static void storm_memset_cmng(struct bnx2x *bp,
2599 struct cmng_init *cmng,
2600 u8 port)
2601{
2602 int vn;
2603 size_t size = sizeof(struct cmng_struct_per_port);
2604
2605 u32 addr = BAR_XSTRORM_INTMEM +
2606 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2607
2608 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2609
2610 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2611 int func = func_by_vn(bp, vn);
2612
2613 addr = BAR_XSTRORM_INTMEM +
2614 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2615 size = sizeof(struct rate_shaping_vars_per_vn);
2616 __storm_memset_struct(bp, addr, size,
2617 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2618
2619 addr = BAR_XSTRORM_INTMEM +
2620 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2621 size = sizeof(struct fairness_vars_per_vn);
2622 __storm_memset_struct(bp, addr, size,
2623 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2624 }
2625}
2626
568e2426
DK		 2627/* init cmng mode in HW according to local configuration */
2628void bnx2x_set_local_cmng(struct bnx2x *bp)
2629{
2630 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2631
2632 if (cmng_fns != CMNG_FNS_NONE) {
2633 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2634 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2635 } else {
2636 /* rate shaping and fairness are disabled */
2637 DP(NETIF_MSG_IFUP,
2638 "single function mode without fairness\n");
2639 }
2640}
2641
c18487ee
YR		 2642/* This function is called upon link interrupt */
2643static void bnx2x_link_attn(struct bnx2x *bp)
2644{
bb2a0f7a
YG		 2645 /* Make sure that we are synced with the current statistics */
2646 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2647
c18487ee 2648 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2649
9156b30b 2650 bnx2x_init_dropless_fc(bp);
1c06328c 2651
9156b30b 2652 if (bp->link_vars.link_up) {
1c06328c 2653
619c5cb6 2654 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2655 struct host_port_stats *pstats;
2656
2657 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2658 /* reset old mac stats */
bb2a0f7a
YG		 2659 memset(&(pstats->mac_stx[0]), 0,
2660 sizeof(struct mac_stx));
2661 }
f34d28ea 2662 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2663 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2664 }
2665
568e2426
DK		 2666 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2667 bnx2x_set_local_cmng(bp);
9fdc3e95 2668
2ae17f66
VZ		 2669 __bnx2x_link_report(bp);
2670
9fdc3e95
DK		 2671 if (IS_MF(bp))
2672 bnx2x_link_sync_notify(bp);
c18487ee 2673}
a2fbb9ea 2674
9f6c9258 2675void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2676{
2ae17f66 2677 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2678 return;
a2fbb9ea 2679
00253a8c 2680 /* read updated dcb configuration */
ad5afc89
AE		 2681 if (IS_PF(bp)) {
2682 bnx2x_dcbx_pmf_update(bp);
2683 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2684 if (bp->link_vars.link_up)
2685 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2686 else
2687 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2688 /* indicate link status */
2689 bnx2x_link_report(bp);
a2fbb9ea 2690
ad5afc89
AE		 2691 } else { /* VF */
2692 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2693 SUPPORTED_10baseT_Full |
2694 SUPPORTED_100baseT_Half |
2695 SUPPORTED_100baseT_Full |
2696 SUPPORTED_1000baseT_Full |
2697 SUPPORTED_2500baseX_Full |
2698 SUPPORTED_10000baseT_Full |
2699 SUPPORTED_TP |
2700 SUPPORTED_FIBRE |
2701 SUPPORTED_Autoneg |
2702 SUPPORTED_Pause |
2703 SUPPORTED_Asym_Pause);
2704 bp->port.advertising[0] = bp->port.supported[0];
2705
2706 bp->link_params.bp = bp;
2707 bp->link_params.port = BP_PORT(bp);
2708 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2709 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2710 bp->link_params.req_line_speed[0] = SPEED_10000;
2711 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2712 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2713 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2714 bp->link_vars.line_speed = SPEED_10000;
2715 bp->link_vars.link_status =
2716 (LINK_STATUS_LINK_UP |
2717 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2718 bp->link_vars.link_up = 1;
2719 bp->link_vars.duplex = DUPLEX_FULL;
2720 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2721 __bnx2x_link_report(bp);
6495d15a
DK		 2722
2723 bnx2x_sample_bulletin(bp);
2724
2725 /* if bulletin board did not have an update for link status
2726 * __bnx2x_link_report will report current status
2727 * but it will NOT duplicate report in case of already reported
2728 * during sampling bulletin board.
2729 */
bb2a0f7a 2730 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2731 }
a2fbb9ea 2732}
a2fbb9ea 2733
a3348722
BW		 2734static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2735 u16 vlan_val, u8 allowed_prio)
2736{
86564c3f 2737 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2738 struct bnx2x_func_afex_update_params *f_update_params =
2739 &func_params.params.afex_update;
2740
2741 func_params.f_obj = &bp->func_obj;
2742 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2743
2744 /* no need to wait for RAMROD completion, so don't
2745 * set RAMROD_COMP_WAIT flag
2746 */
2747
2748 f_update_params->vif_id = vifid;
2749 f_update_params->afex_default_vlan = vlan_val;
2750 f_update_params->allowed_priorities = allowed_prio;
2751
2752 /* if ramrod can not be sent, response to MCP immediately */
2753 if (bnx2x_func_state_change(bp, &func_params) < 0)
2754 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2755
2756 return 0;
2757}
2758
2759static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2760 u16 vif_index, u8 func_bit_map)
2761{
86564c3f 2762 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2763 struct bnx2x_func_afex_viflists_params *update_params =
2764 &func_params.params.afex_viflists;
2765 int rc;
2766 u32 drv_msg_code;
2767
2768 /* validate only LIST_SET and LIST_GET are received from switch */
2769 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2770 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2771 cmd_type);
2772
2773 func_params.f_obj = &bp->func_obj;
2774 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2775
2776 /* set parameters according to cmd_type */
2777 update_params->afex_vif_list_command = cmd_type;
86564c3f 2778 update_params->vif_list_index = vif_index;
a3348722
BW		 2779 update_params->func_bit_map =
2780 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2781 update_params->func_to_clear = 0;
2782 drv_msg_code =
2783 (cmd_type == VIF_LIST_RULE_GET) ?
2784 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2785 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2786
2787 /* if ramrod can not be sent, respond to MCP immediately for
2788 * SET and GET requests (other are not triggered from MCP)
2789 */
2790 rc = bnx2x_func_state_change(bp, &func_params);
2791 if (rc < 0)
2792 bnx2x_fw_command(bp, drv_msg_code, 0);
2793
2794 return 0;
2795}
2796
2797static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2798{
2799 struct afex_stats afex_stats;
2800 u32 func = BP_ABS_FUNC(bp);
2801 u32 mf_config;
2802 u16 vlan_val;
2803 u32 vlan_prio;
2804 u16 vif_id;
2805 u8 allowed_prio;
2806 u8 vlan_mode;
2807 u32 addr_to_write, vifid, addrs, stats_type, i;
2808
2809 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2810 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2811 DP(BNX2X_MSG_MCP,
2812 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2813 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2814 }
2815
2816 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2817 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2818 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2819 DP(BNX2X_MSG_MCP,
2820 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2821 vifid, addrs);
2822 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2823 addrs);
2824 }
2825
2826 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2827 addr_to_write = SHMEM2_RD(bp,
2828 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2829 stats_type = SHMEM2_RD(bp,
2830 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2831
2832 DP(BNX2X_MSG_MCP,
2833 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2834 addr_to_write);
2835
2836 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2837
2838 /* write response to scratchpad, for MCP */
2839 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2840 REG_WR(bp, addr_to_write + i*sizeof(u32),
2841 *(((u32 *)(&afex_stats))+i));
2842
2843 /* send ack message to MCP */
2844 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2845 }
2846
2847 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2848 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2849 bp->mf_config[BP_VN(bp)] = mf_config;
2850 DP(BNX2X_MSG_MCP,
2851 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2852 mf_config);
2853
2854 /* if VIF_SET is "enabled" */
2855 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2856 /* set rate limit directly to internal RAM */
2857 struct cmng_init_input cmng_input;
2858 struct rate_shaping_vars_per_vn m_rs_vn;
2859 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2860 u32 addr = BAR_XSTRORM_INTMEM +
2861 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2862
2863 bp->mf_config[BP_VN(bp)] = mf_config;
2864
2865 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2866 m_rs_vn.vn_counter.rate =
2867 cmng_input.vnic_max_rate[BP_VN(bp)];
2868 m_rs_vn.vn_counter.quota =
2869 (m_rs_vn.vn_counter.rate *
2870 RS_PERIODIC_TIMEOUT_USEC) / 8;
2871
2872 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2873
2874 /* read relevant values from mf_cfg struct in shmem */
2875 vif_id =
2876 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2877 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2878 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2879 vlan_val =
2880 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2881 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2882 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2883 vlan_prio = (mf_config &
2884 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2885 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2886 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2887 vlan_mode =
2888 (MF_CFG_RD(bp,
2889 func_mf_config[func].afex_config) &
2890 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2891 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2892 allowed_prio =
2893 (MF_CFG_RD(bp,
2894 func_mf_config[func].afex_config) &
2895 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2896 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2897
2898 /* send ramrod to FW, return in case of failure */
2899 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2900 allowed_prio))
2901 return;
2902
2903 bp->afex_def_vlan_tag = vlan_val;
2904 bp->afex_vlan_mode = vlan_mode;
2905 } else {
2906 /* notify link down because BP->flags is disabled */
2907 bnx2x_link_report(bp);
2908
2909 /* send INVALID VIF ramrod to FW */
2910 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2911
2912 /* Reset the default afex VLAN */
2913 bp->afex_def_vlan_tag = -1;
2914 }
2915 }
2916}
2917
7609647e
YM		 2918static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2919{
2920 struct bnx2x_func_switch_update_params *switch_update_params;
2921 struct bnx2x_func_state_params func_params;
2922
2923 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2924 switch_update_params = &func_params.params.switch_update;
2925 func_params.f_obj = &bp->func_obj;
2926 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2927
230d00eb 2928 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
7609647e
YM		 2929 int func = BP_ABS_FUNC(bp);
2930 u32 val;
2931
2932 /* Re-learn the S-tag from shmem */
2933 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2934 FUNC_MF_CFG_E1HOV_TAG_MASK;
2935 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2936 bp->mf_ov = val;
2937 } else {
2938 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2939 goto fail;
2940 }
2941
2942 /* Configure new S-tag in LLH */
2943 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2944 bp->mf_ov);
2945
2946 /* Send Ramrod to update FW of change */
2947 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2948 &switch_update_params->changes);
2949 switch_update_params->vlan = bp->mf_ov;
2950
2951 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2952 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2953 bp->mf_ov);
2954 goto fail;
230d00eb
YM		 2955 } else {
2956 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2957 bp->mf_ov);
7609647e 2958 }
230d00eb
YM		 2959 } else {
2960 goto fail;
7609647e
YM		 2961 }
2962
230d00eb
YM		 2963 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2964 return;
7609647e
YM		 2965fail:
2966 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2967}
2968
34f80b04
EG		 2969static void bnx2x_pmf_update(struct bnx2x *bp)
2970{
2971 int port = BP_PORT(bp);
2972 u32 val;
2973
2974 bp->port.pmf = 1;
51c1a580 2975 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2976
3deb8167
YR		 2977 /*
2978 * We need the mb() to ensure the ordering between the writing to
2979 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2980 */
2981 smp_mb();
2982
2983 /* queue a periodic task */
2984 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2985
ef01854e
DK		 2986 bnx2x_dcbx_pmf_update(bp);
2987
34f80b04 2988 /* enable nig attention */
3395a033 2989 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2990 if (bp->common.int_block == INT_BLOCK_HC) {
2991 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2992 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2993 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2994 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2995 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2996 }
bb2a0f7a
YG		 2997
2998 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2999}
3000
c18487ee 3001/* end of Link */
a2fbb9ea
ET		 3002
3003/* slow path */
3004
3005/*
3006 * General service functions
3007 */
3008
2691d51d 3009/* send the MCP a request, block until there is a reply */
a22f0788 3010u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 3011{
f2e0899f 3012 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 3013 u32 seq;
2691d51d
EG		 3014 u32 rc = 0;
3015 u32 cnt = 1;
3016 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3017
c4ff7cbf 3018 mutex_lock(&bp->fw_mb_mutex);
a5971d43 3019 seq = ++bp->fw_seq;
f2e0899f
DK		 3020 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3021 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3022
754a2f52
DK		 3023 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3024 (command | seq), param);
2691d51d
EG		 3025
3026 do {
3027 /* let the FW do it's magic ... */
3028 msleep(delay);
3029
f2e0899f 3030 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 3031
c4ff7cbf
EG		 3032 /* Give the FW up to 5 second (500*10ms) */
3033 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 3034
3035 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3036 cnt*delay, rc, seq);
3037
3038 /* is this a reply to our command? */
3039 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3040 rc &= FW_MSG_CODE_MASK;
3041 else {
3042 /* FW BUG! */
3043 BNX2X_ERR("FW failed to respond!\n");
3044 bnx2x_fw_dump(bp);
3045 rc = 0;
3046 }
c4ff7cbf 3047 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 3048
3049 return rc;
3050}
3051
1191cb83
ED		 3052static void storm_memset_func_cfg(struct bnx2x *bp,
3053 struct tstorm_eth_function_common_config *tcfg,
3054 u16 abs_fid)
3055{
3056 size_t size = sizeof(struct tstorm_eth_function_common_config);
3057
3058 u32 addr = BAR_TSTRORM_INTMEM +
3059 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3060
3061 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3062}
3063
619c5cb6
VZ		 3064void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3065{
3066 if (CHIP_IS_E1x(bp)) {
3067 struct tstorm_eth_function_common_config tcfg = {0};
3068
3069 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3070 }
3071
3072 /* Enable the function in the FW */
3073 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3074 storm_memset_func_en(bp, p->func_id, 1);
3075
3076 /* spq */
05cc5a39 3077 if (p->spq_active) {
619c5cb6
VZ		 3078 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3079 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3080 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3081 }
3082}
3083
6383c0b3 3084/**
16a5fd92 3085 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3086 *
3087 * @bp device handle
3088 * @fp queue handle
3089 * @zero_stats TRUE if statistics zeroing is needed
3090 *
3091 * Return the flags that are common for the Tx-only and not normal connections.
3092 */
1191cb83
ED		 3093static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3094 struct bnx2x_fastpath *fp,
3095 bool zero_stats)
28912902 3096{
619c5cb6
VZ		 3097 unsigned long flags = 0;
3098
3099 /* PF driver will always initialize the Queue to an ACTIVE state */
3100 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3101
6383c0b3 3102 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3103 * parent connection). The statistics are zeroed when the parent
3104 * connection is initialized.
6383c0b3 3105 */
50f0a562
BW		 3106
3107 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3108 if (zero_stats)
3109 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3110
c14db202
YM		 3111 if (bp->flags & TX_SWITCHING)
3112 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3113
91226790 3114 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3115 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3116
823e1d90
YM		 3117#ifdef BNX2X_STOP_ON_ERROR
3118 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3119#endif
3120
6383c0b3
AE		 3121 return flags;
3122}
3123
1191cb83
ED		 3124static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3125 struct bnx2x_fastpath *fp,
3126 bool leading)
6383c0b3
AE		 3127{
3128 unsigned long flags = 0;
3129
619c5cb6
VZ		 3130 /* calculate other queue flags */
3131 if (IS_MF_SD(bp))
3132 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3133
a3348722 3134 if (IS_FCOE_FP(fp)) {
619c5cb6 3135 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3136 /* For FCoE - force usage of default priority (for afex) */
3137 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3138 }
523224a3 3139
7e6b4d44 3140 if (fp->mode != TPA_MODE_DISABLED) {
619c5cb6 3141 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3142 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3143 if (fp->mode == TPA_MODE_GRO)
3144 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3145 }
619c5cb6 3146
619c5cb6
VZ		 3147 if (leading) {
3148 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3149 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3150 }
523224a3 3151
619c5cb6
VZ		 3152 /* Always set HW VLAN stripping */
3153 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3154
a3348722
BW		 3155 /* configure silent vlan removal */
3156 if (IS_MF_AFEX(bp))
3157 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3158
6383c0b3 3159 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3160}
3161
619c5cb6 3162static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3163 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3164 u8 cos)
619c5cb6
VZ		 3165{
3166 gen_init->stat_id = bnx2x_stats_id(fp);
3167 gen_init->spcl_id = fp->cl_id;
3168
3169 /* Always use mini-jumbo MTU for FCoE L2 ring */
3170 if (IS_FCOE_FP(fp))
3171 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3172 else
3173 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3174
3175 gen_init->cos = cos;
02dc4025
YM		 3176
3177 gen_init->fp_hsi = ETH_FP_HSI_VERSION;
619c5cb6
VZ		 3178}
3179
3180static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3181 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3182 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3183{
619c5cb6 3184 u8 max_sge = 0;
523224a3
DK		 3185 u16 sge_sz = 0;
3186 u16 tpa_agg_size = 0;
3187
7e6b4d44 3188 if (fp->mode != TPA_MODE_DISABLED) {
dfacf138
DK		 3189 pause->sge_th_lo = SGE_TH_LO(bp);
3190 pause->sge_th_hi = SGE_TH_HI(bp);
3191
3192 /* validate SGE ring has enough to cross high threshold */
3193 WARN_ON(bp->dropless_fc &&
3194 pause->sge_th_hi + FW_PREFETCH_CNT >
3195 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3196
924d75ab 3197 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3198 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3199 SGE_PAGE_SHIFT;
3200 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3201 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3202 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3203 }
3204
3205 /* pause - not for e1 */
3206 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3207 pause->bd_th_lo = BD_TH_LO(bp);
3208 pause->bd_th_hi = BD_TH_HI(bp);
3209
3210 pause->rcq_th_lo = RCQ_TH_LO(bp);
3211 pause->rcq_th_hi = RCQ_TH_HI(bp);
3212 /*
3213 * validate that rings have enough entries to cross
3214 * high thresholds
3215 */
3216 WARN_ON(bp->dropless_fc &&
3217 pause->bd_th_hi + FW_PREFETCH_CNT >
3218 bp->rx_ring_size);
3219 WARN_ON(bp->dropless_fc &&
3220 pause->rcq_th_hi + FW_PREFETCH_CNT >
3221 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3222
523224a3
DK		 3223 pause->pri_map = 1;
3224 }
3225
3226 /* rxq setup */
523224a3
DK		 3227 rxq_init->dscr_map = fp->rx_desc_mapping;
3228 rxq_init->sge_map = fp->rx_sge_mapping;
3229 rxq_init->rcq_map = fp->rx_comp_mapping;
3230 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3231
619c5cb6
VZ		 3232 /* This should be a maximum number of data bytes that may be
3233 * placed on the BD (not including paddings).
3234 */
e52fcb24 3235 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3236 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3237
523224a3 3238 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3239 rxq_init->tpa_agg_sz = tpa_agg_size;
3240 rxq_init->sge_buf_sz = sge_sz;
3241 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3242 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3243 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3244
3245 /* Maximum number or simultaneous TPA aggregation for this Queue.
3246 *
2de67439 3247 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3248 * VF driver(s) may want to define it to a smaller value.
3249 */
dfacf138 3250 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3251
523224a3
DK		 3252 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3253 rxq_init->fw_sb_id = fp->fw_sb_id;
3254
ec6ba945
VZ		 3255 if (IS_FCOE_FP(fp))
3256 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3257 else
6383c0b3 3258 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3259 /* configure silent vlan removal
3260 * if multi function mode is afex, then mask default vlan
3261 */
3262 if (IS_MF_AFEX(bp)) {
3263 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3264 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3265 }
523224a3
DK		 3266}
3267
619c5cb6 3268static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3269 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3270 u8 cos)
523224a3 3271{
65565884 3272 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3273 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3274 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3275 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3276
619c5cb6 3277 /*
16a5fd92 3278 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3279 * leading RSS client id
3280 */
3281 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3282
ec6ba945
VZ		 3283 if (IS_FCOE_FP(fp)) {
3284 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3285 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3286 }
523224a3
DK		 3287}
3288
8d96286a 3289static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3290{
3291 struct bnx2x_func_init_params func_init = {0};
523224a3 3292 struct event_ring_data eq_data = { {0} };
523224a3 3293
619c5cb6 3294 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3295 /* reset IGU PF statistics: MSIX + ATTN */
3296 /* PF */
3297 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3298 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3299 (CHIP_MODE_IS_4_PORT(bp) ?
3300 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3301 /* ATTN */
3302 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3303 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3304 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3305 (CHIP_MODE_IS_4_PORT(bp) ?
3306 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3307 }
3308
05cc5a39 3309 func_init.spq_active = true;
523224a3
DK		 3310 func_init.pf_id = BP_FUNC(bp);
3311 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3312 func_init.spq_map = bp->spq_mapping;
3313 func_init.spq_prod = bp->spq_prod_idx;
3314
3315 bnx2x_func_init(bp, &func_init);
3316
3317 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3318
3319 /*
619c5cb6
VZ		 3320 * Congestion management values depend on the link rate
3321 * There is no active link so initial link rate is set to 10 Gbps.
3322 * When the link comes up The congestion management values are
3323 * re-calculated according to the actual link rate.
3324 */
523224a3
DK		 3325 bp->link_vars.line_speed = SPEED_10000;
3326 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3327
3328 /* Only the PMF sets the HW */
3329 if (bp->port.pmf)
3330 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3331
86564c3f 3332 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3333 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3334 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3335 eq_data.producer = bp->eq_prod;
3336 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3337 eq_data.sb_id = DEF_SB_ID;
3338 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3339}
3340
523224a3
DK		 3341static void bnx2x_e1h_disable(struct bnx2x *bp)
3342{
3343 int port = BP_PORT(bp);
3344
619c5cb6 3345 bnx2x_tx_disable(bp);
523224a3
DK		 3346
3347 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3348}
3349
3350static void bnx2x_e1h_enable(struct bnx2x *bp)
3351{
3352 int port = BP_PORT(bp);
3353
7609647e
YM		 3354 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3355 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
523224a3 3356
16a5fd92 3357 /* Tx queue should be only re-enabled */
523224a3
DK		 3358 netif_tx_wake_all_queues(bp->dev);
3359
3360 /*
3361 * Should not call netif_carrier_on since it will be called if the link
3362 * is up when checking for link state
3363 */
3364}
3365
1d187b34
BW		 3366#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3367
3368static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3369{
3370 struct eth_stats_info *ether_stat =
3371 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3372 struct bnx2x_vlan_mac_obj *mac_obj =
3373 &bp->sp_objs->mac_obj;
3374 int i;
1d187b34 3375
786fdf0b
DC		 3376 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3377 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3378
3ec9f9ca
AE		 3379 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3380 * mac_local field in ether_stat struct. The base address is offset by 2
3381 * bytes to account for the field being 8 bytes but a mac address is
3382 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3383 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3384 * allocated by the ether_stat struct, so the macs will land in their
3385 * proper positions.
3386 */
3387 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3388 memset(ether_stat->mac_local + i, 0,
3389 sizeof(ether_stat->mac_local[0]));
3390 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3391 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3392 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3393 ETH_ALEN);
1d187b34 3394 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3395 if (bp->dev->features & NETIF_F_RXCSUM)
3396 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3397 if (bp->dev->features & NETIF_F_TSO)
3398 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3399 ether_stat->feature_flags |= bp->common.boot_mode;
3400
3401 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3402
3403 ether_stat->txq_size = bp->tx_ring_size;
3404 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3405
fcf93a0a 3406#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3407 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3408#endif
1d187b34
BW		 3409}
3410
3411static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3412{
3413 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3414 struct fcoe_stats_info *fcoe_stat =
3415 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3416
55c11941
MS		 3417 if (!CNIC_LOADED(bp))
3418 return;
3419
3ec9f9ca 3420 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3421
3422 fcoe_stat->qos_priority =
3423 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3424
3425 /* insert FCoE stats from ramrod response */
3426 if (!NO_FCOE(bp)) {
3427 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3428 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3429 tstorm_queue_statistics;
3430
3431 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3432 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3433 xstorm_queue_statistics;
3434
3435 struct fcoe_statistics_params *fw_fcoe_stat =
3436 &bp->fw_stats_data->fcoe;
3437
86564c3f
YM		 3438 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3439 fcoe_stat->rx_bytes_lo,
3440 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3441
86564c3f
YM		 3442 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3443 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3444 fcoe_stat->rx_bytes_lo,
3445 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3446
86564c3f
YM		 3447 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3448 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3449 fcoe_stat->rx_bytes_lo,
3450 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3451
86564c3f
YM		 3452 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3453 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3454 fcoe_stat->rx_bytes_lo,
3455 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3456
86564c3f
YM		 3457 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458 fcoe_stat->rx_frames_lo,
3459 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3460
86564c3f
YM		 3461 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462 fcoe_stat->rx_frames_lo,
3463 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3464
86564c3f
YM		 3465 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466 fcoe_stat->rx_frames_lo,
3467 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3468
86564c3f
YM		 3469 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3470 fcoe_stat->rx_frames_lo,
3471 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3472
86564c3f
YM		 3473 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3474 fcoe_stat->tx_bytes_lo,
3475 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3476
86564c3f
YM		 3477 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3478 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3479 fcoe_stat->tx_bytes_lo,
3480 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3481
86564c3f
YM		 3482 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3483 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3484 fcoe_stat->tx_bytes_lo,
3485 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3486
86564c3f
YM		 3487 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3488 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3489 fcoe_stat->tx_bytes_lo,
3490 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3491
86564c3f
YM		 3492 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493 fcoe_stat->tx_frames_lo,
3494 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3495
86564c3f
YM		 3496 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497 fcoe_stat->tx_frames_lo,
3498 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3499
86564c3f
YM		 3500 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501 fcoe_stat->tx_frames_lo,
3502 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3503
86564c3f
YM		 3504 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3505 fcoe_stat->tx_frames_lo,
3506 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3507 }
3508
1d187b34
BW		 3509 /* ask L5 driver to add data to the struct */
3510 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3511}
3512
3513static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3514{
3515 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3516 struct iscsi_stats_info *iscsi_stat =
3517 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3518
55c11941
MS		 3519 if (!CNIC_LOADED(bp))
3520 return;
3521
3ec9f9ca
AE		 3522 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3523 ETH_ALEN);
1d187b34
BW		 3524
3525 iscsi_stat->qos_priority =
3526 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3527
1d187b34
BW		 3528 /* ask L5 driver to add data to the struct */
3529 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3530}
3531
0793f83f
DK		 3532/* called due to MCP event (on pmf):
3533 * reread new bandwidth configuration
3534 * configure FW
3535 * notify others function about the change
3536 */
1191cb83 3537static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3538{
3539 if (bp->link_vars.link_up) {
3540 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3541 bnx2x_link_sync_notify(bp);
3542 }
3543 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3544}
3545
1191cb83 3546static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3547{
3548 bnx2x_config_mf_bw(bp);
3549 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3550}
3551
c8c60d88
YM		 3552static void bnx2x_handle_eee_event(struct bnx2x *bp)
3553{
3554 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3555 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3556}
3557
42f8277f
YM		 3558#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3559#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3560
1d187b34
BW		 3561static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3562{
3563 enum drv_info_opcode op_code;
3564 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
42f8277f
YM		 3565 bool release = false;
3566 int wait;
1d187b34
BW		 3567
3568 /* if drv_info version supported by MFW doesn't match - send NACK */
3569 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3570 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3571 return;
3572 }
3573
3574 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3575 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3576
42f8277f
YM		 3577 /* Must prevent other flows from accessing drv_info_to_mcp */
3578 mutex_lock(&bp->drv_info_mutex);
3579
1d187b34
BW		 3580 memset(&bp->slowpath->drv_info_to_mcp, 0,
3581 sizeof(union drv_info_to_mcp));
3582
3583 switch (op_code) {
3584 case ETH_STATS_OPCODE:
3585 bnx2x_drv_info_ether_stat(bp);
3586 break;
3587 case FCOE_STATS_OPCODE:
3588 bnx2x_drv_info_fcoe_stat(bp);
3589 break;
3590 case ISCSI_STATS_OPCODE:
3591 bnx2x_drv_info_iscsi_stat(bp);
3592 break;
3593 default:
3594 /* if op code isn't supported - send NACK */
3595 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
42f8277f 3596 goto out;
1d187b34
BW		 3597 }
3598
3599 /* if we got drv_info attn from MFW then these fields are defined in
3600 * shmem2 for sure
3601 */
3602 SHMEM2_WR(bp, drv_info_host_addr_lo,
3603 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3604 SHMEM2_WR(bp, drv_info_host_addr_hi,
3605 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3606
3607 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
42f8277f
YM		 3608
3609 /* Since possible management wants both this and get_driver_version
3610 * need to wait until management notifies us it finished utilizing
3611 * the buffer.
3612 */
3613 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3614 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3615 } else if (!bp->drv_info_mng_owner) {
3616 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3617
3618 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3619 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3620
3621 /* Management is done; need to clear indication */
3622 if (indication & bit) {
3623 SHMEM2_WR(bp, mfw_drv_indication,
3624 indication & ~bit);
3625 release = true;
3626 break;
3627 }
3628
3629 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3630 }
3631 }
3632 if (!release) {
3633 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3634 bp->drv_info_mng_owner = true;
3635 }
3636
3637out:
3638 mutex_unlock(&bp->drv_info_mutex);
3639}
3640
3641static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3642{
3643 u8 vals[4];
3644 int i = 0;
3645
3646 if (bnx2x_format) {
3647 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3648 &vals[0], &vals[1], &vals[2], &vals[3]);
3649 if (i > 0)
3650 vals[0] -= '0';
3651 } else {
3652 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3653 &vals[0], &vals[1], &vals[2], &vals[3]);
3654 }
3655
3656 while (i < 4)
3657 vals[i++] = 0;
3658
3659 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3660}
3661
3662void bnx2x_update_mng_version(struct bnx2x *bp)
3663{
3664 u32 iscsiver = DRV_VER_NOT_LOADED;
3665 u32 fcoever = DRV_VER_NOT_LOADED;
3666 u32 ethver = DRV_VER_NOT_LOADED;
3667 int idx = BP_FW_MB_IDX(bp);
3668 u8 *version;
3669
3670 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3671 return;
3672
3673 mutex_lock(&bp->drv_info_mutex);
3674 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3675 if (bp->drv_info_mng_owner)
3676 goto out;
3677
3678 if (bp->state != BNX2X_STATE_OPEN)
3679 goto out;
3680
3681 /* Parse ethernet driver version */
3682 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3683 if (!CNIC_LOADED(bp))
3684 goto out;
3685
3686 /* Try getting storage driver version via cnic */
3687 memset(&bp->slowpath->drv_info_to_mcp, 0,
3688 sizeof(union drv_info_to_mcp));
3689 bnx2x_drv_info_iscsi_stat(bp);
3690 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3691 iscsiver = bnx2x_update_mng_version_utility(version, false);
3692
3693 memset(&bp->slowpath->drv_info_to_mcp, 0,
3694 sizeof(union drv_info_to_mcp));
3695 bnx2x_drv_info_fcoe_stat(bp);
3696 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3697 fcoever = bnx2x_update_mng_version_utility(version, false);
3698
3699out:
3700 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3701 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3702 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3703
3704 mutex_unlock(&bp->drv_info_mutex);
3705
3706 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3707 ethver, iscsiver, fcoever);
1d187b34
BW		 3708}
3709
c48f350f
YM		 3710void bnx2x_update_mfw_dump(struct bnx2x *bp)
3711{
c48f350f
YM		 3712 u32 drv_ver;
3713 u32 valid_dump;
3714
3715 if (!SHMEM2_HAS(bp, drv_info))
3716 return;
3717
a19a19de
AB		 3718 /* Update Driver load time, possibly broken in y2038 */
3719 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
c48f350f
YM		 3720
3721 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3722 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3723
3724 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3725
3726 /* Check & notify On-Chip dump. */
3727 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3728
3729 if (valid_dump & FIRST_DUMP_VALID)
3730 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3731
3732 if (valid_dump & SECOND_DUMP_VALID)
3733 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3734}
3735
7609647e 3736static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
523224a3 3737{
7609647e
YM		 3738 u32 cmd_ok, cmd_fail;
3739
3740 /* sanity */
3741 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3742 event & DRV_STATUS_OEM_EVENT_MASK) {
3743 BNX2X_ERR("Received simultaneous events %08x\n", event);
3744 return;
3745 }
523224a3 3746
7609647e
YM		 3747 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3748 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3749 cmd_ok = DRV_MSG_CODE_DCC_OK;
3750 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3751 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3752 cmd_ok = DRV_MSG_CODE_OEM_OK;
3753 }
523224a3 3754
7609647e
YM		 3755 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3756
3757 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3758 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3759 /* This is the only place besides the function initialization
523224a3
DK		 3760 * where the bp->flags can change so it is done without any
3761 * locks
3762 */
f2e0899f 3763 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3764 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3765 bp->flags |= MF_FUNC_DIS;
3766
3767 bnx2x_e1h_disable(bp);
3768 } else {
51c1a580 3769 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3770 bp->flags &= ~MF_FUNC_DIS;
3771
3772 bnx2x_e1h_enable(bp);
3773 }
7609647e
YM		 3774 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3775 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
523224a3 3776 }
7609647e
YM		 3777
3778 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3779 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
0793f83f 3780 bnx2x_config_mf_bw(bp);
7609647e
YM		 3781 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3782 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
523224a3
DK		 3783 }
3784
3785 /* Report results to MCP */
7609647e
YM		 3786 if (event)
3787 bnx2x_fw_command(bp, cmd_fail, 0);
523224a3 3788 else
7609647e 3789 bnx2x_fw_command(bp, cmd_ok, 0);
523224a3
DK		 3790}
3791
3792/* must be called under the spq lock */
1191cb83 3793static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3794{
3795 struct eth_spe *next_spe = bp->spq_prod_bd;
3796
3797 if (bp->spq_prod_bd == bp->spq_last_bd) {
3798 bp->spq_prod_bd = bp->spq;
3799 bp->spq_prod_idx = 0;
51c1a580 3800 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3801 } else {
3802 bp->spq_prod_bd++;
3803 bp->spq_prod_idx++;
3804 }
3805 return next_spe;
3806}
3807
3808/* must be called under the spq lock */
1191cb83 3809static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3810{
3811 int func = BP_FUNC(bp);
3812
53e51e2f
VZ		 3813 /*
3814 * Make sure that BD data is updated before writing the producer:
3815 * BD data is written to the memory, the producer is read from the
3816 * memory, thus we need a full memory barrier to ensure the ordering.
3817 */
3818 mb();
28912902 3819
523224a3 3820 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3821 bp->spq_prod_idx);
28912902
MC		 3822 mmiowb();
3823}
3824
619c5cb6
VZ		 3825/**
3826 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3827 *
3828 * @cmd: command to check
3829 * @cmd_type: command type
3830 */
1191cb83 3831static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3832{
3833 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3834 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3835 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3836 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3837 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3838 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3839 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3840 return true;
3841 else
3842 return false;
619c5cb6
VZ		 3843}
3844
619c5cb6
VZ		 3845/**
3846 * bnx2x_sp_post - place a single command on an SP ring
3847 *
3848 * @bp: driver handle
3849 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3850 * @cid: SW CID the command is related to
3851 * @data_hi: command private data address (high 32 bits)
3852 * @data_lo: command private data address (low 32 bits)
3853 * @cmd_type: command type (e.g. NONE, ETH)
3854 *
3855 * SP data is handled as if it's always an address pair, thus data fields are
3856 * not swapped to little endian in upper functions. Instead this function swaps
3857 * data as if it's two u32 fields.
3858 */
9f6c9258 3859int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3860 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3861{
28912902 3862 struct eth_spe *spe;
523224a3 3863 u16 type;
619c5cb6 3864 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3865
a2fbb9ea 3866#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3867 if (unlikely(bp->panic)) {
3868 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3869 return -EIO;
51c1a580 3870 }
a2fbb9ea
ET		 3871#endif
3872
34f80b04 3873 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3874
6e30dd4e
VZ		 3875 if (common) {
3876 if (!atomic_read(&bp->eq_spq_left)) {
3877 BNX2X_ERR("BUG! EQ ring full!\n");
3878 spin_unlock_bh(&bp->spq_lock);
3879 bnx2x_panic();
3880 return -EBUSY;
3881 }
3882 } else if (!atomic_read(&bp->cq_spq_left)) {
3883 BNX2X_ERR("BUG! SPQ ring full!\n");
3884 spin_unlock_bh(&bp->spq_lock);
3885 bnx2x_panic();
3886 return -EBUSY;
a2fbb9ea 3887 }
f1410647 3888
28912902
MC		 3889 spe = bnx2x_sp_get_next(bp);
3890
a2fbb9ea 3891 /* CID needs port number to be encoded int it */
28912902 3892 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3893 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3894 HW_CID(bp, cid));
523224a3 3895
14a94ebd
MK		 3896 /* In some cases, type may already contain the func-id
3897 * mainly in SRIOV related use cases, so we add it here only
3898 * if it's not already set.
3899 */
3900 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3901 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3902 SPE_HDR_CONN_TYPE;
3903 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3904 SPE_HDR_FUNCTION_ID);
3905 } else {
3906 type = cmd_type;
3907 }
a2fbb9ea 3908
523224a3
DK		 3909 spe->hdr.type = cpu_to_le16(type);
3910
3911 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3912 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3913
d6cae238
VZ		 3914 /*
3915 * It's ok if the actual decrement is issued towards the memory
3916 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3917 * more explicit memory barrier is needed.
d6cae238
VZ		 3918 */
3919 if (common)
3920 atomic_dec(&bp->eq_spq_left);
3921 else
3922 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3923
51c1a580
MS		 3924 DP(BNX2X_MSG_SP,
3925 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3926 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3927 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3928 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3929 HW_CID(bp, cid), data_hi, data_lo, type,
3930 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3931
28912902 3932 bnx2x_sp_prod_update(bp);
34f80b04 3933 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3934 return 0;
3935}
3936
3937/* acquire split MCP access lock register */
4a37fb66 3938static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3939{
72fd0718 3940 u32 j, val;
34f80b04 3941 int rc = 0;
a2fbb9ea
ET		 3942
3943 might_sleep();
72fd0718 3944 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3945 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3946 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3947 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3948 break;
3949
639d65b8 3950 usleep_range(5000, 10000);
a2fbb9ea 3951 }
3cdeec22 3952 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3953 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3954 rc = -EBUSY;
3955 }
3956
3957 return rc;
3958}
3959
4a37fb66
YG		 3960/* release split MCP access lock register */
3961static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3962{
3cdeec22 3963 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3964}
3965
523224a3
DK		 3966#define BNX2X_DEF_SB_ATT_IDX 0x0001
3967#define BNX2X_DEF_SB_IDX 0x0002
3968
1191cb83 3969static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3970{
523224a3 3971 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3972 u16 rc = 0;
3973
3974 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3975 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3976 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3977 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3978 }
523224a3
DK		 3979
3980 if (bp->def_idx != def_sb->sp_sb.running_index) {
3981 bp->def_idx = def_sb->sp_sb.running_index;
3982 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3983 }
523224a3 3984
16a5fd92 3985 /* Do not reorder: indices reading should complete before handling */
523224a3 3986 barrier();
a2fbb9ea
ET		 3987 return rc;
3988}
3989
3990/*
3991 * slow path service functions
3992 */
3993
3994static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3995{
34f80b04 3996 int port = BP_PORT(bp);
a2fbb9ea
ET		 3997 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3998 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3999 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4000 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 4001 u32 aeu_mask;
87942b46 4002 u32 nig_mask = 0;
f2e0899f 4003 u32 reg_addr;
a2fbb9ea 4004
a2fbb9ea
ET		 4005 if (bp->attn_state & asserted)
4006 BNX2X_ERR("IGU ERROR\n");
4007
3fcaf2e5
EG		 4008 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4009 aeu_mask = REG_RD(bp, aeu_addr);
4010
a2fbb9ea 4011 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 4012 aeu_mask, asserted);
72fd0718 4013 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 4014 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4015
3fcaf2e5
EG		 4016 REG_WR(bp, aeu_addr, aeu_mask);
4017 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 4018
3fcaf2e5 4019 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 4020 bp->attn_state |= asserted;
3fcaf2e5 4021 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 4022
4023 if (asserted & ATTN_HARD_WIRED_MASK) {
4024 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 4025
a5e9a7cf
EG		 4026 bnx2x_acquire_phy_lock(bp);
4027
877e9aa4 4028 /* save nig interrupt mask */
87942b46 4029 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 4030
361c391e
YR		 4031 /* If nig_mask is not set, no need to call the update
4032 * function.
4033 */
4034 if (nig_mask) {
4035 REG_WR(bp, nig_int_mask_addr, 0);
4036
4037 bnx2x_link_attn(bp);
4038 }
a2fbb9ea
ET		 4039
4040 /* handle unicore attn? */
4041 }
4042 if (asserted & ATTN_SW_TIMER_4_FUNC)
4043 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4044
4045 if (asserted & GPIO_2_FUNC)
4046 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4047
4048 if (asserted & GPIO_3_FUNC)
4049 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4050
4051 if (asserted & GPIO_4_FUNC)
4052 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4053
4054 if (port == 0) {
4055 if (asserted & ATTN_GENERAL_ATTN_1) {
4056 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4057 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4058 }
4059 if (asserted & ATTN_GENERAL_ATTN_2) {
4060 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4061 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4062 }
4063 if (asserted & ATTN_GENERAL_ATTN_3) {
4064 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4065 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4066 }
4067 } else {
4068 if (asserted & ATTN_GENERAL_ATTN_4) {
4069 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4070 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4071 }
4072 if (asserted & ATTN_GENERAL_ATTN_5) {
4073 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4074 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4075 }
4076 if (asserted & ATTN_GENERAL_ATTN_6) {
4077 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4078 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4079 }
4080 }
4081
4082 } /* if hardwired */
4083
f2e0899f
DK		 4084 if (bp->common.int_block == INT_BLOCK_HC)
4085 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4086 COMMAND_REG_ATTN_BITS_SET);
4087 else
4088 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4089
4090 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4091 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4092 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 4093
4094 /* now set back the mask */
a5e9a7cf 4095 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 4096 /* Verify that IGU ack through BAR was written before restoring
4097 * NIG mask. This loop should exit after 2-3 iterations max.
4098 */
4099 if (bp->common.int_block != INT_BLOCK_HC) {
4100 u32 cnt = 0, igu_acked;
4101 do {
4102 igu_acked = REG_RD(bp,
4103 IGU_REG_ATTENTION_ACK_BITS);
4104 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4105 (++cnt < MAX_IGU_ATTN_ACK_TO));
4106 if (!igu_acked)
4107 DP(NETIF_MSG_HW,
4108 "Failed to verify IGU ack on time\n");
4109 barrier();
4110 }
87942b46 4111 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 4112 bnx2x_release_phy_lock(bp);
4113 }
a2fbb9ea
ET		 4114}
4115
1191cb83 4116static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 4117{
4118 int port = BP_PORT(bp);
b7737c9b 4119 u32 ext_phy_config;
fd4ef40d 4120 /* mark the failure */
b7737c9b
YR		 4121 ext_phy_config =
4122 SHMEM_RD(bp,
4123 dev_info.port_hw_config[port].external_phy_config);
4124
4125 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4126 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 4127 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 4128 ext_phy_config);
fd4ef40d
EG		 4129
4130 /* log the failure */
51c1a580
MS		 4131 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4132 "Please contact OEM Support for assistance\n");
8304859a 4133
16a5fd92 4134 /* Schedule device reset (unload)
8304859a
AE		 4135 * This is due to some boards consuming sufficient power when driver is
4136 * up to overheat if fan fails.
4137 */
230bb0f3 4138 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
fd4ef40d 4139}
ab6ad5a4 4140
1191cb83 4141static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 4142{
34f80b04 4143 int port = BP_PORT(bp);
877e9aa4 4144 int reg_offset;
d90d96ba 4145 u32 val;
877e9aa4 4146
34f80b04
EG		 4147 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4148 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 4149
34f80b04 4150 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 4151
4152 val = REG_RD(bp, reg_offset);
4153 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4154 REG_WR(bp, reg_offset, val);
4155
4156 BNX2X_ERR("SPIO5 hw attention\n");
4157
fd4ef40d 4158 /* Fan failure attention */
d90d96ba 4159 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 4160 bnx2x_fan_failure(bp);
877e9aa4 4161 }
34f80b04 4162
3deb8167 4163 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 4164 bnx2x_acquire_phy_lock(bp);
4165 bnx2x_handle_module_detect_int(&bp->link_params);
4166 bnx2x_release_phy_lock(bp);
4167 }
4168
34f80b04
EG		 4169 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4170
4171 val = REG_RD(bp, reg_offset);
4172 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4173 REG_WR(bp, reg_offset, val);
4174
4175 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 4176 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 4177 bnx2x_panic();
4178 }
877e9aa4
ET		 4179}
4180
1191cb83 4181static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4182{
4183 u32 val;
4184
0626b899 4185 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 4186
4187 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4188 BNX2X_ERR("DB hw attention 0x%x\n", val);
4189 /* DORQ discard attention */
4190 if (val & 0x2)
4191 BNX2X_ERR("FATAL error from DORQ\n");
4192 }
34f80b04
EG		 4193
4194 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4195
4196 int port = BP_PORT(bp);
4197 int reg_offset;
4198
4199 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4200 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4201
4202 val = REG_RD(bp, reg_offset);
4203 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4204 REG_WR(bp, reg_offset, val);
4205
4206 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 4207 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 4208 bnx2x_panic();
4209 }
877e9aa4
ET		 4210}
4211
1191cb83 4212static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4213{
4214 u32 val;
4215
4216 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4217
4218 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4219 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4220 /* CFC error attention */
4221 if (val & 0x2)
4222 BNX2X_ERR("FATAL error from CFC\n");
4223 }
4224
4225 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 4226 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4227 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4228 /* RQ_USDMDP_FIFO_OVERFLOW */
4229 if (val & 0x18000)
4230 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4231
4232 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4233 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4234 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4235 }
877e9aa4 4236 }
34f80b04
EG		 4237
4238 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4239
4240 int port = BP_PORT(bp);
4241 int reg_offset;
4242
4243 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4244 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4245
4246 val = REG_RD(bp, reg_offset);
4247 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4248 REG_WR(bp, reg_offset, val);
4249
4250 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 4251 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 4252 bnx2x_panic();
4253 }
877e9aa4
ET		 4254}
4255
1191cb83 4256static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4257{
34f80b04
EG		 4258 u32 val;
4259
877e9aa4
ET		 4260 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4261
34f80b04
EG		 4262 if (attn & BNX2X_PMF_LINK_ASSERT) {
4263 int func = BP_FUNC(bp);
4264
4265 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4266 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4267 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4268 func_mf_config[BP_ABS_FUNC(bp)].config);
4269 val = SHMEM_RD(bp,
4270 func_mb[BP_FW_MB_IDX(bp)].drv_status);
7609647e
YM		 4271
4272 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4273 DRV_STATUS_OEM_EVENT_MASK))
4274 bnx2x_oem_event(bp,
4275 (val & (DRV_STATUS_DCC_EVENT_MASK |
4276 DRV_STATUS_OEM_EVENT_MASK)));
0793f83f
DK		 4277
4278 if (val & DRV_STATUS_SET_MF_BW)
4279 bnx2x_set_mf_bw(bp);
4280
1d187b34
BW		 4281 if (val & DRV_STATUS_DRV_INFO_REQ)
4282 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4283
4284 if (val & DRV_STATUS_VF_DISABLED)
370d4a26
YM		 4285 bnx2x_schedule_iov_task(bp,
4286 BNX2X_IOV_HANDLE_FLR);
d16132ce 4287
2691d51d 4288 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4289 bnx2x_pmf_update(bp);
4290
e4901dde 4291 if (bp->port.pmf &&
785b9b1a
SR		 4292 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4293 bp->dcbx_enabled > 0)
e4901dde
VZ		 4294 /* start dcbx state machine */
4295 bnx2x_dcbx_set_params(bp,
4296 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4297 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4298 bnx2x_handle_afex_cmd(bp,
4299 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4300 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4301 bnx2x_handle_eee_event(bp);
7609647e
YM		 4302
4303 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4304 bnx2x_handle_update_svid_cmd(bp);
4305
3deb8167
YR		 4306 if (bp->link_vars.periodic_flags &
4307 PERIODIC_FLAGS_LINK_EVENT) {
4308 /* sync with link */
4309 bnx2x_acquire_phy_lock(bp);
4310 bp->link_vars.periodic_flags &=
4311 ~PERIODIC_FLAGS_LINK_EVENT;
4312 bnx2x_release_phy_lock(bp);
4313 if (IS_MF(bp))
4314 bnx2x_link_sync_notify(bp);
4315 bnx2x_link_report(bp);
4316 }
4317 /* Always call it here: bnx2x_link_report() will
4318 * prevent the link indication duplication.
4319 */
4320 bnx2x__link_status_update(bp);
34f80b04 4321 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4322
4323 BNX2X_ERR("MC assert!\n");
d6cae238 4324 bnx2x_mc_assert(bp);
877e9aa4
ET		 4325 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4326 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4327 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4328 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4329 bnx2x_panic();
4330
4331 } else if (attn & BNX2X_MCP_ASSERT) {
4332
4333 BNX2X_ERR("MCP assert!\n");
4334 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4335 bnx2x_fw_dump(bp);
877e9aa4
ET		 4336
4337 } else
4338 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4339 }
4340
4341 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4342 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4343 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4344 val = CHIP_IS_E1(bp) ? 0 :
4345 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4346 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4347 }
4348 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4349 val = CHIP_IS_E1(bp) ? 0 :
4350 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4351 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4352 }
877e9aa4 4353 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4354 }
4355}
4356
c9ee9206
VZ		 4357/*
4358 * Bits map:
4359 * 0-7 - Engine0 load counter.
4360 * 8-15 - Engine1 load counter.
4361 * 16 - Engine0 RESET_IN_PROGRESS bit.
4362 * 17 - Engine1 RESET_IN_PROGRESS bit.
4363 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4364 * on the engine
4365 * 19 - Engine1 ONE_IS_LOADED.
4366 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4367 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4368 * just the one belonging to its engine).
4369 *
4370 */
4371#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4372
4373#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4374#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4375#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4376#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4377#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4378#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4379#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4380
4381/*
4382 * Set the GLOBAL_RESET bit.
4383 *
4384 * Should be run under rtnl lock
4385 */
4386void bnx2x_set_reset_global(struct bnx2x *bp)
4387{
f16da43b
AE		 4388 u32 val;
4389 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4390 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4391 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4392 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4393}
4394
4395/*
4396 * Clear the GLOBAL_RESET bit.
4397 *
4398 * Should be run under rtnl lock
4399 */
1191cb83 4400static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4401{
f16da43b
AE		 4402 u32 val;
4403 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4404 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4405 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4406 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4407}
f85582f8 4408
72fd0718 4409/*
c9ee9206
VZ		 4410 * Checks the GLOBAL_RESET bit.
4411 *
72fd0718
VZ		 4412 * should be run under rtnl lock
4413 */
1191cb83 4414static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4415{
3cdeec22 4416 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4417
4418 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4419 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4420}
4421
4422/*
4423 * Clear RESET_IN_PROGRESS bit for the current engine.
4424 *
4425 * Should be run under rtnl lock
4426 */
1191cb83 4427static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4428{
f16da43b 4429 u32 val;
c9ee9206
VZ		 4430 u32 bit = BP_PATH(bp) ?
4431 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4432 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4433 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4434
4435 /* Clear the bit */
4436 val &= ~bit;
4437 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4438
4439 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4440}
4441
4442/*
c9ee9206
VZ		 4443 * Set RESET_IN_PROGRESS for the current engine.
4444 *
72fd0718
VZ		 4445 * should be run under rtnl lock
4446 */
c9ee9206 4447void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4448{
f16da43b 4449 u32 val;
c9ee9206
VZ		 4450 u32 bit = BP_PATH(bp) ?
4451 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4452 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4453 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4454
4455 /* Set the bit */
4456 val |= bit;
4457 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4458 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4459}
4460
4461/*
c9ee9206 4462 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4463 * should be run under rtnl lock
4464 */
c9ee9206 4465bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4466{
3cdeec22 4467 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4468 u32 bit = engine ?
4469 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4470
4471 /* return false if bit is set */
4472 return (val & bit) ? false : true;
72fd0718
VZ		 4473}
4474
4475/*
889b9af3 4476 * set pf load for the current pf.
c9ee9206 4477 *
72fd0718
VZ		 4478 * should be run under rtnl lock
4479 */
889b9af3 4480void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4481{
f16da43b 4482 u32 val1, val;
c9ee9206
VZ		 4483 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4484 BNX2X_PATH0_LOAD_CNT_MASK;
4485 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4486 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4487
f16da43b
AE		 4488 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4489 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4490
51c1a580 4491 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4492
c9ee9206
VZ		 4493 /* get the current counter value */
4494 val1 = (val & mask) >> shift;
4495
889b9af3
AE		 4496 /* set bit of that PF */
4497 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4498
4499 /* clear the old value */
4500 val &= ~mask;
4501
4502 /* set the new one */
4503 val |= ((val1 << shift) & mask);
4504
4505 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4506 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4507}
4508
c9ee9206 4509/**
889b9af3 4510 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4511 *
4512 * @bp: driver handle
4513 *
4514 * Should be run under rtnl lock.
4515 * Decrements the load counter for the current engine. Returns
889b9af3 4516 * whether other functions are still loaded
72fd0718 4517 */
889b9af3 4518bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4519{
f16da43b 4520 u32 val1, val;
c9ee9206
VZ		 4521 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4522 BNX2X_PATH0_LOAD_CNT_MASK;
4523 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4524 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4525
f16da43b
AE		 4526 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4527 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4528 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4529
c9ee9206
VZ		 4530 /* get the current counter value */
4531 val1 = (val & mask) >> shift;
4532
889b9af3
AE		 4533 /* clear bit of that PF */
4534 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4535
4536 /* clear the old value */
4537 val &= ~mask;
4538
4539 /* set the new one */
4540 val |= ((val1 << shift) & mask);
4541
4542 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4543 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4544 return val1 != 0;
72fd0718
VZ		 4545}
4546
4547/*
889b9af3 4548 * Read the load status for the current engine.
c9ee9206 4549 *
72fd0718
VZ		 4550 * should be run under rtnl lock
4551 */
1191cb83 4552static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4553{
c9ee9206
VZ		 4554 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4555 BNX2X_PATH0_LOAD_CNT_MASK);
4556 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4557 BNX2X_PATH0_LOAD_CNT_SHIFT);
4558 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4559
51c1a580 4560 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4561
4562 val = (val & mask) >> shift;
4563
51c1a580
MS		 4564 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4565 engine, val);
c9ee9206 4566
889b9af3 4567 return val != 0;
72fd0718
VZ		 4568}
4569
6bf07b8e
YM		 4570static void _print_parity(struct bnx2x *bp, u32 reg)
4571{
4572 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4573}
4574
1191cb83 4575static void _print_next_block(int idx, const char *blk)
72fd0718 4576{
f1deab50 4577 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4578}
4579
4293b9f5
DK		 4580static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4581 int *par_num, bool print)
72fd0718 4582{
4293b9f5
DK		 4583 u32 cur_bit;
4584 bool res;
4585 int i;
4586
4587 res = false;
4588
72fd0718 4589 for (i = 0; sig; i++) {
4293b9f5 4590 cur_bit = (0x1UL << i);
72fd0718 4591 if (sig & cur_bit) {
4293b9f5
DK		 4592 res |= true; /* Each bit is real error! */
4593
4594 if (print) {
4595 switch (cur_bit) {
4596 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4597 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4598 _print_parity(bp,
4599 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4600 break;
4601 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4602 _print_next_block((*par_num)++,
4603 "PARSER");
6bf07b8e 4604 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4605 break;
4606 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4607 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4608 _print_parity(bp,
4609 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4610 break;
4611 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4612 _print_next_block((*par_num)++,
c9ee9206 4613 "SEARCHER");
6bf07b8e 4614 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4615 break;
4616 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4617 _print_next_block((*par_num)++, "TCM");
4618 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4619 break;
4620 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4621 _print_next_block((*par_num)++,
4622 "TSEMI");
6bf07b8e
YM		 4623 _print_parity(bp,
4624 TSEM_REG_TSEM_PRTY_STS_0);
4625 _print_parity(bp,
4626 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4627 break;
4628 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4629 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4630 _print_parity(bp, GRCBASE_XPB +
4631 PB_REG_PB_PRTY_STS);
4293b9f5 4632 break;
6bf07b8e 4633 }
72fd0718
VZ		 4634 }
4635
4636 /* Clear the bit */
4637 sig &= ~cur_bit;
4638 }
4639 }
4640
4293b9f5 4641 return res;
72fd0718
VZ		 4642}
4643
4293b9f5
DK		 4644static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4645 int *par_num, bool *global,
6bf07b8e 4646 bool print)
72fd0718 4647{
4293b9f5
DK		 4648 u32 cur_bit;
4649 bool res;
4650 int i;
4651
4652 res = false;
4653
72fd0718 4654 for (i = 0; sig; i++) {
4293b9f5 4655 cur_bit = (0x1UL << i);
72fd0718 4656 if (sig & cur_bit) {
4293b9f5 4657 res |= true; /* Each bit is real error! */
72fd0718 4658 switch (cur_bit) {
c9ee9206 4659 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4660 if (print) {
4293b9f5 4661 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4662 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4663 }
72fd0718
VZ		 4664 break;
4665 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4666 if (print) {
4293b9f5 4667 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4668 _print_parity(bp, QM_REG_QM_PRTY_STS);
4669 }
c9ee9206
VZ		 4670 break;
4671 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4672 if (print) {
4293b9f5 4673 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4674 _print_parity(bp, TM_REG_TM_PRTY_STS);
4675 }
72fd0718
VZ		 4676 break;
4677 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4678 if (print) {
4293b9f5 4679 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4680 _print_parity(bp,
4681 XSDM_REG_XSDM_PRTY_STS);
4682 }
c9ee9206
VZ		 4683 break;
4684 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4685 if (print) {
4293b9f5 4686 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4687 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4688 }
72fd0718
VZ		 4689 break;
4690 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4691 if (print) {
4293b9f5
DK		 4692 _print_next_block((*par_num)++,
4693 "XSEMI");
6bf07b8e
YM		 4694 _print_parity(bp,
4695 XSEM_REG_XSEM_PRTY_STS_0);
4696 _print_parity(bp,
4697 XSEM_REG_XSEM_PRTY_STS_1);
4698 }
72fd0718
VZ		 4699 break;
4700 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4701 if (print) {
4293b9f5 4702 _print_next_block((*par_num)++,
c9ee9206 4703 "DOORBELLQ");
6bf07b8e
YM		 4704 _print_parity(bp,
4705 DORQ_REG_DORQ_PRTY_STS);
4706 }
c9ee9206
VZ		 4707 break;
4708 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4709 if (print) {
4293b9f5 4710 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4711 if (CHIP_IS_E1x(bp)) {
4712 _print_parity(bp,
4713 NIG_REG_NIG_PRTY_STS);
4714 } else {
4715 _print_parity(bp,
4716 NIG_REG_NIG_PRTY_STS_0);
4717 _print_parity(bp,
4718 NIG_REG_NIG_PRTY_STS_1);
4719 }
4720 }
72fd0718
VZ		 4721 break;
4722 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4723 if (print)
4293b9f5 4724 _print_next_block((*par_num)++,
c9ee9206
VZ		 4725 "VAUX PCI CORE");
4726 *global = true;
72fd0718
VZ		 4727 break;
4728 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4729 if (print) {
4293b9f5
DK		 4730 _print_next_block((*par_num)++,
4731 "DEBUG");
6bf07b8e
YM		 4732 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4733 }
72fd0718
VZ		 4734 break;
4735 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4736 if (print) {
4293b9f5 4737 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4738 _print_parity(bp,
4739 USDM_REG_USDM_PRTY_STS);
4740 }
72fd0718 4741 break;
8736c826 4742 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4743 if (print) {
4293b9f5 4744 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4745 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4746 }
8736c826 4747 break;
72fd0718 4748 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4749 if (print) {
4293b9f5
DK		 4750 _print_next_block((*par_num)++,
4751 "USEMI");
6bf07b8e
YM		 4752 _print_parity(bp,
4753 USEM_REG_USEM_PRTY_STS_0);
4754 _print_parity(bp,
4755 USEM_REG_USEM_PRTY_STS_1);
4756 }
72fd0718
VZ		 4757 break;
4758 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4759 if (print) {
4293b9f5 4760 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4761 _print_parity(bp, GRCBASE_UPB +
4762 PB_REG_PB_PRTY_STS);
4763 }
72fd0718
VZ		 4764 break;
4765 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4766 if (print) {
4293b9f5 4767 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4768 _print_parity(bp,
4769 CSDM_REG_CSDM_PRTY_STS);
4770 }
72fd0718 4771 break;
8736c826 4772 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4773 if (print) {
4293b9f5 4774 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4775 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4776 }
8736c826 4777 break;
72fd0718
VZ		 4778 }
4779
4780 /* Clear the bit */
4781 sig &= ~cur_bit;
4782 }
4783 }
4784
4293b9f5 4785 return res;
72fd0718
VZ		 4786}
4787
4293b9f5
DK		 4788static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4789 int *par_num, bool print)
72fd0718 4790{
4293b9f5
DK		 4791 u32 cur_bit;
4792 bool res;
4793 int i;
4794
4795 res = false;
4796
72fd0718 4797 for (i = 0; sig; i++) {
4293b9f5 4798 cur_bit = (0x1UL << i);
72fd0718 4799 if (sig & cur_bit) {
0c23ad37 4800 res = true; /* Each bit is real error! */
4293b9f5
DK		 4801 if (print) {
4802 switch (cur_bit) {
4803 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4804 _print_next_block((*par_num)++,
4805 "CSEMI");
6bf07b8e
YM		 4806 _print_parity(bp,
4807 CSEM_REG_CSEM_PRTY_STS_0);
4808 _print_parity(bp,
4809 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4810 break;
4811 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4812 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4813 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4814 _print_parity(bp,
4815 PXP2_REG_PXP2_PRTY_STS_0);
4816 _print_parity(bp,
4817 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4818 break;
4819 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4820 _print_next_block((*par_num)++,
4821 "PXPPCICLOCKCLIENT");
4822 break;
4823 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4824 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4825 _print_parity(bp,
4826 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4827 break;
4828 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4829 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4830 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4831 break;
4832 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4833 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4834 _print_parity(bp,
4835 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4836 break;
4837 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4838 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4839 if (CHIP_IS_E1x(bp))
4840 _print_parity(bp,
4841 HC_REG_HC_PRTY_STS);
4842 else
4843 _print_parity(bp,
4844 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4845 break;
4846 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4847 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4848 _print_parity(bp,
4849 MISC_REG_MISC_PRTY_STS);
4293b9f5 4850 break;
6bf07b8e 4851 }
72fd0718
VZ		 4852 }
4853
4854 /* Clear the bit */
4855 sig &= ~cur_bit;
4856 }
4857 }
4858
4293b9f5 4859 return res;
72fd0718
VZ		 4860}
4861
4293b9f5
DK		 4862static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4863 int *par_num, bool *global,
4864 bool print)
72fd0718 4865{
4293b9f5
DK		 4866 bool res = false;
4867 u32 cur_bit;
4868 int i;
4869
72fd0718 4870 for (i = 0; sig; i++) {
4293b9f5 4871 cur_bit = (0x1UL << i);
72fd0718
VZ		 4872 if (sig & cur_bit) {
4873 switch (cur_bit) {
4874 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4875 if (print)
4293b9f5
DK		 4876 _print_next_block((*par_num)++,
4877 "MCP ROM");
c9ee9206 4878 *global = true;
0c23ad37 4879 res = true;
72fd0718
VZ		 4880 break;
4881 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4882 if (print)
4293b9f5 4883 _print_next_block((*par_num)++,
c9ee9206
VZ		 4884 "MCP UMP RX");
4885 *global = true;
0c23ad37 4886 res = true;
72fd0718
VZ		 4887 break;
4888 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4889 if (print)
4293b9f5 4890 _print_next_block((*par_num)++,
c9ee9206
VZ		 4891 "MCP UMP TX");
4892 *global = true;
0c23ad37 4893 res = true;
72fd0718
VZ		 4894 break;
4895 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
ad6afbe9 4896 (*par_num)++;
4293b9f5
DK		 4897 /* clear latched SCPAD PATIRY from MCP */
4898 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4899 1UL << 10);
72fd0718
VZ		 4900 break;
4901 }
4902
4903 /* Clear the bit */
4904 sig &= ~cur_bit;
4905 }
4906 }
4907
4293b9f5 4908 return res;
72fd0718
VZ		 4909}
4910
4293b9f5
DK		 4911static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4912 int *par_num, bool print)
8736c826 4913{
4293b9f5
DK		 4914 u32 cur_bit;
4915 bool res;
4916 int i;
4917
4918 res = false;
4919
8736c826 4920 for (i = 0; sig; i++) {
4293b9f5 4921 cur_bit = (0x1UL << i);
8736c826 4922 if (sig & cur_bit) {
0c23ad37 4923 res = true; /* Each bit is real error! */
4293b9f5
DK		 4924 if (print) {
4925 switch (cur_bit) {
4926 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4927 _print_next_block((*par_num)++,
4928 "PGLUE_B");
6bf07b8e 4929 _print_parity(bp,
4293b9f5
DK		 4930 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4931 break;
4932 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4933 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4934 _print_parity(bp,
4935 ATC_REG_ATC_PRTY_STS);
4293b9f5 4936 break;
6bf07b8e 4937 }
8736c826 4938 }
8736c826
VZ		 4939 /* Clear the bit */
4940 sig &= ~cur_bit;
4941 }
4942 }
4943
4293b9f5 4944 return res;
8736c826
VZ		 4945}
4946
1191cb83
ED		 4947static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4948 u32 *sig)
72fd0718 4949{
4293b9f5
DK		 4950 bool res = false;
4951
8736c826
VZ		 4952 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4953 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4954 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4955 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4956 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4957 int par_num = 0;
ad6afbe9 4958
51c1a580
MS		 4959 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4960 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4961 sig[0] & HW_PRTY_ASSERT_SET_0,
4962 sig[1] & HW_PRTY_ASSERT_SET_1,
4963 sig[2] & HW_PRTY_ASSERT_SET_2,
4964 sig[3] & HW_PRTY_ASSERT_SET_3,
4965 sig[4] & HW_PRTY_ASSERT_SET_4);
ad6afbe9
MC		 4966 if (print) {
4967 if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4968 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4969 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4970 (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4971 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4972 netdev_err(bp->dev,
4973 "Parity errors detected in blocks: ");
4974 } else {
4975 print = false;
4976 }
4977 }
4293b9f5
DK		 4978 res |= bnx2x_check_blocks_with_parity0(bp,
4979 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4980 res |= bnx2x_check_blocks_with_parity1(bp,
4981 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4982 res |= bnx2x_check_blocks_with_parity2(bp,
4983 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4984 res |= bnx2x_check_blocks_with_parity3(bp,
4985 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4986 res |= bnx2x_check_blocks_with_parity4(bp,
4987 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4988
c9ee9206
VZ		 4989 if (print)
4990 pr_cont("\n");
4293b9f5 4991 }
8736c826 4992
4293b9f5 4993 return res;
72fd0718
VZ		 4994}
4995
c9ee9206
VZ		 4996/**
4997 * bnx2x_chk_parity_attn - checks for parity attentions.
4998 *
4999 * @bp: driver handle
5000 * @global: true if there was a global attention
5001 * @print: show parity attention in syslog
5002 */
5003bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 5004{
8736c826 5005 struct attn_route attn = { {0} };
72fd0718
VZ		 5006 int port = BP_PORT(bp);
5007
5008 attn.sig[0] = REG_RD(bp,
5009 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5010 port*4);
5011 attn.sig[1] = REG_RD(bp,
5012 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5013 port*4);
5014 attn.sig[2] = REG_RD(bp,
5015 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5016 port*4);
5017 attn.sig[3] = REG_RD(bp,
5018 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5019 port*4);
0a5ccb75
YM		 5020 /* Since MCP attentions can't be disabled inside the block, we need to
5021 * read AEU registers to see whether they're currently disabled
5022 */
5023 attn.sig[3] &= ((REG_RD(bp,
5024 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5025 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5026 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5027 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 5028
8736c826
VZ		 5029 if (!CHIP_IS_E1x(bp))
5030 attn.sig[4] = REG_RD(bp,
5031 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5032 port*4);
5033
5034 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 5035}
5036
1191cb83 5037static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 5038{
5039 u32 val;
5040 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5041
5042 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5043 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5044 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 5045 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 5046 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 5047 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 5048 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 5049 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 5050 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 5051 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 5052 if (val &
5053 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 5054 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 5055 if (val &
5056 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 5057 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 5058 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 5059 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 5060 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 5061 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 5062 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 5063 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 5064 }
5065 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5066 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5067 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5068 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5069 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5070 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 5071 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 5072 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 5073 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 5074 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 5075 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 5076 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5077 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5078 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 5079 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 5080 }
5081
5082 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5083 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5084 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5085 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5086 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5087 }
f2e0899f
DK		 5088}
5089
72fd0718
VZ		 5090static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5091{
5092 struct attn_route attn, *group_mask;
34f80b04 5093 int port = BP_PORT(bp);
877e9aa4 5094 int index;
a2fbb9ea
ET		 5095 u32 reg_addr;
5096 u32 val;
3fcaf2e5 5097 u32 aeu_mask;
c9ee9206 5098 bool global = false;
a2fbb9ea
ET		 5099
5100 /* need to take HW lock because MCP or other port might also
5101 try to handle this event */
4a37fb66 5102 bnx2x_acquire_alr(bp);
a2fbb9ea 5103
c9ee9206
VZ		 5104 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5105#ifndef BNX2X_STOP_ON_ERROR
72fd0718 5106 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 5107 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 5108 /* Disable HW interrupts */
5109 bnx2x_int_disable(bp);
72fd0718
VZ		 5110 /* In case of parity errors don't handle attentions so that
5111 * other function would "see" parity errors.
5112 */
c9ee9206
VZ		 5113#else
5114 bnx2x_panic();
5115#endif
5116 bnx2x_release_alr(bp);
72fd0718
VZ		 5117 return;
5118 }
5119
a2fbb9ea
ET		 5120 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5121 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5122 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5123 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 5124 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5125 attn.sig[4] =
5126 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5127 else
5128 attn.sig[4] = 0;
5129
5130 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5131 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 5132
5133 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5134 if (deasserted & (1 << index)) {
72fd0718 5135 group_mask = &bp->attn_group[index];
a2fbb9ea 5136
51c1a580 5137 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 5138 index,
5139 group_mask->sig[0], group_mask->sig[1],
5140 group_mask->sig[2], group_mask->sig[3],
5141 group_mask->sig[4]);
a2fbb9ea 5142
f2e0899f
DK		 5143 bnx2x_attn_int_deasserted4(bp,
5144 attn.sig[4] & group_mask->sig[4]);
877e9aa4 5145 bnx2x_attn_int_deasserted3(bp,
72fd0718 5146 attn.sig[3] & group_mask->sig[3]);
877e9aa4 5147 bnx2x_attn_int_deasserted1(bp,
72fd0718 5148 attn.sig[1] & group_mask->sig[1]);
877e9aa4 5149 bnx2x_attn_int_deasserted2(bp,
72fd0718 5150 attn.sig[2] & group_mask->sig[2]);
877e9aa4 5151 bnx2x_attn_int_deasserted0(bp,
72fd0718 5152 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 5153 }
5154 }
5155
4a37fb66 5156 bnx2x_release_alr(bp);
a2fbb9ea 5157
f2e0899f
DK		 5158 if (bp->common.int_block == INT_BLOCK_HC)
5159 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5160 COMMAND_REG_ATTN_BITS_CLR);
5161 else
5162 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 5163
5164 val = ~deasserted;
f2e0899f
DK		 5165 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5166 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 5167 REG_WR(bp, reg_addr, val);
a2fbb9ea 5168
a2fbb9ea 5169 if (~bp->attn_state & deasserted)
3fcaf2e5 5170 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 5171
5172 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5173 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5174
3fcaf2e5
EG		 5175 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5176 aeu_mask = REG_RD(bp, reg_addr);
5177
5178 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5179 aeu_mask, deasserted);
72fd0718 5180 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 5181 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 5182
3fcaf2e5
EG		 5183 REG_WR(bp, reg_addr, aeu_mask);
5184 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 5185
5186 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5187 bp->attn_state &= ~deasserted;
5188 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5189}
5190
5191static void bnx2x_attn_int(struct bnx2x *bp)
5192{
5193 /* read local copy of bits */
68d59484
EG		 5194 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5195 attn_bits);
5196 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5197 attn_bits_ack);
a2fbb9ea
ET		 5198 u32 attn_state = bp->attn_state;
5199
5200 /* look for changed bits */
5201 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5202 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5203
5204 DP(NETIF_MSG_HW,
5205 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5206 attn_bits, attn_ack, asserted, deasserted);
5207
5208 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 5209 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 5210
5211 /* handle bits that were raised */
5212 if (asserted)
5213 bnx2x_attn_int_asserted(bp, asserted);
5214
5215 if (deasserted)
5216 bnx2x_attn_int_deasserted(bp, deasserted);
5217}
5218
619c5cb6
VZ		 5219void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5220 u16 index, u8 op, u8 update)
5221{
dc1ba591
AE		 5222 u32 igu_addr = bp->igu_base_addr;
5223 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 5224 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5225 igu_addr);
5226}
5227
1191cb83 5228static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 5229{
5230 /* No memory barriers */
5231 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5232 mmiowb(); /* keep prod updates ordered */
5233}
5234
523224a3
DK		 5235static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5236 union event_ring_elem *elem)
5237{
619c5cb6
VZ		 5238 u8 err = elem->message.error;
5239
523224a3 5240 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 5241 (cid < bp->cnic_eth_dev.starting_cid &&
5242 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5243 return 1;
5244
5245 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5246
619c5cb6
VZ		 5247 if (unlikely(err)) {
5248
523224a3
DK		 5249 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5250 cid);
823e1d90 5251 bnx2x_panic_dump(bp, false);
523224a3 5252 }
619c5cb6 5253 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5254 return 0;
5255}
523224a3 5256
1191cb83 5257static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5258{
5259 struct bnx2x_mcast_ramrod_params rparam;
5260 int rc;
5261
5262 memset(&rparam, 0, sizeof(rparam));
5263
5264 rparam.mcast_obj = &bp->mcast_obj;
5265
5266 netif_addr_lock_bh(bp->dev);
5267
5268 /* Clear pending state for the last command */
5269 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5270
5271 /* If there are pending mcast commands - send them */
5272 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5273 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5274 if (rc < 0)
5275 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5276 rc);
5277 }
5278
5279 netif_addr_unlock_bh(bp->dev);
5280}
5281
1191cb83
ED		 5282static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5283 union event_ring_elem *elem)
619c5cb6
VZ		 5284{
5285 unsigned long ramrod_flags = 0;
5286 int rc = 0;
9cd753a1
MS		 5287 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
5288 u32 cid = echo & BNX2X_SWCID_MASK;
619c5cb6
VZ		 5289 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5290
5291 /* Always push next commands out, don't wait here */
5292 __set_bit(RAMROD_CONT, &ramrod_flags);
5293
9cd753a1 5294 switch (echo >> BNX2X_SWCID_SHIFT) {
619c5cb6 5295 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5296 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5297 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5298 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5299 else
15192a8c 5300 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6 5301
05cc5a39
YM		 5302 break;
5303 case BNX2X_FILTER_VLAN_PENDING:
5304 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5305 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
619c5cb6 5306 break;
619c5cb6 5307 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5308 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5309 /* This is only relevant for 57710 where multicast MACs are
5310 * configured as unicast MACs using the same ramrod.
5311 */
5312 bnx2x_handle_mcast_eqe(bp);
5313 return;
5314 default:
9cd753a1 5315 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
619c5cb6
VZ		 5316 return;
5317 }
5318
5319 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5320
5321 if (rc < 0)
5322 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5323 else if (rc > 0)
5324 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5325}
5326
619c5cb6 5327static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5328
1191cb83 5329static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5330{
5331 netif_addr_lock_bh(bp->dev);
5332
5333 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5334
5335 /* Send rx_mode command again if was requested */
5336 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5337 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5338 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5339 &bp->sp_state))
5340 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5341 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5342 &bp->sp_state))
5343 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5344
5345 netif_addr_unlock_bh(bp->dev);
5346}
5347
1191cb83 5348static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5349 union event_ring_elem *elem)
5350{
5351 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5352 DP(BNX2X_MSG_SP,
5353 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5354 elem->message.data.vif_list_event.func_bit_map);
5355 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5356 elem->message.data.vif_list_event.func_bit_map);
5357 } else if (elem->message.data.vif_list_event.echo ==
5358 VIF_LIST_RULE_SET) {
5359 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5360 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5361 }
5362}
5363
5364/* called with rtnl_lock */
1191cb83 5365static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5366{
5367 int q, rc;
5368 struct bnx2x_fastpath *fp;
5369 struct bnx2x_queue_state_params queue_params = {NULL};
5370 struct bnx2x_queue_update_params *q_update_params =
5371 &queue_params.params.update;
5372
2de67439 5373 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5374 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5375
5376 /* set silent vlan removal values according to vlan mode */
5377 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5378 &q_update_params->update_flags);
5379 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5380 &q_update_params->update_flags);
5381 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5382
5383 /* in access mode mark mask and value are 0 to strip all vlans */
5384 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5385 q_update_params->silent_removal_value = 0;
5386 q_update_params->silent_removal_mask = 0;
5387 } else {
5388 q_update_params->silent_removal_value =
5389 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5390 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5391 }
5392
5393 for_each_eth_queue(bp, q) {
5394 /* Set the appropriate Queue object */
5395 fp = &bp->fp[q];
15192a8c 5396 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5397
5398 /* send the ramrod */
5399 rc = bnx2x_queue_state_change(bp, &queue_params);
5400 if (rc < 0)
5401 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5402 q);
5403 }
5404
fea75645 5405 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5406 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5407 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5408
5409 /* clear pending completion bit */
5410 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5411
5412 /* mark latest Q bit */
4e857c58 5413 smp_mb__before_atomic();
a3348722 5414 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 5415 smp_mb__after_atomic();
a3348722
BW		 5416
5417 /* send Q update ramrod for FCoE Q */
5418 rc = bnx2x_queue_state_change(bp, &queue_params);
5419 if (rc < 0)
5420 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5421 q);
5422 } else {
5423 /* If no FCoE ring - ACK MCP now */
5424 bnx2x_link_report(bp);
5425 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5426 }
a3348722
BW		 5427}
5428
1191cb83 5429static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5430 struct bnx2x *bp, u32 cid)
5431{
94f05b0f 5432 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5433
5434 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5435 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5436 else
15192a8c 5437 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5438}
5439
523224a3
DK		 5440static void bnx2x_eq_int(struct bnx2x *bp)
5441{
5442 u16 hw_cons, sw_cons, sw_prod;
5443 union event_ring_elem *elem;
55c11941 5444 u8 echo;
523224a3
DK		 5445 u32 cid;
5446 u8 opcode;
fd1fc79d 5447 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5448 struct bnx2x_queue_sp_obj *q_obj;
5449 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5450 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5451
5452 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5453
5454 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5455 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5456 * condition below will be met. The next element is the size of a
5457 * regular element and hence incrementing by 1
5458 */
5459 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5460 hw_cons++;
5461
25985edc 5462 /* This function may never run in parallel with itself for a
523224a3
DK		 5463 * specific bp, thus there is no need in "paired" read memory
5464 * barrier here.
5465 */
5466 sw_cons = bp->eq_cons;
5467 sw_prod = bp->eq_prod;
5468
d6cae238 5469 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5470 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5471
5472 for (; sw_cons != hw_cons;
5473 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5474
523224a3
DK		 5475 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5476
fd1fc79d
AE		 5477 rc = bnx2x_iov_eq_sp_event(bp, elem);
5478 if (!rc) {
5479 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5480 rc);
5481 goto next_spqe;
5482 }
523224a3 5483
86564c3f 5484 opcode = elem->message.opcode;
523224a3
DK		 5485
5486 /* handle eq element */
5487 switch (opcode) {
fd1fc79d 5488 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
370d4a26
YM		 5489 bnx2x_vf_mbx_schedule(bp,
5490 &elem->message.data.vf_pf_event);
fd1fc79d
AE		 5491 continue;
5492
523224a3 5493 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5494 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5495 "got statistics comp event %d\n",
5496 bp->stats_comp++);
523224a3 5497 /* nothing to do with stats comp */
d6cae238 5498 goto next_spqe;
523224a3
DK		 5499
5500 case EVENT_RING_OPCODE_CFC_DEL:
5501 /* handle according to cid range */
5502 /*
5503 * we may want to verify here that the bp state is
5504 * HALTING
5505 */
ca4f2d50
MS		 5506
5507 /* elem CID originates from FW; actually LE */
da472731 5508 cid = SW_CID(elem->message.data.cfc_del_event.cid);
ca4f2d50 5509
d6cae238 5510 DP(BNX2X_MSG_SP,
523224a3 5511 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5512
5513 if (CNIC_LOADED(bp) &&
5514 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5515 goto next_spqe;
55c11941 5516
619c5cb6
VZ		 5517 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5518
5519 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5520 break;
5521
523224a3 5522 goto next_spqe;
e4901dde
VZ		 5523
5524 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5525 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5526 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5527 if (f_obj->complete_cmd(bp, f_obj,
5528 BNX2X_F_CMD_TX_STOP))
5529 break;
e4901dde 5530 goto next_spqe;
619c5cb6 5531
e4901dde 5532 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5533 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5534 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5535 if (f_obj->complete_cmd(bp, f_obj,
5536 BNX2X_F_CMD_TX_START))
5537 break;
e4901dde 5538 goto next_spqe;
55c11941 5539
a3348722 5540 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5541 echo = elem->message.data.function_update_event.echo;
5542 if (echo == SWITCH_UPDATE) {
5543 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5544 "got FUNC_SWITCH_UPDATE ramrod\n");
5545 if (f_obj->complete_cmd(
5546 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5547 break;
a3348722 5548
55c11941 5549 } else {
230bb0f3
YM		 5550 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5551
55c11941
MS		 5552 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5553 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5554 f_obj->complete_cmd(bp, f_obj,
5555 BNX2X_F_CMD_AFEX_UPDATE);
5556
5557 /* We will perform the Queues update from
5558 * sp_rtnl task as all Queue SP operations
5559 * should run under rtnl_lock.
5560 */
230bb0f3 5561 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
55c11941 5562 }
a3348722 5563
a3348722
BW		 5564 goto next_spqe;
5565
5566 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5567 f_obj->complete_cmd(bp, f_obj,
5568 BNX2X_F_CMD_AFEX_VIFLISTS);
5569 bnx2x_after_afex_vif_lists(bp, elem);
5570 goto next_spqe;
619c5cb6 5571 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5572 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5573 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5574 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5575 break;
5576
5577 goto next_spqe;
5578
5579 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5580 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5581 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5582 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5583 break;
5584
5585 goto next_spqe;
eeed018c
MK		 5586
5587 case EVENT_RING_OPCODE_SET_TIMESYNC:
5588 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5589 "got set_timesync ramrod completion\n");
5590 if (f_obj->complete_cmd(bp, f_obj,
5591 BNX2X_F_CMD_SET_TIMESYNC))
5592 break;
5593 goto next_spqe;
523224a3
DK		 5594 }
5595
5596 switch (opcode | bp->state) {
619c5cb6
VZ		 5597 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5598 BNX2X_STATE_OPEN):
5599 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5600 BNX2X_STATE_OPENING_WAIT4_PORT):
28311f8e
YM		 5601 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5602 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5603 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
9cd753a1 5604 SW_CID(elem->message.data.eth_event.echo));
619c5cb6 5605 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5606 break;
5607
619c5cb6
VZ		 5608 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5609 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5610 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5611 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5612 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5613 BNX2X_STATE_OPEN):
5614 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5615 BNX2X_STATE_DIAG):
5616 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5617 BNX2X_STATE_CLOSING_WAIT4_HALT):
05cc5a39 5618 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
619c5cb6 5619 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5620 break;
5621
619c5cb6
VZ		 5622 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5623 BNX2X_STATE_OPEN):
5624 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5625 BNX2X_STATE_DIAG):
5626 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5627 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5628 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5629 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5630 break;
5631
619c5cb6
VZ		 5632 case (EVENT_RING_OPCODE_FILTERS_RULES |
5633 BNX2X_STATE_OPEN):
5634 case (EVENT_RING_OPCODE_FILTERS_RULES |
5635 BNX2X_STATE_DIAG):
5636 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5637 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5638 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5639 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5640 break;
5641 default:
5642 /* unknown event log error and continue */
619c5cb6
VZ		 5643 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5644 elem->message.opcode, bp->state);
523224a3
DK		 5645 }
5646next_spqe:
5647 spqe_cnt++;
5648 } /* for */
5649
4e857c58 5650 smp_mb__before_atomic();
6e30dd4e 5651 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5652
5653 bp->eq_cons = sw_cons;
5654 bp->eq_prod = sw_prod;
5655 /* Make sure that above mem writes were issued towards the memory */
5656 smp_wmb();
5657
5658 /* update producer */
5659 bnx2x_update_eq_prod(bp, bp->eq_prod);
5660}
5661
a2fbb9ea
ET		 5662static void bnx2x_sp_task(struct work_struct *work)
5663{
1cf167f2 5664 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5665
fd1fc79d 5666 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5667
16a5fd92 5668 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5669 smp_rmb();
5670 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5671
fd1fc79d
AE		 5672 /* what work needs to be performed? */
5673 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5674
fd1fc79d
AE		 5675 DP(BNX2X_MSG_SP, "status %x\n", status);
5676 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5677 atomic_set(&bp->interrupt_occurred, 0);
5678
5679 /* HW attentions */
5680 if (status & BNX2X_DEF_SB_ATT_IDX) {
5681 bnx2x_attn_int(bp);
5682 status &= ~BNX2X_DEF_SB_ATT_IDX;
5683 }
5684
5685 /* SP events: STAT_QUERY and others */
5686 if (status & BNX2X_DEF_SB_IDX) {
5687 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5688
7e88009b 5689 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5690 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5691 /* Prevent local bottom-halves from running as
5692 * we are going to change the local NAPI list.
5693 */
5694 local_bh_disable();
5695 napi_schedule(&bnx2x_fcoe(bp, napi));
5696 local_bh_enable();
5697 }
5698
5699 /* Handle EQ completions */
5700 bnx2x_eq_int(bp);
5701 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5702 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5703
5704 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5705 }
55c11941 5706
fd1fc79d
AE		 5707 /* if status is non zero then perhaps something went wrong */
5708 if (unlikely(status))
5709 DP(BNX2X_MSG_SP,
5710 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5711
fd1fc79d
AE		 5712 /* ack status block only if something was actually handled */
5713 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5714 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5715 }
5716
a3348722
BW		 5717 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5718 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5719 &bp->sp_state)) {
5720 bnx2x_link_report(bp);
5721 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5722 }
a2fbb9ea
ET		 5723}
5724
9f6c9258 5725irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5726{
5727 struct net_device *dev = dev_instance;
5728 struct bnx2x *bp = netdev_priv(dev);
5729
523224a3
DK		 5730 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5731 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5732
5733#ifdef BNX2X_STOP_ON_ERROR
5734 if (unlikely(bp->panic))
5735 return IRQ_HANDLED;
5736#endif
5737
55c11941 5738 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5739 struct cnic_ops *c_ops;
5740
5741 rcu_read_lock();
5742 c_ops = rcu_dereference(bp->cnic_ops);
5743 if (c_ops)
5744 c_ops->cnic_handler(bp->cnic_data, NULL);
5745 rcu_read_unlock();
5746 }
55c11941 5747
fd1fc79d
AE		 5748 /* schedule sp task to perform default status block work, ack
5749 * attentions and enable interrupts.
5750 */
5751 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5752
5753 return IRQ_HANDLED;
5754}
5755
5756/* end of slow path */
5757
619c5cb6
VZ		 5758void bnx2x_drv_pulse(struct bnx2x *bp)
5759{
5760 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5761 bp->fw_drv_pulse_wr_seq);
5762}
5763
a2fbb9ea
ET		 5764static void bnx2x_timer(unsigned long data)
5765{
5766 struct bnx2x *bp = (struct bnx2x *) data;
5767
5768 if (!netif_running(bp->dev))
5769 return;
5770
67c431a5
AE		 5771 if (IS_PF(bp) &&
5772 !BP_NOMCP(bp)) {
f2e0899f 5773 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5774 u16 drv_pulse;
5775 u16 mcp_pulse;
a2fbb9ea
ET		 5776
5777 ++bp->fw_drv_pulse_wr_seq;
5778 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5779 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5780 bnx2x_drv_pulse(bp);
a2fbb9ea 5781
f2e0899f 5782 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5783 MCP_PULSE_SEQ_MASK);
5784 /* The delta between driver pulse and mcp response
4c868664
EG		 5785 * should not get too big. If the MFW is more than 5 pulses
5786 * behind, we should worry about it enough to generate an error
5787 * log.
a2fbb9ea 5788 */
4c868664
EG		 5789 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5790 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5791 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5792 }
5793
f34d28ea 5794 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5795 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5796
abc5a021 5797 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5798 if (IS_VF(bp))
5799 bnx2x_timer_sriov(bp);
78c3bcc5 5800
a2fbb9ea
ET		 5801 mod_timer(&bp->timer, jiffies + bp->current_interval);
5802}
5803
5804/* end of Statistics */
5805
5806/* nic init */
5807
5808/*
5809 * nic init service functions
5810 */
5811
1191cb83 5812static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5813{
523224a3
DK		 5814 u32 i;
5815 if (!(len%4) && !(addr%4))
5816 for (i = 0; i < len; i += 4)
5817 REG_WR(bp, addr + i, fill);
5818 else
5819 for (i = 0; i < len; i++)
5820 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5821}
5822
523224a3 5823/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5824static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5825 int fw_sb_id,
5826 u32 *sb_data_p,
5827 u32 data_size)
34f80b04 5828{
a2fbb9ea 5829 int index;
523224a3
DK		 5830 for (index = 0; index < data_size; index++)
5831 REG_WR(bp, BAR_CSTRORM_INTMEM +
5832 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5833 sizeof(u32)*index,
5834 *(sb_data_p + index));
5835}
a2fbb9ea 5836
1191cb83 5837static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5838{
5839 u32 *sb_data_p;
5840 u32 data_size = 0;
f2e0899f 5841 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5842 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5843
523224a3 5844 /* disable the function first */
619c5cb6 5845 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5846 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5847 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5848 sb_data_e2.common.p_func.vf_valid = false;
5849 sb_data_p = (u32 *)&sb_data_e2;
5850 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5851 } else {
5852 memset(&sb_data_e1x, 0,
5853 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5854 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5855 sb_data_e1x.common.p_func.vf_valid = false;
5856 sb_data_p = (u32 *)&sb_data_e1x;
5857 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5858 }
523224a3 5859 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5860
523224a3
DK		 5861 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5862 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5863 CSTORM_STATUS_BLOCK_SIZE);
5864 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5865 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5866 CSTORM_SYNC_BLOCK_SIZE);
5867}
34f80b04 5868
523224a3 5869/* helper: writes SP SB data to FW */
1191cb83 5870static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5871 struct hc_sp_status_block_data *sp_sb_data)
5872{
5873 int func = BP_FUNC(bp);
5874 int i;
5875 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5876 REG_WR(bp, BAR_CSTRORM_INTMEM +
5877 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5878 i*sizeof(u32),
5879 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5880}
5881
1191cb83 5882static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5883{
5884 int func = BP_FUNC(bp);
523224a3
DK		 5885 struct hc_sp_status_block_data sp_sb_data;
5886 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5887
619c5cb6 5888 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5889 sp_sb_data.p_func.vf_valid = false;
5890
5891 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5892
5893 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5894 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5895 CSTORM_SP_STATUS_BLOCK_SIZE);
5896 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5897 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5898 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5899}
5900
1191cb83 5901static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5902 int igu_sb_id, int igu_seg_id)
5903{
5904 hc_sm->igu_sb_id = igu_sb_id;
5905 hc_sm->igu_seg_id = igu_seg_id;
5906 hc_sm->timer_value = 0xFF;
5907 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5908}
5909
150966ad 5910/* allocates state machine ids. */
1191cb83 5911static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5912{
5913 /* zero out state machine indices */
5914 /* rx indices */
5915 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5916
5917 /* tx indices */
5918 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5919 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5920 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5921 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5922
5923 /* map indices */
5924 /* rx indices */
5925 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5926 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5927
5928 /* tx indices */
5929 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5930 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5931 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5932 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5933 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5934 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5935 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5936 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5937}
5938
b93288d5 5939void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5940 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5941{
523224a3
DK		 5942 int igu_seg_id;
5943
f2e0899f 5944 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5945 struct hc_status_block_data_e1x sb_data_e1x;
5946 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5947 int data_size;
5948 u32 *sb_data_p;
5949
f2e0899f
DK		 5950 if (CHIP_INT_MODE_IS_BC(bp))
5951 igu_seg_id = HC_SEG_ACCESS_NORM;
5952 else
5953 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5954
5955 bnx2x_zero_fp_sb(bp, fw_sb_id);
5956
619c5cb6 5957 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5958 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5959 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5960 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5961 sb_data_e2.common.p_func.vf_id = vfid;
5962 sb_data_e2.common.p_func.vf_valid = vf_valid;
5963 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5964 sb_data_e2.common.same_igu_sb_1b = true;
5965 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5966 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5967 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5968 sb_data_p = (u32 *)&sb_data_e2;
5969 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5970 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5971 } else {
5972 memset(&sb_data_e1x, 0,
5973 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5974 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5975 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5976 sb_data_e1x.common.p_func.vf_id = 0xff;
5977 sb_data_e1x.common.p_func.vf_valid = false;
5978 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5979 sb_data_e1x.common.same_igu_sb_1b = true;
5980 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5981 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5982 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5983 sb_data_p = (u32 *)&sb_data_e1x;
5984 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5985 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5986 }
523224a3
DK		 5987
5988 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5989 igu_sb_id, igu_seg_id);
5990 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5991 igu_sb_id, igu_seg_id);
5992
51c1a580 5993 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 5994
86564c3f 5995 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 5996 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5997}
5998
619c5cb6 5999static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 6000 u16 tx_usec, u16 rx_usec)
6001{
6383c0b3 6002 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 6003 false, rx_usec);
6383c0b3
AE		 6004 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6005 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6006 tx_usec);
6007 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6008 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6009 tx_usec);
6010 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6011 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6012 tx_usec);
523224a3 6013}
f2e0899f 6014
523224a3
DK		 6015static void bnx2x_init_def_sb(struct bnx2x *bp)
6016{
6017 struct host_sp_status_block *def_sb = bp->def_status_blk;
6018 dma_addr_t mapping = bp->def_status_blk_mapping;
6019 int igu_sp_sb_index;
6020 int igu_seg_id;
34f80b04
EG		 6021 int port = BP_PORT(bp);
6022 int func = BP_FUNC(bp);
f2eaeb58 6023 int reg_offset, reg_offset_en5;
a2fbb9ea 6024 u64 section;
523224a3
DK		 6025 int index;
6026 struct hc_sp_status_block_data sp_sb_data;
6027 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6028
f2e0899f
DK		 6029 if (CHIP_INT_MODE_IS_BC(bp)) {
6030 igu_sp_sb_index = DEF_SB_IGU_ID;
6031 igu_seg_id = HC_SEG_ACCESS_DEF;
6032 } else {
6033 igu_sp_sb_index = bp->igu_dsb_id;
6034 igu_seg_id = IGU_SEG_ACCESS_DEF;
6035 }
a2fbb9ea
ET		 6036
6037 /* ATTN */
523224a3 6038 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 6039 atten_status_block);
523224a3 6040 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 6041
49d66772
ET		 6042 bp->attn_state = 0;
6043
a2fbb9ea
ET		 6044 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6045 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 6046 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6047 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 6048 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 6049 int sindex;
6050 /* take care of sig[0]..sig[4] */
6051 for (sindex = 0; sindex < 4; sindex++)
6052 bp->attn_group[index].sig[sindex] =
6053 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 6054
619c5cb6 6055 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6056 /*
6057 * enable5 is separate from the rest of the registers,
6058 * and therefore the address skip is 4
6059 * and not 16 between the different groups
6060 */
6061 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 6062 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 6063 else
6064 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 6065 }
6066
f2e0899f
DK		 6067 if (bp->common.int_block == INT_BLOCK_HC) {
6068 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6069 HC_REG_ATTN_MSG0_ADDR_L);
6070
6071 REG_WR(bp, reg_offset, U64_LO(section));
6072 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 6073 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6074 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6075 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6076 }
a2fbb9ea 6077
523224a3
DK		 6078 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6079 sp_sb);
a2fbb9ea 6080
523224a3 6081 bnx2x_zero_sp_sb(bp);
a2fbb9ea 6082
86564c3f 6083 /* PCI guarantees endianity of regpairs */
619c5cb6 6084 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 6085 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6086 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6087 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6088 sp_sb_data.igu_seg_id = igu_seg_id;
6089 sp_sb_data.p_func.pf_id = func;
f2e0899f 6090 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 6091 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 6092
523224a3 6093 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 6094
523224a3 6095 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 6096}
6097
9f6c9258 6098void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 6099{
a2fbb9ea
ET		 6100 int i;
6101
ec6ba945 6102 for_each_eth_queue(bp, i)
523224a3 6103 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 6104 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 6105}
6106
a2fbb9ea
ET		 6107static void bnx2x_init_sp_ring(struct bnx2x *bp)
6108{
a2fbb9ea 6109 spin_lock_init(&bp->spq_lock);
6e30dd4e 6110 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 6111
a2fbb9ea 6112 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 6113 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6114 bp->spq_prod_bd = bp->spq;
6115 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 6116}
6117
523224a3 6118static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 6119{
6120 int i;
523224a3
DK		 6121 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6122 union event_ring_elem *elem =
6123 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 6124
523224a3
DK		 6125 elem->next_page.addr.hi =
6126 cpu_to_le32(U64_HI(bp->eq_mapping +
6127 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6128 elem->next_page.addr.lo =
6129 cpu_to_le32(U64_LO(bp->eq_mapping +
6130 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 6131 }
523224a3
DK		 6132 bp->eq_cons = 0;
6133 bp->eq_prod = NUM_EQ_DESC;
6134 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 6135 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 6136 atomic_set(&bp->eq_spq_left,
6137 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 6138}
6139
619c5cb6 6140/* called with netif_addr_lock_bh() */
a8f47eb7 6141static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6142 unsigned long rx_mode_flags,
6143 unsigned long rx_accept_flags,
6144 unsigned long tx_accept_flags,
6145 unsigned long ramrod_flags)
ab532cf3 6146{
619c5cb6
VZ		 6147 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6148 int rc;
6149
6150 memset(&ramrod_param, 0, sizeof(ramrod_param));
6151
6152 /* Prepare ramrod parameters */
6153 ramrod_param.cid = 0;
6154 ramrod_param.cl_id = cl_id;
6155 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6156 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 6157
619c5cb6
VZ		 6158 ramrod_param.pstate = &bp->sp_state;
6159 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 6160
619c5cb6
VZ		 6161 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6162 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6163
6164 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6165
6166 ramrod_param.ramrod_flags = ramrod_flags;
6167 ramrod_param.rx_mode_flags = rx_mode_flags;
6168
6169 ramrod_param.rx_accept_flags = rx_accept_flags;
6170 ramrod_param.tx_accept_flags = tx_accept_flags;
6171
6172 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6173 if (rc < 0) {
6174 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 6175 return rc;
619c5cb6 6176 }
924d75ab
YM		 6177
6178 return 0;
a2fbb9ea
ET		 6179}
6180
86564c3f
YM		 6181static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6182 unsigned long *rx_accept_flags,
6183 unsigned long *tx_accept_flags)
471de716 6184{
924d75ab
YM		 6185 /* Clear the flags first */
6186 *rx_accept_flags = 0;
6187 *tx_accept_flags = 0;
619c5cb6 6188
924d75ab 6189 switch (rx_mode) {
619c5cb6
VZ		 6190 case BNX2X_RX_MODE_NONE:
6191 /*
6192 * 'drop all' supersedes any accept flags that may have been
6193 * passed to the function.
6194 */
6195 break;
6196 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 6197 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6198 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6199 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6200
6201 /* internal switching mode */
924d75ab
YM		 6202 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6203 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6204 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6 6205
05cc5a39
YM		 6206 if (bp->accept_any_vlan) {
6207 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6208 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6209 }
6210
619c5cb6
VZ		 6211 break;
6212 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 6213 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6214 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6215 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6216
6217 /* internal switching mode */
924d75ab
YM		 6218 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6219 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6220 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6 6221
05cc5a39
YM		 6222 if (bp->accept_any_vlan) {
6223 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6224 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6225 }
6226
619c5cb6
VZ		 6227 break;
6228 case BNX2X_RX_MODE_PROMISC:
16a5fd92 6229 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 6230 * should receive matched and unmatched (in resolution of port)
6231 * unicast packets.
6232 */
924d75ab
YM		 6233 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6234 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6235 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6236 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6237
6238 /* internal switching mode */
924d75ab
YM		 6239 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6240 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6241
6242 if (IS_MF_SI(bp))
924d75ab 6243 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 6244 else
924d75ab 6245 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6 6246
05cc5a39
YM		 6247 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6248 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6249
619c5cb6
VZ		 6250 break;
6251 default:
924d75ab
YM		 6252 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6253 return -EINVAL;
619c5cb6 6254 }
de832a55 6255
924d75ab
YM		 6256 return 0;
6257}
6258
6259/* called with netif_addr_lock_bh() */
a8f47eb7 6260static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6261{
6262 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6263 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6264 int rc;
6265
6266 if (!NO_FCOE(bp))
6267 /* Configure rx_mode of FCoE Queue */
6268 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6269
6270 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6271 &tx_accept_flags);
6272 if (rc)
6273 return rc;
6274
619c5cb6
VZ		 6275 __set_bit(RAMROD_RX, &ramrod_flags);
6276 __set_bit(RAMROD_TX, &ramrod_flags);
6277
924d75ab
YM		 6278 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6279 rx_accept_flags, tx_accept_flags,
6280 ramrod_flags);
619c5cb6
VZ		 6281}
6282
6283static void bnx2x_init_internal_common(struct bnx2x *bp)
6284{
6285 int i;
6286
523224a3
DK		 6287 /* Zero this manually as its initialization is
6288 currently missing in the initTool */
6289 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6290 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6291 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6292 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6293 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6294 CHIP_INT_MODE_IS_BC(bp) ?
6295 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6296 }
523224a3 6297}
8a1c38d1 6298
471de716
EG		 6299static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6300{
6301 switch (load_code) {
6302 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6303 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6304 bnx2x_init_internal_common(bp);
6305 /* no break */
6306
6307 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6308 /* nothing to do */
471de716
EG		 6309 /* no break */
6310
6311 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6312 /* internal memory per function is
6313 initialized inside bnx2x_pf_init */
471de716
EG		 6314 break;
6315
6316 default:
6317 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6318 break;
6319 }
6320}
6321
619c5cb6 6322static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6323{
55c11941 6324 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6325}
523224a3 6326
619c5cb6
VZ		 6327static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6328{
55c11941 6329 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6330}
6331
1191cb83 6332static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6333{
6334 if (CHIP_IS_E1x(fp->bp))
6335 return BP_L_ID(fp->bp) + fp->index;
6336 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6337 return bnx2x_fp_igu_sb_id(fp);
6338}
6339
6383c0b3 6340static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6341{
6342 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6343 u8 cos;
619c5cb6 6344 unsigned long q_type = 0;
6383c0b3 6345 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6346 fp->rx_queue = fp_idx;
b3b83c3f 6347 fp->cid = fp_idx;
619c5cb6
VZ		 6348 fp->cl_id = bnx2x_fp_cl_id(fp);
6349 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6350 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6351 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6352 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6353
523224a3 6354 /* init shortcut */
619c5cb6 6355 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6356
16a5fd92 6357 /* Setup SB indices */
523224a3 6358 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6359
619c5cb6
VZ		 6360 /* Configure Queue State object */
6361 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6362 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6363
6364 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6365
6366 /* init tx data */
6367 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6368 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6369 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6370 FP_COS_TO_TXQ(fp, cos, bp),
6371 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6372 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6373 }
6374
ad5afc89
AE		 6375 /* nothing more for vf to do here */
6376 if (IS_VF(bp))
6377 return;
6378
6379 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6380 fp->fw_sb_id, fp->igu_sb_id);
6381 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6382 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6383 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6384 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6385
6386 /**
6387 * Configure classification DBs: Always enable Tx switching
6388 */
6389 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6390
ad5afc89
AE		 6391 DP(NETIF_MSG_IFUP,
6392 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6393 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6394 fp->igu_sb_id);
523224a3
DK		 6395}
6396
1191cb83
ED		 6397static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6398{
6399 int i;
6400
6401 for (i = 1; i <= NUM_TX_RINGS; i++) {
6402 struct eth_tx_next_bd *tx_next_bd =
6403 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6404
6405 tx_next_bd->addr_hi =
6406 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6407 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6408 tx_next_bd->addr_lo =
6409 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6410 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6411 }
6412
639d65b8
YM		 6413 *txdata->tx_cons_sb = cpu_to_le16(0);
6414
1191cb83
ED		 6415 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6416 txdata->tx_db.data.zero_fill1 = 0;
6417 txdata->tx_db.data.prod = 0;
6418
6419 txdata->tx_pkt_prod = 0;
6420 txdata->tx_pkt_cons = 0;
6421 txdata->tx_bd_prod = 0;
6422 txdata->tx_bd_cons = 0;
6423 txdata->tx_pkt = 0;
6424}
6425
55c11941
MS		 6426static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6427{
6428 int i;
6429
6430 for_each_tx_queue_cnic(bp, i)
6431 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6432}
d76a6111 6433
1191cb83
ED		 6434static void bnx2x_init_tx_rings(struct bnx2x *bp)
6435{
6436 int i;
6437 u8 cos;
6438
55c11941 6439 for_each_eth_queue(bp, i)
1191cb83 6440 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6441 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6442}
6443
a8f47eb7 6444static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6445{
6446 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6447 unsigned long q_type = 0;
6448
6449 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6450 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6451 BNX2X_FCOE_ETH_CL_ID_IDX);
6452 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6453 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6454 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6455 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6456 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6457 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6458 fp);
6459
6460 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6461
6462 /* qZone id equals to FW (per path) client id */
6463 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6464 /* init shortcut */
6465 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6466 bnx2x_rx_ustorm_prods_offset(fp);
6467
6468 /* Configure Queue State object */
6469 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6470 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6471
6472 /* No multi-CoS for FCoE L2 client */
6473 BUG_ON(fp->max_cos != 1);
6474
6475 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6476 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6477 bnx2x_sp_mapping(bp, q_rdata), q_type);
6478
6479 DP(NETIF_MSG_IFUP,
6480 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6481 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6482 fp->igu_sb_id);
6483}
6484
55c11941 6485void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6486{
ec6ba945
VZ		 6487 if (!NO_FCOE(bp))
6488 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6489
6490 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6491 BNX2X_VF_ID_INVALID, false,
619c5cb6 6492 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6493
55c11941
MS		 6494 /* ensure status block indices were read */
6495 rmb();
6496 bnx2x_init_rx_rings_cnic(bp);
6497 bnx2x_init_tx_rings_cnic(bp);
6498
6499 /* flush all */
6500 mb();
6501 mmiowb();
6502}
a2fbb9ea 6503
ecf01c22 6504void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6505{
6506 int i;
6507
ecf01c22 6508 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6509 for_each_eth_queue(bp, i)
6510 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6511
6512 /* ensure status block indices were read */
6513 rmb();
6514 bnx2x_init_rx_rings(bp);
6515 bnx2x_init_tx_rings(bp);
6516
ecf01c22
YM		 6517 if (IS_PF(bp)) {
6518 /* Initialize MOD_ABS interrupts */
6519 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6520 bp->common.shmem_base,
6521 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6522
ecf01c22
YM		 6523 /* initialize the default status block and sp ring */
6524 bnx2x_init_def_sb(bp);
6525 bnx2x_update_dsb_idx(bp);
6526 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6527 } else {
6528 bnx2x_memset_stats(bp);
ecf01c22
YM		 6529 }
6530}
16119785 6531
ecf01c22
YM		 6532void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6533{
523224a3 6534 bnx2x_init_eq_ring(bp);
471de716 6535 bnx2x_init_internal(bp, load_code);
523224a3 6536 bnx2x_pf_init(bp);
0ef00459
EG		 6537 bnx2x_stats_init(bp);
6538
0ef00459
EG		 6539 /* flush all before enabling interrupts */
6540 mb();
6541 mmiowb();
6542
615f8fd9 6543 bnx2x_int_enable(bp);
eb8da205
EG		 6544
6545 /* Check for SPIO5 */
6546 bnx2x_attn_int_deasserted0(bp,
6547 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6548 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6549}
6550
ecf01c22 6551/* gzip service functions */
a2fbb9ea
ET		 6552static int bnx2x_gunzip_init(struct bnx2x *bp)
6553{
1a983142
FT		 6554 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6555 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6556 if (bp->gunzip_buf == NULL)
6557 goto gunzip_nomem1;
6558
6559 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6560 if (bp->strm == NULL)
6561 goto gunzip_nomem2;
6562
7ab24bfd 6563 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6564 if (bp->strm->workspace == NULL)
6565 goto gunzip_nomem3;
6566
6567 return 0;
6568
6569gunzip_nomem3:
6570 kfree(bp->strm);
6571 bp->strm = NULL;
6572
6573gunzip_nomem2:
1a983142
FT		 6574 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6575 bp->gunzip_mapping);
a2fbb9ea
ET		 6576 bp->gunzip_buf = NULL;
6577
6578gunzip_nomem1:
51c1a580 6579 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6580 return -ENOMEM;
6581}
6582
6583static void bnx2x_gunzip_end(struct bnx2x *bp)
6584{
b3b83c3f 6585 if (bp->strm) {
7ab24bfd 6586 vfree(bp->strm->workspace);
b3b83c3f
DK		 6587 kfree(bp->strm);
6588 bp->strm = NULL;
6589 }
a2fbb9ea
ET		 6590
6591 if (bp->gunzip_buf) {
1a983142
FT		 6592 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6593 bp->gunzip_mapping);
a2fbb9ea
ET		 6594 bp->gunzip_buf = NULL;
6595 }
6596}
6597
94a78b79 6598static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6599{
6600 int n, rc;
6601
6602 /* check gzip header */
94a78b79
VZ		 6603 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6604 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6605 return -EINVAL;
94a78b79 6606 }
a2fbb9ea
ET		 6607
6608 n = 10;
6609
34f80b04 6610#define FNAME 0x8
a2fbb9ea
ET		 6611
6612 if (zbuf[3] & FNAME)
6613 while ((zbuf[n++] != 0) && (n < len));
6614
94a78b79 6615 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6616 bp->strm->avail_in = len - n;
6617 bp->strm->next_out = bp->gunzip_buf;
6618 bp->strm->avail_out = FW_BUF_SIZE;
6619
6620 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6621 if (rc != Z_OK)
6622 return rc;
6623
6624 rc = zlib_inflate(bp->strm, Z_FINISH);
6625 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6626 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6627 bp->strm->msg);
a2fbb9ea
ET		 6628
6629 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6630 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6631 netdev_err(bp->dev,
6632 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6633 bp->gunzip_outlen);
a2fbb9ea
ET		 6634 bp->gunzip_outlen >>= 2;
6635
6636 zlib_inflateEnd(bp->strm);
6637
6638 if (rc == Z_STREAM_END)
6639 return 0;
6640
6641 return rc;
6642}
6643
6644/* nic load/unload */
6645
6646/*
34f80b04 6647 * General service functions
a2fbb9ea
ET		 6648 */
6649
6650/* send a NIG loopback debug packet */
6651static void bnx2x_lb_pckt(struct bnx2x *bp)
6652{
a2fbb9ea 6653 u32 wb_write[3];
a2fbb9ea
ET		 6654
6655 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6656 wb_write[0] = 0x55555555;
6657 wb_write[1] = 0x55555555;
34f80b04 6658 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6659 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6660
6661 /* NON-IP protocol */
a2fbb9ea
ET		 6662 wb_write[0] = 0x09000000;
6663 wb_write[1] = 0x55555555;
34f80b04 6664 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6665 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6666}
6667
6668/* some of the internal memories
6669 * are not directly readable from the driver
6670 * to test them we send debug packets
6671 */
6672static int bnx2x_int_mem_test(struct bnx2x *bp)
6673{
6674 int factor;
6675 int count, i;
6676 u32 val = 0;
6677
ad8d3948 6678 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6679 factor = 120;
ad8d3948
EG		 6680 else if (CHIP_REV_IS_EMUL(bp))
6681 factor = 200;
6682 else
a2fbb9ea 6683 factor = 1;
a2fbb9ea 6684
a2fbb9ea
ET		 6685 /* Disable inputs of parser neighbor blocks */
6686 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6687 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6688 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6689 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6690
6691 /* Write 0 to parser credits for CFC search request */
6692 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6693
6694 /* send Ethernet packet */
6695 bnx2x_lb_pckt(bp);
6696
6697 /* TODO do i reset NIG statistic? */
6698 /* Wait until NIG register shows 1 packet of size 0x10 */
6699 count = 1000 * factor;
6700 while (count) {
34f80b04 6701
a2fbb9ea
ET		 6702 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6703 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6704 if (val == 0x10)
6705 break;
6706
639d65b8 6707 usleep_range(10000, 20000);
a2fbb9ea
ET		 6708 count--;
6709 }
6710 if (val != 0x10) {
6711 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6712 return -1;
6713 }
6714
6715 /* Wait until PRS register shows 1 packet */
6716 count = 1000 * factor;
6717 while (count) {
6718 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6719 if (val == 1)
6720 break;
6721
639d65b8 6722 usleep_range(10000, 20000);
a2fbb9ea
ET		 6723 count--;
6724 }
6725 if (val != 0x1) {
6726 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6727 return -2;
6728 }
6729
6730 /* Reset and init BRB, PRS */
34f80b04 6731 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6732 msleep(50);
34f80b04 6733 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6734 msleep(50);
619c5cb6
VZ		 6735 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6736 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6737
6738 DP(NETIF_MSG_HW, "part2\n");
6739
6740 /* Disable inputs of parser neighbor blocks */
6741 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6742 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6743 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6744 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6745
6746 /* Write 0 to parser credits for CFC search request */
6747 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6748
6749 /* send 10 Ethernet packets */
6750 for (i = 0; i < 10; i++)
6751 bnx2x_lb_pckt(bp);
6752
6753 /* Wait until NIG register shows 10 + 1
6754 packets of size 11*0x10 = 0xb0 */
6755 count = 1000 * factor;
6756 while (count) {
34f80b04 6757
a2fbb9ea
ET		 6758 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6759 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6760 if (val == 0xb0)
6761 break;
6762
639d65b8 6763 usleep_range(10000, 20000);
a2fbb9ea
ET		 6764 count--;
6765 }
6766 if (val != 0xb0) {
6767 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6768 return -3;
6769 }
6770
6771 /* Wait until PRS register shows 2 packets */
6772 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6773 if (val != 2)
6774 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6775
6776 /* Write 1 to parser credits for CFC search request */
6777 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6778
6779 /* Wait until PRS register shows 3 packets */
6780 msleep(10 * factor);
6781 /* Wait until NIG register shows 1 packet of size 0x10 */
6782 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6783 if (val != 3)
6784 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6785
6786 /* clear NIG EOP FIFO */
6787 for (i = 0; i < 11; i++)
6788 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6789 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6790 if (val != 1) {
6791 BNX2X_ERR("clear of NIG failed\n");
6792 return -4;
6793 }
6794
6795 /* Reset and init BRB, PRS, NIG */
6796 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6797 msleep(50);
6798 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6799 msleep(50);
619c5cb6
VZ		 6800 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6801 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6802 if (!CNIC_SUPPORT(bp))
6803 /* set NIC mode */
6804 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6805
6806 /* Enable inputs of parser neighbor blocks */
6807 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6808 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6809 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6810 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6811
6812 DP(NETIF_MSG_HW, "done\n");
6813
6814 return 0; /* OK */
6815}
6816
4a33bc03 6817static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6818{
b343d002
YM		 6819 u32 val;
6820
a2fbb9ea 6821 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6822 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6823 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6824 else
6825 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6826 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6827 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6828 /*
6829 * mask read length error interrupts in brb for parser
6830 * (parsing unit and 'checksum and crc' unit)
6831 * these errors are legal (PU reads fixed length and CAC can cause
6832 * read length error on truncated packets)
6833 */
6834 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6835 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6836 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6837 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6838 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6839 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6840/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6841/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6842 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6843 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6844 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6845/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6846/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6847 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6848 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6849 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6850 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6851/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6852/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6853
b343d002
YM		 6854 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6855 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6856 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6857 if (!CHIP_IS_E1x(bp))
6858 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6859 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6860 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6861
a2fbb9ea
ET		 6862 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6863 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6864 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6865/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6866
6867 if (!CHIP_IS_E1x(bp))
6868 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6869 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6870
a2fbb9ea
ET		 6871 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6872 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6873/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6874 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6875}
6876
81f75bbf
EG		 6877static void bnx2x_reset_common(struct bnx2x *bp)
6878{
619c5cb6
VZ		 6879 u32 val = 0x1400;
6880
81f75bbf
EG		 6881 /* reset_common */
6882 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6883 0xd3ffff7f);
619c5cb6
VZ		 6884
6885 if (CHIP_IS_E3(bp)) {
6886 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6887 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6888 }
6889
6890 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6891}
6892
6893static void bnx2x_setup_dmae(struct bnx2x *bp)
6894{
6895 bp->dmae_ready = 0;
6896 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6897}
6898
573f2035
EG		 6899static void bnx2x_init_pxp(struct bnx2x *bp)
6900{
6901 u16 devctl;
6902 int r_order, w_order;
6903
2a80eebc 6904 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6905 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6906 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6907 if (bp->mrrs == -1)
6908 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6909 else {
6910 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6911 r_order = bp->mrrs;
6912 }
6913
6914 bnx2x_init_pxp_arb(bp, r_order, w_order);
6915}
fd4ef40d
EG		 6916
6917static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6918{
2145a920 6919 int is_required;
fd4ef40d 6920 u32 val;
2145a920 6921 int port;
fd4ef40d 6922
2145a920
VZ		 6923 if (BP_NOMCP(bp))
6924 return;
6925
6926 is_required = 0;
fd4ef40d
EG		 6927 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6928 SHARED_HW_CFG_FAN_FAILURE_MASK;
6929
6930 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6931 is_required = 1;
6932
6933 /*
6934 * The fan failure mechanism is usually related to the PHY type since
6935 * the power consumption of the board is affected by the PHY. Currently,
6936 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6937 */
6938 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6939 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6940 is_required |=
d90d96ba
YR		 6941 bnx2x_fan_failure_det_req(
6942 bp,
6943 bp->common.shmem_base,
a22f0788 6944 bp->common.shmem2_base,
d90d96ba 6945 port);
fd4ef40d
EG		 6946 }
6947
6948 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6949
6950 if (is_required == 0)
6951 return;
6952
6953 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6954 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6955
6956 /* set to active low mode */
6957 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6958 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6959 REG_WR(bp, MISC_REG_SPIO_INT, val);
6960
6961 /* enable interrupt to signal the IGU */
6962 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6963 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6964 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6965}
6966
c9ee9206 6967void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6968{
6969 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6970 val &= ~IGU_PF_CONF_FUNC_EN;
6971
6972 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6973 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6974 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6975}
6976
1191cb83 6977static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6978{
6979 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6980 /* Avoid common init in case MFW supports LFA */
6981 if (SHMEM2_RD(bp, size) >
6982 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6983 return;
619c5cb6
VZ		 6984 shmem_base[0] = bp->common.shmem_base;
6985 shmem2_base[0] = bp->common.shmem2_base;
6986 if (!CHIP_IS_E1x(bp)) {
6987 shmem_base[1] =
6988 SHMEM2_RD(bp, other_shmem_base_addr);
6989 shmem2_base[1] =
6990 SHMEM2_RD(bp, other_shmem2_base_addr);
6991 }
6992 bnx2x_acquire_phy_lock(bp);
6993 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6994 bp->common.chip_id);
6995 bnx2x_release_phy_lock(bp);
6996}
6997
04860eb7
MC		 6998static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6999{
7000 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
7001 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7002 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7003 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7004 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7005
7006 /* make sure this value is 0 */
7007 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7008
7009 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7010 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7011 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7012 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7013}
7014
7015static void bnx2x_set_endianity(struct bnx2x *bp)
7016{
7017#ifdef __BIG_ENDIAN
7018 bnx2x_config_endianity(bp, 1);
7019#else
7020 bnx2x_config_endianity(bp, 0);
7021#endif
7022}
7023
7024static void bnx2x_reset_endianity(struct bnx2x *bp)
7025{
7026 bnx2x_config_endianity(bp, 0);
7027}
7028
619c5cb6
VZ		 7029/**
7030 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7031 *
7032 * @bp: driver handle
7033 */
7034static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 7035{
619c5cb6 7036 u32 val;
a2fbb9ea 7037
51c1a580 7038 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 7039
2031bd3a 7040 /*
2de67439 7041 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 7042 * registers while we're resetting the chip
7043 */
7a06a122 7044 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 7045
81f75bbf 7046 bnx2x_reset_common(bp);
34f80b04 7047 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 7048
619c5cb6
VZ		 7049 val = 0xfffc;
7050 if (CHIP_IS_E3(bp)) {
7051 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7052 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7053 }
7054 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7055
7a06a122 7056 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 7057
619c5cb6 7058 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 7059
619c5cb6
VZ		 7060 if (!CHIP_IS_E1x(bp)) {
7061 u8 abs_func_id;
f2e0899f
DK		 7062
7063 /**
7064 * 4-port mode or 2-port mode we need to turn of master-enable
7065 * for everyone, after that, turn it back on for self.
7066 * so, we disregard multi-function or not, and always disable
7067 * for all functions on the given path, this means 0,2,4,6 for
7068 * path 0 and 1,3,5,7 for path 1
7069 */
619c5cb6
VZ		 7070 for (abs_func_id = BP_PATH(bp);
7071 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7072 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 7073 REG_WR(bp,
7074 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7075 1);
7076 continue;
7077 }
7078
619c5cb6 7079 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 7080 /* clear pf enable */
7081 bnx2x_pf_disable(bp);
7082 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7083 }
7084 }
a2fbb9ea 7085
619c5cb6 7086 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 7087 if (CHIP_IS_E1(bp)) {
7088 /* enable HW interrupt from PXP on USDM overflow
7089 bit 16 on INT_MASK_0 */
7090 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7091 }
a2fbb9ea 7092
619c5cb6 7093 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 7094 bnx2x_init_pxp(bp);
04860eb7 7095 bnx2x_set_endianity(bp);
523224a3
DK		 7096 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7097
34f80b04
EG		 7098 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7099 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 7100
34f80b04
EG		 7101 /* let the HW do it's magic ... */
7102 msleep(100);
7103 /* finish PXP init */
7104 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7105 if (val != 1) {
7106 BNX2X_ERR("PXP2 CFG failed\n");
7107 return -EBUSY;
7108 }
7109 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7110 if (val != 1) {
7111 BNX2X_ERR("PXP2 RD_INIT failed\n");
7112 return -EBUSY;
7113 }
a2fbb9ea 7114
f2e0899f
DK		 7115 /* Timers bug workaround E2 only. We need to set the entire ILT to
7116 * have entries with value "0" and valid bit on.
7117 * This needs to be done by the first PF that is loaded in a path
7118 * (i.e. common phase)
7119 */
619c5cb6
VZ		 7120 if (!CHIP_IS_E1x(bp)) {
7121/* In E2 there is a bug in the timers block that can cause function 6 / 7
7122 * (i.e. vnic3) to start even if it is marked as "scan-off".
7123 * This occurs when a different function (func2,3) is being marked
7124 * as "scan-off". Real-life scenario for example: if a driver is being
7125 * load-unloaded while func6,7 are down. This will cause the timer to access
7126 * the ilt, translate to a logical address and send a request to read/write.
7127 * Since the ilt for the function that is down is not valid, this will cause
7128 * a translation error which is unrecoverable.
7129 * The Workaround is intended to make sure that when this happens nothing fatal
7130 * will occur. The workaround:
7131 * 1. First PF driver which loads on a path will:
7132 * a. After taking the chip out of reset, by using pretend,
7133 * it will write "0" to the following registers of
7134 * the other vnics.
7135 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7136 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7137 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7138 * And for itself it will write '1' to
7139 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7140 * dmae-operations (writing to pram for example.)
7141 * note: can be done for only function 6,7 but cleaner this
7142 * way.
7143 * b. Write zero+valid to the entire ILT.
7144 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7145 * VNIC3 (of that port). The range allocated will be the
7146 * entire ILT. This is needed to prevent ILT range error.
7147 * 2. Any PF driver load flow:
7148 * a. ILT update with the physical addresses of the allocated
7149 * logical pages.
7150 * b. Wait 20msec. - note that this timeout is needed to make
7151 * sure there are no requests in one of the PXP internal
7152 * queues with "old" ILT addresses.
7153 * c. PF enable in the PGLC.
7154 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 7155 * occurred while driver was down)
619c5cb6
VZ		 7156 * e. PF enable in the CFC (WEAK + STRONG)
7157 * f. Timers scan enable
7158 * 3. PF driver unload flow:
7159 * a. Clear the Timers scan_en.
7160 * b. Polling for scan_on=0 for that PF.
7161 * c. Clear the PF enable bit in the PXP.
7162 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7163 * e. Write zero+valid to all ILT entries (The valid bit must
7164 * stay set)
7165 * f. If this is VNIC 3 of a port then also init
7166 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 7167 * to the last entry in the ILT.
619c5cb6
VZ		 7168 *
7169 * Notes:
7170 * Currently the PF error in the PGLC is non recoverable.
7171 * In the future the there will be a recovery routine for this error.
7172 * Currently attention is masked.
7173 * Having an MCP lock on the load/unload process does not guarantee that
7174 * there is no Timer disable during Func6/7 enable. This is because the
7175 * Timers scan is currently being cleared by the MCP on FLR.
7176 * Step 2.d can be done only for PF6/7 and the driver can also check if
7177 * there is error before clearing it. But the flow above is simpler and
7178 * more general.
7179 * All ILT entries are written by zero+valid and not just PF6/7
7180 * ILT entries since in the future the ILT entries allocation for
7181 * PF-s might be dynamic.
7182 */
f2e0899f
DK		 7183 struct ilt_client_info ilt_cli;
7184 struct bnx2x_ilt ilt;
7185 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7186 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7187
b595076a 7188 /* initialize dummy TM client */
f2e0899f
DK		 7189 ilt_cli.start = 0;
7190 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7191 ilt_cli.client_num = ILT_CLIENT_TM;
7192
7193 /* Step 1: set zeroes to all ilt page entries with valid bit on
7194 * Step 2: set the timers first/last ilt entry to point
7195 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 7196 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 7197 *
7198 * both steps performed by call to bnx2x_ilt_client_init_op()
7199 * with dummy TM client
7200 *
7201 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7202 * and his brother are split registers
7203 */
7204 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7205 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7206 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7207
7208 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7209 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7210 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7211 }
7212
34f80b04
EG		 7213 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7214 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 7215
619c5cb6 7216 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7217 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7218 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 7219 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 7220
619c5cb6 7221 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 7222
7223 /* let the HW do it's magic ... */
7224 do {
7225 msleep(200);
7226 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7227 } while (factor-- && (val != 1));
7228
7229 if (val != 1) {
7230 BNX2X_ERR("ATC_INIT failed\n");
7231 return -EBUSY;
7232 }
7233 }
7234
619c5cb6 7235 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 7236
b56e9670
AE		 7237 bnx2x_iov_init_dmae(bp);
7238
34f80b04
EG		 7239 /* clean the DMAE memory */
7240 bp->dmae_ready = 1;
619c5cb6
VZ		 7241 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7242
7243 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7244
7245 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7246
7247 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 7248
619c5cb6 7249 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 7250
34f80b04
EG		 7251 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7252 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7253 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7254 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7255
619c5cb6 7256 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 7257
523224a3
DK		 7258 /* QM queues pointers table */
7259 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7260
34f80b04
EG		 7261 /* soft reset pulse */
7262 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7263 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 7264
55c11941
MS		 7265 if (CNIC_SUPPORT(bp))
7266 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 7267
619c5cb6 7268 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 7269
619c5cb6 7270 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7271 /* enable hw interrupt from doorbell Q */
7272 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7273
619c5cb6 7274 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7275
619c5cb6 7276 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7277 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7278
f2e0899f 7279 if (!CHIP_IS_E1(bp))
619c5cb6 7280 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7281
a3348722
BW		 7282 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7283 if (IS_MF_AFEX(bp)) {
7284 /* configure that VNTag and VLAN headers must be
7285 * received in afex mode
7286 */
7287 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7288 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7289 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7290 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7291 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7292 } else {
7293 /* Bit-map indicating which L2 hdrs may appear
7294 * after the basic Ethernet header
7295 */
7296 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7297 bp->path_has_ovlan ? 7 : 6);
7298 }
7299 }
a2fbb9ea 7300
619c5cb6
VZ		 7301 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7302 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7303 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7304 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7305
619c5cb6
VZ		 7306 if (!CHIP_IS_E1x(bp)) {
7307 /* reset VFC memories */
7308 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7309 VFC_MEMORIES_RST_REG_CAM_RST |
7310 VFC_MEMORIES_RST_REG_RAM_RST);
7311 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7312 VFC_MEMORIES_RST_REG_CAM_RST |
7313 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7314
619c5cb6
VZ		 7315 msleep(20);
7316 }
a2fbb9ea 7317
619c5cb6
VZ		 7318 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7319 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7320 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7321 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7322
34f80b04
EG		 7323 /* sync semi rtc */
7324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7325 0x80000000);
7326 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7327 0x80000000);
a2fbb9ea 7328
619c5cb6
VZ		 7329 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7330 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7331 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7332
a3348722
BW		 7333 if (!CHIP_IS_E1x(bp)) {
7334 if (IS_MF_AFEX(bp)) {
7335 /* configure that VNTag and VLAN headers must be
7336 * sent in afex mode
7337 */
7338 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7339 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7340 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7341 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7342 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7343 } else {
7344 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7345 bp->path_has_ovlan ? 7 : 6);
7346 }
7347 }
f2e0899f 7348
34f80b04 7349 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7350
619c5cb6
VZ		 7351 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7352
55c11941
MS		 7353 if (CNIC_SUPPORT(bp)) {
7354 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7355 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7356 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7357 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7358 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7359 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7360 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7361 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7362 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7363 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7364 }
34f80b04 7365 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7366
34f80b04
EG		 7367 if (sizeof(union cdu_context) != 1024)
7368 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7369 dev_alert(&bp->pdev->dev,
7370 "please adjust the size of cdu_context(%ld)\n",
7371 (long)sizeof(union cdu_context));
a2fbb9ea 7372
619c5cb6 7373 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7374 val = (4 << 24) + (0 << 12) + 1024;
7375 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7376
619c5cb6 7377 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7378 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7379 /* enable context validation interrupt from CFC */
7380 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7381
7382 /* set the thresholds to prevent CFC/CDU race */
7383 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7384
619c5cb6 7385 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7386
619c5cb6 7387 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7388 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7389
619c5cb6
VZ		 7390 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7391 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7392
34f80b04
EG		 7393 /* Reset PCIE errors for debug */
7394 REG_WR(bp, 0x2814, 0xffffffff);
7395 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7396
619c5cb6 7397 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7398 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7399 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7400 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7401 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7402 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7403 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7404 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7405 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7406 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7407 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7408 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7409 }
7410
619c5cb6 7411 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7412 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7413 /* in E3 this done in per-port section */
7414 if (!CHIP_IS_E3(bp))
7415 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7416 }
619c5cb6
VZ		 7417 if (CHIP_IS_E1H(bp))
7418 /* not applicable for E2 (and above ...) */
7419 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7420
7421 if (CHIP_REV_IS_SLOW(bp))
7422 msleep(200);
7423
7424 /* finish CFC init */
7425 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7426 if (val != 1) {
7427 BNX2X_ERR("CFC LL_INIT failed\n");
7428 return -EBUSY;
7429 }
7430 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7431 if (val != 1) {
7432 BNX2X_ERR("CFC AC_INIT failed\n");
7433 return -EBUSY;
7434 }
7435 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7436 if (val != 1) {
7437 BNX2X_ERR("CFC CAM_INIT failed\n");
7438 return -EBUSY;
7439 }
7440 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7441
f2e0899f
DK		 7442 if (CHIP_IS_E1(bp)) {
7443 /* read NIG statistic
7444 to see if this is our first up since powerup */
7445 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7446 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7447
f2e0899f
DK		 7448 /* do internal memory self test */
7449 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7450 BNX2X_ERR("internal mem self test failed\n");
7451 return -EBUSY;
7452 }
34f80b04
EG		 7453 }
7454
fd4ef40d
EG		 7455 bnx2x_setup_fan_failure_detection(bp);
7456
34f80b04
EG		 7457 /* clear PXP2 attentions */
7458 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7459
4a33bc03 7460 bnx2x_enable_blocks_attention(bp);
c9ee9206 7461 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7462
6bbca910 7463 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7464 if (CHIP_IS_E1x(bp))
7465 bnx2x__common_init_phy(bp);
6bbca910
YR		 7466 } else
7467 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7468
230d00eb
YM		 7469 if (SHMEM2_HAS(bp, netproc_fw_ver))
7470 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7471
34f80b04
EG		 7472 return 0;
7473}
a2fbb9ea 7474
619c5cb6
VZ		 7475/**
7476 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7477 *
7478 * @bp: driver handle
7479 */
7480static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7481{
7482 int rc = bnx2x_init_hw_common(bp);
7483
7484 if (rc)
7485 return rc;
7486
7487 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7488 if (!BP_NOMCP(bp))
7489 bnx2x__common_init_phy(bp);
7490
7491 return 0;
7492}
7493
523224a3 7494static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7495{
7496 int port = BP_PORT(bp);
619c5cb6 7497 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7498 u32 low, high;
4293b9f5 7499 u32 val, reg;
a2fbb9ea 7500
51c1a580 7501 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7502
7503 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7504
619c5cb6
VZ		 7505 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7506 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7507 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7508
f2e0899f
DK		 7509 /* Timers bug workaround: disables the pf_master bit in pglue at
7510 * common phase, we need to enable it here before any dmae access are
7511 * attempted. Therefore we manually added the enable-master to the
7512 * port phase (it also happens in the function phase)
7513 */
619c5cb6 7514 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7515 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7516
619c5cb6
VZ		 7517 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7518 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7519 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7520 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7521
7522 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7523 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7524 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7525 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7526
523224a3
DK		 7527 /* QM cid (connection) count */
7528 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7529
55c11941
MS		 7530 if (CNIC_SUPPORT(bp)) {
7531 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7532 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7533 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7534 }
cdaa7cb8 7535
619c5cb6 7536 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7537
2b674047
DK		 7538 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7539
f2e0899f 7540 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7541
7542 if (IS_MF(bp))
7543 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7544 else if (bp->dev->mtu > 4096) {
7545 if (bp->flags & ONE_PORT_FLAG)
7546 low = 160;
7547 else {
7548 val = bp->dev->mtu;
7549 /* (24*1024 + val*4)/256 */
7550 low = 96 + (val/64) +
7551 ((val % 64) ? 1 : 0);
7552 }
7553 } else
7554 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7555 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7556 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7557 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7558 }
1c06328c 7559
619c5cb6
VZ		 7560 if (CHIP_MODE_IS_4_PORT(bp))
7561 REG_WR(bp, (BP_PORT(bp) ?
7562 BRB1_REG_MAC_GUARANTIED_1 :
7563 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7564
619c5cb6 7565 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7566 if (CHIP_IS_E3B0(bp)) {
7567 if (IS_MF_AFEX(bp)) {
7568 /* configure headers for AFEX mode */
7569 REG_WR(bp, BP_PORT(bp) ?
7570 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7571 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7572 REG_WR(bp, BP_PORT(bp) ?
7573 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7574 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7575 REG_WR(bp, BP_PORT(bp) ?
7576 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7577 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7578 } else {
7579 /* Ovlan exists only if we are in multi-function +
7580 * switch-dependent mode, in switch-independent there
7581 * is no ovlan headers
7582 */
7583 REG_WR(bp, BP_PORT(bp) ?
7584 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7585 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7586 (bp->path_has_ovlan ? 7 : 6));
7587 }
7588 }
356e2385 7589
619c5cb6
VZ		 7590 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7591 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7592 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7593 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7594
619c5cb6
VZ		 7595 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7596 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7597 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7598 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7599
619c5cb6
VZ		 7600 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7601 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7602
619c5cb6
VZ		 7603 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7604
7605 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7606 /* configure PBF to work without PAUSE mtu 9000 */
7607 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7608
f2e0899f
DK		 7609 /* update threshold */
7610 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7611 /* update init credit */
7612 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7613
f2e0899f
DK		 7614 /* probe changes */
7615 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7616 udelay(50);
7617 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7618 }
a2fbb9ea 7619
55c11941
MS		 7620 if (CNIC_SUPPORT(bp))
7621 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7622
619c5cb6
VZ		 7623 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7624 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7625
7626 if (CHIP_IS_E1(bp)) {
7627 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7628 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7629 }
619c5cb6 7630 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7631
619c5cb6 7632 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7633
619c5cb6 7634 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7635 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7636 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7637 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7638 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7639 val = IS_MF(bp) ? 0xF7 : 0x7;
7640 /* Enable DCBX attention for all but E1 */
7641 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7642 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7643
4293b9f5
DK		 7644 /* SCPAD_PARITY should NOT trigger close the gates */
7645 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7646 REG_WR(bp, reg,
7647 REG_RD(bp, reg) &
7648 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7649
7650 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7651 REG_WR(bp, reg,
7652 REG_RD(bp, reg) &
7653 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7654
619c5cb6
VZ		 7655 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7656
7657 if (!CHIP_IS_E1x(bp)) {
7658 /* Bit-map indicating which L2 hdrs may appear after the
7659 * basic Ethernet header
7660 */
a3348722
BW		 7661 if (IS_MF_AFEX(bp))
7662 REG_WR(bp, BP_PORT(bp) ?
7663 NIG_REG_P1_HDRS_AFTER_BASIC :
7664 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7665 else
7666 REG_WR(bp, BP_PORT(bp) ?
7667 NIG_REG_P1_HDRS_AFTER_BASIC :
7668 NIG_REG_P0_HDRS_AFTER_BASIC,
7669 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7670
7671 if (CHIP_IS_E3(bp))
7672 REG_WR(bp, BP_PORT(bp) ?
7673 NIG_REG_LLH1_MF_MODE :
7674 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7675 }
7676 if (!CHIP_IS_E3(bp))
7677 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7678
f2e0899f 7679 if (!CHIP_IS_E1(bp)) {
fb3bff17 7680 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7681 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7682 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7683
619c5cb6 7684 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7685 val = 0;
7686 switch (bp->mf_mode) {
7687 case MULTI_FUNCTION_SD:
7688 val = 1;
7689 break;
7690 case MULTI_FUNCTION_SI:
a3348722 7691 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7692 val = 2;
7693 break;
7694 }
7695
7696 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7697 NIG_REG_LLH0_CLS_TYPE), val);
7698 }
1c06328c
EG		 7699 {
7700 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7701 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7702 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7703 }
34f80b04
EG		 7704 }
7705
619c5cb6
VZ		 7706 /* If SPIO5 is set to generate interrupts, enable it for this port */
7707 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7708 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7709 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7710 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7711 val = REG_RD(bp, reg_addr);
f1410647 7712 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7713 REG_WR(bp, reg_addr, val);
f1410647 7714 }
a2fbb9ea 7715
34f80b04
EG		 7716 return 0;
7717}
7718
34f80b04
EG		 7719static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7720{
7721 int reg;
32d68de1 7722 u32 wb_write[2];
34f80b04 7723
f2e0899f 7724 if (CHIP_IS_E1(bp))
34f80b04 7725 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7726 else
7727 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7728
32d68de1
YM		 7729 wb_write[0] = ONCHIP_ADDR1(addr);
7730 wb_write[1] = ONCHIP_ADDR2(addr);
7731 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7732}
7733
b56e9670 7734void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7735{
7736 u32 data, ctl, cnt = 100;
7737 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7738 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7739 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7740 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7741 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7742 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7743
7744 /* Not supported in BC mode */
7745 if (CHIP_INT_MODE_IS_BC(bp))
7746 return;
7747
7748 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7749 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7750 IGU_REGULAR_CLEANUP_SET |
7751 IGU_REGULAR_BCLEANUP;
7752
7753 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7754 func_encode << IGU_CTRL_REG_FID_SHIFT |
7755 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7756
7757 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7758 data, igu_addr_data);
7759 REG_WR(bp, igu_addr_data, data);
7760 mmiowb();
7761 barrier();
7762 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7763 ctl, igu_addr_ctl);
7764 REG_WR(bp, igu_addr_ctl, ctl);
7765 mmiowb();
7766 barrier();
7767
7768 /* wait for clean up to finish */
7769 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7770 msleep(20);
7771
1191cb83
ED		 7772 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7773 DP(NETIF_MSG_HW,
7774 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7775 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7776 }
7777}
7778
7779static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7780{
619c5cb6 7781 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7782}
7783
1191cb83 7784static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7785{
7786 u32 i, base = FUNC_ILT_BASE(func);
7787 for (i = base; i < base + ILT_PER_FUNC; i++)
7788 bnx2x_ilt_wr(bp, i, 0);
7789}
7790
910cc727 7791static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7792{
7793 int port = BP_PORT(bp);
7794 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7795 /* T1 hash bits value determines the T1 number of entries */
7796 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7797}
7798
7799static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7800{
7801 int rc;
7802 struct bnx2x_func_state_params func_params = {NULL};
7803 struct bnx2x_func_switch_update_params *switch_update_params =
7804 &func_params.params.switch_update;
7805
7806 /* Prepare parameters for function state transitions */
7807 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7808 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7809
7810 func_params.f_obj = &bp->func_obj;
7811 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7812
7813 /* Function parameters */
e42780b6
DK		 7814 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7815 &switch_update_params->changes);
7816 if (suspend)
7817 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7818 &switch_update_params->changes);
55c11941
MS		 7819
7820 rc = bnx2x_func_state_change(bp, &func_params);
7821
7822 return rc;
7823}
7824
910cc727 7825static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7826{
7827 int rc, i, port = BP_PORT(bp);
7828 int vlan_en = 0, mac_en[NUM_MACS];
7829
55c11941
MS		 7830 /* Close input from network */
7831 if (bp->mf_mode == SINGLE_FUNCTION) {
7832 bnx2x_set_rx_filter(&bp->link_params, 0);
7833 } else {
7834 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7835 NIG_REG_LLH0_FUNC_EN);
7836 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7837 NIG_REG_LLH0_FUNC_EN, 0);
7838 for (i = 0; i < NUM_MACS; i++) {
7839 mac_en[i] = REG_RD(bp, port ?
7840 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7841 4 * i) :
7842 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7843 4 * i));
7844 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7845 4 * i) :
7846 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7847 }
7848 }
7849
7850 /* Close BMC to host */
7851 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7852 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7853
7854 /* Suspend Tx switching to the PF. Completion of this ramrod
7855 * further guarantees that all the packets of that PF / child
7856 * VFs in BRB were processed by the Parser, so it is safe to
7857 * change the NIC_MODE register.
7858 */
7859 rc = bnx2x_func_switch_update(bp, 1);
7860 if (rc) {
7861 BNX2X_ERR("Can't suspend tx-switching!\n");
7862 return rc;
7863 }
7864
7865 /* Change NIC_MODE register */
7866 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7867
7868 /* Open input from network */
7869 if (bp->mf_mode == SINGLE_FUNCTION) {
7870 bnx2x_set_rx_filter(&bp->link_params, 1);
7871 } else {
7872 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7873 NIG_REG_LLH0_FUNC_EN, vlan_en);
7874 for (i = 0; i < NUM_MACS; i++) {
7875 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7876 4 * i) :
7877 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7878 mac_en[i]);
7879 }
7880 }
7881
7882 /* Enable BMC to host */
7883 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7884 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7885
7886 /* Resume Tx switching to the PF */
7887 rc = bnx2x_func_switch_update(bp, 0);
7888 if (rc) {
7889 BNX2X_ERR("Can't resume tx-switching!\n");
7890 return rc;
7891 }
7892
7893 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7894 return 0;
7895}
7896
7897int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7898{
7899 int rc;
7900
7901 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7902
7903 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7904 /* Configure searcher as part of function hw init */
55c11941
MS		 7905 bnx2x_init_searcher(bp);
7906
7907 /* Reset NIC mode */
7908 rc = bnx2x_reset_nic_mode(bp);
7909 if (rc)
7910 BNX2X_ERR("Can't change NIC mode!\n");
7911 return rc;
7912 }
7913
7914 return 0;
7915}
7916
da254fbc
YM		 7917/* previous driver DMAE transaction may have occurred when pre-boot stage ended
7918 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7919 * the addresses of the transaction, resulting in was-error bit set in the pci
7920 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7921 * to clear the interrupt which detected this from the pglueb and the was done
7922 * bit
7923 */
7924static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7925{
7926 if (!CHIP_IS_E1x(bp))
7927 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7928 1 << BP_ABS_FUNC(bp));
7929}
7930
523224a3 7931static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7932{
7933 int port = BP_PORT(bp);
7934 int func = BP_FUNC(bp);
619c5cb6 7935 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7936 struct bnx2x_ilt *ilt = BP_ILT(bp);
7937 u16 cdu_ilt_start;
8badd27a 7938 u32 addr, val;
f4a66897 7939 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7940 int i, main_mem_width, rc;
34f80b04 7941
51c1a580 7942 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7943
619c5cb6 7944 /* FLR cleanup - hmmm */
89db4ad8
AE		 7945 if (!CHIP_IS_E1x(bp)) {
7946 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7947 if (rc) {
7948 bnx2x_fw_dump(bp);
89db4ad8 7949 return rc;
04c46736 7950 }
89db4ad8 7951 }
619c5cb6 7952
8badd27a 7953 /* set MSI reconfigure capability */
f2e0899f
DK		 7954 if (bp->common.int_block == INT_BLOCK_HC) {
7955 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7956 val = REG_RD(bp, addr);
7957 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7958 REG_WR(bp, addr, val);
7959 }
8badd27a 7960
619c5cb6
VZ		 7961 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7962 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7963
523224a3
DK		 7964 ilt = BP_ILT(bp);
7965 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7966
290ca2bb
AE		 7967 if (IS_SRIOV(bp))
7968 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7969 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7970
7971 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7972 * those of the VFs, so start line should be reset
7973 */
7974 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7975 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7976 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7977 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7978 bp->context[i].cxt_mapping;
7979 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7980 }
290ca2bb 7981
523224a3 7982 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7983
55c11941
MS		 7984 if (!CONFIGURE_NIC_MODE(bp)) {
7985 bnx2x_init_searcher(bp);
7986 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7987 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7988 } else {
7989 /* Set NIC mode */
7990 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 7991 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 7992 }
37b091ba 7993
619c5cb6 7994 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7995 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7996
7997 /* Turn on a single ISR mode in IGU if driver is going to use
7998 * INT#x or MSI
7999 */
8000 if (!(bp->flags & USING_MSIX_FLAG))
8001 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8002 /*
8003 * Timers workaround bug: function init part.
8004 * Need to wait 20msec after initializing ILT,
8005 * needed to make sure there are no requests in
8006 * one of the PXP internal queues with "old" ILT addresses
8007 */
8008 msleep(20);
8009 /*
8010 * Master enable - Due to WB DMAE writes performed before this
8011 * register is re-initialized as part of the regular function
8012 * init
8013 */
8014 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8015 /* Enable the function in IGU */
8016 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8017 }
8018
523224a3 8019 bp->dmae_ready = 1;
34f80b04 8020
619c5cb6 8021 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 8022
da254fbc 8023 bnx2x_clean_pglue_errors(bp);
f2e0899f 8024
619c5cb6
VZ		 8025 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8026 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8027 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8028 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8029 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8030 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8031 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8032 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8033 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8034 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8035 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8036 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8037 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8038
8039 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8040 REG_WR(bp, QM_REG_PF_EN, 1);
8041
619c5cb6
VZ		 8042 if (!CHIP_IS_E1x(bp)) {
8043 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8044 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8045 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8046 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8047 }
8048 bnx2x_init_block(bp, BLOCK_QM, init_phase);
8049
8050 bnx2x_init_block(bp, BLOCK_TM, init_phase);
8051 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 8052 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 8053
8054 bnx2x_iov_init_dq(bp);
8055
619c5cb6
VZ		 8056 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8057 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8058 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8059 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8060 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8061 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8062 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8063 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8064 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8065 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8066 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8067
619c5cb6 8068 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 8069
619c5cb6 8070 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 8071
619c5cb6 8072 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8073 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8074
fb3bff17 8075 if (IS_MF(bp)) {
7609647e
YM		 8076 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8077 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8078 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8079 bp->mf_ov);
8080 }
34f80b04
EG		 8081 }
8082
619c5cb6 8083 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 8084
34f80b04 8085 /* HC init per function */
f2e0899f
DK		 8086 if (bp->common.int_block == INT_BLOCK_HC) {
8087 if (CHIP_IS_E1H(bp)) {
8088 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8089
8090 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8091 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8092 }
619c5cb6 8093 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 8094
8095 } else {
8096 int num_segs, sb_idx, prod_offset;
8097
34f80b04
EG		 8098 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8099
619c5cb6 8100 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8101 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8102 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8103 }
8104
619c5cb6 8105 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 8106
619c5cb6 8107 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8108 int dsb_idx = 0;
8109 /**
8110 * Producer memory:
8111 * E2 mode: address 0-135 match to the mapping memory;
8112 * 136 - PF0 default prod; 137 - PF1 default prod;
8113 * 138 - PF2 default prod; 139 - PF3 default prod;
8114 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8115 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8116 * 144-147 reserved.
8117 *
8118 * E1.5 mode - In backward compatible mode;
8119 * for non default SB; each even line in the memory
8120 * holds the U producer and each odd line hold
8121 * the C producer. The first 128 producers are for
8122 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8123 * producers are for the DSB for each PF.
8124 * Each PF has five segments: (the order inside each
8125 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8126 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8127 * 144-147 attn prods;
8128 */
8129 /* non-default-status-blocks */
8130 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8131 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8132 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8133 prod_offset = (bp->igu_base_sb + sb_idx) *
8134 num_segs;
8135
8136 for (i = 0; i < num_segs; i++) {
8137 addr = IGU_REG_PROD_CONS_MEMORY +
8138 (prod_offset + i) * 4;
8139 REG_WR(bp, addr, 0);
8140 }
8141 /* send consumer update with value 0 */
8142 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8143 USTORM_ID, 0, IGU_INT_NOP, 1);
8144 bnx2x_igu_clear_sb(bp,
8145 bp->igu_base_sb + sb_idx);
8146 }
8147
8148 /* default-status-blocks */
8149 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8150 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8151
8152 if (CHIP_MODE_IS_4_PORT(bp))
8153 dsb_idx = BP_FUNC(bp);
8154 else
3395a033 8155 dsb_idx = BP_VN(bp);
f2e0899f
DK		 8156
8157 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8158 IGU_BC_BASE_DSB_PROD + dsb_idx :
8159 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8160
3395a033
DK		 8161 /*
8162 * igu prods come in chunks of E1HVN_MAX (4) -
8163 * does not matters what is the current chip mode
8164 */
f2e0899f
DK		 8165 for (i = 0; i < (num_segs * E1HVN_MAX);
8166 i += E1HVN_MAX) {
8167 addr = IGU_REG_PROD_CONS_MEMORY +
8168 (prod_offset + i)*4;
8169 REG_WR(bp, addr, 0);
8170 }
8171 /* send consumer update with 0 */
8172 if (CHIP_INT_MODE_IS_BC(bp)) {
8173 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8174 USTORM_ID, 0, IGU_INT_NOP, 1);
8175 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8176 CSTORM_ID, 0, IGU_INT_NOP, 1);
8177 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8178 XSTORM_ID, 0, IGU_INT_NOP, 1);
8179 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8180 TSTORM_ID, 0, IGU_INT_NOP, 1);
8181 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8182 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8183 } else {
8184 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8185 USTORM_ID, 0, IGU_INT_NOP, 1);
8186 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8187 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8188 }
8189 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8190
16a5fd92 8191 /* !!! These should become driver const once
f2e0899f
DK		 8192 rf-tool supports split-68 const */
8193 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8194 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8195 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8196 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8197 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8198 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8199 }
34f80b04 8200 }
34f80b04 8201
c14423fe 8202 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 8203 REG_WR(bp, 0x2114, 0xffffffff);
8204 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 8205
f4a66897
VZ		 8206 if (CHIP_IS_E1x(bp)) {
8207 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8208 main_mem_base = HC_REG_MAIN_MEMORY +
8209 BP_PORT(bp) * (main_mem_size * 4);
8210 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8211 main_mem_width = 8;
8212
8213 val = REG_RD(bp, main_mem_prty_clr);
8214 if (val)
51c1a580
MS		 8215 DP(NETIF_MSG_HW,
8216 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8217 val);
f4a66897
VZ		 8218
8219 /* Clear "false" parity errors in MSI-X table */
8220 for (i = main_mem_base;
8221 i < main_mem_base + main_mem_size * 4;
8222 i += main_mem_width) {
8223 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8224 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8225 i, main_mem_width / 4);
8226 }
8227 /* Clear HC parity attention */
8228 REG_RD(bp, main_mem_prty_clr);
8229 }
8230
619c5cb6
VZ		 8231#ifdef BNX2X_STOP_ON_ERROR
8232 /* Enable STORMs SP logging */
8233 REG_WR8(bp, BAR_USTRORM_INTMEM +
8234 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8235 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8236 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8237 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8238 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8239 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8240 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8241#endif
8242
b7737c9b 8243 bnx2x_phy_probe(&bp->link_params);
f85582f8 8244
34f80b04
EG		 8245 return 0;
8246}
8247
55c11941
MS		 8248void bnx2x_free_mem_cnic(struct bnx2x *bp)
8249{
8250 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8251
8252 if (!CHIP_IS_E1x(bp))
8253 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8254 sizeof(struct host_hc_status_block_e2));
8255 else
8256 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8257 sizeof(struct host_hc_status_block_e1x));
8258
8259 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8260}
8261
9f6c9258 8262void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 8263{
a052997e
MS		 8264 int i;
8265
619c5cb6
VZ		 8266 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8267 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8268
b4cddbd6
AE		 8269 if (IS_VF(bp))
8270 return;
8271
8272 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8273 sizeof(struct host_sp_status_block));
8274
a2fbb9ea 8275 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 8276 sizeof(struct bnx2x_slowpath));
a2fbb9ea 8277
a052997e
MS		 8278 for (i = 0; i < L2_ILT_LINES(bp); i++)
8279 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8280 bp->context[i].size);
523224a3
DK		 8281 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8282
8283 BNX2X_FREE(bp->ilt->lines);
f85582f8 8284
7a9b2557 8285 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 8286
523224a3
DK		 8287 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8288 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 8289
05952246
YM		 8290 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8291
580d9d08 8292 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8293}
8294
55c11941 8295int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8296{
cd2b0389 8297 if (!CHIP_IS_E1x(bp)) {
619c5cb6 8298 /* size = the status block + ramrod buffers */
cd2b0389
JP		 8299 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8300 sizeof(struct host_hc_status_block_e2));
8301 if (!bp->cnic_sb.e2_sb)
8302 goto alloc_mem_err;
8303 } else {
8304 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8305 sizeof(struct host_hc_status_block_e1x));
8306 if (!bp->cnic_sb.e1x_sb)
8307 goto alloc_mem_err;
8308 }
8badd27a 8309
cd2b0389 8310 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
16a5fd92 8311 /* allocate searcher T2 table, as it wasn't allocated before */
cd2b0389
JP		 8312 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8313 if (!bp->t2)
8314 goto alloc_mem_err;
8315 }
55c11941
MS		 8316
8317 /* write address to which L5 should insert its values */
8318 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8319 &bp->slowpath->drv_info_to_mcp;
8320
8321 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8322 goto alloc_mem_err;
8323
8324 return 0;
8325
8326alloc_mem_err:
8327 bnx2x_free_mem_cnic(bp);
8328 BNX2X_ERR("Can't allocate memory\n");
8329 return -ENOMEM;
8330}
8331
8332int bnx2x_alloc_mem(struct bnx2x *bp)
8333{
8334 int i, allocated, context_size;
a2fbb9ea 8335
cd2b0389 8336 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
55c11941 8337 /* allocate searcher T2 table */
cd2b0389
JP		 8338 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8339 if (!bp->t2)
8340 goto alloc_mem_err;
8341 }
8badd27a 8342
cd2b0389
JP		 8343 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8344 sizeof(struct host_sp_status_block));
8345 if (!bp->def_status_blk)
8346 goto alloc_mem_err;
a2fbb9ea 8347
cd2b0389
JP		 8348 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8349 sizeof(struct bnx2x_slowpath));
8350 if (!bp->slowpath)
8351 goto alloc_mem_err;
a2fbb9ea 8352
a052997e
MS		 8353 /* Allocate memory for CDU context:
8354 * This memory is allocated separately and not in the generic ILT
8355 * functions because CDU differs in few aspects:
8356 * 1. There are multiple entities allocating memory for context -
8357 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8358 * its own ILT lines.
8359 * 2. Since CDU page-size is not a single 4KB page (which is the case
8360 * for the other ILT clients), to be efficient we want to support
8361 * allocation of sub-page-size in the last entry.
8362 * 3. Context pointers are used by the driver to pass to FW / update
8363 * the context (for the other ILT clients the pointers are used just to
8364 * free the memory during unload).
8365 */
8366 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8367
a052997e
MS		 8368 for (i = 0, allocated = 0; allocated < context_size; i++) {
8369 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8370 (context_size - allocated));
cd2b0389
JP		 8371 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8372 bp->context[i].size);
8373 if (!bp->context[i].vcxt)
8374 goto alloc_mem_err;
a052997e
MS		 8375 allocated += bp->context[i].size;
8376 }
cd2b0389
JP		 8377 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8378 GFP_KERNEL);
8379 if (!bp->ilt->lines)
8380 goto alloc_mem_err;
65abd74d 8381
523224a3
DK		 8382 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8383 goto alloc_mem_err;
65abd74d 8384
67c431a5
AE		 8385 if (bnx2x_iov_alloc_mem(bp))
8386 goto alloc_mem_err;
8387
9f6c9258 8388 /* Slow path ring */
cd2b0389
JP		 8389 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8390 if (!bp->spq)
8391 goto alloc_mem_err;
65abd74d 8392
523224a3 8393 /* EQ */
cd2b0389
JP		 8394 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8395 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8396 if (!bp->eq_ring)
8397 goto alloc_mem_err;
ab532cf3 8398
9f6c9258 8399 return 0;
e1510706 8400
9f6c9258
DK		 8401alloc_mem_err:
8402 bnx2x_free_mem(bp);
51c1a580 8403 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8404 return -ENOMEM;
65abd74d
YG		 8405}
8406
a2fbb9ea
ET		 8407/*
8408 * Init service functions
8409 */
a2fbb9ea 8410
619c5cb6
VZ		 8411int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8412 struct bnx2x_vlan_mac_obj *obj, bool set,
8413 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8414{
619c5cb6
VZ		 8415 int rc;
8416 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8417
619c5cb6 8418 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8419
619c5cb6
VZ		 8420 /* Fill general parameters */
8421 ramrod_param.vlan_mac_obj = obj;
8422 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8423
619c5cb6
VZ		 8424 /* Fill a user request section if needed */
8425 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8426 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8427
619c5cb6 8428 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8429
619c5cb6
VZ		 8430 /* Set the command: ADD or DEL */
8431 if (set)
8432 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8433 else
8434 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8435 }
8436
619c5cb6 8437 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8438
8439 if (rc == -EEXIST) {
8440 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8441 /* do not treat adding same MAC as error */
8442 rc = 0;
8443 } else if (rc < 0)
619c5cb6 8444 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8445
619c5cb6 8446 return rc;
a2fbb9ea
ET		 8447}
8448
05cc5a39
YM		 8449int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8450 struct bnx2x_vlan_mac_obj *obj, bool set,
8451 unsigned long *ramrod_flags)
8452{
8453 int rc;
8454 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8455
8456 memset(&ramrod_param, 0, sizeof(ramrod_param));
8457
8458 /* Fill general parameters */
8459 ramrod_param.vlan_mac_obj = obj;
8460 ramrod_param.ramrod_flags = *ramrod_flags;
8461
8462 /* Fill a user request section if needed */
8463 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8464 ramrod_param.user_req.u.vlan.vlan = vlan;
8465 /* Set the command: ADD or DEL */
8466 if (set)
8467 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8468 else
8469 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8470 }
8471
8472 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8473
8474 if (rc == -EEXIST) {
8475 /* Do not treat adding same vlan as error. */
8476 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8477 rc = 0;
8478 } else if (rc < 0) {
8479 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8480 }
8481
8482 return rc;
8483}
8484
619c5cb6
VZ		 8485int bnx2x_del_all_macs(struct bnx2x *bp,
8486 struct bnx2x_vlan_mac_obj *mac_obj,
8487 int mac_type, bool wait_for_comp)
e665bfda 8488{
619c5cb6
VZ		 8489 int rc;
8490 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8491
619c5cb6
VZ		 8492 /* Wait for completion of requested */
8493 if (wait_for_comp)
8494 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8495
619c5cb6
VZ		 8496 /* Set the mac type of addresses we want to clear */
8497 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8498
619c5cb6
VZ		 8499 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8500 if (rc < 0)
8501 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8502
619c5cb6 8503 return rc;
0793f83f
DK		 8504}
8505
619c5cb6 8506int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8507{
f8f4f61a
DK		 8508 if (IS_PF(bp)) {
8509 unsigned long ramrod_flags = 0;
0793f83f 8510
f8f4f61a
DK		 8511 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8512 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8513 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8514 &bp->sp_objs->mac_obj, set,
8515 BNX2X_ETH_MAC, &ramrod_flags);
8516 } else { /* vf */
8517 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
bb9e9c1d 8518 bp->fp->index, set);
f8f4f61a 8519 }
e665bfda 8520}
6e30dd4e 8521
619c5cb6 8522int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8523{
60cad4e6
AE		 8524 if (IS_PF(bp))
8525 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8526 else /* VF */
8527 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8528}
a2fbb9ea 8529
d6214d7a 8530/**
e8920674 8531 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8532 *
e8920674 8533 * @bp: driver handle
d6214d7a 8534 *
e8920674 8535 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8536 */
1ab4434c 8537int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8538{
1ab4434c
AE		 8539 int rc = 0;
8540
60cad4e6
AE		 8541 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8542 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8543 return -EINVAL;
60cad4e6 8544 }
1ab4434c 8545
9ee3d37b 8546 switch (int_mode) {
1ab4434c
AE		 8547 case BNX2X_INT_MODE_MSIX:
8548 /* attempt to enable msix */
8549 rc = bnx2x_enable_msix(bp);
8550
8551 /* msix attained */
8552 if (!rc)
8553 return 0;
8554
8555 /* vfs use only msix */
8556 if (rc && IS_VF(bp))
8557 return rc;
8558
8559 /* failed to enable multiple MSI-X */
8560 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8561 bp->num_queues,
8562 1 + bp->num_cnic_queues);
8563
8564 /* falling through... */
8565 case BNX2X_INT_MODE_MSI:
d6214d7a 8566 bnx2x_enable_msi(bp);
1ab4434c 8567
d6214d7a 8568 /* falling through... */
1ab4434c 8569 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8570 bp->num_ethernet_queues = 1;
8571 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8572 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8573 break;
d6214d7a 8574 default:
1ab4434c
AE		 8575 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8576 return -EINVAL;
9f6c9258 8577 }
1ab4434c 8578 return 0;
a2fbb9ea
ET		 8579}
8580
1ab4434c 8581/* must be called prior to any HW initializations */
c2bff63f
DK		 8582static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8583{
290ca2bb
AE		 8584 if (IS_SRIOV(bp))
8585 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8586 return L2_ILT_LINES(bp);
8587}
8588
523224a3
DK		 8589void bnx2x_ilt_set_info(struct bnx2x *bp)
8590{
8591 struct ilt_client_info *ilt_client;
8592 struct bnx2x_ilt *ilt = BP_ILT(bp);
8593 u16 line = 0;
8594
8595 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8596 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8597
8598 /* CDU */
8599 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8600 ilt_client->client_num = ILT_CLIENT_CDU;
8601 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8602 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8603 ilt_client->start = line;
619c5cb6 8604 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8605
8606 if (CNIC_SUPPORT(bp))
8607 line += CNIC_ILT_LINES;
523224a3
DK		 8608 ilt_client->end = line - 1;
8609
51c1a580 8610 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8611 ilt_client->start,
8612 ilt_client->end,
8613 ilt_client->page_size,
8614 ilt_client->flags,
8615 ilog2(ilt_client->page_size >> 12));
8616
8617 /* QM */
8618 if (QM_INIT(bp->qm_cid_count)) {
8619 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8620 ilt_client->client_num = ILT_CLIENT_QM;
8621 ilt_client->page_size = QM_ILT_PAGE_SZ;
8622 ilt_client->flags = 0;
8623 ilt_client->start = line;
8624
8625 /* 4 bytes for each cid */
8626 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8627 QM_ILT_PAGE_SZ);
8628
8629 ilt_client->end = line - 1;
8630
51c1a580
MS		 8631 DP(NETIF_MSG_IFUP,
8632 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8633 ilt_client->start,
8634 ilt_client->end,
8635 ilt_client->page_size,
8636 ilt_client->flags,
8637 ilog2(ilt_client->page_size >> 12));
523224a3 8638 }
523224a3 8639
55c11941
MS		 8640 if (CNIC_SUPPORT(bp)) {
8641 /* SRC */
8642 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8643 ilt_client->client_num = ILT_CLIENT_SRC;
8644 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8645 ilt_client->flags = 0;
8646 ilt_client->start = line;
8647 line += SRC_ILT_LINES;
8648 ilt_client->end = line - 1;
523224a3 8649
55c11941
MS		 8650 DP(NETIF_MSG_IFUP,
8651 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8652 ilt_client->start,
8653 ilt_client->end,
8654 ilt_client->page_size,
8655 ilt_client->flags,
8656 ilog2(ilt_client->page_size >> 12));
9f6c9258 8657
55c11941
MS		 8658 /* TM */
8659 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8660 ilt_client->client_num = ILT_CLIENT_TM;
8661 ilt_client->page_size = TM_ILT_PAGE_SZ;
8662 ilt_client->flags = 0;
8663 ilt_client->start = line;
8664 line += TM_ILT_LINES;
8665 ilt_client->end = line - 1;
523224a3 8666
55c11941
MS		 8667 DP(NETIF_MSG_IFUP,
8668 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8669 ilt_client->start,
8670 ilt_client->end,
8671 ilt_client->page_size,
8672 ilt_client->flags,
8673 ilog2(ilt_client->page_size >> 12));
8674 }
9f6c9258 8675
619c5cb6 8676 BUG_ON(line > ILT_MAX_LINES);
523224a3 8677}
f85582f8 8678
619c5cb6
VZ		 8679/**
8680 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8681 *
8682 * @bp: driver handle
8683 * @fp: pointer to fastpath
8684 * @init_params: pointer to parameters structure
8685 *
8686 * parameters configured:
8687 * - HC configuration
8688 * - Queue's CDU context
8689 */
1191cb83 8690static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8691 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8692{
6383c0b3 8693 u8 cos;
a052997e
MS		 8694 int cxt_index, cxt_offset;
8695
619c5cb6
VZ		 8696 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8697 if (!IS_FCOE_FP(fp)) {
8698 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8699 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8700
16a5fd92 8701 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8702 * to INIT state.
8703 */
8704 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8705 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8706
8707 /* HC rate */
8708 init_params->rx.hc_rate = bp->rx_ticks ?
8709 (1000000 / bp->rx_ticks) : 0;
8710 init_params->tx.hc_rate = bp->tx_ticks ?
8711 (1000000 / bp->tx_ticks) : 0;
8712
8713 /* FW SB ID */
8714 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8715 fp->fw_sb_id;
8716
8717 /*
8718 * CQ index among the SB indices: FCoE clients uses the default
8719 * SB, therefore it's different.
8720 */
6383c0b3
AE		 8721 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8722 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8723 }
8724
6383c0b3
AE		 8725 /* set maximum number of COSs supported by this queue */
8726 init_params->max_cos = fp->max_cos;
8727
51c1a580 8728 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8729 fp->index, init_params->max_cos);
8730
8731 /* set the context pointers queue object */
a052997e 8732 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8733 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8734 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8735 ILT_PAGE_CIDS);
6383c0b3 8736 init_params->cxts[cos] =
a052997e
MS		 8737 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8738 }
619c5cb6
VZ		 8739}
8740
910cc727 8741static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8742 struct bnx2x_queue_state_params *q_params,
8743 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8744 int tx_index, bool leading)
8745{
8746 memset(tx_only_params, 0, sizeof(*tx_only_params));
8747
8748 /* Set the command */
8749 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8750
8751 /* Set tx-only QUEUE flags: don't zero statistics */
8752 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8753
8754 /* choose the index of the cid to send the slow path on */
8755 tx_only_params->cid_index = tx_index;
8756
8757 /* Set general TX_ONLY_SETUP parameters */
8758 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8759
8760 /* Set Tx TX_ONLY_SETUP parameters */
8761 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8762
51c1a580
MS		 8763 DP(NETIF_MSG_IFUP,
8764 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8765 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8766 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8767 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8768
8769 /* send the ramrod */
8770 return bnx2x_queue_state_change(bp, q_params);
8771}
8772
619c5cb6
VZ		 8773/**
8774 * bnx2x_setup_queue - setup queue
8775 *
8776 * @bp: driver handle
8777 * @fp: pointer to fastpath
8778 * @leading: is leading
8779 *
8780 * This function performs 2 steps in a Queue state machine
8781 * actually: 1) RESET->INIT 2) INIT->SETUP
8782 */
8783
8784int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8785 bool leading)
8786{
3b603066 8787 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8788 struct bnx2x_queue_setup_params *setup_params =
8789 &q_params.params.setup;
6383c0b3
AE		 8790 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8791 &q_params.params.tx_only;
a2fbb9ea 8792 int rc;
6383c0b3
AE		 8793 u8 tx_index;
8794
51c1a580 8795 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8796
ec6ba945
VZ		 8797 /* reset IGU state skip FCoE L2 queue */
8798 if (!IS_FCOE_FP(fp))
8799 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8800 IGU_INT_ENABLE, 0);
a2fbb9ea 8801
15192a8c 8802 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8803 /* We want to wait for completion in this context */
8804 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8805
619c5cb6
VZ		 8806 /* Prepare the INIT parameters */
8807 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8808
619c5cb6
VZ		 8809 /* Set the command */
8810 q_params.cmd = BNX2X_Q_CMD_INIT;
8811
8812 /* Change the state to INIT */
8813 rc = bnx2x_queue_state_change(bp, &q_params);
8814 if (rc) {
6383c0b3 8815 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8816 return rc;
8817 }
ec6ba945 8818
51c1a580 8819 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8820
619c5cb6
VZ		 8821 /* Now move the Queue to the SETUP state... */
8822 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8823
619c5cb6
VZ		 8824 /* Set QUEUE flags */
8825 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8826
619c5cb6 8827 /* Set general SETUP parameters */
6383c0b3
AE		 8828 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8829 FIRST_TX_COS_INDEX);
619c5cb6 8830
6383c0b3 8831 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8832 &setup_params->rxq_params);
8833
6383c0b3
AE		 8834 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8835 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8836
8837 /* Set the command */
8838 q_params.cmd = BNX2X_Q_CMD_SETUP;
8839
55c11941
MS		 8840 if (IS_FCOE_FP(fp))
8841 bp->fcoe_init = true;
8842
619c5cb6
VZ		 8843 /* Change the state to SETUP */
8844 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8845 if (rc) {
8846 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8847 return rc;
8848 }
8849
8850 /* loop through the relevant tx-only indices */
8851 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8852 tx_index < fp->max_cos;
8853 tx_index++) {
8854
8855 /* prepare and send tx-only ramrod*/
8856 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8857 tx_only_params, tx_index, leading);
8858 if (rc) {
8859 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8860 fp->index, tx_index);
8861 return rc;
8862 }
8863 }
523224a3 8864
34f80b04 8865 return rc;
a2fbb9ea
ET		 8866}
8867
619c5cb6 8868static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8869{
619c5cb6 8870 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8871 struct bnx2x_fp_txdata *txdata;
3b603066 8872 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8873 int rc, tx_index;
8874
51c1a580 8875 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8876
15192a8c 8877 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8878 /* We want to wait for completion in this context */
8879 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8880
6383c0b3
AE		 8881 /* close tx-only connections */
8882 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8883 tx_index < fp->max_cos;
8884 tx_index++){
8885
8886 /* ascertain this is a normal queue*/
65565884 8887 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8888
51c1a580 8889 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8890 txdata->txq_index);
8891
8892 /* send halt terminate on tx-only connection */
8893 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8894 memset(&q_params.params.terminate, 0,
8895 sizeof(q_params.params.terminate));
8896 q_params.params.terminate.cid_index = tx_index;
8897
8898 rc = bnx2x_queue_state_change(bp, &q_params);
8899 if (rc)
8900 return rc;
8901
8902 /* send halt terminate on tx-only connection */
8903 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8904 memset(&q_params.params.cfc_del, 0,
8905 sizeof(q_params.params.cfc_del));
8906 q_params.params.cfc_del.cid_index = tx_index;
8907 rc = bnx2x_queue_state_change(bp, &q_params);
8908 if (rc)
8909 return rc;
8910 }
8911 /* Stop the primary connection: */
8912 /* ...halt the connection */
619c5cb6
VZ		 8913 q_params.cmd = BNX2X_Q_CMD_HALT;
8914 rc = bnx2x_queue_state_change(bp, &q_params);
8915 if (rc)
da5a662a 8916 return rc;
a2fbb9ea 8917
6383c0b3 8918 /* ...terminate the connection */
619c5cb6 8919 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8920 memset(&q_params.params.terminate, 0,
8921 sizeof(q_params.params.terminate));
8922 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8923 rc = bnx2x_queue_state_change(bp, &q_params);
8924 if (rc)
523224a3 8925 return rc;
6383c0b3 8926 /* ...delete cfc entry */
619c5cb6 8927 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8928 memset(&q_params.params.cfc_del, 0,
8929 sizeof(q_params.params.cfc_del));
8930 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8931 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8932}
8933
34f80b04
EG		 8934static void bnx2x_reset_func(struct bnx2x *bp)
8935{
8936 int port = BP_PORT(bp);
8937 int func = BP_FUNC(bp);
f2e0899f 8938 int i;
523224a3
DK		 8939
8940 /* Disable the function in the FW */
8941 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8942 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8943 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8944 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8945
8946 /* FP SBs */
ec6ba945 8947 for_each_eth_queue(bp, i) {
523224a3 8948 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8949 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8950 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8951 SB_DISABLED);
523224a3
DK		 8952 }
8953
55c11941
MS		 8954 if (CNIC_LOADED(bp))
8955 /* CNIC SB */
8956 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8957 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8958 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8959
523224a3 8960 /* SP SB */
619c5cb6 8961 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8962 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8963 SB_DISABLED);
523224a3
DK		 8964
8965 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8966 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8967 0);
34f80b04
EG		 8968
8969 /* Configure IGU */
f2e0899f
DK		 8970 if (bp->common.int_block == INT_BLOCK_HC) {
8971 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8972 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8973 } else {
8974 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8975 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8976 }
34f80b04 8977
55c11941
MS		 8978 if (CNIC_LOADED(bp)) {
8979 /* Disable Timer scan */
8980 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8981 /*
8982 * Wait for at least 10ms and up to 2 second for the timers
8983 * scan to complete
8984 */
8985 for (i = 0; i < 200; i++) {
639d65b8 8986 usleep_range(10000, 20000);
55c11941
MS		 8987 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8988 break;
8989 }
37b091ba 8990 }
34f80b04 8991 /* Clear ILT */
f2e0899f
DK		 8992 bnx2x_clear_func_ilt(bp, func);
8993
8994 /* Timers workaround bug for E2: if this is vnic-3,
8995 * we need to set the entire ilt range for this timers.
8996 */
619c5cb6 8997 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8998 struct ilt_client_info ilt_cli;
8999 /* use dummy TM client */
9000 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
9001 ilt_cli.start = 0;
9002 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9003 ilt_cli.client_num = ILT_CLIENT_TM;
9004
9005 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9006 }
9007
9008 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 9009 if (!CHIP_IS_E1x(bp))
f2e0899f 9010 bnx2x_pf_disable(bp);
523224a3
DK		 9011
9012 bp->dmae_ready = 0;
34f80b04
EG		 9013}
9014
9015static void bnx2x_reset_port(struct bnx2x *bp)
9016{
9017 int port = BP_PORT(bp);
9018 u32 val;
9019
619c5cb6
VZ		 9020 /* Reset physical Link */
9021 bnx2x__link_reset(bp);
9022
34f80b04
EG		 9023 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9024
9025 /* Do not rcv packets to BRB */
9026 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9027 /* Do not direct rcv packets that are not for MCP to the BRB */
9028 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9029 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9030
9031 /* Configure AEU */
9032 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9033
9034 msleep(100);
9035 /* Check for BRB port occupancy */
9036 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9037 if (val)
9038 DP(NETIF_MSG_IFDOWN,
33471629 9039 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 9040
9041 /* TODO: Close Doorbell port? */
9042}
9043
1191cb83 9044static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 9045{
3b603066 9046 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 9047
619c5cb6
VZ		 9048 /* Prepare parameters for function state transitions */
9049 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 9050
619c5cb6
VZ		 9051 func_params.f_obj = &bp->func_obj;
9052 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 9053
619c5cb6 9054 func_params.params.hw_init.load_phase = load_code;
49d66772 9055
619c5cb6 9056 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 9057}
9058
1191cb83 9059static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 9060{
3b603066 9061 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 9062 int rc;
228241eb 9063
619c5cb6
VZ		 9064 /* Prepare parameters for function state transitions */
9065 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9066 func_params.f_obj = &bp->func_obj;
9067 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 9068
619c5cb6
VZ		 9069 /*
9070 * Try to stop the function the 'good way'. If fails (in case
9071 * of a parity error during bnx2x_chip_cleanup()) and we are
9072 * not in a debug mode, perform a state transaction in order to
9073 * enable further HW_RESET transaction.
9074 */
9075 rc = bnx2x_func_state_change(bp, &func_params);
9076 if (rc) {
34f80b04 9077#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 9078 return rc;
34f80b04 9079#else
51c1a580 9080 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 9081 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9082 return bnx2x_func_state_change(bp, &func_params);
34f80b04 9083#endif
228241eb 9084 }
a2fbb9ea 9085
619c5cb6
VZ		 9086 return 0;
9087}
523224a3 9088
619c5cb6
VZ		 9089/**
9090 * bnx2x_send_unload_req - request unload mode from the MCP.
9091 *
9092 * @bp: driver handle
9093 * @unload_mode: requested function's unload mode
9094 *
9095 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9096 */
9097u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9098{
9099 u32 reset_code = 0;
9100 int port = BP_PORT(bp);
3101c2bc 9101
619c5cb6 9102 /* Select the UNLOAD request mode */
65abd74d
YG		 9103 if (unload_mode == UNLOAD_NORMAL)
9104 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9105
7d0446c2 9106 else if (bp->flags & NO_WOL_FLAG)
65abd74d 9107 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 9108
7d0446c2 9109 else if (bp->wol) {
65abd74d
YG		 9110 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9111 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 9112 struct pci_dev *pdev = bp->pdev;
65abd74d 9113 u32 val;
f9977903
DK		 9114 u16 pmc;
9115
65abd74d 9116 /* The mac address is written to entries 1-4 to
f9977903
DK		 9117 * preserve entry 0 which is used by the PMF
9118 */
3395a033 9119 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 9120
9121 val = (mac_addr[0] << 8) | mac_addr[1];
9122 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9123
9124 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9125 (mac_addr[4] << 8) | mac_addr[5];
9126 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9127
f9977903 9128 /* Enable the PME and clear the status */
29ed74c3 9129 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 9130 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 9131 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 9132
65abd74d
YG		 9133 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9134
9135 } else
9136 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 9137
619c5cb6
VZ		 9138 /* Send the request to the MCP */
9139 if (!BP_NOMCP(bp))
9140 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9141 else {
9142 int path = BP_PATH(bp);
9143
51c1a580 9144 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 9145 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9146 bnx2x_load_count[path][2]);
9147 bnx2x_load_count[path][0]--;
9148 bnx2x_load_count[path][1 + port]--;
51c1a580 9149 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 9150 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9151 bnx2x_load_count[path][2]);
9152 if (bnx2x_load_count[path][0] == 0)
619c5cb6 9153 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 9154 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 9155 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9156 else
9157 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9158 }
9159
9160 return reset_code;
9161}
9162
9163/**
9164 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9165 *
9166 * @bp: driver handle
5d07d868 9167 * @keep_link: true iff link should be kept up
619c5cb6 9168 */
5d07d868 9169void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 9170{
5d07d868
YM		 9171 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9172
619c5cb6
VZ		 9173 /* Report UNLOAD_DONE to MCP */
9174 if (!BP_NOMCP(bp))
5d07d868 9175 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 9176}
9177
1191cb83 9178static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 9179{
9180 int tout = 50;
9181 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9182
9183 if (!bp->port.pmf)
9184 return 0;
9185
9186 /*
9187 * (assumption: No Attention from MCP at this stage)
16a5fd92 9188 * PMF probably in the middle of TX disable/enable transaction
6debea87 9189 * 1. Sync IRS for default SB
16a5fd92
YM		 9190 * 2. Sync SP queue - this guarantees us that attention handling started
9191 * 3. Wait, that TX disable/enable transaction completes
6debea87 9192 *
16a5fd92
YM		 9193 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9194 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9195 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 9196 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9197 * transaction.
9198 */
9199
9200 /* make sure default SB ISR is done */
9201 if (msix)
9202 synchronize_irq(bp->msix_table[0].vector);
9203 else
9204 synchronize_irq(bp->pdev->irq);
9205
9206 flush_workqueue(bnx2x_wq);
370d4a26 9207 flush_workqueue(bnx2x_iov_wq);
6debea87
DK		 9208
9209 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9210 BNX2X_F_STATE_STARTED && tout--)
9211 msleep(20);
9212
9213 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9214 BNX2X_F_STATE_STARTED) {
9215#ifdef BNX2X_STOP_ON_ERROR
51c1a580 9216 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 9217 return -EBUSY;
9218#else
9219 /*
9220 * Failed to complete the transaction in a "good way"
9221 * Force both transactions with CLR bit
9222 */
3b603066 9223 struct bnx2x_func_state_params func_params = {NULL};
6debea87 9224
51c1a580 9225 DP(NETIF_MSG_IFDOWN,
0c23ad37 9226 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
6debea87
DK		 9227
9228 func_params.f_obj = &bp->func_obj;
9229 __set_bit(RAMROD_DRV_CLR_ONLY,
9230 &func_params.ramrod_flags);
9231
9232 /* STARTED-->TX_ST0PPED */
9233 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9234 bnx2x_func_state_change(bp, &func_params);
9235
9236 /* TX_ST0PPED-->STARTED */
9237 func_params.cmd = BNX2X_F_CMD_TX_START;
9238 return bnx2x_func_state_change(bp, &func_params);
9239#endif
9240 }
9241
9242 return 0;
9243}
9244
eeed018c
MK		 9245static void bnx2x_disable_ptp(struct bnx2x *bp)
9246{
9247 int port = BP_PORT(bp);
9248
9249 /* Disable sending PTP packets to host */
9250 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9251 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9252
9253 /* Reset PTP event detection rules */
9254 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9255 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9256 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9257 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9258 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9259 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9260 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9261 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9262
9263 /* Disable the PTP feature */
9264 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9265 NIG_REG_P0_PTP_EN, 0x0);
9266}
9267
9268/* Called during unload, to stop PTP-related stuff */
1444c301 9269static void bnx2x_stop_ptp(struct bnx2x *bp)
eeed018c
MK		 9270{
9271 /* Cancel PTP work queue. Should be done after the Tx queues are
9272 * drained to prevent additional scheduling.
9273 */
9274 cancel_work_sync(&bp->ptp_task);
9275
9276 if (bp->ptp_tx_skb) {
9277 dev_kfree_skb_any(bp->ptp_tx_skb);
9278 bp->ptp_tx_skb = NULL;
9279 }
9280
9281 /* Disable PTP in HW */
9282 bnx2x_disable_ptp(bp);
9283
9284 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9285}
9286
5d07d868 9287void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 9288{
9289 int port = BP_PORT(bp);
6383c0b3
AE		 9290 int i, rc = 0;
9291 u8 cos;
3b603066 9292 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 9293 u32 reset_code;
9294
9295 /* Wait until tx fastpath tasks complete */
9296 for_each_tx_queue(bp, i) {
9297 struct bnx2x_fastpath *fp = &bp->fp[i];
9298
6383c0b3 9299 for_each_cos_in_tx_queue(fp, cos)
65565884 9300 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 9301#ifdef BNX2X_STOP_ON_ERROR
9302 if (rc)
9303 return;
9304#endif
9305 }
9306
9307 /* Give HW time to discard old tx messages */
0926d499 9308 usleep_range(1000, 2000);
619c5cb6
VZ		 9309
9310 /* Clean all ETH MACs */
15192a8c
BW		 9311 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9312 false);
619c5cb6
VZ		 9313 if (rc < 0)
9314 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9315
9316 /* Clean up UC list */
15192a8c 9317 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 9318 true);
9319 if (rc < 0)
51c1a580
MS		 9320 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9321 rc);
619c5cb6
VZ		 9322
9323 /* Disable LLH */
9324 if (!CHIP_IS_E1(bp))
9325 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9326
9327 /* Set "drop all" (stop Rx).
9328 * We need to take a netif_addr_lock() here in order to prevent
9329 * a race between the completion code and this code.
9330 */
9331 netif_addr_lock_bh(bp->dev);
9332 /* Schedule the rx_mode command */
9333 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9334 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9335 else
9336 bnx2x_set_storm_rx_mode(bp);
9337
9338 /* Cleanup multicast configuration */
9339 rparam.mcast_obj = &bp->mcast_obj;
9340 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9341 if (rc < 0)
9342 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9343
9344 netif_addr_unlock_bh(bp->dev);
9345
f1929b01 9346 bnx2x_iov_chip_cleanup(bp);
619c5cb6 9347
6debea87
DK		 9348 /*
9349 * Send the UNLOAD_REQUEST to the MCP. This will return if
9350 * this function should perform FUNC, PORT or COMMON HW
9351 * reset.
9352 */
9353 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9354
9355 /*
9356 * (assumption: No Attention from MCP at this stage)
16a5fd92 9357 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 9358 */
9359 rc = bnx2x_func_wait_started(bp);
9360 if (rc) {
9361 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9362#ifdef BNX2X_STOP_ON_ERROR
9363 return;
9364#endif
9365 }
9366
34f80b04 9367 /* Close multi and leading connections
619c5cb6
VZ		 9368 * Completions for ramrods are collected in a synchronous way
9369 */
55c11941 9370 for_each_eth_queue(bp, i)
619c5cb6 9371 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 9372#ifdef BNX2X_STOP_ON_ERROR
9373 return;
9374#else
228241eb 9375 goto unload_error;
523224a3 9376#endif
55c11941
MS		 9377
9378 if (CNIC_LOADED(bp)) {
9379 for_each_cnic_queue(bp, i)
9380 if (bnx2x_stop_queue(bp, i))
9381#ifdef BNX2X_STOP_ON_ERROR
9382 return;
9383#else
9384 goto unload_error;
9385#endif
9386 }
9387
619c5cb6
VZ		 9388 /* If SP settings didn't get completed so far - something
9389 * very wrong has happen.
9390 */
9391 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9392 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9393
619c5cb6
VZ		 9394#ifndef BNX2X_STOP_ON_ERROR
9395unload_error:
9396#endif
523224a3 9397 rc = bnx2x_func_stop(bp);
da5a662a 9398 if (rc) {
523224a3 9399 BNX2X_ERR("Function stop failed!\n");
da5a662a 9400#ifdef BNX2X_STOP_ON_ERROR
523224a3 9401 return;
523224a3 9402#endif
34f80b04 9403 }
a2fbb9ea 9404
eeed018c
MK		 9405 /* stop_ptp should be after the Tx queues are drained to prevent
9406 * scheduling to the cancelled PTP work queue. It should also be after
9407 * function stop ramrod is sent, since as part of this ramrod FW access
9408 * PTP registers.
9409 */
d53c66a5
ED		 9410 if (bp->flags & PTP_SUPPORTED)
9411 bnx2x_stop_ptp(bp);
eeed018c 9412
523224a3
DK		 9413 /* Disable HW interrupts, NAPI */
9414 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9415 /* Delete all NAPI objects */
9416 bnx2x_del_all_napi(bp);
55c11941
MS		 9417 if (CNIC_LOADED(bp))
9418 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9419
9420 /* Release IRQs */
d6214d7a 9421 bnx2x_free_irq(bp);
523224a3 9422
b44e108b
GP		 9423 /* Reset the chip, unless PCI function is offline. If we reach this
9424 * point following a PCI error handling, it means device is really
9425 * in a bad state and we're about to remove it, so reset the chip
9426 * is not a good idea.
9427 */
9428 if (!pci_channel_offline(bp->pdev)) {
9429 rc = bnx2x_reset_hw(bp, reset_code);
9430 if (rc)
9431 BNX2X_ERR("HW_RESET failed\n");
9432 }
a2fbb9ea 9433
619c5cb6 9434 /* Report UNLOAD_DONE to MCP */
5d07d868 9435 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9436}
9437
9f6c9258 9438void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9439{
9440 u32 val;
9441
51c1a580 9442 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9443
9444 if (CHIP_IS_E1(bp)) {
9445 int port = BP_PORT(bp);
9446 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9447 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9448
9449 val = REG_RD(bp, addr);
9450 val &= ~(0x300);
9451 REG_WR(bp, addr, val);
619c5cb6 9452 } else {
72fd0718
VZ		 9453 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9454 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9455 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9456 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9457 }
9458}
9459
72fd0718
VZ		 9460/* Close gates #2, #3 and #4: */
9461static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9462{
c9ee9206 9463 u32 val;
72fd0718
VZ		 9464
9465 /* Gates #2 and #4a are closed/opened for "not E1" only */
9466 if (!CHIP_IS_E1(bp)) {
9467 /* #4 */
c9ee9206 9468 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9469 /* #2 */
c9ee9206 9470 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9471 }
9472
9473 /* #3 */
c9ee9206
VZ		 9474 if (CHIP_IS_E1x(bp)) {
9475 /* Prevent interrupts from HC on both ports */
9476 val = REG_RD(bp, HC_REG_CONFIG_1);
9477 REG_WR(bp, HC_REG_CONFIG_1,
9478 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9479 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9480
9481 val = REG_RD(bp, HC_REG_CONFIG_0);
9482 REG_WR(bp, HC_REG_CONFIG_0,
9483 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9484 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9485 } else {
d82603c6 9486 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9487 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9488
9489 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9490 (!close) ?
9491 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9492 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9493 }
72fd0718 9494
51c1a580 9495 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9496 close ? "closing" : "opening");
9497 mmiowb();
9498}
9499
9500#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9501
9502static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9503{
9504 /* Do some magic... */
9505 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9506 *magic_val = val & SHARED_MF_CLP_MAGIC;
9507 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9508}
9509
e8920674
DK		 9510/**
9511 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9512 *
e8920674
DK		 9513 * @bp: driver handle
9514 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9515 */
9516static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9517{
9518 /* Restore the `magic' bit value... */
72fd0718
VZ		 9519 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9520 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9521 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9522}
9523
f85582f8 9524/**
e8920674 9525 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9526 *
e8920674
DK		 9527 * @bp: driver handle
9528 * @magic_val: old value of 'magic' bit.
9529 *
9530 * Takes care of CLP configurations.
72fd0718
VZ		 9531 */
9532static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9533{
9534 u32 shmem;
9535 u32 validity_offset;
9536
51c1a580 9537 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9538
9539 /* Set `magic' bit in order to save MF config */
9540 if (!CHIP_IS_E1(bp))
9541 bnx2x_clp_reset_prep(bp, magic_val);
9542
9543 /* Get shmem offset */
9544 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9545 validity_offset =
9546 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9547
9548 /* Clear validity map flags */
9549 if (shmem > 0)
9550 REG_WR(bp, shmem + validity_offset, 0);
9551}
9552
9553#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9554#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9555
e8920674
DK		 9556/**
9557 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9558 *
e8920674 9559 * @bp: driver handle
72fd0718 9560 */
1191cb83 9561static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9562{
9563 /* special handling for emulation and FPGA,
9564 wait 10 times longer */
9565 if (CHIP_REV_IS_SLOW(bp))
9566 msleep(MCP_ONE_TIMEOUT*10);
9567 else
9568 msleep(MCP_ONE_TIMEOUT);
9569}
9570
1b6e2ceb
DK		 9571/*
9572 * initializes bp->common.shmem_base and waits for validity signature to appear
9573 */
9574static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9575{
1b6e2ceb
DK		 9576 int cnt = 0;
9577 u32 val = 0;
72fd0718 9578
1b6e2ceb
DK		 9579 do {
9580 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9581 if (bp->common.shmem_base) {
9582 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9583 if (val & SHR_MEM_VALIDITY_MB)
9584 return 0;
9585 }
72fd0718 9586
1b6e2ceb 9587 bnx2x_mcp_wait_one(bp);
72fd0718 9588
1b6e2ceb 9589 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9590
1b6e2ceb 9591 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9592
1b6e2ceb
DK		 9593 return -ENODEV;
9594}
72fd0718 9595
1b6e2ceb
DK		 9596static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9597{
9598 int rc = bnx2x_init_shmem(bp);
72fd0718 9599
72fd0718
VZ		 9600 /* Restore the `magic' bit value */
9601 if (!CHIP_IS_E1(bp))
9602 bnx2x_clp_reset_done(bp, magic_val);
9603
9604 return rc;
9605}
9606
9607static void bnx2x_pxp_prep(struct bnx2x *bp)
9608{
9609 if (!CHIP_IS_E1(bp)) {
9610 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9611 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9612 mmiowb();
9613 }
9614}
9615
9616/*
9617 * Reset the whole chip except for:
9618 * - PCIE core
9619 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9620 * one reset bit)
9621 * - IGU
9622 * - MISC (including AEU)
9623 * - GRC
9624 * - RBCN, RBCP
9625 */
c9ee9206 9626static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9627{
9628 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9629 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9630
9631 /*
9632 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9633 * (per chip) blocks.
9634 */
9635 global_bits2 =
9636 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9637 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9638
c55e771b
BW		 9639 /* Don't reset the following blocks.
9640 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9641 * reset, as in 4 port device they might still be owned
9642 * by the MCP (there is only one leader per path).
9643 */
72fd0718
VZ		 9644 not_reset_mask1 =
9645 MISC_REGISTERS_RESET_REG_1_RST_HC |
9646 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9647 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9648
9649 not_reset_mask2 =
c9ee9206 9650 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9651 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9652 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9653 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9654 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9655 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9656 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9657 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9658 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9659 MISC_REGISTERS_RESET_REG_2_PGLC |
9660 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9661 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9662 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9663 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9664 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9665 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9666
8736c826
VZ		 9667 /*
9668 * Keep the following blocks in reset:
9669 * - all xxMACs are handled by the bnx2x_link code.
9670 */
9671 stay_reset2 =
8736c826
VZ		 9672 MISC_REGISTERS_RESET_REG_2_XMAC |
9673 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9674
9675 /* Full reset masks according to the chip */
72fd0718
VZ		 9676 reset_mask1 = 0xffffffff;
9677
9678 if (CHIP_IS_E1(bp))
9679 reset_mask2 = 0xffff;
8736c826 9680 else if (CHIP_IS_E1H(bp))
72fd0718 9681 reset_mask2 = 0x1ffff;
8736c826
VZ		 9682 else if (CHIP_IS_E2(bp))
9683 reset_mask2 = 0xfffff;
9684 else /* CHIP_IS_E3 */
9685 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9686
9687 /* Don't reset global blocks unless we need to */
9688 if (!global)
9689 reset_mask2 &= ~global_bits2;
9690
9691 /*
9692 * In case of attention in the QM, we need to reset PXP
9693 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9694 * because otherwise QM reset would release 'close the gates' shortly
9695 * before resetting the PXP, then the PSWRQ would send a write
9696 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9697 * read the payload data from PSWWR, but PSWWR would not
9698 * respond. The write queue in PGLUE would stuck, dmae commands
9699 * would not return. Therefore it's important to reset the second
9700 * reset register (containing the
9701 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9702 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9703 * bit).
9704 */
72fd0718
VZ		 9705 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9706 reset_mask2 & (~not_reset_mask2));
9707
c9ee9206
VZ		 9708 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9709 reset_mask1 & (~not_reset_mask1));
9710
72fd0718
VZ		 9711 barrier();
9712 mmiowb();
9713
8736c826
VZ		 9714 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9715 reset_mask2 & (~stay_reset2));
9716
9717 barrier();
9718 mmiowb();
9719
c9ee9206 9720 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9721 mmiowb();
9722}
9723
c9ee9206
VZ		 9724/**
9725 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9726 * It should get cleared in no more than 1s.
9727 *
9728 * @bp: driver handle
9729 *
9730 * It should get cleared in no more than 1s. Returns 0 if
9731 * pending writes bit gets cleared.
9732 */
9733static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9734{
9735 u32 cnt = 1000;
9736 u32 pend_bits = 0;
9737
9738 do {
9739 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9740
9741 if (pend_bits == 0)
9742 break;
9743
0926d499 9744 usleep_range(1000, 2000);
c9ee9206
VZ		 9745 } while (cnt-- > 0);
9746
9747 if (cnt <= 0) {
9748 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9749 pend_bits);
9750 return -EBUSY;
9751 }
9752
9753 return 0;
9754}
9755
9756static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9757{
9758 int cnt = 1000;
9759 u32 val = 0;
9760 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9761 u32 tags_63_32 = 0;
72fd0718
VZ		 9762
9763 /* Empty the Tetris buffer, wait for 1s */
9764 do {
9765 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9766 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9767 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9768 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9769 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9770 if (CHIP_IS_E3(bp))
9771 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9772
72fd0718
VZ		 9773 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9774 ((port_is_idle_0 & 0x1) == 0x1) &&
9775 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9776 (pgl_exp_rom2 == 0xffffffff) &&
9777 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9778 break;
0926d499 9779 usleep_range(1000, 2000);
72fd0718
VZ		 9780 } while (cnt-- > 0);
9781
9782 if (cnt <= 0) {
51c1a580
MS		 9783 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9784 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9785 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9786 pgl_exp_rom2);
9787 return -EAGAIN;
9788 }
9789
9790 barrier();
9791
9792 /* Close gates #2, #3 and #4 */
9793 bnx2x_set_234_gates(bp, true);
9794
c9ee9206
VZ		 9795 /* Poll for IGU VQs for 57712 and newer chips */
9796 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9797 return -EAGAIN;
9798
72fd0718
VZ		 9799 /* TBD: Indicate that "process kill" is in progress to MCP */
9800
9801 /* Clear "unprepared" bit */
9802 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9803 barrier();
9804
9805 /* Make sure all is written to the chip before the reset */
9806 mmiowb();
9807
9808 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9809 * PSWHST, GRC and PSWRD Tetris buffer.
9810 */
0926d499 9811 usleep_range(1000, 2000);
72fd0718
VZ		 9812
9813 /* Prepare to chip reset: */
9814 /* MCP */
c9ee9206
VZ		 9815 if (global)
9816 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9817
9818 /* PXP */
9819 bnx2x_pxp_prep(bp);
9820 barrier();
9821
9822 /* reset the chip */
c9ee9206 9823 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9824 barrier();
9825
9dcd9acd
DK		 9826 /* clear errors in PGB */
9827 if (!CHIP_IS_E1x(bp))
9828 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9829
72fd0718
VZ		 9830 /* Recover after reset: */
9831 /* MCP */
c9ee9206 9832 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9833 return -EAGAIN;
9834
c9ee9206
VZ		 9835 /* TBD: Add resetting the NO_MCP mode DB here */
9836
72fd0718
VZ		 9837 /* Open the gates #2, #3 and #4 */
9838 bnx2x_set_234_gates(bp, false);
9839
9840 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9841 * reset state, re-enable attentions. */
9842
a2fbb9ea
ET		 9843 return 0;
9844}
9845
910cc727 9846static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9847{
9848 int rc = 0;
c9ee9206 9849 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9850 u32 load_code;
9851
9852 /* if not going to reset MCP - load "fake" driver to reset HW while
9853 * driver is owner of the HW
9854 */
9855 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9856 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9857 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9858 if (!load_code) {
9859 BNX2X_ERR("MCP response failure, aborting\n");
9860 rc = -EAGAIN;
9861 goto exit_leader_reset;
9862 }
9863 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9864 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9865 BNX2X_ERR("MCP unexpected resp, aborting\n");
9866 rc = -EAGAIN;
9867 goto exit_leader_reset2;
9868 }
9869 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9870 if (!load_code) {
9871 BNX2X_ERR("MCP response failure, aborting\n");
9872 rc = -EAGAIN;
9873 goto exit_leader_reset2;
9874 }
9875 }
c9ee9206 9876
72fd0718 9877 /* Try to recover after the failure */
c9ee9206 9878 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9879 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9880 BP_PATH(bp));
72fd0718 9881 rc = -EAGAIN;
95c6c616 9882 goto exit_leader_reset2;
72fd0718
VZ		 9883 }
9884
c9ee9206
VZ		 9885 /*
9886 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9887 * state.
9888 */
72fd0718 9889 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9890 if (global)
9891 bnx2x_clear_reset_global(bp);
72fd0718 9892
95c6c616
AE		 9893exit_leader_reset2:
9894 /* unload "fake driver" if it was loaded */
9895 if (!global && !BP_NOMCP(bp)) {
9896 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9897 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9898 }
72fd0718
VZ		 9899exit_leader_reset:
9900 bp->is_leader = 0;
c9ee9206
VZ		 9901 bnx2x_release_leader_lock(bp);
9902 smp_mb();
72fd0718
VZ		 9903 return rc;
9904}
9905
1191cb83 9906static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9907{
9908 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9909
9910 /* Disconnect this device */
9911 netif_device_detach(bp->dev);
9912
9913 /*
9914 * Block ifup for all function on this engine until "process kill"
9915 * or power cycle.
9916 */
9917 bnx2x_set_reset_in_progress(bp);
9918
9919 /* Shut down the power */
9920 bnx2x_set_power_state(bp, PCI_D3hot);
9921
9922 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9923
9924 smp_mb();
9925}
9926
9927/*
9928 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9929 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9930 * will never be called when netif_running(bp->dev) is false.
9931 */
9932static void bnx2x_parity_recover(struct bnx2x *bp)
9933{
c9ee9206 9934 bool global = false;
7a752993 9935 u32 error_recovered, error_unrecovered;
95c6c616 9936 bool is_parity;
c9ee9206 9937
72fd0718
VZ		 9938 DP(NETIF_MSG_HW, "Handling parity\n");
9939 while (1) {
9940 switch (bp->recovery_state) {
9941 case BNX2X_RECOVERY_INIT:
9942 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9943 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9944 WARN_ON(!is_parity);
c9ee9206 9945
72fd0718 9946 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9947 if (bnx2x_trylock_leader_lock(bp)) {
9948 bnx2x_set_reset_in_progress(bp);
9949 /*
9950 * Check if there is a global attention and if
9951 * there was a global attention, set the global
9952 * reset bit.
9953 */
9954
9955 if (global)
9956 bnx2x_set_reset_global(bp);
9957
72fd0718 9958 bp->is_leader = 1;
c9ee9206 9959 }
72fd0718
VZ		 9960
9961 /* Stop the driver */
9962 /* If interface has been removed - break */
5d07d868 9963 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9964 return;
9965
9966 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9967
c9ee9206
VZ		 9968 /* Ensure "is_leader", MCP command sequence and
9969 * "recovery_state" update values are seen on other
9970 * CPUs.
72fd0718 9971 */
c9ee9206 9972 smp_mb();
72fd0718
VZ		 9973 break;
9974
9975 case BNX2X_RECOVERY_WAIT:
9976 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9977 if (bp->is_leader) {
c9ee9206 9978 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9979 bool other_load_status =
9980 bnx2x_get_load_status(bp, other_engine);
9981 bool load_status =
9982 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9983 global = bnx2x_reset_is_global(bp);
9984
9985 /*
9986 * In case of a parity in a global block, let
9987 * the first leader that performs a
9988 * leader_reset() reset the global blocks in
9989 * order to clear global attentions. Otherwise
16a5fd92 9990 * the gates will remain closed for that
c9ee9206
VZ		 9991 * engine.
9992 */
889b9af3
AE		 9993 if (load_status ||
9994 (global && other_load_status)) {
72fd0718
VZ		 9995 /* Wait until all other functions get
9996 * down.
9997 */
7be08a72 9998 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9999 HZ/10);
10000 return;
10001 } else {
10002 /* If all other functions got down -
10003 * try to bring the chip back to
10004 * normal. In any case it's an exit
10005 * point for a leader.
10006 */
c9ee9206
VZ		 10007 if (bnx2x_leader_reset(bp)) {
10008 bnx2x_recovery_failed(bp);
72fd0718
VZ		 10009 return;
10010 }
10011
c9ee9206
VZ		 10012 /* If we are here, means that the
10013 * leader has succeeded and doesn't
10014 * want to be a leader any more. Try
10015 * to continue as a none-leader.
10016 */
10017 break;
72fd0718
VZ		 10018 }
10019 } else { /* non-leader */
c9ee9206 10020 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 10021 /* Try to get a LEADER_LOCK HW lock as
10022 * long as a former leader may have
10023 * been unloaded by the user or
10024 * released a leadership by another
10025 * reason.
10026 */
c9ee9206 10027 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 10028 /* I'm a leader now! Restart a
10029 * switch case.
10030 */
10031 bp->is_leader = 1;
10032 break;
10033 }
10034
7be08a72 10035 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 10036 HZ/10);
10037 return;
10038
c9ee9206
VZ		 10039 } else {
10040 /*
10041 * If there was a global attention, wait
10042 * for it to be cleared.
10043 */
10044 if (bnx2x_reset_is_global(bp)) {
10045 schedule_delayed_work(
7be08a72
AE		 10046 &bp->sp_rtnl_task,
10047 HZ/10);
c9ee9206
VZ		 10048 return;
10049 }
10050
7a752993
AE		 10051 error_recovered =
10052 bp->eth_stats.recoverable_error;
10053 error_unrecovered =
10054 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 10055 bp->recovery_state =
10056 BNX2X_RECOVERY_NIC_LOADING;
10057 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 10058 error_unrecovered++;
95c6c616 10059 netdev_err(bp->dev,
51c1a580 10060 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 10061 /* Disconnect this device */
10062 netif_device_detach(bp->dev);
10063 /* Shut down the power */
10064 bnx2x_set_power_state(
10065 bp, PCI_D3hot);
10066 smp_mb();
10067 } else {
c9ee9206
VZ		 10068 bp->recovery_state =
10069 BNX2X_RECOVERY_DONE;
7a752993 10070 error_recovered++;
c9ee9206
VZ		 10071 smp_mb();
10072 }
7a752993
AE		 10073 bp->eth_stats.recoverable_error =
10074 error_recovered;
10075 bp->eth_stats.unrecoverable_error =
10076 error_unrecovered;
c9ee9206 10077
72fd0718
VZ		 10078 return;
10079 }
10080 }
10081 default:
10082 return;
10083 }
10084 }
10085}
10086
883ce97d 10087static int bnx2x_udp_port_update(struct bnx2x *bp)
f34fa14c
RB		 10088{
10089 struct bnx2x_func_switch_update_params *switch_update_params;
10090 struct bnx2x_func_state_params func_params = {NULL};
883ce97d
YM		 10091 struct bnx2x_udp_tunnel *udp_tunnel;
10092 u16 vxlan_port = 0, geneve_port = 0;
f34fa14c
RB		 10093 int rc;
10094
10095 switch_update_params = &func_params.params.switch_update;
10096
10097 /* Prepare parameters for function state transitions */
10098 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10099 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10100
10101 func_params.f_obj = &bp->func_obj;
10102 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10103
10104 /* Function parameters */
10105 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10106 &switch_update_params->changes);
883ce97d
YM		 10107
10108 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
10109 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
10110 geneve_port = udp_tunnel->dst_port;
10111 switch_update_params->geneve_dst_port = geneve_port;
10112 }
10113
10114 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
10115 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
10116 vxlan_port = udp_tunnel->dst_port;
10117 switch_update_params->vxlan_dst_port = vxlan_port;
10118 }
10119
10120 /* Re-enable inner-rss for the offloaded UDP tunnels */
10121 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
10122 &switch_update_params->changes);
10123
f34fa14c
RB		 10124 rc = bnx2x_func_state_change(bp, &func_params);
10125 if (rc)
883ce97d
YM		 10126 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10127 vxlan_port, geneve_port, rc);
10128 else
10129 DP(BNX2X_MSG_SP,
10130 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10131 vxlan_port, geneve_port);
10132
f34fa14c
RB		 10133 return rc;
10134}
10135
883ce97d
YM		 10136static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port,
10137 enum bnx2x_udp_port_type type)
f34fa14c 10138{
883ce97d
YM		 10139 struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10140
10141 if (!netif_running(bp->dev) || !IS_PF(bp))
10142 return;
10143
10144 if (udp_port->count && udp_port->dst_port == port) {
10145 udp_port->count++;
f34fa14c 10146 return;
883ce97d 10147 }
f34fa14c 10148
883ce97d
YM		 10149 if (udp_port->count) {
10150 DP(BNX2X_MSG_SP,
10151 "UDP tunnel [%d] - destination port limit reached\n",
10152 type);
ac7eccd4
JB		 10153 return;
10154 }
10155
883ce97d
YM		 10156 udp_port->dst_port = port;
10157 udp_port->count = 1;
10158 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10159}
10160
10161static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port,
10162 enum bnx2x_udp_port_type type)
10163{
10164 struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10165
10166 if (!IS_PF(bp))
10167 return;
10168
10169 if (!udp_port->count || udp_port->dst_port != port) {
10170 DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n",
10171 type);
f34fa14c
RB		 10172 return;
10173 }
10174
883ce97d
YM		 10175 /* Remove reference, and make certain it's no longer in use */
10176 udp_port->count--;
10177 if (udp_port->count)
10178 return;
10179 udp_port->dst_port = 0;
10180
10181 if (netif_running(bp->dev))
10182 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10183 else
10184 DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n",
10185 type, port);
f34fa14c 10186}
883ce97d 10187
6b352912
AD		 10188static void bnx2x_udp_tunnel_add(struct net_device *netdev,
10189 struct udp_tunnel_info *ti)
883ce97d
YM		 10190{
10191 struct bnx2x *bp = netdev_priv(netdev);
6b352912 10192 u16 t_port = ntohs(ti->port);
883ce97d 10193
6b352912
AD		 10194 switch (ti->type) {
10195 case UDP_TUNNEL_TYPE_VXLAN:
10196 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10197 break;
10198 case UDP_TUNNEL_TYPE_GENEVE:
10199 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10200 break;
10201 default:
10202 break;
10203 }
f34fa14c
RB		 10204}
10205
6b352912
AD		 10206static void bnx2x_udp_tunnel_del(struct net_device *netdev,
10207 struct udp_tunnel_info *ti)
f34fa14c
RB		 10208{
10209 struct bnx2x *bp = netdev_priv(netdev);
6b352912 10210 u16 t_port = ntohs(ti->port);
f34fa14c 10211
6b352912
AD		 10212 switch (ti->type) {
10213 case UDP_TUNNEL_TYPE_VXLAN:
10214 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10215 break;
10216 case UDP_TUNNEL_TYPE_GENEVE:
10217 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10218 break;
10219 default:
10220 break;
10221 }
f34fa14c 10222}
f34fa14c 10223
56ad3152
MS		 10224static int bnx2x_close(struct net_device *dev);
10225
72fd0718
VZ		 10226/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10227 * scheduled on a general queue in order to prevent a dead lock.
10228 */
7be08a72 10229static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 10230{
7be08a72 10231 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 10232
10233 rtnl_lock();
10234
8395be5e
AE		 10235 if (!netif_running(bp->dev)) {
10236 rtnl_unlock();
10237 return;
10238 }
7be08a72 10239
6bf07b8e 10240 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 10241#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 10242 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10243 "you will need to reboot when done\n");
10244 goto sp_rtnl_not_reset;
7be08a72 10245#endif
7be08a72 10246 /*
b1fb8740
VZ		 10247 * Clear all pending SP commands as we are going to reset the
10248 * function anyway.
7be08a72 10249 */
b1fb8740
VZ		 10250 bp->sp_rtnl_state = 0;
10251 smp_mb();
10252
72fd0718 10253 bnx2x_parity_recover(bp);
b1fb8740 10254
8395be5e
AE		 10255 rtnl_unlock();
10256 return;
b1fb8740
VZ		 10257 }
10258
10259 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 10260#ifdef BNX2X_STOP_ON_ERROR
10261 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10262 "you will need to reboot when done\n");
10263 goto sp_rtnl_not_reset;
10264#endif
10265
b1fb8740
VZ		 10266 /*
10267 * Clear all pending SP commands as we are going to reset the
10268 * function anyway.
10269 */
10270 bp->sp_rtnl_state = 0;
10271 smp_mb();
10272
5d07d868 10273 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 10274 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740 10275
8395be5e
AE		 10276 rtnl_unlock();
10277 return;
72fd0718 10278 }
b1fb8740
VZ		 10279#ifdef BNX2X_STOP_ON_ERROR
10280sp_rtnl_not_reset:
10281#endif
10282 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10283 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 10284 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10285 bnx2x_after_function_update(bp);
8304859a
AE		 10286 /*
10287 * in case of fan failure we need to reset id if the "stop on error"
10288 * debug flag is set, since we trying to prevent permanent overheating
10289 * damage
10290 */
10291 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 10292 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 10293 netif_device_detach(bp->dev);
10294 bnx2x_close(bp->dev);
8395be5e
AE		 10295 rtnl_unlock();
10296 return;
8304859a
AE		 10297 }
10298
381ac16b
AE		 10299 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10300 DP(BNX2X_MSG_SP,
10301 "sending set mcast vf pf channel message from rtnl sp-task\n");
10302 bnx2x_vfpf_set_mcast(bp->dev);
10303 }
78c3bcc5
AE		 10304 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10305 &bp->sp_rtnl_state)){
10306 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10307 bnx2x_tx_disable(bp);
10308 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10309 }
10310 }
381ac16b 10311
8b09be5f
YM		 10312 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10313 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10314 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 10315 }
10316
3ec9f9ca
AE		 10317 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10318 &bp->sp_rtnl_state))
10319 bnx2x_pf_set_vfs_vlan(bp);
10320
6ffa39f2 10321 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 10322 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 10323 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 10324 }
07b4eb3b 10325
42f8277f
YM		 10326 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10327 &bp->sp_rtnl_state))
10328 bnx2x_update_mng_version(bp);
10329
883ce97d 10330 if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT,
f34fa14c 10331 &bp->sp_rtnl_state)) {
883ce97d
YM		 10332 if (bnx2x_udp_port_update(bp)) {
10333 /* On error, forget configuration */
10334 memset(bp->udp_tunnel_ports, 0,
10335 sizeof(struct bnx2x_udp_tunnel) *
10336 BNX2X_UDP_PORT_MAX);
10337 } else {
10338 /* Since we don't store additional port information,
6b352912 10339 * if no ports are configured for any feature ask for
883ce97d
YM		 10340 * information about currently configured ports.
10341 */
6b352912
AD		 10342 if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count &&
10343 !bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count)
10344 udp_tunnel_get_rx_info(bp->dev);
f34fa14c
RB		 10345 }
10346 }
f34fa14c 10347
8395be5e
AE		 10348 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10349 * can be called from other contexts as well)
10350 */
34f80b04 10351 rtnl_unlock();
8395be5e 10352
6411280a 10353 /* enable SR-IOV if applicable */
8395be5e 10354 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 10355 &bp->sp_rtnl_state)) {
10356 bnx2x_disable_sriov(bp);
6411280a 10357 bnx2x_enable_sriov(bp);
3c76feff 10358 }
34f80b04
EG		 10359}
10360
3deb8167
YR		 10361static void bnx2x_period_task(struct work_struct *work)
10362{
10363 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10364
10365 if (!netif_running(bp->dev))
10366 goto period_task_exit;
10367
10368 if (CHIP_REV_IS_SLOW(bp)) {
10369 BNX2X_ERR("period task called on emulation, ignoring\n");
10370 goto period_task_exit;
10371 }
10372
10373 bnx2x_acquire_phy_lock(bp);
10374 /*
10375 * The barrier is needed to ensure the ordering between the writing to
10376 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10377 * the reading here.
10378 */
10379 smp_mb();
10380 if (bp->port.pmf) {
10381 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10382
10383 /* Re-queue task in 1 sec */
10384 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10385 }
10386
10387 bnx2x_release_phy_lock(bp);
10388period_task_exit:
10389 return;
10390}
10391
a2fbb9ea
ET		 10392/*
10393 * Init service functions
10394 */
10395
a8f47eb7 10396static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 10397{
10398 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10399 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10400 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 10401}
10402
3d6b7253
YM		 10403static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10404 u8 port, u32 reset_reg,
10405 struct bnx2x_mac_vals *vals)
10406{
10407 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10408 u32 base_addr;
10409
10410 if (!(mask & reset_reg))
10411 return false;
10412
10413 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10414 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10415 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10416 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10417 REG_WR(bp, vals->umac_addr[port], 0);
10418
10419 return true;
10420}
10421
1ef1d45a
BW		 10422static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10423 struct bnx2x_mac_vals *vals)
34f80b04 10424{
452427b0
YM		 10425 u32 val, base_addr, offset, mask, reset_reg;
10426 bool mac_stopped = false;
10427 u8 port = BP_PORT(bp);
34f80b04 10428
1ef1d45a 10429 /* reset addresses as they also mark which values were changed */
3d6b7253 10430 memset(vals, 0, sizeof(*vals));
1ef1d45a 10431
452427b0 10432 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 10433
452427b0
YM		 10434 if (!CHIP_IS_E3(bp)) {
10435 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10436 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10437 if ((mask & reset_reg) && val) {
10438 u32 wb_data[2];
10439 BNX2X_DEV_INFO("Disable bmac Rx\n");
10440 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10441 : NIG_REG_INGRESS_BMAC0_MEM;
10442 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10443 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 10444
452427b0
YM		 10445 /*
10446 * use rd/wr since we cannot use dmae. This is safe
10447 * since MCP won't access the bus due to the request
10448 * to unload, and no function on the path can be
10449 * loaded at this time.
10450 */
10451 wb_data[0] = REG_RD(bp, base_addr + offset);
10452 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 10453 vals->bmac_addr = base_addr + offset;
10454 vals->bmac_val[0] = wb_data[0];
10455 vals->bmac_val[1] = wb_data[1];
452427b0 10456 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 10457 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10458 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 10459 }
10460 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 10461 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10462 vals->emac_val = REG_RD(bp, vals->emac_addr);
10463 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 10464 mac_stopped = true;
10465 } else {
10466 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10467 BNX2X_DEV_INFO("Disable xmac Rx\n");
10468 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10469 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10470 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10471 val & ~(1 << 1));
10472 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10473 val | (1 << 1));
1ef1d45a
BW		 10474 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10475 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10476 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 10477 mac_stopped = true;
10478 }
3d6b7253
YM		 10479
10480 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10481 reset_reg, vals);
10482 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10483 reset_reg, vals);
452427b0
YM		 10484 }
10485
10486 if (mac_stopped)
10487 msleep(20);
452427b0
YM		 10488}
10489
10490#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
7c3afd85
YM		 10491#define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10492 0x1848 + ((f) << 4))
452427b0
YM		 10493#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10494#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10495#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10496
91ebb929
YM		 10497#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10498#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10499#define BCM_5710_UNDI_FW_MF_VERS (0x05)
b17b0ca1
YM		 10500
10501static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10502{
10503 /* UNDI marks its presence in DORQ -
10504 * it initializes CID offset for normal bell to 0x7
10505 */
10506 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10507 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10508 return false;
10509
10510 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10511 BNX2X_DEV_INFO("UNDI previously loaded\n");
10512 return true;
10513 }
10514
10515 return false;
10516}
10517
7c3afd85 10518static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
452427b0
YM		 10519{
10520 u16 rcq, bd;
7c3afd85 10521 u32 addr, tmp_reg;
452427b0 10522
7c3afd85
YM		 10523 if (BP_FUNC(bp) < 2)
10524 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10525 else
10526 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10527
10528 tmp_reg = REG_RD(bp, addr);
452427b0
YM		 10529 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10530 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10531
10532 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
7c3afd85 10533 REG_WR(bp, addr, tmp_reg);
452427b0 10534
7c3afd85
YM		 10535 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10536 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
452427b0
YM		 10537}
10538
0329aba1 10539static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10540{
5d07d868
YM		 10541 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10542 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10543 if (!rc) {
10544 BNX2X_ERR("MCP response failure, aborting\n");
10545 return -EBUSY;
10546 }
10547
10548 return 0;
10549}
10550
c63da990
BW		 10551static struct bnx2x_prev_path_list *
10552 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10553{
10554 struct bnx2x_prev_path_list *tmp_list;
10555
10556 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10557 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10558 bp->pdev->bus->number == tmp_list->bus &&
10559 BP_PATH(bp) == tmp_list->path)
10560 return tmp_list;
10561
10562 return NULL;
10563}
10564
7fa6f340
YM		 10565static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10566{
10567 struct bnx2x_prev_path_list *tmp_list;
10568 int rc;
10569
10570 rc = down_interruptible(&bnx2x_prev_sem);
10571 if (rc) {
10572 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10573 return rc;
10574 }
10575
10576 tmp_list = bnx2x_prev_path_get_entry(bp);
10577 if (tmp_list) {
10578 tmp_list->aer = 1;
10579 rc = 0;
10580 } else {
10581 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10582 BP_PATH(bp));
10583 }
10584
10585 up(&bnx2x_prev_sem);
10586
10587 return rc;
10588}
10589
0329aba1 10590static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10591{
10592 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10593 bool rc = false;
452427b0
YM		 10594
10595 if (down_trylock(&bnx2x_prev_sem))
10596 return false;
10597
7fa6f340
YM		 10598 tmp_list = bnx2x_prev_path_get_entry(bp);
10599 if (tmp_list) {
10600 if (tmp_list->aer) {
10601 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10602 BP_PATH(bp));
10603 } else {
452427b0
YM		 10604 rc = true;
10605 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10606 BP_PATH(bp));
452427b0
YM		 10607 }
10608 }
10609
10610 up(&bnx2x_prev_sem);
10611
10612 return rc;
10613}
10614
178135c1
DK		 10615bool bnx2x_port_after_undi(struct bnx2x *bp)
10616{
10617 struct bnx2x_prev_path_list *entry;
10618 bool val;
10619
10620 down(&bnx2x_prev_sem);
10621
10622 entry = bnx2x_prev_path_get_entry(bp);
10623 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10624
10625 up(&bnx2x_prev_sem);
10626
10627 return val;
10628}
10629
c63da990 10630static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10631{
10632 struct bnx2x_prev_path_list *tmp_list;
10633 int rc;
10634
7fa6f340
YM		 10635 rc = down_interruptible(&bnx2x_prev_sem);
10636 if (rc) {
10637 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10638 return rc;
10639 }
10640
10641 /* Check whether the entry for this path already exists */
10642 tmp_list = bnx2x_prev_path_get_entry(bp);
10643 if (tmp_list) {
10644 if (!tmp_list->aer) {
10645 BNX2X_ERR("Re-Marking the path.\n");
10646 } else {
10647 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10648 BP_PATH(bp));
10649 tmp_list->aer = 0;
10650 }
10651 up(&bnx2x_prev_sem);
10652 return 0;
10653 }
10654 up(&bnx2x_prev_sem);
10655
10656 /* Create an entry for this path and add it */
ea4b3857 10657 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10658 if (!tmp_list) {
10659 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10660 return -ENOMEM;
10661 }
10662
10663 tmp_list->bus = bp->pdev->bus->number;
10664 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10665 tmp_list->path = BP_PATH(bp);
7fa6f340 10666 tmp_list->aer = 0;
c63da990 10667 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10668
10669 rc = down_interruptible(&bnx2x_prev_sem);
10670 if (rc) {
10671 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10672 kfree(tmp_list);
10673 } else {
7fa6f340
YM		 10674 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10675 BP_PATH(bp));
452427b0
YM		 10676 list_add(&tmp_list->list, &bnx2x_prev_list);
10677 up(&bnx2x_prev_sem);
10678 }
10679
10680 return rc;
10681}
10682
0329aba1 10683static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10684{
452427b0
YM		 10685 struct pci_dev *dev = bp->pdev;
10686
8eee694c
YM		 10687 if (CHIP_IS_E1x(bp)) {
10688 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10689 return -EINVAL;
10690 }
10691
10692 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10693 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10694 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10695 bp->common.bc_ver);
10696 return -EINVAL;
10697 }
452427b0 10698
8903b9eb
CL		 10699 if (!pci_wait_for_pending_transaction(dev))
10700 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10701
8eee694c 10702 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10703 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10704
10705 return 0;
10706}
10707
0329aba1 10708static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10709{
10710 int rc;
10711
10712 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10713
10714 /* Test if previous unload process was already finished for this path */
10715 if (bnx2x_prev_is_path_marked(bp))
10716 return bnx2x_prev_mcp_done(bp);
10717
04c46736
YM		 10718 BNX2X_DEV_INFO("Path is unmarked\n");
10719
b17b0ca1
YM		 10720 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10721 if (bnx2x_prev_is_after_undi(bp))
10722 goto out;
10723
452427b0
YM		 10724 /* If function has FLR capabilities, and existing FW version matches
10725 * the one required, then FLR will be sufficient to clean any residue
10726 * left by previous driver
10727 */
91ebb929 10728 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10729
10730 if (!rc) {
10731 /* fw version is good */
10732 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10733 rc = bnx2x_do_flr(bp);
10734 }
10735
10736 if (!rc) {
10737 /* FLR was performed */
10738 BNX2X_DEV_INFO("FLR successful\n");
10739 return 0;
10740 }
10741
10742 BNX2X_DEV_INFO("Could not FLR\n");
452427b0 10743
b17b0ca1 10744out:
452427b0
YM		 10745 /* Close the MCP request, return failure*/
10746 rc = bnx2x_prev_mcp_done(bp);
10747 if (!rc)
10748 rc = BNX2X_PREV_WAIT_NEEDED;
10749
10750 return rc;
10751}
10752
0329aba1 10753static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10754{
10755 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10756 bool prev_undi = false;
1ef1d45a
BW		 10757 struct bnx2x_mac_vals mac_vals;
10758
452427b0
YM		 10759 /* It is possible a previous function received 'common' answer,
10760 * but hasn't loaded yet, therefore creating a scenario of
10761 * multiple functions receiving 'common' on the same path.
10762 */
10763 BNX2X_DEV_INFO("Common unload Flow\n");
10764
1ef1d45a
BW		 10765 memset(&mac_vals, 0, sizeof(mac_vals));
10766
452427b0
YM		 10767 if (bnx2x_prev_is_path_marked(bp))
10768 return bnx2x_prev_mcp_done(bp);
10769
10770 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10771
10772 /* Reset should be performed after BRB is emptied */
10773 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10774 u32 timer_count = 1000;
452427b0
YM		 10775
10776 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10777 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10778
3d6b7253 10779 /* close LLH filters for both ports towards the BRB */
1ef1d45a 10780 bnx2x_set_rx_filter(&bp->link_params, 0);
3d6b7253 10781 bp->link_params.port ^= 1;
1ef1d45a 10782 bnx2x_set_rx_filter(&bp->link_params, 0);
3d6b7253 10783 bp->link_params.port ^= 1;
452427b0 10784
b17b0ca1
YM		 10785 /* Check if the UNDI driver was previously loaded */
10786 if (bnx2x_prev_is_after_undi(bp)) {
10787 prev_undi = true;
10788 /* clear the UNDI indication */
10789 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10790 /* clear possible idle check errors */
10791 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
452427b0 10792 }
d46f7c4d
DK		 10793 if (!CHIP_IS_E1x(bp))
10794 /* block FW from writing to host */
10795 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10796
452427b0
YM		 10797 /* wait until BRB is empty */
10798 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10799 while (timer_count) {
10800 u32 prev_brb = tmp_reg;
34f80b04 10801
452427b0
YM		 10802 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10803 if (!tmp_reg)
10804 break;
619c5cb6 10805
452427b0 10806 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10807
452427b0
YM		 10808 /* reset timer as long as BRB actually gets emptied */
10809 if (prev_brb > tmp_reg)
10810 timer_count = 1000;
10811 else
10812 timer_count--;
da5a662a 10813
7c3afd85
YM		 10814 /* If UNDI resides in memory, manually increment it */
10815 if (prev_undi)
10816 bnx2x_prev_unload_undi_inc(bp, 1);
10817
452427b0 10818 udelay(10);
7a06a122 10819 }
452427b0
YM		 10820
10821 if (!timer_count)
10822 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10823 }
f16da43b 10824
452427b0
YM		 10825 /* No packets are in the pipeline, path is ready for reset */
10826 bnx2x_reset_common(bp);
10827
1ef1d45a
BW		 10828 if (mac_vals.xmac_addr)
10829 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
3d6b7253
YM		 10830 if (mac_vals.umac_addr[0])
10831 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10832 if (mac_vals.umac_addr[1])
10833 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
1ef1d45a
BW		 10834 if (mac_vals.emac_addr)
10835 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10836 if (mac_vals.bmac_addr) {
10837 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10838 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10839 }
10840
c63da990 10841 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10842 if (rc) {
10843 bnx2x_prev_mcp_done(bp);
10844 return rc;
10845 }
10846
10847 return bnx2x_prev_mcp_done(bp);
10848}
10849
0329aba1 10850static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10851{
10852 int time_counter = 10;
10853 u32 rc, fw, hw_lock_reg, hw_lock_val;
10854 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10855
24f06716
AE		 10856 /* clear hw from errors which may have resulted from an interrupted
10857 * dmae transaction.
10858 */
da254fbc 10859 bnx2x_clean_pglue_errors(bp);
24f06716
AE		 10860
10861 /* Release previously held locks */
452427b0
YM		 10862 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10863 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10864 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10865
3cdeec22 10866 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10867 if (hw_lock_val) {
10868 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10869 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10870 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10871 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10872 }
10873
10874 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10875 REG_WR(bp, hw_lock_reg, 0xffffffff);
10876 } else
10877 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10878
10879 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10880 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10881 bnx2x_release_alr(bp);
452427b0
YM		 10882 }
10883
452427b0 10884 do {
7fa6f340 10885 int aer = 0;
452427b0
YM		 10886 /* Lock MCP using an unload request */
10887 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10888 if (!fw) {
10889 BNX2X_ERR("MCP response failure, aborting\n");
10890 rc = -EBUSY;
10891 break;
10892 }
10893
7fa6f340
YM		 10894 rc = down_interruptible(&bnx2x_prev_sem);
10895 if (rc) {
10896 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10897 rc);
10898 } else {
10899 /* If Path is marked by EEH, ignore unload status */
10900 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10901 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10902 up(&bnx2x_prev_sem);
7fa6f340 10903 }
7fa6f340
YM		 10904
10905 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10906 rc = bnx2x_prev_unload_common(bp);
10907 break;
10908 }
10909
16a5fd92 10910 /* non-common reply from MCP might require looping */
452427b0
YM		 10911 rc = bnx2x_prev_unload_uncommon(bp);
10912 if (rc != BNX2X_PREV_WAIT_NEEDED)
10913 break;
10914
10915 msleep(20);
10916 } while (--time_counter);
10917
10918 if (!time_counter || rc) {
91ebb929
YM		 10919 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10920 rc = -EPROBE_DEFER;
452427b0
YM		 10921 }
10922
c63da990 10923 /* Mark function if its port was used to boot from SAN */
178135c1 10924 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10925 bp->link_params.feature_config_flags |=
10926 FEATURE_CONFIG_BOOT_FROM_SAN;
10927
452427b0
YM		 10928 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10929
10930 return rc;
34f80b04
EG		 10931}
10932
0329aba1 10933static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10934{
1d187b34 10935 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10936 u16 pmc;
34f80b04
EG		 10937
10938 /* Get the chip revision id and number. */
10939 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10940 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10941 id = ((val & 0xffff) << 16);
10942 val = REG_RD(bp, MISC_REG_CHIP_REV);
10943 id |= ((val & 0xf) << 12);
f22fdf25
YM		 10944
10945 /* Metal is read from PCI regs, but we can't access >=0x400 from
10946 * the configuration space (so we need to reg_rd)
10947 */
10948 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10949 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 10950 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10951 id |= (val & 0xf);
10952 bp->common.chip_id = id;
523224a3 10953
7e8e02df
BW		 10954 /* force 57811 according to MISC register */
10955 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10956 if (CHIP_IS_57810(bp))
10957 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10958 (bp->common.chip_id & 0x0000FFFF);
10959 else if (CHIP_IS_57810_MF(bp))
10960 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10961 (bp->common.chip_id & 0x0000FFFF);
10962 bp->common.chip_id |= 0x1;
10963 }
10964
523224a3
DK		 10965 /* Set doorbell size */
10966 bp->db_size = (1 << BNX2X_DB_SHIFT);
10967
619c5cb6 10968 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10969 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10970 if ((val & 1) == 0)
10971 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10972 else
10973 val = (val >> 1) & 1;
10974 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10975 "2_PORT_MODE");
10976 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10977 CHIP_2_PORT_MODE;
10978
10979 if (CHIP_MODE_IS_4_PORT(bp))
10980 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10981 else
10982 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10983 } else {
10984 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10985 bp->pfid = bp->pf_num; /* 0..7 */
10986 }
10987
51c1a580
MS		 10988 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10989
f2e0899f
DK		 10990 bp->link_params.chip_id = bp->common.chip_id;
10991 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10992
1c06328c
EG		 10993 val = (REG_RD(bp, 0x2874) & 0x55);
10994 if ((bp->common.chip_id & 0x1) ||
10995 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10996 bp->flags |= ONE_PORT_FLAG;
10997 BNX2X_DEV_INFO("single port device\n");
10998 }
10999
34f80b04 11000 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 11001 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 11002 (val & MCPR_NVM_CFG4_FLASH_SIZE));
11003 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
11004 bp->common.flash_size, bp->common.flash_size);
11005
1b6e2ceb
DK		 11006 bnx2x_init_shmem(bp);
11007
f2e0899f
DK		 11008 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
11009 MISC_REG_GENERIC_CR_1 :
11010 MISC_REG_GENERIC_CR_0));
1b6e2ceb 11011
34f80b04 11012 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 11013 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 11014 if (SHMEM2_RD(bp, size) >
11015 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
11016 bp->link_params.lfa_base =
11017 REG_RD(bp, bp->common.shmem2_base +
11018 (u32)offsetof(struct shmem2_region,
11019 lfa_host_addr[BP_PORT(bp)]));
11020 else
11021 bp->link_params.lfa_base = 0;
2691d51d
EG		 11022 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
11023 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 11024
f2e0899f 11025 if (!bp->common.shmem_base) {
34f80b04
EG		 11026 BNX2X_DEV_INFO("MCP not active\n");
11027 bp->flags |= NO_MCP_FLAG;
11028 return;
11029 }
11030
34f80b04 11031 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 11032 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 11033
11034 bp->link_params.hw_led_mode = ((bp->common.hw_config &
11035 SHARED_HW_CFG_LED_MODE_MASK) >>
11036 SHARED_HW_CFG_LED_MODE_SHIFT);
11037
c2c8b03e
EG		 11038 bp->link_params.feature_config_flags = 0;
11039 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
11040 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
11041 bp->link_params.feature_config_flags |=
11042 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11043 else
11044 bp->link_params.feature_config_flags &=
11045 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11046
34f80b04
EG		 11047 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
11048 bp->common.bc_ver = val;
11049 BNX2X_DEV_INFO("bc_ver %X\n", val);
11050 if (val < BNX2X_BC_VER) {
11051 /* for now only warn
11052 * later we might need to enforce this */
51c1a580
MS		 11053 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11054 BNX2X_BC_VER, val);
34f80b04 11055 }
4d295db0 11056 bp->link_params.feature_config_flags |=
a22f0788 11057 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 11058 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11059
a22f0788
YR		 11060 bp->link_params.feature_config_flags |=
11061 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11062 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 11063 bp->link_params.feature_config_flags |=
11064 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11065 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 11066 bp->link_params.feature_config_flags |=
11067 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11068 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 11069
11070 bp->link_params.feature_config_flags |=
11071 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11072 FEATURE_CONFIG_MT_SUPPORT : 0;
11073
0e898dd7
BW		 11074 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11075 BC_SUPPORTS_PFC_STATS : 0;
85242eea 11076
2e499d3c
BW		 11077 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11078 BC_SUPPORTS_FCOE_FEATURES : 0;
11079
9876879f
BW		 11080 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11081 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 11082
11083 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11084 BC_SUPPORTS_RMMOD_CMD : 0;
11085
1d187b34
BW		 11086 boot_mode = SHMEM_RD(bp,
11087 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11088 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11089 switch (boot_mode) {
11090 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11091 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11092 break;
11093 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11094 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11095 break;
11096 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11097 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11098 break;
11099 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11100 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11101 break;
11102 }
11103
29ed74c3 11104 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 11105 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11106
72ce58c3 11107 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 11108 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 11109
11110 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11111 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11112 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11113 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11114
cdaa7cb8
VZ		 11115 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11116 val, val2, val3, val4);
34f80b04
EG		 11117}
11118
f2e0899f
DK		 11119#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11120#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11121
0329aba1 11122static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 11123{
11124 int pfid = BP_FUNC(bp);
f2e0899f
DK		 11125 int igu_sb_id;
11126 u32 val;
6383c0b3 11127 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 11128
11129 bp->igu_base_sb = 0xff;
f2e0899f 11130 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 11131 int vn = BP_VN(bp);
6383c0b3 11132 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 11133 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11134 FP_SB_MAX_E1x;
11135
11136 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
11137 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11138
9b341bb1 11139 return 0;
f2e0899f
DK		 11140 }
11141
11142 /* IGU in normal mode - read CAM */
11143 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11144 igu_sb_id++) {
11145 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11146 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11147 continue;
11148 fid = IGU_FID(val);
11149 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11150 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11151 continue;
11152 if (IGU_VEC(val) == 0)
11153 /* default status block */
11154 bp->igu_dsb_id = igu_sb_id;
11155 else {
11156 if (bp->igu_base_sb == 0xff)
11157 bp->igu_base_sb = igu_sb_id;
6383c0b3 11158 igu_sb_cnt++;
f2e0899f
DK		 11159 }
11160 }
11161 }
619c5cb6 11162
6383c0b3 11163#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 11164 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11165 * optional that number of CAM entries will not be equal to the value
11166 * advertised in PCI.
11167 * Driver should use the minimal value of both as the actual status
11168 * block count
619c5cb6 11169 */
185d4c8b 11170 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 11171#endif
619c5cb6 11172
9b341bb1 11173 if (igu_sb_cnt == 0) {
f2e0899f 11174 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 11175 return -EINVAL;
11176 }
11177
11178 return 0;
f2e0899f
DK		 11179}
11180
1dd06ae8 11181static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 11182{
a22f0788
YR		 11183 int cfg_size = 0, idx, port = BP_PORT(bp);
11184
11185 /* Aggregation of supported attributes of all external phys */
11186 bp->port.supported[0] = 0;
11187 bp->port.supported[1] = 0;
b7737c9b
YR		 11188 switch (bp->link_params.num_phys) {
11189 case 1:
a22f0788
YR		 11190 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11191 cfg_size = 1;
11192 break;
b7737c9b 11193 case 2:
a22f0788
YR		 11194 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11195 cfg_size = 1;
11196 break;
11197 case 3:
11198 if (bp->link_params.multi_phy_config &
11199 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11200 bp->port.supported[1] =
11201 bp->link_params.phy[EXT_PHY1].supported;
11202 bp->port.supported[0] =
11203 bp->link_params.phy[EXT_PHY2].supported;
11204 } else {
11205 bp->port.supported[0] =
11206 bp->link_params.phy[EXT_PHY1].supported;
11207 bp->port.supported[1] =
11208 bp->link_params.phy[EXT_PHY2].supported;
11209 }
11210 cfg_size = 2;
11211 break;
b7737c9b 11212 }
a2fbb9ea 11213
a22f0788 11214 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 11215 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 11216 SHMEM_RD(bp,
a22f0788
YR		 11217 dev_info.port_hw_config[port].external_phy_config),
11218 SHMEM_RD(bp,
11219 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 11220 return;
f85582f8 11221 }
a2fbb9ea 11222
619c5cb6
VZ		 11223 if (CHIP_IS_E3(bp))
11224 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11225 else {
11226 switch (switch_cfg) {
11227 case SWITCH_CFG_1G:
11228 bp->port.phy_addr = REG_RD(
11229 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11230 break;
11231 case SWITCH_CFG_10G:
11232 bp->port.phy_addr = REG_RD(
11233 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11234 break;
11235 default:
11236 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11237 bp->port.link_config[0]);
11238 return;
11239 }
a2fbb9ea 11240 }
619c5cb6 11241 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 11242 /* mask what we support according to speed_cap_mask per configuration */
11243 for (idx = 0; idx < cfg_size; idx++) {
11244 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11245 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 11246 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 11247
a22f0788 11248 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11249 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 11250 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 11251
a22f0788 11252 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11253 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 11254 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 11255
a22f0788 11256 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11257 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 11258 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 11259
a22f0788 11260 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11261 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 11262 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 11263 SUPPORTED_1000baseT_Full);
a2fbb9ea 11264
a22f0788 11265 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11266 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 11267 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 11268
a22f0788 11269 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11270 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 11271 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 11272
11273 if (!(bp->link_params.speed_cap_mask[idx] &
11274 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11275 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 11276 }
a2fbb9ea 11277
a22f0788
YR		 11278 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11279 bp->port.supported[1]);
a2fbb9ea
ET		 11280}
11281
0329aba1 11282static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 11283{
a22f0788
YR		 11284 u32 link_config, idx, cfg_size = 0;
11285 bp->port.advertising[0] = 0;
11286 bp->port.advertising[1] = 0;
11287 switch (bp->link_params.num_phys) {
11288 case 1:
11289 case 2:
11290 cfg_size = 1;
11291 break;
11292 case 3:
11293 cfg_size = 2;
11294 break;
11295 }
11296 for (idx = 0; idx < cfg_size; idx++) {
11297 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11298 link_config = bp->port.link_config[idx];
11299 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 11300 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 11301 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11302 bp->link_params.req_line_speed[idx] =
11303 SPEED_AUTO_NEG;
11304 bp->port.advertising[idx] |=
11305 bp->port.supported[idx];
10bd1f24
MY		 11306 if (bp->link_params.phy[EXT_PHY1].type ==
11307 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11308 bp->port.advertising[idx] |=
11309 (SUPPORTED_100baseT_Half |
11310 SUPPORTED_100baseT_Full);
f85582f8
DK		 11311 } else {
11312 /* force 10G, no AN */
a22f0788
YR		 11313 bp->link_params.req_line_speed[idx] =
11314 SPEED_10000;
11315 bp->port.advertising[idx] |=
11316 (ADVERTISED_10000baseT_Full |
f85582f8 11317 ADVERTISED_FIBRE);
a22f0788 11318 continue;
f85582f8
DK		 11319 }
11320 break;
a2fbb9ea 11321
f85582f8 11322 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 11323 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11324 bp->link_params.req_line_speed[idx] =
11325 SPEED_10;
11326 bp->port.advertising[idx] |=
11327 (ADVERTISED_10baseT_Full |
f85582f8
DK		 11328 ADVERTISED_TP);
11329 } else {
51c1a580 11330 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 11331 link_config,
a22f0788 11332 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11333 return;
11334 }
11335 break;
a2fbb9ea 11336
f85582f8 11337 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 11338 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11339 bp->link_params.req_line_speed[idx] =
11340 SPEED_10;
11341 bp->link_params.req_duplex[idx] =
11342 DUPLEX_HALF;
11343 bp->port.advertising[idx] |=
11344 (ADVERTISED_10baseT_Half |
f85582f8
DK		 11345 ADVERTISED_TP);
11346 } else {
51c1a580 11347 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11348 link_config,
11349 bp->link_params.speed_cap_mask[idx]);
11350 return;
11351 }
11352 break;
a2fbb9ea 11353
f85582f8
DK		 11354 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11355 if (bp->port.supported[idx] &
11356 SUPPORTED_100baseT_Full) {
a22f0788
YR		 11357 bp->link_params.req_line_speed[idx] =
11358 SPEED_100;
11359 bp->port.advertising[idx] |=
11360 (ADVERTISED_100baseT_Full |
f85582f8
DK		 11361 ADVERTISED_TP);
11362 } else {
51c1a580 11363 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11364 link_config,
11365 bp->link_params.speed_cap_mask[idx]);
11366 return;
11367 }
11368 break;
a2fbb9ea 11369
f85582f8
DK		 11370 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11371 if (bp->port.supported[idx] &
11372 SUPPORTED_100baseT_Half) {
11373 bp->link_params.req_line_speed[idx] =
11374 SPEED_100;
11375 bp->link_params.req_duplex[idx] =
11376 DUPLEX_HALF;
a22f0788
YR		 11377 bp->port.advertising[idx] |=
11378 (ADVERTISED_100baseT_Half |
f85582f8
DK		 11379 ADVERTISED_TP);
11380 } else {
51c1a580 11381 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11382 link_config,
11383 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11384 return;
11385 }
11386 break;
a2fbb9ea 11387
f85582f8 11388 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 11389 if (bp->port.supported[idx] &
11390 SUPPORTED_1000baseT_Full) {
11391 bp->link_params.req_line_speed[idx] =
11392 SPEED_1000;
11393 bp->port.advertising[idx] |=
11394 (ADVERTISED_1000baseT_Full |
f85582f8 11395 ADVERTISED_TP);
5d67c1c5
YM		 11396 } else if (bp->port.supported[idx] &
11397 SUPPORTED_1000baseKX_Full) {
11398 bp->link_params.req_line_speed[idx] =
11399 SPEED_1000;
11400 bp->port.advertising[idx] |=
11401 ADVERTISED_1000baseKX_Full;
f85582f8 11402 } else {
51c1a580 11403 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11404 link_config,
11405 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11406 return;
11407 }
11408 break;
a2fbb9ea 11409
f85582f8 11410 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 11411 if (bp->port.supported[idx] &
11412 SUPPORTED_2500baseX_Full) {
11413 bp->link_params.req_line_speed[idx] =
11414 SPEED_2500;
11415 bp->port.advertising[idx] |=
11416 (ADVERTISED_2500baseX_Full |
34f80b04 11417 ADVERTISED_TP);
f85582f8 11418 } else {
51c1a580 11419 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11420 link_config,
f85582f8
DK		 11421 bp->link_params.speed_cap_mask[idx]);
11422 return;
11423 }
11424 break;
a2fbb9ea 11425
f85582f8 11426 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 11427 if (bp->port.supported[idx] &
11428 SUPPORTED_10000baseT_Full) {
11429 bp->link_params.req_line_speed[idx] =
11430 SPEED_10000;
11431 bp->port.advertising[idx] |=
11432 (ADVERTISED_10000baseT_Full |
34f80b04 11433 ADVERTISED_FIBRE);
5d67c1c5
YM		 11434 } else if (bp->port.supported[idx] &
11435 SUPPORTED_10000baseKR_Full) {
11436 bp->link_params.req_line_speed[idx] =
11437 SPEED_10000;
11438 bp->port.advertising[idx] |=
11439 (ADVERTISED_10000baseKR_Full |
11440 ADVERTISED_FIBRE);
f85582f8 11441 } else {
51c1a580 11442 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11443 link_config,
f85582f8
DK		 11444 bp->link_params.speed_cap_mask[idx]);
11445 return;
11446 }
11447 break;
3c9ada22
YR		 11448 case PORT_FEATURE_LINK_SPEED_20G:
11449 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 11450
3c9ada22 11451 break;
f85582f8 11452 default:
51c1a580 11453 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 11454 link_config);
f85582f8
DK		 11455 bp->link_params.req_line_speed[idx] =
11456 SPEED_AUTO_NEG;
11457 bp->port.advertising[idx] =
11458 bp->port.supported[idx];
11459 break;
11460 }
a2fbb9ea 11461
a22f0788 11462 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 11463 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 11464 if (bp->link_params.req_flow_ctrl[idx] ==
11465 BNX2X_FLOW_CTRL_AUTO) {
11466 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11467 bp->link_params.req_flow_ctrl[idx] =
11468 BNX2X_FLOW_CTRL_NONE;
11469 else
11470 bnx2x_set_requested_fc(bp);
a22f0788 11471 }
a2fbb9ea 11472
51c1a580 11473 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 11474 bp->link_params.req_line_speed[idx],
11475 bp->link_params.req_duplex[idx],
11476 bp->link_params.req_flow_ctrl[idx],
11477 bp->port.advertising[idx]);
11478 }
a2fbb9ea
ET		 11479}
11480
0329aba1 11481static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 11482{
86564c3f
YM		 11483 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11484 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11485 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11486 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 11487}
11488
0329aba1 11489static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 11490{
34f80b04 11491 int port = BP_PORT(bp);
589abe3a 11492 u32 config;
c8c60d88 11493 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 11494
c18487ee 11495 bp->link_params.bp = bp;
34f80b04 11496 bp->link_params.port = port;
c18487ee 11497
c18487ee 11498 bp->link_params.lane_config =
a2fbb9ea 11499 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 11500
a22f0788 11501 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 11502 SHMEM_RD(bp,
b0261926
YR		 11503 dev_info.port_hw_config[port].speed_capability_mask) &
11504 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 11505 bp->link_params.speed_cap_mask[1] =
11506 SHMEM_RD(bp,
b0261926
YR		 11507 dev_info.port_hw_config[port].speed_capability_mask2) &
11508 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 11509 bp->port.link_config[0] =
a2fbb9ea
ET		 11510 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11511
a22f0788
YR		 11512 bp->port.link_config[1] =
11513 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 11514
a22f0788
YR		 11515 bp->link_params.multi_phy_config =
11516 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 11517 /* If the device is capable of WoL, set the default state according
11518 * to the HW
11519 */
4d295db0 11520 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 11521 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11522 (config & PORT_FEATURE_WOL_ENABLED));
11523
4ba7699b
YM		 11524 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11525 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11526 bp->flags |= NO_ISCSI_FLAG;
11527 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11528 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11529 bp->flags |= NO_FCOE_FLAG;
11530
51c1a580 11531 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11532 bp->link_params.lane_config,
a22f0788
YR		 11533 bp->link_params.speed_cap_mask[0],
11534 bp->port.link_config[0]);
a2fbb9ea 11535
a22f0788 11536 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11537 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11538 bnx2x_phy_probe(&bp->link_params);
c18487ee 11539 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11540
11541 bnx2x_link_settings_requested(bp);
11542
01cd4528
EG		 11543 /*
11544 * If connected directly, work with the internal PHY, otherwise, work
11545 * with the external PHY
11546 */
b7737c9b
YR		 11547 ext_phy_config =
11548 SHMEM_RD(bp,
11549 dev_info.port_hw_config[port].external_phy_config);
11550 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11551 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11552 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11553
11554 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11555 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11556 bp->mdio.prtad =
b7737c9b 11557 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11558
c8c60d88
YM		 11559 /* Configure link feature according to nvram value */
11560 eee_mode = (((SHMEM_RD(bp, dev_info.
11561 port_feature_config[port].eee_power_mode)) &
11562 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11563 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11564 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11565 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11566 EEE_MODE_ENABLE_LPI |
11567 EEE_MODE_OUTPUT_TIME;
11568 } else {
11569 bp->link_params.eee_mode = 0;
11570 }
0793f83f 11571}
01cd4528 11572
b306f5ed 11573void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11574{
9e62e912 11575 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11576 int port = BP_PORT(bp);
2ba45142 11577 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11578 drv_lic_key[port].max_iscsi_conn);
2ba45142 11579
55c11941
MS		 11580 if (!CNIC_SUPPORT(bp)) {
11581 bp->flags |= no_flags;
11582 return;
11583 }
11584
b306f5ed 11585 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11586 bp->cnic_eth_dev.max_iscsi_conn =
11587 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11588 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11589
b306f5ed
DK		 11590 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11591 bp->cnic_eth_dev.max_iscsi_conn);
11592
11593 /*
11594 * If maximum allowed number of connections is zero -
11595 * disable the feature.
11596 */
11597 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11598 bp->flags |= no_flags;
b306f5ed
DK		 11599}
11600
0329aba1 11601static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11602{
11603 /* Port info */
11604 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11605 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11606 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11607 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11608
11609 /* Node info */
11610 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11611 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11612 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11613 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11614}
86800194
DK		 11615
11616static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11617{
11618 u8 count = 0;
11619
11620 if (IS_MF(bp)) {
11621 u8 fid;
11622
11623 /* iterate over absolute function ids for this path: */
11624 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11625 if (IS_MF_SD(bp)) {
11626 u32 cfg = MF_CFG_RD(bp,
11627 func_mf_config[fid].config);
11628
11629 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11630 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11631 FUNC_MF_CFG_PROTOCOL_FCOE))
11632 count++;
11633 } else {
11634 u32 cfg = MF_CFG_RD(bp,
11635 func_ext_config[fid].
11636 func_cfg);
11637
11638 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11639 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11640 count++;
11641 }
11642 }
11643 } else { /* SF */
11644 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11645
11646 for (port = 0; port < port_cnt; port++) {
11647 u32 lic = SHMEM_RD(bp,
11648 drv_lic_key[port].max_fcoe_conn) ^
11649 FW_ENCODE_32BIT_PATTERN;
11650 if (lic)
11651 count++;
11652 }
11653 }
11654
11655 return count;
11656}
11657
0329aba1 11658static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11659{
11660 int port = BP_PORT(bp);
11661 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11662 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11663 drv_lic_key[port].max_fcoe_conn);
86800194 11664 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11665
55c11941
MS		 11666 if (!CNIC_SUPPORT(bp)) {
11667 bp->flags |= NO_FCOE_FLAG;
11668 return;
11669 }
11670
b306f5ed 11671 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11672 bp->cnic_eth_dev.max_fcoe_conn =
11673 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11674 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11675
0eb43b4b
BPG		 11676 /* Calculate the number of maximum allowed FCoE tasks */
11677 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11678
11679 /* check if FCoE resources must be shared between different functions */
11680 if (num_fcoe_func)
11681 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11682
bf61ee14
VZ		 11683 /* Read the WWN: */
11684 if (!IS_MF(bp)) {
11685 /* Port info */
11686 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11687 SHMEM_RD(bp,
2de67439 11688 dev_info.port_hw_config[port].
bf61ee14
VZ		 11689 fcoe_wwn_port_name_upper);
11690 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11691 SHMEM_RD(bp,
2de67439 11692 dev_info.port_hw_config[port].
bf61ee14
VZ		 11693 fcoe_wwn_port_name_lower);
11694
11695 /* Node info */
11696 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11697 SHMEM_RD(bp,
2de67439 11698 dev_info.port_hw_config[port].
bf61ee14
VZ		 11699 fcoe_wwn_node_name_upper);
11700 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11701 SHMEM_RD(bp,
2de67439 11702 dev_info.port_hw_config[port].
bf61ee14
VZ		 11703 fcoe_wwn_node_name_lower);
11704 } else if (!IS_MF_SD(bp)) {
2e98ffc2 11705 /* Read the WWN info only if the FCoE feature is enabled for
bf61ee14
VZ		 11706 * this function.
11707 */
2e98ffc2
DK		 11708 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11709 bnx2x_get_ext_wwn_info(bp, func);
11710 } else {
11711 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912 11712 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11713 }
bf61ee14 11714
b306f5ed 11715 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11716
bf61ee14
VZ		 11717 /*
11718 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11719 * disable the feature.
11720 */
2ba45142
VZ		 11721 if (!bp->cnic_eth_dev.max_fcoe_conn)
11722 bp->flags |= NO_FCOE_FLAG;
11723}
b306f5ed 11724
0329aba1 11725static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11726{
11727 /*
11728 * iSCSI may be dynamically disabled but reading
11729 * info here we will decrease memory usage by driver
11730 * if the feature is disabled for good
11731 */
11732 bnx2x_get_iscsi_info(bp);
11733 bnx2x_get_fcoe_info(bp);
11734}
2ba45142 11735
0329aba1 11736static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11737{
11738 u32 val, val2;
11739 int func = BP_ABS_FUNC(bp);
11740 int port = BP_PORT(bp);
2ba45142
VZ		 11741 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11742 u8 *fip_mac = bp->fip_mac;
0793f83f 11743
55c11941
MS		 11744 if (IS_MF(bp)) {
11745 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11746 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11747 * In non SD mode features configuration comes from struct
11748 * func_ext_config.
2ba45142 11749 */
2e98ffc2 11750 if (!IS_MF_SD(bp)) {
0793f83f
DK		 11751 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11752 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11753 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11754 iscsi_mac_addr_upper);
0793f83f 11755 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11756 iscsi_mac_addr_lower);
2ba45142 11757 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11758 BNX2X_DEV_INFO
11759 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11760 } else {
2ba45142 11761 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11762 }
2ba45142
VZ		 11763
11764 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11765 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11766 fcoe_mac_addr_upper);
2ba45142 11767 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11768 fcoe_mac_addr_lower);
2ba45142 11769 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11770 BNX2X_DEV_INFO
11771 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11772 } else {
2ba45142 11773 bp->flags |= NO_FCOE_FLAG;
55c11941 11774 }
a3348722
BW		 11775
11776 bp->mf_ext_config = cfg;
11777
9e62e912 11778 } else { /* SD MODE */
55c11941
MS		 11779 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11780 /* use primary mac as iscsi mac */
11781 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11782
11783 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11784 BNX2X_DEV_INFO
11785 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11786 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11787 /* use primary mac as fip mac */
11788 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11789 BNX2X_DEV_INFO("SD FCoE MODE\n");
11790 BNX2X_DEV_INFO
11791 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11792 }
0793f83f 11793 }
a3348722 11794
82594f8f
YM		 11795 /* If this is a storage-only interface, use SAN mac as
11796 * primary MAC. Notice that for SD this is already the case,
11797 * as the SAN mac was copied from the primary MAC.
11798 */
11799 if (IS_MF_FCOE_AFEX(bp))
a3348722 11800 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11801 } else {
0793f83f 11802 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11803 iscsi_mac_upper);
0793f83f 11804 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11805 iscsi_mac_lower);
2ba45142 11806 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11807
11808 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11809 fcoe_fip_mac_upper);
c03bd39c 11810 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11811 fcoe_fip_mac_lower);
c03bd39c 11812 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11813 }
11814
55c11941 11815 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11816 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11817 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
c7bf7169 11818 eth_zero_addr(iscsi_mac);
426b9241
DK		 11819 }
11820
55c11941 11821 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11822 if (!is_valid_ether_addr(fip_mac)) {
11823 bp->flags |= NO_FCOE_FLAG;
c7bf7169 11824 eth_zero_addr(bp->fip_mac);
426b9241 11825 }
55c11941
MS		 11826}
11827
0329aba1 11828static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11829{
11830 u32 val, val2;
11831 int func = BP_ABS_FUNC(bp);
11832 int port = BP_PORT(bp);
11833
11834 /* Zero primary MAC configuration */
c7bf7169 11835 eth_zero_addr(bp->dev->dev_addr);
55c11941
MS		 11836
11837 if (BP_NOMCP(bp)) {
11838 BNX2X_ERROR("warning: random MAC workaround active\n");
11839 eth_hw_addr_random(bp->dev);
11840 } else if (IS_MF(bp)) {
11841 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11842 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11843 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11844 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11845 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11846
11847 if (CNIC_SUPPORT(bp))
11848 bnx2x_get_cnic_mac_hwinfo(bp);
11849 } else {
11850 /* in SF read MACs from port configuration */
11851 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11852 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11853 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11854
11855 if (CNIC_SUPPORT(bp))
11856 bnx2x_get_cnic_mac_hwinfo(bp);
11857 }
11858
3d7d562c
YM		 11859 if (!BP_NOMCP(bp)) {
11860 /* Read physical port identifier from shmem */
11861 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11862 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11863 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11864 bp->flags |= HAS_PHYS_PORT_ID;
11865 }
11866
55c11941 11867 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11868
2e98ffc2 11869 if (!is_valid_ether_addr(bp->dev->dev_addr))
619c5cb6 11870 dev_err(&bp->pdev->dev,
51c1a580
MS		 11871 "bad Ethernet MAC address configuration: %pM\n"
11872 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11873 bp->dev->dev_addr);
7964211d 11874}
51c1a580 11875
0329aba1 11876static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11877{
11878 int tmp;
11879 u32 cfg;
51c1a580 11880
aeeddb8b 11881 if (IS_VF(bp))
4e833c59 11882 return false;
aeeddb8b 11883
7964211d
YM		 11884 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11885 /* Take function: tmp = func */
11886 tmp = BP_ABS_FUNC(bp);
11887 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11888 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11889 } else {
11890 /* Take port: tmp = port */
11891 tmp = BP_PORT(bp);
11892 cfg = SHMEM_RD(bp,
11893 dev_info.port_hw_config[tmp].generic_features);
11894 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11895 }
11896 return cfg;
34f80b04
EG		 11897}
11898
83bad206
YM		 11899static void validate_set_si_mode(struct bnx2x *bp)
11900{
11901 u8 func = BP_ABS_FUNC(bp);
11902 u32 val;
11903
11904 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11905
11906 /* check for legal mac (upper bytes) */
11907 if (val != 0xffff) {
11908 bp->mf_mode = MULTI_FUNCTION_SI;
11909 bp->mf_config[BP_VN(bp)] =
11910 MF_CFG_RD(bp, func_mf_config[func].config);
11911 } else
11912 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11913}
11914
0329aba1 11915static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11916{
0793f83f 11917 int /*abs*/func = BP_ABS_FUNC(bp);
230d00eb 11918 int vn, mfw_vn;
83bad206 11919 u32 val = 0, val2 = 0;
34f80b04 11920 int rc = 0;
a2fbb9ea 11921
0f587f1b
YM		 11922 /* Validate that chip access is feasible */
11923 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11924 dev_err(&bp->pdev->dev,
11925 "Chip read returns all Fs. Preventing probe from continuing\n");
11926 return -EINVAL;
11927 }
11928
34f80b04 11929 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11930
6383c0b3
AE		 11931 /*
11932 * initialize IGU parameters
11933 */
f2e0899f
DK		 11934 if (CHIP_IS_E1x(bp)) {
11935 bp->common.int_block = INT_BLOCK_HC;
11936
11937 bp->igu_dsb_id = DEF_SB_IGU_ID;
11938 bp->igu_base_sb = 0;
f2e0899f
DK		 11939 } else {
11940 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 11941
16a5fd92 11942 /* do not allow device reset during IGU info processing */
7a06a122
DK		 11943 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11944
f2e0899f 11945 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 11946
11947 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11948 int tout = 5000;
11949
11950 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11951
11952 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11953 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11954 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11955
11956 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11957 tout--;
0926d499 11958 usleep_range(1000, 2000);
619c5cb6
VZ		 11959 }
11960
11961 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11962 dev_err(&bp->pdev->dev,
11963 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 11964 bnx2x_release_hw_lock(bp,
11965 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 11966 return -EPERM;
11967 }
11968 }
11969
f2e0899f 11970 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 11971 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 11972 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11973 } else
619c5cb6 11974 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 11975
9b341bb1 11976 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 11977 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 11978 if (rc)
11979 return rc;
f2e0899f 11980 }
619c5cb6
VZ		 11981
11982 /*
11983 * set base FW non-default (fast path) status block id, this value is
11984 * used to initialize the fw_sb_id saved on the fp/queue structure to
11985 * determine the id used by the FW.
11986 */
11987 if (CHIP_IS_E1x(bp))
11988 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11989 else /*
11990 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11991 * the same queue are indicated on the same IGU SB). So we prefer
11992 * FW and IGU SBs to be the same value.
11993 */
11994 bp->base_fw_ndsb = bp->igu_base_sb;
11995
11996 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11997 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11998 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 11999
12000 /*
12001 * Initialize MF configuration
12002 */
523224a3 12003
fb3bff17
DK		 12004 bp->mf_ov = 0;
12005 bp->mf_mode = 0;
7609647e 12006 bp->mf_sub_mode = 0;
3395a033 12007 vn = BP_VN(bp);
230d00eb 12008 mfw_vn = BP_FW_MB_IDX(bp);
0793f83f 12009
f2e0899f 12010 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 12011 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12012 bp->common.shmem2_base, SHMEM2_RD(bp, size),
12013 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
12014
f2e0899f
DK		 12015 if (SHMEM2_HAS(bp, mf_cfg_addr))
12016 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
12017 else
12018 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 12019 offsetof(struct shmem_region, func_mb) +
12020 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 12021 /*
12022 * get mf configuration:
16a5fd92 12023 * 1. Existence of MF configuration
0793f83f
DK		 12024 * 2. MAC address must be legal (check only upper bytes)
12025 * for Switch-Independent mode;
12026 * OVLAN must be legal for Switch-Dependent mode
12027 * 3. SF_MODE configures specific MF mode
12028 */
12029 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12030 /* get mf configuration */
12031 val = SHMEM_RD(bp,
12032 dev_info.shared_feature_config.config);
12033 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
12034
12035 switch (val) {
12036 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
83bad206 12037 validate_set_si_mode(bp);
0793f83f 12038 break;
a3348722
BW		 12039 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
12040 if ((!CHIP_IS_E1x(bp)) &&
12041 (MF_CFG_RD(bp, func_mf_config[func].
12042 mac_upper) != 0xffff) &&
12043 (SHMEM2_HAS(bp,
12044 afex_driver_support))) {
12045 bp->mf_mode = MULTI_FUNCTION_AFEX;
12046 bp->mf_config[vn] = MF_CFG_RD(bp,
12047 func_mf_config[func].config);
12048 } else {
12049 BNX2X_DEV_INFO("can not configure afex mode\n");
12050 }
12051 break;
0793f83f
DK		 12052 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
12053 /* get OV configuration */
12054 val = MF_CFG_RD(bp,
12055 func_mf_config[FUNC_0].e1hov_tag);
12056 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12057
12058 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12059 bp->mf_mode = MULTI_FUNCTION_SD;
12060 bp->mf_config[vn] = MF_CFG_RD(bp,
12061 func_mf_config[func].config);
12062 } else
754a2f52 12063 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 12064 break;
230d00eb
YM		 12065 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12066 bp->mf_mode = MULTI_FUNCTION_SD;
12067 bp->mf_sub_mode = SUB_MF_MODE_BD;
12068 bp->mf_config[vn] =
12069 MF_CFG_RD(bp,
12070 func_mf_config[func].config);
12071
12072 if (SHMEM2_HAS(bp, mtu_size)) {
12073 int mtu_idx = BP_FW_MB_IDX(bp);
12074 u16 mtu_size;
12075 u32 mtu;
12076
12077 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12078 mtu_size = (u16)mtu;
12079 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12080 mtu_size, mtu);
12081
12082 /* if valid: update device mtu */
12083 if (((mtu_size + ETH_HLEN) >=
12084 ETH_MIN_PACKET_SIZE) &&
12085 (mtu_size <=
12086 ETH_MAX_JUMBO_PACKET_SIZE))
12087 bp->dev->mtu = mtu_size;
12088 }
12089 break;
7609647e
YM		 12090 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12091 bp->mf_mode = MULTI_FUNCTION_SD;
12092 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12093 bp->mf_config[vn] =
12094 MF_CFG_RD(bp,
12095 func_mf_config[func].config);
12096 break;
3786b942
AE		 12097 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12098 bp->mf_config[vn] = 0;
12099 break;
83bad206
YM		 12100 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12101 val2 = SHMEM_RD(bp,
12102 dev_info.shared_hw_config.config_3);
12103 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12104 switch (val2) {
12105 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12106 validate_set_si_mode(bp);
12107 bp->mf_sub_mode =
12108 SUB_MF_MODE_NPAR1_DOT_5;
12109 break;
12110 default:
12111 /* Unknown configuration */
12112 bp->mf_config[vn] = 0;
12113 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12114 val);
12115 }
12116 break;
0793f83f
DK		 12117 default:
12118 /* Unknown configuration: reset mf_config */
12119 bp->mf_config[vn] = 0;
51c1a580 12120 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 12121 }
12122 }
a2fbb9ea 12123
2691d51d 12124 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 12125 IS_MF(bp) ? "multi" : "single");
2691d51d 12126
0793f83f
DK		 12127 switch (bp->mf_mode) {
12128 case MULTI_FUNCTION_SD:
12129 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12130 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 12131 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 12132 bp->mf_ov = val;
619c5cb6
VZ		 12133 bp->path_has_ovlan = true;
12134
51c1a580
MS		 12135 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12136 func, bp->mf_ov, bp->mf_ov);
230d00eb
YM		 12137 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12138 (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
7609647e 12139 dev_err(&bp->pdev->dev,
230d00eb 12140 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
7609647e
YM		 12141 func);
12142 bp->path_has_ovlan = true;
2691d51d 12143 } else {
619c5cb6 12144 dev_err(&bp->pdev->dev,
51c1a580
MS		 12145 "No valid MF OV for func %d, aborting\n",
12146 func);
619c5cb6 12147 return -EPERM;
34f80b04 12148 }
0793f83f 12149 break;
a3348722
BW		 12150 case MULTI_FUNCTION_AFEX:
12151 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12152 break;
0793f83f 12153 case MULTI_FUNCTION_SI:
51c1a580
MS		 12154 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12155 func);
0793f83f
DK		 12156 break;
12157 default:
12158 if (vn) {
619c5cb6 12159 dev_err(&bp->pdev->dev,
51c1a580
MS		 12160 "VN %d is in a single function mode, aborting\n",
12161 vn);
619c5cb6 12162 return -EPERM;
2691d51d 12163 }
0793f83f 12164 break;
34f80b04 12165 }
0793f83f 12166
619c5cb6
VZ		 12167 /* check if other port on the path needs ovlan:
12168 * Since MF configuration is shared between ports
12169 * Possible mixed modes are only
12170 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12171 */
12172 if (CHIP_MODE_IS_4_PORT(bp) &&
12173 !bp->path_has_ovlan &&
12174 !IS_MF(bp) &&
12175 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12176 u8 other_port = !BP_PORT(bp);
12177 u8 other_func = BP_PATH(bp) + 2*other_port;
12178 val = MF_CFG_RD(bp,
12179 func_mf_config[other_func].e1hov_tag);
12180 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12181 bp->path_has_ovlan = true;
12182 }
34f80b04 12183 }
a2fbb9ea 12184
e848582c
DK		 12185 /* adjust igu_sb_cnt to MF for E1H */
12186 if (CHIP_IS_E1H(bp) && IS_MF(bp))
12187 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 12188
619c5cb6
VZ		 12189 /* port info */
12190 bnx2x_get_port_hwinfo(bp);
f2e0899f 12191
0793f83f
DK		 12192 /* Get MAC addresses */
12193 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 12194
2ba45142 12195 bnx2x_get_cnic_info(bp);
2ba45142 12196
34f80b04
EG		 12197 return rc;
12198}
12199
0329aba1 12200static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 12201{
12202 int cnt, i, block_end, rodi;
fcdf95cb 12203 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 12204 char str_id_reg[VENDOR_ID_LEN+1];
12205 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 12206 char *vpd_data;
12207 char *vpd_extended_data = NULL;
34f24c7f
VZ		 12208 u8 len;
12209
fcdf95cb 12210 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 12211 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12212
12213 if (cnt < BNX2X_VPD_LEN)
12214 goto out_not_found;
12215
fcdf95cb
BW		 12216 /* VPD RO tag should be first tag after identifier string, hence
12217 * we should be able to find it in first BNX2X_VPD_LEN chars
12218 */
12219 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 12220 PCI_VPD_LRDT_RO_DATA);
12221 if (i < 0)
12222 goto out_not_found;
12223
34f24c7f 12224 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 12225 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 12226
12227 i += PCI_VPD_LRDT_TAG_SIZE;
12228
fcdf95cb
BW		 12229 if (block_end > BNX2X_VPD_LEN) {
12230 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12231 if (vpd_extended_data == NULL)
12232 goto out_not_found;
12233
12234 /* read rest of vpd image into vpd_extended_data */
12235 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12236 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12237 block_end - BNX2X_VPD_LEN,
12238 vpd_extended_data + BNX2X_VPD_LEN);
12239 if (cnt < (block_end - BNX2X_VPD_LEN))
12240 goto out_not_found;
12241 vpd_data = vpd_extended_data;
12242 } else
12243 vpd_data = vpd_start;
12244
12245 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 12246
12247 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12248 PCI_VPD_RO_KEYWORD_MFR_ID);
12249 if (rodi < 0)
12250 goto out_not_found;
12251
12252 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12253
12254 if (len != VENDOR_ID_LEN)
12255 goto out_not_found;
12256
12257 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12258
12259 /* vendor specific info */
12260 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12261 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12262 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12263 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12264
12265 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12266 PCI_VPD_RO_KEYWORD_VENDOR0);
12267 if (rodi >= 0) {
12268 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12269
12270 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12271
12272 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12273 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12274 bp->fw_ver[len] = ' ';
12275 }
12276 }
fcdf95cb 12277 kfree(vpd_extended_data);
34f24c7f
VZ		 12278 return;
12279 }
12280out_not_found:
fcdf95cb 12281 kfree(vpd_extended_data);
34f24c7f
VZ		 12282 return;
12283}
12284
0329aba1 12285static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 12286{
12287 u32 flags = 0;
12288
12289 if (CHIP_REV_IS_FPGA(bp))
12290 SET_FLAGS(flags, MODE_FPGA);
12291 else if (CHIP_REV_IS_EMUL(bp))
12292 SET_FLAGS(flags, MODE_EMUL);
12293 else
12294 SET_FLAGS(flags, MODE_ASIC);
12295
12296 if (CHIP_MODE_IS_4_PORT(bp))
12297 SET_FLAGS(flags, MODE_PORT4);
12298 else
12299 SET_FLAGS(flags, MODE_PORT2);
12300
12301 if (CHIP_IS_E2(bp))
12302 SET_FLAGS(flags, MODE_E2);
12303 else if (CHIP_IS_E3(bp)) {
12304 SET_FLAGS(flags, MODE_E3);
12305 if (CHIP_REV(bp) == CHIP_REV_Ax)
12306 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 12307 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12308 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 12309 }
12310
12311 if (IS_MF(bp)) {
12312 SET_FLAGS(flags, MODE_MF);
12313 switch (bp->mf_mode) {
12314 case MULTI_FUNCTION_SD:
12315 SET_FLAGS(flags, MODE_MF_SD);
12316 break;
12317 case MULTI_FUNCTION_SI:
12318 SET_FLAGS(flags, MODE_MF_SI);
12319 break;
a3348722
BW		 12320 case MULTI_FUNCTION_AFEX:
12321 SET_FLAGS(flags, MODE_MF_AFEX);
12322 break;
619c5cb6
VZ		 12323 }
12324 } else
12325 SET_FLAGS(flags, MODE_SF);
12326
12327#if defined(__LITTLE_ENDIAN)
12328 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12329#else /*(__BIG_ENDIAN)*/
12330 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12331#endif
12332 INIT_MODE_FLAGS(bp) = flags;
12333}
12334
0329aba1 12335static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 12336{
f2e0899f 12337 int func;
34f80b04
EG		 12338 int rc;
12339
34f80b04 12340 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 12341 mutex_init(&bp->fw_mb_mutex);
42f8277f 12342 mutex_init(&bp->drv_info_mutex);
c6e36d8c 12343 sema_init(&bp->stats_lock, 1);
42f8277f 12344 bp->drv_info_mng_owner = false;
05cc5a39 12345 INIT_LIST_HEAD(&bp->vlan_reg);
55c11941 12346
1cf167f2 12347 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 12348 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 12349 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
370d4a26 12350 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
1ab4434c
AE		 12351 if (IS_PF(bp)) {
12352 rc = bnx2x_get_hwinfo(bp);
12353 if (rc)
12354 return rc;
12355 } else {
e09b74d0 12356 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 12357 }
34f80b04 12358
619c5cb6
VZ		 12359 bnx2x_set_modes_bitmap(bp);
12360
12361 rc = bnx2x_alloc_mem_bp(bp);
12362 if (rc)
12363 return rc;
523224a3 12364
34f24c7f 12365 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 12366
12367 func = BP_FUNC(bp);
12368
34f80b04 12369 /* need to reset chip if undi was active */
1ab4434c 12370 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 12371 /* init fw_seq */
12372 bp->fw_seq =
12373 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12374 DRV_MSG_SEQ_NUMBER_MASK;
12375 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12376
91ebb929
YM		 12377 rc = bnx2x_prev_unload(bp);
12378 if (rc) {
12379 bnx2x_free_mem_bp(bp);
12380 return rc;
12381 }
452427b0
YM		 12382 }
12383
34f80b04 12384 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 12385 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 12386
12387 if (BP_NOMCP(bp) && (func == 0))
51c1a580 12388 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 12389
614c76df 12390 bp->disable_tpa = disable_tpa;
2e98ffc2 12391 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
94d9de3c 12392 /* Reduce memory usage in kdump environment by disabling TPA */
c9931896 12393 bp->disable_tpa |= is_kdump_kernel();
614c76df 12394
7a9b2557 12395 /* Set TPA flags */
614c76df 12396 if (bp->disable_tpa) {
d9b9e860 12397 bp->dev->hw_features &= ~NETIF_F_LRO;
7a9b2557 12398 bp->dev->features &= ~NETIF_F_LRO;
7a9b2557
VZ		 12399 }
12400
a18f5128
EG		 12401 if (CHIP_IS_E1(bp))
12402 bp->dropless_fc = 0;
12403 else
7964211d 12404 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 12405
8d5726c4 12406 bp->mrrs = mrrs;
7a9b2557 12407
2e98ffc2 12408 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 12409 if (IS_VF(bp))
12410 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 12411
7d323bfd 12412 /* make sure that the numbers are in the right granularity */
523224a3
DK		 12413 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12414 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 12415
fc543637 12416 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 12417
12418 init_timer(&bp->timer);
12419 bp->timer.expires = jiffies + bp->current_interval;
12420 bp->timer.data = (unsigned long) bp;
12421 bp->timer.function = bnx2x_timer;
12422
0370cf90
BW		 12423 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12424 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
9c73267d 12425 SHMEM2_HAS(bp, dcbx_en) &&
0370cf90 12426 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
9c73267d
YM		 12427 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) &&
12428 SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
0370cf90
BW		 12429 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12430 bnx2x_dcbx_init_params(bp);
12431 } else {
12432 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12433 }
e4901dde 12434
619c5cb6
VZ		 12435 if (CHIP_IS_E1x(bp))
12436 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12437 else
12438 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 12439
6383c0b3 12440 /* multiple tx priority */
1ab4434c
AE		 12441 if (IS_VF(bp))
12442 bp->max_cos = 1;
12443 else if (CHIP_IS_E1x(bp))
6383c0b3 12444 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 12445 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 12446 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 12447 else if (CHIP_IS_E3B0(bp))
6383c0b3 12448 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 12449 else
12450 BNX2X_ERR("unknown chip %x revision %x\n",
12451 CHIP_NUM(bp), CHIP_REV(bp));
12452 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 12453
55c11941
MS		 12454 /* We need at least one default status block for slow-path events,
12455 * second status block for the L2 queue, and a third status block for
16a5fd92 12456 * CNIC if supported.
55c11941 12457 */
60cad4e6
AE		 12458 if (IS_VF(bp))
12459 bp->min_msix_vec_cnt = 1;
12460 else if (CNIC_SUPPORT(bp))
55c11941 12461 bp->min_msix_vec_cnt = 3;
60cad4e6 12462 else /* PF w/o cnic */
55c11941
MS		 12463 bp->min_msix_vec_cnt = 2;
12464 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12465
5bb680d6
MS		 12466 bp->dump_preset_idx = 1;
12467
eeed018c
MK		 12468 if (CHIP_IS_E3B0(bp))
12469 bp->flags |= PTP_SUPPORTED;
12470
34f80b04 12471 return rc;
a2fbb9ea
ET		 12472}
12473
de0c62db
DK		 12474/****************************************************************************
12475* General service functions
12476****************************************************************************/
a2fbb9ea 12477
619c5cb6
VZ		 12478/*
12479 * net_device service functions
12480 */
12481
bb2a0f7a 12482/* called with rtnl_lock */
a2fbb9ea
ET		 12483static int bnx2x_open(struct net_device *dev)
12484{
12485 struct bnx2x *bp = netdev_priv(dev);
8395be5e 12486 int rc;
a2fbb9ea 12487
1355b704
MY		 12488 bp->stats_init = true;
12489
6eccabb3
EG		 12490 netif_carrier_off(dev);
12491
a2fbb9ea
ET		 12492 bnx2x_set_power_state(bp, PCI_D0);
12493
ad5afc89 12494 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 12495 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12496 * want the first function loaded on the current engine to
12497 * complete the recovery.
ad5afc89 12498 * Parity recovery is only relevant for PF driver.
c9ee9206 12499 */
ad5afc89 12500 if (IS_PF(bp)) {
1a6974b2
YM		 12501 int other_engine = BP_PATH(bp) ? 0 : 1;
12502 bool other_load_status, load_status;
12503 bool global = false;
12504
ad5afc89
AE		 12505 other_load_status = bnx2x_get_load_status(bp, other_engine);
12506 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12507 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12508 bnx2x_chk_parity_attn(bp, &global, true)) {
12509 do {
12510 /* If there are attentions and they are in a
12511 * global blocks, set the GLOBAL_RESET bit
12512 * regardless whether it will be this function
12513 * that will complete the recovery or not.
12514 */
12515 if (global)
12516 bnx2x_set_reset_global(bp);
72fd0718 12517
ad5afc89
AE		 12518 /* Only the first function on the current
12519 * engine should try to recover in open. In case
12520 * of attentions in global blocks only the first
12521 * in the chip should try to recover.
12522 */
12523 if ((!load_status &&
12524 (!global || !other_load_status)) &&
12525 bnx2x_trylock_leader_lock(bp) &&
12526 !bnx2x_leader_reset(bp)) {
12527 netdev_info(bp->dev,
12528 "Recovered in open\n");
12529 break;
12530 }
72fd0718 12531
ad5afc89
AE		 12532 /* recovery has failed... */
12533 bnx2x_set_power_state(bp, PCI_D3hot);
12534 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 12535
ad5afc89
AE		 12536 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12537 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 12538
ad5afc89
AE		 12539 return -EAGAIN;
12540 } while (0);
12541 }
12542 }
72fd0718
VZ		 12543
12544 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 12545 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12546 if (rc)
12547 return rc;
f34fa14c 12548
883ce97d 12549 if (IS_PF(bp))
6b352912 12550 udp_tunnel_get_rx_info(dev);
f34fa14c 12551
9a8130bc 12552 return 0;
a2fbb9ea
ET		 12553}
12554
bb2a0f7a 12555/* called with rtnl_lock */
56ad3152 12556static int bnx2x_close(struct net_device *dev)
a2fbb9ea 12557{
a2fbb9ea
ET		 12558 struct bnx2x *bp = netdev_priv(dev);
12559
12560 /* Unload the driver, release IRQs */
5d07d868 12561 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 12562
a2fbb9ea
ET		 12563 return 0;
12564}
12565
1191cb83
ED		 12566static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12567 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 12568{
619c5cb6
VZ		 12569 int mc_count = netdev_mc_count(bp->dev);
12570 struct bnx2x_mcast_list_elem *mc_mac =
cd2b0389 12571 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
619c5cb6 12572 struct netdev_hw_addr *ha;
6e30dd4e 12573
c7b7b483
YM		 12574 if (!mc_mac) {
12575 BNX2X_ERR("Failed to allocate mc MAC list\n");
619c5cb6 12576 return -ENOMEM;
c7b7b483 12577 }
6e30dd4e 12578
619c5cb6 12579 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 12580
619c5cb6
VZ		 12581 netdev_for_each_mc_addr(ha, bp->dev) {
12582 mc_mac->mac = bnx2x_mc_addr(ha);
12583 list_add_tail(&mc_mac->link, &p->mcast_list);
12584 mc_mac++;
6e30dd4e 12585 }
619c5cb6
VZ		 12586
12587 p->mcast_list_len = mc_count;
12588
12589 return 0;
6e30dd4e
VZ		 12590}
12591
1191cb83 12592static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 12593 struct bnx2x_mcast_ramrod_params *p)
12594{
12595 struct bnx2x_mcast_list_elem *mc_mac =
12596 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12597 link);
12598
12599 WARN_ON(!mc_mac);
12600 kfree(mc_mac);
12601}
12602
12603/**
12604 * bnx2x_set_uc_list - configure a new unicast MACs list.
12605 *
12606 * @bp: driver handle
6e30dd4e 12607 *
619c5cb6 12608 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 12609 */
1191cb83 12610static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12611{
619c5cb6 12612 int rc;
6e30dd4e 12613 struct net_device *dev = bp->dev;
6e30dd4e 12614 struct netdev_hw_addr *ha;
15192a8c 12615 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12616 unsigned long ramrod_flags = 0;
6e30dd4e 12617
619c5cb6
VZ		 12618 /* First schedule a cleanup up of old configuration */
12619 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12620 if (rc < 0) {
12621 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12622 return rc;
12623 }
6e30dd4e
VZ		 12624
12625 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12626 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12627 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12628 if (rc == -EEXIST) {
12629 DP(BNX2X_MSG_SP,
12630 "Failed to schedule ADD operations: %d\n", rc);
12631 /* do not treat adding same MAC as error */
12632 rc = 0;
12633
12634 } else if (rc < 0) {
12635
619c5cb6
VZ		 12636 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12637 rc);
12638 return rc;
6e30dd4e
VZ		 12639 }
12640 }
12641
619c5cb6
VZ		 12642 /* Execute the pending commands */
12643 __set_bit(RAMROD_CONT, &ramrod_flags);
12644 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12645 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12646}
12647
c7b7b483 12648static int bnx2x_set_mc_list_e1x(struct bnx2x *bp)
6e30dd4e 12649{
619c5cb6 12650 struct net_device *dev = bp->dev;
3b603066 12651 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12652 int rc = 0;
6e30dd4e 12653
619c5cb6 12654 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12655
619c5cb6
VZ		 12656 /* first, clear all configured multicast MACs */
12657 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12658 if (rc < 0) {
51c1a580 12659 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12660 return rc;
12661 }
6e30dd4e 12662
619c5cb6
VZ		 12663 /* then, configure a new MACs list */
12664 if (netdev_mc_count(dev)) {
12665 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
c7b7b483 12666 if (rc)
619c5cb6 12667 return rc;
6e30dd4e 12668
619c5cb6
VZ		 12669 /* Now add the new MACs */
12670 rc = bnx2x_config_mcast(bp, &rparam,
12671 BNX2X_MCAST_CMD_ADD);
12672 if (rc < 0)
51c1a580
MS		 12673 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12674 rc);
6e30dd4e 12675
619c5cb6
VZ		 12676 bnx2x_free_mcast_macs_list(&rparam);
12677 }
6e30dd4e 12678
619c5cb6 12679 return rc;
6e30dd4e
VZ		 12680}
12681
c7b7b483
YM		 12682static int bnx2x_set_mc_list(struct bnx2x *bp)
12683{
12684 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12685 struct net_device *dev = bp->dev;
12686 int rc = 0;
12687
12688 /* On older adapters, we need to flush and re-add filters */
12689 if (CHIP_IS_E1x(bp))
12690 return bnx2x_set_mc_list_e1x(bp);
12691
12692 rparam.mcast_obj = &bp->mcast_obj;
12693
12694 if (netdev_mc_count(dev)) {
12695 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12696 if (rc)
12697 return rc;
12698
12699 /* Override the curently configured set of mc filters */
12700 rc = bnx2x_config_mcast(bp, &rparam,
12701 BNX2X_MCAST_CMD_SET);
12702 if (rc < 0)
12703 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12704 rc);
12705
12706 bnx2x_free_mcast_macs_list(&rparam);
12707 } else {
12708 /* If no mc addresses are required, flush the configuration */
12709 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12710 if (rc)
12711 BNX2X_ERR("Failed to clear multicast configuration %d\n",
12712 rc);
12713 }
12714
12715 return rc;
12716}
12717
619c5cb6 12718/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12719static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12720{
12721 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12722
12723 if (bp->state != BNX2X_STATE_OPEN) {
12724 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12725 return;
8b09be5f
YM		 12726 } else {
12727 /* Schedule an SP task to handle rest of change */
230bb0f3
YM		 12728 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12729 NETIF_MSG_IFUP);
34f80b04 12730 }
8b09be5f
YM		 12731}
12732
12733void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12734{
12735 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12736
619c5cb6 12737 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12738
8b09be5f
YM		 12739 netif_addr_lock_bh(bp->dev);
12740
12741 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12742 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12743 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12744 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12745 CHIP_IS_E1(bp))) {
34f80b04 12746 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12747 } else {
381ac16b
AE		 12748 if (IS_PF(bp)) {
12749 /* some multicasts */
12750 if (bnx2x_set_mc_list(bp) < 0)
12751 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12752
8b09be5f
YM		 12753 /* release bh lock, as bnx2x_set_uc_list might sleep */
12754 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12755 if (bnx2x_set_uc_list(bp) < 0)
12756 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12757 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12758 } else {
12759 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12760 * wait for the pf's response).
381ac16b 12761 */
230bb0f3
YM		 12762 bnx2x_schedule_sp_rtnl(bp,
12763 BNX2X_SP_RTNL_VFPF_MCAST, 0);
381ac16b 12764 }
34f80b04
EG		 12765 }
12766
12767 bp->rx_mode = rx_mode;
614c76df 12768 /* handle ISCSI SD mode */
2e98ffc2 12769 if (IS_MF_ISCSI_ONLY(bp))
614c76df 12770 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12771
12772 /* Schedule the rx_mode command */
12773 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12774 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12775 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12776 return;
12777 }
12778
381ac16b
AE		 12779 if (IS_PF(bp)) {
12780 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12781 netif_addr_unlock_bh(bp->dev);
381ac16b 12782 } else {
8b09be5f
YM		 12783 /* VF will need to request the PF to make this change, and so
12784 * the VF needs to release the bottom-half lock prior to the
12785 * request (as it will likely require sleep on the VF side)
381ac16b 12786 */
8b09be5f
YM		 12787 netif_addr_unlock_bh(bp->dev);
12788 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12789 }
34f80b04
EG		 12790}
12791
c18487ee 12792/* called with rtnl_lock */
01cd4528
EG		 12793static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12794 int devad, u16 addr)
a2fbb9ea 12795{
01cd4528
EG		 12796 struct bnx2x *bp = netdev_priv(netdev);
12797 u16 value;
12798 int rc;
a2fbb9ea 12799
01cd4528
EG		 12800 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12801 prtad, devad, addr);
a2fbb9ea 12802
01cd4528
EG		 12803 /* The HW expects different devad if CL22 is used */
12804 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12805
01cd4528 12806 bnx2x_acquire_phy_lock(bp);
e10bc84d 12807 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12808 bnx2x_release_phy_lock(bp);
12809 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12810
01cd4528
EG		 12811 if (!rc)
12812 rc = value;
12813 return rc;
12814}
a2fbb9ea 12815
01cd4528
EG		 12816/* called with rtnl_lock */
12817static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12818 u16 addr, u16 value)
12819{
12820 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12821 int rc;
12822
51c1a580
MS		 12823 DP(NETIF_MSG_LINK,
12824 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12825 prtad, devad, addr, value);
01cd4528 12826
01cd4528
EG		 12827 /* The HW expects different devad if CL22 is used */
12828 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12829
01cd4528 12830 bnx2x_acquire_phy_lock(bp);
e10bc84d 12831 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12832 bnx2x_release_phy_lock(bp);
12833 return rc;
12834}
c18487ee 12835
01cd4528
EG		 12836/* called with rtnl_lock */
12837static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12838{
12839 struct bnx2x *bp = netdev_priv(dev);
12840 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12841
01cd4528
EG		 12842 if (!netif_running(dev))
12843 return -EAGAIN;
12844
eeed018c
MK		 12845 switch (cmd) {
12846 case SIOCSHWTSTAMP:
12847 return bnx2x_hwtstamp_ioctl(bp, ifr);
12848 default:
12849 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12850 mdio->phy_id, mdio->reg_num, mdio->val_in);
12851 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12852 }
a2fbb9ea
ET		 12853}
12854
257ddbda 12855#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 12856static void poll_bnx2x(struct net_device *dev)
12857{
12858 struct bnx2x *bp = netdev_priv(dev);
14a15d61 12859 int i;
a2fbb9ea 12860
14a15d61
MS		 12861 for_each_eth_queue(bp, i) {
12862 struct bnx2x_fastpath *fp = &bp->fp[i];
12863 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12864 }
a2fbb9ea
ET		 12865}
12866#endif
12867
614c76df
DK		 12868static int bnx2x_validate_addr(struct net_device *dev)
12869{
12870 struct bnx2x *bp = netdev_priv(dev);
12871
e09b74d0
AE		 12872 /* query the bulletin board for mac address configured by the PF */
12873 if (IS_VF(bp))
12874 bnx2x_sample_bulletin(bp);
12875
2e98ffc2 12876 if (!is_valid_ether_addr(dev->dev_addr)) {
51c1a580 12877 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12878 return -EADDRNOTAVAIL;
51c1a580 12879 }
614c76df
DK		 12880 return 0;
12881}
12882
3d7d562c 12883static int bnx2x_get_phys_port_id(struct net_device *netdev,
02637fce 12884 struct netdev_phys_item_id *ppid)
3d7d562c
YM		 12885{
12886 struct bnx2x *bp = netdev_priv(netdev);
12887
12888 if (!(bp->flags & HAS_PHYS_PORT_ID))
12889 return -EOPNOTSUPP;
12890
12891 ppid->id_len = sizeof(bp->phys_port_id);
12892 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12893
12894 return 0;
12895}
12896
5f35227e
JG		 12897static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12898 struct net_device *dev,
12899 netdev_features_t features)
51de7bb9 12900{
8cb65d00 12901 features = vlan_features_check(skb, features);
5f35227e 12902 return vxlan_features_check(skb, features);
51de7bb9
JS		 12903}
12904
05cc5a39
YM		 12905static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12906{
12907 int rc;
12908
12909 if (IS_PF(bp)) {
12910 unsigned long ramrod_flags = 0;
12911
12912 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12913 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12914 add, &ramrod_flags);
12915 } else {
12916 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12917 }
12918
12919 return rc;
12920}
12921
a02cc9d3 12922static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp)
05cc5a39
YM		 12923{
12924 struct bnx2x_vlan_entry *vlan;
12925 int rc = 0;
12926
a02cc9d3 12927 /* Configure all non-configured entries */
05cc5a39 12928 list_for_each_entry(vlan, &bp->vlan_reg, link) {
a02cc9d3 12929 if (vlan->hw)
05cc5a39
YM		 12930 continue;
12931
a02cc9d3
MS		 12932 if (bp->vlan_cnt >= bp->vlan_credit)
12933 return -ENOBUFS;
05cc5a39
YM		 12934
12935 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12936 if (rc) {
a02cc9d3
MS		 12937 BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid);
12938 return rc;
05cc5a39 12939 }
a02cc9d3
MS		 12940
12941 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid);
12942 vlan->hw = true;
12943 bp->vlan_cnt++;
05cc5a39
YM		 12944 }
12945
a02cc9d3
MS		 12946 return 0;
12947}
12948
12949static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode)
12950{
12951 bool need_accept_any_vlan;
12952
12953 need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp);
12954
12955 if (bp->accept_any_vlan != need_accept_any_vlan) {
12956 bp->accept_any_vlan = need_accept_any_vlan;
12957 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n",
12958 bp->accept_any_vlan ? "raised" : "cleared");
12959 if (set_rx_mode) {
12960 if (IS_PF(bp))
12961 bnx2x_set_rx_mode_inner(bp);
12962 else
12963 bnx2x_vfpf_storm_rx_mode(bp);
12964 }
12965 }
12966}
12967
12968int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
12969{
12970 struct bnx2x_vlan_entry *vlan;
12971
12972 /* The hw forgot all entries after reload */
12973 list_for_each_entry(vlan, &bp->vlan_reg, link)
12974 vlan->hw = false;
12975 bp->vlan_cnt = 0;
12976
12977 /* Don't set rx mode here. Our caller will do it. */
12978 bnx2x_vlan_configure(bp, false);
12979
12980 return 0;
05cc5a39
YM		 12981}
12982
12983static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
12984{
12985 struct bnx2x *bp = netdev_priv(dev);
12986 struct bnx2x_vlan_entry *vlan;
05cc5a39
YM		 12987
12988 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
12989
12990 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
12991 if (!vlan)
12992 return -ENOMEM;
12993
05cc5a39 12994 vlan->vid = vid;
a02cc9d3
MS		 12995 vlan->hw = false;
12996 list_add_tail(&vlan->link, &bp->vlan_reg);
05cc5a39 12997
a02cc9d3
MS		 12998 if (netif_running(dev))
12999 bnx2x_vlan_configure(bp, true);
05cc5a39 13000
a02cc9d3 13001 return 0;
05cc5a39
YM		 13002}
13003
13004static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
13005{
13006 struct bnx2x *bp = netdev_priv(dev);
13007 struct bnx2x_vlan_entry *vlan;
a02cc9d3 13008 bool found = false;
05cc5a39
YM		 13009 int rc = 0;
13010
05cc5a39
YM		 13011 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
13012
05cc5a39 13013 list_for_each_entry(vlan, &bp->vlan_reg, link)
a02cc9d3
MS		 13014 if (vlan->vid == vid) {
13015 found = true;
05cc5a39 13016 break;
a02cc9d3 13017 }
05cc5a39 13018
a02cc9d3 13019 if (!found) {
05cc5a39
YM		 13020 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
13021 return -EINVAL;
13022 }
13023
a02cc9d3 13024 if (netif_running(dev) && vlan->hw) {
05cc5a39 13025 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
a02cc9d3
MS		 13026 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid);
13027 bp->vlan_cnt--;
13028 }
05cc5a39
YM		 13029
13030 list_del(&vlan->link);
13031 kfree(vlan);
13032
a02cc9d3
MS		 13033 if (netif_running(dev))
13034 bnx2x_vlan_configure(bp, true);
05cc5a39
YM		 13035
13036 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
13037
13038 return rc;
13039}
13040
c64213cd
SH		 13041static const struct net_device_ops bnx2x_netdev_ops = {
13042 .ndo_open = bnx2x_open,
13043 .ndo_stop = bnx2x_close,
13044 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 13045 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 13046 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 13047 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 13048 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 13049 .ndo_do_ioctl = bnx2x_ioctl,
13050 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 13051 .ndo_fix_features = bnx2x_fix_features,
13052 .ndo_set_features = bnx2x_set_features,
c64213cd 13053 .ndo_tx_timeout = bnx2x_tx_timeout,
05cc5a39
YM		 13054 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid,
13055 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid,
257ddbda 13056#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 13057 .ndo_poll_controller = poll_bnx2x,
13058#endif
e4c6734e 13059 .ndo_setup_tc = __bnx2x_setup_tc,
6411280a 13060#ifdef CONFIG_BNX2X_SRIOV
abc5a021 13061 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 13062 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 13063 .ndo_get_vf_config = bnx2x_get_vf_config,
6411280a 13064#endif
55c11941 13065#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 13066 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
13067#endif
8f20aa57 13068
3d7d562c 13069 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
6495d15a 13070 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
5f35227e 13071 .ndo_features_check = bnx2x_features_check,
6b352912
AD		 13072 .ndo_udp_tunnel_add = bnx2x_udp_tunnel_add,
13073 .ndo_udp_tunnel_del = bnx2x_udp_tunnel_del,
c64213cd
SH		 13074};
13075
1191cb83 13076static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 13077{
13078 struct device *dev = &bp->pdev->dev;
13079
8ceafbfa
LT		 13080 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13081 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 13082 dev_err(dev, "System does not support DMA, aborting\n");
13083 return -EIO;
13084 }
13085
13086 return 0;
13087}
13088
33d8e6a5
YM		 13089static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13090{
13091 if (bp->flags & AER_ENABLED) {
13092 pci_disable_pcie_error_reporting(bp->pdev);
13093 bp->flags &= ~AER_ENABLED;
13094 }
13095}
13096
1ab4434c
AE		 13097static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13098 struct net_device *dev, unsigned long board_type)
a2fbb9ea 13099{
a2fbb9ea 13100 int rc;
c22610d0 13101 u32 pci_cfg_dword;
65087cfe
AE		 13102 bool chip_is_e1x = (board_type == BCM57710 ||
13103 board_type == BCM57711 ||
13104 board_type == BCM57711E);
a2fbb9ea
ET		 13105
13106 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 13107
34f80b04
EG		 13108 bp->dev = dev;
13109 bp->pdev = pdev;
a2fbb9ea
ET		 13110
13111 rc = pci_enable_device(pdev);
13112 if (rc) {
cdaa7cb8
VZ		 13113 dev_err(&bp->pdev->dev,
13114 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 13115 goto err_out;
13116 }
13117
13118 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 13119 dev_err(&bp->pdev->dev,
13120 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 13121 rc = -ENODEV;
13122 goto err_out_disable;
13123 }
13124
1ab4434c
AE		 13125 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13126 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 13127 rc = -ENODEV;
13128 goto err_out_disable;
13129 }
13130
092a5fc9
YR		 13131 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13132 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13133 PCICFG_REVESION_ID_ERROR_VAL) {
13134 pr_err("PCI device error, probably due to fan failure, aborting\n");
13135 rc = -ENODEV;
13136 goto err_out_disable;
13137 }
13138
34f80b04
EG		 13139 if (atomic_read(&pdev->enable_cnt) == 1) {
13140 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13141 if (rc) {
cdaa7cb8
VZ		 13142 dev_err(&bp->pdev->dev,
13143 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 13144 goto err_out_disable;
13145 }
a2fbb9ea 13146
34f80b04
EG		 13147 pci_set_master(pdev);
13148 pci_save_state(pdev);
13149 }
a2fbb9ea 13150
1ab4434c 13151 if (IS_PF(bp)) {
29ed74c3 13152 if (!pdev->pm_cap) {
1ab4434c
AE		 13153 dev_err(&bp->pdev->dev,
13154 "Cannot find power management capability, aborting\n");
13155 rc = -EIO;
13156 goto err_out_release;
13157 }
a2fbb9ea
ET		 13158 }
13159
77c98e6a 13160 if (!pci_is_pcie(pdev)) {
51c1a580 13161 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 13162 rc = -EIO;
13163 goto err_out_release;
13164 }
13165
619c5cb6
VZ		 13166 rc = bnx2x_set_coherency_mask(bp);
13167 if (rc)
a2fbb9ea 13168 goto err_out_release;
a2fbb9ea 13169
34f80b04
EG		 13170 dev->mem_start = pci_resource_start(pdev, 0);
13171 dev->base_addr = dev->mem_start;
13172 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 13173
13174 dev->irq = pdev->irq;
13175
275f165f 13176 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 13177 if (!bp->regview) {
cdaa7cb8
VZ		 13178 dev_err(&bp->pdev->dev,
13179 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 13180 rc = -ENOMEM;
13181 goto err_out_release;
13182 }
13183
c22610d0
AE		 13184 /* In E1/E1H use pci device function given by kernel.
13185 * In E2/E3 read physical function from ME register since these chips
13186 * support Physical Device Assignment where kernel BDF maybe arbitrary
13187 * (depending on hypervisor).
13188 */
2de67439 13189 if (chip_is_e1x) {
c22610d0 13190 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 13191 } else {
13192 /* chip is E2/3*/
c22610d0
AE		 13193 pci_read_config_dword(bp->pdev,
13194 PCICFG_ME_REGISTER, &pci_cfg_dword);
13195 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 13196 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 13197 }
51c1a580 13198 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 13199
34f80b04
EG		 13200 /* clean indirect addresses */
13201 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13202 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5 13203
da293700
BK		 13204 /* Set PCIe reset type to fundamental for EEH recovery */
13205 pdev->needs_freset = 1;
13206
33d8e6a5
YM		 13207 /* AER (Advanced Error reporting) configuration */
13208 rc = pci_enable_pcie_error_reporting(pdev);
13209 if (!rc)
13210 bp->flags |= AER_ENABLED;
13211 else
13212 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13213
a5c53dbc
DK		 13214 /*
13215 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 13216 * is not used by the driver.
13217 */
1ab4434c
AE		 13218 if (IS_PF(bp)) {
13219 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13220 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13221 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13222 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13223
13224 if (chip_is_e1x) {
13225 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13226 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13227 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13228 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13229 }
a5c53dbc 13230
1ab4434c
AE		 13231 /* Enable internal target-read (in case we are probed after PF
13232 * FLR). Must be done prior to any BAR read access. Only for
13233 * 57712 and up
13234 */
13235 if (!chip_is_e1x)
13236 REG_WR(bp,
13237 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 13238 }
a2fbb9ea 13239
34f80b04 13240 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 13241
c64213cd 13242 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 13243 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 13244
01789349
JP		 13245 dev->priv_flags |= IFF_UNICAST_FLT;
13246
66371c44 13247 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 13248 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13249 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
f646968f 13250 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a8e0c246 13251 if (!chip_is_e1x) {
736c4c1d
AD		 13252 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13253 NETIF_F_GSO_IPXIP4 |
13254 NETIF_F_GSO_UDP_TUNNEL |
13255 NETIF_F_GSO_UDP_TUNNEL_CSUM |
13256 NETIF_F_GSO_PARTIAL;
13257
a848ade4
DK		 13258 dev->hw_enc_features =
13259 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13260 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
7e13318d 13261 NETIF_F_GSO_IPXIP4 |
736c4c1d
AD		 13262 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13263 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
13264 NETIF_F_GSO_PARTIAL;
13265
13266 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM |
13267 NETIF_F_GSO_UDP_TUNNEL_CSUM;
a848ade4 13268 }
66371c44
MM		 13269
13270 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13271 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13272
05cc5a39
YM		 13273 /* VF with OLD Hypervisor or old PF do not support filtering */
13274 if (IS_PF(bp)) {
ab6d7846 13275 if (chip_is_e1x)
05cc5a39
YM		 13276 bp->accept_any_vlan = true;
13277 else
13278 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
ce7fa78c 13279#ifdef CONFIG_BNX2X_SRIOV
05cc5a39
YM		 13280 } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
13281 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
ce7fa78c 13282#endif
05cc5a39
YM		 13283 }
13284
f646968f 13285 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 13286 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 13287
538dd2e3
MB		 13288 /* Add Loopback capability to the device */
13289 dev->hw_features |= NETIF_F_LOOPBACK;
13290
98507672 13291#ifdef BCM_DCBNL
785b9b1a
SR		 13292 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13293#endif
13294
01cd4528
EG		 13295 /* get_port_hwinfo() will set prtad and mmds properly */
13296 bp->mdio.prtad = MDIO_PRTAD_NONE;
13297 bp->mdio.mmds = 0;
13298 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13299 bp->mdio.dev = dev;
13300 bp->mdio.mdio_read = bnx2x_mdio_read;
13301 bp->mdio.mdio_write = bnx2x_mdio_write;
13302
a2fbb9ea
ET		 13303 return 0;
13304
a2fbb9ea 13305err_out_release:
34f80b04
EG		 13306 if (atomic_read(&pdev->enable_cnt) == 1)
13307 pci_release_regions(pdev);
a2fbb9ea
ET		 13308
13309err_out_disable:
13310 pci_disable_device(pdev);
a2fbb9ea
ET		 13311
13312err_out:
13313 return rc;
13314}
13315
6891dd25 13316static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 13317{
37f9ce62 13318 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 13319 struct bnx2x_fw_file_hdr *fw_hdr;
13320 struct bnx2x_fw_file_section *sections;
94a78b79 13321 u32 offset, len, num_ops;
86564c3f 13322 __be16 *ops_offsets;
94a78b79 13323 int i;
37f9ce62 13324 const u8 *fw_ver;
94a78b79 13325
51c1a580
MS		 13326 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
13327 BNX2X_ERR("Wrong FW size\n");
94a78b79 13328 return -EINVAL;
51c1a580 13329 }
94a78b79
VZ		 13330
13331 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
13332 sections = (struct bnx2x_fw_file_section *)fw_hdr;
13333
13334 /* Make sure none of the offsets and sizes make us read beyond
13335 * the end of the firmware data */
13336 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
13337 offset = be32_to_cpu(sections[i].offset);
13338 len = be32_to_cpu(sections[i].len);
13339 if (offset + len > firmware->size) {
51c1a580 13340 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 13341 return -EINVAL;
13342 }
13343 }
13344
13345 /* Likewise for the init_ops offsets */
13346 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 13347 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 13348 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
13349
13350 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
13351 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 13352 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 13353 return -EINVAL;
13354 }
13355 }
13356
13357 /* Check FW version */
13358 offset = be32_to_cpu(fw_hdr->fw_version.offset);
13359 fw_ver = firmware->data + offset;
13360 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13361 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13362 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13363 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 13364 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13365 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13366 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 13367 BCM_5710_FW_MINOR_VERSION,
13368 BCM_5710_FW_REVISION_VERSION,
13369 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 13370 return -EINVAL;
94a78b79
VZ		 13371 }
13372
13373 return 0;
13374}
13375
1191cb83 13376static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 13377{
ab6ad5a4
EG		 13378 const __be32 *source = (const __be32 *)_source;
13379 u32 *target = (u32 *)_target;
94a78b79 13380 u32 i;
94a78b79
VZ		 13381
13382 for (i = 0; i < n/4; i++)
13383 target[i] = be32_to_cpu(source[i]);
13384}
13385
13386/*
13387 Ops array is stored in the following format:
13388 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13389 */
1191cb83 13390static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 13391{
ab6ad5a4
EG		 13392 const __be32 *source = (const __be32 *)_source;
13393 struct raw_op *target = (struct raw_op *)_target;
94a78b79 13394 u32 i, j, tmp;
94a78b79 13395
ab6ad5a4 13396 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 13397 tmp = be32_to_cpu(source[j]);
13398 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 13399 target[i].offset = tmp & 0xffffff;
13400 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 13401 }
13402}
ab6ad5a4 13403
1aa8b471 13404/* IRO array is stored in the following format:
523224a3
DK		 13405 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13406 */
1191cb83 13407static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 13408{
13409 const __be32 *source = (const __be32 *)_source;
13410 struct iro *target = (struct iro *)_target;
13411 u32 i, j, tmp;
13412
13413 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13414 target[i].base = be32_to_cpu(source[j]);
13415 j++;
13416 tmp = be32_to_cpu(source[j]);
13417 target[i].m1 = (tmp >> 16) & 0xffff;
13418 target[i].m2 = tmp & 0xffff;
13419 j++;
13420 tmp = be32_to_cpu(source[j]);
13421 target[i].m3 = (tmp >> 16) & 0xffff;
13422 target[i].size = tmp & 0xffff;
13423 j++;
13424 }
13425}
13426
1191cb83 13427static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 13428{
ab6ad5a4
EG		 13429 const __be16 *source = (const __be16 *)_source;
13430 u16 *target = (u16 *)_target;
94a78b79 13431 u32 i;
94a78b79
VZ		 13432
13433 for (i = 0; i < n/2; i++)
13434 target[i] = be16_to_cpu(source[i]);
13435}
13436
7995c64e
JP		 13437#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13438do { \
13439 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13440 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 13441 if (!bp->arr) \
7995c64e 13442 goto lbl; \
7995c64e
JP		 13443 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13444 (u8 *)bp->arr, len); \
13445} while (0)
94a78b79 13446
3b603066 13447static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 13448{
c0ea452e 13449 const char *fw_file_name;
94a78b79 13450 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 13451 int rc;
94a78b79 13452
c0ea452e
MS		 13453 if (bp->firmware)
13454 return 0;
94a78b79 13455
c0ea452e
MS		 13456 if (CHIP_IS_E1(bp))
13457 fw_file_name = FW_FILE_NAME_E1;
13458 else if (CHIP_IS_E1H(bp))
13459 fw_file_name = FW_FILE_NAME_E1H;
13460 else if (!CHIP_IS_E1x(bp))
13461 fw_file_name = FW_FILE_NAME_E2;
13462 else {
13463 BNX2X_ERR("Unsupported chip revision\n");
13464 return -EINVAL;
13465 }
13466 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 13467
c0ea452e
MS		 13468 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13469 if (rc) {
13470 BNX2X_ERR("Can't load firmware file %s\n",
13471 fw_file_name);
13472 goto request_firmware_exit;
13473 }
eb2afd4a 13474
c0ea452e
MS		 13475 rc = bnx2x_check_firmware(bp);
13476 if (rc) {
13477 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13478 goto request_firmware_exit;
94a78b79
VZ		 13479 }
13480
13481 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13482
13483 /* Initialize the pointers to the init arrays */
13484 /* Blob */
13485 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13486
13487 /* Opcodes */
13488 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13489
13490 /* Offsets */
ab6ad5a4
EG		 13491 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13492 be16_to_cpu_n);
94a78b79
VZ		 13493
13494 /* STORMs firmware */
573f2035
EG		 13495 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13496 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13497 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13498 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13499 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13500 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13501 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13502 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13503 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13504 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13505 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13506 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13507 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13508 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13509 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13510 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 13511 /* IRO */
13512 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 13513
13514 return 0;
ab6ad5a4 13515
523224a3
DK		 13516iro_alloc_err:
13517 kfree(bp->init_ops_offsets);
94a78b79
VZ		 13518init_offsets_alloc_err:
13519 kfree(bp->init_ops);
13520init_ops_alloc_err:
13521 kfree(bp->init_data);
13522request_firmware_exit:
13523 release_firmware(bp->firmware);
127d0a19 13524 bp->firmware = NULL;
94a78b79
VZ		 13525
13526 return rc;
13527}
13528
619c5cb6
VZ		 13529static void bnx2x_release_firmware(struct bnx2x *bp)
13530{
13531 kfree(bp->init_ops_offsets);
13532 kfree(bp->init_ops);
13533 kfree(bp->init_data);
13534 release_firmware(bp->firmware);
eb2afd4a 13535 bp->firmware = NULL;
619c5cb6
VZ		 13536}
13537
619c5cb6
VZ		 13538static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13539 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13540 .init_hw_cmn = bnx2x_init_hw_common,
13541 .init_hw_port = bnx2x_init_hw_port,
13542 .init_hw_func = bnx2x_init_hw_func,
13543
13544 .reset_hw_cmn = bnx2x_reset_common,
13545 .reset_hw_port = bnx2x_reset_port,
13546 .reset_hw_func = bnx2x_reset_func,
13547
13548 .gunzip_init = bnx2x_gunzip_init,
13549 .gunzip_end = bnx2x_gunzip_end,
13550
13551 .init_fw = bnx2x_init_firmware,
13552 .release_fw = bnx2x_release_firmware,
13553};
13554
13555void bnx2x__init_func_obj(struct bnx2x *bp)
13556{
13557 /* Prepare DMAE related driver resources */
13558 bnx2x_setup_dmae(bp);
13559
13560 bnx2x_init_func_obj(bp, &bp->func_obj,
13561 bnx2x_sp(bp, func_rdata),
13562 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 13563 bnx2x_sp(bp, func_afex_rdata),
13564 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 13565 &bnx2x_func_sp_drv);
13566}
13567
13568/* must be called after sriov-enable */
1191cb83 13569static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 13570{
37ae41a9 13571 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 13572
290ca2bb
AE		 13573 if (IS_SRIOV(bp))
13574 cid_count += BNX2X_VF_CIDS;
13575
55c11941
MS		 13576 if (CNIC_SUPPORT(bp))
13577 cid_count += CNIC_CID_MAX;
290ca2bb 13578
523224a3
DK		 13579 return roundup(cid_count, QM_CID_ROUND);
13580}
f85582f8 13581
619c5cb6 13582/**
6383c0b3 13583 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 13584 *
13585 * @dev: pci device
13586 *
13587 */
60cad4e6 13588static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 13589{
ae2104be 13590 int index;
1ab4434c 13591 u16 control = 0;
619c5cb6 13592
6383c0b3
AE		 13593 /*
13594 * If MSI-X is not supported - return number of SBs needed to support
13595 * one fast path queue: one FP queue + SB for CNIC
13596 */
ae2104be 13597 if (!pdev->msix_cap) {
1ab4434c 13598 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 13599 return 1 + cnic_cnt;
1ab4434c
AE		 13600 }
13601 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 13602
6383c0b3
AE		 13603 /*
13604 * The value in the PCI configuration space is the index of the last
13605 * entry, namely one less than the actual size of the table, which is
13606 * exactly what we want to return from this function: number of all SBs
13607 * without the default SB.
1ab4434c 13608 * For VFs there is no default SB, then we return (index+1).
6383c0b3 13609 */
73413ffa 13610 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
619c5cb6 13611
1ab4434c 13612 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 13613
60cad4e6 13614 return index;
1ab4434c 13615}
523224a3 13616
1ab4434c
AE		 13617static int set_max_cos_est(int chip_id)
13618{
13619 switch (chip_id) {
f2e0899f
DK		 13620 case BCM57710:
13621 case BCM57711:
13622 case BCM57711E:
1ab4434c 13623 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 13624 case BCM57712:
619c5cb6 13625 case BCM57712_MF:
1ab4434c 13626 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 13627 case BCM57800:
13628 case BCM57800_MF:
13629 case BCM57810:
13630 case BCM57810_MF:
c3def943
YM		 13631 case BCM57840_4_10:
13632 case BCM57840_2_20:
1ab4434c 13633 case BCM57840_O:
c3def943 13634 case BCM57840_MFO:
619c5cb6 13635 case BCM57840_MF:
7e8e02df
BW		 13636 case BCM57811:
13637 case BCM57811_MF:
1ab4434c 13638 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 13639 case BCM57712_VF:
13640 case BCM57800_VF:
13641 case BCM57810_VF:
13642 case BCM57840_VF:
13643 case BCM57811_VF:
1ab4434c 13644 return 1;
f2e0899f 13645 default:
1ab4434c 13646 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 13647 return -ENODEV;
f2e0899f 13648 }
1ab4434c 13649}
f2e0899f 13650
1ab4434c
AE		 13651static int set_is_vf(int chip_id)
13652{
13653 switch (chip_id) {
13654 case BCM57712_VF:
13655 case BCM57800_VF:
13656 case BCM57810_VF:
13657 case BCM57840_VF:
13658 case BCM57811_VF:
13659 return true;
13660 default:
13661 return false;
13662 }
13663}
6383c0b3 13664
eeed018c
MK		 13665/* nig_tsgen registers relative address */
13666#define tsgen_ctrl 0x0
13667#define tsgen_freecount 0x10
13668#define tsgen_synctime_t0 0x20
13669#define tsgen_offset_t0 0x28
13670#define tsgen_drift_t0 0x30
13671#define tsgen_synctime_t1 0x58
13672#define tsgen_offset_t1 0x60
13673#define tsgen_drift_t1 0x68
13674
13675/* FW workaround for setting drift */
13676static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13677 int best_val, int best_period)
13678{
13679 struct bnx2x_func_state_params func_params = {NULL};
13680 struct bnx2x_func_set_timesync_params *set_timesync_params =
13681 &func_params.params.set_timesync;
13682
13683 /* Prepare parameters for function state transitions */
13684 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13685 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13686
13687 func_params.f_obj = &bp->func_obj;
13688 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13689
13690 /* Function parameters */
13691 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13692 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13693 set_timesync_params->add_sub_drift_adjust_value =
13694 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13695 set_timesync_params->drift_adjust_value = best_val;
13696 set_timesync_params->drift_adjust_period = best_period;
13697
13698 return bnx2x_func_state_change(bp, &func_params);
13699}
13700
13701static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13702{
13703 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13704 int rc;
13705 int drift_dir = 1;
13706 int val, period, period1, period2, dif, dif1, dif2;
13707 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13708
13709 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13710
13711 if (!netif_running(bp->dev)) {
13712 DP(BNX2X_MSG_PTP,
13713 "PTP adjfreq called while the interface is down\n");
13714 return -EFAULT;
13715 }
13716
13717 if (ppb < 0) {
13718 ppb = -ppb;
13719 drift_dir = 0;
13720 }
13721
13722 if (ppb == 0) {
13723 best_val = 1;
13724 best_period = 0x1FFFFFF;
13725 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13726 best_val = 31;
13727 best_period = 1;
13728 } else {
13729 /* Changed not to allow val = 8, 16, 24 as these values
13730 * are not supported in workaround.
13731 */
13732 for (val = 0; val <= 31; val++) {
13733 if ((val & 0x7) == 0)
13734 continue;
13735 period1 = val * 1000000 / ppb;
13736 period2 = period1 + 1;
13737 if (period1 != 0)
13738 dif1 = ppb - (val * 1000000 / period1);
13739 else
13740 dif1 = BNX2X_MAX_PHC_DRIFT;
13741 if (dif1 < 0)
13742 dif1 = -dif1;
13743 dif2 = ppb - (val * 1000000 / period2);
13744 if (dif2 < 0)
13745 dif2 = -dif2;
13746 dif = (dif1 < dif2) ? dif1 : dif2;
13747 period = (dif1 < dif2) ? period1 : period2;
13748 if (dif < best_dif) {
13749 best_dif = dif;
13750 best_val = val;
13751 best_period = period;
13752 }
13753 }
13754 }
13755
13756 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13757 best_period);
13758 if (rc) {
13759 BNX2X_ERR("Failed to set drift\n");
13760 return -EFAULT;
13761 }
13762
bf27c353 13763 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
eeed018c
MK		 13764 best_period);
13765
13766 return 0;
13767}
13768
13769static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13770{
13771 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
eeed018c
MK		 13772
13773 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13774
2e5601f9 13775 timecounter_adjtime(&bp->timecounter, delta);
eeed018c
MK		 13776
13777 return 0;
13778}
13779
5d45186b 13780static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
eeed018c
MK		 13781{
13782 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13783 u64 ns;
eeed018c
MK		 13784
13785 ns = timecounter_read(&bp->timecounter);
13786
13787 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13788
f7dcdefe 13789 *ts = ns_to_timespec64(ns);
eeed018c
MK		 13790
13791 return 0;
13792}
13793
13794static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
5d45186b 13795 const struct timespec64 *ts)
eeed018c
MK		 13796{
13797 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13798 u64 ns;
13799
f7dcdefe 13800 ns = timespec64_to_ns(ts);
eeed018c
MK		 13801
13802 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13803
13804 /* Re-init the timecounter */
13805 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13806
13807 return 0;
13808}
13809
13810/* Enable (or disable) ancillary features of the phc subsystem */
13811static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13812 struct ptp_clock_request *rq, int on)
13813{
13814 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13815
13816 BNX2X_ERR("PHC ancillary features are not supported\n");
13817 return -ENOTSUPP;
13818}
13819
1444c301 13820static void bnx2x_register_phc(struct bnx2x *bp)
eeed018c
MK		 13821{
13822 /* Fill the ptp_clock_info struct and register PTP clock*/
13823 bp->ptp_clock_info.owner = THIS_MODULE;
13824 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13825 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13826 bp->ptp_clock_info.n_alarm = 0;
13827 bp->ptp_clock_info.n_ext_ts = 0;
13828 bp->ptp_clock_info.n_per_out = 0;
13829 bp->ptp_clock_info.pps = 0;
13830 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13831 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
5d45186b
RC		 13832 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13833 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
eeed018c
MK		 13834 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13835
13836 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13837 if (IS_ERR(bp->ptp_clock)) {
13838 bp->ptp_clock = NULL;
13839 BNX2X_ERR("PTP clock registeration failed\n");
13840 }
13841}
13842
1ab4434c
AE		 13843static int bnx2x_init_one(struct pci_dev *pdev,
13844 const struct pci_device_id *ent)
13845{
13846 struct net_device *dev = NULL;
13847 struct bnx2x *bp;
b91e1a1a
YM		 13848 enum pcie_link_width pcie_width;
13849 enum pci_bus_speed pcie_speed;
1ab4434c
AE		 13850 int rc, max_non_def_sbs;
13851 int rx_count, tx_count, rss_count, doorbell_size;
13852 int max_cos_est;
13853 bool is_vf;
13854 int cnic_cnt;
13855
12a8541d
YM		 13856 /* Management FW 'remembers' living interfaces. Allow it some time
13857 * to forget previously living interfaces, allowing a proper re-load.
13858 */
cd9c3997
MS		 13859 if (is_kdump_kernel()) {
13860 ktime_t now = ktime_get_boottime();
13861 ktime_t fw_ready_time = ktime_set(5, 0);
13862
13863 if (ktime_before(now, fw_ready_time))
13864 msleep(ktime_ms_delta(fw_ready_time, now));
13865 }
12a8541d 13866
1ab4434c
AE		 13867 /* An estimated maximum supported CoS number according to the chip
13868 * version.
13869 * We will try to roughly estimate the maximum number of CoSes this chip
13870 * may support in order to minimize the memory allocated for Tx
13871 * netdev_queue's. This number will be accurately calculated during the
13872 * initialization of bp->max_cos based on the chip versions AND chip
13873 * revision in the bnx2x_init_bp().
13874 */
13875 max_cos_est = set_max_cos_est(ent->driver_data);
13876 if (max_cos_est < 0)
13877 return max_cos_est;
13878 is_vf = set_is_vf(ent->driver_data);
13879 cnic_cnt = is_vf ? 0 : 1;
13880
60cad4e6
AE		 13881 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13882
13883 /* add another SB for VF as it has no default SB */
13884 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 13885
13886 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 13887 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 13888
13889 if (rss_count < 1)
13890 return -EINVAL;
6383c0b3
AE		 13891
13892 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 13893 rx_count = rss_count + cnic_cnt;
6383c0b3 13894
1ab4434c 13895 /* Maximum number of netdev Tx queues:
37ae41a9 13896 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 13897 */
55c11941 13898 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 13899
a2fbb9ea 13900 /* dev zeroed in init_etherdev */
6383c0b3 13901 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 13902 if (!dev)
a2fbb9ea
ET		 13903 return -ENOMEM;
13904
a2fbb9ea 13905 bp = netdev_priv(dev);
a2fbb9ea 13906
1ab4434c
AE		 13907 bp->flags = 0;
13908 if (is_vf)
13909 bp->flags |= IS_VF_FLAG;
13910
6383c0b3 13911 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 13912 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 13913 bp->msg_enable = debug;
55c11941 13914 bp->cnic_support = cnic_cnt;
4bd9b0ff 13915 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 13916
6383c0b3 13917 pci_set_drvdata(pdev, dev);
523224a3 13918
1ab4434c 13919 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 13920 if (rc < 0) {
13921 free_netdev(dev);
13922 return rc;
13923 }
13924
1ab4434c
AE		 13925 BNX2X_DEV_INFO("This is a %s function\n",
13926 IS_PF(bp) ? "physical" : "virtual");
55c11941 13927 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 13928 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 13929 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 13930 tx_count, rx_count);
60aa0509 13931
34f80b04 13932 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 13933 if (rc)
13934 goto init_one_exit;
13935
1ab4434c
AE		 13936 /* Map doorbells here as we need the real value of bp->max_cos which
13937 * is initialized in bnx2x_init_bp() to determine the number of
13938 * l2 connections.
6383c0b3 13939 */
1ab4434c 13940 if (IS_VF(bp)) {
1d6f3cd8 13941 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 13942 rc = bnx2x_vf_pci_alloc(bp);
13943 if (rc)
bae5499c 13944 goto init_one_freemem;
1ab4434c
AE		 13945 } else {
13946 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13947 if (doorbell_size > pci_resource_len(pdev, 2)) {
13948 dev_err(&bp->pdev->dev,
13949 "Cannot map doorbells, bar size too small, aborting\n");
13950 rc = -ENOMEM;
bae5499c 13951 goto init_one_freemem;
1ab4434c
AE		 13952 }
13953 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13954 doorbell_size);
37ae41a9 13955 }
6383c0b3
AE		 13956 if (!bp->doorbells) {
13957 dev_err(&bp->pdev->dev,
13958 "Cannot map doorbell space, aborting\n");
13959 rc = -ENOMEM;
bae5499c 13960 goto init_one_freemem;
6383c0b3
AE		 13961 }
13962
be1f1ffa
AE		 13963 if (IS_VF(bp)) {
13964 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13965 if (rc)
bae5499c 13966 goto init_one_freemem;
be1f1ffa
AE		 13967 }
13968
3c76feff
AE		 13969 /* Enable SRIOV if capability found in configuration space */
13970 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb 13971 if (rc)
bae5499c 13972 goto init_one_freemem;
290ca2bb 13973
523224a3 13974 /* calc qm_cid_count */
6383c0b3 13975 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 13976 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 13977
55c11941 13978 /* disable FCOE L2 queue for E1x*/
62ac0dc9 13979 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 13980 bp->flags |= NO_FCOE_FLAG;
13981
0e8d2ec5
MS		 13982 /* Set bp->num_queues for MSI-X mode*/
13983 bnx2x_set_num_queues(bp);
13984
25985edc 13985 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 13986 * needed.
d6214d7a 13987 */
1ab4434c
AE		 13988 rc = bnx2x_set_int_mode(bp);
13989 if (rc) {
13990 dev_err(&pdev->dev, "Cannot set interrupts\n");
bae5499c 13991 goto init_one_freemem;
1ab4434c 13992 }
04c46736 13993 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 13994
1ab4434c 13995 /* register the net device */
b340007f
VZ		 13996 rc = register_netdev(dev);
13997 if (rc) {
13998 dev_err(&pdev->dev, "Cannot register net device\n");
bae5499c 13999 goto init_one_freemem;
b340007f 14000 }
1ab4434c 14001 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 14002
ec6ba945
VZ		 14003 if (!NO_FCOE(bp)) {
14004 /* Add storage MAC address */
14005 rtnl_lock();
14006 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14007 rtnl_unlock();
14008 }
b91e1a1a
YM		 14009 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
14010 pcie_speed == PCI_SPEED_UNKNOWN ||
14011 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
14012 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
14013 else
14014 BNX2X_DEV_INFO(
14015 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
ca1ee4b2
DK		 14016 board_info[ent->driver_data].name,
14017 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
14018 pcie_width,
b91e1a1a
YM		 14019 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
14020 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
14021 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
ca1ee4b2
DK		 14022 "Unknown",
14023 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 14024
eeed018c
MK		 14025 bnx2x_register_phc(bp);
14026
230d00eb
YM		 14027 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
14028 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
14029
a2fbb9ea 14030 return 0;
34f80b04 14031
bae5499c
VK		 14032init_one_freemem:
14033 bnx2x_free_mem_bp(bp);
14034
34f80b04 14035init_one_exit:
33d8e6a5
YM		 14036 bnx2x_disable_pcie_error_reporting(bp);
14037
34f80b04
EG		 14038 if (bp->regview)
14039 iounmap(bp->regview);
14040
1ab4434c 14041 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 14042 iounmap(bp->doorbells);
14043
14044 free_netdev(dev);
14045
14046 if (atomic_read(&pdev->enable_cnt) == 1)
14047 pci_release_regions(pdev);
14048
14049 pci_disable_device(pdev);
34f80b04
EG		 14050
14051 return rc;
a2fbb9ea
ET		 14052}
14053
b030ed2f
YM		 14054static void __bnx2x_remove(struct pci_dev *pdev,
14055 struct net_device *dev,
14056 struct bnx2x *bp,
14057 bool remove_netdev)
a2fbb9ea 14058{
eeed018c
MK		 14059 if (bp->ptp_clock) {
14060 ptp_clock_unregister(bp->ptp_clock);
14061 bp->ptp_clock = NULL;
14062 }
14063
ec6ba945
VZ		 14064 /* Delete storage MAC address */
14065 if (!NO_FCOE(bp)) {
14066 rtnl_lock();
14067 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14068 rtnl_unlock();
14069 }
ec6ba945 14070
98507672
SR		 14071#ifdef BCM_DCBNL
14072 /* Delete app tlvs from dcbnl */
14073 bnx2x_dcbnl_update_applist(bp, true);
14074#endif
14075
a6d3a5ba
BW		 14076 if (IS_PF(bp) &&
14077 !BP_NOMCP(bp) &&
14078 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14079 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14080
b030ed2f
YM		 14081 /* Close the interface - either directly or implicitly */
14082 if (remove_netdev) {
14083 unregister_netdev(dev);
14084 } else {
14085 rtnl_lock();
6ef5a92c 14086 dev_close(dev);
b030ed2f
YM		 14087 rtnl_unlock();
14088 }
a2fbb9ea 14089
78c3bcc5
AE		 14090 bnx2x_iov_remove_one(bp);
14091
084d6cbb 14092 /* Power on: we can't let PCI layer write to us while we are in D3 */
04860eb7 14093 if (IS_PF(bp)) {
1ab4434c 14094 bnx2x_set_power_state(bp, PCI_D0);
230d00eb 14095 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
084d6cbb 14096
04860eb7
MC		 14097 /* Set endianity registers to reset values in case next driver
14098 * boots in different endianty environment.
14099 */
14100 bnx2x_reset_endianity(bp);
14101 }
14102
d6214d7a
DK		 14103 /* Disable MSI/MSI-X */
14104 bnx2x_disable_msi(bp);
f85582f8 14105
084d6cbb 14106 /* Power off */
1ab4434c
AE		 14107 if (IS_PF(bp))
14108 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 14109
72fd0718 14110 /* Make sure RESET task is not scheduled before continuing */
7be08a72 14111 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 14112
4513f925
AE		 14113 /* send message via vfpf channel to release the resources of this vf */
14114 if (IS_VF(bp))
14115 bnx2x_vfpf_release(bp);
72fd0718 14116
b030ed2f
YM		 14117 /* Assumes no further PCIe PM changes will occur */
14118 if (system_state == SYSTEM_POWER_OFF) {
14119 pci_wake_from_d3(pdev, bp->wol);
14120 pci_set_power_state(pdev, PCI_D3hot);
14121 }
14122
33d8e6a5 14123 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 14124 if (remove_netdev) {
14125 if (bp->regview)
14126 iounmap(bp->regview);
33d8e6a5 14127
d9aee591
YM		 14128 /* For vfs, doorbells are part of the regview and were unmapped
14129 * along with it. FW is only loaded by PF.
14130 */
14131 if (IS_PF(bp)) {
14132 if (bp->doorbells)
14133 iounmap(bp->doorbells);
eb2afd4a 14134
d9aee591 14135 bnx2x_release_firmware(bp);
e2a367f8
YM		 14136 } else {
14137 bnx2x_vf_pci_dealloc(bp);
d9aee591
YM		 14138 }
14139 bnx2x_free_mem_bp(bp);
523224a3 14140
b030ed2f 14141 free_netdev(dev);
34f80b04 14142
d9aee591
YM		 14143 if (atomic_read(&pdev->enable_cnt) == 1)
14144 pci_release_regions(pdev);
34f80b04 14145
5f6db130
YM		 14146 pci_disable_device(pdev);
14147 }
a2fbb9ea
ET		 14148}
14149
b030ed2f
YM		 14150static void bnx2x_remove_one(struct pci_dev *pdev)
14151{
14152 struct net_device *dev = pci_get_drvdata(pdev);
14153 struct bnx2x *bp;
14154
14155 if (!dev) {
14156 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14157 return;
14158 }
14159 bp = netdev_priv(dev);
14160
14161 __bnx2x_remove(pdev, dev, bp, true);
14162}
14163
f8ef6e44
YG		 14164static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14165{
7fa6f340 14166 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 14167
14168 bp->rx_mode = BNX2X_RX_MODE_NONE;
14169
55c11941
MS		 14170 if (CNIC_LOADED(bp))
14171 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14172
619c5cb6
VZ		 14173 /* Stop Tx */
14174 bnx2x_tx_disable(bp);
26614ba5
MS		 14175 /* Delete all NAPI objects */
14176 bnx2x_del_all_napi(bp);
55c11941
MS		 14177 if (CNIC_LOADED(bp))
14178 bnx2x_del_all_napi_cnic(bp);
7fa6f340 14179 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 14180
14181 del_timer_sync(&bp->timer);
0c0e6341 14182 cancel_delayed_work_sync(&bp->sp_task);
14183 cancel_delayed_work_sync(&bp->period_task);
619c5cb6 14184
c6e36d8c
YM		 14185 if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14186 bp->stats_state = STATS_STATE_DISABLED;
14187 up(&bp->stats_lock);
14188 }
f8ef6e44 14189
7fa6f340 14190 bnx2x_save_statistics(bp);
f8ef6e44 14191
619c5cb6
VZ		 14192 netif_carrier_off(bp->dev);
14193
f8ef6e44
YG		 14194 return 0;
14195}
14196
493adb1f
WX		 14197/**
14198 * bnx2x_io_error_detected - called when PCI error is detected
14199 * @pdev: Pointer to PCI device
14200 * @state: The current pci connection state
14201 *
14202 * This function is called after a PCI bus error affecting
14203 * this device has been detected.
14204 */
14205static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14206 pci_channel_state_t state)
14207{
14208 struct net_device *dev = pci_get_drvdata(pdev);
14209 struct bnx2x *bp = netdev_priv(dev);
14210
14211 rtnl_lock();
14212
7fa6f340
YM		 14213 BNX2X_ERR("IO error detected\n");
14214
493adb1f
WX		 14215 netif_device_detach(dev);
14216
07ce50e4
DN		 14217 if (state == pci_channel_io_perm_failure) {
14218 rtnl_unlock();
14219 return PCI_ERS_RESULT_DISCONNECT;
14220 }
14221
493adb1f 14222 if (netif_running(dev))
f8ef6e44 14223 bnx2x_eeh_nic_unload(bp);
493adb1f 14224
7fa6f340
YM		 14225 bnx2x_prev_path_mark_eeh(bp);
14226
493adb1f
WX		 14227 pci_disable_device(pdev);
14228
14229 rtnl_unlock();
14230
14231 /* Request a slot reset */
14232 return PCI_ERS_RESULT_NEED_RESET;
14233}
14234
14235/**
14236 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14237 * @pdev: Pointer to PCI device
14238 *
14239 * Restart the card from scratch, as if from a cold-boot.
14240 */
14241static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14242{
14243 struct net_device *dev = pci_get_drvdata(pdev);
14244 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 14245 int i;
493adb1f
WX		 14246
14247 rtnl_lock();
7fa6f340 14248 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 14249 if (pci_enable_device(pdev)) {
14250 dev_err(&pdev->dev,
14251 "Cannot re-enable PCI device after reset\n");
14252 rtnl_unlock();
14253 return PCI_ERS_RESULT_DISCONNECT;
14254 }
14255
14256 pci_set_master(pdev);
14257 pci_restore_state(pdev);
70632d0a 14258 pci_save_state(pdev);
493adb1f
WX		 14259
14260 if (netif_running(dev))
14261 bnx2x_set_power_state(bp, PCI_D0);
14262
7fa6f340
YM		 14263 if (netif_running(dev)) {
14264 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 14265
14266 /* MCP should have been reset; Need to wait for validity */
14267 bnx2x_init_shmem(bp);
14268
7fa6f340
YM		 14269 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14270 u32 v;
14271
14272 v = SHMEM2_RD(bp,
14273 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14274 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14275 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14276 }
14277 bnx2x_drain_tx_queues(bp);
14278 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14279 bnx2x_netif_stop(bp, 1);
14280 bnx2x_free_irq(bp);
14281
14282 /* Report UNLOAD_DONE to MCP */
14283 bnx2x_send_unload_done(bp, true);
14284
14285 bp->sp_state = 0;
14286 bp->port.pmf = 0;
14287
14288 bnx2x_prev_unload(bp);
14289
16a5fd92 14290 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 14291 * assume the FW will no longer write to the bnx2x driver.
14292 */
14293 bnx2x_squeeze_objects(bp);
14294 bnx2x_free_skbs(bp);
14295 for_each_rx_queue(bp, i)
14296 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14297 bnx2x_free_fp_mem(bp);
14298 bnx2x_free_mem(bp);
14299
14300 bp->state = BNX2X_STATE_CLOSED;
14301 }
14302
493adb1f
WX		 14303 rtnl_unlock();
14304
33d8e6a5
YM		 14305 /* If AER, perform cleanup of the PCIe registers */
14306 if (bp->flags & AER_ENABLED) {
14307 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14308 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14309 else
14310 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14311 }
14312
493adb1f
WX		 14313 return PCI_ERS_RESULT_RECOVERED;
14314}
14315
14316/**
14317 * bnx2x_io_resume - called when traffic can start flowing again
14318 * @pdev: Pointer to PCI device
14319 *
14320 * This callback is called when the error recovery driver tells us that
14321 * its OK to resume normal operation.
14322 */
14323static void bnx2x_io_resume(struct pci_dev *pdev)
14324{
14325 struct net_device *dev = pci_get_drvdata(pdev);
14326 struct bnx2x *bp = netdev_priv(dev);
14327
72fd0718 14328 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 14329 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 14330 return;
14331 }
14332
493adb1f
WX		 14333 rtnl_lock();
14334
7fa6f340
YM		 14335 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14336 DRV_MSG_SEQ_NUMBER_MASK;
14337
493adb1f 14338 if (netif_running(dev))
f8ef6e44 14339 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 14340
14341 netif_device_attach(dev);
14342
14343 rtnl_unlock();
14344}
14345
3646f0e5 14346static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 14347 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 14348 .slot_reset = bnx2x_io_slot_reset,
14349 .resume = bnx2x_io_resume,
493adb1f
WX		 14350};
14351
b030ed2f
YM		 14352static void bnx2x_shutdown(struct pci_dev *pdev)
14353{
14354 struct net_device *dev = pci_get_drvdata(pdev);
14355 struct bnx2x *bp;
14356
14357 if (!dev)
14358 return;
14359
14360 bp = netdev_priv(dev);
14361 if (!bp)
14362 return;
14363
14364 rtnl_lock();
14365 netif_device_detach(dev);
14366 rtnl_unlock();
14367
14368 /* Don't remove the netdevice, as there are scenarios which will cause
14369 * the kernel to hang, e.g., when trying to remove bnx2i while the
14370 * rootfs is mounted from SAN.
14371 */
14372 __bnx2x_remove(pdev, dev, bp, false);
14373}
14374
a2fbb9ea 14375static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 14376 .name = DRV_MODULE_NAME,
14377 .id_table = bnx2x_pci_tbl,
14378 .probe = bnx2x_init_one,
0329aba1 14379 .remove = bnx2x_remove_one,
493adb1f
WX		 14380 .suspend = bnx2x_suspend,
14381 .resume = bnx2x_resume,
14382 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 14383#ifdef CONFIG_BNX2X_SRIOV
14384 .sriov_configure = bnx2x_sriov_configure,
14385#endif
b030ed2f 14386 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 14387};
14388
14389static int __init bnx2x_init(void)
14390{
dd21ca6d
SG		 14391 int ret;
14392
7995c64e 14393 pr_info("%s", version);
938cf541 14394
1cf167f2
EG		 14395 bnx2x_wq = create_singlethread_workqueue("bnx2x");
14396 if (bnx2x_wq == NULL) {
7995c64e 14397 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 14398 return -ENOMEM;
14399 }
370d4a26
YM		 14400 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14401 if (!bnx2x_iov_wq) {
14402 pr_err("Cannot create iov workqueue\n");
14403 destroy_workqueue(bnx2x_wq);
14404 return -ENOMEM;
14405 }
1cf167f2 14406
dd21ca6d
SG		 14407 ret = pci_register_driver(&bnx2x_pci_driver);
14408 if (ret) {
7995c64e 14409 pr_err("Cannot register driver\n");
dd21ca6d 14410 destroy_workqueue(bnx2x_wq);
370d4a26 14411 destroy_workqueue(bnx2x_iov_wq);
dd21ca6d
SG		 14412 }
14413 return ret;
a2fbb9ea
ET		 14414}
14415
14416static void __exit bnx2x_cleanup(void)
14417{
452427b0 14418 struct list_head *pos, *q;
d76a6111 14419
a2fbb9ea 14420 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 14421
14422 destroy_workqueue(bnx2x_wq);
370d4a26 14423 destroy_workqueue(bnx2x_iov_wq);
452427b0 14424
16a5fd92 14425 /* Free globally allocated resources */
452427b0
YM		 14426 list_for_each_safe(pos, q, &bnx2x_prev_list) {
14427 struct bnx2x_prev_path_list *tmp =
14428 list_entry(pos, struct bnx2x_prev_path_list, list);
14429 list_del(pos);
14430 kfree(tmp);
14431 }
a2fbb9ea
ET		 14432}
14433
3deb8167
YR		 14434void bnx2x_notify_link_changed(struct bnx2x *bp)
14435{
14436 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14437}
14438
a2fbb9ea
ET		 14439module_init(bnx2x_init);
14440module_exit(bnx2x_cleanup);
14441
619c5cb6
VZ		 14442/**
14443 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14444 *
14445 * @bp: driver handle
14446 * @set: set or clear the CAM entry
14447 *
16a5fd92 14448 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 14449 * Return 0 if success, -ENODEV if ramrod doesn't return.
14450 */
1191cb83 14451static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 14452{
14453 unsigned long ramrod_flags = 0;
14454
14455 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14456 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14457 &bp->iscsi_l2_mac_obj, true,
14458 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14459}
993ac7b5
MC		 14460
14461/* count denotes the number of new completions we have seen */
14462static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14463{
14464 struct eth_spe *spe;
a052997e 14465 int cxt_index, cxt_offset;
993ac7b5
MC		 14466
14467#ifdef BNX2X_STOP_ON_ERROR
14468 if (unlikely(bp->panic))
14469 return;
14470#endif
14471
14472 spin_lock_bh(&bp->spq_lock);
c2bff63f 14473 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 14474 bp->cnic_spq_pending -= count;
14475
c2bff63f
DK		 14476 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14477 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14478 & SPE_HDR_CONN_TYPE) >>
14479 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 14480 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14481 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 14482
14483 /* Set validation for iSCSI L2 client before sending SETUP
14484 * ramrod
14485 */
14486 if (type == ETH_CONNECTION_TYPE) {
a052997e 14487 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 14488 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 14489 ILT_PAGE_CIDS;
37ae41a9 14490 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 14491 (cxt_index * ILT_PAGE_CIDS);
14492 bnx2x_set_ctx_validation(bp,
14493 &bp->context[cxt_index].
14494 vcxt[cxt_offset].eth,
37ae41a9 14495 BNX2X_ISCSI_ETH_CID(bp));
a052997e 14496 }
c2bff63f
DK		 14497 }
14498
619c5cb6
VZ		 14499 /*
14500 * There may be not more than 8 L2, not more than 8 L5 SPEs
14501 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 14502 * COMMON ramrods is not more than the EQ and SPQ can
14503 * accommodate.
c2bff63f 14504 */
6e30dd4e
VZ		 14505 if (type == ETH_CONNECTION_TYPE) {
14506 if (!atomic_read(&bp->cq_spq_left))
14507 break;
14508 else
14509 atomic_dec(&bp->cq_spq_left);
14510 } else if (type == NONE_CONNECTION_TYPE) {
14511 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 14512 break;
14513 else
6e30dd4e 14514 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 14515 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14516 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 14517 if (bp->cnic_spq_pending >=
14518 bp->cnic_eth_dev.max_kwqe_pending)
14519 break;
14520 else
14521 bp->cnic_spq_pending++;
14522 } else {
14523 BNX2X_ERR("Unknown SPE type: %d\n", type);
14524 bnx2x_panic();
993ac7b5 14525 break;
c2bff63f 14526 }
993ac7b5
MC		 14527
14528 spe = bnx2x_sp_get_next(bp);
14529 *spe = *bp->cnic_kwq_cons;
14530
51c1a580 14531 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 14532 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14533
14534 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14535 bp->cnic_kwq_cons = bp->cnic_kwq;
14536 else
14537 bp->cnic_kwq_cons++;
14538 }
14539 bnx2x_sp_prod_update(bp);
14540 spin_unlock_bh(&bp->spq_lock);
14541}
14542
14543static int bnx2x_cnic_sp_queue(struct net_device *dev,
14544 struct kwqe_16 *kwqes[], u32 count)
14545{
14546 struct bnx2x *bp = netdev_priv(dev);
14547 int i;
14548
14549#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 14550 if (unlikely(bp->panic)) {
14551 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 14552 return -EIO;
51c1a580 14553 }
993ac7b5
MC		 14554#endif
14555
95c6c616
AE		 14556 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14557 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 14558 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 14559 return -EAGAIN;
14560 }
14561
993ac7b5
MC		 14562 spin_lock_bh(&bp->spq_lock);
14563
14564 for (i = 0; i < count; i++) {
14565 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14566
14567 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14568 break;
14569
14570 *bp->cnic_kwq_prod = *spe;
14571
14572 bp->cnic_kwq_pending++;
14573
51c1a580 14574 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 14575 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 14576 spe->data.update_data_addr.hi,
14577 spe->data.update_data_addr.lo,
993ac7b5
MC		 14578 bp->cnic_kwq_pending);
14579
14580 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14581 bp->cnic_kwq_prod = bp->cnic_kwq;
14582 else
14583 bp->cnic_kwq_prod++;
14584 }
14585
14586 spin_unlock_bh(&bp->spq_lock);
14587
14588 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14589 bnx2x_cnic_sp_post(bp, 0);
14590
14591 return i;
14592}
14593
14594static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14595{
14596 struct cnic_ops *c_ops;
14597 int rc = 0;
14598
14599 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 14600 c_ops = rcu_dereference_protected(bp->cnic_ops,
14601 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 14602 if (c_ops)
14603 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14604 mutex_unlock(&bp->cnic_mutex);
14605
14606 return rc;
14607}
14608
14609static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14610{
14611 struct cnic_ops *c_ops;
14612 int rc = 0;
14613
14614 rcu_read_lock();
14615 c_ops = rcu_dereference(bp->cnic_ops);
14616 if (c_ops)
14617 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14618 rcu_read_unlock();
14619
14620 return rc;
14621}
14622
14623/*
14624 * for commands that have no data
14625 */
9f6c9258 14626int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 14627{
14628 struct cnic_ctl_info ctl = {0};
14629
14630 ctl.cmd = cmd;
14631
14632 return bnx2x_cnic_ctl_send(bp, &ctl);
14633}
14634
619c5cb6 14635static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 14636{
619c5cb6 14637 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 14638
14639 /* first we tell CNIC and only then we count this as a completion */
14640 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14641 ctl.data.comp.cid = cid;
619c5cb6 14642 ctl.data.comp.error = err;
993ac7b5
MC		 14643
14644 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 14645 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 14646}
14647
619c5cb6
VZ		 14648/* Called with netif_addr_lock_bh() taken.
14649 * Sets an rx_mode config for an iSCSI ETH client.
14650 * Doesn't block.
14651 * Completion should be checked outside.
14652 */
14653static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14654{
14655 unsigned long accept_flags = 0, ramrod_flags = 0;
14656 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14657 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14658
14659 if (start) {
14660 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14661 * because it's the only way for UIO Queue to accept
14662 * multicasts (in non-promiscuous mode only one Queue per
14663 * function will receive multicast packets (leading in our
14664 * case).
14665 */
14666 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14667 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14668 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14669 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14670
14671 /* Clear STOP_PENDING bit if START is requested */
14672 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14673
14674 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14675 } else
14676 /* Clear START_PENDING bit if STOP is requested */
14677 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14678
14679 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14680 set_bit(sched_state, &bp->sp_state);
14681 else {
14682 __set_bit(RAMROD_RX, &ramrod_flags);
14683 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14684 ramrod_flags);
14685 }
14686}
14687
993ac7b5
MC		 14688static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14689{
14690 struct bnx2x *bp = netdev_priv(dev);
14691 int rc = 0;
14692
14693 switch (ctl->cmd) {
14694 case DRV_CTL_CTXTBL_WR_CMD: {
14695 u32 index = ctl->data.io.offset;
14696 dma_addr_t addr = ctl->data.io.dma_addr;
14697
14698 bnx2x_ilt_wr(bp, index, addr);
14699 break;
14700 }
14701
c2bff63f
DK		 14702 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14703 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 14704
14705 bnx2x_cnic_sp_post(bp, count);
14706 break;
14707 }
14708
14709 /* rtnl_lock is held. */
14710 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 14711 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14712 unsigned long sp_bits = 0;
14713
14714 /* Configure the iSCSI classification object */
14715 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14716 cp->iscsi_l2_client_id,
14717 cp->iscsi_l2_cid, BP_FUNC(bp),
14718 bnx2x_sp(bp, mac_rdata),
14719 bnx2x_sp_mapping(bp, mac_rdata),
14720 BNX2X_FILTER_MAC_PENDING,
14721 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14722 &bp->macs_pool);
ec6ba945 14723
523224a3 14724 /* Set iSCSI MAC address */
619c5cb6
VZ		 14725 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14726 if (rc)
14727 break;
523224a3
DK		 14728
14729 mmiowb();
14730 barrier();
14731
619c5cb6
VZ		 14732 /* Start accepting on iSCSI L2 ring */
14733
14734 netif_addr_lock_bh(dev);
14735 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14736 netif_addr_unlock_bh(dev);
14737
14738 /* bits to wait on */
14739 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14740 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14741
14742 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14743 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 14744
993ac7b5
MC		 14745 break;
14746 }
14747
14748 /* rtnl_lock is held. */
14749 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 14750 unsigned long sp_bits = 0;
993ac7b5 14751
523224a3 14752 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 14753 netif_addr_lock_bh(dev);
14754 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14755 netif_addr_unlock_bh(dev);
14756
14757 /* bits to wait on */
14758 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14759 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14760
14761 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14762 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 14763
14764 mmiowb();
14765 barrier();
14766
14767 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 14768 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14769 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 14770 break;
14771 }
c2bff63f
DK		 14772 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14773 int count = ctl->data.credit.credit_count;
14774
4e857c58 14775 smp_mb__before_atomic();
6e30dd4e 14776 atomic_add(count, &bp->cq_spq_left);
4e857c58 14777 smp_mb__after_atomic();
c2bff63f
DK		 14778 break;
14779 }
1d187b34 14780 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 14781 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 14782
14783 if (CHIP_IS_E3(bp)) {
14784 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 14785 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14786 int path = BP_PATH(bp);
14787 int port = BP_PORT(bp);
14788 int i;
14789 u32 scratch_offset;
14790 u32 *host_addr;
1d187b34 14791
2e499d3c 14792 /* first write capability to shmem2 */
1d187b34
BW		 14793 if (ulp_type == CNIC_ULP_ISCSI)
14794 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14795 else if (ulp_type == CNIC_ULP_FCOE)
14796 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14797 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 14798
14799 if ((ulp_type != CNIC_ULP_FCOE) ||
14800 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14801 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14802 break;
14803
14804 /* if reached here - should write fcoe capabilities */
14805 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14806 if (!scratch_offset)
14807 break;
14808 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14809 fcoe_features[path][port]);
14810 host_addr = (u32 *) &(ctl->data.register_data.
14811 fcoe_features);
14812 for (i = 0; i < sizeof(struct fcoe_capabilities);
14813 i += 4)
14814 REG_WR(bp, scratch_offset + i,
14815 *(host_addr + i/4));
1d187b34 14816 }
42f8277f 14817 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14818 break;
14819 }
2e499d3c 14820
1d187b34
BW		 14821 case DRV_CTL_ULP_UNREGISTER_CMD: {
14822 int ulp_type = ctl->data.ulp_type;
14823
14824 if (CHIP_IS_E3(bp)) {
14825 int idx = BP_FW_MB_IDX(bp);
14826 u32 cap;
14827
14828 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14829 if (ulp_type == CNIC_ULP_ISCSI)
14830 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14831 else if (ulp_type == CNIC_ULP_FCOE)
14832 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14833 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14834 }
42f8277f 14835 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14836 break;
14837 }
993ac7b5
MC		 14838
14839 default:
14840 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14841 rc = -EINVAL;
14842 }
14843
97ac4ef7
YM		 14844 /* For storage-only interfaces, change driver state */
14845 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14846 switch (ctl->drv_state) {
14847 case DRV_NOP:
14848 break;
14849 case DRV_ACTIVE:
14850 bnx2x_set_os_driver_state(bp,
14851 OS_DRIVER_STATE_ACTIVE);
14852 break;
14853 case DRV_INACTIVE:
14854 bnx2x_set_os_driver_state(bp,
14855 OS_DRIVER_STATE_DISABLED);
14856 break;
14857 case DRV_UNLOADED:
14858 bnx2x_set_os_driver_state(bp,
14859 OS_DRIVER_STATE_NOT_LOADED);
14860 break;
14861 default:
14862 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14863 }
14864 }
14865
14866 return rc;
14867}
14868
14869static int bnx2x_get_fc_npiv(struct net_device *dev,
14870 struct cnic_fc_npiv_tbl *cnic_tbl)
14871{
14872 struct bnx2x *bp = netdev_priv(dev);
14873 struct bdn_fc_npiv_tbl *tbl = NULL;
14874 u32 offset, entries;
14875 int rc = -EINVAL;
14876 int i;
14877
14878 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14879 goto out;
14880
14881 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14882
14883 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14884 if (!tbl) {
14885 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14886 goto out;
14887 }
14888
14889 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
1e6bb1a3
YM		 14890 if (!offset) {
14891 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n");
14892 goto out;
14893 }
97ac4ef7
YM		 14894 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14895
14896 /* Read the table contents from nvram */
14897 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14898 BNX2X_ERR("Failed to read FC-NPIV table\n");
14899 goto out;
14900 }
14901
14902 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14903 * the number of entries back to cpu endianness.
14904 */
14905 entries = tbl->fc_npiv_cfg.num_of_npiv;
14906 entries = (__force u32)be32_to_cpu((__force __be32)entries);
14907 tbl->fc_npiv_cfg.num_of_npiv = entries;
14908
14909 if (!tbl->fc_npiv_cfg.num_of_npiv) {
14910 DP(BNX2X_MSG_MCP,
14911 "No FC-NPIV table [valid, simply not present]\n");
14912 goto out;
14913 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14914 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14915 tbl->fc_npiv_cfg.num_of_npiv);
14916 goto out;
14917 } else {
14918 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14919 tbl->fc_npiv_cfg.num_of_npiv);
14920 }
14921
14922 /* Copy the data into cnic-provided struct */
14923 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14924 for (i = 0; i < cnic_tbl->count; i++) {
14925 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14926 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14927 }
14928
14929 rc = 0;
14930out:
14931 kfree(tbl);
993ac7b5
MC		 14932 return rc;
14933}
14934
9f6c9258 14935void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 14936{
14937 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14938
14939 if (bp->flags & USING_MSIX_FLAG) {
14940 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14941 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14942 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14943 } else {
14944 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14945 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14946 }
619c5cb6 14947 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 14948 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14949 else
14950 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14951
619c5cb6
VZ		 14952 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14953 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 14954 cp->irq_arr[1].status_blk = bp->def_status_blk;
14955 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 14956 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 14957
14958 cp->num_irq = 2;
14959}
14960
37ae41a9
MS		 14961void bnx2x_setup_cnic_info(struct bnx2x *bp)
14962{
14963 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14964
37ae41a9
MS		 14965 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14966 bnx2x_cid_ilt_lines(bp);
14967 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14968 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14969 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14970
f78afb35
MC		 14971 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14972 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14973 cp->iscsi_l2_cid);
14974
37ae41a9
MS		 14975 if (NO_ISCSI_OOO(bp))
14976 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14977}
14978
993ac7b5
MC		 14979static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14980 void *data)
14981{
14982 struct bnx2x *bp = netdev_priv(dev);
14983 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 14984 int rc;
14985
14986 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 14987
51c1a580
MS		 14988 if (ops == NULL) {
14989 BNX2X_ERR("NULL ops received\n");
993ac7b5 14990 return -EINVAL;
51c1a580 14991 }
993ac7b5 14992
55c11941
MS		 14993 if (!CNIC_SUPPORT(bp)) {
14994 BNX2X_ERR("Can't register CNIC when not supported\n");
14995 return -EOPNOTSUPP;
14996 }
14997
14998 if (!CNIC_LOADED(bp)) {
14999 rc = bnx2x_load_cnic(bp);
15000 if (rc) {
15001 BNX2X_ERR("CNIC-related load failed\n");
15002 return rc;
15003 }
55c11941
MS		 15004 }
15005
15006 bp->cnic_enabled = true;
15007
993ac7b5
MC		 15008 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
15009 if (!bp->cnic_kwq)
15010 return -ENOMEM;
15011
15012 bp->cnic_kwq_cons = bp->cnic_kwq;
15013 bp->cnic_kwq_prod = bp->cnic_kwq;
15014 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
15015
15016 bp->cnic_spq_pending = 0;
15017 bp->cnic_kwq_pending = 0;
15018
15019 bp->cnic_data = data;
15020
15021 cp->num_irq = 0;
619c5cb6 15022 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 15023 cp->iro_arr = bp->iro_arr;
993ac7b5 15024
993ac7b5 15025 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 15026
993ac7b5
MC		 15027 rcu_assign_pointer(bp->cnic_ops, ops);
15028
42f8277f
YM		 15029 /* Schedule driver to read CNIC driver versions */
15030 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
15031
993ac7b5
MC		 15032 return 0;
15033}
15034
15035static int bnx2x_unregister_cnic(struct net_device *dev)
15036{
15037 struct bnx2x *bp = netdev_priv(dev);
15038 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15039
15040 mutex_lock(&bp->cnic_mutex);
993ac7b5 15041 cp->drv_state = 0;
2cfa5a04 15042 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 15043 mutex_unlock(&bp->cnic_mutex);
15044 synchronize_rcu();
fea75645 15045 bp->cnic_enabled = false;
993ac7b5
MC		 15046 kfree(bp->cnic_kwq);
15047 bp->cnic_kwq = NULL;
15048
15049 return 0;
15050}
15051
a8f47eb7 15052static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 15053{
15054 struct bnx2x *bp = netdev_priv(dev);
15055 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15056
2ba45142
VZ		 15057 /* If both iSCSI and FCoE are disabled - return NULL in
15058 * order to indicate CNIC that it should not try to work
15059 * with this device.
15060 */
15061 if (NO_ISCSI(bp) && NO_FCOE(bp))
15062 return NULL;
15063
993ac7b5
MC		 15064 cp->drv_owner = THIS_MODULE;
15065 cp->chip_id = CHIP_ID(bp);
15066 cp->pdev = bp->pdev;
15067 cp->io_base = bp->regview;
15068 cp->io_base2 = bp->doorbells;
15069 cp->max_kwqe_pending = 8;
523224a3 15070 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 15071 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15072 bnx2x_cid_ilt_lines(bp);
993ac7b5 15073 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 15074 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 15075 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15076 cp->drv_ctl = bnx2x_drv_ctl;
97ac4ef7 15077 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
993ac7b5
MC		 15078 cp->drv_register_cnic = bnx2x_register_cnic;
15079 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 15080 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 15081 cp->iscsi_l2_client_id =
15082 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 15083 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 15084
2ba45142
VZ		 15085 if (NO_ISCSI_OOO(bp))
15086 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15087
15088 if (NO_ISCSI(bp))
15089 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15090
15091 if (NO_FCOE(bp))
15092 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15093
51c1a580
MS		 15094 BNX2X_DEV_INFO(
15095 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 15096 cp->ctx_blk_size,
15097 cp->ctx_tbl_offset,
15098 cp->ctx_tbl_len,
15099 cp->starting_cid);
993ac7b5
MC		 15100 return cp;
15101}
993ac7b5 15102
a8f47eb7 15103static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 15104{
6411280a
AE		 15105 struct bnx2x *bp = fp->bp;
15106 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 15107
6411280a
AE		 15108 if (IS_VF(bp))
15109 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15110 else if (!CHIP_IS_E1x(bp))
15111 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15112 else
15113 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 15114
6411280a 15115 return offset;
8d9ac297 15116}
381ac16b 15117
6411280a
AE		 15118/* called only on E1H or E2.
15119 * When pretending to be PF, the pretend value is the function number 0...7
15120 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15121 * combination
15122 */
15123int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 15124{
6411280a 15125 u32 pretend_reg;
381ac16b 15126
23826850 15127 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 15128 return -1;
381ac16b 15129
6411280a
AE		 15130 /* get my own pretend register */
15131 pretend_reg = bnx2x_get_pretend_reg(bp);
15132 REG_WR(bp, pretend_reg, pretend_func_val);
15133 REG_RD(bp, pretend_reg);
381ac16b
AE		 15134 return 0;
15135}
eeed018c
MK		 15136
15137static void bnx2x_ptp_task(struct work_struct *work)
15138{
15139 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15140 int port = BP_PORT(bp);
15141 u32 val_seq;
15142 u64 timestamp, ns;
15143 struct skb_shared_hwtstamps shhwtstamps;
15144
15145 /* Read Tx timestamp registers */
15146 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15147 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15148 if (val_seq & 0x10000) {
15149 /* There is a valid timestamp value */
15150 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15151 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15152 timestamp <<= 32;
15153 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15154 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15155 /* Reset timestamp register to allow new timestamp */
15156 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15157 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15158 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15159
15160 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15161 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15162 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15163 dev_kfree_skb_any(bp->ptp_tx_skb);
15164 bp->ptp_tx_skb = NULL;
15165
15166 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15167 timestamp, ns);
15168 } else {
15169 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15170 /* Reschedule to keep checking for a valid timestamp value */
15171 schedule_work(&bp->ptp_task);
15172 }
15173}
15174
15175void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15176{
15177 int port = BP_PORT(bp);
15178 u64 timestamp, ns;
15179
15180 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15181 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15182 timestamp <<= 32;
15183 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15184 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15185
15186 /* Reset timestamp register to allow new timestamp */
15187 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15188 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15189
15190 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15191
15192 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15193
15194 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15195 timestamp, ns);
15196}
15197
15198/* Read the PHC */
15199static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15200{
15201 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15202 int port = BP_PORT(bp);
15203 u32 wb_data[2];
15204 u64 phc_cycles;
15205
15206 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15207 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15208 phc_cycles = wb_data[1];
15209 phc_cycles = (phc_cycles << 32) + wb_data[0];
15210
15211 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15212
15213 return phc_cycles;
15214}
15215
15216static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15217{
15218 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15219 bp->cyclecounter.read = bnx2x_cyclecounter_read;
f28ba401 15220 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
eeed018c
MK		 15221 bp->cyclecounter.shift = 1;
15222 bp->cyclecounter.mult = 1;
15223}
15224
15225static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15226{
15227 struct bnx2x_func_state_params func_params = {NULL};
15228 struct bnx2x_func_set_timesync_params *set_timesync_params =
15229 &func_params.params.set_timesync;
15230
15231 /* Prepare parameters for function state transitions */
15232 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15233 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15234
15235 func_params.f_obj = &bp->func_obj;
15236 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15237
15238 /* Function parameters */
15239 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15240 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15241
15242 return bnx2x_func_state_change(bp, &func_params);
15243}
15244
1444c301 15245static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
eeed018c
MK		 15246{
15247 struct bnx2x_queue_state_params q_params;
15248 int rc, i;
15249
15250 /* send queue update ramrod to enable PTP packets */
15251 memset(&q_params, 0, sizeof(q_params));
15252 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15253 q_params.cmd = BNX2X_Q_CMD_UPDATE;
15254 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15255 &q_params.params.update.update_flags);
15256 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15257 &q_params.params.update.update_flags);
15258
15259 /* send the ramrod on all the queues of the PF */
15260 for_each_eth_queue(bp, i) {
15261 struct bnx2x_fastpath *fp = &bp->fp[i];
15262
15263 /* Set the appropriate Queue object */
15264 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15265
15266 /* Update the Queue state */
15267 rc = bnx2x_queue_state_change(bp, &q_params);
15268 if (rc) {
15269 BNX2X_ERR("Failed to enable PTP packets\n");
15270 return rc;
15271 }
15272 }
15273
15274 return 0;
15275}
15276
15277int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15278{
15279 int port = BP_PORT(bp);
15280 int rc;
15281
15282 if (!bp->hwtstamp_ioctl_called)
15283 return 0;
15284
15285 switch (bp->tx_type) {
15286 case HWTSTAMP_TX_ON:
15287 bp->flags |= TX_TIMESTAMPING_EN;
15288 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15289 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15290 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15291 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15292 break;
15293 case HWTSTAMP_TX_ONESTEP_SYNC:
15294 BNX2X_ERR("One-step timestamping is not supported\n");
15295 return -ERANGE;
15296 }
15297
15298 switch (bp->rx_filter) {
15299 case HWTSTAMP_FILTER_NONE:
15300 break;
15301 case HWTSTAMP_FILTER_ALL:
15302 case HWTSTAMP_FILTER_SOME:
15303 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15304 break;
15305 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15306 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15307 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15308 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15309 /* Initialize PTP detection for UDP/IPv4 events */
15310 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15311 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15312 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15313 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15314 break;
15315 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15316 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15317 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15318 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15319 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15320 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15321 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15322 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15323 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15324 break;
15325 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15326 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15327 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15328 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15329 /* Initialize PTP detection L2 events */
15330 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15331 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15332 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15333 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15334
15335 break;
15336 case HWTSTAMP_FILTER_PTP_V2_EVENT:
15337 case HWTSTAMP_FILTER_PTP_V2_SYNC:
15338 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15339 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15340 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15341 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15342 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15343 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15344 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15345 break;
15346 }
15347
15348 /* Indicate to FW that this PF expects recorded PTP packets */
15349 rc = bnx2x_enable_ptp_packets(bp);
15350 if (rc)
15351 return rc;
15352
15353 /* Enable sending PTP packets to host */
15354 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15355 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15356
15357 return 0;
15358}
15359
15360static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15361{
15362 struct hwtstamp_config config;
15363 int rc;
15364
15365 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15366
15367 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15368 return -EFAULT;
15369
15370 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15371 config.tx_type, config.rx_filter);
15372
15373 if (config.flags) {
15374 BNX2X_ERR("config.flags is reserved for future use\n");
15375 return -EINVAL;
15376 }
15377
15378 bp->hwtstamp_ioctl_called = 1;
15379 bp->tx_type = config.tx_type;
15380 bp->rx_filter = config.rx_filter;
15381
15382 rc = bnx2x_configure_ptp_filters(bp);
15383 if (rc)
15384 return rc;
15385
15386 config.rx_filter = bp->rx_filter;
15387
15388 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15389 -EFAULT : 0;
15390}
15391
bf27c353 15392/* Configures HW for PTP */
eeed018c
MK		 15393static int bnx2x_configure_ptp(struct bnx2x *bp)
15394{
15395 int rc, port = BP_PORT(bp);
15396 u32 wb_data[2];
15397
15398 /* Reset PTP event detection rules - will be configured in the IOCTL */
15399 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15400 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15401 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15402 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15403 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15404 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15405 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15406 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15407
15408 /* Disable PTP packets to host - will be configured in the IOCTL*/
15409 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15410 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15411
15412 /* Enable the PTP feature */
15413 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15414 NIG_REG_P0_PTP_EN, 0x3F);
15415
15416 /* Enable the free-running counter */
15417 wb_data[0] = 0;
15418 wb_data[1] = 0;
15419 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15420
15421 /* Reset drift register (offset register is not reset) */
15422 rc = bnx2x_send_reset_timesync_ramrod(bp);
15423 if (rc) {
15424 BNX2X_ERR("Failed to reset PHC drift register\n");
15425 return -EFAULT;
15426 }
15427
15428 /* Reset possibly old timestamps */
15429 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15430 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15431 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15432 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15433
15434 return 0;
15435}
15436
15437/* Called during load, to initialize PTP-related stuff */
15438void bnx2x_init_ptp(struct bnx2x *bp)
15439{
15440 int rc;
15441
15442 /* Configure PTP in HW */
15443 rc = bnx2x_configure_ptp(bp);
15444 if (rc) {
15445 BNX2X_ERR("Stopping PTP initialization\n");
15446 return;
15447 }
15448
15449 /* Init work queue for Tx timestamping */
15450 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15451
15452 /* Init cyclecounter and timecounter. This is done only in the first
15453 * load. If done in every load, PTP application will fail when doing
15454 * unload / load (e.g. MTU change) while it is running.
15455 */
15456 if (!bp->timecounter_init_done) {
15457 bnx2x_init_cyclecounter(bp);
15458 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15459 ktime_to_ns(ktime_get_real()));
15460 bp->timecounter_init_done = 1;
15461 }
15462
15463 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15464}
Linux kernel - Deliverables
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